content stringlengths 1 1.04M ⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
---------------------------------------------------------------------------------
-- Title : ARP Packet TX
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : ArpPacketTx.vhd
-- Author : Kurtis Nishimura
------------... |
-- VHDL da logica do jogo da velha
library ieee;
use ieee.std_logic_1164.all;
entity logica_jogo is
port(
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
fim_recepcao : in std_logic;
jogador_atual : in std_logic;
entrada_dado : in std_l... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
entity step3_env is
end entity step3_env;
library STD;
use STD.textio.all;
library WORK;
use WORK.pkg_readline.all;
use WORK.types.all;
use WORK.printer.all;
use WORK.reader.all;
use WORK.env.all;
architecture test of step3_env is
procedure mal_READ(str: in string; ast: out mal_val_ptr; err: out mal_val_ptr) is
b... |
library IEEE;
use IEEE.std_logic_1164.ALL;
entity functions is
generic (
CORE : string(2 downto 1);
ADDR_LIMIT : integer
);
port (
addr : in integer
);
end entity functions;
architecture behav_functions of functions is
begin
process( addr )
begin
if addr <= ADDR_LIMIT the... |
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--entity MD5 is
-- Port( Clk : in std_logic;
-- Reset : in std_logic;
-- Run : in std_logic;
-- FirstRun : in std_logic;
-- w0, w1, w2, w3, w4, w5, w6, w7, w8, w... |
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--entity MD5 is
-- Port( Clk : in std_logic;
-- Reset : in std_logic;
-- Run : in std_logic;
-- FirstRun : in std_logic;
-- w0, w1, w2, w3, w4, w5, w6, w7, w8, w... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
-------------------------------------------------------------------------------
-- AXI_GPIO - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ***************************************************************************
-- DISCLAIMER OF LIABILITY
--
-- This ... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_143 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
gt : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_143 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
gt : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity sub_143 is
port (
output : out std_logic_vector(63 downto 0);
lt : out std_logic;
le : out std_logic;
sign : in std_logic;
gt : out std_logic;
in_a : in std_logic_vector(63 downto 0);
in_b : in std_logic_vector... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEHYJMBQS is
port(
input : in std_logic_vector(24 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEHYJMBQS is
port(
input : in std_logic_vector(24 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEHYJMBQS is
port(
input : in std_logic_vector(24 downto 0);
output : out std_log... |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_port_GNEHYJMBQS is
port(
input : in std_logic_vector(24 downto 0);
output : out std_log... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity projeto1 is
port (
e : in std_logic_vector (1 downto 0) := "00";
c : in std_logic := '0';
s : out std_logic
);
end projeto1;
architecture Behavioral of projeto1 is
signal multiplex : std_logic;
begin
process (multiplex, e, c)
begin
if(e = "00") then
mu... |
--------------------------------------------------------------------------------
--
-- DIST MEM GEN Core - Address Generator
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--=============================================================================
-- This file is part of FPGA_NEURAL-Network.
--
-- FPGA_NEURAL-Network is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Founda... |
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and prop... |
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
termi... |
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.rv_components.all;
entity a4l_master is
generic (
ADDRESS_WIDTH : positive;
DATA_WIDTH : positive;
MAX_OUTSTANDING_REQUESTS : natural
);
port (
clk : in std_logic;
reset ... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
... |
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00229
--
-- AUTHOR:
--
-- A. Wilm... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:29:02 07/09/2014
-- Design Name:
-- Module Name: expansion_ram_dp - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-... |
-- megafunction wizard: %LPM_DIVIDE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_divide
-- ============================================================
-- File Name: lpm_divide0.vhd
-- Megafunction Name(s):
-- lpm_divide
-- ============================================================
-- **************... |
-- revision history:
-- 05.08.2015 Bahri Enis Demirtel created
library IEEE;
use IEEE.std_logic_1164.ALL;
library IEEE;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity tb_write_back is
end entity tb_write_back;
architecture behav_tb_write_back of tb_write_back is
-- -------- SIMULATION CONSTANTS -----... |
-- This is utf-8 encoding, with a BOM.
package p1 is
end p1;
|
-- This is utf-8 encoding, with a BOM.
package p1 is
end p1;
|
-- This is utf-8 encoding, with a BOM.
package p1 is
end p1;
|
library verilog;
use verilog.vl_types.all;
entity light_vlg_vec_tst is
end light_vlg_vec_tst;
|
-- GAISLER_LICENSE
-----------------------------------------------------------------------------
-- Entity: dma
-- File: dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple DMA (needs the AHB master interface)
--------------------------------------------------------------------... |
-- GAISLER_LICENSE
-----------------------------------------------------------------------------
-- Entity: dma
-- File: dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple DMA (needs the AHB master interface)
--------------------------------------------------------------------... |
-- GAISLER_LICENSE
-----------------------------------------------------------------------------
-- Entity: dma
-- File: dma.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simple DMA (needs the AHB master interface)
--------------------------------------------------------------------... |
-------------------------------------------------------------------------------
--
-- SID 6581
--
-- A fully functional SID chip implementation in VHDL
--
-------------------------------------------------------------------------------
-- to do: - filter
-- - smaller implementation... |
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 01:28:25 03/22/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: disp_controller - Behavioral
-- Target Devices: Spartan-3E Starter Kit
--... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 26.01.2017 10:52:07
-- Design Name:
-- Module Name: CellArray - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-... |
entity tb_bnot is
end tb_bnot;
architecture behav of tb_bnot is
signal i : bit;
signal o : bit;
begin
dut: entity work.bnot
port map (i, o);
process
begin
i <= '0';
wait for 1 ns;
assert o = '1' severity failure;
i <= '1';
wait for 1 ns;
assert o = '0' severity failure;
wai... |
entity top3 is
generic (
ok : boolean := false
);
port (
clk : in bit;
inp : in bit;
outp : out bit);
end;
architecture beh of top3 is
begin
assert ok report "my assert message, value:" & bit'image(inp);
outp <= inp;
end beh;
|
-----------------------------------------------------------------------------------------
--
-- File Name: MT46V16M16.VHD
-- Version: 2.1
-- Date: January 14th, 2002
-- Model: Behavioral
-- Simulator: NCDesktop - http://www.cadence.com
-- ModelSim PE - http://www.mo... |
-------------------------------------------------------------------------------
-- system_microblaze_0_dlmb_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library lmb_v10_v2_00_b;
use lm... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
component <name> is
port(
);
end component;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
use std.textio.all;
use ieee.std_logic_misc.all;
package TB_Package is
function Header_gen(Packet_length, source, destination, packet_id: integ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity top_level is
port(
-- FX2LP interface ---------------------------------------------------------------------------
fx2Clk_in : in std_logic; -- 48MHz clock from FX2LP
fx2Addr_out : out std_logic_vector(1 down... |
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_key_permutation_1 is
end test_key_permutation_1;
architecture behavior of test_key_permutation_1 is
--component declaration of the unit under test
signal data_in: std_logic_vector(0 to 63);
signal permuted_left_half: std_logic_vector(0 to 27);
... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: LPM_COUNTER
-- ============================================================
-- File Name: lpm_counter3.vhd
-- Megafunction Name(s):
-- LPM_COUNTER
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Thu Oct 26 22:45:43 2017
-- Host : Juice-Laptop running 64-bit major re... |
-- virtual_jtag.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity virtual_jtag is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; ... |
-- virtual_jtag.vhd
-- Generated using ACDS version 15.1 185
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity virtual_jtag is
port (
tdi : out std_logic; -- jtag.tdi
tdo : in std_logic := '0'; ... |
entity E1 is
end entity;
architecture behav of E1 is
-- array with unconstrained array element type
type A is array(natural range <>) of bit_vector;
begin
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library WORK;
use WORK.CONSTANTS.ALL;
use WORK.FUNCTIONS.ALL;
entity Iterator is
Port ( go : in STD_LOGIC;
clock : in STD_LOGIC;
reset : in STD_LOGIC;
x0 : in STD_LOGIC_VECTOR (XY_RANGE-1 downto 0);
y... |
----------------------------------------------------------------------------------
-- Company: Ratner Engineering
-- Engineer: bryan mealy
--
-- Create Date: 15:27:40 04/27/2007
-- Design Name:
-- Module Name: CLK_DIV_FS
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: This divides the ... |
entity libparen is
end libparen;
architecture behav of libparen is
constant c : boolean := work(5);
begin
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Config.all;
-- used as Next State Register and as Output Pattern Register
entity ConfigRegister is
generic (
Width : integer range 1 to 65536
);
port (
Reset_n_i : in std_logic;
Output_o : out std_logic_vector(Width-1 downto 0)... |
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.Config.all;
-- used as Next State Register and as Output Pattern Register
entity ConfigRegister is
generic (
Width : integer range 1 to 65536
);
port (
Reset_n_i : in std_logic;
Output_o : out std_logic_vector(Width-1 downto 0)... |
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 06:23:47 2019
-- Host : varun-laptop running 64-bit Serv... |
-- The MIT License (MIT)
-- Copyright (c) 2014 Shuo Li
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, c... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- ... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- ... |
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- --
-- This is the TOP-Level for TG68_fast to generate 68K Bus signals --
-- ... |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistr... |
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