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-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
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-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
Use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
Use axi_datamover_v5_1_9.axi_datamover_stbs_set;
Use axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_indet_btt.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_indet_btt.vhd
--
-- Description:
-- This file implements the DataMover S2MM Indeterminate BTT support module.
-- This Module keeps track of the incoming data stream and generates a transfer
-- descriptor for each AXI MMap Burst worth of data loaded in the Data FIFO.
-- This information is stored in a separate FIFO that the Predictive Transfer
-- Calculator fetches sequentially as it is generating commands for the AXI MMap
-- bus.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_pkg_v1_0_2;
Use lib_pkg_v1_0_2.lib_pkg.clog2;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_sfifo_autord;
use axi_datamover_v5_1_9.axi_datamover_skid_buf;
Use axi_datamover_v5_1_9.axi_datamover_stbs_set;
Use axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre;
-------------------------------------------------------------------------------
entity axi_datamover_indet_btt is
generic (
C_SF_FIFO_DEPTH : integer range 128 to 8192 := 128;
-- Sets the depth of the Data FIFO
C_IBTT_XFER_BYTES_WIDTH : Integer range 1 to 14 := 8;
-- Sets the width of the sf2pcc_xfer_bytes port
C_STRT_OFFSET_WIDTH : Integer range 1 to 7 := 2;
-- Sets the bit width of the starting address offset port
-- This should be set to log2(C_MMAP_DWIDTH/C_STREAM_DWIDTH)
C_MAX_BURST_LEN : Integer range 2 to 256 := 16;
-- Indicates what is set as the allowed max burst length for AXI4
-- transfers
C_MMAP_DWIDTH : Integer range 32 to 1024 := 32;
-- Indicates the width of the AXI4 MMap data path
C_STREAM_DWIDTH : Integer range 8 to 1024 := 32;
-- Indicates the width of the stream data path
C_ENABLE_SKID_BUF : string := "11111";
C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1;
C_ENABLE_DRE : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA Family
);
port (
-- Clock input --------------------------------------------
primary_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- Reset input --
mmap_reset : in std_logic; --
-- Reset used for the internal master logic --
-----------------------------------------------------------
-- Write Data Controller I/O ----------------------------------------------------------
--
ibtt2wdc_stbs_asserted : Out std_logic_vector(7 downto 0); --
-- Indicates the number of asserted WSTRB bits for the --
-- associated output stream data beat --
--
ibtt2wdc_eop : Out std_logic; --
-- Write End of Packet flag output to Write Data Controller --
--
ibtt2wdc_tdata : Out std_logic_vector(C_MMAP_DWIDTH-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tstrb : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); --
-- Write DATA output to Write Data Controller --
--
ibtt2wdc_tlast : Out std_logic; --
-- Write LAST output to Write Data Controller --
--
ibtt2wdc_tvalid : Out std_logic; --
-- Write VALID output to Write Data Controller --
--
wdc2ibtt_tready : In std_logic; --
-- Write READY input from Write Data Controller --
---------------------------------------------------------------------------------------
-- DRE Stream In ----------------------------------------------------------------------
--
dre2ibtt_tvalid : In std_logic; --
-- DRE Stream VALID Output --
--
ibtt2dre_tready : Out Std_logic; --
-- DRE Stream READY input --
--
dre2ibtt_tdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0); --
-- DRE Stream DATA input --
--
dre2ibtt_tstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); --
-- DRE Stream STRB input --
--
dre2ibtt_tlast : In std_logic; --
-- DRE Xfer LAST input --
--
dre2ibtt_eop : In std_logic; --
-- DRE Stream end of Stream packet flag --
--------------------------------------------------------------------------------------
-- Starting Address Offset Input -------------------------------------------------
--
dre2ibtt_strt_addr_offset : In std_logic_vector(C_STRT_OFFSET_WIDTH-1 downto 0); --
-- Used by Packing logic to set the initial data slice position for the --
-- packing operation. Packing is only needed if the MMap and Stream Data --
-- widths do not match. This input is sampled on the first valid DRE Stream In --
-- input databeat of a packet. --
-- --
-----------------------------------------------------------------------------------
-- Store and Forward Command Calculator Interface ---------------------------------------
--
sf2pcc_xfer_valid : Out std_logic; --
-- Indicates that at least 1 xfer descriptor entry is in in the XFER_DESCR_FIFO --
--
pcc2sf_xfer_ready : in std_logic; --
-- Indicates that a full burst of data has been loaded into the data FIFO --
--
--
sf2pcc_cmd_cmplt : Out std_logic; --
-- Indicates that this is the final xfer for an associated command loaded --
-- into the Realigner by the IBTTCC interface --
--
--
sf2pcc_packet_eop : Out std_logic; --
-- Indicates the end of a Stream Packet corresponds to the pending --
-- xfer data described by this xfer descriptor --
--
sf2pcc_xfer_bytes : Out std_logic_vector(C_IBTT_XFER_BYTES_WIDTH-1 downto 0) --
-- This byte count is used by the IBTTCC for setting up the spawned child --
-- commands. The IBTTCC must use this count to generate the appropriate --
-- LEN value to put out on the AXI4 Write Addr Channel and the WSTRB on the AXI4 --
-- Write Data Channel. --
-----------------------------------------------------------------------------------------
);
end entity axi_datamover_indet_btt;
architecture implementation of axi_datamover_indet_btt is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Functions
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_cntr_width
--
-- Function Description:
-- This function calculates the needed counter bit width from the
-- number of count sates needed (input).
--
-------------------------------------------------------------------
function funct_get_cntr_width (num_cnt_values : integer) return integer is
Variable temp_cnt_width : Integer := 0;
begin
if (num_cnt_values <= 2) then
temp_cnt_width := 1;
elsif (num_cnt_values <= 4) then
temp_cnt_width := 2;
elsif (num_cnt_values <= 8) then
temp_cnt_width := 3;
elsif (num_cnt_values <= 16) then
temp_cnt_width := 4;
elsif (num_cnt_values <= 32) then
temp_cnt_width := 5;
elsif (num_cnt_values <= 64) then
temp_cnt_width := 6;
elsif (num_cnt_values <= 128) then
temp_cnt_width := 7;
else
temp_cnt_width := 8;
end if;
Return (temp_cnt_width);
end function funct_get_cntr_width;
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_rnd2pwr_of_2
--
-- Function Description:
-- Rounds the input value up to the nearest power of 2 between
-- 4 and 32. THis is used for sizing the SRL based XD FIFO.
--
-------------------------------------------------------------------
function funct_rnd2pwr_of_2 (input_value : integer) return integer is
Variable temp_pwr2 : Integer := 128;
begin
if (input_value <= 4) then
temp_pwr2 := 4;
elsif (input_value <= 8) then
temp_pwr2 := 8;
elsif (input_value <= 16) then
temp_pwr2 := 16;
else
temp_pwr2 := 32;
end if;
Return (temp_pwr2);
end function funct_rnd2pwr_of_2;
-------------------------------------------------------------------
-- Constants
Constant LOGIC_LOW : std_logic := '0';
Constant LOGIC_HIGH : std_logic := '1';
Constant BITS_PER_BYTE : integer := 8;
Constant MMAP2STRM_WIDTH_RATO : integer := C_MMAP_DWIDTH/C_STREAM_DWIDTH;
Constant STRM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant STRM_STRBS_ASSERTED_WIDTH : integer := clog2(STRM_WSTB_WIDTH)+1;
-- Constant DATA_FIFO_DFACTOR : integer := 4; -- set buffer to 4 times the Max allowed Burst Length
-- Constant DATA_FIFO_DEPTH : integer := C_MAX_BURST_LEN*DATA_FIFO_DFACTOR;
Constant DATA_FIFO_DEPTH : integer := C_SF_FIFO_DEPTH;
Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+MMAP_WSTB_WIDTH*C_ENABLE_S2MM_TKEEP+2;
-- Constant DATA_FIFO_WIDTH : integer := C_MMAP_DWIDTH+STRB_CNTR_WIDTH+2;
Constant DATA_FIFO_CNT_WIDTH : integer := clog2(DATA_FIFO_DEPTH)+1;
Constant BURST_CNTR_WIDTH : integer := clog2(C_MAX_BURST_LEN);
Constant MAX_BURST_DBEATS : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(C_MAX_BURST_LEN-1, BURST_CNTR_WIDTH);
Constant DBC_ONE : Unsigned(BURST_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BURST_CNTR_WIDTH);
Constant BYTE_CNTR_WIDTH : integer := C_IBTT_XFER_BYTES_WIDTH;
Constant BYTES_PER_MMAP_DBEAT : integer := C_MMAP_DWIDTH/BITS_PER_BYTE;
Constant BYTES_PER_STRM_DBEAT : integer := C_STREAM_DWIDTH/BITS_PER_BYTE;
--Constant MAX_BYTE_CNT : integer := C_MAX_BURST_LEN*BYTES_PER_DBEAT;
--Constant NUM_STRB_BITS : integer := BYTES_PER_DBEAT;
Constant BCNTR_ONE : Unsigned(BYTE_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, BYTE_CNTR_WIDTH);
--Constant XD_FIFO_DEPTH : integer := 16;
Constant XD_FIFO_DEPTH : integer := funct_rnd2pwr_of_2(DATA_FIFO_DEPTH/C_MAX_BURST_LEN);
Constant XD_FIFO_CNT_WIDTH : integer := clog2(XD_FIFO_DEPTH)+1;
Constant XD_FIFO_WIDTH : integer := BYTE_CNTR_WIDTH+2;
Constant MMAP_STBS_ASSERTED_WIDTH : integer := 8;
Constant SKIDBUF2WDC_DWIDTH : integer := C_MMAP_DWIDTH + MMAP_STBS_ASSERTED_WIDTH;
Constant SKIDBUF2WDC_STRB_WIDTH : integer := SKIDBUF2WDC_DWIDTH/BITS_PER_BYTE;
--Constant NUM_ZEROS_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
Constant STRB_CNTR_WIDTH : integer := MMAP_STBS_ASSERTED_WIDTH;
-- Signals
signal sig_wdc2ibtt_tready : std_logic := '0';
signal sig_ibtt2wdc_tvalid : std_logic := '0';
signal sig_ibtt2wdc_tdata : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tstrb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_tlast : std_logic := '0';
signal sig_ibtt2wdc_eop : std_logic := '0';
signal sig_push_data_fifo : std_logic := '0';
signal sig_pop_data_fifo : std_logic := '0';
signal sig_data_fifo_data_in : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_data_out : std_logic_vector(DATA_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_dvalid : std_logic := '0';
signal sig_data_fifo_full : std_logic := '0';
signal sig_data_fifo_rd_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_data_fifo_wr_cnt : std_logic_vector(DATA_FIFO_CNT_WIDTH-1 downto 0) := (others => '0');
signal sig_push_xd_fifo : std_logic := '0';
signal sig_pop_xd_fifo : std_logic := '0';
signal sig_xd_fifo_data_in : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_data_out : std_logic_vector(XD_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_xd_fifo_dvalid : std_logic := '0';
signal sig_xd_fifo_full : std_logic := '0';
signal sig_tmp : std_logic := '0';
signal sig_strm_in_ready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_good_tlast_dbeat : std_logic := '0';
signal sig_dre2ibtt_tlast_reg : std_logic := '0';
signal sig_dre2ibtt_eop_reg : std_logic := '0';
signal sig_burst_dbeat_cntr : Unsigned(BURST_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbeat_cntr : std_logic := '0';
signal sig_clr_dbc_reg : std_logic := '0';
signal sig_dbc_max : std_logic := '0';
signal sig_pcc2ibtt_xfer_ready : std_logic := '0';
signal sig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_ld_byte_cntr : std_logic := '0';
signal sig_incr_byte_cntr : std_logic := '0';
signal sig_clr_byte_cntr : std_logic := '0';
signal sig_fifo_tstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal sig_num_ls_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ls_assert_found : std_logic := '0';
signal sig_num_ms_zeros : integer range 0 to STRM_WSTB_WIDTH := 0;
signal sig_ms_assert_found : std_logic := '0';
-- signal sig_num_zeros : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
-- signal sig_num_ones : unsigned(NUM_ZEROS_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2sfcc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_stbs2wdc_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_ibtt2wdc_stbs_asserted : std_logic_vector(MMAP_STBS_ASSERTED_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tready : std_logic := '0';
signal sig_skidbuf_in_tvalid : std_logic := '0';
signal sig_skidbuf_in_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_in_tlast : std_logic := '0';
signal sig_skidbuf_in_eop : std_logic := '0';
signal sig_skidbuf_out_tready : std_logic := '0';
signal sig_skidbuf_out_tvalid : std_logic := '0';
signal sig_skidbuf_out_tdata : std_logic_vector(SKIDBUF2WDC_DWIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tstrb : std_logic_vector(SKIDBUF2WDC_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_skidbuf_out_tlast : std_logic := '0';
signal sig_skidbuf_out_eop : std_logic := '0';
signal sig_enable_dbcntr : std_logic := '0';
signal sig_good_fifo_write : std_logic := '0';
begin --(architecture implementation)
-- Write Data Controller I/O
sig_wdc2ibtt_tready <= wdc2ibtt_tready ;
ibtt2wdc_tvalid <= sig_ibtt2wdc_tvalid ;
ibtt2wdc_tdata <= sig_ibtt2wdc_tdata ;
ibtt2wdc_tstrb <= sig_ibtt2wdc_tstrb ;
ibtt2wdc_tlast <= sig_ibtt2wdc_tlast ;
ibtt2wdc_eop <= sig_ibtt2wdc_eop ;
ibtt2wdc_stbs_asserted <= sig_ibtt2wdc_stbs_asserted;
-- PCC I/O
sf2pcc_xfer_valid <= sig_xd_fifo_dvalid;
sig_pcc2ibtt_xfer_ready <= pcc2sf_xfer_ready;
sf2pcc_packet_eop <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH+1);
sf2pcc_cmd_cmplt <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH);
sf2pcc_xfer_bytes <= sig_xd_fifo_data_out(BYTE_CNTR_WIDTH-1 downto 0);
-- DRE Stream In
ibtt2dre_tready <= sig_strm_in_ready;
-- sig_strm_in_ready <= not(sig_xd_fifo_full) and
-- not(sig_data_fifo_full);
sig_good_strm_dbeat <= dre2ibtt_tvalid and
sig_strm_in_ready;
sig_good_tlast_dbeat <= sig_good_strm_dbeat and
dre2ibtt_tlast;
-- Burst Packet Counter Logic -------------------------------
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_DBC_STUFF
--
-- Process Description:
-- Just a register for data beat counter signals.
--
-------------------------------------------------------------
REG_DBC_STUFF : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dre2ibtt_tlast_reg <= '0';
sig_dre2ibtt_eop_reg <= '0';
sig_clr_dbc_reg <= '0';
else
sig_dre2ibtt_tlast_reg <= dre2ibtt_tlast;
sig_dre2ibtt_eop_reg <= dre2ibtt_eop;
sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
end if;
end if;
end process REG_DBC_STUFF;
-- sig_clr_dbc_reg <= sig_clr_dbeat_cntr;
-- Increment the dataBeat counter on a data fifo wide
-- load condition. If packer logic is enabled, this will
-- only occur when a full fifo data width has been collected
-- from the Stream input.
sig_incr_dbeat_cntr <= sig_good_strm_dbeat and
sig_enable_dbcntr;
-- Check to see if a max burst len of databeats have been
-- loaded into the FIFO
sig_dbc_max <= '1'
when (sig_burst_dbeat_cntr = MAX_BURST_DBEATS)
Else '0';
-- Start the counter over at a max burst len boundary or at
-- the end of the packet.
sig_clr_dbeat_cntr <= '1'
when (sig_dbc_max = '1' and
sig_good_strm_dbeat = '1' and
sig_enable_dbcntr = '1') or
(sig_good_tlast_dbeat = '1' and
sig_enable_dbcntr = '1')
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DBC_CMTR
--
-- Process Description:
-- The Databeat Counter keeps track of how many databeats have
-- been loaded into the Data FIFO. When a max burst worth of
-- databeats have been loaded (or a TLAST encountered), the
-- XD FIFO can be loaded with a transfer data set to be sent
-- to the IBTTCC.
--
-------------------------------------------------------------
IMP_DBC_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= (others => '0');
elsif (sig_incr_dbeat_cntr = '1') then
sig_burst_dbeat_cntr <= sig_burst_dbeat_cntr + DBC_ONE;
else
null; -- hold current value
end if;
end if;
end process IMP_DBC_CMTR;
----- Byte Counter Logic -----------------------------------------------
sig_clr_byte_cntr <= sig_clr_dbc_reg and
not(sig_good_strm_dbeat);
sig_ld_byte_cntr <= sig_clr_dbc_reg and
sig_good_strm_dbeat;
sig_incr_byte_cntr <= sig_good_strm_dbeat;
sig_byte_cntr_incr_value <= RESIZE(UNSIGNED(sig_stbs2sfcc_asserted), BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_clr_byte_cntr = '1') then
sig_byte_cntr <= (others => '0');
elsif (sig_ld_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr_incr_value;
elsif (sig_incr_byte_cntr = '1') then
sig_byte_cntr <= sig_byte_cntr + sig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
------------------------------------------------------------
-- Instance: I_IBTTCC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the IBTTCC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate SAME_WIDTH_NO_DRE;
DIFF_WIDTH_OR_DRE : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_IBTTCC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => STRM_WSTB_WIDTH
)
port map (
tstrb_in => dre2ibtt_tstrb,
num_stbs_asserted => sig_stbs2sfcc_asserted -- 8 bit wide slv
);
end generate DIFF_WIDTH_OR_DRE;
----- Xfer Descriptor FIFO Logic -----------------------------------------------
sig_push_xd_fifo <= sig_clr_dbc_reg ;
sig_pop_xd_fifo <= sig_pcc2ibtt_xfer_ready and
sig_xd_fifo_dvalid ;
sig_xd_fifo_data_in <= sig_dre2ibtt_eop_reg & -- (TLAST for the input Stream)
sig_dre2ibtt_tlast_reg & -- (TLAST for the IBTTCC command)
std_logic_vector(sig_byte_cntr); -- Number of bytes in this xfer
------------------------------------------------------------
-- Instance: I_XD_FIFO
--
-- Description:
-- Implement the Transfer Desciptor (XD) FIFO. This FIFO holds
-- the individual child command xfer descriptors used by the
-- IBTTCC to generate the commands sent to the Address Cntlr and
-- the Data Cntlr.
--
------------------------------------------------------------
I_XD_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => XD_FIFO_WIDTH ,
C_DEPTH => XD_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => XD_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 1 ,
C_USE_BLKMEM => 0 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_xd_fifo ,
SFIFO_Din => sig_xd_fifo_data_in ,
SFIFO_Rd_en => sig_pop_xd_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_xd_fifo_dvalid ,
SFIFO_Dout => sig_xd_fifo_data_out ,
SFIFO_Full => sig_xd_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => sig_tmp ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => open ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => open ,
SFIFO_Rd_ack => open
);
----------------------------------------------------------------
-- Packing Logic ------------------------------------------
----------------------------------------------------------------
------------------------------------------------------------
-- If Generate
--
-- Label: OMIT_PACKING
--
-- If Generate Description:
-- Omits any packing logic in the Store and Forward module.
-- The Stream and MMap data widths are the same.
--
------------------------------------------------------------
OMIT_PACKING : if (C_MMAP_DWIDTH = C_STREAM_DWIDTH) generate
begin
-- The data beat counter is always enabled when the packer
-- is omitted.
sig_enable_dbcntr <= '1';
sig_good_fifo_write <= sig_good_strm_dbeat;
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_data_fifo_full) and
not (sig_tmp);
GEN_S2MM_TKEEP_ENABLE5 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_ENABLE5;
GEN_S2MM_TKEEP_DISABLE5 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Concatonate the Stream inputs into the single FIFO data
-- word input value
sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
dre2ibtt_tlast & -- Tlast marker
--dre2ibtt_tstrb & -- TSTRB Value
dre2ibtt_tdata; -- data value
end generate GEN_S2MM_TKEEP_DISABLE5;
end generate OMIT_PACKING;
------------------------------------------------------------
-- If Generate
--
-- Label: INCLUDE_PACKING
--
-- If Generate Description:
-- Includes packing logic in the IBTT Store and Forward
-- module. The MMap Data bus is wider than the Stream width.
--
------------------------------------------------------------
INCLUDE_PACKING : if (C_MMAP_DWIDTH > C_STREAM_DWIDTH) generate
Constant TLAST_WIDTH : integer := 1; -- bit
Constant EOP_WIDTH : integer := 1; -- bit
Constant DATA_SLICE_WIDTH : integer := C_STREAM_DWIDTH;
Constant STRB_SLICE_WIDTH : integer := STRM_WSTB_WIDTH;
Constant FLAG_SLICE_WIDTH : integer := TLAST_WIDTH +
EOP_WIDTH;
Constant OFFSET_CNTR_WIDTH : integer := funct_get_cntr_width(MMAP2STRM_WIDTH_RATO);
Constant OFFSET_CNT_ONE : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(1, OFFSET_CNTR_WIDTH);
Constant OFFSET_CNT_MAX : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) :=
TO_UNSIGNED(MMAP2STRM_WIDTH_RATO-1, OFFSET_CNTR_WIDTH);
-- Types -----------------------------------------------------------------------------
type lsig_data_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(DATA_SLICE_WIDTH-1 downto 0);
type lsig_strb_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(STRB_SLICE_WIDTH-1 downto 0);
type lsig_flag_slice_type is array(MMAP2STRM_WIDTH_RATO-1 downto 0) of
std_logic_vector(FLAG_SLICE_WIDTH-1 downto 0);
-- local signals
signal lsig_data_slice_reg : lsig_data_slice_type;
signal lsig_strb_slice_reg : lsig_strb_slice_type;
signal lsig_flag_slice_reg : lsig_flag_slice_type;
signal lsig_reg_segment : std_logic_vector(DATA_SLICE_WIDTH-1 downto 0) := (others => '0');
signal lsig_segment_ld : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_segment_clr : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_0ffset_to_to_use : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_0ffset_cntr : unsigned(OFFSET_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_offset : std_logic := '0';
signal lsig_incr_offset : std_logic := '0';
signal lsig_offset_cntr_eq_max : std_logic := '0';
signal lsig_combined_data : std_logic_vector(C_MMAP_DWIDTH-1 downto 0) := (others => '0');
signal lsig_combined_strb : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0');
signal lsig_tlast_or : std_logic := '0';
signal lsig_eop_or : std_logic := '0';
signal lsig_partial_tlast_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_partial_eop_or : std_logic_vector(MMAP2STRM_WIDTH_RATO-1 downto 0) := (others => '0');
signal lsig_packer_full : std_logic := '0';
signal lsig_packer_empty : std_logic := '0';
signal lsig_set_packer_full : std_logic := '0';
signal lsig_good_push2fifo : std_logic := '0';
signal lsig_first_dbeat : std_logic := '0';
begin
-- Generate the stream ready
sig_strm_in_ready <= not(sig_xd_fifo_full) and
not(sig_tmp) and
(not(lsig_packer_full) or
lsig_good_push2fifo) ;
-- Enable the Data Beat counter when the packer is
-- going full
sig_enable_dbcntr <= lsig_set_packer_full;
-- Assign the flag indicating that a fifo write is going
-- to occur at the next rising clock edge.
sig_good_fifo_write <= lsig_good_push2fifo;
GEN_S2MM_TKEEP_ENABLE6 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_ENABLE6;
GEN_S2MM_TKEEP_DISABLE6 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
-- Format the composite FIFO input data word
sig_data_fifo_data_in <= lsig_eop_or & -- MS Bit
lsig_tlast_or &
--lsig_combined_strb &
lsig_combined_data ; -- LS Bits
end generate GEN_S2MM_TKEEP_DISABLE6;
-- Generate a flag indicating a write to the DataFIFO
-- is going to complete
lsig_good_push2fifo <= lsig_packer_full and
not(sig_data_fifo_full);
-- Generate the control that loads the starting address
-- offset for the next input packet
lsig_ld_offset <= lsig_first_dbeat and
sig_good_strm_dbeat;
-- Generate the control for incrementing the offset counter
lsig_incr_offset <= sig_good_strm_dbeat;
-- Generate a flag indicating the packer input register
-- array is full or has loaded the last data beat of
-- the input paket
lsig_set_packer_full <= sig_good_strm_dbeat and
(dre2ibtt_tlast or
lsig_offset_cntr_eq_max);
-- Check to see if the offset counter has reached its max
-- value
lsig_offset_cntr_eq_max <= '1'
--when (lsig_0ffset_cntr = OFFSET_CNT_MAX)
when (lsig_0ffset_to_to_use = OFFSET_CNT_MAX)
Else '0';
-- Mux between the input start offset and the offset counter
-- output to use for the packer slice load control.
lsig_0ffset_to_to_use <= UNSIGNED(dre2ibtt_strt_addr_offset)
when (lsig_first_dbeat = '1')
Else lsig_0ffset_cntr;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_LD_MARKER
--
-- Process Description:
-- Implements the flop indicating the first databeat of
-- an input data packet.
--
-------------------------------------------------------------
IMP_OFFSET_LD_MARKER : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_first_dbeat <= '1';
elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '0') then
lsig_first_dbeat <= '0';
Elsif (sig_good_strm_dbeat = '1' and
dre2ibtt_tlast = '1') Then
lsig_first_dbeat <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_LD_MARKER;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_OFFSET_CNTR
--
-- Process Description:
-- Implements the address offset counter that is used to
-- steer the data loads into the packer register slices.
-- Note that the counter has to be loaded with the starting
-- offset plus one to sync up with the data input.
-------------------------------------------------------------
IMP_OFFSET_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_0ffset_cntr <= (others => '0');
Elsif (lsig_ld_offset = '1') Then
lsig_0ffset_cntr <= UNSIGNED(dre2ibtt_strt_addr_offset) + OFFSET_CNT_ONE;
elsif (lsig_incr_offset = '1') then
lsig_0ffset_cntr <= lsig_0ffset_cntr + OFFSET_CNT_ONE;
else
null; -- Hold Current State
end if;
end if;
end process IMP_OFFSET_CNTR;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PACK_REG_FULL
--
-- Process Description:
-- Implements the Packer Register full/empty flags
--
-------------------------------------------------------------
IMP_PACK_REG_FULL : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
Elsif (lsig_set_packer_full = '1' and
lsig_packer_full = '0') Then
lsig_packer_full <= '1';
lsig_packer_empty <= '0';
elsif (lsig_set_packer_full = '0' and
lsig_good_push2fifo = '1') then
lsig_packer_full <= '0';
lsig_packer_empty <= '1';
else
null; -- Hold Current State
end if;
end if;
end process IMP_PACK_REG_FULL;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_REG_SLICES
--
-- For Generate Description:
--
-- Implements the Packng Register Slices
--
--
------------------------------------------------------------
DO_REG_SLICES : for slice_index in 0 to MMAP2STRM_WIDTH_RATO-1 generate
begin
-- generate the register load enable for each slice segment based
-- on the address offset count value
lsig_segment_ld(slice_index) <= '1'
when (sig_good_strm_dbeat = '1' and
TO_INTEGER(lsig_0ffset_to_to_use) = slice_index)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DATA_SLICE
--
-- Process Description:
-- Implement a data register slice abd Strobe register slice
-- for the packer (upsizer).
--
-------------------------------------------------------------
IMP_DATA_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_data_slice_reg(slice_index) <= dre2ibtt_tdata;
lsig_strb_slice_reg(slice_index) <= dre2ibtt_tstrb;
-- optional clear of slice reg
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_data_slice_reg(slice_index) <= (others => '0');
lsig_strb_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_DATA_SLICE;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_FLAG_SLICE
--
-- Process Description:
-- Implement a flag register slice for the packer.
--
-------------------------------------------------------------
IMP_FLAG_SLICE : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
elsif (lsig_segment_ld(slice_index) = '1') then
lsig_flag_slice_reg(slice_index) <= dre2ibtt_tlast & -- bit 1
dre2ibtt_eop; -- bit 0
elsif (lsig_segment_ld(slice_index) = '0' and
lsig_good_push2fifo = '1') then
lsig_flag_slice_reg(slice_index) <= (others => '0');
else
null; -- Hold Current State
end if;
end if;
end process IMP_FLAG_SLICE;
end generate DO_REG_SLICES;
-- Do the OR functions of the Flags -------------------------------------
lsig_tlast_or <= lsig_partial_tlast_or(MMAP2STRM_WIDTH_RATO-1) ;
lsig_eop_or <= lsig_partial_eop_or(MMAP2STRM_WIDTH_RATO-1);
lsig_partial_tlast_or(0) <= lsig_flag_slice_reg(0)(1);
lsig_partial_eop_or(0) <= lsig_flag_slice_reg(0)(0);
------------------------------------------------------------
-- For Generate
--
-- Label: DO_FLAG_OR
--
-- For Generate Description:
-- Implement the OR of the TLAST and EOP Error flags.
--
--
--
------------------------------------------------------------
DO_FLAG_OR : for slice_index in 1 to MMAP2STRM_WIDTH_RATO-1 generate
begin
lsig_partial_tlast_or(slice_index) <= lsig_partial_tlast_or(slice_index-1) or
--lsig_partial_tlast_or(slice_index);
lsig_flag_slice_reg(slice_index)(1);
lsig_partial_eop_or(slice_index) <= lsig_partial_eop_or(slice_index-1) or
--lsig_partial_eop_or(slice_index);
lsig_flag_slice_reg(slice_index)(0);
end generate DO_FLAG_OR;
------------------------------------------------------------
-- For Generate
--
-- Label: DO_DATA_COMBINER
--
-- For Generate Description:
-- Combines the Data Slice register and Strobe slice register
-- outputs into a single data and single strobe vector used for
-- input data to the Data FIFO.
--
--
------------------------------------------------------------
DO_DATA_COMBINER : for slice_index in 1 to MMAP2STRM_WIDTH_RATO generate
begin
lsig_combined_data((slice_index*DATA_SLICE_WIDTH)-1 downto
(slice_index-1)*DATA_SLICE_WIDTH) <=
lsig_data_slice_reg(slice_index-1);
lsig_combined_strb((slice_index*STRB_SLICE_WIDTH)-1 downto
(slice_index-1)*STRB_SLICE_WIDTH) <=
lsig_strb_slice_reg(slice_index-1);
end generate DO_DATA_COMBINER;
end generate INCLUDE_PACKING;
-- Data FIFO Logic ------------------------------------------
--sig_push_data_fifo <= sig_good_strm_dbeat;
sig_push_data_fifo <= sig_good_fifo_write;
sig_pop_data_fifo <= sig_skidbuf_in_tready and
sig_data_fifo_dvalid;
-- -- Concatonate the Stream inputs into the single FIFO data in value
-- sig_data_fifo_data_in <= dre2ibtt_eop & -- end of packet marker
-- dre2ibtt_tlast &
-- dre2ibtt_tstrb &
-- dre2ibtt_tdata;
------------------------------------------------------------
-- Instance: I_DATA_FIFO
--
-- Description:
-- Implements the Store and Forward data FIFO
--
------------------------------------------------------------
I_DATA_FIFO : entity axi_datamover_v5_1_9.axi_datamover_sfifo_autord
generic map (
C_DWIDTH => DATA_FIFO_WIDTH ,
C_DEPTH => DATA_FIFO_DEPTH ,
C_DATA_CNT_WIDTH => DATA_FIFO_CNT_WIDTH ,
C_NEED_ALMOST_EMPTY => 0 ,
C_NEED_ALMOST_FULL => 0 ,
C_USE_BLKMEM => 1 ,
C_FAMILY => C_FAMILY
)
port map (
-- Inputs
SFIFO_Sinit => mmap_reset ,
SFIFO_Clk => primary_aclk ,
SFIFO_Wr_en => sig_push_data_fifo ,
SFIFO_Din => sig_data_fifo_data_in ,
SFIFO_Rd_en => sig_pop_data_fifo ,
SFIFO_Clr_Rd_Data_Valid => LOGIC_LOW ,
-- Outputs
SFIFO_DValid => sig_data_fifo_dvalid ,
SFIFO_Dout => sig_data_fifo_data_out ,
SFIFO_Full => sig_data_fifo_full ,
SFIFO_Empty => open ,
SFIFO_Almost_full => open ,
SFIFO_Almost_empty => open ,
SFIFO_Rd_count => sig_data_fifo_rd_cnt ,
SFIFO_Rd_count_minus1 => open ,
SFIFO_Wr_count => sig_data_fifo_wr_cnt ,
SFIFO_Rd_ack => open
);
-------------------------------------------------------------------------
---------------- Asserted TSTRB calculation logic ---------------------
-------------------------------------------------------------------------
GEN_S2MM_TKEEP_ENABLE7 : if C_ENABLE_S2MM_TKEEP = 1 generate
begin
-- Rip the write strobe value from the FIFO output data
sig_fifo_tstrb_out <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
C_MMAP_DWIDTH);
end generate GEN_S2MM_TKEEP_ENABLE7;
GEN_S2MM_TKEEP_DISBALE7 : if C_ENABLE_S2MM_TKEEP = 0 generate
begin
sig_fifo_tstrb_out <= (others => '1');
end generate GEN_S2MM_TKEEP_DISBALE7;
------------------------------------------------------------
-- Instance: I_WDC_STBS_SET
--
-- Description:
-- Instance of the asserted strobe counter for the WDC
-- interface.
--
------------------------------------------------------------
SAME_WIDTH_NO_DRE_WDC : if (C_ENABLE_DRE = 0 and (C_STREAM_DWIDTH = C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set_nodre
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate SAME_WIDTH_NO_DRE_WDC;
DIFF_WIDTH_OR_DRE_WDC : if (C_ENABLE_DRE /= 0 or (C_STREAM_DWIDTH /= C_MMAP_DWIDTH)) generate
begin
I_WDC_STBS_SET : entity axi_datamover_v5_1_9.axi_datamover_stbs_set
generic map (
C_STROBE_WIDTH => MMAP_WSTB_WIDTH
)
port map (
tstrb_in => sig_fifo_tstrb_out,
num_stbs_asserted => sig_stbs2wdc_asserted
);
end generate DIFF_WIDTH_OR_DRE_WDC;
-------------------------------------------------------------------------
------- Isolation Skid Buffer Logic (needed for Fmax timing) -----------
-------------------------------------------------------------------------
-- Skid Buffer output assignments -----------
sig_skidbuf_out_tready <= sig_wdc2ibtt_tready;
sig_ibtt2wdc_tvalid <= sig_skidbuf_out_tvalid;
sig_ibtt2wdc_tdata <= sig_skidbuf_out_tdata(C_MMAP_DWIDTH-1 downto 0) ;
sig_ibtt2wdc_tstrb <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH-1 downto 0) ;
sig_ibtt2wdc_tlast <= sig_skidbuf_out_tlast ;
-- Rip the EOP marker from the MS bit of the skid output strobes
sig_ibtt2wdc_eop <= sig_skidbuf_out_tstrb(MMAP_WSTB_WIDTH) ;
-- Rip the upper 8 bits of the skid output data for the strobes asserted value
sig_ibtt2wdc_stbs_asserted <= sig_skidbuf_out_tdata(SKIDBUF2WDC_DWIDTH-1 downto
C_MMAP_DWIDTH);
-- Skid Buffer input assignments -----------
sig_skidbuf_in_tvalid <= sig_data_fifo_dvalid;
sig_skidbuf_in_eop <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-1);
sig_skidbuf_in_tlast <= sig_data_fifo_data_out(DATA_FIFO_WIDTH-2);
-- Steal the extra input strobe bit and use it for the EOP marker
---- sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
---- sig_data_fifo_data_out(DATA_FIFO_WIDTH-3 downto
---- C_MMAP_DWIDTH);
----
sig_skidbuf_in_tstrb <= sig_skidbuf_in_eop &
sig_fifo_tstrb_out;
-- Insert the Strobes Asserted count in the extra (MS) data byte
-- for the skid buffer
sig_skidbuf_in_tdata <= sig_stbs2wdc_asserted &
sig_data_fifo_data_out(C_MMAP_DWIDTH-1 downto 0);
ENABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '1' generate
begin
------------------------------------------------------------
-- Instance: I_INDET_BTT_SKID_BUF
--
-- Description:
-- Instance for the Store and Forward isolation Skid Buffer
-- which is required to achieve Fmax timing. Note that this
-- skid buffer is 1 byte wider than the stream data width to
-- allow for the asserted strobes count to be passed through
-- it. The EOP marker is inserted in the extra strobe slot.
--
------------------------------------------------------------
I_INDET_BTT_SKID_BUF : entity axi_datamover_v5_1_9.axi_datamover_skid_buf
generic map (
C_WDATA_WIDTH => SKIDBUF2WDC_DWIDTH
)
port map (
-- System Ports
aclk => primary_aclk ,
arst => mmap_reset ,
-- Shutdown control (assert for 1 clk pulse)
skid_stop => LOGIC_LOW ,
-- Slave Side (Stream Data Input)
s_valid => sig_skidbuf_in_tvalid ,
s_ready => sig_skidbuf_in_tready ,
s_data => sig_skidbuf_in_tdata ,
s_strb => sig_skidbuf_in_tstrb ,
s_last => sig_skidbuf_in_tlast ,
-- Master Side (Stream Data Output
m_valid => sig_skidbuf_out_tvalid ,
m_ready => sig_skidbuf_out_tready ,
m_data => sig_skidbuf_out_tdata ,
m_strb => sig_skidbuf_out_tstrb ,
m_last => sig_skidbuf_out_tlast
);
end generate ENABLE_AXIS_SKID;
DISABLE_AXIS_SKID : if C_ENABLE_SKID_BUF(2) = '0' generate
begin
sig_skidbuf_out_tvalid <= sig_skidbuf_in_tvalid;
sig_skidbuf_in_tready <= sig_skidbuf_out_tready ;
sig_skidbuf_out_tdata <= sig_skidbuf_in_tdata ;
sig_skidbuf_out_tstrb <= sig_skidbuf_in_tstrb ;
sig_skidbuf_out_tlast <= sig_skidbuf_in_tlast ;
end generate DISABLE_AXIS_SKID;
end implementation;
|
--------------------------------------------------------------------------------
-- ****
-- T80(c) core. Attempt to finish all undocumented features and provide
-- accurate timings.
-- Version 350.
-- Copyright (c) 2018 Sorgelig
-- Test passed: ZEXDOC, ZEXALL, Z80Full(*), Z80memptr
-- (*) Currently only SCF and CCF instructions aren't passed X/Y flags check as
-- correct implementation is still unclear.
--
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 300 started tidyup
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0242
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
library IEEE;
use IEEE.std_logic_1164.all;
package T80_Pack is
component T80
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 0 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic;
REG : out std_logic_vector(207 downto 0) -- IY, HL', DE', BC', IX, HL, DE, BC, PC, SP, R, I, F', A', F, A
);
end component;
component T80_Reg
port(
Clk : in std_logic;
CEN : in std_logic;
WEH : in std_logic;
WEL : in std_logic;
AddrA : in std_logic_vector(2 downto 0);
AddrB : in std_logic_vector(2 downto 0);
AddrC : in std_logic_vector(2 downto 0);
DIH : in std_logic_vector(7 downto 0);
DIL : in std_logic_vector(7 downto 0);
DOAH : out std_logic_vector(7 downto 0);
DOAL : out std_logic_vector(7 downto 0);
DOBH : out std_logic_vector(7 downto 0);
DOBL : out std_logic_vector(7 downto 0);
DOCH : out std_logic_vector(7 downto 0);
DOCL : out std_logic_vector(7 downto 0);
DOR : out std_logic_vector(127 downto 0)
);
end component;
component T80_MCode
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
IR : in std_logic_vector(7 downto 0);
ISet : in std_logic_vector(1 downto 0);
MCycle : in std_logic_vector(2 downto 0);
F : in std_logic_vector(7 downto 0);
NMICycle : in std_logic;
IntCycle : in std_logic;
XY_State : in std_logic_vector(1 downto 0);
MCycles : out std_logic_vector(2 downto 0);
TStates : out std_logic_vector(2 downto 0);
Prefix : out std_logic_vector(1 downto 0); -- None,BC,ED,DD/FD
Inc_PC : out std_logic;
Inc_WZ : out std_logic;
IncDec_16 : out std_logic_vector(3 downto 0); -- BC,DE,HL,SP 0 is inc
Read_To_Reg : out std_logic;
Read_To_Acc : out std_logic;
Set_BusA_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI/DB,A,SP(L),SP(M),0,F
Set_BusB_To : out std_logic_vector(3 downto 0); -- B,C,D,E,H,L,DI,A,SP(L),SP(M),1,F,PC(L),PC(M),0
ALU_Op : out std_logic_vector(3 downto 0);
-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
Save_ALU : out std_logic;
PreserveC : out std_logic;
Arith16 : out std_logic;
Set_Addr_To : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
IORQ : out std_logic;
Jump : out std_logic;
JumpE : out std_logic;
JumpXY : out std_logic;
Call : out std_logic;
RstP : out std_logic;
LDZ : out std_logic;
LDW : out std_logic;
LDSPHL : out std_logic;
Special_LD : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
ExchangeDH : out std_logic;
ExchangeRp : out std_logic;
ExchangeAF : out std_logic;
ExchangeRS : out std_logic;
I_DJNZ : out std_logic;
I_CPL : out std_logic;
I_CCF : out std_logic;
I_SCF : out std_logic;
I_RETN : out std_logic;
I_BT : out std_logic;
I_BC : out std_logic;
I_BTR : out std_logic;
I_RLD : out std_logic;
I_RRD : out std_logic;
I_INRC : out std_logic;
SetWZ : out std_logic_vector(1 downto 0);
SetDI : out std_logic;
SetEI : out std_logic;
IMode : out std_logic_vector(1 downto 0);
Halt : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
XYbit_undoc : out std_logic
);
end component;
component T80_ALU
generic(
Mode : integer := 0;
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
Arith16 : in std_logic;
Z16 : in std_logic;
WZ : in std_logic_vector(15 downto 0);
XY_State : in std_logic_vector(1 downto 0);
ALU_Op : in std_logic_vector(3 downto 0);
IR : in std_logic_vector(5 downto 0);
ISet : in std_logic_vector(1 downto 0);
BusA : in std_logic_vector(7 downto 0);
BusB : in std_logic_vector(7 downto 0);
F_In : in std_logic_vector(7 downto 0);
Q : out std_logic_vector(7 downto 0);
F_Out : out std_logic_vector(7 downto 0)
);
end component;
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera;
use altera.all;
entity adqout is
port(
clk : in std_logic; -- clk0
clk_oct : in std_logic; -- clk90
dq_h : in std_logic;
dq_l : in std_logic;
dq_oe : in std_logic;
dq_oct : in std_logic; -- gnd = disable
dq_pad : out std_logic -- DQ pad
);
end;
architecture rtl of adqout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dq_reg : std_logic;
signal dq_oe_reg, dq_oe_reg_n, dq_oct_reg : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dq_oe_reg : signal is true;
attribute syn_preserve of dq_oe_reg : signal is true;
attribute syn_keep of dq_oe_reg_n : signal is true;
attribute syn_preserve of dq_oe_reg_n : signal is true;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQ output register --------------------------------------------------------------
dq_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => dq_l,
datainhi => dq_h,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dq_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and oct for DQ -----------------------------------------------------
-- dq_oe_reg0 : stratixiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "stratixiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oe,
-- clk => clk,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oe_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- dq_oe_reg0 : dff
-- port map(
-- d => dq_oe,
-- clk => clk,
-- clrn => vcc,
-- prn => vcc,
-- q => dq_oe_reg
-- );
dq_oe_reg0 : process(clk)
begin if rising_edge(clk) then dq_oe_reg <= not dq_oe; end if; end process;
dq_oe_reg_n <= not dq_oe_reg;
-- dq_oct_reg0 : cycloneiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "cycloneiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oct,
-- clk => clk_oct,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oct_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- Out buffer (DQ) ------------------------------------------------------------------
dq_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dq_reg,
oe => dq_oe_reg,--_n,
--devoe => vcc,
o => dq_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera;
use altera.all;
entity adqout is
port(
clk : in std_logic; -- clk0
clk_oct : in std_logic; -- clk90
dq_h : in std_logic;
dq_l : in std_logic;
dq_oe : in std_logic;
dq_oct : in std_logic; -- gnd = disable
dq_pad : out std_logic -- DQ pad
);
end;
architecture rtl of adqout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dq_reg : std_logic;
signal dq_oe_reg, dq_oe_reg_n, dq_oct_reg : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dq_oe_reg : signal is true;
attribute syn_preserve of dq_oe_reg : signal is true;
attribute syn_keep of dq_oe_reg_n : signal is true;
attribute syn_preserve of dq_oe_reg_n : signal is true;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQ output register --------------------------------------------------------------
dq_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => dq_l,
datainhi => dq_h,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dq_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and oct for DQ -----------------------------------------------------
-- dq_oe_reg0 : stratixiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "stratixiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oe,
-- clk => clk,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oe_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- dq_oe_reg0 : dff
-- port map(
-- d => dq_oe,
-- clk => clk,
-- clrn => vcc,
-- prn => vcc,
-- q => dq_oe_reg
-- );
dq_oe_reg0 : process(clk)
begin if rising_edge(clk) then dq_oe_reg <= not dq_oe; end if; end process;
dq_oe_reg_n <= not dq_oe_reg;
-- dq_oct_reg0 : cycloneiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "cycloneiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oct,
-- clk => clk_oct,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oct_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- Out buffer (DQ) ------------------------------------------------------------------
dq_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dq_reg,
oe => dq_oe_reg,--_n,
--devoe => vcc,
o => dq_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
library cycloneiii;
use cycloneiii.all;
library altera;
use altera.all;
entity adqout is
port(
clk : in std_logic; -- clk0
clk_oct : in std_logic; -- clk90
dq_h : in std_logic;
dq_l : in std_logic;
dq_oe : in std_logic;
dq_oct : in std_logic; -- gnd = disable
dq_pad : out std_logic -- DQ pad
);
end;
architecture rtl of adqout is
component cycloneiii_ddio_out
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_out"
);
port (
datainlo : in std_logic := '0';
datainhi : in std_logic := '0';
clk : in std_logic := '0';
ena : in std_logic := '1';
areset : in std_logic := '0';
sreset : in std_logic := '0';
dataout : out std_logic;
dfflo : out std_logic;
dffhi : out std_logic-- ;
--devclrn : in std_logic := '1';
--devpor : in std_logic := '1'
);
end component;
component cycloneiii_io_obuf
generic(
bus_hold : string := "false";
open_drain_output : string := "false";
lpm_type : string := "cycloneiii_io_obuf"
);
port(
i : in std_logic := '0';
oe : in std_logic := '1';
--devoe : in std_logic := '1';
o : out std_logic;
obar : out std_logic--;
--seriesterminationcontrol : in std_logic_vector(15 downto 0) := (others => '0')
);
end component;
component cycloneiii_ddio_oe is
generic(
power_up : string := "low";
async_mode : string := "none";
sync_mode : string := "none";
lpm_type : string := "cycloneiii_ddio_oe"
);
port (
oe : IN std_logic := '1';
clk : IN std_logic := '0';
ena : IN std_logic := '1';
areset : IN std_logic := '0';
sreset : IN std_logic := '0';
dataout : OUT std_logic--;
--dfflo : OUT std_logic;
--dffhi : OUT std_logic;
--devclrn : IN std_logic := '1';
--devpor : IN std_logic := '1'
);
end component;
component DFF is
port(
d, clk, clrn, prn : in std_logic;
q : out std_logic);
end component;
signal vcc : std_logic;
signal gnd : std_logic_vector(13 downto 0);
signal dq_reg : std_logic;
signal dq_oe_reg, dq_oe_reg_n, dq_oct_reg : std_logic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of dq_oe_reg : signal is true;
attribute syn_preserve of dq_oe_reg : signal is true;
attribute syn_keep of dq_oe_reg_n : signal is true;
attribute syn_preserve of dq_oe_reg_n : signal is true;
begin
vcc <= '1'; gnd <= (others => '0');
-- DQ output register --------------------------------------------------------------
dq_reg0 : cycloneiii_ddio_out
generic map(
power_up => "high",
async_mode => "none",
sync_mode => "none",
lpm_type => "cycloneiii_ddio_out"
)
port map(
datainlo => dq_l,
datainhi => dq_h,
clk => clk,
ena => vcc,
areset => gnd(0),
sreset => gnd(0),
dataout => dq_reg--,
--dfflo => open,
--dffhi => open,
--devclrn => vcc,
--devpor => vcc
);
-- Outout enable and oct for DQ -----------------------------------------------------
-- dq_oe_reg0 : stratixiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "stratixiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oe,
-- clk => clk,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oe_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- dq_oe_reg0 : dff
-- port map(
-- d => dq_oe,
-- clk => clk,
-- clrn => vcc,
-- prn => vcc,
-- q => dq_oe_reg
-- );
dq_oe_reg0 : process(clk)
begin if rising_edge(clk) then dq_oe_reg <= not dq_oe; end if; end process;
dq_oe_reg_n <= not dq_oe_reg;
-- dq_oct_reg0 : cycloneiii_ddio_oe
-- generic map(
-- power_up => "low",
-- async_mode => "none",
-- sync_mode => "none",
-- lpm_type => "cycloneiii_ddio_oe"
-- )
-- port map(
-- oe => dq_oct,
-- clk => clk_oct,
-- ena => vcc,
-- areset => gnd(0),
-- sreset => gnd(0),
-- dataout => dq_oct_reg--,
-- --dfflo => open,
-- --dffhi => open,
-- --devclrn => vcc,
-- --devpor => vcc
-- );
-- Out buffer (DQ) ------------------------------------------------------------------
dq_buf0 : cycloneiii_io_obuf
generic map(
open_drain_output => "false",
bus_hold => "false",
lpm_type => "cycloneiii_io_obuf"
)
port map(
i => dq_reg,
oe => dq_oe_reg,--_n,
--devoe => vcc,
o => dq_pad,
obar => open
--seriesterminationcontrol => gnd,
);
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix2;
constant CFG_MEMTECH : integer := stratix2;
constant CFG_PADTECH : integer := stratix2;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix2;
constant CFG_CLKMUL : integer := (8);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- PROM/SRAM controller
constant CFG_SRCTRL : integer := 0;
constant CFG_SRCTRL_PROMWS : integer := 0;
constant CFG_SRCTRL_RAMWS : integer := 0;
constant CFG_SRCTRL_IOWS : integer := 0;
constant CFG_SRCTRL_RMW : integer := 0;
constant CFG_SRCTRL_8BIT : integer := 0;
constant CFG_SRCTRL_SRBANKS : integer := 1;
constant CFG_SRCTRL_BANKSZ : integer := 0;
constant CFG_SRCTRL_ROMASEL : integer := 0;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 1;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#FFFF#;
constant CFG_GRGPIO_WIDTH : integer := (32);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
----------------------------------------------------------------------------------
-- Company: TU Vienna
-- Engineer: Georg Blemenschitz
--
-- Create Date: 19:47:48 01/31/2010
-- Design Name: SPI
-- Module Name: SPIFrqDiv - RTL
-- Description: Frequency Divider for SPI
--
-- Revision:
-- Revision 0.01 - File Created
--
-- Associated Testbench:
-- tb_SPIFrqDiv.vhd
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity SPIFrqDiv is
Generic (
SPPRWidth : integer range 1 to 8 := 3;
SPRWidth : integer range 1 to 8 := 3);
Port (
Reset_n : in STD_LOGIC;
Clk : in STD_LOGIC;
SPPR_i : in STD_LOGIC_VECTOR(SPPRWidth-1 downto 0);
SPR_i : in STD_LOGIC_VECTOR(SPRWidth-1 downto 0);
EnFrqDivider_i : in STD_LOGIC;
NextStep_o : out STD_LOGIC);
end SPIFrqDiv;
|
package pkg is
type p1 is protected
end protected;
end package;
package body pkg is
type p1 is protected body
end protected body;
end package body;
entity e is
end entity;
use work.pkg.all;
architecture a of e is
type p2 is protected
end protected;
type p2 is protected body
end protected body;
shared variable t : p1;
shared variable s : p2;
begin
end architecture;
|
package pkg is
type p1 is protected
end protected;
end package;
package body pkg is
type p1 is protected body
end protected body;
end package body;
entity e is
end entity;
use work.pkg.all;
architecture a of e is
type p2 is protected
end protected;
type p2 is protected body
end protected body;
shared variable t : p1;
shared variable s : p2;
begin
end architecture;
|
package pkg is
type p1 is protected
end protected;
end package;
package body pkg is
type p1 is protected body
end protected body;
end package body;
entity e is
end entity;
use work.pkg.all;
architecture a of e is
type p2 is protected
end protected;
type p2 is protected body
end protected body;
shared variable t : p1;
shared variable s : p2;
begin
end architecture;
|
package pkg is
type p1 is protected
end protected;
end package;
package body pkg is
type p1 is protected body
end protected body;
end package body;
entity e is
end entity;
use work.pkg.all;
architecture a of e is
type p2 is protected
end protected;
type p2 is protected body
end protected body;
shared variable t : p1;
shared variable s : p2;
begin
end architecture;
|
package pkg is
type p1 is protected
end protected;
end package;
package body pkg is
type p1 is protected body
end protected body;
end package body;
entity e is
end entity;
use work.pkg.all;
architecture a of e is
type p2 is protected
end protected;
type p2 is protected body
end protected body;
shared variable t : p1;
shared variable s : p2;
begin
end architecture;
|
entity HelloWorld is
end;
architecture HelloWorld of HelloWorld is
begin
stimulus : PROCESS
begin
assert false report "Hello World!"
severity note;
wait;
end PROCESS stimulus;
end HelloWorld;
|
entity HelloWorld is
end;
architecture HelloWorld of HelloWorld is
begin
stimulus : PROCESS
begin
assert false report "Hello World!"
severity note;
wait;
end PROCESS stimulus;
end HelloWorld;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-17.11:31:09)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY ewf_femo_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2: IN unsigned(0 TO 3);
output1, output2, output3, output4, output5: OUT unsigned(0 TO 4));
END ewf_femo_entity;
ARCHITECTURE ewf_femo_description OF ewf_femo_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 + 2;
WHEN "00000010" =>
register3 := register2 + 4;
WHEN "00000011" =>
register4 := register3 + 6;
WHEN "00000100" =>
register4 := register1 + register4;
WHEN "00000101" =>
register5 := register4 * 8;
WHEN "00000110" =>
register5 := register3 + register5;
register6 := register4 * 10;
WHEN "00000111" =>
register3 := register3 + register5;
register4 := register4 + register5;
WHEN "00001000" =>
register6 := register1 + register6;
register3 := register3 * 12;
WHEN "00001001" =>
output1 <= register6 + register4;
register1 := register1 + register6;
WHEN "00001010" =>
register3 := register2 + register3;
register1 := register1 * 15;
WHEN "00001011" =>
register2 := register2 + register3;
WHEN "00001100" =>
register2 := register2 * 17;
WHEN "00001101" =>
register2 := register2 + 19;
register4 := register5 + register3;
WHEN "00001110" =>
output2 <= register3 + register2;
register2 := register4 + 22;
WHEN "00001111" =>
register3 := register2 * 24;
WHEN "00010000" =>
register3 := register3 + 26;
WHEN "00010001" =>
output3 <= register2 + register3;
register1 := register1 + 29;
WHEN "00010010" =>
register2 := register1 + 31;
WHEN "00010011" =>
register2 := register2 * 33;
register3 := register6 + register1;
WHEN "00010100" =>
register3 := register3 + 35;
output4 <= register1 + register2;
WHEN "00010101" =>
register1 := register3 * 38;
WHEN "00010110" =>
register1 := register1 + 40;
WHEN "00010111" =>
output5 <= register3 + register1;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END ewf_femo_description; |
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Wed Aug 17 14:15:47 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design.bd
--Design : block_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1X21ZCV is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1X21ZCV;
architecture STRUCTURE of m00_couplers_imp_1X21ZCV is
component block_design_m00_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_m00_regslice_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_regslice_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_regslice_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_regslice_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_regslice_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_regslice_WVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_regslice_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_regslice_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_regslice_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_regslice_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_regslice_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_regslice_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_regslice_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_regslice_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_regslice_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1(0) <= M_ARESETN(0);
M_AXI_araddr(5 downto 0) <= m00_regslice_to_m00_couplers_ARADDR(5 downto 0);
M_AXI_arprot(2 downto 0) <= m00_regslice_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_regslice_to_m00_couplers_ARVALID;
M_AXI_awaddr(5 downto 0) <= m00_regslice_to_m00_couplers_AWADDR(5 downto 0);
M_AXI_awprot(2 downto 0) <= m00_regslice_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_regslice_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_regslice_to_m00_couplers_BREADY;
M_AXI_rready <= m00_regslice_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_regslice_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_regslice_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_regslice_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_regslice_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_regslice_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_regslice_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_regslice_RVALID;
S_AXI_wready <= m00_couplers_to_m00_regslice_WREADY;
m00_couplers_to_m00_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_regslice_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_regslice_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_regslice_BREADY <= S_AXI_bready;
m00_couplers_to_m00_regslice_RREADY <= S_AXI_rready;
m00_couplers_to_m00_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_regslice_WVALID <= S_AXI_wvalid;
m00_regslice_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_regslice_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_regslice_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_regslice_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_regslice_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_regslice_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_regslice_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_regslice_to_m00_couplers_WREADY <= M_AXI_wready;
m00_regslice: component block_design_m00_regslice_0
port map (
aclk => M_ACLK_1,
aresetn => M_ARESETN_1(0),
m_axi_araddr(5 downto 0) => m00_regslice_to_m00_couplers_ARADDR(5 downto 0),
m_axi_arprot(2 downto 0) => m00_regslice_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready => m00_regslice_to_m00_couplers_ARREADY,
m_axi_arvalid => m00_regslice_to_m00_couplers_ARVALID,
m_axi_awaddr(5 downto 0) => m00_regslice_to_m00_couplers_AWADDR(5 downto 0),
m_axi_awprot(2 downto 0) => m00_regslice_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready => m00_regslice_to_m00_couplers_AWREADY,
m_axi_awvalid => m00_regslice_to_m00_couplers_AWVALID,
m_axi_bready => m00_regslice_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => m00_regslice_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => m00_regslice_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => m00_regslice_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready => m00_regslice_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => m00_regslice_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => m00_regslice_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => m00_regslice_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready => m00_regslice_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => m00_regslice_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => m00_regslice_to_m00_couplers_WVALID,
s_axi_araddr(5 downto 0) => m00_couplers_to_m00_regslice_ARADDR(5 downto 0),
s_axi_arprot(2 downto 0) => m00_couplers_to_m00_regslice_ARPROT(2 downto 0),
s_axi_arready => m00_couplers_to_m00_regslice_ARREADY,
s_axi_arvalid => m00_couplers_to_m00_regslice_ARVALID,
s_axi_awaddr(5 downto 0) => m00_couplers_to_m00_regslice_AWADDR(5 downto 0),
s_axi_awprot(2 downto 0) => m00_couplers_to_m00_regslice_AWPROT(2 downto 0),
s_axi_awready => m00_couplers_to_m00_regslice_AWREADY,
s_axi_awvalid => m00_couplers_to_m00_regslice_AWVALID,
s_axi_bready => m00_couplers_to_m00_regslice_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_m00_regslice_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_m00_regslice_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_m00_regslice_RDATA(31 downto 0),
s_axi_rready => m00_couplers_to_m00_regslice_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_m00_regslice_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_m00_regslice_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_m00_regslice_WDATA(31 downto 0),
s_axi_wready => m00_couplers_to_m00_regslice_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_m00_regslice_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_m00_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1UJ7QBJ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1UJ7QBJ;
architecture STRUCTURE of m01_couplers_imp_1UJ7QBJ is
component block_design_m01_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_m01_regslice_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_regslice_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_regslice_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_regslice_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_regslice_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_regslice_WVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_regslice_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_regslice_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_regslice_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_regslice_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_regslice_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_regslice_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_WVALID : STD_LOGIC;
signal NLW_m01_regslice_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_m01_regslice_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_m01_regslice_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1(0) <= M_ARESETN(0);
M_AXI_araddr(8 downto 0) <= m01_regslice_to_m01_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m01_regslice_to_m01_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m01_regslice_to_m01_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m01_regslice_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_regslice_to_m01_couplers_BREADY;
M_AXI_rready <= m01_regslice_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_regslice_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m01_regslice_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_regslice_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_regslice_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_regslice_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_regslice_RVALID;
S_AXI_wready <= m01_couplers_to_m01_regslice_WREADY;
m01_couplers_to_m01_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_regslice_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_regslice_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_regslice_BREADY <= S_AXI_bready;
m01_couplers_to_m01_regslice_RREADY <= S_AXI_rready;
m01_couplers_to_m01_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_regslice_WVALID <= S_AXI_wvalid;
m01_regslice_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_regslice_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_regslice_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_regslice_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_regslice_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_regslice_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_regslice_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_regslice_to_m01_couplers_WREADY <= M_AXI_wready;
m01_regslice: component block_design_m01_regslice_0
port map (
aclk => M_ACLK_1,
aresetn => M_ARESETN_1(0),
m_axi_araddr(8 downto 0) => m01_regslice_to_m01_couplers_ARADDR(8 downto 0),
m_axi_arprot(2 downto 0) => NLW_m01_regslice_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => m01_regslice_to_m01_couplers_ARREADY,
m_axi_arvalid => m01_regslice_to_m01_couplers_ARVALID,
m_axi_awaddr(8 downto 0) => m01_regslice_to_m01_couplers_AWADDR(8 downto 0),
m_axi_awprot(2 downto 0) => NLW_m01_regslice_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => m01_regslice_to_m01_couplers_AWREADY,
m_axi_awvalid => m01_regslice_to_m01_couplers_AWVALID,
m_axi_bready => m01_regslice_to_m01_couplers_BREADY,
m_axi_bresp(1 downto 0) => m01_regslice_to_m01_couplers_BRESP(1 downto 0),
m_axi_bvalid => m01_regslice_to_m01_couplers_BVALID,
m_axi_rdata(31 downto 0) => m01_regslice_to_m01_couplers_RDATA(31 downto 0),
m_axi_rready => m01_regslice_to_m01_couplers_RREADY,
m_axi_rresp(1 downto 0) => m01_regslice_to_m01_couplers_RRESP(1 downto 0),
m_axi_rvalid => m01_regslice_to_m01_couplers_RVALID,
m_axi_wdata(31 downto 0) => m01_regslice_to_m01_couplers_WDATA(31 downto 0),
m_axi_wready => m01_regslice_to_m01_couplers_WREADY,
m_axi_wstrb(3 downto 0) => NLW_m01_regslice_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => m01_regslice_to_m01_couplers_WVALID,
s_axi_araddr(8 downto 0) => m01_couplers_to_m01_regslice_ARADDR(8 downto 0),
s_axi_arprot(2 downto 0) => m01_couplers_to_m01_regslice_ARPROT(2 downto 0),
s_axi_arready => m01_couplers_to_m01_regslice_ARREADY,
s_axi_arvalid => m01_couplers_to_m01_regslice_ARVALID,
s_axi_awaddr(8 downto 0) => m01_couplers_to_m01_regslice_AWADDR(8 downto 0),
s_axi_awprot(2 downto 0) => m01_couplers_to_m01_regslice_AWPROT(2 downto 0),
s_axi_awready => m01_couplers_to_m01_regslice_AWREADY,
s_axi_awvalid => m01_couplers_to_m01_regslice_AWVALID,
s_axi_bready => m01_couplers_to_m01_regslice_BREADY,
s_axi_bresp(1 downto 0) => m01_couplers_to_m01_regslice_BRESP(1 downto 0),
s_axi_bvalid => m01_couplers_to_m01_regslice_BVALID,
s_axi_rdata(31 downto 0) => m01_couplers_to_m01_regslice_RDATA(31 downto 0),
s_axi_rready => m01_couplers_to_m01_regslice_RREADY,
s_axi_rresp(1 downto 0) => m01_couplers_to_m01_regslice_RRESP(1 downto 0),
s_axi_rvalid => m01_couplers_to_m01_regslice_RVALID,
s_axi_wdata(31 downto 0) => m01_couplers_to_m01_regslice_WDATA(31 downto 0),
s_axi_wready => m01_couplers_to_m01_regslice_WREADY,
s_axi_wstrb(3 downto 0) => m01_couplers_to_m01_regslice_WSTRB(3 downto 0),
s_axi_wvalid => m01_couplers_to_m01_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RQO0KS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1RQO0KS;
architecture STRUCTURE of s00_couplers_imp_1RQO0KS is
component block_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component block_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_QE4JF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_QE4JF;
architecture STRUCTURE of s00_couplers_imp_QE4JF is
component block_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_s00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_s00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_rdata(63 downto 0) <= s00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
auto_pc: component block_design_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_s00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_s00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_rdata(63 downto 0) => s00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end block_design_axi_interconnect_0_0;
architecture STRUCTURE of block_design_axi_interconnect_0_0 is
component block_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component block_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(5 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(5 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(5 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(5 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(8 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(8 downto 0);
M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
M01_AXI_awaddr(8 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(8 downto 0);
M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= ACLK;
axi_interconnect_0_ARESETN_net(0) <= ARESETN(0);
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1X21ZCV
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(5 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(5 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(5 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(5 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1UJ7QBJ
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(8 downto 0),
M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(8 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(8 downto 0),
M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1RQO0KS
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_interconnect_0_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_interconnect_0_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_interconnect_0_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
xbar: component block_design_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_1_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC
);
end block_design_axi_interconnect_1_0;
architecture STRUCTURE of block_design_axi_interconnect_1_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_1_ACLK_net : STD_LOGIC;
signal axi_interconnect_1_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_1_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_interconnect_1_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_axi_interconnect_1_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_RVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_1_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_1_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARCACHE(3 downto 0);
M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_interconnect_1_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_1_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_1_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_1_ARVALID;
M00_AXI_rready <= s00_couplers_to_axi_interconnect_1_RREADY;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_1_to_s00_couplers_ARREADY;
S00_AXI_rdata(63 downto 0) <= axi_interconnect_1_to_s00_couplers_RDATA(63 downto 0);
S00_AXI_rlast <= axi_interconnect_1_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_1_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_1_to_s00_couplers_RVALID;
axi_interconnect_1_ACLK_net <= M00_ACLK;
axi_interconnect_1_ARESETN_net(0) <= M00_ARESETN(0);
axi_interconnect_1_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_1_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_1_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_1_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_interconnect_1_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_1_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_1_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_1_to_s00_couplers_RREADY <= S00_AXI_rready;
s00_couplers_to_axi_interconnect_1_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_interconnect_1_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
s00_couplers_to_axi_interconnect_1_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_interconnect_1_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_1_RVALID <= M00_AXI_rvalid;
s00_couplers: entity work.s00_couplers_imp_QE4JF
port map (
M_ACLK => axi_interconnect_1_ACLK_net,
M_ARESETN(0) => axi_interconnect_1_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_1_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_1_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARCACHE(3 downto 0),
M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_interconnect_1_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_1_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_1_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_1_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_1_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_interconnect_1_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_axi_interconnect_1_RLAST,
M_AXI_rready => s00_couplers_to_axi_interconnect_1_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_1_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_1_RVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_1_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_1_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_1_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_interconnect_1_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_1_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_interconnect_1_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_1_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_1_to_s00_couplers_ARVALID,
S_AXI_rdata(63 downto 0) => axi_interconnect_1_to_s00_couplers_RDATA(63 downto 0),
S_AXI_rlast => axi_interconnect_1_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_1_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_1_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_1_to_s00_couplers_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_vs : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of block_design : entity is "block_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=block_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=17,numReposBlks=11,numNonXlnxBlks=1,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of block_design : entity is "block_design.hwdef";
end block_design;
architecture STRUCTURE of block_design is
component block_design_axi_dispctrl_0_0 is
port (
REF_CLK_I : in STD_LOGIC;
PXL_CLK_O : out STD_LOGIC;
PXL_CLK_5X_O : out STD_LOGIC;
LOCKED_O : out STD_LOGIC;
FSYNC_O : out STD_LOGIC;
HSYNC_O : out STD_LOGIC;
VSYNC_O : out STD_LOGIC;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR ( 4 downto 0 );
GREEN_O : out STD_LOGIC_VECTOR ( 5 downto 0 );
BLUE_O : out STD_LOGIC_VECTOR ( 4 downto 0 );
DEBUG_O : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axis_mm2s_aclk : in STD_LOGIC;
s_axis_mm2s_aresetn : in STD_LOGIC;
s_axis_mm2s_tready : out STD_LOGIC;
s_axis_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_mm2s_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_mm2s_tlast : in STD_LOGIC;
s_axis_mm2s_tvalid : in STD_LOGIC
);
end component block_design_axi_dispctrl_0_0;
component block_design_axi_vdma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axis_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
mm2s_fsync : in STD_LOGIC;
mm2s_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component block_design_axi_vdma_0_0;
component block_design_processing_system7_0_0 is
port (
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component block_design_processing_system7_0_0;
component block_design_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_0_0;
component block_design_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component block_design_xlconstant_0_0;
component block_design_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_1_0;
signal axi_dispctrl_0_BLUE_O : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_dispctrl_0_FSYNC_O : STD_LOGIC;
signal axi_dispctrl_0_GREEN_O : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_dispctrl_0_HSYNC_O : STD_LOGIC;
signal axi_dispctrl_0_PXL_CLK_O : STD_LOGIC;
signal axi_dispctrl_0_RED_O : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_dispctrl_0_VSYNC_O : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_1_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_interconnect_1_M00_AXI_RLAST : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_RVALID : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_vdma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_vdma_0_m_axis_mm2s_tkeep : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_vdma_0_mm2s_introut : STD_LOGIC;
signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_1_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_dispctrl_0_DE_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_LOCKED_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_PXL_CLK_5X_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_DEBUG_O_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_vdma_0_m_axis_mm2s_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
vga_b(4 downto 0) <= axi_dispctrl_0_BLUE_O(4 downto 0);
vga_g(5 downto 0) <= axi_dispctrl_0_GREEN_O(5 downto 0);
vga_hs <= axi_dispctrl_0_HSYNC_O;
vga_r(4 downto 0) <= axi_dispctrl_0_RED_O(4 downto 0);
vga_vs <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0: component block_design_axi_dispctrl_0_0
port map (
BLUE_O(4 downto 0) => axi_dispctrl_0_BLUE_O(4 downto 0),
DEBUG_O(31 downto 0) => NLW_axi_dispctrl_0_DEBUG_O_UNCONNECTED(31 downto 0),
DE_O => NLW_axi_dispctrl_0_DE_O_UNCONNECTED,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
GREEN_O(5 downto 0) => axi_dispctrl_0_GREEN_O(5 downto 0),
HSYNC_O => axi_dispctrl_0_HSYNC_O,
LOCKED_O => NLW_axi_dispctrl_0_LOCKED_O_UNCONNECTED,
PXL_CLK_5X_O => NLW_axi_dispctrl_0_PXL_CLK_5X_O_UNCONNECTED,
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
RED_O(4 downto 0) => axi_dispctrl_0_RED_O(4 downto 0),
REF_CLK_I => processing_system7_0_FCLK_CLK0,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(5 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(5 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s_axi_awaddr(5 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(5 downto 0),
s_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID,
s_axis_mm2s_aclk => axi_dispctrl_0_PXL_CLK_O,
s_axis_mm2s_aresetn => proc_sys_reset_1_peripheral_aresetn(0),
s_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_TLAST,
s_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_TREADY,
s_axis_mm2s_tstrb(3 downto 0) => axi_vdma_0_m_axis_mm2s_tkeep(3 downto 0),
s_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID
);
axi_interconnect_0: entity work.block_design_axi_interconnect_0_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(5 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(5 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(5 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(5 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M01_AXI_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
axi_interconnect_1: entity work.block_design_axi_interconnect_1_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_interconnect_1_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_interconnect_1_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arlen(3 downto 0) => axi_interconnect_1_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_interconnect_1_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_1_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_interconnect_1_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_interconnect_1_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_interconnect_1_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_interconnect_1_M00_AXI_ARVALID,
M00_AXI_rdata(63 downto 0) => axi_interconnect_1_M00_AXI_RDATA(63 downto 0),
M00_AXI_rlast => axi_interconnect_1_M00_AXI_RLAST,
M00_AXI_rready => axi_interconnect_1_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_1_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_1_M00_AXI_RVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_vdma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_vdma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_vdma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_vdma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready => axi_vdma_0_M_AXI_MM2S_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_vdma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(63 downto 0) => axi_vdma_0_M_AXI_MM2S_RDATA(63 downto 0),
S00_AXI_rlast => axi_vdma_0_M_AXI_MM2S_RLAST,
S00_AXI_rready => axi_vdma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_vdma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID
);
axi_vdma_0: component block_design_axi_vdma_0_0
port map (
axi_resetn => proc_sys_reset_0_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_vdma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_vdma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_vdma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_vdma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_vdma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_vdma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(63 downto 0) => axi_vdma_0_M_AXI_MM2S_RDATA(63 downto 0),
m_axi_mm2s_rlast => axi_vdma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_vdma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_vdma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID,
m_axis_mm2s_aclk => axi_dispctrl_0_PXL_CLK_O,
m_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_vdma_0_m_axis_mm2s_tkeep(3 downto 0),
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tuser(0) => NLW_axi_vdma_0_m_axis_mm2s_tuser_UNCONNECTED(0),
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID,
mm2s_frame_ptr_in(5 downto 0) => xlconstant_0_dout(5 downto 0),
mm2s_frame_ptr_out(5 downto 0) => NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED(5 downto 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_introut => axi_vdma_0_mm2s_introut,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
s_axi_lite_arready => axi_interconnect_0_M01_AXI_ARREADY,
s_axi_lite_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s_axi_lite_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
s_axi_lite_awready => axi_interconnect_0_M01_AXI_AWREADY,
s_axi_lite_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s_axi_lite_bready => axi_interconnect_0_M01_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => axi_interconnect_0_M01_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => axi_interconnect_0_M01_AXI_WREADY,
s_axi_lite_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
proc_sys_reset_0: component block_design_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
proc_sys_reset_1: component block_design_proc_sys_reset_1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_1_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => axi_dispctrl_0_PXL_CLK_O
);
processing_system7_0: component block_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => axi_vdma_0_mm2s_introut,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_interconnect_1_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_interconnect_1_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => axi_interconnect_1_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_interconnect_1_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_interconnect_1_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_interconnect_1_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_interconnect_1_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_interconnect_1_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_interconnect_1_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_interconnect_1_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => axi_interconnect_1_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_interconnect_1_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_interconnect_1_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_interconnect_1_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0'
);
xlconstant_0: component block_design_xlconstant_0_0
port map (
dout(5 downto 0) => xlconstant_0_dout(5 downto 0)
);
end STRUCTURE;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
--Date : Wed Aug 17 14:15:47 2016
--Host : andrewandrepowell2-desktop running 64-bit Ubuntu 16.04 LTS
--Command : generate_target block_design.bd
--Design : block_design
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m00_couplers_imp_1X21ZCV is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m00_couplers_imp_1X21ZCV;
architecture STRUCTURE of m00_couplers_imp_1X21ZCV is
component block_design_m00_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_m00_regslice_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m00_couplers_to_m00_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_regslice_ARREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_ARVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_m00_regslice_AWREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_AWVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_BREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_regslice_BVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_RREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_m00_regslice_RVALID : STD_LOGIC;
signal m00_couplers_to_m00_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_m00_regslice_WREADY : STD_LOGIC;
signal m00_couplers_to_m00_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_m00_regslice_WVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_regslice_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_regslice_to_m00_couplers_ARREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_ARVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_regslice_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_regslice_to_m00_couplers_AWREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_AWVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_BREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_regslice_to_m00_couplers_BVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_regslice_to_m00_couplers_RREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_regslice_to_m00_couplers_RVALID : STD_LOGIC;
signal m00_regslice_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_regslice_to_m00_couplers_WREADY : STD_LOGIC;
signal m00_regslice_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_regslice_to_m00_couplers_WVALID : STD_LOGIC;
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1(0) <= M_ARESETN(0);
M_AXI_araddr(5 downto 0) <= m00_regslice_to_m00_couplers_ARADDR(5 downto 0);
M_AXI_arprot(2 downto 0) <= m00_regslice_to_m00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= m00_regslice_to_m00_couplers_ARVALID;
M_AXI_awaddr(5 downto 0) <= m00_regslice_to_m00_couplers_AWADDR(5 downto 0);
M_AXI_awprot(2 downto 0) <= m00_regslice_to_m00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= m00_regslice_to_m00_couplers_AWVALID;
M_AXI_bready <= m00_regslice_to_m00_couplers_BREADY;
M_AXI_rready <= m00_regslice_to_m00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m00_regslice_to_m00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= m00_regslice_to_m00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= m00_regslice_to_m00_couplers_WVALID;
S_AXI_arready <= m00_couplers_to_m00_regslice_ARREADY;
S_AXI_awready <= m00_couplers_to_m00_regslice_AWREADY;
S_AXI_bresp(1 downto 0) <= m00_couplers_to_m00_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= m00_couplers_to_m00_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= m00_couplers_to_m00_regslice_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m00_couplers_to_m00_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= m00_couplers_to_m00_regslice_RVALID;
S_AXI_wready <= m00_couplers_to_m00_regslice_WREADY;
m00_couplers_to_m00_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m00_couplers_to_m00_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m00_couplers_to_m00_regslice_ARVALID <= S_AXI_arvalid;
m00_couplers_to_m00_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m00_couplers_to_m00_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m00_couplers_to_m00_regslice_AWVALID <= S_AXI_awvalid;
m00_couplers_to_m00_regslice_BREADY <= S_AXI_bready;
m00_couplers_to_m00_regslice_RREADY <= S_AXI_rready;
m00_couplers_to_m00_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m00_couplers_to_m00_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m00_couplers_to_m00_regslice_WVALID <= S_AXI_wvalid;
m00_regslice_to_m00_couplers_ARREADY <= M_AXI_arready;
m00_regslice_to_m00_couplers_AWREADY <= M_AXI_awready;
m00_regslice_to_m00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m00_regslice_to_m00_couplers_BVALID <= M_AXI_bvalid;
m00_regslice_to_m00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m00_regslice_to_m00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m00_regslice_to_m00_couplers_RVALID <= M_AXI_rvalid;
m00_regslice_to_m00_couplers_WREADY <= M_AXI_wready;
m00_regslice: component block_design_m00_regslice_0
port map (
aclk => M_ACLK_1,
aresetn => M_ARESETN_1(0),
m_axi_araddr(5 downto 0) => m00_regslice_to_m00_couplers_ARADDR(5 downto 0),
m_axi_arprot(2 downto 0) => m00_regslice_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready => m00_regslice_to_m00_couplers_ARREADY,
m_axi_arvalid => m00_regslice_to_m00_couplers_ARVALID,
m_axi_awaddr(5 downto 0) => m00_regslice_to_m00_couplers_AWADDR(5 downto 0),
m_axi_awprot(2 downto 0) => m00_regslice_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready => m00_regslice_to_m00_couplers_AWREADY,
m_axi_awvalid => m00_regslice_to_m00_couplers_AWVALID,
m_axi_bready => m00_regslice_to_m00_couplers_BREADY,
m_axi_bresp(1 downto 0) => m00_regslice_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid => m00_regslice_to_m00_couplers_BVALID,
m_axi_rdata(31 downto 0) => m00_regslice_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready => m00_regslice_to_m00_couplers_RREADY,
m_axi_rresp(1 downto 0) => m00_regslice_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid => m00_regslice_to_m00_couplers_RVALID,
m_axi_wdata(31 downto 0) => m00_regslice_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready => m00_regslice_to_m00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => m00_regslice_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => m00_regslice_to_m00_couplers_WVALID,
s_axi_araddr(5 downto 0) => m00_couplers_to_m00_regslice_ARADDR(5 downto 0),
s_axi_arprot(2 downto 0) => m00_couplers_to_m00_regslice_ARPROT(2 downto 0),
s_axi_arready => m00_couplers_to_m00_regslice_ARREADY,
s_axi_arvalid => m00_couplers_to_m00_regslice_ARVALID,
s_axi_awaddr(5 downto 0) => m00_couplers_to_m00_regslice_AWADDR(5 downto 0),
s_axi_awprot(2 downto 0) => m00_couplers_to_m00_regslice_AWPROT(2 downto 0),
s_axi_awready => m00_couplers_to_m00_regslice_AWREADY,
s_axi_awvalid => m00_couplers_to_m00_regslice_AWVALID,
s_axi_bready => m00_couplers_to_m00_regslice_BREADY,
s_axi_bresp(1 downto 0) => m00_couplers_to_m00_regslice_BRESP(1 downto 0),
s_axi_bvalid => m00_couplers_to_m00_regslice_BVALID,
s_axi_rdata(31 downto 0) => m00_couplers_to_m00_regslice_RDATA(31 downto 0),
s_axi_rready => m00_couplers_to_m00_regslice_RREADY,
s_axi_rresp(1 downto 0) => m00_couplers_to_m00_regslice_RRESP(1 downto 0),
s_axi_rvalid => m00_couplers_to_m00_regslice_RVALID,
s_axi_wdata(31 downto 0) => m00_couplers_to_m00_regslice_WDATA(31 downto 0),
s_axi_wready => m00_couplers_to_m00_regslice_WREADY,
s_axi_wstrb(3 downto 0) => m00_couplers_to_m00_regslice_WSTRB(3 downto 0),
s_axi_wvalid => m00_couplers_to_m00_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity m01_couplers_imp_1UJ7QBJ is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end m01_couplers_imp_1UJ7QBJ;
architecture STRUCTURE of m01_couplers_imp_1UJ7QBJ is
component block_design_m01_regslice_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_m01_regslice_0;
signal M_ACLK_1 : STD_LOGIC;
signal M_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal m01_couplers_to_m01_regslice_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_regslice_ARREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_ARVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m01_couplers_to_m01_regslice_AWREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_AWVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_BREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_regslice_BVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_RREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_m01_regslice_RVALID : STD_LOGIC;
signal m01_couplers_to_m01_regslice_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_m01_regslice_WREADY : STD_LOGIC;
signal m01_couplers_to_m01_regslice_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m01_couplers_to_m01_regslice_WVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_regslice_to_m01_couplers_ARREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_ARVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_regslice_to_m01_couplers_AWREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_AWVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_BREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_regslice_to_m01_couplers_BVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_regslice_to_m01_couplers_RREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_regslice_to_m01_couplers_RVALID : STD_LOGIC;
signal m01_regslice_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_regslice_to_m01_couplers_WREADY : STD_LOGIC;
signal m01_regslice_to_m01_couplers_WVALID : STD_LOGIC;
signal NLW_m01_regslice_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_m01_regslice_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_m01_regslice_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
M_ACLK_1 <= M_ACLK;
M_ARESETN_1(0) <= M_ARESETN(0);
M_AXI_araddr(8 downto 0) <= m01_regslice_to_m01_couplers_ARADDR(8 downto 0);
M_AXI_arvalid <= m01_regslice_to_m01_couplers_ARVALID;
M_AXI_awaddr(8 downto 0) <= m01_regslice_to_m01_couplers_AWADDR(8 downto 0);
M_AXI_awvalid <= m01_regslice_to_m01_couplers_AWVALID;
M_AXI_bready <= m01_regslice_to_m01_couplers_BREADY;
M_AXI_rready <= m01_regslice_to_m01_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= m01_regslice_to_m01_couplers_WDATA(31 downto 0);
M_AXI_wvalid <= m01_regslice_to_m01_couplers_WVALID;
S_AXI_arready <= m01_couplers_to_m01_regslice_ARREADY;
S_AXI_awready <= m01_couplers_to_m01_regslice_AWREADY;
S_AXI_bresp(1 downto 0) <= m01_couplers_to_m01_regslice_BRESP(1 downto 0);
S_AXI_bvalid <= m01_couplers_to_m01_regslice_BVALID;
S_AXI_rdata(31 downto 0) <= m01_couplers_to_m01_regslice_RDATA(31 downto 0);
S_AXI_rresp(1 downto 0) <= m01_couplers_to_m01_regslice_RRESP(1 downto 0);
S_AXI_rvalid <= m01_couplers_to_m01_regslice_RVALID;
S_AXI_wready <= m01_couplers_to_m01_regslice_WREADY;
m01_couplers_to_m01_regslice_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
m01_couplers_to_m01_regslice_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
m01_couplers_to_m01_regslice_ARVALID <= S_AXI_arvalid;
m01_couplers_to_m01_regslice_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
m01_couplers_to_m01_regslice_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
m01_couplers_to_m01_regslice_AWVALID <= S_AXI_awvalid;
m01_couplers_to_m01_regslice_BREADY <= S_AXI_bready;
m01_couplers_to_m01_regslice_RREADY <= S_AXI_rready;
m01_couplers_to_m01_regslice_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
m01_couplers_to_m01_regslice_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
m01_couplers_to_m01_regslice_WVALID <= S_AXI_wvalid;
m01_regslice_to_m01_couplers_ARREADY <= M_AXI_arready;
m01_regslice_to_m01_couplers_AWREADY <= M_AXI_awready;
m01_regslice_to_m01_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
m01_regslice_to_m01_couplers_BVALID <= M_AXI_bvalid;
m01_regslice_to_m01_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
m01_regslice_to_m01_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
m01_regslice_to_m01_couplers_RVALID <= M_AXI_rvalid;
m01_regslice_to_m01_couplers_WREADY <= M_AXI_wready;
m01_regslice: component block_design_m01_regslice_0
port map (
aclk => M_ACLK_1,
aresetn => M_ARESETN_1(0),
m_axi_araddr(8 downto 0) => m01_regslice_to_m01_couplers_ARADDR(8 downto 0),
m_axi_arprot(2 downto 0) => NLW_m01_regslice_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arready => m01_regslice_to_m01_couplers_ARREADY,
m_axi_arvalid => m01_regslice_to_m01_couplers_ARVALID,
m_axi_awaddr(8 downto 0) => m01_regslice_to_m01_couplers_AWADDR(8 downto 0),
m_axi_awprot(2 downto 0) => NLW_m01_regslice_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awready => m01_regslice_to_m01_couplers_AWREADY,
m_axi_awvalid => m01_regslice_to_m01_couplers_AWVALID,
m_axi_bready => m01_regslice_to_m01_couplers_BREADY,
m_axi_bresp(1 downto 0) => m01_regslice_to_m01_couplers_BRESP(1 downto 0),
m_axi_bvalid => m01_regslice_to_m01_couplers_BVALID,
m_axi_rdata(31 downto 0) => m01_regslice_to_m01_couplers_RDATA(31 downto 0),
m_axi_rready => m01_regslice_to_m01_couplers_RREADY,
m_axi_rresp(1 downto 0) => m01_regslice_to_m01_couplers_RRESP(1 downto 0),
m_axi_rvalid => m01_regslice_to_m01_couplers_RVALID,
m_axi_wdata(31 downto 0) => m01_regslice_to_m01_couplers_WDATA(31 downto 0),
m_axi_wready => m01_regslice_to_m01_couplers_WREADY,
m_axi_wstrb(3 downto 0) => NLW_m01_regslice_m_axi_wstrb_UNCONNECTED(3 downto 0),
m_axi_wvalid => m01_regslice_to_m01_couplers_WVALID,
s_axi_araddr(8 downto 0) => m01_couplers_to_m01_regslice_ARADDR(8 downto 0),
s_axi_arprot(2 downto 0) => m01_couplers_to_m01_regslice_ARPROT(2 downto 0),
s_axi_arready => m01_couplers_to_m01_regslice_ARREADY,
s_axi_arvalid => m01_couplers_to_m01_regslice_ARVALID,
s_axi_awaddr(8 downto 0) => m01_couplers_to_m01_regslice_AWADDR(8 downto 0),
s_axi_awprot(2 downto 0) => m01_couplers_to_m01_regslice_AWPROT(2 downto 0),
s_axi_awready => m01_couplers_to_m01_regslice_AWREADY,
s_axi_awvalid => m01_couplers_to_m01_regslice_AWVALID,
s_axi_bready => m01_couplers_to_m01_regslice_BREADY,
s_axi_bresp(1 downto 0) => m01_couplers_to_m01_regslice_BRESP(1 downto 0),
s_axi_bvalid => m01_couplers_to_m01_regslice_BVALID,
s_axi_rdata(31 downto 0) => m01_couplers_to_m01_regslice_RDATA(31 downto 0),
s_axi_rready => m01_couplers_to_m01_regslice_RREADY,
s_axi_rresp(1 downto 0) => m01_couplers_to_m01_regslice_RRESP(1 downto 0),
s_axi_rvalid => m01_couplers_to_m01_regslice_RVALID,
s_axi_wdata(31 downto 0) => m01_couplers_to_m01_regslice_WDATA(31 downto 0),
s_axi_wready => m01_couplers_to_m01_regslice_WREADY,
s_axi_wstrb(3 downto 0) => m01_couplers_to_m01_regslice_WSTRB(3 downto 0),
s_axi_wvalid => m01_couplers_to_m01_regslice_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_1RQO0KS is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arvalid : out STD_LOGIC;
M_AXI_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_awready : in STD_LOGIC;
M_AXI_awvalid : out STD_LOGIC;
M_AXI_bready : out STD_LOGIC;
M_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_bvalid : in STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
M_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_wready : in STD_LOGIC;
M_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_wvalid : out STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_awready : out STD_LOGIC;
S_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_awvalid : in STD_LOGIC;
S_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_bready : in STD_LOGIC;
S_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_bvalid : out STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC;
S_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S_AXI_wlast : in STD_LOGIC;
S_AXI_wready : out STD_LOGIC;
S_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_wvalid : in STD_LOGIC
);
end s00_couplers_imp_1RQO0KS;
architecture STRUCTURE of s00_couplers_imp_1RQO0KS is
component block_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_0;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_AWREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_AWVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_BREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_BVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_WREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_WVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_AWREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_AWVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_BREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_BVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s00_couplers_to_auto_pc_WLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_WREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_WVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_awaddr(31 downto 0) <= auto_pc_to_s00_couplers_AWADDR(31 downto 0);
M_AXI_awprot(2 downto 0) <= auto_pc_to_s00_couplers_AWPROT(2 downto 0);
M_AXI_awvalid <= auto_pc_to_s00_couplers_AWVALID;
M_AXI_bready <= auto_pc_to_s00_couplers_BREADY;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
M_AXI_wdata(31 downto 0) <= auto_pc_to_s00_couplers_WDATA(31 downto 0);
M_AXI_wstrb(3 downto 0) <= auto_pc_to_s00_couplers_WSTRB(3 downto 0);
M_AXI_wvalid <= auto_pc_to_s00_couplers_WVALID;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_awready <= s00_couplers_to_auto_pc_AWREADY;
S_AXI_bid(11 downto 0) <= s00_couplers_to_auto_pc_BID(11 downto 0);
S_AXI_bresp(1 downto 0) <= s00_couplers_to_auto_pc_BRESP(1 downto 0);
S_AXI_bvalid <= s00_couplers_to_auto_pc_BVALID;
S_AXI_rdata(31 downto 0) <= s00_couplers_to_auto_pc_RDATA(31 downto 0);
S_AXI_rid(11 downto 0) <= s00_couplers_to_auto_pc_RID(11 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
S_AXI_wready <= s00_couplers_to_auto_pc_WREADY;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_AWREADY <= M_AXI_awready;
auto_pc_to_s00_couplers_BRESP(1 downto 0) <= M_AXI_bresp(1 downto 0);
auto_pc_to_s00_couplers_BVALID <= M_AXI_bvalid;
auto_pc_to_s00_couplers_RDATA(31 downto 0) <= M_AXI_rdata(31 downto 0);
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
auto_pc_to_s00_couplers_WREADY <= M_AXI_wready;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARID(11 downto 0) <= S_AXI_arid(11 downto 0);
s00_couplers_to_auto_pc_ARLEN(3 downto 0) <= S_AXI_arlen(3 downto 0);
s00_couplers_to_auto_pc_ARLOCK(1 downto 0) <= S_AXI_arlock(1 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARQOS(3 downto 0) <= S_AXI_arqos(3 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_AWADDR(31 downto 0) <= S_AXI_awaddr(31 downto 0);
s00_couplers_to_auto_pc_AWBURST(1 downto 0) <= S_AXI_awburst(1 downto 0);
s00_couplers_to_auto_pc_AWCACHE(3 downto 0) <= S_AXI_awcache(3 downto 0);
s00_couplers_to_auto_pc_AWID(11 downto 0) <= S_AXI_awid(11 downto 0);
s00_couplers_to_auto_pc_AWLEN(3 downto 0) <= S_AXI_awlen(3 downto 0);
s00_couplers_to_auto_pc_AWLOCK(1 downto 0) <= S_AXI_awlock(1 downto 0);
s00_couplers_to_auto_pc_AWPROT(2 downto 0) <= S_AXI_awprot(2 downto 0);
s00_couplers_to_auto_pc_AWQOS(3 downto 0) <= S_AXI_awqos(3 downto 0);
s00_couplers_to_auto_pc_AWSIZE(2 downto 0) <= S_AXI_awsize(2 downto 0);
s00_couplers_to_auto_pc_AWVALID <= S_AXI_awvalid;
s00_couplers_to_auto_pc_BREADY <= S_AXI_bready;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
s00_couplers_to_auto_pc_WDATA(31 downto 0) <= S_AXI_wdata(31 downto 0);
s00_couplers_to_auto_pc_WID(11 downto 0) <= S_AXI_wid(11 downto 0);
s00_couplers_to_auto_pc_WLAST <= S_AXI_wlast;
s00_couplers_to_auto_pc_WSTRB(3 downto 0) <= S_AXI_wstrb(3 downto 0);
s00_couplers_to_auto_pc_WVALID <= S_AXI_wvalid;
auto_pc: component block_design_auto_pc_0
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_awaddr(31 downto 0) => auto_pc_to_s00_couplers_AWADDR(31 downto 0),
m_axi_awprot(2 downto 0) => auto_pc_to_s00_couplers_AWPROT(2 downto 0),
m_axi_awready => auto_pc_to_s00_couplers_AWREADY,
m_axi_awvalid => auto_pc_to_s00_couplers_AWVALID,
m_axi_bready => auto_pc_to_s00_couplers_BREADY,
m_axi_bresp(1 downto 0) => auto_pc_to_s00_couplers_BRESP(1 downto 0),
m_axi_bvalid => auto_pc_to_s00_couplers_BVALID,
m_axi_rdata(31 downto 0) => auto_pc_to_s00_couplers_RDATA(31 downto 0),
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
m_axi_wdata(31 downto 0) => auto_pc_to_s00_couplers_WDATA(31 downto 0),
m_axi_wready => auto_pc_to_s00_couplers_WREADY,
m_axi_wstrb(3 downto 0) => auto_pc_to_s00_couplers_WSTRB(3 downto 0),
m_axi_wvalid => auto_pc_to_s00_couplers_WVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arid(11 downto 0) => s00_couplers_to_auto_pc_ARID(11 downto 0),
s_axi_arlen(3 downto 0) => s00_couplers_to_auto_pc_ARLEN(3 downto 0),
s_axi_arlock(1 downto 0) => s00_couplers_to_auto_pc_ARLOCK(1 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => s00_couplers_to_auto_pc_ARQOS(3 downto 0),
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_auto_pc_AWADDR(31 downto 0),
s_axi_awburst(1 downto 0) => s00_couplers_to_auto_pc_AWBURST(1 downto 0),
s_axi_awcache(3 downto 0) => s00_couplers_to_auto_pc_AWCACHE(3 downto 0),
s_axi_awid(11 downto 0) => s00_couplers_to_auto_pc_AWID(11 downto 0),
s_axi_awlen(3 downto 0) => s00_couplers_to_auto_pc_AWLEN(3 downto 0),
s_axi_awlock(1 downto 0) => s00_couplers_to_auto_pc_AWLOCK(1 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_auto_pc_AWPROT(2 downto 0),
s_axi_awqos(3 downto 0) => s00_couplers_to_auto_pc_AWQOS(3 downto 0),
s_axi_awready => s00_couplers_to_auto_pc_AWREADY,
s_axi_awsize(2 downto 0) => s00_couplers_to_auto_pc_AWSIZE(2 downto 0),
s_axi_awvalid => s00_couplers_to_auto_pc_AWVALID,
s_axi_bid(11 downto 0) => s00_couplers_to_auto_pc_BID(11 downto 0),
s_axi_bready => s00_couplers_to_auto_pc_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_auto_pc_BRESP(1 downto 0),
s_axi_bvalid => s00_couplers_to_auto_pc_BVALID,
s_axi_rdata(31 downto 0) => s00_couplers_to_auto_pc_RDATA(31 downto 0),
s_axi_rid(11 downto 0) => s00_couplers_to_auto_pc_RID(11 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID,
s_axi_wdata(31 downto 0) => s00_couplers_to_auto_pc_WDATA(31 downto 0),
s_axi_wid(11 downto 0) => s00_couplers_to_auto_pc_WID(11 downto 0),
s_axi_wlast => s00_couplers_to_auto_pc_WLAST,
s_axi_wready => s00_couplers_to_auto_pc_WREADY,
s_axi_wstrb(3 downto 0) => s00_couplers_to_auto_pc_WSTRB(3 downto 0),
s_axi_wvalid => s00_couplers_to_auto_pc_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity s00_couplers_imp_QE4JF is
port (
M_ACLK : in STD_LOGIC;
M_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_arready : in STD_LOGIC;
M_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_arvalid : out STD_LOGIC;
M_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M_AXI_rlast : in STD_LOGIC;
M_AXI_rready : out STD_LOGIC;
M_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_rvalid : in STD_LOGIC;
S_ACLK : in STD_LOGIC;
S_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arready : out STD_LOGIC;
S_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_arvalid : in STD_LOGIC;
S_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_rlast : out STD_LOGIC;
S_AXI_rready : in STD_LOGIC;
S_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_rvalid : out STD_LOGIC
);
end s00_couplers_imp_QE4JF;
architecture STRUCTURE of s00_couplers_imp_QE4JF is
component block_design_auto_pc_1 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end component block_design_auto_pc_1;
signal S_ACLK_1 : STD_LOGIC;
signal S_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal auto_pc_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal auto_pc_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal auto_pc_to_s00_couplers_ARREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal auto_pc_to_s00_couplers_ARVALID : STD_LOGIC;
signal auto_pc_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal auto_pc_to_s00_couplers_RLAST : STD_LOGIC;
signal auto_pc_to_s00_couplers_RREADY : STD_LOGIC;
signal auto_pc_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal auto_pc_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_auto_pc_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_auto_pc_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s00_couplers_to_auto_pc_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_auto_pc_ARVALID : STD_LOGIC;
signal s00_couplers_to_auto_pc_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_auto_pc_RLAST : STD_LOGIC;
signal s00_couplers_to_auto_pc_RREADY : STD_LOGIC;
signal s00_couplers_to_auto_pc_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_auto_pc_RVALID : STD_LOGIC;
begin
M_AXI_araddr(31 downto 0) <= auto_pc_to_s00_couplers_ARADDR(31 downto 0);
M_AXI_arburst(1 downto 0) <= auto_pc_to_s00_couplers_ARBURST(1 downto 0);
M_AXI_arcache(3 downto 0) <= auto_pc_to_s00_couplers_ARCACHE(3 downto 0);
M_AXI_arlen(3 downto 0) <= auto_pc_to_s00_couplers_ARLEN(3 downto 0);
M_AXI_arlock(1 downto 0) <= auto_pc_to_s00_couplers_ARLOCK(1 downto 0);
M_AXI_arprot(2 downto 0) <= auto_pc_to_s00_couplers_ARPROT(2 downto 0);
M_AXI_arqos(3 downto 0) <= auto_pc_to_s00_couplers_ARQOS(3 downto 0);
M_AXI_arsize(2 downto 0) <= auto_pc_to_s00_couplers_ARSIZE(2 downto 0);
M_AXI_arvalid <= auto_pc_to_s00_couplers_ARVALID;
M_AXI_rready <= auto_pc_to_s00_couplers_RREADY;
S_ACLK_1 <= S_ACLK;
S_ARESETN_1(0) <= S_ARESETN(0);
S_AXI_arready <= s00_couplers_to_auto_pc_ARREADY;
S_AXI_rdata(63 downto 0) <= s00_couplers_to_auto_pc_RDATA(63 downto 0);
S_AXI_rlast <= s00_couplers_to_auto_pc_RLAST;
S_AXI_rresp(1 downto 0) <= s00_couplers_to_auto_pc_RRESP(1 downto 0);
S_AXI_rvalid <= s00_couplers_to_auto_pc_RVALID;
auto_pc_to_s00_couplers_ARREADY <= M_AXI_arready;
auto_pc_to_s00_couplers_RDATA(63 downto 0) <= M_AXI_rdata(63 downto 0);
auto_pc_to_s00_couplers_RLAST <= M_AXI_rlast;
auto_pc_to_s00_couplers_RRESP(1 downto 0) <= M_AXI_rresp(1 downto 0);
auto_pc_to_s00_couplers_RVALID <= M_AXI_rvalid;
s00_couplers_to_auto_pc_ARADDR(31 downto 0) <= S_AXI_araddr(31 downto 0);
s00_couplers_to_auto_pc_ARBURST(1 downto 0) <= S_AXI_arburst(1 downto 0);
s00_couplers_to_auto_pc_ARCACHE(3 downto 0) <= S_AXI_arcache(3 downto 0);
s00_couplers_to_auto_pc_ARLEN(7 downto 0) <= S_AXI_arlen(7 downto 0);
s00_couplers_to_auto_pc_ARPROT(2 downto 0) <= S_AXI_arprot(2 downto 0);
s00_couplers_to_auto_pc_ARSIZE(2 downto 0) <= S_AXI_arsize(2 downto 0);
s00_couplers_to_auto_pc_ARVALID <= S_AXI_arvalid;
s00_couplers_to_auto_pc_RREADY <= S_AXI_rready;
auto_pc: component block_design_auto_pc_1
port map (
aclk => S_ACLK_1,
aresetn => S_ARESETN_1(0),
m_axi_araddr(31 downto 0) => auto_pc_to_s00_couplers_ARADDR(31 downto 0),
m_axi_arburst(1 downto 0) => auto_pc_to_s00_couplers_ARBURST(1 downto 0),
m_axi_arcache(3 downto 0) => auto_pc_to_s00_couplers_ARCACHE(3 downto 0),
m_axi_arlen(3 downto 0) => auto_pc_to_s00_couplers_ARLEN(3 downto 0),
m_axi_arlock(1 downto 0) => auto_pc_to_s00_couplers_ARLOCK(1 downto 0),
m_axi_arprot(2 downto 0) => auto_pc_to_s00_couplers_ARPROT(2 downto 0),
m_axi_arqos(3 downto 0) => auto_pc_to_s00_couplers_ARQOS(3 downto 0),
m_axi_arready => auto_pc_to_s00_couplers_ARREADY,
m_axi_arsize(2 downto 0) => auto_pc_to_s00_couplers_ARSIZE(2 downto 0),
m_axi_arvalid => auto_pc_to_s00_couplers_ARVALID,
m_axi_rdata(63 downto 0) => auto_pc_to_s00_couplers_RDATA(63 downto 0),
m_axi_rlast => auto_pc_to_s00_couplers_RLAST,
m_axi_rready => auto_pc_to_s00_couplers_RREADY,
m_axi_rresp(1 downto 0) => auto_pc_to_s00_couplers_RRESP(1 downto 0),
m_axi_rvalid => auto_pc_to_s00_couplers_RVALID,
s_axi_araddr(31 downto 0) => s00_couplers_to_auto_pc_ARADDR(31 downto 0),
s_axi_arburst(1 downto 0) => s00_couplers_to_auto_pc_ARBURST(1 downto 0),
s_axi_arcache(3 downto 0) => s00_couplers_to_auto_pc_ARCACHE(3 downto 0),
s_axi_arlen(7 downto 0) => s00_couplers_to_auto_pc_ARLEN(7 downto 0),
s_axi_arlock(0) => '0',
s_axi_arprot(2 downto 0) => s00_couplers_to_auto_pc_ARPROT(2 downto 0),
s_axi_arqos(3 downto 0) => B"0000",
s_axi_arready => s00_couplers_to_auto_pc_ARREADY,
s_axi_arregion(3 downto 0) => B"0000",
s_axi_arsize(2 downto 0) => s00_couplers_to_auto_pc_ARSIZE(2 downto 0),
s_axi_arvalid => s00_couplers_to_auto_pc_ARVALID,
s_axi_rdata(63 downto 0) => s00_couplers_to_auto_pc_RDATA(63 downto 0),
s_axi_rlast => s00_couplers_to_auto_pc_RLAST,
s_axi_rready => s00_couplers_to_auto_pc_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_auto_pc_RRESP(1 downto 0),
s_axi_rvalid => s00_couplers_to_auto_pc_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_0_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_awaddr : out STD_LOGIC_VECTOR ( 5 downto 0 );
M00_AXI_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_awready : in STD_LOGIC;
M00_AXI_awvalid : out STD_LOGIC;
M00_AXI_bready : out STD_LOGIC;
M00_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_bvalid : in STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
M00_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_wready : in STD_LOGIC;
M00_AXI_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_wvalid : out STD_LOGIC;
M01_ACLK : in STD_LOGIC;
M01_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M01_AXI_araddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_arready : in STD_LOGIC;
M01_AXI_arvalid : out STD_LOGIC;
M01_AXI_awaddr : out STD_LOGIC_VECTOR ( 8 downto 0 );
M01_AXI_awready : in STD_LOGIC;
M01_AXI_awvalid : out STD_LOGIC;
M01_AXI_bready : out STD_LOGIC;
M01_AXI_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_bvalid : in STD_LOGIC;
M01_AXI_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_rready : out STD_LOGIC;
M01_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M01_AXI_rvalid : in STD_LOGIC;
M01_AXI_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
M01_AXI_wready : in STD_LOGIC;
M01_AXI_wvalid : out STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_awready : out STD_LOGIC;
S00_AXI_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_awvalid : in STD_LOGIC;
S00_AXI_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_bready : in STD_LOGIC;
S00_AXI_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_bvalid : out STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC;
S00_AXI_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
S00_AXI_wlast : in STD_LOGIC;
S00_AXI_wready : out STD_LOGIC;
S00_AXI_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_wvalid : in STD_LOGIC
);
end block_design_axi_interconnect_0_0;
architecture STRUCTURE of block_design_axi_interconnect_0_0 is
component block_design_xbar_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bready : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rready : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_awvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_arvalid : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rvalid : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rready : out STD_LOGIC_VECTOR ( 1 downto 0 )
);
end component block_design_xbar_0;
signal M00_ACLK_1 : STD_LOGIC;
signal M00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal M01_ACLK_1 : STD_LOGIC;
signal M01_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_ACLK_net : STD_LOGIC;
signal axi_interconnect_0_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_0_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_to_s00_couplers_AWVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_BVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_to_s00_couplers_RVALID : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WLAST : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WREADY : STD_LOGIC;
signal axi_interconnect_0_to_s00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_to_s00_couplers_WVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal m00_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m00_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m00_couplers_to_axi_interconnect_0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal m00_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_axi_interconnect_0_ARREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_ARVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal m01_couplers_to_axi_interconnect_0_AWREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_AWVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_BVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal m01_couplers_to_axi_interconnect_0_RVALID : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal m01_couplers_to_axi_interconnect_0_WREADY : STD_LOGIC;
signal m01_couplers_to_axi_interconnect_0_WVALID : STD_LOGIC;
signal s00_couplers_to_xbar_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_ARREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_ARVALID : STD_LOGIC;
signal s00_couplers_to_xbar_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_xbar_AWREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_AWVALID : STD_LOGIC;
signal s00_couplers_to_xbar_BREADY : STD_LOGIC;
signal s00_couplers_to_xbar_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_BVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_RREADY : STD_LOGIC;
signal s00_couplers_to_xbar_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_xbar_RVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_xbar_WREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal s00_couplers_to_xbar_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_xbar_WVALID : STD_LOGIC;
signal xbar_to_m00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m00_couplers_ARVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal xbar_to_m00_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m00_couplers_AWVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_BVALID : STD_LOGIC;
signal xbar_to_m00_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_RREADY : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m00_couplers_RVALID : STD_LOGIC;
signal xbar_to_m00_couplers_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m00_couplers_WREADY : STD_LOGIC;
signal xbar_to_m00_couplers_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal xbar_to_m00_couplers_WVALID : STD_LOGIC_VECTOR ( 0 to 0 );
signal xbar_to_m01_couplers_ARADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_ARPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_ARREADY : STD_LOGIC;
signal xbar_to_m01_couplers_ARVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_AWADDR : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_AWPROT : STD_LOGIC_VECTOR ( 5 downto 3 );
signal xbar_to_m01_couplers_AWREADY : STD_LOGIC;
signal xbar_to_m01_couplers_AWVALID : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_BVALID : STD_LOGIC;
signal xbar_to_m01_couplers_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal xbar_to_m01_couplers_RREADY : STD_LOGIC_VECTOR ( 1 to 1 );
signal xbar_to_m01_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal xbar_to_m01_couplers_RVALID : STD_LOGIC;
signal xbar_to_m01_couplers_WDATA : STD_LOGIC_VECTOR ( 63 downto 32 );
signal xbar_to_m01_couplers_WREADY : STD_LOGIC;
signal xbar_to_m01_couplers_WSTRB : STD_LOGIC_VECTOR ( 7 downto 4 );
signal xbar_to_m01_couplers_WVALID : STD_LOGIC_VECTOR ( 1 to 1 );
begin
M00_ACLK_1 <= M00_ACLK;
M00_ARESETN_1(0) <= M00_ARESETN(0);
M00_AXI_araddr(5 downto 0) <= m00_couplers_to_axi_interconnect_0_ARADDR(5 downto 0);
M00_AXI_arprot(2 downto 0) <= m00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0);
M00_AXI_arvalid <= m00_couplers_to_axi_interconnect_0_ARVALID;
M00_AXI_awaddr(5 downto 0) <= m00_couplers_to_axi_interconnect_0_AWADDR(5 downto 0);
M00_AXI_awprot(2 downto 0) <= m00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0);
M00_AXI_awvalid <= m00_couplers_to_axi_interconnect_0_AWVALID;
M00_AXI_bready <= m00_couplers_to_axi_interconnect_0_BREADY;
M00_AXI_rready <= m00_couplers_to_axi_interconnect_0_RREADY;
M00_AXI_wdata(31 downto 0) <= m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M00_AXI_wstrb(3 downto 0) <= m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0);
M00_AXI_wvalid <= m00_couplers_to_axi_interconnect_0_WVALID;
M01_ACLK_1 <= M01_ACLK;
M01_ARESETN_1(0) <= M01_ARESETN(0);
M01_AXI_araddr(8 downto 0) <= m01_couplers_to_axi_interconnect_0_ARADDR(8 downto 0);
M01_AXI_arvalid <= m01_couplers_to_axi_interconnect_0_ARVALID;
M01_AXI_awaddr(8 downto 0) <= m01_couplers_to_axi_interconnect_0_AWADDR(8 downto 0);
M01_AXI_awvalid <= m01_couplers_to_axi_interconnect_0_AWVALID;
M01_AXI_bready <= m01_couplers_to_axi_interconnect_0_BREADY;
M01_AXI_rready <= m01_couplers_to_axi_interconnect_0_RREADY;
M01_AXI_wdata(31 downto 0) <= m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0);
M01_AXI_wvalid <= m01_couplers_to_axi_interconnect_0_WVALID;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_0_to_s00_couplers_ARREADY;
S00_AXI_awready <= axi_interconnect_0_to_s00_couplers_AWREADY;
S00_AXI_bid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_BID(11 downto 0);
S00_AXI_bresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0);
S00_AXI_bvalid <= axi_interconnect_0_to_s00_couplers_BVALID;
S00_AXI_rdata(31 downto 0) <= axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0);
S00_AXI_rid(11 downto 0) <= axi_interconnect_0_to_s00_couplers_RID(11 downto 0);
S00_AXI_rlast <= axi_interconnect_0_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_0_to_s00_couplers_RVALID;
S00_AXI_wready <= axi_interconnect_0_to_s00_couplers_WREADY;
axi_interconnect_0_ACLK_net <= ACLK;
axi_interconnect_0_ARESETN_net(0) <= ARESETN(0);
axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARID(11 downto 0) <= S00_AXI_arid(11 downto 0);
axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0) <= S00_AXI_arlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0) <= S00_AXI_arlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0) <= S00_AXI_arqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0) <= S00_AXI_awaddr(31 downto 0);
axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0) <= S00_AXI_awburst(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0) <= S00_AXI_awcache(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWID(11 downto 0) <= S00_AXI_awid(11 downto 0);
axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0) <= S00_AXI_awlen(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0) <= S00_AXI_awlock(1 downto 0);
axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0) <= S00_AXI_awprot(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0) <= S00_AXI_awqos(3 downto 0);
axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0) <= S00_AXI_awsize(2 downto 0);
axi_interconnect_0_to_s00_couplers_AWVALID <= S00_AXI_awvalid;
axi_interconnect_0_to_s00_couplers_BREADY <= S00_AXI_bready;
axi_interconnect_0_to_s00_couplers_RREADY <= S00_AXI_rready;
axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0) <= S00_AXI_wdata(31 downto 0);
axi_interconnect_0_to_s00_couplers_WID(11 downto 0) <= S00_AXI_wid(11 downto 0);
axi_interconnect_0_to_s00_couplers_WLAST <= S00_AXI_wlast;
axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0) <= S00_AXI_wstrb(3 downto 0);
axi_interconnect_0_to_s00_couplers_WVALID <= S00_AXI_wvalid;
m00_couplers_to_axi_interconnect_0_ARREADY <= M00_AXI_arready;
m00_couplers_to_axi_interconnect_0_AWREADY <= M00_AXI_awready;
m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M00_AXI_bresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_BVALID <= M00_AXI_bvalid;
m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M00_AXI_rdata(31 downto 0);
m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
m00_couplers_to_axi_interconnect_0_RVALID <= M00_AXI_rvalid;
m00_couplers_to_axi_interconnect_0_WREADY <= M00_AXI_wready;
m01_couplers_to_axi_interconnect_0_ARREADY <= M01_AXI_arready;
m01_couplers_to_axi_interconnect_0_AWREADY <= M01_AXI_awready;
m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0) <= M01_AXI_bresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_BVALID <= M01_AXI_bvalid;
m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0) <= M01_AXI_rdata(31 downto 0);
m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0) <= M01_AXI_rresp(1 downto 0);
m01_couplers_to_axi_interconnect_0_RVALID <= M01_AXI_rvalid;
m01_couplers_to_axi_interconnect_0_WREADY <= M01_AXI_wready;
m00_couplers: entity work.m00_couplers_imp_1X21ZCV
port map (
M_ACLK => M00_ACLK_1,
M_ARESETN(0) => M00_ARESETN_1(0),
M_AXI_araddr(5 downto 0) => m00_couplers_to_axi_interconnect_0_ARADDR(5 downto 0),
M_AXI_arprot(2 downto 0) => m00_couplers_to_axi_interconnect_0_ARPROT(2 downto 0),
M_AXI_arready => m00_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m00_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(5 downto 0) => m00_couplers_to_axi_interconnect_0_AWADDR(5 downto 0),
M_AXI_awprot(2 downto 0) => m00_couplers_to_axi_interconnect_0_AWPROT(2 downto 0),
M_AXI_awready => m00_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m00_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m00_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m00_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m00_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m00_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m00_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m00_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m00_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wstrb(3 downto 0) => m00_couplers_to_axi_interconnect_0_WSTRB(3 downto 0),
M_AXI_wvalid => m00_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
S_AXI_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
S_AXI_arready => xbar_to_m00_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m00_couplers_ARVALID(0),
S_AXI_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
S_AXI_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
S_AXI_awready => xbar_to_m00_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m00_couplers_AWVALID(0),
S_AXI_bready => xbar_to_m00_couplers_BREADY(0),
S_AXI_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m00_couplers_RREADY(0),
S_AXI_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
S_AXI_wready => xbar_to_m00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => xbar_to_m00_couplers_WVALID(0)
);
m01_couplers: entity work.m01_couplers_imp_1UJ7QBJ
port map (
M_ACLK => M01_ACLK_1,
M_ARESETN(0) => M01_ARESETN_1(0),
M_AXI_araddr(8 downto 0) => m01_couplers_to_axi_interconnect_0_ARADDR(8 downto 0),
M_AXI_arready => m01_couplers_to_axi_interconnect_0_ARREADY,
M_AXI_arvalid => m01_couplers_to_axi_interconnect_0_ARVALID,
M_AXI_awaddr(8 downto 0) => m01_couplers_to_axi_interconnect_0_AWADDR(8 downto 0),
M_AXI_awready => m01_couplers_to_axi_interconnect_0_AWREADY,
M_AXI_awvalid => m01_couplers_to_axi_interconnect_0_AWVALID,
M_AXI_bready => m01_couplers_to_axi_interconnect_0_BREADY,
M_AXI_bresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_BRESP(1 downto 0),
M_AXI_bvalid => m01_couplers_to_axi_interconnect_0_BVALID,
M_AXI_rdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_RDATA(31 downto 0),
M_AXI_rready => m01_couplers_to_axi_interconnect_0_RREADY,
M_AXI_rresp(1 downto 0) => m01_couplers_to_axi_interconnect_0_RRESP(1 downto 0),
M_AXI_rvalid => m01_couplers_to_axi_interconnect_0_RVALID,
M_AXI_wdata(31 downto 0) => m01_couplers_to_axi_interconnect_0_WDATA(31 downto 0),
M_AXI_wready => m01_couplers_to_axi_interconnect_0_WREADY,
M_AXI_wvalid => m01_couplers_to_axi_interconnect_0_WVALID,
S_ACLK => axi_interconnect_0_ACLK_net,
S_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
S_AXI_araddr(31 downto 0) => xbar_to_m01_couplers_ARADDR(63 downto 32),
S_AXI_arprot(2 downto 0) => xbar_to_m01_couplers_ARPROT(5 downto 3),
S_AXI_arready => xbar_to_m01_couplers_ARREADY,
S_AXI_arvalid => xbar_to_m01_couplers_ARVALID(1),
S_AXI_awaddr(31 downto 0) => xbar_to_m01_couplers_AWADDR(63 downto 32),
S_AXI_awprot(2 downto 0) => xbar_to_m01_couplers_AWPROT(5 downto 3),
S_AXI_awready => xbar_to_m01_couplers_AWREADY,
S_AXI_awvalid => xbar_to_m01_couplers_AWVALID(1),
S_AXI_bready => xbar_to_m01_couplers_BREADY(1),
S_AXI_bresp(1 downto 0) => xbar_to_m01_couplers_BRESP(1 downto 0),
S_AXI_bvalid => xbar_to_m01_couplers_BVALID,
S_AXI_rdata(31 downto 0) => xbar_to_m01_couplers_RDATA(31 downto 0),
S_AXI_rready => xbar_to_m01_couplers_RREADY(1),
S_AXI_rresp(1 downto 0) => xbar_to_m01_couplers_RRESP(1 downto 0),
S_AXI_rvalid => xbar_to_m01_couplers_RVALID,
S_AXI_wdata(31 downto 0) => xbar_to_m01_couplers_WDATA(63 downto 32),
S_AXI_wready => xbar_to_m01_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => xbar_to_m01_couplers_WSTRB(7 downto 4),
S_AXI_wvalid => xbar_to_m01_couplers_WVALID(1)
);
s00_couplers: entity work.s00_couplers_imp_1RQO0KS
port map (
M_ACLK => axi_interconnect_0_ACLK_net,
M_ARESETN(0) => axi_interconnect_0_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
M_AXI_arready => s00_couplers_to_xbar_ARREADY(0),
M_AXI_arvalid => s00_couplers_to_xbar_ARVALID,
M_AXI_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
M_AXI_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
M_AXI_awready => s00_couplers_to_xbar_AWREADY(0),
M_AXI_awvalid => s00_couplers_to_xbar_AWVALID,
M_AXI_bready => s00_couplers_to_xbar_BREADY,
M_AXI_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
M_AXI_bvalid => s00_couplers_to_xbar_BVALID(0),
M_AXI_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
M_AXI_rready => s00_couplers_to_xbar_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_xbar_RVALID(0),
M_AXI_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
M_AXI_wready => s00_couplers_to_xbar_WREADY(0),
M_AXI_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
M_AXI_wvalid => s00_couplers_to_xbar_WVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arid(11 downto 0) => axi_interconnect_0_to_s00_couplers_ARID(11 downto 0),
S_AXI_arlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARLEN(3 downto 0),
S_AXI_arlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_ARLOCK(1 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_ARQOS(3 downto 0),
S_AXI_arready => axi_interconnect_0_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_0_to_s00_couplers_ARVALID,
S_AXI_awaddr(31 downto 0) => axi_interconnect_0_to_s00_couplers_AWADDR(31 downto 0),
S_AXI_awburst(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWBURST(1 downto 0),
S_AXI_awcache(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWCACHE(3 downto 0),
S_AXI_awid(11 downto 0) => axi_interconnect_0_to_s00_couplers_AWID(11 downto 0),
S_AXI_awlen(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWLEN(3 downto 0),
S_AXI_awlock(1 downto 0) => axi_interconnect_0_to_s00_couplers_AWLOCK(1 downto 0),
S_AXI_awprot(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWPROT(2 downto 0),
S_AXI_awqos(3 downto 0) => axi_interconnect_0_to_s00_couplers_AWQOS(3 downto 0),
S_AXI_awready => axi_interconnect_0_to_s00_couplers_AWREADY,
S_AXI_awsize(2 downto 0) => axi_interconnect_0_to_s00_couplers_AWSIZE(2 downto 0),
S_AXI_awvalid => axi_interconnect_0_to_s00_couplers_AWVALID,
S_AXI_bid(11 downto 0) => axi_interconnect_0_to_s00_couplers_BID(11 downto 0),
S_AXI_bready => axi_interconnect_0_to_s00_couplers_BREADY,
S_AXI_bresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_BRESP(1 downto 0),
S_AXI_bvalid => axi_interconnect_0_to_s00_couplers_BVALID,
S_AXI_rdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_RDATA(31 downto 0),
S_AXI_rid(11 downto 0) => axi_interconnect_0_to_s00_couplers_RID(11 downto 0),
S_AXI_rlast => axi_interconnect_0_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_0_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_0_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_0_to_s00_couplers_RVALID,
S_AXI_wdata(31 downto 0) => axi_interconnect_0_to_s00_couplers_WDATA(31 downto 0),
S_AXI_wid(11 downto 0) => axi_interconnect_0_to_s00_couplers_WID(11 downto 0),
S_AXI_wlast => axi_interconnect_0_to_s00_couplers_WLAST,
S_AXI_wready => axi_interconnect_0_to_s00_couplers_WREADY,
S_AXI_wstrb(3 downto 0) => axi_interconnect_0_to_s00_couplers_WSTRB(3 downto 0),
S_AXI_wvalid => axi_interconnect_0_to_s00_couplers_WVALID
);
xbar: component block_design_xbar_0
port map (
aclk => axi_interconnect_0_ACLK_net,
aresetn => axi_interconnect_0_ARESETN_net(0),
m_axi_araddr(63 downto 32) => xbar_to_m01_couplers_ARADDR(63 downto 32),
m_axi_araddr(31 downto 0) => xbar_to_m00_couplers_ARADDR(31 downto 0),
m_axi_arprot(5 downto 3) => xbar_to_m01_couplers_ARPROT(5 downto 3),
m_axi_arprot(2 downto 0) => xbar_to_m00_couplers_ARPROT(2 downto 0),
m_axi_arready(1) => xbar_to_m01_couplers_ARREADY,
m_axi_arready(0) => xbar_to_m00_couplers_ARREADY,
m_axi_arvalid(1) => xbar_to_m01_couplers_ARVALID(1),
m_axi_arvalid(0) => xbar_to_m00_couplers_ARVALID(0),
m_axi_awaddr(63 downto 32) => xbar_to_m01_couplers_AWADDR(63 downto 32),
m_axi_awaddr(31 downto 0) => xbar_to_m00_couplers_AWADDR(31 downto 0),
m_axi_awprot(5 downto 3) => xbar_to_m01_couplers_AWPROT(5 downto 3),
m_axi_awprot(2 downto 0) => xbar_to_m00_couplers_AWPROT(2 downto 0),
m_axi_awready(1) => xbar_to_m01_couplers_AWREADY,
m_axi_awready(0) => xbar_to_m00_couplers_AWREADY,
m_axi_awvalid(1) => xbar_to_m01_couplers_AWVALID(1),
m_axi_awvalid(0) => xbar_to_m00_couplers_AWVALID(0),
m_axi_bready(1) => xbar_to_m01_couplers_BREADY(1),
m_axi_bready(0) => xbar_to_m00_couplers_BREADY(0),
m_axi_bresp(3 downto 2) => xbar_to_m01_couplers_BRESP(1 downto 0),
m_axi_bresp(1 downto 0) => xbar_to_m00_couplers_BRESP(1 downto 0),
m_axi_bvalid(1) => xbar_to_m01_couplers_BVALID,
m_axi_bvalid(0) => xbar_to_m00_couplers_BVALID,
m_axi_rdata(63 downto 32) => xbar_to_m01_couplers_RDATA(31 downto 0),
m_axi_rdata(31 downto 0) => xbar_to_m00_couplers_RDATA(31 downto 0),
m_axi_rready(1) => xbar_to_m01_couplers_RREADY(1),
m_axi_rready(0) => xbar_to_m00_couplers_RREADY(0),
m_axi_rresp(3 downto 2) => xbar_to_m01_couplers_RRESP(1 downto 0),
m_axi_rresp(1 downto 0) => xbar_to_m00_couplers_RRESP(1 downto 0),
m_axi_rvalid(1) => xbar_to_m01_couplers_RVALID,
m_axi_rvalid(0) => xbar_to_m00_couplers_RVALID,
m_axi_wdata(63 downto 32) => xbar_to_m01_couplers_WDATA(63 downto 32),
m_axi_wdata(31 downto 0) => xbar_to_m00_couplers_WDATA(31 downto 0),
m_axi_wready(1) => xbar_to_m01_couplers_WREADY,
m_axi_wready(0) => xbar_to_m00_couplers_WREADY,
m_axi_wstrb(7 downto 4) => xbar_to_m01_couplers_WSTRB(7 downto 4),
m_axi_wstrb(3 downto 0) => xbar_to_m00_couplers_WSTRB(3 downto 0),
m_axi_wvalid(1) => xbar_to_m01_couplers_WVALID(1),
m_axi_wvalid(0) => xbar_to_m00_couplers_WVALID(0),
s_axi_araddr(31 downto 0) => s00_couplers_to_xbar_ARADDR(31 downto 0),
s_axi_arprot(2 downto 0) => s00_couplers_to_xbar_ARPROT(2 downto 0),
s_axi_arready(0) => s00_couplers_to_xbar_ARREADY(0),
s_axi_arvalid(0) => s00_couplers_to_xbar_ARVALID,
s_axi_awaddr(31 downto 0) => s00_couplers_to_xbar_AWADDR(31 downto 0),
s_axi_awprot(2 downto 0) => s00_couplers_to_xbar_AWPROT(2 downto 0),
s_axi_awready(0) => s00_couplers_to_xbar_AWREADY(0),
s_axi_awvalid(0) => s00_couplers_to_xbar_AWVALID,
s_axi_bready(0) => s00_couplers_to_xbar_BREADY,
s_axi_bresp(1 downto 0) => s00_couplers_to_xbar_BRESP(1 downto 0),
s_axi_bvalid(0) => s00_couplers_to_xbar_BVALID(0),
s_axi_rdata(31 downto 0) => s00_couplers_to_xbar_RDATA(31 downto 0),
s_axi_rready(0) => s00_couplers_to_xbar_RREADY,
s_axi_rresp(1 downto 0) => s00_couplers_to_xbar_RRESP(1 downto 0),
s_axi_rvalid(0) => s00_couplers_to_xbar_RVALID(0),
s_axi_wdata(31 downto 0) => s00_couplers_to_xbar_WDATA(31 downto 0),
s_axi_wready(0) => s00_couplers_to_xbar_WREADY(0),
s_axi_wstrb(3 downto 0) => s00_couplers_to_xbar_WSTRB(3 downto 0),
s_axi_wvalid(0) => s00_couplers_to_xbar_WVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design_axi_interconnect_1_0 is
port (
ACLK : in STD_LOGIC;
ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_ACLK : in STD_LOGIC;
M00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
M00_AXI_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
M00_AXI_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlen : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arlock : out STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
M00_AXI_arready : in STD_LOGIC;
M00_AXI_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
M00_AXI_arvalid : out STD_LOGIC;
M00_AXI_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
M00_AXI_rlast : in STD_LOGIC;
M00_AXI_rready : out STD_LOGIC;
M00_AXI_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
M00_AXI_rvalid : in STD_LOGIC;
S00_ACLK : in STD_LOGIC;
S00_ARESETN : in STD_LOGIC_VECTOR ( 0 to 0 );
S00_AXI_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S00_AXI_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S00_AXI_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
S00_AXI_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arready : out STD_LOGIC;
S00_AXI_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S00_AXI_arvalid : in STD_LOGIC;
S00_AXI_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
S00_AXI_rlast : out STD_LOGIC;
S00_AXI_rready : in STD_LOGIC;
S00_AXI_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S00_AXI_rvalid : out STD_LOGIC
);
end block_design_axi_interconnect_1_0;
architecture STRUCTURE of block_design_axi_interconnect_1_0 is
signal S00_ACLK_1 : STD_LOGIC;
signal S00_ARESETN_1 : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_1_ACLK_net : STD_LOGIC;
signal axi_interconnect_1_ARESETN_net : STD_LOGIC_VECTOR ( 0 to 0 );
signal axi_interconnect_1_to_s00_couplers_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARREADY : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_to_s00_couplers_ARVALID : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_interconnect_1_to_s00_couplers_RLAST : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RREADY : STD_LOGIC;
signal axi_interconnect_1_to_s00_couplers_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_to_s00_couplers_RVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal s00_couplers_to_axi_interconnect_1_ARVALID : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal s00_couplers_to_axi_interconnect_1_RLAST : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RREADY : STD_LOGIC;
signal s00_couplers_to_axi_interconnect_1_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal s00_couplers_to_axi_interconnect_1_RVALID : STD_LOGIC;
begin
M00_AXI_araddr(31 downto 0) <= s00_couplers_to_axi_interconnect_1_ARADDR(31 downto 0);
M00_AXI_arburst(1 downto 0) <= s00_couplers_to_axi_interconnect_1_ARBURST(1 downto 0);
M00_AXI_arcache(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARCACHE(3 downto 0);
M00_AXI_arlen(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARLEN(3 downto 0);
M00_AXI_arlock(1 downto 0) <= s00_couplers_to_axi_interconnect_1_ARLOCK(1 downto 0);
M00_AXI_arprot(2 downto 0) <= s00_couplers_to_axi_interconnect_1_ARPROT(2 downto 0);
M00_AXI_arqos(3 downto 0) <= s00_couplers_to_axi_interconnect_1_ARQOS(3 downto 0);
M00_AXI_arsize(2 downto 0) <= s00_couplers_to_axi_interconnect_1_ARSIZE(2 downto 0);
M00_AXI_arvalid <= s00_couplers_to_axi_interconnect_1_ARVALID;
M00_AXI_rready <= s00_couplers_to_axi_interconnect_1_RREADY;
S00_ACLK_1 <= S00_ACLK;
S00_ARESETN_1(0) <= S00_ARESETN(0);
S00_AXI_arready <= axi_interconnect_1_to_s00_couplers_ARREADY;
S00_AXI_rdata(63 downto 0) <= axi_interconnect_1_to_s00_couplers_RDATA(63 downto 0);
S00_AXI_rlast <= axi_interconnect_1_to_s00_couplers_RLAST;
S00_AXI_rresp(1 downto 0) <= axi_interconnect_1_to_s00_couplers_RRESP(1 downto 0);
S00_AXI_rvalid <= axi_interconnect_1_to_s00_couplers_RVALID;
axi_interconnect_1_ACLK_net <= M00_ACLK;
axi_interconnect_1_ARESETN_net(0) <= M00_ARESETN(0);
axi_interconnect_1_to_s00_couplers_ARADDR(31 downto 0) <= S00_AXI_araddr(31 downto 0);
axi_interconnect_1_to_s00_couplers_ARBURST(1 downto 0) <= S00_AXI_arburst(1 downto 0);
axi_interconnect_1_to_s00_couplers_ARCACHE(3 downto 0) <= S00_AXI_arcache(3 downto 0);
axi_interconnect_1_to_s00_couplers_ARLEN(7 downto 0) <= S00_AXI_arlen(7 downto 0);
axi_interconnect_1_to_s00_couplers_ARPROT(2 downto 0) <= S00_AXI_arprot(2 downto 0);
axi_interconnect_1_to_s00_couplers_ARSIZE(2 downto 0) <= S00_AXI_arsize(2 downto 0);
axi_interconnect_1_to_s00_couplers_ARVALID <= S00_AXI_arvalid;
axi_interconnect_1_to_s00_couplers_RREADY <= S00_AXI_rready;
s00_couplers_to_axi_interconnect_1_ARREADY <= M00_AXI_arready;
s00_couplers_to_axi_interconnect_1_RDATA(63 downto 0) <= M00_AXI_rdata(63 downto 0);
s00_couplers_to_axi_interconnect_1_RLAST <= M00_AXI_rlast;
s00_couplers_to_axi_interconnect_1_RRESP(1 downto 0) <= M00_AXI_rresp(1 downto 0);
s00_couplers_to_axi_interconnect_1_RVALID <= M00_AXI_rvalid;
s00_couplers: entity work.s00_couplers_imp_QE4JF
port map (
M_ACLK => axi_interconnect_1_ACLK_net,
M_ARESETN(0) => axi_interconnect_1_ARESETN_net(0),
M_AXI_araddr(31 downto 0) => s00_couplers_to_axi_interconnect_1_ARADDR(31 downto 0),
M_AXI_arburst(1 downto 0) => s00_couplers_to_axi_interconnect_1_ARBURST(1 downto 0),
M_AXI_arcache(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARCACHE(3 downto 0),
M_AXI_arlen(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARLEN(3 downto 0),
M_AXI_arlock(1 downto 0) => s00_couplers_to_axi_interconnect_1_ARLOCK(1 downto 0),
M_AXI_arprot(2 downto 0) => s00_couplers_to_axi_interconnect_1_ARPROT(2 downto 0),
M_AXI_arqos(3 downto 0) => s00_couplers_to_axi_interconnect_1_ARQOS(3 downto 0),
M_AXI_arready => s00_couplers_to_axi_interconnect_1_ARREADY,
M_AXI_arsize(2 downto 0) => s00_couplers_to_axi_interconnect_1_ARSIZE(2 downto 0),
M_AXI_arvalid => s00_couplers_to_axi_interconnect_1_ARVALID,
M_AXI_rdata(63 downto 0) => s00_couplers_to_axi_interconnect_1_RDATA(63 downto 0),
M_AXI_rlast => s00_couplers_to_axi_interconnect_1_RLAST,
M_AXI_rready => s00_couplers_to_axi_interconnect_1_RREADY,
M_AXI_rresp(1 downto 0) => s00_couplers_to_axi_interconnect_1_RRESP(1 downto 0),
M_AXI_rvalid => s00_couplers_to_axi_interconnect_1_RVALID,
S_ACLK => S00_ACLK_1,
S_ARESETN(0) => S00_ARESETN_1(0),
S_AXI_araddr(31 downto 0) => axi_interconnect_1_to_s00_couplers_ARADDR(31 downto 0),
S_AXI_arburst(1 downto 0) => axi_interconnect_1_to_s00_couplers_ARBURST(1 downto 0),
S_AXI_arcache(3 downto 0) => axi_interconnect_1_to_s00_couplers_ARCACHE(3 downto 0),
S_AXI_arlen(7 downto 0) => axi_interconnect_1_to_s00_couplers_ARLEN(7 downto 0),
S_AXI_arprot(2 downto 0) => axi_interconnect_1_to_s00_couplers_ARPROT(2 downto 0),
S_AXI_arready => axi_interconnect_1_to_s00_couplers_ARREADY,
S_AXI_arsize(2 downto 0) => axi_interconnect_1_to_s00_couplers_ARSIZE(2 downto 0),
S_AXI_arvalid => axi_interconnect_1_to_s00_couplers_ARVALID,
S_AXI_rdata(63 downto 0) => axi_interconnect_1_to_s00_couplers_RDATA(63 downto 0),
S_AXI_rlast => axi_interconnect_1_to_s00_couplers_RLAST,
S_AXI_rready => axi_interconnect_1_to_s00_couplers_RREADY,
S_AXI_rresp(1 downto 0) => axi_interconnect_1_to_s00_couplers_RRESP(1 downto 0),
S_AXI_rvalid => axi_interconnect_1_to_s00_couplers_RVALID
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity block_design is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 5 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 4 downto 0 );
vga_vs : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of block_design : entity is "block_design,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=block_design,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=17,numReposBlks=11,numNonXlnxBlks=1,numHierBlks=6,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=Global}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of block_design : entity is "block_design.hwdef";
end block_design;
architecture STRUCTURE of block_design is
component block_design_axi_dispctrl_0_0 is
port (
REF_CLK_I : in STD_LOGIC;
PXL_CLK_O : out STD_LOGIC;
PXL_CLK_5X_O : out STD_LOGIC;
LOCKED_O : out STD_LOGIC;
FSYNC_O : out STD_LOGIC;
HSYNC_O : out STD_LOGIC;
VSYNC_O : out STD_LOGIC;
DE_O : out STD_LOGIC;
RED_O : out STD_LOGIC_VECTOR ( 4 downto 0 );
GREEN_O : out STD_LOGIC_VECTOR ( 5 downto 0 );
BLUE_O : out STD_LOGIC_VECTOR ( 4 downto 0 );
DEBUG_O : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axis_mm2s_aclk : in STD_LOGIC;
s_axis_mm2s_aresetn : in STD_LOGIC;
s_axis_mm2s_tready : out STD_LOGIC;
s_axis_mm2s_tdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axis_mm2s_tstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axis_mm2s_tlast : in STD_LOGIC;
s_axis_mm2s_tvalid : in STD_LOGIC
);
end component block_design_axi_dispctrl_0_0;
component block_design_axi_vdma_0_0 is
port (
s_axi_lite_aclk : in STD_LOGIC;
m_axi_mm2s_aclk : in STD_LOGIC;
m_axis_mm2s_aclk : in STD_LOGIC;
axi_resetn : in STD_LOGIC;
s_axi_lite_awvalid : in STD_LOGIC;
s_axi_lite_awready : out STD_LOGIC;
s_axi_lite_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_lite_wvalid : in STD_LOGIC;
s_axi_lite_wready : out STD_LOGIC;
s_axi_lite_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_lite_bvalid : out STD_LOGIC;
s_axi_lite_bready : in STD_LOGIC;
s_axi_lite_arvalid : in STD_LOGIC;
s_axi_lite_arready : out STD_LOGIC;
s_axi_lite_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_lite_rvalid : out STD_LOGIC;
s_axi_lite_rready : in STD_LOGIC;
s_axi_lite_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_lite_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
mm2s_fsync : in STD_LOGIC;
mm2s_frame_ptr_in : in STD_LOGIC_VECTOR ( 5 downto 0 );
mm2s_frame_ptr_out : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_axi_mm2s_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_mm2s_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_mm2s_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_mm2s_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_mm2s_arvalid : out STD_LOGIC;
m_axi_mm2s_arready : in STD_LOGIC;
m_axi_mm2s_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_mm2s_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_mm2s_rlast : in STD_LOGIC;
m_axi_mm2s_rvalid : in STD_LOGIC;
m_axi_mm2s_rready : out STD_LOGIC;
m_axis_mm2s_tdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axis_mm2s_tkeep : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_mm2s_tuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_mm2s_tvalid : out STD_LOGIC;
m_axis_mm2s_tready : in STD_LOGIC;
m_axis_mm2s_tlast : out STD_LOGIC;
mm2s_introut : out STD_LOGIC
);
end component block_design_axi_vdma_0_0;
component block_design_processing_system7_0_0 is
port (
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARREADY : out STD_LOGIC;
S_AXI_HP0_AWREADY : out STD_LOGIC;
S_AXI_HP0_BVALID : out STD_LOGIC;
S_AXI_HP0_RLAST : out STD_LOGIC;
S_AXI_HP0_RVALID : out STD_LOGIC;
S_AXI_HP0_WREADY : out STD_LOGIC;
S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 );
S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_ACLK : in STD_LOGIC;
S_AXI_HP0_ARVALID : in STD_LOGIC;
S_AXI_HP0_AWVALID : in STD_LOGIC;
S_AXI_HP0_BREADY : in STD_LOGIC;
S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_RREADY : in STD_LOGIC;
S_AXI_HP0_WLAST : in STD_LOGIC;
S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC;
S_AXI_HP0_WVALID : in STD_LOGIC;
S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 );
S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 );
S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component block_design_processing_system7_0_0;
component block_design_proc_sys_reset_0_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_0_0;
component block_design_xlconstant_0_0 is
port (
dout : out STD_LOGIC_VECTOR ( 5 downto 0 )
);
end component block_design_xlconstant_0_0;
component block_design_proc_sys_reset_1_0 is
port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end component block_design_proc_sys_reset_1_0;
signal axi_dispctrl_0_BLUE_O : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_dispctrl_0_FSYNC_O : STD_LOGIC;
signal axi_dispctrl_0_GREEN_O : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_dispctrl_0_HSYNC_O : STD_LOGIC;
signal axi_dispctrl_0_PXL_CLK_O : STD_LOGIC;
signal axi_dispctrl_0_RED_O : STD_LOGIC_VECTOR ( 4 downto 0 );
signal axi_dispctrl_0_VSYNC_O : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_interconnect_0_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWADDR : STD_LOGIC_VECTOR ( 5 downto 0 );
signal axi_interconnect_0_M00_AXI_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_0_M00_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M00_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M00_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M00_AXI_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_0_M00_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal axi_interconnect_0_M01_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWADDR : STD_LOGIC_VECTOR ( 8 downto 0 );
signal axi_interconnect_0_M01_AXI_AWREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_AWVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_BVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_0_M01_AXI_RVALID : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_0_M01_AXI_WREADY : STD_LOGIC;
signal axi_interconnect_0_M01_AXI_WVALID : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_interconnect_1_M00_AXI_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_M00_AXI_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_interconnect_1_M00_AXI_ARREADY : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_interconnect_1_M00_AXI_ARVALID : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_interconnect_1_M00_AXI_RLAST : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RREADY : STD_LOGIC;
signal axi_interconnect_1_M00_AXI_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_interconnect_1_M00_AXI_RVALID : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_vdma_0_M_AXIS_MM2S_TLAST : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TREADY : STD_LOGIC;
signal axi_vdma_0_M_AXIS_MM2S_TVALID : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARLEN : STD_LOGIC_VECTOR ( 7 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARREADY : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_ARVALID : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_RDATA : STD_LOGIC_VECTOR ( 63 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_RLAST : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_RREADY : STD_LOGIC;
signal axi_vdma_0_M_AXI_MM2S_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal axi_vdma_0_M_AXI_MM2S_RVALID : STD_LOGIC;
signal axi_vdma_0_m_axis_mm2s_tkeep : STD_LOGIC_VECTOR ( 3 downto 0 );
signal axi_vdma_0_mm2s_introut : STD_LOGIC;
signal proc_sys_reset_0_interconnect_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_0_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal proc_sys_reset_1_peripheral_aresetn : STD_LOGIC_VECTOR ( 0 to 0 );
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_ARSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_ARVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWADDR : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWBURST : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWCACHE : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLEN : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWLOCK : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWPROT : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWQOS : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_AWSIZE : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_M_AXI_GP0_AWVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_BREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_BRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_BVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_RID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_RLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_RRESP : STD_LOGIC_VECTOR ( 1 downto 0 );
signal processing_system7_0_M_AXI_GP0_RVALID : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WDATA : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_M_AXI_GP0_WID : STD_LOGIC_VECTOR ( 11 downto 0 );
signal processing_system7_0_M_AXI_GP0_WLAST : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WREADY : STD_LOGIC;
signal processing_system7_0_M_AXI_GP0_WSTRB : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_M_AXI_GP0_WVALID : STD_LOGIC;
signal xlconstant_0_dout : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_axi_dispctrl_0_DE_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_LOCKED_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_PXL_CLK_5X_O_UNCONNECTED : STD_LOGIC;
signal NLW_axi_dispctrl_0_DEBUG_O_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_axi_vdma_0_m_axis_mm2s_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_proc_sys_reset_0_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_mb_reset_UNCONNECTED : STD_LOGIC;
signal NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
signal NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
begin
vga_b(4 downto 0) <= axi_dispctrl_0_BLUE_O(4 downto 0);
vga_g(5 downto 0) <= axi_dispctrl_0_GREEN_O(5 downto 0);
vga_hs <= axi_dispctrl_0_HSYNC_O;
vga_r(4 downto 0) <= axi_dispctrl_0_RED_O(4 downto 0);
vga_vs <= axi_dispctrl_0_VSYNC_O;
axi_dispctrl_0: component block_design_axi_dispctrl_0_0
port map (
BLUE_O(4 downto 0) => axi_dispctrl_0_BLUE_O(4 downto 0),
DEBUG_O(31 downto 0) => NLW_axi_dispctrl_0_DEBUG_O_UNCONNECTED(31 downto 0),
DE_O => NLW_axi_dispctrl_0_DE_O_UNCONNECTED,
FSYNC_O => axi_dispctrl_0_FSYNC_O,
GREEN_O(5 downto 0) => axi_dispctrl_0_GREEN_O(5 downto 0),
HSYNC_O => axi_dispctrl_0_HSYNC_O,
LOCKED_O => NLW_axi_dispctrl_0_LOCKED_O_UNCONNECTED,
PXL_CLK_5X_O => NLW_axi_dispctrl_0_PXL_CLK_5X_O_UNCONNECTED,
PXL_CLK_O => axi_dispctrl_0_PXL_CLK_O,
RED_O(4 downto 0) => axi_dispctrl_0_RED_O(4 downto 0),
REF_CLK_I => processing_system7_0_FCLK_CLK0,
VSYNC_O => axi_dispctrl_0_VSYNC_O,
s_axi_aclk => processing_system7_0_FCLK_CLK0,
s_axi_araddr(5 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(5 downto 0),
s_axi_aresetn => proc_sys_reset_0_peripheral_aresetn(0),
s_axi_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
s_axi_arready => axi_interconnect_0_M00_AXI_ARREADY,
s_axi_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
s_axi_awaddr(5 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(5 downto 0),
s_axi_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
s_axi_awready => axi_interconnect_0_M00_AXI_AWREADY,
s_axi_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
s_axi_bready => axi_interconnect_0_M00_AXI_BREADY,
s_axi_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
s_axi_bvalid => axi_interconnect_0_M00_AXI_BVALID,
s_axi_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
s_axi_rready => axi_interconnect_0_M00_AXI_RREADY,
s_axi_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
s_axi_rvalid => axi_interconnect_0_M00_AXI_RVALID,
s_axi_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
s_axi_wready => axi_interconnect_0_M00_AXI_WREADY,
s_axi_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
s_axi_wvalid => axi_interconnect_0_M00_AXI_WVALID,
s_axis_mm2s_aclk => axi_dispctrl_0_PXL_CLK_O,
s_axis_mm2s_aresetn => proc_sys_reset_1_peripheral_aresetn(0),
s_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0),
s_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_TLAST,
s_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_TREADY,
s_axis_mm2s_tstrb(3 downto 0) => axi_vdma_0_m_axis_mm2s_tkeep(3 downto 0),
s_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID
);
axi_interconnect_0: entity work.block_design_axi_interconnect_0_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(5 downto 0) => axi_interconnect_0_M00_AXI_ARADDR(5 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_0_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arready => axi_interconnect_0_M00_AXI_ARREADY,
M00_AXI_arvalid => axi_interconnect_0_M00_AXI_ARVALID,
M00_AXI_awaddr(5 downto 0) => axi_interconnect_0_M00_AXI_AWADDR(5 downto 0),
M00_AXI_awprot(2 downto 0) => axi_interconnect_0_M00_AXI_AWPROT(2 downto 0),
M00_AXI_awready => axi_interconnect_0_M00_AXI_AWREADY,
M00_AXI_awvalid => axi_interconnect_0_M00_AXI_AWVALID,
M00_AXI_bready => axi_interconnect_0_M00_AXI_BREADY,
M00_AXI_bresp(1 downto 0) => axi_interconnect_0_M00_AXI_BRESP(1 downto 0),
M00_AXI_bvalid => axi_interconnect_0_M00_AXI_BVALID,
M00_AXI_rdata(31 downto 0) => axi_interconnect_0_M00_AXI_RDATA(31 downto 0),
M00_AXI_rready => axi_interconnect_0_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_0_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_0_M00_AXI_RVALID,
M00_AXI_wdata(31 downto 0) => axi_interconnect_0_M00_AXI_WDATA(31 downto 0),
M00_AXI_wready => axi_interconnect_0_M00_AXI_WREADY,
M00_AXI_wstrb(3 downto 0) => axi_interconnect_0_M00_AXI_WSTRB(3 downto 0),
M00_AXI_wvalid => axi_interconnect_0_M00_AXI_WVALID,
M01_ACLK => processing_system7_0_FCLK_CLK0,
M01_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M01_AXI_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
M01_AXI_arready => axi_interconnect_0_M01_AXI_ARREADY,
M01_AXI_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
M01_AXI_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
M01_AXI_awready => axi_interconnect_0_M01_AXI_AWREADY,
M01_AXI_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
M01_AXI_bready => axi_interconnect_0_M01_AXI_BREADY,
M01_AXI_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
M01_AXI_bvalid => axi_interconnect_0_M01_AXI_BVALID,
M01_AXI_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
M01_AXI_rready => axi_interconnect_0_M01_AXI_RREADY,
M01_AXI_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
M01_AXI_rvalid => axi_interconnect_0_M01_AXI_RVALID,
M01_AXI_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
M01_AXI_wready => axi_interconnect_0_M01_AXI_WREADY,
M01_AXI_wvalid => axi_interconnect_0_M01_AXI_WVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
S00_AXI_arid(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
S00_AXI_arlen(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
S00_AXI_arlock(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
S00_AXI_arprot(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
S00_AXI_arqos(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
S00_AXI_arready => processing_system7_0_M_AXI_GP0_ARREADY,
S00_AXI_arsize(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
S00_AXI_arvalid => processing_system7_0_M_AXI_GP0_ARVALID,
S00_AXI_awaddr(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
S00_AXI_awburst(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
S00_AXI_awcache(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
S00_AXI_awid(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
S00_AXI_awlen(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
S00_AXI_awlock(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
S00_AXI_awprot(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
S00_AXI_awqos(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
S00_AXI_awready => processing_system7_0_M_AXI_GP0_AWREADY,
S00_AXI_awsize(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
S00_AXI_awvalid => processing_system7_0_M_AXI_GP0_AWVALID,
S00_AXI_bid(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
S00_AXI_bready => processing_system7_0_M_AXI_GP0_BREADY,
S00_AXI_bresp(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
S00_AXI_bvalid => processing_system7_0_M_AXI_GP0_BVALID,
S00_AXI_rdata(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
S00_AXI_rid(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
S00_AXI_rlast => processing_system7_0_M_AXI_GP0_RLAST,
S00_AXI_rready => processing_system7_0_M_AXI_GP0_RREADY,
S00_AXI_rresp(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
S00_AXI_rvalid => processing_system7_0_M_AXI_GP0_RVALID,
S00_AXI_wdata(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
S00_AXI_wid(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
S00_AXI_wlast => processing_system7_0_M_AXI_GP0_WLAST,
S00_AXI_wready => processing_system7_0_M_AXI_GP0_WREADY,
S00_AXI_wstrb(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
S00_AXI_wvalid => processing_system7_0_M_AXI_GP0_WVALID
);
axi_interconnect_1: entity work.block_design_axi_interconnect_1_0
port map (
ACLK => processing_system7_0_FCLK_CLK0,
ARESETN(0) => proc_sys_reset_0_interconnect_aresetn(0),
M00_ACLK => processing_system7_0_FCLK_CLK0,
M00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
M00_AXI_araddr(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
M00_AXI_arburst(1 downto 0) => axi_interconnect_1_M00_AXI_ARBURST(1 downto 0),
M00_AXI_arcache(3 downto 0) => axi_interconnect_1_M00_AXI_ARCACHE(3 downto 0),
M00_AXI_arlen(3 downto 0) => axi_interconnect_1_M00_AXI_ARLEN(3 downto 0),
M00_AXI_arlock(1 downto 0) => axi_interconnect_1_M00_AXI_ARLOCK(1 downto 0),
M00_AXI_arprot(2 downto 0) => axi_interconnect_1_M00_AXI_ARPROT(2 downto 0),
M00_AXI_arqos(3 downto 0) => axi_interconnect_1_M00_AXI_ARQOS(3 downto 0),
M00_AXI_arready => axi_interconnect_1_M00_AXI_ARREADY,
M00_AXI_arsize(2 downto 0) => axi_interconnect_1_M00_AXI_ARSIZE(2 downto 0),
M00_AXI_arvalid => axi_interconnect_1_M00_AXI_ARVALID,
M00_AXI_rdata(63 downto 0) => axi_interconnect_1_M00_AXI_RDATA(63 downto 0),
M00_AXI_rlast => axi_interconnect_1_M00_AXI_RLAST,
M00_AXI_rready => axi_interconnect_1_M00_AXI_RREADY,
M00_AXI_rresp(1 downto 0) => axi_interconnect_1_M00_AXI_RRESP(1 downto 0),
M00_AXI_rvalid => axi_interconnect_1_M00_AXI_RVALID,
S00_ACLK => processing_system7_0_FCLK_CLK0,
S00_ARESETN(0) => proc_sys_reset_0_peripheral_aresetn(0),
S00_AXI_araddr(31 downto 0) => axi_vdma_0_M_AXI_MM2S_ARADDR(31 downto 0),
S00_AXI_arburst(1 downto 0) => axi_vdma_0_M_AXI_MM2S_ARBURST(1 downto 0),
S00_AXI_arcache(3 downto 0) => axi_vdma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
S00_AXI_arlen(7 downto 0) => axi_vdma_0_M_AXI_MM2S_ARLEN(7 downto 0),
S00_AXI_arprot(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARPROT(2 downto 0),
S00_AXI_arready => axi_vdma_0_M_AXI_MM2S_ARREADY,
S00_AXI_arsize(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
S00_AXI_arvalid => axi_vdma_0_M_AXI_MM2S_ARVALID,
S00_AXI_rdata(63 downto 0) => axi_vdma_0_M_AXI_MM2S_RDATA(63 downto 0),
S00_AXI_rlast => axi_vdma_0_M_AXI_MM2S_RLAST,
S00_AXI_rready => axi_vdma_0_M_AXI_MM2S_RREADY,
S00_AXI_rresp(1 downto 0) => axi_vdma_0_M_AXI_MM2S_RRESP(1 downto 0),
S00_AXI_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID
);
axi_vdma_0: component block_design_axi_vdma_0_0
port map (
axi_resetn => proc_sys_reset_0_peripheral_aresetn(0),
m_axi_mm2s_aclk => processing_system7_0_FCLK_CLK0,
m_axi_mm2s_araddr(31 downto 0) => axi_vdma_0_M_AXI_MM2S_ARADDR(31 downto 0),
m_axi_mm2s_arburst(1 downto 0) => axi_vdma_0_M_AXI_MM2S_ARBURST(1 downto 0),
m_axi_mm2s_arcache(3 downto 0) => axi_vdma_0_M_AXI_MM2S_ARCACHE(3 downto 0),
m_axi_mm2s_arlen(7 downto 0) => axi_vdma_0_M_AXI_MM2S_ARLEN(7 downto 0),
m_axi_mm2s_arprot(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARPROT(2 downto 0),
m_axi_mm2s_arready => axi_vdma_0_M_AXI_MM2S_ARREADY,
m_axi_mm2s_arsize(2 downto 0) => axi_vdma_0_M_AXI_MM2S_ARSIZE(2 downto 0),
m_axi_mm2s_arvalid => axi_vdma_0_M_AXI_MM2S_ARVALID,
m_axi_mm2s_rdata(63 downto 0) => axi_vdma_0_M_AXI_MM2S_RDATA(63 downto 0),
m_axi_mm2s_rlast => axi_vdma_0_M_AXI_MM2S_RLAST,
m_axi_mm2s_rready => axi_vdma_0_M_AXI_MM2S_RREADY,
m_axi_mm2s_rresp(1 downto 0) => axi_vdma_0_M_AXI_MM2S_RRESP(1 downto 0),
m_axi_mm2s_rvalid => axi_vdma_0_M_AXI_MM2S_RVALID,
m_axis_mm2s_aclk => axi_dispctrl_0_PXL_CLK_O,
m_axis_mm2s_tdata(31 downto 0) => axi_vdma_0_M_AXIS_MM2S_TDATA(31 downto 0),
m_axis_mm2s_tkeep(3 downto 0) => axi_vdma_0_m_axis_mm2s_tkeep(3 downto 0),
m_axis_mm2s_tlast => axi_vdma_0_M_AXIS_MM2S_TLAST,
m_axis_mm2s_tready => axi_vdma_0_M_AXIS_MM2S_TREADY,
m_axis_mm2s_tuser(0) => NLW_axi_vdma_0_m_axis_mm2s_tuser_UNCONNECTED(0),
m_axis_mm2s_tvalid => axi_vdma_0_M_AXIS_MM2S_TVALID,
mm2s_frame_ptr_in(5 downto 0) => xlconstant_0_dout(5 downto 0),
mm2s_frame_ptr_out(5 downto 0) => NLW_axi_vdma_0_mm2s_frame_ptr_out_UNCONNECTED(5 downto 0),
mm2s_fsync => axi_dispctrl_0_FSYNC_O,
mm2s_introut => axi_vdma_0_mm2s_introut,
s_axi_lite_aclk => processing_system7_0_FCLK_CLK0,
s_axi_lite_araddr(8 downto 0) => axi_interconnect_0_M01_AXI_ARADDR(8 downto 0),
s_axi_lite_arready => axi_interconnect_0_M01_AXI_ARREADY,
s_axi_lite_arvalid => axi_interconnect_0_M01_AXI_ARVALID,
s_axi_lite_awaddr(8 downto 0) => axi_interconnect_0_M01_AXI_AWADDR(8 downto 0),
s_axi_lite_awready => axi_interconnect_0_M01_AXI_AWREADY,
s_axi_lite_awvalid => axi_interconnect_0_M01_AXI_AWVALID,
s_axi_lite_bready => axi_interconnect_0_M01_AXI_BREADY,
s_axi_lite_bresp(1 downto 0) => axi_interconnect_0_M01_AXI_BRESP(1 downto 0),
s_axi_lite_bvalid => axi_interconnect_0_M01_AXI_BVALID,
s_axi_lite_rdata(31 downto 0) => axi_interconnect_0_M01_AXI_RDATA(31 downto 0),
s_axi_lite_rready => axi_interconnect_0_M01_AXI_RREADY,
s_axi_lite_rresp(1 downto 0) => axi_interconnect_0_M01_AXI_RRESP(1 downto 0),
s_axi_lite_rvalid => axi_interconnect_0_M01_AXI_RVALID,
s_axi_lite_wdata(31 downto 0) => axi_interconnect_0_M01_AXI_WDATA(31 downto 0),
s_axi_lite_wready => axi_interconnect_0_M01_AXI_WREADY,
s_axi_lite_wvalid => axi_interconnect_0_M01_AXI_WVALID
);
proc_sys_reset_0: component block_design_proc_sys_reset_0_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_0_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => proc_sys_reset_0_interconnect_aresetn(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_0_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_0_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_0_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => processing_system7_0_FCLK_CLK0
);
proc_sys_reset_1: component block_design_proc_sys_reset_1_0
port map (
aux_reset_in => '1',
bus_struct_reset(0) => NLW_proc_sys_reset_1_bus_struct_reset_UNCONNECTED(0),
dcm_locked => '1',
ext_reset_in => processing_system7_0_FCLK_RESET0_N,
interconnect_aresetn(0) => NLW_proc_sys_reset_1_interconnect_aresetn_UNCONNECTED(0),
mb_debug_sys_rst => '0',
mb_reset => NLW_proc_sys_reset_1_mb_reset_UNCONNECTED,
peripheral_aresetn(0) => proc_sys_reset_1_peripheral_aresetn(0),
peripheral_reset(0) => NLW_proc_sys_reset_1_peripheral_reset_UNCONNECTED(0),
slowest_sync_clk => axi_dispctrl_0_PXL_CLK_O
);
processing_system7_0: component block_design_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
IRQ_F2P(0) => axi_vdma_0_mm2s_introut,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_ARADDR(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_ARBURST(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_ARCACHE(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => processing_system7_0_M_AXI_GP0_ARID(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_ARLEN(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_ARLOCK(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_ARPROT(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_ARQOS(3 downto 0),
M_AXI_GP0_ARREADY => processing_system7_0_M_AXI_GP0_ARREADY,
M_AXI_GP0_ARSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_ARSIZE(2 downto 0),
M_AXI_GP0_ARVALID => processing_system7_0_M_AXI_GP0_ARVALID,
M_AXI_GP0_AWADDR(31 downto 0) => processing_system7_0_M_AXI_GP0_AWADDR(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => processing_system7_0_M_AXI_GP0_AWBURST(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => processing_system7_0_M_AXI_GP0_AWCACHE(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => processing_system7_0_M_AXI_GP0_AWID(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => processing_system7_0_M_AXI_GP0_AWLEN(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => processing_system7_0_M_AXI_GP0_AWLOCK(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => processing_system7_0_M_AXI_GP0_AWPROT(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => processing_system7_0_M_AXI_GP0_AWQOS(3 downto 0),
M_AXI_GP0_AWREADY => processing_system7_0_M_AXI_GP0_AWREADY,
M_AXI_GP0_AWSIZE(2 downto 0) => processing_system7_0_M_AXI_GP0_AWSIZE(2 downto 0),
M_AXI_GP0_AWVALID => processing_system7_0_M_AXI_GP0_AWVALID,
M_AXI_GP0_BID(11 downto 0) => processing_system7_0_M_AXI_GP0_BID(11 downto 0),
M_AXI_GP0_BREADY => processing_system7_0_M_AXI_GP0_BREADY,
M_AXI_GP0_BRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_BRESP(1 downto 0),
M_AXI_GP0_BVALID => processing_system7_0_M_AXI_GP0_BVALID,
M_AXI_GP0_RDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_RDATA(31 downto 0),
M_AXI_GP0_RID(11 downto 0) => processing_system7_0_M_AXI_GP0_RID(11 downto 0),
M_AXI_GP0_RLAST => processing_system7_0_M_AXI_GP0_RLAST,
M_AXI_GP0_RREADY => processing_system7_0_M_AXI_GP0_RREADY,
M_AXI_GP0_RRESP(1 downto 0) => processing_system7_0_M_AXI_GP0_RRESP(1 downto 0),
M_AXI_GP0_RVALID => processing_system7_0_M_AXI_GP0_RVALID,
M_AXI_GP0_WDATA(31 downto 0) => processing_system7_0_M_AXI_GP0_WDATA(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => processing_system7_0_M_AXI_GP0_WID(11 downto 0),
M_AXI_GP0_WLAST => processing_system7_0_M_AXI_GP0_WLAST,
M_AXI_GP0_WREADY => processing_system7_0_M_AXI_GP0_WREADY,
M_AXI_GP0_WSTRB(3 downto 0) => processing_system7_0_M_AXI_GP0_WSTRB(3 downto 0),
M_AXI_GP0_WVALID => processing_system7_0_M_AXI_GP0_WVALID,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
S_AXI_HP0_ACLK => processing_system7_0_FCLK_CLK0,
S_AXI_HP0_ARADDR(31 downto 0) => axi_interconnect_1_M00_AXI_ARADDR(31 downto 0),
S_AXI_HP0_ARBURST(1 downto 0) => axi_interconnect_1_M00_AXI_ARBURST(1 downto 0),
S_AXI_HP0_ARCACHE(3 downto 0) => axi_interconnect_1_M00_AXI_ARCACHE(3 downto 0),
S_AXI_HP0_ARID(5 downto 0) => B"000000",
S_AXI_HP0_ARLEN(3 downto 0) => axi_interconnect_1_M00_AXI_ARLEN(3 downto 0),
S_AXI_HP0_ARLOCK(1 downto 0) => axi_interconnect_1_M00_AXI_ARLOCK(1 downto 0),
S_AXI_HP0_ARPROT(2 downto 0) => axi_interconnect_1_M00_AXI_ARPROT(2 downto 0),
S_AXI_HP0_ARQOS(3 downto 0) => axi_interconnect_1_M00_AXI_ARQOS(3 downto 0),
S_AXI_HP0_ARREADY => axi_interconnect_1_M00_AXI_ARREADY,
S_AXI_HP0_ARSIZE(2 downto 0) => axi_interconnect_1_M00_AXI_ARSIZE(2 downto 0),
S_AXI_HP0_ARVALID => axi_interconnect_1_M00_AXI_ARVALID,
S_AXI_HP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000",
S_AXI_HP0_AWBURST(1 downto 0) => B"00",
S_AXI_HP0_AWCACHE(3 downto 0) => B"0000",
S_AXI_HP0_AWID(5 downto 0) => B"000000",
S_AXI_HP0_AWLEN(3 downto 0) => B"0000",
S_AXI_HP0_AWLOCK(1 downto 0) => B"00",
S_AXI_HP0_AWPROT(2 downto 0) => B"000",
S_AXI_HP0_AWQOS(3 downto 0) => B"0000",
S_AXI_HP0_AWREADY => NLW_processing_system7_0_S_AXI_HP0_AWREADY_UNCONNECTED,
S_AXI_HP0_AWSIZE(2 downto 0) => B"000",
S_AXI_HP0_AWVALID => '0',
S_AXI_HP0_BID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BID_UNCONNECTED(5 downto 0),
S_AXI_HP0_BREADY => '0',
S_AXI_HP0_BRESP(1 downto 0) => NLW_processing_system7_0_S_AXI_HP0_BRESP_UNCONNECTED(1 downto 0),
S_AXI_HP0_BVALID => NLW_processing_system7_0_S_AXI_HP0_BVALID_UNCONNECTED,
S_AXI_HP0_RACOUNT(2 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RACOUNT_UNCONNECTED(2 downto 0),
S_AXI_HP0_RCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_RDATA(63 downto 0) => axi_interconnect_1_M00_AXI_RDATA(63 downto 0),
S_AXI_HP0_RDISSUECAP1_EN => '0',
S_AXI_HP0_RID(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_RID_UNCONNECTED(5 downto 0),
S_AXI_HP0_RLAST => axi_interconnect_1_M00_AXI_RLAST,
S_AXI_HP0_RREADY => axi_interconnect_1_M00_AXI_RREADY,
S_AXI_HP0_RRESP(1 downto 0) => axi_interconnect_1_M00_AXI_RRESP(1 downto 0),
S_AXI_HP0_RVALID => axi_interconnect_1_M00_AXI_RVALID,
S_AXI_HP0_WACOUNT(5 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WACOUNT_UNCONNECTED(5 downto 0),
S_AXI_HP0_WCOUNT(7 downto 0) => NLW_processing_system7_0_S_AXI_HP0_WCOUNT_UNCONNECTED(7 downto 0),
S_AXI_HP0_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000",
S_AXI_HP0_WID(5 downto 0) => B"000000",
S_AXI_HP0_WLAST => '0',
S_AXI_HP0_WREADY => NLW_processing_system7_0_S_AXI_HP0_WREADY_UNCONNECTED,
S_AXI_HP0_WRISSUECAP1_EN => '0',
S_AXI_HP0_WSTRB(7 downto 0) => B"00000000",
S_AXI_HP0_WVALID => '0'
);
xlconstant_0: component block_design_xlconstant_0_0
port map (
dout(5 downto 0) => xlconstant_0_dout(5 downto 0)
);
end STRUCTURE;
|
-- USB target controller
constant CFG_USBTGT : integer := CONFIG_USBTGT;
|
-- USB target controller
constant CFG_USBTGT : integer := CONFIG_USBTGT;
|
-- $Id: ibdr_pc11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_pc11 - syn
-- Description: ibus dev(rem): PC11
--
-- Dependencies: -
-- Test bench: xxdp: zpcae0
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 26 97 0 57 s 6.0
-- 2009-06-28 230 10.1.03 K39 xc3s1000-4 25 92 0 54 s 4.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-27 1140 1.4.2 set rbuf.[rp]size0
-- 2019-04-24 1137 1.4.1 add rcsr.ir,ique,iack and pcsr.ir fields (rem)
-- 2019-04-06 1126 1.4 for pc11_buf compat: pbuf.pval in bit 15 and 8;
-- move rbusy reporting from pbuf to rbuf register
-- 2013-05-04 515 1.3 BUGFIX: r.rbuf was immediately cleared ! Was broken
-- since ibus V2 update, never tested afterwards...
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-06-28 230 1.0 prdy now inits to '1'; setting err bit in csr now
-- causes interrupt, if enabled; validated with zpcae0
-- 2009-06-01 221 0.9 Initial version (untested)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_pc11 is -- ibus dev(rem): PC11
-- fixed address: 177550
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_PTR : out slbit; -- interrupt request, reader
EI_REQ_PTP : out slbit; -- interrupt request, punch
EI_ACK_PTR : in slbit; -- interrupt acknowledge, reader
EI_ACK_PTP : in slbit -- interrupt acknowledge, punch
);
end ibdr_pc11;
architecture syn of ibdr_pc11 is
constant ibaddr_pc11 : slv16 := slv(to_unsigned(8#177550#,16));
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_pcsr : slv2 := "10"; -- pcsr address offset
constant ibaddr_pbuf : slv2 := "11"; -- pbuf address offset
constant rcsr_ibf_rerr : integer := 15;
constant rcsr_ibf_rbusy : integer := 11;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rcsr_ibf_ique : integer := 3;
constant rcsr_ibf_iack : integer := 2;
constant rcsr_ibf_renb : integer := 0;
constant rbuf_ibf_rbusy : integer := 15;
constant rbuf_ibf_rsize0: integer := 8;
constant rbuf_ibf_psize0: integer := 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
constant pcsr_ibf_perr : integer := 15;
constant pcsr_ibf_prdy : integer := 7;
constant pcsr_ibf_pie : integer := 6;
constant pcsr_ibf_pir : integer := 5;
constant pbuf_ibf_pval : integer := 15;
constant pbuf_ibf_pval8 : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rerr : slbit; -- rcsr: reader error
rbusy : slbit; -- rcsr: reader busy
rdone : slbit; -- rcsr: reader done
rie : slbit; -- rcsr: reader interrupt enable
rbuf : slv8; -- rbuf:
rintreq : slbit; -- ptr interrupt request
rique : slbit; -- ptr interrupt queued (req set)
riack : slbit; -- ptr interrupt acknowledged
perr : slbit; -- pcsr: punch error
prdy : slbit; -- pcsr: punch ready
pie : slbit; -- pcsr: punch interrupt enable
pbuf : slv8; -- pbuf:
pintreq : slbit; -- ptp interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
'1', -- rerr (init=1!)
'0','0','0', -- rbusy,rdone,rie
(others=>'0'), -- rbuf
'0','0','0', -- rintreq,rique,riack
'1', -- perr (init=1!)
'1', -- prdy (init=1!)
'0', -- pie
(others=>'0'), -- pbuf
'0' -- pintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
begin
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then -- BRESET is 1 for system and ibus reset
R_REGS <= regs_init; --
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rerr <= N_REGS.rerr; -- don't reset RERR flag
R_REGS.perr <= N_REGS.perr; -- don't reset PERR flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_PTR, EI_ACK_PTP)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=ibaddr_pc11(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- reader control status -----
idout(rcsr_ibf_rerr) := r.rerr;
idout(rcsr_ibf_rbusy) := r.rbusy;
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then-- set IE to 1
if r.rie = '0' and -- IE 0->1 transition
IB_MREQ.din(rcsr_ibf_renb)='0' and -- when RENB not set
(r.rerr='1' or r.rdone='1') then -- but err or done set
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
else -- set IE to 0
n.rintreq := '0'; -- cancel interrupts
end if;
if IB_MREQ.din(rcsr_ibf_renb) = '1' then -- set RENB
if r.rerr = '0' then -- if not in error state
n.rbusy := '1'; -- set busy
n.rdone := '0'; -- clear done
n.rbuf := (others=>'0'); -- clear buffer
n.rintreq := '0'; -- cancel interrupt
n.rique := '0'; -- and que flag
n.riack := '0'; -- and ack flag
ilam := '1'; -- rri lam
else -- if in error state
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rir) := r.rintreq;
idout(rcsr_ibf_ique) := r.rique;
idout(rcsr_ibf_iack) := r.riack;
if ibw1 = '1' then
n.rerr := IB_MREQ.din(rcsr_ibf_rerr); -- set ERR bit
if IB_MREQ.din(rcsr_ibf_rerr)='1' -- if 0->1 transition
and r.rerr='0' then
n.rbusy := '0'; -- clear busy
n.rdone := '0'; -- clear done
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
end if;
when ibaddr_rbuf => -- RBUF -- reader data buffer --------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := r.rbuf;
if ibreq = '1' then -- !! PC11 is unusual !!
n.rdone := '0'; -- *any* read or write will clear done
n.rbuf := (others=>'0'); -- and the reader buffer
n.rintreq := '0'; -- also interrupt is canceled
end if;
else -- rri ---------------------
idout(rbuf_ibf_rbusy) := r.rbusy;
idout(rbuf_ibf_rsize0) := r.rdone; -- rbuf occupied when rdone=1
idout(rbuf_ibf_psize0) := not r.prdy; -- pbuf empty when prdy=1
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(rbuf_ibf_data);
n.rbusy := '0';
n.rdone := '1';
if r.rie = '1' then -- if interrupts on
n.rintreq := '1'; -- request interrupt
n.rique := '1'; -- and set que flag
end if;
end if;
end if;
when ibaddr_pcsr => -- PCSR -- punch control status ------
idout(pcsr_ibf_perr) := r.perr;
idout(pcsr_ibf_prdy) := r.prdy;
idout(pcsr_ibf_pie) := r.pie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.pie := IB_MREQ.din(pcsr_ibf_pie);
if IB_MREQ.din(pcsr_ibf_pie) = '1' then-- set IE to 1
if r.pie='0' and -- IE 0->1 transition
(r.perr='1' or r.prdy='1') then -- but err or done set
n.pintreq := '1'; -- request interrupt
end if;
else -- set IE to 0
n.pintreq := '0'; -- cancel interrupts
end if;
end if;
else -- rri ---------------------
idout(pcsr_ibf_pir) := r.pintreq;
if ibw1 = '1' then
n.perr := IB_MREQ.din(pcsr_ibf_perr); -- set ERR bit
if IB_MREQ.din(pcsr_ibf_perr)='1' -- if 0->1 transition
and r.perr='0' then
n.prdy := '1'; -- set ready
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
end if;
when ibaddr_pbuf => -- PBUF -- punch data buffer ---------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
if r.perr = '0' then -- if not in error state
n.pbuf := IB_MREQ.din(n.pbuf'range);
n.prdy := '0'; -- clear ready
n.pintreq := '0'; -- cancel interrupts
ilam := '1'; -- rri lam
else -- if in error state
if r.pie = '1' then -- if interrupts on
n.pintreq := '1'; -- request interrupt
end if;
end if;
end if;
else -- rri ---------------------
idout(r.pbuf'range) := r.pbuf;
idout(pbuf_ibf_pval) := not r.prdy;
idout(pbuf_ibf_pval8) := not r.prdy;
if ibrd = '1' then
n.prdy := '1';
if r.pie = '1' then
n.pintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_PTR = '1' then
n.rintreq := '0';
n.riack := '1';
end if;
if EI_ACK_PTP = '1' then
n.pintreq := '0';
end if;
N_REGS <= n;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_PTR <= r.rintreq;
EI_REQ_PTP <= r.pintreq;
end process proc_next;
end syn;
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
entity parameterized_or_gate is
generic
(
bits : integer := 9
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic := '0'
);
end parameterized_or_gate;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
architecture parameterized_or_gate_arch of parameterized_or_gate is
--SIGNALS
signal im : std_logic_vector(2*ceil2(bits)-2 downto 0) := (others=>'0');
begin
--connect inputs
connect_input : for j in 0 to bits-1 generate
im(j) <= A(j);
end generate;--inputs
blank_inputs : if(ceil2(bits)/=bits) generate
connect_low : for k in bits to ceil2(bits)-1 generate
im(k) <= '0';
end generate;--connect low state
end generate;--zeros on input
--generate tree of gates
or_gates:for g in 0 to ceil2(bits)-2 generate
im(g+ceil2(bits)) <= im(g*2) OR im(g*2+1);
end generate; --g
--connect output
O <= im(im'high);
end parameterized_or_gate_arch; -- end of architecture
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
entity parameterized_or_gate is
generic
(
bits : integer := 9
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic := '0'
);
end parameterized_or_gate;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
architecture parameterized_or_gate_arch of parameterized_or_gate is
--SIGNALS
signal im : std_logic_vector(2*ceil2(bits)-2 downto 0) := (others=>'0');
begin
--connect inputs
connect_input : for j in 0 to bits-1 generate
im(j) <= A(j);
end generate;--inputs
blank_inputs : if(ceil2(bits)/=bits) generate
connect_low : for k in bits to ceil2(bits)-1 generate
im(k) <= '0';
end generate;--connect low state
end generate;--zeros on input
--generate tree of gates
or_gates:for g in 0 to ceil2(bits)-2 generate
im(g+ceil2(bits)) <= im(g*2) OR im(g*2+1);
end generate; --g
--connect output
O <= im(im'high);
end parameterized_or_gate_arch; -- end of architecture
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
entity parameterized_or_gate is
generic
(
bits : integer := 9
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic := '0'
);
end parameterized_or_gate;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
architecture parameterized_or_gate_arch of parameterized_or_gate is
--SIGNALS
signal im : std_logic_vector(2*ceil2(bits)-2 downto 0) := (others=>'0');
begin
--connect inputs
connect_input : for j in 0 to bits-1 generate
im(j) <= A(j);
end generate;--inputs
blank_inputs : if(ceil2(bits)/=bits) generate
connect_low : for k in bits to ceil2(bits)-1 generate
im(k) <= '0';
end generate;--connect low state
end generate;--zeros on input
--generate tree of gates
or_gates:for g in 0 to ceil2(bits)-2 generate
im(g+ceil2(bits)) <= im(g*2) OR im(g*2+1);
end generate; --g
--connect output
O <= im(im'high);
end parameterized_or_gate_arch; -- end of architecture
|
--======================================================--
-- --
-- NORTHEASTERN UNIVERSITY --
-- DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING --
-- Reconfigurable & GPU Computing Laboratory --
-- --
-- AUTHOR | Pavle Belanovic --
-- -------------+------------------------------------ --
-- DATE | 20 June 2002 --
-- -------------+------------------------------------ --
-- REVISED BY | Haiqian Yu --
-- -------------+------------------------------------ --
-- DATE | 18 Jan. 2003 --
-- -------------+------------------------------------ --
-- REVISED BY | Jainik Kathiara --
-- -------------+------------------------------------ --
-- DATE | 21 Sept. 2010 --
-- -------------------------------------------------- --
-- REVISED BY | Xin Fang --
-- -------------------------------------------------- --
-- DATE | 25 Oct. 2012 --
--======================================================--
--******************************************************************************--
-- --
-- Copyright (C) 2014 --
-- --
-- This program is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU General Public License --
-- as published by the Free Software Foundation; either version 3 --
-- of the License, or (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see<http://www.gnu.org/licenses/>. --
-- --
--******************************************************************************--
--======================================================--
-- LIBRARIES --
--======================================================--
-- IEEE Libraries --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
-- float
library fp_lib;
use fp_lib.float_pkg.all;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
entity parameterized_or_gate is
generic
(
bits : integer := 9
);
port
(
--inputs
A : in std_logic_vector(bits-1 downto 0);
--outputs
O : out std_logic := '0'
);
end parameterized_or_gate;
----------------------------------------------------------
-- Parameterized OR gate --
----------------------------------------------------------
architecture parameterized_or_gate_arch of parameterized_or_gate is
--SIGNALS
signal im : std_logic_vector(2*ceil2(bits)-2 downto 0) := (others=>'0');
begin
--connect inputs
connect_input : for j in 0 to bits-1 generate
im(j) <= A(j);
end generate;--inputs
blank_inputs : if(ceil2(bits)/=bits) generate
connect_low : for k in bits to ceil2(bits)-1 generate
im(k) <= '0';
end generate;--connect low state
end generate;--zeros on input
--generate tree of gates
or_gates:for g in 0 to ceil2(bits)-2 generate
im(g+ceil2(bits)) <= im(g*2) OR im(g*2+1);
end generate; --g
--connect output
O <= im(im'high);
end parameterized_or_gate_arch; -- end of architecture
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:15:04 09/28/2016
-- Design Name:
-- Module Name: ALU - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ALU is
Port ( alu_input_1 : IN STD_LOGIC_VECTOR (7 downto 0); -- first ALU input ( 8 bit)
alu_input_2 : IN STD_LOGIC_VECTOR (7 downto 0); -- second ALU input ( 8 bit)
alu_output : OUT STD_LOGIC_VECTOR (7 downto 0); -- output signal of ALU ( 8 bit)
alu_command : IN STD_LOGIC_VECTOR (7 downto 0); -- command for ALU
busy : INOUT STD_LOGIC; -- one bit signal that tells us if ALU is busy or not
clk : IN STD_LOGIC -- clock input
);
end ALU;
architecture Behavioral of ALU is
begin
CALCULATE_RESULT : process(clk)
begin
if clk = '1' and clk'event then
if alu_command = "00000001" then
busy <= '1';
alu_output <= alu_input_1 + alu_input_2;-- addition of input
busy <= '0';
elsif alu_command = "00000010" then
busy <= '1';
alu_output <= alu_input_1 - alu_input_2; -- substraction of input signals
busy <= '0';
elsif alu_command = "00000011" then
busy <= '1';
alu_output <= alu_input_1 and alu_input_2; -- AND operation
busy <= '0';
elsif alu_command = "00000100" then
busy <= '1';
alu_output <= alu_input_1 or alu_input_2; -- OR operation
busy <= '0';
elsif alu_command = "00000101" then
busy <= '1';
alu_output <= alu_input_1 xor alu_input_2; -- XOR operation
busy <= '0';
elsif alu_command = "00000110" then
busy <= '1';
alu_output <= not alu_input_1; -- NOT operation
busy <= '0';
elsif alu_command = "00000111" then
busy <= '1';
alu_output <= std_logic_vector(unsigned(alu_input_1) srl 1); --shift right
busy <= '0';
elsif alu_command = "00001000" then
busy <= '1';
alu_output <= alu_input_1 + alu_input_1; --shift left
busy <= '0';
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2958.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02958ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end --Failure here
END c02s02b00x00p02n01i02958ent;
ARCHITECTURE c02s02b00x00p02n01i02958arch OF c02s02b00x00p02n01i02958ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02958 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2958.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02958ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end --Failure here
END c02s02b00x00p02n01i02958ent;
ARCHITECTURE c02s02b00x00p02n01i02958arch OF c02s02b00x00p02n01i02958ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02958 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02958arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2958.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p02n01i02958ent IS
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer);
procedure PX (signal I1: in Bit; signal I2 : out Bit; signal I3 : inout Integer) is
begin
assert (I1 /= '1')
report "No failure on test" ;
assert (I3 /= 5)
report "No failure on test" ;
end --Failure here
END c02s02b00x00p02n01i02958ent;
ARCHITECTURE c02s02b00x00p02n01i02958arch OF c02s02b00x00p02n01i02958ent IS
signal S1 : Bit := '1';
signal S2 : Integer := 5;
signal S3 : Bit;
BEGIN
TESTING: PROCESS
BEGIN
PX(S1,S3,S2);
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c02s02b00x00p02n01i02958 - Missing semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p02n01i02958arch;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of ent_ad
--
-- Generated
-- by: wig
-- on: Mon Jul 18 16:07:02 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -sheet HIER=HIER_VHDL -strip -nodelta ../../verilog.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ad-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ent_ad-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of ent_ad
--
architecture rtl of ent_ad is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Copyright (c) 2009 Alan Daly. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_OlimexModVGA.vhd
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_OlimexModVGA
--Device: spartan3A
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_OlimexModVGA is
port (clk_25M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ERSTn : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
CE1 : out std_logic;
RAMWRn : out std_logic;
RAMOEn : out std_logic;
RamA : out std_logic_vector (15 downto 0);
RamD : inout std_logic_vector (15 downto 0);
audiol : out std_logic;
audioR : out std_logic;
FLASH_CS : out std_logic; -- Active low FLASH chip select
FLASH_SI : out std_logic; -- Serial output to FLASH chip SI pin
FLASH_CK : out std_logic; -- FLASH clock
FLASH_SO : in std_logic; -- Serial input from FLASH chip SO
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic);
end AtomFpga_OlimexModVGA;
architecture behavioral of AtomFpga_OlimexModVGA is
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal Phi2 : std_logic;
signal powerup_reset_n : std_logic;
signal hard_reset_n : std_logic;
signal reset_counter : std_logic_vector(15 downto 0);
signal RAM_A : std_logic_vector(18 downto 0);
signal RAM_Din : std_logic_vector(7 downto 0);
signal RAM_Dout : std_logic_vector(7 downto 0);
signal RAM_nWE : std_logic;
signal RAM_nOE : std_logic;
signal RAM_nCS : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector(18 downto 0);
signal ExternDin : std_logic_vector(7 downto 0);
signal ExternDout : std_logic_vector(7 downto 0);
-----------------------------------------------
-- Bootstrap ROM Image from SPI FLASH into SRAM
-----------------------------------------------
-- TODO: The user_ values below are a hack
-- specifying 030000/008000 did not work, although it should!
-- there seems to be something different about the way the AT45DB041D is addressed
-- but that's not obvious in the data sheet
-- https://www.adestotech.com/wp-content/uploads/doc3595.pdf
-- start address of user data in FLASH as obtained from bitmerge.py
constant user_address : std_logic_vector(23 downto 0) := x"000000";
-- lenth of user data in FLASH = 32KB (8x 4KB ROM) images
constant user_length : std_logic_vector(23 downto 0) := x"038000";
-- high when FLASH is being copied to SRAM, can be used by user as active high reset
signal bootstrap_busy : std_logic;
begin
inst_dcm2 : entity work.dcm2 port map(
CLKIN_IN => clk_25M00,
CLK0_OUT => clock_25,
CLKFX_OUT => clock_16);
inst_dcm3 : entity work.dcm3 port map (
CLKIN_IN => clock_16,
CLK0_OUT => clock_32,
CLK0_OUT1 => open,
CLK2X_OUT => open);
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => true,
CImplAtoMMC2 => false,
CImplGraphicsExt => false,
CImplSoftChar => false,
CImplSID => false,
CImplVGA80x40 => false,
CImplHWScrolling => false,
CImplMouse => false,
CImplUart => false,
CImplDoubleVideo => false,
CImplRamRomNone => true,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clock_25,
clk_main => clock_16,
clk_avr => clock_16,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => open,
ps2_mouse_data => open,
powerup_reset_n => powerup_reset_n,
ext_reset_n => hard_reset_n,
int_reset_n => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
Phi2 => Phi2,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => '1',
uart_TxD => open,
avr_RxD => '1',
avr_TxD => open,
LED1 => open,
LED2 => open,
charSet => '0'
);
--------------------------------------------------------
-- Power Up Reset Generation
--------------------------------------------------------
-- On the Duo the external reset signal is not asserted on power up
-- This internal counter forces power up reset to happen
-- This is needed by the GODIL to initialize some of the registers
ResetProcess : process (clock_16)
begin
if rising_edge(clock_16) then
if (reset_counter(reset_counter'high) = '0') then
reset_counter <= reset_counter + 1;
end if;
powerup_reset_n <= ERSTn and reset_counter(reset_counter'high);
end if;
end process;
-- extend the version seen by the core to hold the 6502 reset during bootstrap
hard_reset_n <= powerup_reset_n and not bootstrap_busy;
--------------------------------------------------------
-- BOOTSTRAP SPI FLASH to SRAM
--------------------------------------------------------
inst_bootstrap: entity work.bootstrap
generic map (
gated_write => false,
user_length => user_length
)
port map(
clock => clock_16,
powerup_reset_n => powerup_reset_n,
bootstrap_busy => bootstrap_busy,
user_address => user_address,
RAM_nOE => RAM_nOE,
RAM_nWE => RAM_nWE,
RAM_nCS => RAM_nCS,
RAM_A => RAM_A,
RAM_Din => RAM_Din,
RAM_Dout => RAM_Dout,
SRAM_nOE => RamOEn,
SRAM_nWE => RamWRn,
SRAM_nCS => CE1,
SRAM_A(20 downto 16) => open,
SRAM_A(15 downto 0) => RamA,
SRAM_D => RamD(7 downto 0),
FLASH_CS => FLASH_CS,
FLASH_SI => FLASH_SI,
FLASH_CK => FLASH_CK,
FLASH_SO => FLASH_SO
);
RamD(15 downto 8) <= (others => 'Z');
MemProcess : process (clock_16)
begin
if rising_edge(clock_16) then
RAM_A <= ExternA xor ("000" & x"8000");
RAM_nCS <= not ExternCE;
RAM_nOE <= not ((not ExternWE) and ExternCE);
RAM_nWE <= not (ExternWE and ExternCE and phi2);
RAM_Din <= ExternDin;
end if;
end process;
ExternDout <= RAM_Dout;
end behavioral;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0_8;
USE proc_sys_reset_v5_0_8.proc_sys_reset;
ENTITY zc702_proc_sys_reset_1_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END zc702_proc_sys_reset_1_0;
ARCHITECTURE zc702_proc_sys_reset_1_0_arch OF zc702_proc_sys_reset_1_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF zc702_proc_sys_reset_1_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END zc702_proc_sys_reset_1_0_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2298.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02298ent IS
END c07s02b06x00p35n01i02298ent;
ARCHITECTURE c07s02b06x00p35n01i02298arch OF c07s02b06x00p35n01i02298ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 ns / 1000.0) < 1 ns);
assert ((1 ps / 1000.0) < 1 ps);
assert ((1 fs / 1000.0) < 1 fs);
wait for 5 fs;
assert NOT( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***PASSED TEST: c07s02b06x00p35n01i02298"
severity NOTE;
assert ( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***FAILED TEST: c07s02b06x00p35n01i02298 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02298arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2298.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02298ent IS
END c07s02b06x00p35n01i02298ent;
ARCHITECTURE c07s02b06x00p35n01i02298arch OF c07s02b06x00p35n01i02298ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 ns / 1000.0) < 1 ns);
assert ((1 ps / 1000.0) < 1 ps);
assert ((1 fs / 1000.0) < 1 fs);
wait for 5 fs;
assert NOT( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***PASSED TEST: c07s02b06x00p35n01i02298"
severity NOTE;
assert ( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***FAILED TEST: c07s02b06x00p35n01i02298 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02298arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2298.vhd,v 1.2 2001-10-26 16:29:47 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b06x00p35n01i02298ent IS
END c07s02b06x00p35n01i02298ent;
ARCHITECTURE c07s02b06x00p35n01i02298arch OF c07s02b06x00p35n01i02298ent IS
BEGIN
TESTING: PROCESS
BEGIN
-- Test the predefined type TIME in this respect.
assert ((1 ns / 1000.0) < 1 ns);
assert ((1 ps / 1000.0) < 1 ps);
assert ((1 fs / 1000.0) < 1 fs);
wait for 5 fs;
assert NOT( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***PASSED TEST: c07s02b06x00p35n01i02298"
severity NOTE;
assert ( ((1 ns / 1000.0) < 1 ns) and
((1 ps / 1000.0) < 1 ps) and
((1 fs / 1000.0) < 1 fs))
report "***FAILED TEST: c07s02b06x00p35n01i02298 - Division of an predefined physical type by a real type test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b06x00p35n01i02298arch;
|
-- Taken from https://github.com/universal-ctags/ctags/issues/2678
-- commented by @pidgeon777.
entity ENTITY_A is
generic (
GENERIC_C : integer := value;
);
port (
PORT_C : in std_logic
);
end entity;
entity ENTITY_B is
generic (
GENERIC_C : integer := value;
);
port (
PORT_C : in std_logic
);
end entity;
|
-- Taken from https://github.com/universal-ctags/ctags/issues/2678
-- commented by @pidgeon777.
entity ENTITY_A is
generic (
GENERIC_C : integer := value;
);
port (
PORT_C : in std_logic
);
end entity;
entity ENTITY_B is
generic (
GENERIC_C : integer := value;
);
port (
PORT_C : in std_logic
);
end entity;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad Behrad Niazmand
library ieee;
use ieee.std_logic_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.ALL;
entity LBDR is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8
);
port ( reset: in std_logic;
clk: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
cur_addr_y, cur_addr_x: in std_logic_vector(6 downto 0);
dst_addr_y, dst_addr_x: in std_logic_vector(6 downto 0);
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic
);
end LBDR;
architecture behavior of LBDR is
signal Cx: std_logic_vector(3 downto 0);
signal Rxy: std_logic_vector(7 downto 0);
signal N1, E1, W1, S1 :std_logic :='0';
signal Req_N_in, Req_E_in, Req_W_in, Req_S_in, Req_L_in: std_logic;
signal Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF: std_logic;
signal grants: std_logic;
begin
grants <= grant_N or grant_E or grant_W or grant_S or grant_L;
Cx <= std_logic_vector(to_unsigned(Cx_rst, Cx'length));
Rxy <= std_logic_vector(to_unsigned(Rxy_rst, Rxy'length));
N1 <= '1' when dst_addr_y < cur_addr_y else '0';
E1 <= '1' when cur_addr_x < dst_addr_x else '0';
W1 <= '1' when dst_addr_x < cur_addr_x else '0';
S1 <= '1' when cur_addr_y < dst_addr_y else '0';
process(clk, reset)
begin
if reset = '0' then
Req_N_FF <= '0';
Req_E_FF <= '0';
Req_W_FF <= '0';
Req_S_FF <= '0';
Req_L_FF <= '0';
elsif clk'event and clk = '1' then
Req_N_FF <= Req_N_in;
Req_E_FF <= Req_E_in;
Req_W_FF <= Req_W_in;
Req_S_FF <= Req_S_in;
Req_L_FF <= Req_L_in;
end if;
end process;
-- The combionational part
Req_N <= Req_N_FF;
Req_E <= Req_E_FF;
Req_W <= Req_W_FF;
Req_S <= Req_S_FF;
Req_L <= Req_L_FF;
process(N1, E1, W1, S1, Rxy, Cx, flit_type, empty, Req_N_FF, Req_E_FF, Req_W_FF, Req_S_FF, Req_L_FF, grants) begin
if flit_type = "001" and empty = '0' then
Req_N_in <= ((N1 and not E1 and not W1) or (N1 and E1 and Rxy(0)) or (N1 and W1 and Rxy(1))) and Cx(0);
Req_E_in <= ((E1 and not N1 and not S1) or (E1 and N1 and Rxy(2)) or (E1 and S1 and Rxy(3))) and Cx(1);
Req_W_in <= ((W1 and not N1 and not S1) or (W1 and N1 and Rxy(4)) or (W1 and S1 and Rxy(5))) and Cx(2);
Req_S_in <= ((S1 and not E1 and not W1) or (S1 and E1 and Rxy(6)) or (S1 and W1 and Rxy(7))) and Cx(3);
Req_L_in <= not N1 and not E1 and not W1 and not S1;
elsif flit_type = "100" and empty = '0' and grants = '1' then
Req_N_in <= '0';
Req_E_in <= '0';
Req_W_in <= '0';
Req_S_in <= '0';
Req_L_in <= '0';
else
Req_N_in <= Req_N_FF;
Req_E_in <= Req_E_FF;
Req_W_in <= Req_W_FF;
Req_S_in <= Req_S_FF;
Req_L_in <= Req_L_FF;
end if;
end process;
END; |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:30:55 02/20/2013
-- Design Name:
-- Module Name: /home/frank/testproject/mips_proc_tb.vhd
-- Project Name: testproject
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: mips_proc
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
entity mips_proc_tb is
end mips_proc_tb;
architecture behavior of mips_proc_tb is
-- Component Declaration for the Unit Under Test (UUT)
component mips_proc
port(
clk : in std_logic;
reset : in std_logic;
instruction : out std_logic_vector(31 downto 0);
pca_o : out std_logic_vector(31 downto 0)
);
end component;
--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal instruction : std_logic_vector(31 downto 0);
signal pca_o : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : mips_proc port map (
clk => clk,
reset => reset,
instruction => instruction,
pca_o => pca_o
);
-- Clock process definitions
clk_process : process
begin
clk <= '1';
wait for clk_period/2;
clk <= '0';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 100 ns;
reset <= '0';
wait for 41 ns;
reset <= '1';
wait for 4 ns;
reset <= '0';
-- insert stimulus here
wait;
end process;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_tx_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fifo_tx_pkg.ALL;
ENTITY fifo_tx_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fifo_tx_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 50 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fifo_tx_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 19:58:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 44.625000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 75.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 19:58:38 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top system_clk_wiz_0_0 -prefix
-- system_clk_wiz_0_0_ system_clk_wiz_0_0_sim_netlist.vhdl
-- Design : system_clk_wiz_0_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
end system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz;
architecture STRUCTURE of system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz is
signal clk_in1_system_clk_wiz_0_0 : STD_LOGIC;
signal clk_out1_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_buf_system_clk_wiz_0_0 : STD_LOGIC;
signal clkfbout_system_clk_wiz_0_0 : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_system_clk_wiz_0_0,
O => clkfbout_buf_system_clk_wiz_0_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_system_clk_wiz_0_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_system_clk_wiz_0_0,
O => clk_out1
);
mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT_F => 44.625000,
CLKFBOUT_PHASE => 0.000000,
CLKFBOUT_USE_FINE_PS => false,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE_F => 75.000000,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT0_USE_FINE_PS => false,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT1_USE_FINE_PS => false,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT2_USE_FINE_PS => false,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT3_USE_FINE_PS => false,
CLKOUT4_CASCADE => false,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT4_USE_FINE_PS => false,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
CLKOUT5_USE_FINE_PS => false,
CLKOUT6_DIVIDE => 1,
CLKOUT6_DUTY_CYCLE => 0.500000,
CLKOUT6_PHASE => 0.000000,
CLKOUT6_USE_FINE_PS => false,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 5,
IS_CLKINSEL_INVERTED => '0',
IS_PSEN_INVERTED => '0',
IS_PSINCDEC_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
SS_EN => "FALSE",
SS_MODE => "CENTER_HIGH",
SS_MOD_PERIOD => 10000,
STARTUP_WAIT => false
)
port map (
CLKFBIN => clkfbout_buf_system_clk_wiz_0_0,
CLKFBOUT => clkfbout_system_clk_wiz_0_0,
CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
CLKIN1 => clk_in1_system_clk_wiz_0_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
CLKOUT0 => clk_out1_system_clk_wiz_0_0,
CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
DADDR(6 downto 0) => B"0000000",
DCLK => '0',
DEN => '0',
DI(15 downto 0) => B"0000000000000000",
DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => locked,
PSCLK => '0',
PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
PSEN => '0',
PSINCDEC => '0',
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_clk_wiz_0_0 is
port (
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC;
clk_in1 : in STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_clk_wiz_0_0 : entity is true;
end system_clk_wiz_0_0;
architecture STRUCTURE of system_clk_wiz_0_0 is
begin
inst: entity work.system_clk_wiz_0_0_system_clk_wiz_0_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
locked => locked
);
end STRUCTURE;
|
library ieee;
use ieee.std_logic_1164.all;
PACKAGE resources IS
constant base_tempo : time:= 100 ns ;--500; --individuos
constant matriz_i : natural := 3 ; -- linhas (impar)
constant matriz_j : natural := 3 ; -- colunas
constant number_of_vector: integer:= 16 ;--500; --quantidade de estimulos
constant individuos: integer:= 1000 ;--500; --individuos
constant response_file_rpuf1: string := "./data/PUF_Response/CRPUF1_response_PUF_"&integer'image(matriz_i)&"x"&integer'image(matriz_j)&"_bits_"&integer'image(individuos)&"_pufs.txt";
constant response_file_rpuf2: string := "./data/PUF_Response/CRPUF2_response_PUF_"&integer'image(matriz_i)&"x"&integer'image(matriz_j)&"_bits_"&integer'image(individuos)&"_pufs.txt";
constant response_file_raw: string := "./data/PUF_Response/RAW_response_PUF_"&integer'image(matriz_i)&"x"&integer'image(matriz_j)&"_bits_"&integer'image(individuos)&"_pufs.txt";
END resources;
|
architecture RTL of FIFO is
begin
-- These are passing
a <= b; -- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1'; -- Comment 4
-- Failing variations
a <= b; -- Comment 1
a <= when c = '0' else '1'; -- Comment 2
a <= b; -- Comment 3
a <= when c = '0' else '1'; -- Comment 4
process -- comment process
begin -- comment begin
a <= b; -- Comment
b <= c; -- Comment
c <= d; -- Comment
end process; -- comment end process
x <= z when b = c else -- comment a
y when c = d else -- comment b
x when d = e; -- comment c
z <= w when e = f else -- comment d
x when f = g else -- comment e
z; -- comment f
INST : INST_1 -- instantiation comment
port map ( -- port map comment
a => '0' -- port comment
); -- end port map comment
assert True -- assert comment
report "Hello" -- report comment
severity Warning; -- severity comment
procedure_call( -- procedure call comment
a => b, -- procedure call parameter 1
c => d -- procedure call parameter 2
); -- procedure call end parenthesis
-- Block
block_label : block -- Block comment
begin -- block begin comment
a <= b; -- comment z
c <= d; -- comment y
e <= f; -- comment x
end block; -- end block comment
-- Generate statements
for_generate_label : for i in 0 to 200 generate -- for generate comment
ab <= bc; -- comment zz
ac <= ad; -- coment za
ae <= af; -- comment ab
end generate; -- end for generate label
a <= b; -- comment
c <= d; -- comment
-- comment line
s <= a;
-- A
s <= b; -- B
s <= cc; -- C
end architecture RTL;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC | | PHY I/F
-- | | | | SUPPORT LEVEL | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- RGMII Interface
--------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- RGMII Inband Status Registers
----------------------------------
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end tri_mode_ethernet_mac_0_fifo_block;
architecture wrapper of tri_mode_ethernet_mac_0_fifo_block is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support
port(
gtx_clk : in std_logic;
gtx_clk_out : out std_logic;
gtx_clk90_out : out std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tready : out std_logic;
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
signal rx_mac_aclk_int : std_logic; -- MAC Rx clock
signal tx_mac_aclk_int : std_logic; -- MAC Tx clock
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_mac_aclk <= rx_mac_aclk_int;
tx_mac_aclk <= tx_mac_aclk_int;
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
trimac_sup_block : tri_mode_ethernet_mac_0_support
port map(
gtx_clk => gtx_clk,
gtx_clk_out => open,
gtx_clk90_out => open,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_enable => open,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk_int,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Client Transmitter Interface
tx_enable => open,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk_int,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- speed control
speedis100 => open,
speedis10100 => open,
-- RGMII Interface
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI lite interface
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => open
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => rx_mac_aclk_int,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => tx_mac_aclk_int,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_mac_aclk => tx_mac_aclk_int,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser(0),
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_mac_aclk => rx_mac_aclk_int,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
|
--------------------------------------------------------------------------------
-- File : tri_mode_ethernet_mac_0_fifo_block.v
-- Author : Xilinx Inc.
-- -----------------------------------------------------------------------------
-- (c) Copyright 2004-2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- -----------------------------------------------------------------------------
-- Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode
-- Ethernet MAC core. This wrapper enhances the standard MAC core
-- with an example FIFO. The interface to this FIFO is
-- designed to the AXI-S specification.
-- Please refer to core documentation for
-- additional FIFO and AXI-S information.
--
-- _________________________________________________________
-- | |
-- | FIFO BLOCK LEVEL WRAPPER |
-- | |
-- | _____________________ ______________________ |
-- | | _________________ | | | |
-- | | | | | | | |
-- -------->| | TX AXI FIFO | |---->| Tx Tx |--------->
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | | | | | |
-- AXI | | 10/100/1G | | TRI-MODE ETHERNET | |
-- Stream | | ETHERNET FIFO | | MAC | | PHY I/F
-- | | | | SUPPORT LEVEL | |
-- | | _________________ | | | |
-- | | | | | | | |
-- <--------| | RX AXI FIFO | |<----| Rx Rx |<---------
-- | | | | | | AXI-S PHY | |
-- | | |_________________| | | I/F I/F | |
-- | |_____________________| |______________________| |
-- | |
-- |_________________________________________________________|
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- The module declaration for the fifo block level wrapper.
--------------------------------------------------------------------------------
entity tri_mode_ethernet_mac_0_fifo_block is
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- RGMII Interface
--------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
-- RGMII Inband Status Registers
----------------------------------
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic
);
end tri_mode_ethernet_mac_0_fifo_block;
architecture wrapper of tri_mode_ethernet_mac_0_fifo_block is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of wrapper : architecture is "yes";
------------------------------------------------------------------------------
-- Component declaration for the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_support
port(
gtx_clk : in std_logic;
gtx_clk_out : out std_logic;
gtx_clk90_out : out std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Interface
----------------------------
rx_enable : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
rx_mac_aclk : out std_logic;
rx_reset : out std_logic;
rx_axis_mac_tdata : out std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : out std_logic;
rx_axis_mac_tlast : out std_logic;
rx_axis_mac_tuser : out std_logic;
-- Transmitter Interface
-------------------------------
tx_enable : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
tx_mac_aclk : out std_logic;
tx_reset : out std_logic;
tx_axis_mac_tready : out std_logic;
tx_axis_mac_tvalid : in std_logic;
tx_axis_mac_tdata : in std_logic_vector(7 downto 0);
tx_axis_mac_tlast : in std_logic;
tx_axis_mac_tuser : in std_logic_vector(0 downto 0);
-- MAC Control Interface
------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- Reference clock for IDELAYCTRL's
refclk : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- RGMII Interface
------------------
rgmii_txd : out std_logic_vector(3 downto 0);
rgmii_tx_ctl : out std_logic;
rgmii_txc : out std_logic;
rgmii_rxd : in std_logic_vector(3 downto 0);
rgmii_rx_ctl : in std_logic;
rgmii_rxc : in std_logic;
inband_link_status : out std_logic;
inband_clock_speed : out std_logic_vector(1 downto 0);
inband_duplex_status : out std_logic;
-- MDIO Interface
-----------------
mdio : inout std_logic;
mdc : out std_logic;
-- AXI-Lite Interface
-----------------
s_axi_aclk : in std_logic;
s_axi_resetn : in std_logic;
s_axi_awaddr : in std_logic_vector(11 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(31 downto 0);
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in std_logic_vector(11 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out std_logic_vector(31 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
mac_irq : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the fifo
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic (
FULL_DUPLEX_ONLY : boolean := true); -- If fifo is to be used only in full
-- duplex set to true for optimised implementation
port (
tx_fifo_aclk : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tlast : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_mac_aclk : in std_logic;
tx_mac_resetn : in std_logic;
tx_axis_mac_tdata : out std_logic_vector(7 downto 0);
tx_axis_mac_tvalid : out std_logic;
tx_axis_mac_tlast : out std_logic;
tx_axis_mac_tready : in std_logic;
tx_axis_mac_tuser : out std_logic;
tx_fifo_overflow : out std_logic;
tx_fifo_status : out std_logic_vector(3 downto 0);
tx_collision : in std_logic;
tx_retransmit : in std_logic;
rx_fifo_aclk : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tlast : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_mac_aclk : in std_logic;
rx_mac_resetn : in std_logic;
rx_axis_mac_tdata : in std_logic_vector(7 downto 0);
rx_axis_mac_tvalid : in std_logic;
rx_axis_mac_tlast : in std_logic;
rx_axis_mac_tuser : in std_logic;
rx_fifo_status : out std_logic_vector(3 downto 0);
rx_fifo_overflow : out std_logic
);
end component;
------------------------------------------------------------------------------
-- Component declaration for the reset synchroniser
------------------------------------------------------------------------------
component tri_mode_ethernet_mac_0_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic -- "Synchronised" reset signal
);
end component;
------------------------------------------------------------------------------
-- Internal signals used in this fifo block level wrapper.
------------------------------------------------------------------------------
signal rx_mac_aclk_int : std_logic; -- MAC Rx clock
signal tx_mac_aclk_int : std_logic; -- MAC Tx clock
signal rx_reset_int : std_logic; -- MAC Rx reset
signal tx_reset_int : std_logic; -- MAC Tx reset
signal tx_mac_resetn : std_logic;
signal rx_mac_resetn : std_logic;
signal tx_mac_reset : std_logic;
signal rx_mac_reset : std_logic;
-- MAC receiver client I/F
signal rx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid : std_logic;
signal rx_axis_mac_tlast : std_logic;
signal rx_axis_mac_tuser : std_logic;
-- MAC transmitter client I/F
signal tx_axis_mac_tdata : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid : std_logic;
signal tx_axis_mac_tready : std_logic;
signal tx_axis_mac_tlast : std_logic;
signal tx_axis_mac_tuser : std_logic_vector(0 downto 0);
begin
------------------------------------------------------------------------------
-- Connect the output clock signals
------------------------------------------------------------------------------
rx_mac_aclk <= rx_mac_aclk_int;
tx_mac_aclk <= tx_mac_aclk_int;
rx_reset <= rx_reset_int;
tx_reset <= tx_reset_int;
------------------------------------------------------------------------------
-- Instantiate the Tri-Mode Ethernet MAC Support Level wrapper
------------------------------------------------------------------------------
trimac_sup_block : tri_mode_ethernet_mac_0_support
port map(
gtx_clk => gtx_clk,
gtx_clk_out => open,
gtx_clk90_out => open,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => rx_axi_rstn,
tx_axi_rstn => tx_axi_rstn,
-- Client Receiver Interface
rx_enable => open,
rx_statistics_vector => rx_statistics_vector,
rx_statistics_valid => rx_statistics_valid,
rx_mac_aclk => rx_mac_aclk_int,
rx_reset => rx_reset_int,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
-- Client Transmitter Interface
tx_enable => open,
tx_ifg_delay => tx_ifg_delay,
tx_statistics_vector => tx_statistics_vector,
tx_statistics_valid => tx_statistics_valid,
tx_mac_aclk => tx_mac_aclk_int,
tx_reset => tx_reset_int,
tx_axis_mac_tdata => tx_axis_mac_tdata ,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser,
tx_axis_mac_tready => tx_axis_mac_tready,
-- Flow Control
pause_req => pause_req,
pause_val => pause_val,
-- Reference clock for IDELAYCTRL's
refclk => refclk,
-- speed control
speedis100 => open,
speedis10100 => open,
-- RGMII Interface
rgmii_txd => rgmii_txd,
rgmii_tx_ctl => rgmii_tx_ctl,
rgmii_txc => rgmii_txc,
rgmii_rxd => rgmii_rxd,
rgmii_rx_ctl => rgmii_rx_ctl,
rgmii_rxc => rgmii_rxc,
inband_link_status => inband_link_status,
inband_clock_speed => inband_clock_speed,
inband_duplex_status => inband_duplex_status,
-- MDIO Interface
-----------------
mdio => mdio,
mdc => mdc,
-- AXI lite interface
s_axi_aclk => s_axi_aclk,
s_axi_resetn => s_axi_resetn,
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
mac_irq => open
);
------------------------------------------------------------------------------
-- Instantiate the user side FIFO
------------------------------------------------------------------------------
-- locally reset sync the mac generated resets - the resets are already fully sync
-- so adding a reset sync shouldn't change that
rx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => rx_mac_aclk_int,
enable => '1',
reset_in => rx_reset_int,
reset_out => rx_mac_reset
);
tx_mac_reset_gen : tri_mode_ethernet_mac_0_reset_sync
port map (
clk => tx_mac_aclk_int,
enable => '1',
reset_in => tx_reset_int,
reset_out => tx_mac_reset
);
-- create inverted mac resets as the FIFO expects AXI compliant resets
tx_mac_resetn <= not tx_mac_reset;
rx_mac_resetn <= not rx_mac_reset;
user_side_FIFO : tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo
generic map(
FULL_DUPLEX_ONLY => true
)
port map(
-- Transmit FIFO MAC TX Interface
tx_fifo_aclk => tx_fifo_clock,
tx_fifo_resetn => tx_fifo_resetn,
tx_axis_fifo_tready => tx_axis_fifo_tready,
tx_axis_fifo_tvalid => tx_axis_fifo_tvalid,
tx_axis_fifo_tdata => tx_axis_fifo_tdata,
tx_axis_fifo_tlast => tx_axis_fifo_tlast,
tx_mac_aclk => tx_mac_aclk_int,
tx_mac_resetn => tx_mac_resetn,
tx_axis_mac_tready => tx_axis_mac_tready,
tx_axis_mac_tvalid => tx_axis_mac_tvalid,
tx_axis_mac_tdata => tx_axis_mac_tdata,
tx_axis_mac_tlast => tx_axis_mac_tlast,
tx_axis_mac_tuser => tx_axis_mac_tuser(0),
tx_fifo_overflow => open,
tx_fifo_status => open,
tx_collision => '0',
tx_retransmit => '0',
rx_fifo_aclk => rx_fifo_clock,
rx_fifo_resetn => rx_fifo_resetn,
rx_axis_fifo_tready => rx_axis_fifo_tready,
rx_axis_fifo_tvalid => rx_axis_fifo_tvalid,
rx_axis_fifo_tdata => rx_axis_fifo_tdata,
rx_axis_fifo_tlast => rx_axis_fifo_tlast,
rx_mac_aclk => rx_mac_aclk_int,
rx_mac_resetn => rx_mac_resetn,
rx_axis_mac_tvalid => rx_axis_mac_tvalid,
rx_axis_mac_tdata => rx_axis_mac_tdata,
rx_axis_mac_tlast => rx_axis_mac_tlast,
rx_axis_mac_tuser => rx_axis_mac_tuser,
rx_fifo_status => open,
rx_fifo_overflow => open
);
end wrapper;
|
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2946.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02946ent IS
END c02s02b00x00p08n02i02946ent;
ARCHITECTURE c02s02b00x00p08n02i02946arch OF c02s02b00x00p08n02i02946ent IS
function func1 (a1 : real; b1 : integer:= 12) return integer;
function func1 (a1 : real; b1 : integer:= 12) return integer is
begin
end func2; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p08n02i02946 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02946arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2946.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02946ent IS
END c02s02b00x00p08n02i02946ent;
ARCHITECTURE c02s02b00x00p08n02i02946arch OF c02s02b00x00p08n02i02946ent IS
function func1 (a1 : real; b1 : integer:= 12) return integer;
function func1 (a1 : real; b1 : integer:= 12) return integer is
begin
end func2; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p08n02i02946 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02946arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2946.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s02b00x00p08n02i02946ent IS
END c02s02b00x00p08n02i02946ent;
ARCHITECTURE c02s02b00x00p08n02i02946arch OF c02s02b00x00p08n02i02946ent IS
function func1 (a1 : real; b1 : integer:= 12) return integer;
function func1 (a1 : real; b1 : integer:= 12) return integer is
begin
end func2; -- Failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s02b00x00p08n02i02946 - Designator at the end of subprogram body is not the same as the designator of the subprogram."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s02b00x00p08n02i02946arch;
|
-- Copyright (C) 1991-2011 Altera Corporation
-- This simulation model contains highly confidential and
-- proprietary information of Altera and is being provided
-- in accordance with and subject to the protections of the
-- applicable Altera Program License Subscription Agreement
-- which governs its use and disclosure. Your use of Altera
-- Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions,
-- and any output files any of the foregoing (including device
-- programming or simulation files), and any associated
-- documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other
-- applicable license agreement, including, without limitation,
-- that your use is for the sole purpose of simulating designs for
-- use exclusively in logic devices manufactured by Altera and sold
-- by Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details. Altera products and
-- services are protected under numerous U.S. and foreign patents,
-- maskwork rights, copyrights and other intellectual property laws.
-- Altera assumes no responsibility or liability arising out of the
-- application or use of this simulation model.
-- Quartus II 11.0 Build 157 04/27/2011
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
package STRATIXV_PCIE_HIP_COMPONENTS is
component stratixv_hssi_gen3_pcie_hip
generic (
func_mode : string := "disable";
bonding_mode : string := "bond_disable";
prot_mode : string := "disabled_prot_mode";
pcie_spec_1p0_compliance : string := "spec_1p1";
vc_enable : string := "single_vc";
enable_slot_register : string := "false";
pcie_mode : string := "shared_mode";
bypass_cdc : string := "false";
enable_rx_reordering : string := "true";
enable_rx_buffer_checking : string := "false";
single_rx_detect_data : bit_vector := B"0000";
single_rx_detect : string := "single_rx_detect";
use_crc_forwarding : string := "false";
bypass_tl : string := "false";
gen123_lane_rate_mode : string := "gen1";
lane_mask : string := "x4";
disable_link_x2_support : string := "false";
national_inst_thru_enhance : string := "true";
hip_hard_reset : string := "enable";
dis_paritychk : string := "enable";
wrong_device_id : string := "disable";
data_pack_rx : string := "disable";
ast_width : string := "rx_tx_64";
rx_sop_ctrl : string := "boundary_64";
rx_ast_parity : string := "disable";
tx_ast_parity : string := "disable";
ltssm_1ms_timeout : string := "disable";
ltssm_freqlocked_check : string := "disable";
deskew_comma : string := "skp_eieos_deskw";
dl_tx_check_parity_edb : string := "disable";
tl_tx_check_parity_msg : string := "disable";
port_link_number_data : bit_vector := B"00000001";
port_link_number : string := "port_link_number";
device_number_data : bit_vector := B"00000";
device_number : string := "device_number";
bypass_clk_switch : string := "false";
core_clk_out_sel : string := "div_1";
core_clk_divider : string := "div_1";
core_clk_source : string := "pll_fixed_clk";
core_clk_sel : string := "pld_clk";
enable_ch0_pclk_out : string := "true";
enable_ch01_pclk_out : string := "pclk_ch0";
pipex1_debug_sel : string := "disable";
pclk_out_sel : string := "pclk";
vendor_id_data : bit_vector := B"1000101110010";
vendor_id : string := "vendor_id";
device_id_data : bit_vector := B"0000000000000001";
device_id : string := "device_id";
revision_id_data : bit_vector := B"00000001";
revision_id : string := "revision_id";
class_code_data : bit_vector := B"111111110000000000000000";
class_code : string := "class_code";
subsystem_vendor_id_data : bit_vector := B"0001000101110010";
subsystem_vendor_id : string := "subsystem_vendor_id";
subsystem_device_id_data : bit_vector := B"0000000000000001";
subsystem_device_id : string := "subsystem_device_id";
no_soft_reset : string := "false";
maximum_current_data : bit_vector := B"000";
maximum_current : string := "maximum_current";
d1_support : string := "false";
d2_support : string := "false";
d0_pme : string := "false";
d1_pme : string := "false";
d2_pme : string := "false";
d3_hot_pme : string := "false";
d3_cold_pme : string := "false";
use_aer : string := "false";
low_priority_vc : string := "single_vc";
vc_arbitration : string := "single_vc";
disable_snoop_packet : string := "false";
max_payload_size : string := "payload_512";
surprise_down_error_support : string := "false";
dll_active_report_support : string := "false";
extend_tag_field : string := "false";
endpoint_l0_latency_data : bit_vector := B"000";
endpoint_l0_latency : string := "endpoint_l0_latency";
endpoint_l1_latency_data : bit_vector := B"000";
endpoint_l1_latency : string := "endpoint_l1_latency";
indicator_data : bit_vector := B"111";
indicator : string := "indicator";
role_based_error_reporting : string := "false";
slot_power_scale_data : bit_vector := B"00";
slot_power_scale : string := "slot_power_scale";
max_link_width : string := "x4";
enable_l1_aspm : string := "false";
enable_l0s_aspm : string := "false";
l1_exit_latency_sameclock_data : bit_vector := B"000";
l1_exit_latency_sameclock : string := "l1_exit_latency_sameclock";
l1_exit_latency_diffclock_data : bit_vector := B"000";
l1_exit_latency_diffclock : string := "l1_exit_latency_diffclock";
hot_plug_support_data : bit_vector := B"0000000";
hot_plug_support : string := "hot_plug_support";
slot_power_limit_data : bit_vector := B"00000000";
slot_power_limit : string := "slot_power_limit";
slot_number_data : bit_vector := B"0000000000000";
slot_number : string := "slot_number";
diffclock_nfts_count_data : bit_vector := B"00000000";
diffclock_nfts_count : string := "diffclock_nfts_count";
sameclock_nfts_count_data : bit_vector := B"00000000";
sameclock_nfts_count : string := "sameclock_nfts_count";
completion_timeout : string := "abcd";
enable_completion_timeout_disable : string := "true";
extended_tag_reset : string := "false";
ecrc_check_capable : string := "true";
ecrc_gen_capable : string := "true";
no_command_completed : string := "true";
msi_multi_message_capable : string := "count_4";
msi_64bit_addressing_capable : string := "true";
msi_masking_capable : string := "false";
msi_support : string := "true";
interrupt_pin : string := "inta";
ena_ido_req : string := "false";
ena_ido_cpl : string := "false";
enable_function_msix_support : string := "true";
msix_table_size_data : bit_vector := B"00000000000";
msix_table_size : string := "msix_table_size";
msix_table_bir_data : bit_vector := B"000";
msix_table_bir : string := "msix_table_bir";
msix_table_offset_data : bit_vector := B"00000000000000000000000000000";
msix_table_offset : string := "msix_table_offset";
msix_pba_bir_data : bit_vector := B"000";
msix_pba_bir : string := "msix_pba_bir";
msix_pba_offset_data : bit_vector := B"00000000000000000000000000000";
msix_pba_offset : string := "msix_pba_offset";
bridge_port_vga_enable : string := "false";
bridge_port_ssid_support : string := "false";
ssvid_data : bit_vector := B"0000000000000000";
ssvid : string := "ssvid";
ssid_data : bit_vector := B"0000000000000000";
ssid : string := "ssid";
eie_before_nfts_count_data : bit_vector := B"0100";
eie_before_nfts_count : string := "eie_before_nfts_count";
gen2_diffclock_nfts_count_data : bit_vector := B"11111111";
gen2_diffclock_nfts_count : string := "gen2_diffclock_nfts_count";
gen2_sameclock_nfts_count_data : bit_vector := B"11111111";
gen2_sameclock_nfts_count : string := "gen2_sameclock_nfts_count";
deemphasis_enable : string := "false";
pcie_spec_version : string := "v2";
l0_exit_latency_sameclock_data : bit_vector := B"110";
l0_exit_latency_sameclock : string := "l0_exit_latency_sameclock";
l0_exit_latency_diffclock_data : bit_vector := B"110";
l0_exit_latency_diffclock : string := "l0_exit_latency_diffclock";
rx_ei_l0s : string := "disable";
l2_async_logic : string := "enable";
aspm_config_management : string := "true";
atomic_op_routing : string := "false";
atomic_op_completer_32bit : string := "false";
atomic_op_completer_64bit : string := "false";
cas_completer_128bit : string := "false";
ltr_mechanism : string := "false";
tph_completer : string := "false";
extended_format_field : string := "true";
atomic_malformed : string := "false";
flr_capability : string := "true";
enable_adapter_half_rate_mode : string := "false";
vc0_clk_enable : string := "true";
vc1_clk_enable : string := "false";
register_pipe_signals : string := "false";
bar0_io_space : string := "false";
bar0_64bit_mem_space : string := "true";
bar0_prefetchable : string := "true";
bar0_size_mask_data : bit_vector := B"1111111111111111111111111111";
bar0_size_mask : string := "bar0_size_mask";
bar1_io_space : string := "false";
bar1_64bit_mem_space : string := "false";
bar1_prefetchable : string := "false";
bar1_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar1_size_mask : string := "bar1_size_mask";
bar2_io_space : string := "false";
bar2_64bit_mem_space : string := "false";
bar2_prefetchable : string := "false";
bar2_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar2_size_mask : string := "bar2_size_mask";
bar3_io_space : string := "false";
bar3_64bit_mem_space : string := "false";
bar3_prefetchable : string := "false";
bar3_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar3_size_mask : string := "bar3_size_mask";
bar4_io_space : string := "false";
bar4_64bit_mem_space : string := "false";
bar4_prefetchable : string := "false";
bar4_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar4_size_mask : string := "bar4_size_mask";
bar5_io_space : string := "false";
bar5_64bit_mem_space : string := "false";
bar5_prefetchable : string := "false";
bar5_size_mask_data : bit_vector := B"0000000000000000000000000000";
bar5_size_mask : string := "bar5_size_mask";
expansion_base_address_register_data : bit_vector := B"00000000000000000000000000000000";
expansion_base_address_register : string := "expansion_base_address_register";
io_window_addr_width : string := "window_32_bit";
prefetchable_mem_window_addr_width : string := "prefetch_32";
skp_os_gen3_count_data : bit_vector := B"00000000000";
skp_os_gen3_count : string := "skp_os_gen3_count";
rx_cdc_almost_empty_data : bit_vector := B"0000";
rx_cdc_almost_empty : string := "rx_cdc_almost_empty";
tx_cdc_almost_empty_data : bit_vector := B"0000";
tx_cdc_almost_empty : string := "tx_cdc_almost_empty";
rx_cdc_almost_full_data : bit_vector := B"0000";
rx_cdc_almost_full : string := "rx_cdc_almost_full";
tx_cdc_almost_full_data : bit_vector := B"0000";
tx_cdc_almost_full : string := "tx_cdc_almost_full";
rx_l0s_count_idl_data : bit_vector := B"00000000";
rx_l0s_count_idl : string := "rx_l0s_count_idl";
cdc_dummy_insert_limit_data : bit_vector := B"0000";
cdc_dummy_insert_limit : string := "cdc_dummy_insert_limit";
ei_delay_powerdown_count_data : bit_vector := B"00001010";
ei_delay_powerdown_count : string := "ei_delay_powerdown_count";
millisecond_cycle_count_data : bit_vector := B"00000000000000000000";
millisecond_cycle_count : string := "millisecond_cycle_count";
skp_os_schedule_count_data : bit_vector := B"00000000000";
skp_os_schedule_count : string := "skp_os_schedule_count";
fc_init_timer_data : bit_vector := B"10000000000";
fc_init_timer : string := "fc_init_timer";
l01_entry_latency_data : bit_vector := B"11111";
l01_entry_latency : string := "l01_entry_latency";
flow_control_update_count_data : bit_vector := B"11110";
flow_control_update_count : string := "flow_control_update_count";
flow_control_timeout_count_data : bit_vector := B"11001000";
flow_control_timeout_count : string := "flow_control_timeout_count";
vc0_rx_flow_ctrl_posted_header_data : bit_vector := B"00110010";
vc0_rx_flow_ctrl_posted_header : string := "vc0_rx_flow_ctrl_posted_header";
vc0_rx_flow_ctrl_posted_data_data : bit_vector := B"000101101000";
vc0_rx_flow_ctrl_posted_data : string := "vc0_rx_flow_ctrl_posted_data";
vc0_rx_flow_ctrl_nonposted_header_data : bit_vector := B"00110110";
vc0_rx_flow_ctrl_nonposted_header : string := "vc0_rx_flow_ctrl_nonposted_header";
vc0_rx_flow_ctrl_nonposted_data_data : bit_vector := B"00000000";
vc0_rx_flow_ctrl_nonposted_data : string := "vc0_rx_flow_ctrl_nonposted_data";
vc0_rx_flow_ctrl_compl_header_data : bit_vector := B"01110000";
vc0_rx_flow_ctrl_compl_header : string := "vc0_rx_flow_ctrl_compl_header";
vc0_rx_flow_ctrl_compl_data_data : bit_vector := B"000111000000";
vc0_rx_flow_ctrl_compl_data : string := "vc0_rx_flow_ctrl_compl_data";
rx_ptr0_posted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_min : string := "rx_ptr0_posted_dpram_min";
rx_ptr0_posted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_posted_dpram_max : string := "rx_ptr0_posted_dpram_max";
rx_ptr0_nonposted_dpram_min_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_min : string := "rx_ptr0_nonposted_dpram_min";
rx_ptr0_nonposted_dpram_max_data : bit_vector := B"00000000000";
rx_ptr0_nonposted_dpram_max : string := "rx_ptr0_nonposted_dpram_max";
retry_buffer_last_active_address_data : bit_vector := B"1111111111";
retry_buffer_last_active_address : string := "retry_buffer_last_active_address";
retry_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
retry_buffer_memory_settings : string := "retry_buffer_memory_settings";
vc0_rx_buffer_memory_settings_data : bit_vector := B"000000000000000000000000000000";
vc0_rx_buffer_memory_settings : string := "vc0_rx_buffer_memory_settings";
bist_memory_settings_data : bit_vector := B"000000000000000000000000000000000000000000000000000000000000000000000000000";
bist_memory_settings : string := "bist_memory_settings";
credit_buffer_allocation_aux : string := "balanced";
iei_enable_settings : string := "gen2_infei_infsd_gen1_infei_sd";
vsec_id_data : bit_vector := B"0001000101110010";
vsec_id : string := "vsec_id";
cvp_rate_sel : string := "full_rate";
hard_reset_bypass : string := "false";
cvp_data_compressed : string := "false";
cvp_data_encrypted : string := "false";
cvp_mode_reset : string := "false";
cvp_clk_reset : string := "false";
vsec_cap_data : bit_vector := B"0000";
vsec_cap : string := "vsec_cap";
jtag_id_data : bit_vector := B"00000000000000000000000000000000";
jtag_id : string := "jtag_id";
user_id_data : bit_vector := B"0000000000000000";
user_id : string := "user_id";
cseb_extend_pci : string := "false";
cseb_extend_pcie : string := "false";
cseb_cpl_status_during_cvp : string := "config_retry_status";
cseb_route_to_avl_rx_st : string := "cseb";
cseb_config_bypass : string := "disable";
cseb_cpl_tag_checking : string := "enable";
cseb_bar_match_checking : string := "enable";
cseb_min_error_checking : string := "false";
cseb_temp_busy_crs : string := "completer_abort";
cseb_disable_auto_crs : string := "false";
gen3_diffclock_nfts_count_data : bit_vector := B"10000000";
gen3_diffclock_nfts_count : string := "g3_diffclock_nfts_count";
gen3_sameclock_nfts_count_data : bit_vector := B"10000000";
gen3_sameclock_nfts_count : string := "g3_sameclock_nfts_count";
gen3_coeff_errchk : string := "enable";
gen3_paritychk : string := "enable";
gen3_coeff_delay_count_data : bit_vector := B"1111101";
gen3_coeff_delay_count : string := "g3_coeff_dly_count";
gen3_coeff_1_data : bit_vector := B"000000000000000000";
gen3_coeff_1 : string := "g3_coeff_1";
gen3_coeff_1_sel : string := "coeff_1";
gen3_coeff_1_preset_hint_data : bit_vector := B"000";
gen3_coeff_1_preset_hint : string := "g3_coeff_1_prst_hint";
gen3_coeff_1_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_more : string := "g3_coeff_1_nxtber_more";
gen3_coeff_1_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_1_nxtber_less : string := "g3_coeff_1_nxtber_less";
gen3_coeff_1_reqber_data : bit_vector := B"00000";
gen3_coeff_1_reqber : string := "g3_coeff_1_reqber";
gen3_coeff_1_ber_meas_data : bit_vector := B"000000";
gen3_coeff_1_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_2_data : bit_vector := B"000000000000000000";
gen3_coeff_2 : string := "g3_coeff_2";
gen3_coeff_2_sel : string := "coeff_2";
gen3_coeff_2_preset_hint_data : bit_vector := B"000";
gen3_coeff_2_preset_hint : string := "g3_coeff_2_prst_hint";
gen3_coeff_2_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_more : string := "g3_coeff_2_nxtber_more";
gen3_coeff_2_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_2_nxtber_less : string := "g3_coeff_2_nxtber_less";
gen3_coeff_2_reqber_data : bit_vector := B"00000";
gen3_coeff_2_reqber : string := "g3_coeff_2_reqber";
gen3_coeff_2_ber_meas_data : bit_vector := B"000000";
gen3_coeff_2_ber_meas : string := "g3_coeff_1_ber_meas";
gen3_coeff_3_data : bit_vector := B"000000000000000000";
gen3_coeff_3 : string := "g3_coeff_3";
gen3_coeff_3_sel : string := "coeff_3";
gen3_coeff_3_preset_hint_data : bit_vector := B"000";
gen3_coeff_3_preset_hint : string := "g3_coeff_3_prst_hint";
gen3_coeff_3_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_more : string := "g3_coeff_3_nxtber_more";
gen3_coeff_3_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_3_nxtber_less : string := "g3_coeff_3_nxtber_less";
gen3_coeff_3_reqber_data : bit_vector := B"00000";
gen3_coeff_3_reqber : string := "g3_coeff_3_reqber";
gen3_coeff_3_ber_meas_data : bit_vector := B"000000";
gen3_coeff_3_ber_meas : string := "g3_coeff_3_ber_meas";
gen3_coeff_4_data : bit_vector := B"000000000000000000";
gen3_coeff_4 : string := "g3_coeff_4";
gen3_coeff_4_sel : string := "coeff_4";
gen3_coeff_4_preset_hint_data : bit_vector := B"000";
gen3_coeff_4_preset_hint : string := "g3_coeff_4_prst_hint";
gen3_coeff_4_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_more : string := "g3_coeff_4_nxtber_more";
gen3_coeff_4_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_4_nxtber_less : string := "g3_coeff_4_nxtber_less";
gen3_coeff_4_reqber_data : bit_vector := B"00000";
gen3_coeff_4_reqber : string := "g3_coeff_4_reqber";
gen3_coeff_4_ber_meas_data : bit_vector := B"000000";
gen3_coeff_4_ber_meas : string := "g3_coeff_4_ber_meas";
gen3_coeff_5_data : bit_vector := B"000000000000000000";
gen3_coeff_5 : string := "g3_coeff_5";
gen3_coeff_5_sel : string := "coeff_5";
gen3_coeff_5_preset_hint_data : bit_vector := B"000";
gen3_coeff_5_preset_hint : string := "g3_coeff_5_prst_hint";
gen3_coeff_5_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_more : string := "g3_coeff_5_nxtber_more";
gen3_coeff_5_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_5_nxtber_less : string := "g3_coeff_5_nxtber_less";
gen3_coeff_5_reqber_data : bit_vector := B"00000";
gen3_coeff_5_reqber : string := "g3_coeff_5_reqber";
gen3_coeff_5_ber_meas_data : bit_vector := B"000000";
gen3_coeff_5_ber_meas : string := "g3_coeff_5_ber_meas";
gen3_coeff_6_data : bit_vector := B"000000000000000000";
gen3_coeff_6 : string := "g3_coeff_6";
gen3_coeff_6_sel : string := "coeff_6";
gen3_coeff_6_preset_hint_data : bit_vector := B"000";
gen3_coeff_6_preset_hint : string := "g3_coeff_6_prst_hint";
gen3_coeff_6_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_more : string := "g3_coeff_6_nxtber_more";
gen3_coeff_6_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_6_nxtber_less : string := "g3_coeff_6_nxtber_less";
gen3_coeff_6_reqber_data : bit_vector := B"00000";
gen3_coeff_6_reqber : string := "g3_coeff_6_reqber";
gen3_coeff_6_ber_meas_data : bit_vector := B"000000";
gen3_coeff_6_ber_meas : string := "g3_coeff_6_ber_meas";
gen3_coeff_7_data : bit_vector := B"000000000000000000";
gen3_coeff_7 : string := "g3_coeff_7";
gen3_coeff_7_sel : string := "coeff_7";
gen3_coeff_7_preset_hint_data : bit_vector := B"000";
gen3_coeff_7_preset_hint : string := "g3_coeff_7_prst_hint";
gen3_coeff_7_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_more : string := "g3_coeff_7_nxtber_more";
gen3_coeff_7_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_7_nxtber_less : string := "g3_coeff_7_nxtber_less";
gen3_coeff_7_reqber_data : bit_vector := B"00000";
gen3_coeff_7_reqber : string := "g3_coeff_7_reqber";
gen3_coeff_7_ber_meas_data : bit_vector := B"000000";
gen3_coeff_7_ber_meas : string := "g3_coeff_7_ber_meas";
gen3_coeff_8_data : bit_vector := B"000000000000000000";
gen3_coeff_8 : string := "g3_coeff_8";
gen3_coeff_8_sel : string := "coeff_8";
gen3_coeff_8_preset_hint_data : bit_vector := B"000";
gen3_coeff_8_preset_hint : string := "g3_coeff_8_prst_hint";
gen3_coeff_8_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_more : string := "g3_coeff_8_nxtber_more";
gen3_coeff_8_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_8_nxtber_less : string := "g3_coeff_8_nxtber_less";
gen3_coeff_8_reqber_data : bit_vector := B"00000";
gen3_coeff_8_reqber : string := "g3_coeff_8_reqber";
gen3_coeff_8_ber_meas_data : bit_vector := B"000000";
gen3_coeff_8_ber_meas : string := "g3_coeff_8_ber_meas";
gen3_coeff_9_data : bit_vector := B"000000000000000000";
gen3_coeff_9 : string := "g3_coeff_9";
gen3_coeff_9_sel : string := "coeff_9";
gen3_coeff_9_preset_hint_data : bit_vector := B"000";
gen3_coeff_9_preset_hint : string := "g3_coeff_9_prst_hint";
gen3_coeff_9_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_more : string := "g3_coeff_9_nxtber_more";
gen3_coeff_9_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_9_nxtber_less : string := "g3_coeff_9_nxtber_less";
gen3_coeff_9_reqber_data : bit_vector := B"00000";
gen3_coeff_9_reqber : string := "g3_coeff_9_reqber";
gen3_coeff_9_ber_meas_data : bit_vector := B"000000";
gen3_coeff_9_ber_meas : string := "g3_coeff_9_ber_meas";
gen3_coeff_10_data : bit_vector := B"000000000000000000";
gen3_coeff_10 : string := "g3_coeff_10";
gen3_coeff_10_sel : string := "coeff_10";
gen3_coeff_10_preset_hint_data : bit_vector := B"000";
gen3_coeff_10_preset_hint : string := "g3_coeff_10_prst_hint";
gen3_coeff_10_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_more : string := "g3_coeff_10_nxtber_more";
gen3_coeff_10_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_10_nxtber_less : string := "g3_coeff_10_nxtber_less";
gen3_coeff_10_reqber_data : bit_vector := B"00000";
gen3_coeff_10_reqber : string := "g3_coeff_10_reqber";
gen3_coeff_10_ber_meas_data : bit_vector := B"000000";
gen3_coeff_10_ber_meas : string := "g3_coeff_10_ber_meas";
gen3_coeff_11_data : bit_vector := B"000000000000000000";
gen3_coeff_11 : string := "g3_coeff_11";
gen3_coeff_11_sel : string := "coeff_11";
gen3_coeff_11_preset_hint_data : bit_vector := B"000";
gen3_coeff_11_preset_hint : string := "g3_coeff_11_prst_hint";
gen3_coeff_11_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_more : string := "g3_coeff_11_nxtber_more";
gen3_coeff_11_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_11_nxtber_less : string := "g3_coeff_11_nxtber_less";
gen3_coeff_11_reqber_data : bit_vector := B"00000";
gen3_coeff_11_reqber : string := "g3_coeff_11_reqber";
gen3_coeff_11_ber_meas_data : bit_vector := B"000000";
gen3_coeff_11_ber_meas : string := "g3_coeff_11_ber_meas";
gen3_coeff_12_data : bit_vector := B"000000000000000000";
gen3_coeff_12 : string := "g3_coeff_12";
gen3_coeff_12_sel : string := "coeff_12";
gen3_coeff_12_preset_hint_data : bit_vector := B"000";
gen3_coeff_12_preset_hint : string := "g3_coeff_12_prst_hint";
gen3_coeff_12_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_more : string := "g3_coeff_12_nxtber_more";
gen3_coeff_12_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_12_nxtber_less : string := "g3_coeff_12_nxtber_less";
gen3_coeff_12_reqber_data : bit_vector := B"00000";
gen3_coeff_12_reqber : string := "g3_coeff_12_reqber";
gen3_coeff_12_ber_meas_data : bit_vector := B"000000";
gen3_coeff_12_ber_meas : string := "g3_coeff_12_ber_meas";
gen3_coeff_13_data : bit_vector := B"000000000000000000";
gen3_coeff_13 : string := "g3_coeff_13";
gen3_coeff_13_sel : string := "coeff_13";
gen3_coeff_13_preset_hint_data : bit_vector := B"000";
gen3_coeff_13_preset_hint : string := "g3_coeff_13_prst_hint";
gen3_coeff_13_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_more : string := "g3_coeff_13_nxtber_more";
gen3_coeff_13_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_13_nxtber_less : string := "g3_coeff_13_nxtber_less";
gen3_coeff_13_reqber_data : bit_vector := B"00000";
gen3_coeff_13_reqber : string := "g3_coeff_13_reqber";
gen3_coeff_13_ber_meas_data : bit_vector := B"000000";
gen3_coeff_13_ber_meas : string := "g3_coeff_13_ber_meas";
gen3_coeff_14_data : bit_vector := B"000000000000000000";
gen3_coeff_14 : string := "g3_coeff_14";
gen3_coeff_14_sel : string := "coeff_14";
gen3_coeff_14_preset_hint_data : bit_vector := B"000";
gen3_coeff_14_preset_hint : string := "g3_coeff_14_prst_hint";
gen3_coeff_14_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_more : string := "g3_coeff_14_nxtber_more";
gen3_coeff_14_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_14_nxtber_less : string := "g3_coeff_14_nxtber_less";
gen3_coeff_14_reqber_data : bit_vector := B"00000";
gen3_coeff_14_reqber : string := "g3_coeff_14_reqber";
gen3_coeff_14_ber_meas_data : bit_vector := B"000000";
gen3_coeff_14_ber_meas : string := "g3_coeff_14_ber_meas";
gen3_coeff_15_data : bit_vector := B"000000000000000000";
gen3_coeff_15 : string := "g3_coeff_15";
gen3_coeff_15_sel : string := "coeff_15";
gen3_coeff_15_preset_hint_data : bit_vector := B"000";
gen3_coeff_15_preset_hint : string := "g3_coeff_15_prst_hint";
gen3_coeff_15_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_more : string := "g3_coeff_15_nxtber_more";
gen3_coeff_15_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_15_nxtber_less : string := "g3_coeff_15_nxtber_less";
gen3_coeff_15_reqber_data : bit_vector := B"00000";
gen3_coeff_15_reqber : string := "g3_coeff_15_reqber";
gen3_coeff_15_ber_meas_data : bit_vector := B"000000";
gen3_coeff_15_ber_meas : string := "g3_coeff_15_ber_meas";
gen3_coeff_16_data : bit_vector := B"000000000000000000";
gen3_coeff_16 : string := "g3_coeff_16";
gen3_coeff_16_sel : string := "coeff_16";
gen3_coeff_16_preset_hint_data : bit_vector := B"000";
gen3_coeff_16_preset_hint : string := "g3_coeff_16_prst_hint";
gen3_coeff_16_nxtber_more_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_more : string := "g3_coeff_16_nxtber_more";
gen3_coeff_16_nxtber_less_ptr : bit_vector := B"0000";
gen3_coeff_16_nxtber_less : string := "g3_coeff_16_nxtber_less";
gen3_coeff_16_reqber_data : bit_vector := B"00000";
gen3_coeff_16_reqber : string := "g3_coeff_16_reqber";
gen3_coeff_16_ber_meas_data : bit_vector := B"000000";
gen3_coeff_16_ber_meas : string := "g3_coeff_16_ber_meas";
gen3_preset_coeff_1_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_1 : string := "g3_prst_coeff_1";
gen3_preset_coeff_2_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_2 : string := "g3_prst_coeff_2";
gen3_preset_coeff_3_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_3 : string := "g3_prst_coeff_3";
gen3_preset_coeff_4_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_4 : string := "g3_prst_coeff_4";
gen3_preset_coeff_5_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_5 : string := "g3_prst_coeff_5";
gen3_preset_coeff_6_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_6 : string := "g3_prst_coeff_6";
gen3_preset_coeff_7_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_7 : string := "g3_prst_coeff_7";
gen3_preset_coeff_8_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_8 : string := "g3_prst_coeff_8";
gen3_preset_coeff_9_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_9 : string := "g3_prst_coeff_9";
gen3_preset_coeff_10_data : bit_vector := B"000000000000000000";
gen3_preset_coeff_10 : string := "g3_prst_coeff_10";
gen3_rxfreqlock_counter_data : bit_vector := "00000000000000000000";
gen3_rxfreqlock_counter : string := "g3_rxfreqlock_count" ;
rstctrl_pld_clr : string := "false";-- "false", "true".
rstctrl_debug_en : string := "false";-- "false", "true".
rstctrl_force_inactive_rst : string := "false";-- "false", "true".
rstctrl_perst_enable : string := "level";-- "level", "neg_edge", "not_used".
hrdrstctrl_en : string := "hrdrstctrl_dis";--"hrdrstctrl_dis", "hrdrstctrl_en".
rstctrl_hip_ep : string := "hip_ep"; --"hip_ep", "hip_not_ep".
rstctrl_hard_block_enable : string := "hard_rst_ctl";--"hard_rst_ctl", "pld_rst_ctl".
rstctrl_rx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_tx_pma_rstb_inv : string := "false";--"false", "true".
rstctrl_rx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pcs_rst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_crst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_srst_n_inv : string := "false";--"false", "true".
rstctrl_altpe3_rst_n_inv : string := "false";--"false", "true".
rstctrl_tx_pma_syncp_inv : string := "false";--"false", "true".
rstctrl_1us_count_fref_clk : string := "rstctrl_1us_cnt";--
rstctrl_1us_count_fref_clk_value : bit_vector := B"00000000000000111111";--
rstctrl_1ms_count_fref_clk : string := "rstctrl_1ms_cnt";--
rstctrl_1ms_count_fref_clk_value : bit_vector := B"00001111010000100100";--
rstctrl_off_cal_done_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_rx_pma_rstb_cmu_select : string := "not_active";-- "ch1cmu_sel", "ch4cmu_sel", "ch4_10cmu_sel", "not_active".
rstctrl_rx_pll_freq_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active", "ch0_phs_sel", "ch01_phs_sel", "ch0123_phs_sel", "ch0123_5678_phs_sel".
rstctrl_mask_tx_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_rx_pll_lock_select : string := "not_active";-- "ch0_sel", "ch01_sel", "ch0123_sel", "ch0123_5678_sel", "not_active".
rstctrl_perstn_select : string := "perstn_pin";-- "perstn_pin", "perstn_pld".
rstctrl_tx_lc_pll_rstb_select : string := "not_active";-- "ch1_out", "ch7_out", "not_active".
rstctrl_fref_clk_select : string := "ch0_sel";-- "ch0_sel", "ch1_sel", "ch2_sel", "ch3_sel", "ch4_sel", "ch5_sel", "ch6_sel", "ch7_sel", "ch8_sel", "ch9_sel", "ch10_sel", "ch11_sel".
rstctrl_off_cal_en_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch0123_5678_out", "not_active".
rstctrl_tx_pma_syncp_select : string := "not_active";-- "ch1_out", "ch4_out", "ch4_10_out", "not_active".
rstctrl_rx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_cmu_pll_lock_select : string := "not_active";-- "ch1_sel", "ch4_sel", "ch4_10_sel", "not_active".
rstctrl_tx_pcs_rst_n_select : string := "not_active";-- "ch0_out", "ch01_out", "ch0123_out", "ch012345678_out", "ch012345678_10_out", "not_active".
rstctrl_tx_lc_pll_lock_select : string := "not_active";-- "ch1_sel", "ch7_sel", "not_active".
rstctrl_timer_a : string := "rstctrl_timer_a";
rstctrl_timer_a_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_a_value : bit_vector := B"00000001" ;
rstctrl_timer_b : string := "rstctrl_timer_b";
rstctrl_timer_b_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_b_value : bit_vector := B"00000001";
rstctrl_timer_c : string := "rstctrl_timer_c";
rstctrl_timer_c_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_c_value : bit_vector := B"00000001";
rstctrl_timer_d : string := "rstctrl_timer_d";
rstctrl_timer_d_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_d_value : bit_vector := B"00000001";
rstctrl_timer_e : string := "rstctrl_timer_e";
rstctrl_timer_e_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_e_value : bit_vector := B"00000001";
rstctrl_timer_f : string := "rstctrl_timer_f";
rstctrl_timer_f_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_f_value : bit_vector := B"00000001";
rstctrl_timer_g : string := "rstctrl_timer_g";
rstctrl_timer_g_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_g_value : bit_vector := B"00000001";
rstctrl_timer_h : string := "rstctrl_timer_h";
rstctrl_timer_h_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_h_value : bit_vector := B"00000001";
rstctrl_timer_i : string := "rstctrl_timer_i";
rstctrl_timer_i_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_i_value : bit_vector := B"00000001";
rstctrl_timer_j : string := "rstctrl_timer_j";
rstctrl_timer_j_type : string := "milli_secs";--possible values are: "not_enabled", "milli_secs", "micro_secs", "fref_cycles"
rstctrl_timer_j_value : bit_vector := B"00000001"
);
port (
dpriostatus : out std_logic_vector(15 downto 0);
lmidout : out std_logic_vector(31 downto 0);
lmiack : out std_logic_vector(0 downto 0);
lmirden : in std_logic_vector(0 downto 0);
lmiwren : in std_logic_vector(0 downto 0);
lmiaddr : in std_logic_vector(11 downto 0);
lmidin : in std_logic_vector(31 downto 0);
flrreset : in std_logic_vector(0 downto 0);
flrsts : out std_logic_vector(0 downto 0);
resetstatus : out std_logic_vector(0 downto 0);
l2exit : out std_logic_vector(0 downto 0);
hotrstexit : out std_logic_vector(0 downto 0);
dlupexit : out std_logic_vector(0 downto 0);
coreclkout : out std_logic_vector(0 downto 0);
pldclk : in std_logic_vector(0 downto 0);
pldsrst : in std_logic_vector(0 downto 0);
pldrst : in std_logic_vector(0 downto 0);
pclkch0 : in std_logic_vector(0 downto 0);
pclkch1 : in std_logic_vector(0 downto 0);
pclkcentral : in std_logic_vector(0 downto 0);
pllfixedclkch0 : in std_logic_vector(0 downto 0);
pllfixedclkch1 : in std_logic_vector(0 downto 0);
pllfixedclkcentral : in std_logic_vector(0 downto 0);
phyrst : in std_logic_vector(0 downto 0);
physrst : in std_logic_vector(0 downto 0);
coreclkin : in std_logic_vector(0 downto 0);
corerst : in std_logic_vector(0 downto 0);
corepor : in std_logic_vector(0 downto 0);
corecrst : in std_logic_vector(0 downto 0);
coresrst : in std_logic_vector(0 downto 0);
swdnout : out std_logic_vector(6 downto 0);
swupout : out std_logic_vector(2 downto 0);
swdnin : in std_logic_vector(2 downto 0);
swupin : in std_logic_vector(6 downto 0);
swctmod : in std_logic_vector(1 downto 0);
rxstdata : out std_logic_vector(255 downto 0);
rxstparity : out std_logic_vector(31 downto 0);
rxstbe : out std_logic_vector(31 downto 0);
rxsterr : out std_logic_vector(3 downto 0);
rxstsop : out std_logic_vector(3 downto 0);
rxsteop : out std_logic_vector(3 downto 0);
rxstempty : out std_logic_vector(1 downto 0);
rxstvalid : out std_logic_vector(3 downto 0);
rxstbardec1 : out std_logic_vector(7 downto 0);
rxstbardec2 : out std_logic_vector(7 downto 0);
rxstmask : in std_logic_vector(0 downto 0);
rxstready : in std_logic_vector(0 downto 0);
txstready : out std_logic_vector(0 downto 0);
txcredfchipcons : out std_logic_vector(5 downto 0);
txcredfcinfinite : out std_logic_vector(5 downto 0);
txcredhdrfcp : out std_logic_vector(7 downto 0);
txcreddatafcp : out std_logic_vector(11 downto 0);
txcredhdrfcnp : out std_logic_vector(7 downto 0);
txcreddatafcnp : out std_logic_vector(11 downto 0);
txcredhdrfccp : out std_logic_vector(7 downto 0);
txcreddatafccp : out std_logic_vector(11 downto 0);
txstdata : in std_logic_vector(255 downto 0);
txstparity : in std_logic_vector(31 downto 0);
txsterr : in std_logic_vector(3 downto 0);
txstsop : in std_logic_vector(3 downto 0);
txsteop : in std_logic_vector(3 downto 0);
txstempty : in std_logic_vector(1 downto 0);
txstvalid : in std_logic_vector(0 downto 0);
r2cuncecc : out std_logic_vector(0 downto 0);
rxcorrecc : out std_logic_vector(0 downto 0);
retryuncecc : out std_logic_vector(0 downto 0);
retrycorrecc : out std_logic_vector(0 downto 0);
rxparerr : out std_logic_vector(0 downto 0);
txparerr : out std_logic_vector(1 downto 0);
r2cparerr : out std_logic_vector(0 downto 0);
pmetosr : out std_logic_vector(0 downto 0);
pmetocr : in std_logic_vector(0 downto 0);
pmevent : in std_logic_vector(0 downto 0);
pmdata : in std_logic_vector(9 downto 0);
pmauxpwr : in std_logic_vector(0 downto 0);
tlcfgsts : out std_logic_vector(52 downto 0);
tlcfgctl : out std_logic_vector(31 downto 0);
tlcfgadd : out std_logic_vector(3 downto 0);
appintaack : out std_logic_vector(0 downto 0);
appintasts : in std_logic_vector(0 downto 0);
intstatus : out std_logic_vector(3 downto 0);
appmsiack : out std_logic_vector(0 downto 0);
appmsireq : in std_logic_vector(0 downto 0);
appmsitc : in std_logic_vector(2 downto 0);
appmsinum : in std_logic_vector(4 downto 0);
aermsinum : in std_logic_vector(4 downto 0);
pexmsinum : in std_logic_vector(4 downto 0);
hpgctrler : in std_logic_vector(4 downto 0);
cfglink2csrpld : in std_logic_vector(12 downto 0);
cfgprmbuspld : in std_logic_vector(7 downto 0);
csebisshadow : out std_logic_vector(0 downto 0);
csebwrdata : out std_logic_vector(31 downto 0);
csebwrdataparity : out std_logic_vector(3 downto 0);
csebbe : out std_logic_vector(3 downto 0);
csebaddr : out std_logic_vector(32 downto 0);
csebaddrparity : out std_logic_vector(4 downto 0);
csebwren : out std_logic_vector(0 downto 0);
csebrden : out std_logic_vector(0 downto 0);
csebwrrespreq : out std_logic_vector(0 downto 0);
csebrddata : in std_logic_vector(31 downto 0);
csebrddataparity : in std_logic_vector(3 downto 0);
csebwaitrequest : in std_logic_vector(0 downto 0);
csebwrrespvalid : in std_logic_vector(0 downto 0);
csebwrresponse : in std_logic_vector(4 downto 0);
csebrdresponse : in std_logic_vector(4 downto 0);
dlup : out std_logic_vector(0 downto 0);
testouthip : out std_logic_vector(255 downto 0);
testout1hip : out std_logic_vector(63 downto 0);
ev1us : out std_logic_vector(0 downto 0);
ev128ns : out std_logic_vector(0 downto 0);
wakeoen : out std_logic_vector(0 downto 0);
serrout : out std_logic_vector(0 downto 0);
ltssmstate : out std_logic_vector(4 downto 0);
laneact : out std_logic_vector(3 downto 0);
currentspeed : out std_logic_vector(1 downto 0);
slotclkcfg : in std_logic_vector(0 downto 0);
mode : in std_logic_vector(1 downto 0);
testinhip : in std_logic_vector(31 downto 0);
testin1hip : in std_logic_vector(31 downto 0);
cplpending : in std_logic_vector(0 downto 0);
cplerr : in std_logic_vector(6 downto 0);
appinterr : in std_logic_vector(1 downto 0);
egressblkerr : in std_logic_vector(0 downto 0);
pmexitd0ack : in std_logic_vector(0 downto 0);
pmexitd0req : out std_logic_vector(0 downto 0);
currentcoeff0 : out std_logic_vector(17 downto 0);
currentcoeff1 : out std_logic_vector(17 downto 0);
currentcoeff2 : out std_logic_vector(17 downto 0);
currentcoeff3 : out std_logic_vector(17 downto 0);
currentcoeff4 : out std_logic_vector(17 downto 0);
currentcoeff5 : out std_logic_vector(17 downto 0);
currentcoeff6 : out std_logic_vector(17 downto 0);
currentcoeff7 : out std_logic_vector(17 downto 0);
currentrxpreset0 : out std_logic_vector(2 downto 0);
currentrxpreset1 : out std_logic_vector(2 downto 0);
currentrxpreset2 : out std_logic_vector(2 downto 0);
currentrxpreset3 : out std_logic_vector(2 downto 0);
currentrxpreset4 : out std_logic_vector(2 downto 0);
currentrxpreset5 : out std_logic_vector(2 downto 0);
currentrxpreset6 : out std_logic_vector(2 downto 0);
currentrxpreset7 : out std_logic_vector(2 downto 0);
rate0 : out std_logic_vector(1 downto 0);
rate1 : out std_logic_vector(1 downto 0);
rate2 : out std_logic_vector(1 downto 0);
rate3 : out std_logic_vector(1 downto 0);
rate4 : out std_logic_vector(1 downto 0);
rate5 : out std_logic_vector(1 downto 0);
rate6 : out std_logic_vector(1 downto 0);
rate7 : out std_logic_vector(1 downto 0);
ratectrl : out std_logic_vector(1 downto 0);
ratetiedtognd : out std_logic_vector(0 downto 0);
eidleinfersel0 : out std_logic_vector(2 downto 0);
eidleinfersel1 : out std_logic_vector(2 downto 0);
eidleinfersel2 : out std_logic_vector(2 downto 0);
eidleinfersel3 : out std_logic_vector(2 downto 0);
eidleinfersel4 : out std_logic_vector(2 downto 0);
eidleinfersel5 : out std_logic_vector(2 downto 0);
eidleinfersel6 : out std_logic_vector(2 downto 0);
eidleinfersel7 : out std_logic_vector(2 downto 0);
txdata0 : out std_logic_vector(31 downto 0);
txdatak0 : out std_logic_vector(3 downto 0);
txdetectrx0 : out std_logic_vector(0 downto 0);
txelecidle0 : out std_logic_vector(0 downto 0);
txcompl0 : out std_logic_vector(0 downto 0);
rxpolarity0 : out std_logic_vector(0 downto 0);
powerdown0 : out std_logic_vector(1 downto 0);
txdataskip0 : out std_logic_vector(0 downto 0);
txblkst0 : out std_logic_vector(0 downto 0);
txsynchd0 : out std_logic_vector(1 downto 0);
txdeemph0 : out std_logic_vector(0 downto 0);
txmargin0 : out std_logic_vector(2 downto 0);
rxdata0 : in std_logic_vector(31 downto 0);
rxdatak0 : in std_logic_vector(3 downto 0);
rxvalid0 : in std_logic_vector(0 downto 0);
phystatus0 : in std_logic_vector(0 downto 0);
rxelecidle0 : in std_logic_vector(0 downto 0);
rxstatus0 : in std_logic_vector(2 downto 0);
rxdataskip0 : in std_logic_vector(0 downto 0);
rxblkst0 : in std_logic_vector(0 downto 0);
rxsynchd0 : in std_logic_vector(1 downto 0);
rxfreqlocked0 : in std_logic_vector(0 downto 0);
txdata1 : out std_logic_vector(31 downto 0);
txdatak1 : out std_logic_vector(3 downto 0);
txdetectrx1 : out std_logic_vector(0 downto 0);
txelecidle1 : out std_logic_vector(0 downto 0);
txcompl1 : out std_logic_vector(0 downto 0);
rxpolarity1 : out std_logic_vector(0 downto 0);
powerdown1 : out std_logic_vector(1 downto 0);
txdataskip1 : out std_logic_vector(0 downto 0);
txblkst1 : out std_logic_vector(0 downto 0);
txsynchd1 : out std_logic_vector(1 downto 0);
txdeemph1 : out std_logic_vector(0 downto 0);
txmargin1 : out std_logic_vector(2 downto 0);
rxdata1 : in std_logic_vector(31 downto 0);
rxdatak1 : in std_logic_vector(3 downto 0);
rxvalid1 : in std_logic_vector(0 downto 0);
phystatus1 : in std_logic_vector(0 downto 0);
rxelecidle1 : in std_logic_vector(0 downto 0);
rxstatus1 : in std_logic_vector(2 downto 0);
rxdataskip1 : in std_logic_vector(0 downto 0);
rxblkst1 : in std_logic_vector(0 downto 0);
rxsynchd1 : in std_logic_vector(1 downto 0);
rxfreqlocked1 : in std_logic_vector(0 downto 0);
txdata2 : out std_logic_vector(31 downto 0);
txdatak2 : out std_logic_vector(3 downto 0);
txdetectrx2 : out std_logic_vector(0 downto 0);
txelecidle2 : out std_logic_vector(0 downto 0);
txcompl2 : out std_logic_vector(0 downto 0);
rxpolarity2 : out std_logic_vector(0 downto 0);
powerdown2 : out std_logic_vector(1 downto 0);
txdataskip2 : out std_logic_vector(0 downto 0);
txblkst2 : out std_logic_vector(0 downto 0);
txsynchd2 : out std_logic_vector(1 downto 0);
txdeemph2 : out std_logic_vector(0 downto 0);
txmargin2 : out std_logic_vector(2 downto 0);
rxdata2 : in std_logic_vector(31 downto 0);
rxdatak2 : in std_logic_vector(3 downto 0);
rxvalid2 : in std_logic_vector(0 downto 0);
phystatus2 : in std_logic_vector(0 downto 0);
rxelecidle2 : in std_logic_vector(0 downto 0);
rxstatus2 : in std_logic_vector(2 downto 0);
rxdataskip2 : in std_logic_vector(0 downto 0);
rxblkst2 : in std_logic_vector(0 downto 0);
rxsynchd2 : in std_logic_vector(1 downto 0);
rxfreqlocked2 : in std_logic_vector(0 downto 0);
txdata3 : out std_logic_vector(31 downto 0);
txdatak3 : out std_logic_vector(3 downto 0);
txdetectrx3 : out std_logic_vector(0 downto 0);
txelecidle3 : out std_logic_vector(0 downto 0);
txcompl3 : out std_logic_vector(0 downto 0);
rxpolarity3 : out std_logic_vector(0 downto 0);
powerdown3 : out std_logic_vector(1 downto 0);
txdataskip3 : out std_logic_vector(0 downto 0);
txblkst3 : out std_logic_vector(0 downto 0);
txsynchd3 : out std_logic_vector(1 downto 0);
txdeemph3 : out std_logic_vector(0 downto 0);
txmargin3 : out std_logic_vector(2 downto 0);
rxdata3 : in std_logic_vector(31 downto 0);
rxdatak3 : in std_logic_vector(3 downto 0);
rxvalid3 : in std_logic_vector(0 downto 0);
phystatus3 : in std_logic_vector(0 downto 0);
rxelecidle3 : in std_logic_vector(0 downto 0);
rxstatus3 : in std_logic_vector(2 downto 0);
rxdataskip3 : in std_logic_vector(0 downto 0);
rxblkst3 : in std_logic_vector(0 downto 0);
rxsynchd3 : in std_logic_vector(1 downto 0);
rxfreqlocked3 : in std_logic_vector(0 downto 0);
txdata4 : out std_logic_vector(31 downto 0);
txdatak4 : out std_logic_vector(3 downto 0);
txdetectrx4 : out std_logic_vector(0 downto 0);
txelecidle4 : out std_logic_vector(0 downto 0);
txcompl4 : out std_logic_vector(0 downto 0);
rxpolarity4 : out std_logic_vector(0 downto 0);
powerdown4 : out std_logic_vector(1 downto 0);
txdataskip4 : out std_logic_vector(0 downto 0);
txblkst4 : out std_logic_vector(0 downto 0);
txsynchd4 : out std_logic_vector(1 downto 0);
txdeemph4 : out std_logic_vector(0 downto 0);
txmargin4 : out std_logic_vector(2 downto 0);
rxdata4 : in std_logic_vector(31 downto 0);
rxdatak4 : in std_logic_vector(3 downto 0);
rxvalid4 : in std_logic_vector(0 downto 0);
phystatus4 : in std_logic_vector(0 downto 0);
rxelecidle4 : in std_logic_vector(0 downto 0);
rxstatus4 : in std_logic_vector(2 downto 0);
rxdataskip4 : in std_logic_vector(0 downto 0);
rxblkst4 : in std_logic_vector(0 downto 0);
rxsynchd4 : in std_logic_vector(1 downto 0);
rxfreqlocked4 : in std_logic_vector(0 downto 0);
txdata5 : out std_logic_vector(31 downto 0);
txdatak5 : out std_logic_vector(3 downto 0);
txdetectrx5 : out std_logic_vector(0 downto 0);
txelecidle5 : out std_logic_vector(0 downto 0);
txcompl5 : out std_logic_vector(0 downto 0);
rxpolarity5 : out std_logic_vector(0 downto 0);
powerdown5 : out std_logic_vector(1 downto 0);
txdataskip5 : out std_logic_vector(0 downto 0);
txblkst5 : out std_logic_vector(0 downto 0);
txsynchd5 : out std_logic_vector(1 downto 0);
txdeemph5 : out std_logic_vector(0 downto 0);
txmargin5 : out std_logic_vector(2 downto 0);
rxdata5 : in std_logic_vector(31 downto 0);
rxdatak5 : in std_logic_vector(3 downto 0);
rxvalid5 : in std_logic_vector(0 downto 0);
phystatus5 : in std_logic_vector(0 downto 0);
rxelecidle5 : in std_logic_vector(0 downto 0);
rxstatus5 : in std_logic_vector(2 downto 0);
rxdataskip5 : in std_logic_vector(0 downto 0);
rxblkst5 : in std_logic_vector(0 downto 0);
rxsynchd5 : in std_logic_vector(1 downto 0);
rxfreqlocked5 : in std_logic_vector(0 downto 0);
txdata6 : out std_logic_vector(31 downto 0);
txdatak6 : out std_logic_vector(3 downto 0);
txdetectrx6 : out std_logic_vector(0 downto 0);
txelecidle6 : out std_logic_vector(0 downto 0);
txcompl6 : out std_logic_vector(0 downto 0);
rxpolarity6 : out std_logic_vector(0 downto 0);
powerdown6 : out std_logic_vector(1 downto 0);
txdataskip6 : out std_logic_vector(0 downto 0);
txblkst6 : out std_logic_vector(0 downto 0);
txsynchd6 : out std_logic_vector(1 downto 0);
txdeemph6 : out std_logic_vector(0 downto 0);
txmargin6 : out std_logic_vector(2 downto 0);
rxdata6 : in std_logic_vector(31 downto 0);
rxdatak6 : in std_logic_vector(3 downto 0);
rxvalid6 : in std_logic_vector(0 downto 0);
phystatus6 : in std_logic_vector(0 downto 0);
rxelecidle6 : in std_logic_vector(0 downto 0);
rxstatus6 : in std_logic_vector(2 downto 0);
rxdataskip6 : in std_logic_vector(0 downto 0);
rxblkst6 : in std_logic_vector(0 downto 0);
rxsynchd6 : in std_logic_vector(1 downto 0);
rxfreqlocked6 : in std_logic_vector(0 downto 0);
txdata7 : out std_logic_vector(31 downto 0);
txdatak7 : out std_logic_vector(3 downto 0);
txdetectrx7 : out std_logic_vector(0 downto 0);
txelecidle7 : out std_logic_vector(0 downto 0);
txcompl7 : out std_logic_vector(0 downto 0);
rxpolarity7 : out std_logic_vector(0 downto 0);
powerdown7 : out std_logic_vector(1 downto 0);
txdataskip7 : out std_logic_vector(0 downto 0);
txblkst7 : out std_logic_vector(0 downto 0);
txsynchd7 : out std_logic_vector(1 downto 0);
txdeemph7 : out std_logic_vector(0 downto 0);
txmargin7 : out std_logic_vector(2 downto 0);
rxdata7 : in std_logic_vector(31 downto 0);
rxdatak7 : in std_logic_vector(3 downto 0);
rxvalid7 : in std_logic_vector(0 downto 0);
phystatus7 : in std_logic_vector(0 downto 0);
rxelecidle7 : in std_logic_vector(0 downto 0);
rxstatus7 : in std_logic_vector(2 downto 0);
rxdataskip7 : in std_logic_vector(0 downto 0);
rxblkst7 : in std_logic_vector(0 downto 0);
rxsynchd7 : in std_logic_vector(1 downto 0);
rxfreqlocked7 : in std_logic_vector(0 downto 0);
dbgpipex1rx : in std_logic_vector(43 downto 0);
memredsclk : in std_logic_vector(0 downto 0);
memredenscan : in std_logic_vector(0 downto 0);
memredscen : in std_logic_vector(0 downto 0);
memredscin : in std_logic_vector(0 downto 0);
memredscsel : in std_logic_vector(0 downto 0);
memredscrst : in std_logic_vector(0 downto 0);
memredscout : out std_logic_vector(0 downto 0);
memregscanen : in std_logic_vector(0 downto 0);
memregscanin : in std_logic_vector(0 downto 0);
memhiptestenable : in std_logic_vector(0 downto 0);
memregscanout : out std_logic_vector(0 downto 0);
bisttesten : in std_logic_vector(0 downto 0);
bistenrpl : in std_logic_vector(0 downto 0);
bistscanin : in std_logic_vector(0 downto 0);
bistscanen : in std_logic_vector(0 downto 0);
bistenrcv : in std_logic_vector(0 downto 0);
bistscanoutrpl : out std_logic_vector(0 downto 0);
bistdonearpl : out std_logic_vector(0 downto 0);
bistdonebrpl : out std_logic_vector(0 downto 0);
bistpassrpl : out std_logic_vector(0 downto 0);
derrrpl : out std_logic_vector(0 downto 0);
derrcorextrpl : out std_logic_vector(0 downto 0);
bistscanoutrcv : out std_logic_vector(0 downto 0);
bistdonearcv : out std_logic_vector(0 downto 0);
bistdonebrcv : out std_logic_vector(0 downto 0);
bistpassrcv : out std_logic_vector(0 downto 0);
derrcorextrcv : out std_logic_vector(0 downto 0);
bistscanoutrcv1 : out std_logic_vector(0 downto 0);
bistdonearcv1 : out std_logic_vector(0 downto 0);
bistdonebrcv1 : out std_logic_vector(0 downto 0);
bistpassrcv1 : out std_logic_vector(0 downto 0);
derrcorextrcv1 : out std_logic_vector(0 downto 0);
scanmoden : in std_logic_vector(0 downto 0);
scanshiftn : in std_logic_vector(0 downto 0);
nfrzdrv : in std_logic_vector(0 downto 0);
frzreg : in std_logic_vector(0 downto 0);
frzlogic : in std_logic_vector(0 downto 0);
idrpl : in std_logic_vector(7 downto 0);
idrcv : in std_logic_vector(7 downto 0);
plniotri : in std_logic_vector(0 downto 0);
entest : in std_logic_vector(0 downto 0);
npor : in std_logic_vector(0 downto 0);
usermode : in std_logic_vector(0 downto 0);
cvpclk : out std_logic_vector(0 downto 0);
cvpdata : out std_logic_vector(31 downto 0);
cvpstartxfer : out std_logic_vector(0 downto 0);
cvpconfig : out std_logic_vector(0 downto 0);
cvpfullconfig : out std_logic_vector(0 downto 0);
cvpconfigready : in std_logic_vector(0 downto 0);
cvpen : in std_logic_vector(0 downto 0);
cvpconfigerror : in std_logic_vector(0 downto 0);
cvpconfigdone : in std_logic_vector(0 downto 0);
pinperstn : in std_logic_vector(0 downto 0);
pldperstn : in std_logic_vector(0 downto 0);
iocsrrdydly : in std_logic_vector(0 downto 0);
softaltpe3rstn : in std_logic_vector(0 downto 0);
softaltpe3srstn : in std_logic_vector(0 downto 0);
softaltpe3crstn : in std_logic_vector(0 downto 0);
pldclrpmapcshipn : in std_logic_vector(0 downto 0);
pldclrpcshipn : in std_logic_vector(0 downto 0);
pldclrhipn : in std_logic_vector(0 downto 0);
s0ch0emsiptieoff : out std_logic_vector(100 downto 0);
s0ch1emsiptieoff : out std_logic_vector(100 downto 0);
s0ch2emsiptieoff : out std_logic_vector(100 downto 0);
s1ch0emsiptieoff : out std_logic_vector(100 downto 0);
s1ch1emsiptieoff : out std_logic_vector(188 downto 0);
s1ch2emsiptieoff : out std_logic_vector(100 downto 0);
s2ch0emsiptieoff : out std_logic_vector(100 downto 0);
s2ch1emsiptieoff : out std_logic_vector(100 downto 0);
s2ch2emsiptieoff : out std_logic_vector(100 downto 0);
s3ch0emsiptieoff : out std_logic_vector(188 downto 0);
s3ch1emsiptieoff : out std_logic_vector(188 downto 0);
s3ch2emsiptieoff : out std_logic_vector(188 downto 0);
emsiptieofftop : out std_logic_vector(299 downto 0);
emsiptieoffbot : out std_logic_vector(299 downto 0);
txpcsrstn0 : out std_logic_vector(0 downto 0);
rxpcsrstn0 : out std_logic_vector(0 downto 0);
g3txpcsrstn0 : out std_logic_vector(0 downto 0);
g3rxpcsrstn0 : out std_logic_vector(0 downto 0);
txpmasyncp0 : out std_logic_vector(0 downto 0);
rxpmarstb0 : out std_logic_vector(0 downto 0);
txlcpllrstb0 : out std_logic_vector(0 downto 0);
offcalen0 : out std_logic_vector(0 downto 0);
frefclk0 : in std_logic_vector(0 downto 0);
offcaldone0 : in std_logic_vector(0 downto 0);
txlcplllock0 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock0 : in std_logic_vector(0 downto 0);
rxpllphaselock0 : in std_logic_vector(0 downto 0);
masktxplllock0 : in std_logic_vector(0 downto 0);
txpcsrstn1 : out std_logic_vector(0 downto 0);
rxpcsrstn1 : out std_logic_vector(0 downto 0);
g3txpcsrstn1 : out std_logic_vector(0 downto 0);
g3rxpcsrstn1 : out std_logic_vector(0 downto 0);
txpmasyncp1 : out std_logic_vector(0 downto 0);
rxpmarstb1 : out std_logic_vector(0 downto 0);
txlcpllrstb1 : out std_logic_vector(0 downto 0);
offcalen1 : out std_logic_vector(0 downto 0);
frefclk1 : in std_logic_vector(0 downto 0);
offcaldone1 : in std_logic_vector(0 downto 0);
txlcplllock1 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock1 : in std_logic_vector(0 downto 0);
rxpllphaselock1 : in std_logic_vector(0 downto 0);
masktxplllock1 : in std_logic_vector(0 downto 0);
txpcsrstn2 : out std_logic_vector(0 downto 0);
rxpcsrstn2 : out std_logic_vector(0 downto 0);
g3txpcsrstn2 : out std_logic_vector(0 downto 0);
g3rxpcsrstn2 : out std_logic_vector(0 downto 0);
txpmasyncp2 : out std_logic_vector(0 downto 0);
rxpmarstb2 : out std_logic_vector(0 downto 0);
txlcpllrstb2 : out std_logic_vector(0 downto 0);
offcalen2 : out std_logic_vector(0 downto 0);
frefclk2 : in std_logic_vector(0 downto 0);
offcaldone2 : in std_logic_vector(0 downto 0);
txlcplllock2 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock2 : in std_logic_vector(0 downto 0);
rxpllphaselock2 : in std_logic_vector(0 downto 0);
masktxplllock2 : in std_logic_vector(0 downto 0);
txpcsrstn3 : out std_logic_vector(0 downto 0);
rxpcsrstn3 : out std_logic_vector(0 downto 0);
g3txpcsrstn3 : out std_logic_vector(0 downto 0);
g3rxpcsrstn3 : out std_logic_vector(0 downto 0);
txpmasyncp3 : out std_logic_vector(0 downto 0);
rxpmarstb3 : out std_logic_vector(0 downto 0);
txlcpllrstb3 : out std_logic_vector(0 downto 0);
offcalen3 : out std_logic_vector(0 downto 0);
frefclk3 : in std_logic_vector(0 downto 0);
offcaldone3 : in std_logic_vector(0 downto 0);
txlcplllock3 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock3 : in std_logic_vector(0 downto 0);
rxpllphaselock3 : in std_logic_vector(0 downto 0);
masktxplllock3 : in std_logic_vector(0 downto 0);
txpcsrstn4 : out std_logic_vector(0 downto 0);
rxpcsrstn4 : out std_logic_vector(0 downto 0);
g3txpcsrstn4 : out std_logic_vector(0 downto 0);
g3rxpcsrstn4 : out std_logic_vector(0 downto 0);
txpmasyncp4 : out std_logic_vector(0 downto 0);
rxpmarstb4 : out std_logic_vector(0 downto 0);
txlcpllrstb4 : out std_logic_vector(0 downto 0);
offcalen4 : out std_logic_vector(0 downto 0);
frefclk4 : in std_logic_vector(0 downto 0);
offcaldone4 : in std_logic_vector(0 downto 0);
txlcplllock4 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock4 : in std_logic_vector(0 downto 0);
rxpllphaselock4 : in std_logic_vector(0 downto 0);
masktxplllock4 : in std_logic_vector(0 downto 0);
txpcsrstn5 : out std_logic_vector(0 downto 0);
rxpcsrstn5 : out std_logic_vector(0 downto 0);
g3txpcsrstn5 : out std_logic_vector(0 downto 0);
g3rxpcsrstn5 : out std_logic_vector(0 downto 0);
txpmasyncp5 : out std_logic_vector(0 downto 0);
rxpmarstb5 : out std_logic_vector(0 downto 0);
txlcpllrstb5 : out std_logic_vector(0 downto 0);
offcalen5 : out std_logic_vector(0 downto 0);
frefclk5 : in std_logic_vector(0 downto 0);
offcaldone5 : in std_logic_vector(0 downto 0);
txlcplllock5 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock5 : in std_logic_vector(0 downto 0);
rxpllphaselock5 : in std_logic_vector(0 downto 0);
masktxplllock5 : in std_logic_vector(0 downto 0);
txpcsrstn6 : out std_logic_vector(0 downto 0);
rxpcsrstn6 : out std_logic_vector(0 downto 0);
g3txpcsrstn6 : out std_logic_vector(0 downto 0);
g3rxpcsrstn6 : out std_logic_vector(0 downto 0);
txpmasyncp6 : out std_logic_vector(0 downto 0);
rxpmarstb6 : out std_logic_vector(0 downto 0);
txlcpllrstb6 : out std_logic_vector(0 downto 0);
offcalen6 : out std_logic_vector(0 downto 0);
frefclk6 : in std_logic_vector(0 downto 0);
offcaldone6 : in std_logic_vector(0 downto 0);
txlcplllock6 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock6 : in std_logic_vector(0 downto 0);
rxpllphaselock6 : in std_logic_vector(0 downto 0);
masktxplllock6 : in std_logic_vector(0 downto 0);
txpcsrstn7 : out std_logic_vector(0 downto 0);
rxpcsrstn7 : out std_logic_vector(0 downto 0);
g3txpcsrstn7 : out std_logic_vector(0 downto 0);
g3rxpcsrstn7 : out std_logic_vector(0 downto 0);
txpmasyncp7 : out std_logic_vector(0 downto 0);
rxpmarstb7 : out std_logic_vector(0 downto 0);
txlcpllrstb7 : out std_logic_vector(0 downto 0);
offcalen7 : out std_logic_vector(0 downto 0);
frefclk7 : in std_logic_vector(0 downto 0);
offcaldone7 : in std_logic_vector(0 downto 0);
txlcplllock7 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock7 : in std_logic_vector(0 downto 0);
rxpllphaselock7 : in std_logic_vector(0 downto 0);
masktxplllock7 : in std_logic_vector(0 downto 0);
txpcsrstn8 : out std_logic_vector(0 downto 0);
rxpcsrstn8 : out std_logic_vector(0 downto 0);
g3txpcsrstn8 : out std_logic_vector(0 downto 0);
g3rxpcsrstn8 : out std_logic_vector(0 downto 0);
txpmasyncp8 : out std_logic_vector(0 downto 0);
rxpmarstb8 : out std_logic_vector(0 downto 0);
txlcpllrstb8 : out std_logic_vector(0 downto 0);
offcalen8 : out std_logic_vector(0 downto 0);
frefclk8 : in std_logic_vector(0 downto 0);
offcaldone8 : in std_logic_vector(0 downto 0);
txlcplllock8 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock8 : in std_logic_vector(0 downto 0);
rxpllphaselock8 : in std_logic_vector(0 downto 0);
masktxplllock8 : in std_logic_vector(0 downto 0);
txpcsrstn9 : out std_logic_vector(0 downto 0);
rxpcsrstn9 : out std_logic_vector(0 downto 0);
g3txpcsrstn9 : out std_logic_vector(0 downto 0);
g3rxpcsrstn9 : out std_logic_vector(0 downto 0);
txpmasyncp9 : out std_logic_vector(0 downto 0);
rxpmarstb9 : out std_logic_vector(0 downto 0);
txlcpllrstb9 : out std_logic_vector(0 downto 0);
offcalen9 : out std_logic_vector(0 downto 0);
frefclk9 : in std_logic_vector(0 downto 0);
offcaldone9 : in std_logic_vector(0 downto 0);
txlcplllock9 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock9 : in std_logic_vector(0 downto 0);
rxpllphaselock9 : in std_logic_vector(0 downto 0);
masktxplllock9 : in std_logic_vector(0 downto 0);
txpcsrstn10 : out std_logic_vector(0 downto 0);
rxpcsrstn10 : out std_logic_vector(0 downto 0);
g3txpcsrstn10 : out std_logic_vector(0 downto 0);
g3rxpcsrstn10 : out std_logic_vector(0 downto 0);
txpmasyncp10 : out std_logic_vector(0 downto 0);
rxpmarstb10 : out std_logic_vector(0 downto 0);
txlcpllrstb10 : out std_logic_vector(0 downto 0);
offcalen10 : out std_logic_vector(0 downto 0);
frefclk10 : in std_logic_vector(0 downto 0);
offcaldone10 : in std_logic_vector(0 downto 0);
txlcplllock10 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock10 : in std_logic_vector(0 downto 0);
rxpllphaselock10 : in std_logic_vector(0 downto 0);
masktxplllock10 : in std_logic_vector(0 downto 0);
txpcsrstn11 : out std_logic_vector(0 downto 0);
rxpcsrstn11 : out std_logic_vector(0 downto 0);
g3txpcsrstn11 : out std_logic_vector(0 downto 0);
g3rxpcsrstn11 : out std_logic_vector(0 downto 0);
txpmasyncp11 : out std_logic_vector(0 downto 0);
rxpmarstb11 : out std_logic_vector(0 downto 0);
txlcpllrstb11 : out std_logic_vector(0 downto 0);
offcalen11 : out std_logic_vector(0 downto 0);
frefclk11 : in std_logic_vector(0 downto 0);
offcaldone11 : in std_logic_vector(0 downto 0);
txlcplllock11 : in std_logic_vector(0 downto 0);
rxfreqtxcmuplllock11 : in std_logic_vector(0 downto 0);
rxpllphaselock11 : in std_logic_vector(0 downto 0);
masktxplllock11 : in std_logic_vector(0 downto 0);
reservedin : in std_logic_vector(31 downto 0);
reservedclkin : in std_logic_vector(0 downto 0);
reservedout : out std_logic_vector(31 downto 0);
reservedclkout : out std_logic_vector(0 downto 0)
);
end component; --stratixv_hssi_gen3_pcie_hip
end STRATIXV_PCIE_HIP_COMPONENTS;
|
package t is
type arr is array (natural range 0 to 7) of bit;
subtype arridx is arr'range;
end t;
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdRxData
-- Target Devices:
-- TOol versions: XilINx ISE 14.4
-- Description:
--
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
entity KbdRxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbd_Data : IN STD_LOGIC;
kbd_clk : IN STD_LOGIC;
Rx_en : IN STD_LOGIC;
dataValid : OUT STD_LOGIC;
busy : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END KbdRxData;
ARCHITECTURE Behavioral OF KbdRxData IS
SIGNAL tmpData11 : std_logic_vecTOr(0 TO 10);
SIGNAL count : std_logic_vecTOr(3 DOWNTO 0);
SIGNAL dataSTOred : std_logic;
SIGNAL startGet : std_logic;
BEGIN
PROCESS (clk,rst)
BEGIN
IF (rst ='1') THEN
dataSTOred <= '0';
startGet <= '0';
count <= (OTHERS=>'0');
tmpData11 <= (OTHERS=>'0');
ELSIF (clk='1' and clk'Event) THEN
IF (Rx_en = '1') THEN
IF (startGet = '0') THEN
IF (kbd_data = '0') THEN
startGet <= '1';
ELSE
startGet <= '0';
END IF;
ELSIF(kbd_clk = '0') THEN
IF (dataSTOred = '0') THEN
count <= count + conv_std_logic_vecTOr(1,count'LENGTH);
tmpData11 <= kbd_Data & tmpData11(0 TO 9);
dataSTOred <= '1';
END IF;
ELSIF(kbd_clk = '1') THEN
dataSTOred <= '0';
IF(count = conv_std_logic_vecTOr(11,count'LENGTH)) THEN
startGet <= '0';
count <= (OTHERS=>'0');
END IF;
END IF;
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
busy <= '0';
dataValid <= '0';
Data <= (OTHERS=>'0');
ELSIF (clk = '1' and clk'Event) THEN
busy <= startGet;
Data <= (OTHERS=>'0');
dataValid <= '0';
IF (count = conv_std_logic_vecTOr(11,count'LENGTH)) and (kbd_clk = '1') THEN
data <= tmpData11(2 TO 9);
dataValid <= '1';
END IF;
END IF;
END PROCESS;
END Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- EngINeer: Ali Diouri
--
-- Create Date: 20:59:21 05/03/2012
-- Design Name:
-- Module Name: KbdCore - Behavioral
-- Project Name: KbdRxData
-- Target Devices:
-- TOol versions: XilINx ISE 14.4
-- Description:
--
-- DepENDencies:
--
-- RevISion:
-- RevISion 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
entity KbdRxData IS
Port (
clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
kbd_Data : IN STD_LOGIC;
kbd_clk : IN STD_LOGIC;
Rx_en : IN STD_LOGIC;
dataValid : OUT STD_LOGIC;
busy : OUT STD_LOGIC;
Data : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END KbdRxData;
ARCHITECTURE Behavioral OF KbdRxData IS
SIGNAL tmpData11 : std_logic_vecTOr(0 TO 10);
SIGNAL count : std_logic_vecTOr(3 DOWNTO 0);
SIGNAL dataSTOred : std_logic;
SIGNAL startGet : std_logic;
BEGIN
PROCESS (clk,rst)
BEGIN
IF (rst ='1') THEN
dataSTOred <= '0';
startGet <= '0';
count <= (OTHERS=>'0');
tmpData11 <= (OTHERS=>'0');
ELSIF (clk='1' and clk'Event) THEN
IF (Rx_en = '1') THEN
IF (startGet = '0') THEN
IF (kbd_data = '0') THEN
startGet <= '1';
ELSE
startGet <= '0';
END IF;
ELSIF(kbd_clk = '0') THEN
IF (dataSTOred = '0') THEN
count <= count + conv_std_logic_vecTOr(1,count'LENGTH);
tmpData11 <= kbd_Data & tmpData11(0 TO 9);
dataSTOred <= '1';
END IF;
ELSIF(kbd_clk = '1') THEN
dataSTOred <= '0';
IF(count = conv_std_logic_vecTOr(11,count'LENGTH)) THEN
startGet <= '0';
count <= (OTHERS=>'0');
END IF;
END IF;
ELSE
END IF;
END IF;
END PROCESS;
PROCESS(rst, clk)
BEGIN
IF(rst = '1') THEN
busy <= '0';
dataValid <= '0';
Data <= (OTHERS=>'0');
ELSIF (clk = '1' and clk'Event) THEN
busy <= startGet;
Data <= (OTHERS=>'0');
dataValid <= '0';
IF (count = conv_std_logic_vecTOr(11,count'LENGTH)) and (kbd_clk = '1') THEN
data <= tmpData11(2 TO 9);
dataValid <= '1';
END IF;
END IF;
END PROCESS;
END Behavioral;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file WatchEvents.vhd when simulating
-- the core, WatchEvents. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY WatchEvents IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE WatchEvents_a OF WatchEvents IS
-- synthesis translate_off
COMPONENT wrapped_WatchEvents
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan3",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_WatchEvents
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END WatchEvents_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file WatchEvents.vhd when simulating
-- the core, WatchEvents. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY WatchEvents IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE WatchEvents_a OF WatchEvents IS
-- synthesis translate_off
COMPONENT wrapped_WatchEvents
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan3",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_WatchEvents
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END WatchEvents_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file WatchEvents.vhd when simulating
-- the core, WatchEvents. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY WatchEvents IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE WatchEvents_a OF WatchEvents IS
-- synthesis translate_off
COMPONENT wrapped_WatchEvents
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan3",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_WatchEvents
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END WatchEvents_a;
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2016 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file WatchEvents.vhd when simulating
-- the core, WatchEvents. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY WatchEvents IS
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END WatchEvents;
ARCHITECTURE WatchEvents_a OF WatchEvents IS
-- synthesis translate_off
COMPONENT wrapped_WatchEvents
PORT (
clk : IN STD_LOGIC;
srst : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(71 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(71 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_WatchEvents USE ENTITY XilinxCoreLib.fifo_generator_v9_3(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 1,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 72,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 72,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "spartan3",
c_full_flags_rst_val => 0,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 0,
c_has_slave_ce => 0,
c_has_srst => 1,
c_has_underflow => 0,
c_has_valid => 0,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 0,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "512x72",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 0,
c_prog_empty_type_rach => 0,
c_prog_empty_type_rdch => 0,
c_prog_empty_type_wach => 0,
c_prog_empty_type_wdch => 0,
c_prog_empty_type_wrch => 0,
c_prog_full_thresh_assert_val => 511,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 510,
c_prog_full_type => 0,
c_prog_full_type_axis => 0,
c_prog_full_type_rach => 0,
c_prog_full_type_rdch => 0,
c_prog_full_type_wach => 0,
c_prog_full_type_wdch => 0,
c_prog_full_type_wrch => 0,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 512,
c_rd_freq => 1,
c_rd_pntr_width => 9,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 1,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 512,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 9,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_WatchEvents
PORT MAP (
clk => clk,
srst => srst,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty
);
-- synthesis translate_on
END WatchEvents_a;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library IEEE;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sum2_e is
generic (k1, k2: real := 1.0); -- Gain multipliers
port ( terminal in1, in2: electrical;
terminal output: electrical);
end entity sum2_e;
architecture simple of sum2_e is
QUANTITY vin1 ACROSS in1 TO ELECTRICAL_REF;
QUANTITY vin2 ACROSS in2 TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k1*vin1 + k2*vin2;
end architecture simple;
--
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.ELECTRICAL_SYSTEMS.all;
entity gain_e is
generic (
k: REAL := 1.0); -- Gain multiplier
port ( terminal input : electrical;
terminal output: electrical);
end entity gain_e;
architecture simple of gain_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
begin
vout == k*vin;
end architecture simple;
--
-------------------------------------------------------------------------------
-- S-Domain Limiter Model
--
-------------------------------------------------------------------------------
library IEEE_proposed; use IEEE_proposed.electrical_systems.all;
entity limiter_2_e is
generic (
limit_high : real := 4.8; -- upper limit
limit_low : real := -4.8); -- lower limit
port (
terminal input: electrical;
terminal output: electrical);
end entity limiter_2_e;
architecture simple of limiter_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
constant slope : real := 1.0e-4;
begin
if vin > limit_high use -- Upper limit exceeded, so limit input signal
vout == limit_high + slope*(vin - limit_high);
elsif vin < limit_low use -- Lower limit exceeded, so limit input signal
vout == limit_low + slope*(vin - limit_low);
else -- No limit exceeded, so pass input signal as is
vout == vin;
end use;
break on vin'above(limit_high), vin'above(limit_low);
end architecture simple;
--
-------------------------------------------------------------------------------
-- Lead-Lag Filter
--
-- Transfer Function:
--
-- (s + w1)
-- H(s) = k * ----------
-- (s + w2)
--
-- DC Gain = k*w1/w2
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lead_lag_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (zero)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lead_lag_e;
architecture simple of lead_lag_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
constant num : real_vector := (w1, 1.0);
constant den : real_vector := (w2, 1.0);
begin
vin_temp == vin;
vout == k*vin_temp'ltf(num, den);
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rudder_servo is
port(
terminal servo_in : electrical;
terminal pos_fb : electrical;
terminal servo_out : electrical
);
end rudder_servo;
architecture rudder_servo of rudder_servo is
-- Component declarations
-- Signal declarations
terminal error : electrical;
terminal ll_in : electrical;
terminal ll_out : electrical;
terminal summer_fb : electrical;
begin
-- Signal assignments
-- Component instances
summer : entity work.sum2_e(simple)
port map(
in1 => servo_in,
in2 => summer_fb,
output => error
);
forward_gain : entity work.gain_e(simple)
generic map(
k => 100.0
)
port map(
input => error,
output => ll_in
);
fb_gain : entity work.gain_e(simple)
generic map(
k => -4.57
)
port map(
input => pos_fb,
output => summer_fb
);
servo_limiter : entity work.limiter_2_e(simple)
generic map(
limit_high => 4.8,
limit_low => -4.8
)
port map(
input => ll_out,
output => servo_out
);
lead_lag : entity work.lead_lag_e(simple)
generic map(
k => 400.0,
f1 => 5.0,
f2 => 2000.0
)
port map(
input => ll_in,
output => ll_out
);
end rudder_servo;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : gear_rv_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2019-12-30
-------------------------------------------------------------------------------
-- Description: Gear Model (ROTATIONAL_V/ROTATIONAL domains)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/10/10 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity gear_rv_r is
generic(
ratio : real := 1.0); -- Gear ratio (Revs of shaft2 for 1 rev of shaft1)
-- Note: can be negative, if shaft polarity changes
port ( terminal rotv1 : rotational_v;
terminal rot2 : rotational);
end entity gear_rv_r;
-------------------------------------------------------------------------------
-- Ideal Architecture
-------------------------------------------------------------------------------
architecture ideal of gear_rv_r is
quantity w1 across torq_vel through rotv1 to rotational_v_ref;
-- quantity w2 across torq2 through rotv2 to rotational_v_ref;
quantity theta across torq_ang through rot2 to rotational_ref;
begin
-- w2 == w1*ratio;
theta == ratio*w1'integ;
torq_vel == -1.0*torq_ang*ratio;
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Rotational to Electrical Converter
--
-------------------------------------------------------------------------------
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity rot2v is
generic (
k : real := 1.0); -- optional gain
port (
terminal input : rotational; -- input terminal
terminal output : electrical); -- output terminal
end entity rot2v ;
architecture bhv of rot2v is
quantity rot_in across input to rotational_ref; -- Converter's input branch
quantity v_out across out_i through output to electrical_ref;-- Converter's output branch
begin -- bhv
v_out == k*rot_in;
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- tran = R*sin(rot)
--
-- Where pos = output translational position,
-- R = horn radius,
-- theta = input rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_r2t is
generic (
R : real := 1.0); -- horn radius
port (
terminal theta : ROTATIONAL; -- input angular position port
terminal pos : TRANSLATIONAL); -- output translational position port
end entity horn_r2t;
architecture bhv of horn_r2t is
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
begin -- bhv
tran == R*sin(rot); -- Convert angle in to translational out
tran_frc == -rot_tq/R; -- Convert torque in to force out
end bhv;
--
-------------------------------------------------------------------------------
-- Control Horn for Rudder Control (mechanical implementation)
--
-- Transfer Function:
--
-- theta = arcsin(pos/R)
--
-- Where pos = input translational position,
-- R = horn radius,
-- theta = output rotational angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity horn_t2r is
generic (
R : real := 1.0); -- Rudder horn radius
port (
terminal pos : translational; -- input translational position port
terminal theta : rotational); -- output angular position port
end entity horn_t2r ;
architecture bhv of horn_t2r is
QUANTITY tran across tran_frc through pos TO TRANSLATIONAL_REF;
QUANTITY rot across rot_tq through theta TO ROTATIONAL_REF;
begin -- bhv
rot == arcsin(tran/R); -- Convert translational to angle
rot_tq == -tran_frc*R; -- Convert force to torque
end bhv;
--
library IEEE;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity tran_linkage is
port
(
terminal p1, p2 : translational
);
begin
end tran_linkage;
architecture a1 of tran_linkage is
QUANTITY pos_1 across frc_1 through p1 TO translational_ref;
QUANTITY pos_2 across frc_2 through p2 TO translational_ref;
begin
pos_2 == pos_1; -- Pass position
frc_2 == -frc_1; -- Pass force
end;
--
-------------------------------------------------------------------------------
-- Rudder Model (Rotational Spring)
--
-- Transfer Function:
--
-- torq = -k*(theta - theta_0)
--
-- Where theta = input rotational angle,
-- torq = output rotational angle,
-- theta_0 = reference angle
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE;
use ieee.math_real.all;
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
entity rudder is
generic (
k : real := 1.0; -- Spring constant
theta_0 : real := 0.0);
port (
terminal rot : rotational); -- input rotational angle
end entity rudder;
architecture bhv of rudder is
QUANTITY theta across torq through rot TO ROTATIONAL_REF;
begin -- bhv
torq == k*(theta - theta_0); -- Convert force to torque
end bhv;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Constant Voltage Source (Includes Frequency Domain settings)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY v_constant IS
-- Initialize parameters
GENERIC (
level : VOLTAGE; -- Constant voltage value (V)
ac_mag : VOLTAGE := 1.0; -- AC magnitude (V)
ac_phase : real := 0.0); -- AC phase (degrees)
-- Define ports as electrical terminals
PORT (
TERMINAL pos, neg : ELECTRICAL);
END ENTITY v_constant;
-- Ideal Architecture (I = constant)
ARCHITECTURE ideal OF v_constant IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH pos TO neg;
-- Declare quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
IF DOMAIN = QUIESCENT_DOMAIN or DOMAIN = TIME_DOMAIN USE
v == level;
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical sinusoidal voltage source (stick.vhd)
LIBRARY IEEE;
USE IEEE.MATH_REAL.ALL;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY stick IS
-- Initialize parameters
GENERIC (
freq : real; -- frequency, [Hertz]
amplitude : real; -- amplitude, [Volt]
phase : real := 0.0; -- initial phase, [Degree]
offset : real := 0.0; -- DC value, [Volt]
df : real := 0.0; -- damping factor, [1/second]
ac_mag : real := 1.0; -- AC magnitude, [Volt]
ac_phase : real := 0.0); -- AC phase, [Degree]
-- Define ports as electrical terminals
PORT (
TERMINAL v_out : ELECTRICAL);
END ENTITY stick;
-- Ideal Architecture
ARCHITECTURE ideal OF stick IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH v_out TO electrical_ref;
-- Declare Quantity for Phase in radians (calculated below)
QUANTITY phase_rad : real;
-- Declare Quantity in frequency domain for AC analysis
QUANTITY ac_spec : real SPECTRUM ac_mag, math_2_pi*ac_phase/360.0;
BEGIN
-- Convert phase to radians
phase_rad == math_2_pi *(freq * NOW + phase / 360.0);
IF DOMAIN = QUIESCENT_DOMAIN OR DOMAIN = TIME_DOMAIN USE
v == offset + amplitude * sin(phase_rad) * EXP(-NOW * df);
ELSE
v == ac_spec; -- used for Frequency (AC) analysis
END USE;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity RF_xmtr_rcvr is
generic (td : time := 0 ns);
port
(
tdm_in : in std_logic ;
tdm_out : out std_logic
);
end RF_xmtr_rcvr;
architecture behavioral of RF_xmtr_rcvr is
begin
tdm_out <= tdm_in after td;
end;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Simple Digital-Controlled Two-position Switch Model
-- Switch position 1 ('0') or switch position 2 ('1')
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
use IEEE.std_logic_arith.all;
use IEEE.math_real.all;
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY switch_dig_2in is
GENERIC (r_open : RESISTANCE := 1.0e6; -- Open switch resistance
r_closed : RESISTANCE := 0.001; -- Closed switch resistance
trans_time : real := 0.00001); -- Transition time to each position
PORT (sw_state : in std_logic; -- Digital control input
TERMINAL p_in1, p_in2, p_out : ELECTRICAL); -- Analog output
END ENTITY switch_dig_2in;
ARCHITECTURE ideal OF switch_dig_2in IS
-- CONSTANT log_r_open : real := log10(r_open);
-- CONSTANT log_r_closed : real := log10(r_closed);
-- SIGNAL r_sig1 : RESISTANCE := log_r_closed; -- Variable to accept switch resistance
-- SIGNAL r_sig2 : RESISTANCE := log_r_open; -- Variable to accept switch resistance
SIGNAL r_sig1 : RESISTANCE := r_closed; -- Variable to accept switch resistance
SIGNAL r_sig2 : RESISTANCE := r_open; -- Variable to accept switch resistance
QUANTITY v1 ACROSS i1 THROUGH p_in1 TO p_out; -- V & I for in1 to out
QUANTITY v2 ACROSS i2 THROUGH p_in2 TO p_out; -- V & I for in2 to out
QUANTITY r1 : RESISTANCE; -- Time-varying resistance for in1 to out
QUANTITY r2 : RESISTANCE; -- Time-varying resistance for in2 to out
BEGIN
PROCESS (sw_state) -- Sensitivity to digital control input
BEGIN
IF (sw_state'event AND sw_state = '0') THEN -- Close sig1, open sig2
r_sig1 <= r_closed;
r_sig2 <= r_open;
ELSIF (sw_state'event AND sw_state = '1') THEN -- Open sig1, close sig2
r_sig1 <= r_open;
r_sig2 <= r_closed;
END IF;
END PROCESS;
r1 == r_sig1'ramp(trans_time, trans_time); -- Ensure resistance continuity
r2 == r_sig2'ramp(trans_time, trans_time); -- Ensure resistance continuity
v1 == r1*i1; -- Apply Ohm's law to in1
v2 == r2*i2; -- Apply Ohm's law to in2
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Digital clock with 50% duty cycle
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock IS
GENERIC (
period : time); -- Clock period
PORT (
clk_out : OUT std_logic);
END ENTITY clock;
ARCHITECTURE ideal OF clock IS
BEGIN
-- clock process
process
begin
clk_out <= '0';
wait for period/2;
clk_out <= '1';
wait for period/2;
end process;
END ARCHITECTURE ideal;
--
-- This digital clock allows user to specify the duty cycle using
-- the parameters "on_time" and "off_time"
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY clock_duty IS
GENERIC (
on_time : time := 20 us;
off_time : time := 19.98 ms
);
PORT (
clock_out : OUT std_logic := '0');
END ENTITY clock_duty;
ARCHITECTURE ideal OF clock_duty IS
BEGIN
-- clock process
process
begin
clock_out <= '1';
wait for on_time;
clock_out <= '0';
wait for off_time;
end process;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity rc_clk is
port(
clk_100k : out std_logic;
clk_6K : out std_logic;
clk_50 : out std_logic
);
end rc_clk;
architecture rc_clk of rc_clk is
-- Component declarations
-- Signal declarations
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.clock(ideal)
generic map(
period => 10 us
)
port map(
CLK_OUT => clk_100k
);
XCMP2 : entity work.clock(ideal)
generic map(
period => 150 us
)
port map(
CLK_OUT => clk_6K
);
clk_50Hz : entity work.clock_duty(ideal)
generic map(
on_time => 20 us,
off_time => 19.98 ms
)
port map(
CLOCK_OUT => clk_50
);
end rc_clk;
--
-- This model counts the number of input clock transitions and outputs
-- a '1' when this number equals the value of the user-defined constant 'count'
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity bit_cnt is
generic (
count : integer -- User-defined value to count up to
);
port
(
bit_in : in std_logic ;
clk : in std_logic ;
dly_out : out std_logic
);
end bit_cnt;
architecture behavioral of bit_cnt is
begin
serial_clock : process is
begin
wait until bit_in'event AND (bit_in = '1' OR bit_in = 'H');
FOR i IN 0 to count LOOP -- Loop for 'count' clock transitions
wait until clk'event AND (clk = '1' OR clk = 'H');
END LOOP ;
dly_out <= '1'; -- After count is reached, set output high
wait until bit_in'event AND (bit_in = '0' OR bit_in = 'L');
dly_out <= '0'; -- Reset output to '0' on next clock input
end process serial_clock;
end;
--
--//////////////////////////////////////////////////////////////////
-- NOTE: This is an intermediate file for HDL inspection only.
-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach1.sdg.
-- Generated by sde2hdl version 16.1.0.2
--//////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
ENTITY state_mach1 IS
PORT (
a2d_eoc : IN std_logic;
clk_50 : IN std_logic;
clk_100k : IN std_logic;
clk_6k : IN std_logic;
ser_done : IN std_logic;
ch_sel : OUT std_logic;
frm_gen : OUT std_logic;
a2d_oe : OUT std_logic;
a2d_start : OUT std_logic;
p2s_oe : OUT std_logic;
p2s_load : OUT std_logic;
parity_oe : OUT std_logic;
ser_cnt : OUT std_logic;
p2s_clr : OUT std_logic);
END state_mach1;
ARCHITECTURE state_diagram OF state_mach1 IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach1_sm1 IS (V_begin, frm_rd, ser_oe, ch1, data_en, tdm_oe, ch2
, load, ad_ch2, delay);
SIGNAL CS_state_mach1_sm1, NS_state_mach1_sm1 : TYP_state_mach1_sm1;
SIGNAL FB_frm_gen : std_logic;
SIGNAL FB_p2s_load : std_logic;
SIGNAL FB_ch_sel : std_logic;
BEGIN
frm_gen <= FB_frm_gen ;
p2s_load <= FB_p2s_load ;
ch_sel <= FB_ch_sel ;
sm1:
PROCESS (CS_state_mach1_sm1, clk_50, FB_frm_gen, FB_p2s_load, ser_done, a2d_eoc, FB_ch_sel)
BEGIN
CASE CS_state_mach1_sm1 IS
WHEN V_begin =>
FB_frm_gen <= ('1');
a2d_start <= ('0');
a2d_oe <= ('0');
FB_p2s_load <= ('0');
p2s_clr <= ('0');
p2s_oe <= ('0');
FB_ch_sel <= ('0');
parity_oe <= ('0');
ser_cnt <= ('0');
IF ((FB_frm_gen = '1')) THEN
NS_state_mach1_sm1 <= frm_rd;
ELSE
NS_state_mach1_sm1 <= V_begin;
END IF;
WHEN frm_rd =>
FB_p2s_load <= ('1');
IF ((FB_p2s_load = '1')) THEN
NS_state_mach1_sm1 <= ser_oe;
ELSE
NS_state_mach1_sm1 <= frm_rd;
END IF;
WHEN ser_oe =>
p2s_oe <= ('1');
FB_frm_gen <= ('0');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF ((ser_done = '1')) THEN
NS_state_mach1_sm1 <= ch1;
ELSE
NS_state_mach1_sm1 <= ser_oe;
END IF;
WHEN ch1 =>
p2s_oe <= ('0');
FB_ch_sel <= ('0');
a2d_start <= ('1');
ser_cnt <= ('0');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ch1;
END IF;
WHEN data_en =>
a2d_start <= ('0');
a2d_oe <= ('1');
parity_oe <= ('1');
NS_state_mach1_sm1 <= load;
WHEN tdm_oe =>
a2d_oe <= ('0');
parity_oe <= ('0');
p2s_oe <= ('1');
FB_p2s_load <= ('0');
ser_cnt <= ('1');
IF (((ser_done = '1') AND (FB_ch_sel = '0'))) THEN
NS_state_mach1_sm1 <= ch2;
ELSE
NS_state_mach1_sm1 <= tdm_oe;
END IF;
WHEN ch2 =>
p2s_oe <= ('0');
ser_cnt <= ('0');
FB_ch_sel <= ('1');
NS_state_mach1_sm1 <= delay;
WHEN load =>
FB_p2s_load <= ('1');
NS_state_mach1_sm1 <= tdm_oe;
WHEN ad_ch2 =>
a2d_start <= ('1');
IF ((a2d_eoc = '1')) THEN
NS_state_mach1_sm1 <= data_en;
ELSE
NS_state_mach1_sm1 <= ad_ch2;
END IF;
WHEN delay =>
NS_state_mach1_sm1 <= ad_ch2;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach1_sm1 <= V_begin;
ELSE
CS_state_mach1_sm1 <= NS_state_mach1_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt is
port(
a2d_eoc : in std_logic;
clk_50 : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
p2s_load : out std_logic;
p2s_oe : out std_logic;
parity_oe : out std_logic;
a2d_start : out std_logic;
a2d_oe : out std_logic;
frm_gen : out std_logic;
ch_sel : out std_logic;
p2s_clr : out std_logic
);
end sm_cnt;
architecture sm_cnt of sm_cnt is
-- Component declarations
-- Signal declarations
signal ser_done : std_logic;
signal serial_cnt : std_logic;
begin
-- Signal assignments
-- Component instances
bit_cnt1 : entity work.bit_cnt(behavioral)
generic map(
count => 15
)
port map(
bit_in => serial_cnt,
clk => clk_6k,
dly_out => ser_done
);
state_mach16 : entity work.state_mach1
port map(
ser_cnt => serial_cnt,
ch_sel => ch_sel,
frm_gen => frm_gen,
a2d_oe => a2d_oe,
a2d_start => a2d_start,
parity_oe => parity_oe,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
p2s_clr => p2s_clr,
clk_6k => clk_6k,
clk_100k => clk_100k,
clk_50 => clk_50,
a2d_eoc => a2d_eoc,
ser_done => ser_done
);
end sm_cnt;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Analog to Digital Converter (Successive Aproximation Register) model with sar architecture (a2d_nbit.vhd)
--DESCRIPTION:
--
--This is a VHDL-AMS model of a simple analog to digital converter. The model
--describes the general behavior of A/D converters for system level design and
--verification.
--The format of the digital output is binary coding.
--
--N.B, dout(n-1) is the MSB while dout(0) is the LSB.
--
-- Use IEEE natures and packages
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity a2d_nbit is
generic (
Vmax: REAL := 5.0 ; -- ADC's maximum range
Nbits: INTEGER := 10 ; -- number bits in ADC's output
delay: TIME := 10 us -- ADC's conversion time
);
port (
signal start: in std_logic ; -- Start signal
signal clk: in std_logic ; -- Strobe clock
signal oe: in std_logic ; -- Output enable
terminal ain: ELECTRICAL ; -- ADC's analog input terminal
signal eoc: out std_logic := '0' ; -- End Of Conversion pin
signal dout: out std_logic_vector(0 to (Nbits-1))); -- ADC's digital output signal
end entity a2d_nbit;
architecture sar of a2d_nbit is
type states is (input, convert, output) ; -- Three states of A2D Conversion
constant bit_range : INTEGER := Nbits-1 ; -- Bit range for dtmp and dout
quantity Vin across Iin through ain to electrical_ref; -- ADC's input branch
begin
sa_adc: process
variable thresh: REAL := Vmax ; -- Threshold to test input voltage against
variable Vtmp: REAL := Vin ; -- Snapshot of input voltage when conversion starts
variable dtmp: std_logic_vector(0 to (Nbits-1)); -- Temp. output data
variable status: states := input ; -- Begin with "input" CASE
variable bit_cnt: integer := Nbits -1 ;
begin
CASE status is
when input => -- Read input voltages when start goes high
wait on start until start = '1' or start = 'H' ;
thresh := Vmax ;
Vtmp := Vin ;
eoc <= '0' ;
status := convert ; -- Go to convert state
when convert => -- Begin successive approximation conversion
thresh := thresh / 2.0 ; -- Get value of MSB
wait on clk until clk = '1' OR clk = 'H';
if Vtmp > thresh then
dtmp(bit_cnt) := '1' ;
Vtmp := Vtmp - thresh ;
else
dtmp(bit_cnt) := '0' ;
end if ;
bit_cnt := bit_cnt - 1 ;
if (bit_cnt + 1) < 1 then
status := output ; -- Go to output state
end if;
when output => -- Wait for output enable, then put data on output pins
eoc <= '1' after delay ;
wait on oe until oe = '1' OR oe = 'H' ;
FOR i in bit_range DOWNTO 0 LOOP
dout(i) <= dtmp(i) ;
END LOOP ;
wait on oe until oe = '0' OR oe = 'L' ; -- Hi Z when OE is low
FOR i in bit_range DOWNTO 0 LOOP
dout <= "ZZZZZZZZZZ" ;
END LOOP ;
bit_cnt := bit_range ;
status := input ; -- Set up for next conversion
END CASE ;
end process sa_adc ;
Iin == 0.0 ; -- Ideal input draws no current
end architecture sar ;
--
-- Parallel input/serial output shift register
-- With 4 trailing zeros
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity shift_reg is
generic ( td : time := 0 ns);
port
(
bus_in : in std_logic_vector ; -- Input bus
clk : in std_logic ; -- Shift clock
oe : in std_logic ; -- Output enable
ser_out : out std_logic := '0'; -- Output port
load : in std_logic ; -- Parallel input load
clr : in std_logic -- Clear register
);
end entity shift_reg;
architecture behavioral of shift_reg is
begin
control_proc : process
VARIABLE bit_val : std_logic_vector(11 downto 0); -- Default 12-bit input
begin
IF (clr = '1' OR clr = 'H') then
bit_val := "000000000000"; -- Set all input bits to zero
ELSE
wait until load'event AND (load = '1' OR load = 'H');
FOR i IN bus_in'high DOWNTO bus_in'low LOOP
bit_val(i) := bus_in(i) ; -- Transfer input data to variable
END LOOP ;
END IF;
wait until oe'event AND (oe = '1' OR oe = 'H'); -- Shift if output enabled
FOR i IN bit_val'high DOWNTO bit_val'low LOOP
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= bit_val(i) ;
END LOOP ;
FOR i IN 1 TO 4 LOOP -- This loop pads the serial output with 4 zeros
wait until clk'event AND (clk = '1' OR clk = 'H');
ser_out <= '0';
END LOOP;
END process;
end architecture behavioral;
--
-- This model generates a 12-bit data frame synchronization code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_gen is
port
(
oe : in std_logic := '0';
sync_out : out std_logic_vector (11 downto 0) := "ZZZZZZZZZZZZ");
end entity frame_gen;
architecture simple of frame_gen is
begin
enbl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
sync_out <= "010101010101"; -- Sync code
ELSE
sync_out <= "ZZZZZZZZZZZZ";
END IF;
END PROCESS;
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input XOR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY xor2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY xor2;
ARCHITECTURE ideal OF xor2 IS
BEGIN
output <= in1 XOR in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- level_set_tri.vhd
-- If OE = '1' set digital output "level" with parameter "logic_val" (default is 'Z')
-- If OE = '0' set output to high impedance
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set_tri IS
GENERIC (
logic_val : std_logic := 'Z');
PORT (
OE : IN std_logic;
level : OUT std_logic := 'Z');
END ENTITY level_set_tri;
-- Simple architecture
ARCHITECTURE ideal OF level_set_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE;
IF OE = '1' THEN
level <= logic_val;
ELSE
level <= 'Z';
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Simple Tri-state Buffer with delay time
-- If OE = 1, output = input after delay
-- If OE /= 1, output = Z after delay
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY buffer_tri IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
OE : IN std_logic;
output : OUT std_logic);
END ENTITY buffer_tri;
ARCHITECTURE ideal OF buffer_tri IS
BEGIN
oe_ctl: PROCESS
BEGIN
WAIT ON OE, input;
IF OE = '1' THEN
output <= input AFTER delay;
ELSE
output <= 'Z' AFTER delay;
END IF;
END PROCESS;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- ideal one bit D/A converter
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
ENTITY d2a_bit IS
GENERIC (vlow : real :=0.0; -- output high voltage
vhigh : real :=5.0); -- output low voltage
PORT (D : IN std_logic; -- digital (std_logic) intout
TERMINAL A : electrical); -- analog (electrical) output
END ENTITY d2a_bit;
ARCHITECTURE ideal OF d2a_bit IS
QUANTITY vout ACROSS iout THROUGH A TO ELECTRICAL_REF;
SIGNAL vin : real := 0.0;
BEGIN
vin <= vhigh WHEN D = '1' ELSE vlow;
-- Use 'RAMP for discontinuous signal
vout == vin'RAMP(1.0e-9);
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_gen is
port(
parity : in std_logic_vector(1 to 10);
oe : in std_logic;
parity_out : out std_logic_vector(0 to 11)
);
end parity_gen;
architecture parity_gen of parity_gen is
-- Component declarations
-- Signal declarations
terminal par_bit_gen_a : electrical;
signal XSIG010002 : std_logic;
signal XSIG010003 : std_logic;
signal XSIG010004 : std_logic;
signal XSIG010005 : std_logic;
signal XSIG010006 : std_logic;
signal XSIG010007 : std_logic;
signal XSIG010008 : std_logic;
signal XSIG010009 : std_logic;
signal XSIG010098 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => parity(1),
in2 => parity(2),
output => XSIG010002
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => parity(3),
in2 => parity(4),
output => XSIG010003
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => parity(5),
in2 => parity(6),
output => XSIG010004
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => parity(7),
in2 => parity(8),
output => XSIG010005
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => parity(9),
in2 => parity(10),
output => XSIG010008
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010002,
in2 => XSIG010003,
output => XSIG010006
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010004,
in2 => XSIG010005,
output => XSIG010007
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010006,
in2 => XSIG010007,
output => XSIG010009
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010009,
in2 => XSIG010008,
output => XSIG010098
);
XCMP18 : entity work.level_set_tri(ideal)
generic map(
logic_val => '1'
)
port map(
level => parity_out(11),
oe => oe
);
XCMP19 : entity work.buffer_tri(ideal)
port map(
input => parity(1),
output => parity_out(1),
oe => oe
);
XCMP20 : entity work.buffer_tri(ideal)
port map(
input => parity(2),
output => parity_out(2),
oe => oe
);
XCMP21 : entity work.buffer_tri(ideal)
port map(
input => parity(3),
output => parity_out(3),
oe => oe
);
XCMP22 : entity work.buffer_tri(ideal)
port map(
input => parity(4),
output => parity_out(4),
oe => oe
);
XCMP23 : entity work.buffer_tri(ideal)
port map(
input => parity(5),
output => parity_out(5),
oe => oe
);
XCMP24 : entity work.buffer_tri(ideal)
port map(
input => parity(6),
output => parity_out(6),
oe => oe
);
XCMP25 : entity work.buffer_tri(ideal)
port map(
input => parity(7),
output => parity_out(7),
oe => oe
);
XCMP26 : entity work.buffer_tri(ideal)
port map(
input => parity(8),
output => parity_out(8),
oe => oe
);
XCMP27 : entity work.buffer_tri(ideal)
port map(
input => parity(9),
output => parity_out(9),
oe => oe
);
XCMP28 : entity work.buffer_tri(ideal)
port map(
input => parity(10),
output => parity_out(10),
oe => oe
);
XCMP29 : entity work.buffer_tri(ideal)
port map(
input => XSIG010098,
output => parity_out(0),
oe => oe
);
XCMP30 : entity work.d2a_bit(ideal)
port map(
D => XSIG010098,
A => par_bit_gen_a
);
end parity_gen;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tdm_encoder is
port(
clk : in std_logic;
p2s_oe : in std_logic;
p2s_load : in std_logic;
frm_gen : in std_logic;
parity_oe : in std_logic;
tdm_out : out std_logic;
p2s_clr : in std_logic;
a2d_data : in std_logic_vector(1 to 10)
);
end tdm_encoder;
architecture tdm_encoder of tdm_encoder is
-- Component declarations
-- Signal declarations
signal sync_par : std_logic_vector(0 to 11);
begin
-- Signal assignments
-- Component instances
p2s1 : entity work.shift_reg(behavioral)
port map(
bus_in => sync_par,
clk => clk,
oe => p2s_oe,
ser_out => tdm_out,
load => p2s_load,
clr => p2s_clr
);
sync_gen1 : entity work.frame_gen(simple)
port map(
oe => frm_gen,
sync_out => sync_par
);
par_gen1 : entity work.parity_gen
port map(
parity => a2d_data,
parity_out => sync_par,
oe => parity_oe
);
end tdm_encoder;
--
-- Manchester Encoder
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY menc_rsc IS
port ( dig_in : in STD_LOGIC; -- digital input
clk : in STD_LOGIC; -- TX internal clock
reset: in STD_LOGIC; -- not reset
-- bit_out : inout real); -- real output
bit_out : out std_logic); -- real output
END ENTITY menc_rsc;
ARCHITECTURE bhv OF menc_rsc IS
-- signal bhigh:real:= 1.0; -- bit encoding
-- signal blow:real:= -1.0; -- bit encoding
-- signal bnormal:real:=0.0; -- bit encoding
signal bit1:STD_LOGIC;
signal bhigh:std_logic:= '1'; -- bit encoding
signal blow:std_logic:= '0'; -- bit encoding
begin
-- proc1: process (dig_in, clk, bit1,bhigh,blow,bnormal)
proc1: process (dig_in, clk, bit1,bhigh,blow)
begin
if (reset = '1') then
bit1 <= '0';
else
bit1 <= dig_in XOR clk; -- manchester encoding
end if;
if (bit1 = '1') then
bit_out <= bhigh;
else
bit_out <= blow;
-- elsif bit1 = '0' then
-- bit_out <= blow;
-- else
-- bit_out <= bnormal;
end if;
end process;
end architecture bhv;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Digitize_Encode_Man is
port(
tdm_out : out std_logic;
terminal ch1_in : electrical;
terminal ch2_in : electrical
);
end Digitize_Encode_Man;
architecture Digitize_Encode_Man of Digitize_Encode_Man is
-- Component declarations
-- Signal declarations
terminal a2d_ana_in : electrical;
signal ch_bus : std_logic_vector(1 to 10);
signal clk_6K : std_logic;
signal dig_in : std_logic;
signal frm_gen_ctl : std_logic;
signal p2s_clr : std_logic;
signal p2s_load : std_logic;
signal p2s_oe : std_logic;
signal par_oe : std_logic;
signal reset : std_logic;
signal reset_m : std_logic;
signal start_a2d1 : std_logic;
signal sw_ctl : std_logic;
signal XSIG010091 : std_logic;
signal XSIG010190 : std_logic;
signal XSIG010196 : std_logic;
begin
-- Signal assignments
-- Component instances
A_SWITCH1 : entity work.switch_dig_2in(ideal)
port map(
p_in1 => ch1_in,
p_out => a2d_ana_in,
sw_state => sw_ctl,
p_in2 => ch2_in
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => reset,
clk_6K => clk_6K,
clk_100k => XSIG010190
);
sm_xmtr1 : entity work.sm_cnt
port map(
clk_100k => XSIG010190,
a2d_start => start_a2d1,
a2d_eoc => XSIG010091,
p2s_oe => p2s_oe,
p2s_load => p2s_load,
ch_sel => sw_ctl,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
a2d_oe => XSIG010196,
clk_50 => reset,
clk_6k => clk_6K,
p2s_clr => p2s_clr
);
a2d1 : entity work.a2d_nbit(sar)
generic map(
Vmax => 4.8
)
port map(
dout => ch_bus,
ain => a2d_ana_in,
clk => XSIG010190,
start => start_a2d1,
eoc => XSIG010091,
oe => XSIG010196
);
tdm_enc1 : entity work.tdm_encoder
port map(
clk => clk_6K,
p2s_oe => p2s_oe,
tdm_out => dig_in,
p2s_load => p2s_load,
a2d_data => ch_bus,
frm_gen => frm_gen_ctl,
parity_oe => par_oe,
p2s_clr => p2s_clr
);
menc_rsc3 : entity work.menc_rsc(bhv)
port map(
dig_in => dig_in,
clk => clk_6K,
reset => reset_m,
bit_out => tdm_out
);
XCMP90 : entity work.clock_duty(ideal)
generic map(
off_time => 19.98 sec
)
port map(
CLOCK_OUT => reset_m
);
end Digitize_Encode_Man;
--
-------------------------------------------------------------------------------
-- Second Order Lowpass filter
--
-- Transfer Function:
--
-- w1*w2
-- H(s) = k * ----------------
-- (s + w1)(s + w2)
--
-- DC Gain = k
-------------------------------------------------------------------------------
-- Use IEEE_proposed instead of disciplines
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
library IEEE;
use ieee.math_real.all;
entity lpf_2_e is
generic (
k: real := 1.0; -- Gain multiplier
f1: real := 10.0; -- First break frequency (pole)
f2: real := 100.0); -- Second break frequency (pole)
port ( terminal input: electrical;
terminal output: electrical);
end entity lpf_2_e;
architecture simple of lpf_2_e is
QUANTITY vin ACROSS input TO ELECTRICAL_REF;
QUANTITY vout ACROSS iout THROUGH output TO ELECTRICAL_REF;
quantity vin_temp : real;
constant w1 : real := f1*math_2_pi;
constant w2 : real := f2*math_2_pi;
-- constant num : real := k;
constant num : real_vector := (0 => w1*w2*k); -- 0=> is needed to give
-- index when only a single
-- element is used.
constant den : real_vector := (w1*w2, w1+w2, 1.0);
begin
vin_temp == vin; -- intermediate variable (vin) req'd for now
vout == vin_temp'ltf(num, den);
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input AND gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY and2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY and2;
ARCHITECTURE ideal OF and2 IS
BEGIN
output <= in1 AND in2 AFTER delay;
END ARCHITECTURE ideal;
--
-- D Flip Flop with reset (negative edge triggered)
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY d_latch_n_edge_rst IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
data, clk : IN std_logic;
q : OUT std_logic := '0';
qn : OUT std_logic := '1';
rst : IN std_logic := '0'); -- reset
END ENTITY d_latch_n_edge_rst ;
ARCHITECTURE behav OF d_latch_n_edge_rst IS
BEGIN
data_in : PROCESS(clk, rst) IS
BEGIN
IF clk = '0' AND clk'event AND rst /= '1' THEN
q <= data AFTER delay;
qn <= NOT data AFTER delay;
ELSIF rst = '1' THEN
q <= '0';
qn <= '1';
END IF;
END PROCESS data_in; -- End of process data_in
END ARCHITECTURE behav;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity counter_12 is
port(
cnt : out std_logic_vector(0 to 11);
reset : in std_logic;
enable : in std_logic;
clk : in std_logic
);
end counter_12;
architecture counter_12 of counter_12 is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic_vector(0 to 11);
signal XSIG010078 : std_logic;
signal XSIG010081 : std_logic;
signal XSIG010083 : std_logic;
signal XSIG010085 : std_logic;
signal XSIG010087 : std_logic;
signal XSIG010101 : std_logic;
signal XSIG010102 : std_logic;
signal XSIG010103 : std_logic;
signal XSIG010104 : std_logic;
signal XSIG010115 : std_logic;
signal XSIG010116 : std_logic;
signal XSIG010117 : std_logic;
signal XSIG010132 : std_logic;
begin
-- Signal assignments
cnt(0) <= cdb2vhdl_tmp_1(0);
cnt(1) <= cdb2vhdl_tmp_1(1);
cnt(2) <= cdb2vhdl_tmp_1(2);
cnt(3) <= cdb2vhdl_tmp_1(3);
cnt(4) <= cdb2vhdl_tmp_1(4);
cnt(5) <= cdb2vhdl_tmp_1(5);
cnt(6) <= cdb2vhdl_tmp_1(6);
cnt(7) <= cdb2vhdl_tmp_1(7);
cnt(8) <= cdb2vhdl_tmp_1(8);
cnt(9) <= cdb2vhdl_tmp_1(9);
cnt(10) <= cdb2vhdl_tmp_1(10);
cnt(11) <= cdb2vhdl_tmp_1(11);
-- Component instances
XCMP92 : entity work.and2(ideal)
port map(
in1 => clk,
in2 => enable,
output => XSIG010132
);
XCMP93 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => XSIG010132,
DATA => XSIG010078,
QN => XSIG010078,
Q => cdb2vhdl_tmp_1(0),
RST => reset
);
XCMP94 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(0),
DATA => XSIG010081,
QN => XSIG010081,
Q => cdb2vhdl_tmp_1(1),
RST => reset
);
XCMP95 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(1),
DATA => XSIG010083,
QN => XSIG010083,
Q => cdb2vhdl_tmp_1(2),
RST => reset
);
XCMP96 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(2),
DATA => XSIG010085,
QN => XSIG010085,
Q => cdb2vhdl_tmp_1(3),
RST => reset
);
XCMP97 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(3),
DATA => XSIG010087,
QN => XSIG010087,
Q => cdb2vhdl_tmp_1(4),
RST => reset
);
XCMP98 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(4),
DATA => XSIG010101,
QN => XSIG010101,
Q => cdb2vhdl_tmp_1(5),
RST => reset
);
XCMP99 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(5),
DATA => XSIG010102,
QN => XSIG010102,
Q => cdb2vhdl_tmp_1(6),
RST => reset
);
XCMP100 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(6),
DATA => XSIG010103,
QN => XSIG010103,
Q => cdb2vhdl_tmp_1(7),
RST => reset
);
XCMP101 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(7),
DATA => XSIG010104,
QN => XSIG010104,
Q => cdb2vhdl_tmp_1(8),
RST => reset
);
XCMP102 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(8),
DATA => XSIG010115,
QN => XSIG010115,
Q => cdb2vhdl_tmp_1(9),
RST => reset
);
XCMP103 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(9),
DATA => XSIG010116,
QN => XSIG010116,
Q => cdb2vhdl_tmp_1(10),
RST => reset
);
XCMP104 : entity work.d_latch_n_edge_rst(behav)
port map(
CLK => cdb2vhdl_tmp_1(10),
DATA => XSIG010117,
QN => XSIG010117,
Q => cdb2vhdl_tmp_1(11),
RST => reset
);
end counter_12;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- ideal one bit A/D converter
LIBRARY IEEE;
USE IEEE.math_real.ALL;
USE IEEE.std_logic_1164.ALL;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.ALL;
ENTITY a2d_bit IS
GENERIC (
thres : real := 2.5); -- Threshold to determine logic output
PORT (
TERMINAL a : electrical; -- analog input
SIGNAL d : OUT std_logic); -- digital (std_logic) output
END ENTITY a2d_bit;
ARCHITECTURE ideal OF a2d_bit IS
QUANTITY vin ACROSS a;
BEGIN -- threshold
-- Process needed to detect threshold crossing and assign output (d)
PROCESS (vin'ABOVE(thres)) IS
BEGIN -- PROCESS
IF vin'ABOVE(thres) THEN
d <= '1';
ELSE
d <= '0';
END IF;
END PROCESS;
END ideal;
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Digital clock with 50% duty cycle and enable pin
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY clock_en IS
GENERIC (
pw : time); -- Clock pulse width
PORT (
enable : IN std_logic ;
clock_out : INOUT std_logic := '0');
END ENTITY clock_en;
ARCHITECTURE ideal OF clock_en IS
BEGIN
-- clock process
process (clock_out, enable) is
begin
if clock_out = '0' AND enable = '1' THEN
clock_out <= '1' after pw, '0' after 2*pw;
end if;
end process;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Inverter
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY inverter IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
input : IN std_logic;
output : OUT std_logic);
END ENTITY inverter;
ARCHITECTURE ideal OF inverter IS
BEGIN
output <= NOT input AFTER delay;
END ARCHITECTURE ideal;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Two input OR gate
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY or2 IS
GENERIC (
delay : time := 0 ns); -- Delay time
PORT (
in1, in2 : IN std_logic;
output : OUT std_logic);
END ENTITY or2;
ARCHITECTURE ideal OF or2 IS
BEGIN
output <= in1 OR in2 AFTER delay;
END ARCHITECTURE ideal;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
ENTITY d2a_nbit IS
GENERIC (
vmax : real := 5.0; -- High output
vmin : real := 0.0; -- Low output
high_bit : integer := 9; -- High end of bit range for D/A
low_bit : integer := 0); -- Low end of bit range for D/A
PORT (
SIGNAL bus_in : IN STD_LOGIC_VECTOR; -- variable width vector input
SIGNAL latch : IN STD_LOGIC;
TERMINAL ana_out : electrical); -- analog output
END ENTITY d2a_nbit ;
ARCHITECTURE behavioral OF d2a_nbit IS
SIGNAL sout : real := 0.0;
QUANTITY vout across iout through ana_out TO electrical_ref;
BEGIN -- ARCHITECTURE behavioral
proc : PROCESS
VARIABLE v_sum : real; -- Sum of voltage contribution from each bit
VARIABLE delt_v : real; -- Represents the voltage value of each bit
BEGIN
WAIT UNTIL (latch'event and latch = '1'); -- Begin when latch goes high
v_sum := vmin;
delt_v := vmax - vmin;
FOR i IN high_bit DOWNTO low_bit LOOP -- Perform the conversions
delt_v := delt_v / 2.0;
IF bus_in(i) = '1' OR bus_in(i) = 'H' THEN
v_sum := v_sum + delt_v;
END IF;
END LOOP;
sout <= v_sum;
END PROCESS;
vout == sout'ramp(100.0E-9); -- Ensure continuous transition between levels
END ARCHITECTURE behavioral;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity pw2ana is
port(
terminal ana_out : electrical;
terminal pw_in : electrical
);
end pw2ana;
architecture pw2ana of pw2ana is
-- Component declarations
-- Signal declarations
signal bus_servo : std_logic_vector(0 to 11);
signal XSIG010008 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010020 : std_logic;
signal XSIG010021 : std_logic;
signal XSIG010022 : std_logic;
begin
-- Signal assignments
-- Component instances
counter_rudder : entity work.counter_12
port map(
enable => XSIG010022,
cnt => bus_servo,
reset => XSIG010021,
clk => XSIG010008
);
XCMP3 : entity work.a2d_bit(ideal)
port map(
D => XSIG010022,
A => pw_in
);
clk_en_rudder : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010008,
enable => XSIG010022
);
XCMP5 : entity work.inverter(ideal)
generic map(
delay => 2 us
)
port map(
input => XSIG010022,
output => XSIG010013
);
XCMP8 : entity work.inverter(ideal)
generic map(
delay => 2 us
)
port map(
input => XSIG010020,
output => XSIG010021
);
XCMP9 : entity work.inverter(ideal)
generic map(
delay => 2 us
)
port map(
input => XSIG010022,
output => XSIG010019
);
or_rudder : entity work.or2(ideal)
port map(
in1 => XSIG010022,
in2 => XSIG010019,
output => XSIG010020
);
XCMP11 : entity work.d2a_nbit(behavioral)
generic map(
vmax => 4.8,
high_bit => 9,
low_bit => 0
)
port map(
bus_in => bus_servo,
ana_out => ana_out,
latch => XSIG010013
);
end pw2ana;
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : DC_Motor.vhd
-- Author : Mentor Graphics
-- Created : 2001/06/16
-- Last update: 2001/06/16
-------------------------------------------------------------------------------
-- Description: Basic DC Motor
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.mechanical_systems.all;
use IEEE_proposed.electrical_systems.all;
entity DC_Motor is
generic (
r_wind : resistance; -- Motor winding resistance [Ohm]
kt : real; -- Torque coefficient [N*m/Amp]
l : inductance; -- Winding inductance [Henrys]
d : real; -- Damping coefficient [N*m/(rad/sec)]
j : mmoment_i); -- Moment of inertia [kg*meter**2]
port (terminal p1, p2 : electrical;
terminal shaft_rotv : rotational_v);
end entity DC_Motor;
-------------------------------------------------------------------------------
-- Basic Architecture
-- Motor equations: V = Kt*W + I*Rwind + L*dI/dt
-- T = -Kt*I + D*W + J*dW/dt
-------------------------------------------------------------------------------
architecture basic of DC_Motor is
quantity v across i through p1 to p2;
quantity w across torq through shaft_rotv to rotational_v_ref;
begin
torq == -1.0*kt*i + d*w + j*w'dot;
v == kt*w + i*r_wind + l*i'dot;
end architecture basic;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
--
-- This model is a component of the Mentor Graphics VHDL-AMS educational open
-- source model library, and is covered by this license agreement. This model,
-- including any updates, modifications, revisions, copies, and documentation
-- are copyrighted works of Mentor Graphics. USE OF THIS MODEL INDICATES YOUR
-- COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH
-- IN THIS LICENSE AGREEMENT. Mentor Graphics grants you a non-exclusive
-- license to use, reproduce, modify and distribute this model, provided that:
-- (a) no fee or other consideration is charged for any distribution except
-- compilations distributed in accordance with Section (d) of this license
-- agreement; (b) the comment text embedded in this model is included verbatim
-- in each copy of this model made or distributed by you, whether or not such
-- version is modified; (c) any modified version must include a conspicuous
-- notice that this model has been modified and the date of modification; and
-- (d) any compilations sold by you that include this model must include a
-- conspicuous notice that this model is available from Mentor Graphics in its
-- original form at no charge.
--
-- THIS MODEL IS LICENSED TO YOU "AS IS" AND WITH NO WARRANTIES, EXPRESS OR
-- IMPLIED. MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL
-- HAVE NO RESPONSIBILITY FOR ANY DAMAGES WHATSOEVER.
-------------------------------------------------------------------------------
-- File : stop_r.vhd
-- Author : Mentor Graphics
-- Created : 2001/10/10
-- Last update: 2001/10/10
-------------------------------------------------------------------------------
-- Description: Mechanical Hard Stop (ROTATIONAL domain)
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2001/06/16 1.0 Mentor Graphics Created
-------------------------------------------------------------------------------
library IEEE;
use IEEE.MATH_REAL.all;
-- Use proposed IEEE natures and packages
library IEEE_proposed;
use IEEE_proposed.MECHANICAL_SYSTEMS.all;
entity stop_r is
generic (
k_stop : real;
-- ang_max : angle;
-- ang_min : angle := 0.0;
ang_max : real;
ang_min : real := 0.0;
damp_stop : real := 0.000000001
);
port ( terminal ang1, ang2 : rotational);
end entity stop_r;
architecture ideal of stop_r is
quantity velocity : velocity;
quantity ang across trq through ang1 to ang2;
begin
velocity == ang'dot;
if ang'above(ang_max) use
trq == k_stop * (ang - ang_max) + (damp_stop * velocity);
elsif ang'above(ang_min) use
trq == 0.0;
else
trq == k_stop * (ang - ang_min) + (damp_stop * velocity);
end use;
break on ang'above(ang_min), ang'above(ang_max);
end architecture ideal;
-------------------------------------------------------------------------------
-- Copyright (c) 2001 Mentor Graphics Corporation
-------------------------------------------------------------------------------
--
-- 12-bit digital comparator model
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity dig_cmp is
port
(
eq : out std_logic := '0';
in1 : in std_logic_vector (0 to 11);
in2 : in std_logic_vector (0 to 11);
latch_in1 : in std_logic := '0'; -- Currently unused
latch_in2 : in std_logic := '0';
cmp : in std_logic := '0';
clk : in std_logic
);
end entity dig_cmp ;
architecture simple of dig_cmp is
begin
compare: PROCESS (latch_in2, cmp, clk) -- Sensitivity list
variable in2_hold : std_logic_vector (0 to 11) := "000000000000";
BEGIN
if latch_in2 = '1' then -- in2 data is latched and stored
in2_hold := in2;
end if;
if cmp = '1' then
if in1 = in2_hold then -- latched in2 checked against current in1
eq <= '0';
else eq <= '1';
end if;
end if;
END PROCESS;
end architecture simple;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- Electrical Resistor Model
-- Use proposed IEEE natures and packages
LIBRARY IEEE_proposed;
USE IEEE_proposed.ELECTRICAL_SYSTEMS.ALL;
ENTITY resistor IS
-- Initialize parameters
GENERIC (
res : RESISTANCE); -- resistance (no initial value)
-- Define ports as electrical terminals
PORT (
TERMINAL p1, p2 : ELECTRICAL);
END ENTITY resistor;
-- Ideal Architecture (V = I*R)
ARCHITECTURE ideal OF resistor IS
-- Declare Branch Quantities
QUANTITY v ACROSS i THROUGH p1 TO p2;
BEGIN
-- Characteristic equations
v == i*res;
END ARCHITECTURE ideal;
--
-- Set/reset flip flop
-- When S goes high, Q is set high until reset
-- When R goes high, Q is set low until set
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sr_ff is
port
(
S : in std_logic ;
R : in std_logic ;
Q : out std_logic
);
end sr_ff ;
architecture simple of sr_ff is
begin
set_reset: PROCESS(S, R) IS
BEGIN
-- assert S='1' nand R='1' -- Warning if both inputs are high
-- report "S and R are both active. Use with caution"
-- severity warning;
if S'event AND S = '1' then
Q <= '1';
end if;
if R'event AND R = '1' then
Q <= '0';
end if;
END PROCESS set_reset;
end;
--
--//////////////////////////////////////////////////////////////////
-- NOTE: This is an intermediate file for HDL inspection only.
-- Please make all changes to C:\Scott\examples\ex_CS5\design_definition\graphics\state_mach_rcvr.sdg.
-- Generated by sde2hdl version 16.1.0.2
--//////////////////////////////////////////////////////////////////
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
LIBRARY IEEE_proposed;
USE IEEE_proposed.electrical_systems.all;
USE IEEE_proposed.mechanical_systems.all;
USE IEEE_proposed.fluidic_systems.all;
USE IEEE_proposed.thermal_systems.all;
USE IEEE_proposed.radiant_systems.all;
ENTITY state_mach_rcvr IS
PORT (
clk_50 : IN std_logic;
clk_100k : IN std_logic;
ser_done : IN std_logic;
par_det : IN std_logic;
frm_det : IN std_logic;
clk_6k : IN std_logic;
start_pulse : IN std_logic;
dly_done : IN std_logic;
s2p_rst : OUT std_logic;
s2p_en : OUT std_logic;
cnt1_en : OUT std_logic;
cnt1_rst : OUT std_logic;
cmp1_ltch1 : OUT std_logic;
cmp1_ltch2 : OUT std_logic;
cnt2_en : OUT std_logic;
cnt2_rst : OUT std_logic;
cmp2_ltch1 : OUT std_logic;
cmp2_ltch2 : OUT std_logic;
da_latch : OUT std_logic;
ser_cnt : OUT std_logic;
dly_cnt : OUT std_logic;
par_oe : OUT std_logic);
END state_mach_rcvr;
ARCHITECTURE state_diagram OF state_mach_rcvr IS
ATTRIBUTE ENUM_TYPE_ENCODING: STRING;
TYPE TYP_state_mach_rcvr_sm1 IS (V_begin, cnt, ch1, rst1, ch2, rst2, cnt_cmp, rst_cnt
, s_bit, par1, par2);
SIGNAL CS_state_mach_rcvr_sm1, NS_state_mach_rcvr_sm1 : TYP_state_mach_rcvr_sm1;
BEGIN
sm1:
PROCESS (CS_state_mach_rcvr_sm1, clk_50, frm_det, ser_done, start_pulse, dly_done, par_det)
BEGIN
CASE CS_state_mach_rcvr_sm1 IS
WHEN V_begin =>
cnt1_en <= ('0');
cnt1_rst <= ('1');
cmp1_ltch1 <= ('0');
cmp1_ltch2 <= ('0');
cnt2_en <= ('0');
cnt2_rst <= ('1');
cmp2_ltch1 <= ('0');
cmp2_ltch2 <= ('0');
s2p_en <= ('1');
s2p_rst <= ('0');
da_latch <= ('0');
ser_cnt <= ('0');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((frm_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= s_bit;
ELSE
NS_state_mach_rcvr_sm1 <= V_begin;
END IF;
WHEN cnt =>
ser_cnt <= ('1');
cnt1_rst <= ('0');
cnt2_rst <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par1;
ELSE
NS_state_mach_rcvr_sm1 <= cnt;
END IF;
WHEN ch1 =>
cmp1_ltch2 <= ('1');
ser_cnt <= ('0');
dly_cnt <= ('1');
IF (((start_pulse = '1') AND (dly_done = '1'))) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= ch1;
END IF;
WHEN rst1 =>
cmp1_ltch2 <= ('0');
ser_cnt <= ('1');
dly_cnt <= ('0');
par_oe <= ('0');
IF ((ser_done = '1')) THEN
NS_state_mach_rcvr_sm1 <= par2;
ELSE
NS_state_mach_rcvr_sm1 <= rst1;
END IF;
WHEN ch2 =>
cmp2_ltch2 <= ('1');
ser_cnt <= ('0');
da_latch <= ('1');
NS_state_mach_rcvr_sm1 <= rst2;
WHEN rst2 =>
cmp2_ltch2 <= ('0');
s2p_en <= ('0');
par_oe <= ('0');
da_latch <= ('0');
NS_state_mach_rcvr_sm1 <= cnt_cmp;
WHEN cnt_cmp =>
cnt1_en <= ('1');
cmp1_ltch1 <= ('1');
cnt2_en <= ('1');
cmp2_ltch1 <= ('1');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN rst_cnt =>
cnt1_en <= ('0');
cmp1_ltch1 <= ('0');
cnt2_en <= ('0');
cmp2_ltch1 <= ('0');
NS_state_mach_rcvr_sm1 <= rst_cnt;
WHEN s_bit =>
IF ((start_pulse = '1')) THEN
NS_state_mach_rcvr_sm1 <= cnt;
ELSE
NS_state_mach_rcvr_sm1 <= s_bit;
END IF;
WHEN par1 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch1;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst1;
ELSE
NS_state_mach_rcvr_sm1 <= par1;
END IF;
WHEN par2 =>
par_oe <= ('1');
IF ((par_det = '0')) THEN
NS_state_mach_rcvr_sm1 <= ch2;
ELSIF ((par_det = '1')) THEN
NS_state_mach_rcvr_sm1 <= rst2;
ELSE
NS_state_mach_rcvr_sm1 <= par2;
END IF;
END CASE;
END PROCESS;
sm1_CTL:
PROCESS (clk_100k, clk_50)
BEGIN
IF (clk_100k'event AND clk_100k='1') THEN
IF (clk_50= '1' ) THEN
CS_state_mach_rcvr_sm1 <= V_begin;
ELSE
CS_state_mach_rcvr_sm1 <= NS_state_mach_rcvr_sm1;
END IF;
END IF;
END PROCESS;
END state_diagram;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity sm_cnt_rcvr is
port(
cmp1_ltch1 : out std_logic;
cmp2_ltch1 : out std_logic;
s2p_en : out std_logic;
s2p_rst : out std_logic;
frm_det : in std_logic;
par_det : in std_logic;
clk_100k : in std_logic;
clk_6k : in std_logic;
clk_50 : in std_logic;
start_pulse : in std_logic;
cnt1_en : out std_logic;
cnt1_rst : out std_logic;
cmp1_ltch2 : out std_logic;
cnt2_en : out std_logic;
cnt2_rst : out std_logic;
cmp2_ltch2 : out std_logic;
da_latch : out std_logic;
par_oe : out std_logic
);
end sm_cnt_rcvr;
architecture sm_cnt_rcvr of sm_cnt_rcvr is
-- Component declarations
-- Signal declarations
terminal dly_cnt_a : electrical;
terminal dly_done_a : electrical;
terminal ser_cnt_a : electrical;
terminal ser_done_a : electrical;
signal XSIG010001 : std_logic;
signal XSIG010002 : std_logic;
signal XSIG010145 : std_logic;
signal XSIG010146 : std_logic;
begin
-- Signal assignments
-- Component instances
XCMP1 : entity work.d2a_bit(ideal)
port map(
D => XSIG010001,
A => ser_cnt_a
);
XCMP2 : entity work.d2a_bit(ideal)
port map(
D => XSIG010002,
A => ser_done_a
);
bit_cnt3 : entity work.bit_cnt(behavioral)
generic map(
count => 2
)
port map(
bit_in => XSIG010145,
clk => clk_6k,
dly_out => XSIG010146
);
bit_cnt4 : entity work.bit_cnt(behavioral)
generic map(
count => 10
)
port map(
bit_in => XSIG010001,
clk => clk_6k,
dly_out => XSIG010002
);
XCMP8 : entity work.d2a_bit(ideal)
port map(
D => XSIG010145,
A => dly_cnt_a
);
XCMP9 : entity work.d2a_bit(ideal)
port map(
D => XSIG010146,
A => dly_done_a
);
state_mach_rcvr8 : entity work.state_mach_rcvr
port map(
clk_100k => clk_100k,
clk_50 => clk_50,
s2p_rst => s2p_rst,
s2p_en => s2p_en,
cnt1_en => cnt1_en,
cnt1_rst => cnt1_rst,
cmp1_ltch1 => cmp1_ltch1,
cmp1_ltch2 => cmp1_ltch2,
cnt2_en => cnt2_en,
cnt2_rst => cnt2_rst,
cmp2_ltch1 => cmp2_ltch1,
cmp2_ltch2 => cmp2_ltch2,
da_latch => da_latch,
ser_cnt => XSIG010001,
ser_done => XSIG010002,
par_det => par_det,
frm_det => frm_det,
clk_6k => clk_6k,
start_pulse => start_pulse,
dly_done => XSIG010146,
dly_cnt => XSIG010145,
par_oe => par_oe
);
end sm_cnt_rcvr;
--
-- Copyright Mentor Graphics Corporation 2001
-- Confidential Information Provided Under License Agreement for Internal Use Only
-- level_set.vhd
-- Set digital output "level" with parameter "logic_val" (default is '1')
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY level_set IS
GENERIC (
logic_val : std_logic := '1');
PORT (
level : OUT std_logic);
END ENTITY level_set;
-- Simple architecture
ARCHITECTURE ideal OF level_set IS
BEGIN
level <= logic_val;
END ARCHITECTURE ideal;
--
-- Serial to parallel data converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity ser2par is
port
(
par_out : inout std_logic_vector(0 to 11) := "ZZZZZZZZZZZZ";
clk : in std_logic ;
load_en : in std_logic ;
ser_in : in std_logic ;
reset : in std_logic
);
begin
end ser2par;
architecture a1 of ser2par is
BEGIN
sr_sm: PROCESS (load_en, clk, reset, ser_in)
BEGIN
if (reset = '1' and load_en = '1') then
par_out <= "000000000000"; -- Reset the parallel data out
elsif (clk'event and clk = '1') then
if (load_en ='1') then
-- The register will shift when load is enabled
-- and will shift at rising edge of clock
par_out(0) <= ser_in; -- Input data shifts into bit 0
par_out(1) <= par_out(0);
par_out(2) <= par_out(1);
par_out(3) <= par_out(2);
par_out(4) <= par_out(3);
par_out(5) <= par_out(4);
par_out(6) <= par_out(5);
par_out(7) <= par_out(6);
par_out(8) <= par_out(7);
par_out(9) <= par_out(8);
par_out(10) <= par_out(9);
par_out(11) <= par_out(10);
else
-- The otput data will not change
-- if load_en is not enabled
par_out <= "ZZZZZZZZZZZZ";
end if;
end if;
END PROCESS;
end;
--
-- This model ouputs a '1' when a specific bit pattern is encountered
-- Otherwise, it outputs a zero
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity frame_det is
port
(
bus_in : in std_logic_vector (0 to 11);
clk : in std_logic;
frm_bit : out std_logic := '0' -- Initialize output to zero
);
end entity frame_det;
architecture simple of frame_det is
begin
enbl: PROCESS (bus_in, clk) -- Sensitivity list
BEGIN
if bus_in = "010101010101" then -- This is the pre-defined bit pattern
if clk'event AND clk = '0' then -- Output updated synchronously
frm_bit <= '1';
end if;
else frm_bit <= '0';
end if;
END PROCESS;
end architecture simple;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity parity_det is
port(
bus_in : in std_logic_vector(0 to 11);
par_bit : out std_logic;
oe : in std_logic
);
end parity_det;
architecture parity_det of parity_det is
-- Component declarations
-- Signal declarations
signal cdb2vhdl_tmp_1 : std_logic;
terminal par_bit_a : electrical;
signal XSIG010010 : std_logic;
signal XSIG010011 : std_logic;
signal XSIG010012 : std_logic;
signal XSIG010013 : std_logic;
signal XSIG010014 : std_logic;
signal XSIG010015 : std_logic;
signal XSIG010016 : std_logic;
signal XSIG010017 : std_logic;
signal XSIG010019 : std_logic;
signal XSIG010057 : std_logic;
begin
-- Signal assignments
par_bit <= cdb2vhdl_tmp_1;
-- Component instances
XCMP1 : entity work.xor2(ideal)
port map(
in1 => bus_in(1),
in2 => bus_in(2),
output => XSIG010010
);
XCMP2 : entity work.xor2(ideal)
port map(
in1 => bus_in(3),
in2 => bus_in(4),
output => XSIG010011
);
XCMP3 : entity work.xor2(ideal)
port map(
in1 => bus_in(5),
in2 => bus_in(6),
output => XSIG010012
);
XCMP4 : entity work.xor2(ideal)
port map(
in1 => bus_in(7),
in2 => bus_in(8),
output => XSIG010013
);
XCMP5 : entity work.xor2(ideal)
port map(
in1 => bus_in(9),
in2 => bus_in(10),
output => XSIG010016
);
XCMP6 : entity work.xor2(ideal)
port map(
in1 => XSIG010010,
in2 => XSIG010011,
output => XSIG010014
);
XCMP7 : entity work.xor2(ideal)
port map(
in1 => XSIG010012,
in2 => XSIG010013,
output => XSIG010015
);
XCMP8 : entity work.xor2(ideal)
port map(
in1 => XSIG010014,
in2 => XSIG010015,
output => XSIG010017
);
XCMP9 : entity work.xor2(ideal)
port map(
in1 => XSIG010017,
in2 => XSIG010016,
output => XSIG010019
);
XCMP10 : entity work.xor2(ideal)
port map(
in1 => XSIG010019,
in2 => bus_in(0),
output => XSIG010057
);
XCMP11 : entity work.d2a_bit(ideal)
port map(
D => cdb2vhdl_tmp_1,
A => par_bit_a
);
XCMP12 : entity work.and2(ideal)
port map(
in1 => oe,
in2 => XSIG010057,
output => cdb2vhdl_tmp_1
);
end parity_det;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity TDM_Demux_dbg is
port(
s2p_en : in std_logic;
tdm_in : in std_logic;
clk_6k : in std_logic;
s2p_rst : in std_logic;
par_det : out std_logic;
frm_det : out std_logic;
da_latch : in std_logic;
par_oe : in std_logic;
data_bus : out std_logic_vector(1 to 10);
start_bit : out std_logic
);
end TDM_Demux_dbg;
architecture TDM_Demux_dbg of TDM_Demux_dbg is
-- Component declarations
-- Signal declarations
terminal d2a_out : electrical;
signal rcvr_bus : std_logic_vector(0 to 11);
begin
-- Signal assignments
data_bus(1) <= rcvr_bus(1);
data_bus(2) <= rcvr_bus(2);
data_bus(3) <= rcvr_bus(3);
data_bus(4) <= rcvr_bus(4);
data_bus(5) <= rcvr_bus(5);
data_bus(6) <= rcvr_bus(6);
data_bus(7) <= rcvr_bus(7);
data_bus(8) <= rcvr_bus(8);
data_bus(9) <= rcvr_bus(9);
data_bus(10) <= rcvr_bus(10);
start_bit <= rcvr_bus(0);
-- Component instances
s2p1 : entity work.ser2par(a1)
port map(
par_out => rcvr_bus,
clk => clk_6k,
load_en => s2p_en,
ser_in => tdm_in,
reset => s2p_rst
);
frm_det1 : entity work.frame_det(simple)
port map(
bus_in => rcvr_bus,
frm_bit => frm_det,
clk => clk_6k
);
par_det1 : entity work.parity_det
port map(
bus_in => rcvr_bus,
par_bit => par_det,
oe => par_oe
);
XCMP113 : entity work.d2a_nbit(behavioral)
generic map(
low_bit => 1,
high_bit => 10,
vmax => 4.8
)
port map(
bus_in => rcvr_bus(1 to 10),
ana_out => d2a_out,
latch => da_latch
);
end TDM_Demux_dbg;
--
-- Manchester Decoder with clock recovery using 8x referenced clock
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mdec_rsc is
-- port ( din: in real; -- real input
port ( din: in std_logic; -- real input
clk16x: in std_logic; -- 16x referenced clock
reset: in std_logic; -- not reset
bout: out std_logic := '0'; -- digital output
clk_out: inout std_logic := '0'); -- recovered clock
end entity mdec_rsc;
architecture bhv of mdec_rsc is
-- signal bhigh:real:= 1.0; -- bit decoding
-- signal blow:real:= -1.0; -- bit decoding
-- signal bnormal:real:=0.0; -- bit decoding
signal bhigh:std_logic:= '1'; -- bit decoding
signal blow:std_logic:= '0'; -- bit decoding
signal bout1:std_logic;
signal clk_div:std_logic_vector(3 downto 0):="0000"; -- clock counter
signal trans:std_logic; -- transisition trigger
begin
-- bit decoding
proc1: process (reset,din,clk16x)
begin
if (reset = '1') then
bout1 <= 'X';
elsif (clk16x'event and clk16x = '1') then
if (din = bhigh) then
bout1 <= '1';
elsif (din = blow) then
bout1 <= '0';
else
bout1 <= 'X';
end if;
end if;
end process;
-- clock counter
proc2: process (reset, clk16x, clk_div)
begin
if (reset = '1') then
clk_div <= "0000";
elsif (clk16x'event and clk16x = '1') then
clk_div <= clk_div + "0001";
end if;
end process;
-- recovered clock
-- clk_out <= not clk_div(3);
clk_out <= clk_div(3);
-- transition trigger
trans <= ((not clk_div(3)) and (not clk_div(2)) and clk_div(1) and clk_div(0)) or
(clk_div(3) and clk_div(2) and (not clk_div(1)) and (not clk_div(0)));
-- Manchester decoder
proc3: process (reset, trans, bout1, clk_out, clk16x)
begin
if (reset = '1') then
bout <= '0';
elsif (clk16x'event and clk16x = '1') then
if (trans = '1') then
bout <= bout1 XOR clk_out;
end if;
end if;
end process;
end architecture bhv;
architecture bhv_8 of mdec_rsc is
-- signal bhigh:real:= 1.0; -- bit decoding
-- signal blow:real:= -1.0; -- bit decoding
-- signal bnormal:real:=0.0; -- bit decoding
signal bhigh:std_logic:= '1'; -- bit decoding
signal blow:std_logic:= '0'; -- bit decoding
signal bout1:std_logic;
signal clk_div:std_logic_vector(2 downto 0):="000"; -- clock counter
signal trans:std_logic; -- transisition trigger
begin
-- bit decoding
proc1: process (reset,din,clk16x)
begin
if (reset = '1') then
bout1 <= 'X';
elsif (clk16x'event and clk16x = '1') then
if (din = bhigh) then
bout1 <= '1';
elsif (din = blow) then
bout1 <= '0';
else
bout1 <= 'X';
end if;
end if;
end process;
-- clock counter
proc2: process (reset, clk16x, clk_div)
begin
if (reset = '1') then
clk_div <= "000";
elsif (clk16x'event and clk16x = '1') then
clk_div <= clk_div + "001";
end if;
end process;
-- recovered clock
clk_out <= not clk_div(2);
-- transition trigger
trans <= ((not clk_div(1)) and clk_div(0)) or (clk_div(1) and (not clk_div(0)));
-- Manchester decoder
proc3: process (reset, trans, bout1, clk_out, clk16x)
begin
if (reset = '1') then
bout <= '0';
elsif (clk16x'event and clk16x = '1') then
if (trans = '1') then
bout <= bout1 XOR clk_out;
end if;
end if;
end process;
end architecture bhv_8;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity Decode_PW_Man is
port(
terminal power : electrical;
terminal ch1_pw : electrical;
terminal ch2_pw : electrical;
bit_stream_in : in std_logic
);
end Decode_PW_Man;
architecture Decode_PW_Man of Decode_PW_Man is
-- Component declarations
-- Signal declarations
signal bit_stream_in_mdec : std_logic;
signal clk16x : std_logic;
signal clk6k : std_logic;
signal clk_100k : std_logic;
signal cmp_bus : std_logic_vector(0 to 11);
signal cnt1 : std_logic_vector(0 to 11);
signal cnt2 : std_logic_vector(0 to 11);
signal mdec_clk : std_logic;
signal mdec_out : std_logic;
signal reset : std_logic;
signal reset_m : std_logic;
signal XSIG010228 : std_logic;
signal XSIG010229 : std_logic;
signal XSIG010256 : std_logic;
signal XSIG010263 : std_logic;
signal XSIG010264 : std_logic;
signal XSIG010266 : std_logic;
signal XSIG010267 : std_logic;
signal XSIG010268 : std_logic;
signal XSIG010320 : std_logic;
signal XSIG010330 : std_logic;
signal XSIG010334 : std_logic;
signal XSIG010339 : std_logic;
signal XSIG010349 : std_logic;
signal XSIG010357 : std_logic;
signal XSIG010371 : std_logic;
signal XSIG010372 : std_logic;
signal XSIG010373 : std_logic;
signal XSIG010383 : std_logic;
signal XSIG010384 : std_logic;
signal XSIG010385 : std_logic;
signal XSIG010386 : std_logic;
signal XSIG010390 : std_logic;
signal XSIG010433 : std_logic;
begin
-- Signal assignments
bit_stream_in_mdec <= bit_stream_in;
-- Component instances
cntr1 : entity work.counter_12
port map(
enable => XSIG010384,
cnt => cnt1,
reset => XSIG010357,
clk => XSIG010433
);
cntr2 : entity work.counter_12
port map(
enable => XSIG010349,
cnt => cnt2,
reset => XSIG010385,
clk => XSIG010320
);
cmp1 : entity work.dig_cmp(simple)
port map(
in1 => cnt1,
eq => XSIG010371,
clk => XSIG010433,
in2 => cmp_bus,
cmp => XSIG010384,
latch_in1 => XSIG010256,
latch_in2 => XSIG010383
);
cmp2 : entity work.dig_cmp(simple)
port map(
in1 => cnt2,
eq => XSIG010372,
clk => XSIG010320,
in2 => cmp_bus,
cmp => XSIG010349,
latch_in1 => XSIG010263,
latch_in2 => XSIG010264
);
XCMP109 : entity work.resistor(ideal)
generic map(
res => 1000000.0
)
port map(
p1 => power,
p2 => ELECTRICAL_REF
);
clk_1M2 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010320,
enable => XSIG010349
);
clk_1M1 : entity work.clock_en(ideal)
generic map(
pw => 500 ns
)
port map(
CLOCK_OUT => XSIG010433,
enable => XSIG010384
);
XCMP134 : entity work.d2a_bit(ideal)
port map(
D => XSIG010371,
A => ch1_pw
);
XCMP135 : entity work.d2a_bit(ideal)
port map(
D => XSIG010372,
A => ch2_pw
);
XCMP137 : entity work.SR_FF(simple)
port map(
S => XSIG010330,
R => XSIG010334,
Q => XSIG010349
);
XCMP138 : entity work.inverter(ideal)
port map(
input => XSIG010372,
output => XSIG010334
);
XCMP139 : entity work.SR_FF(simple)
port map(
S => XSIG010373,
R => XSIG010339,
Q => XSIG010384
);
XCMP140 : entity work.inverter(ideal)
port map(
input => XSIG010371,
output => XSIG010339
);
rc_clk2 : entity work.rc_clk
port map(
clk_50 => reset,
clk_6K => clk6k,
clk_100k => clk_100k
);
sm_rcvr1 : entity work.sm_cnt_rcvr
port map(
cnt1_en => XSIG010373,
cmp1_ltch1 => XSIG010256,
cnt2_rst => XSIG010385,
clk_100k => clk_100k,
cnt1_rst => XSIG010357,
cnt2_en => XSIG010330,
cmp2_ltch1 => XSIG010263,
frm_det => XSIG010229,
par_det => XSIG010228,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
clk_6k => mdec_clk,
clk_50 => reset,
da_latch => XSIG010268,
cmp1_ltch2 => XSIG010383,
cmp2_ltch2 => XSIG010264,
start_pulse => XSIG010390,
par_oe => XSIG010386
);
XCMP155 : entity work.level_set(ideal)
generic map(
logic_val => '0'
)
port map(
level => cmp_bus(11)
);
XCMP157 : entity work.TDM_Demux_dbg
port map(
data_bus => cmp_bus(0 to 9),
tdm_in => mdec_out,
clk_6k => mdec_clk,
s2p_en => XSIG010266,
s2p_rst => XSIG010267,
da_latch => XSIG010268,
frm_det => XSIG010229,
par_det => XSIG010228,
par_oe => XSIG010386,
start_bit => XSIG010390
);
XCMP172 : entity work.level_set(ideal)
generic map(
logic_val => '1'
)
port map(
level => cmp_bus(10)
);
clock1 : entity work.clock(ideal)
generic map(
period => 9.375 us
)
port map(
CLK_OUT => clk16x
);
mdec_rsc7 : entity work.mdec_rsc(bhv)
port map(
din => bit_stream_in_mdec,
clk16x => clk16x,
reset => reset_m,
bout => mdec_out,
clk_out => mdec_clk
);
XCMP181 : entity work.clock_duty(ideal)
generic map(
off_time => 19.98 sec
)
port map(
CLOCK_OUT => reset_m
);
end Decode_PW_Man;
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library IEEE_proposed;
use IEEE_proposed.electrical_systems.all;
use IEEE_proposed.mechanical_systems.all;
entity tb_CS5_CC_Rudder is
end tb_CS5_CC_Rudder;
architecture TB_CS5_CC_Rudder of tb_CS5_CC_Rudder is
-- Component declarations
-- Signal declarations
terminal gear_out : rotational;
terminal link_in : translational;
terminal link_out : translational;
terminal pot_fb : electrical;
signal rf_in : std_logic;
signal rf_out : std_logic;
terminal rudder : rotational;
terminal rudder_ana : electrical;
terminal rudder_cmd : electrical;
terminal rudder_mtr_in : electrical;
terminal rudder_mtr_out : rotational_v;
terminal rudder_pw : electrical;
terminal rudder_servo_in : electrical;
terminal throttle_ana : electrical;
terminal throttle_cmd : electrical;
terminal throttle_pw : electrical;
terminal XSIG010013 : electrical;
begin
-- Signal assignments
-- Component instances
rudder_servo1 : entity work.rudder_servo
port map(
servo_out => rudder_mtr_in,
servo_in => rudder_servo_in,
pos_fb => pot_fb
);
gear1 : entity work.gear_rv_r(ideal)
generic map(
ratio => 0.01
)
port map(
rotv1 => rudder_mtr_out,
rot2 => gear_out
);
potentiometer : entity work.rot2v(bhv)
generic map(
k => 1.0
)
port map(
output => pot_fb,
input => gear_out
);
g_horn : entity work.horn_r2t(bhv)
port map(
theta => gear_out,
pos => link_in
);
r_horn : entity work.horn_t2r(bhv)
port map(
theta => rudder,
pos => link_out
);
\linkage\ : entity work.tran_linkage(a1)
port map(
p2 => link_out,
p1 => link_in
);
rudder_1 : entity work.rudder(bhv)
generic map(
k => 0.2
)
port map(
rot => rudder
);
XCMP6 : entity work.v_constant(ideal)
generic map(
level => 5.0
)
port map(
pos => XSIG010013,
neg => ELECTRICAL_REF
);
t_stick : entity work.stick(ideal)
generic map(
offset => 2.397,
phase => 0.0,
amplitude => 2.397,
freq => 1.0
)
port map(
v_out => throttle_cmd
);
r_stick : entity work.stick(ideal)
generic map(
freq => 1.0,
amplitude => 2.397,
phase => 270.0,
offset => 2.397
)
port map(
v_out => rudder_cmd
);
RF : entity work.rf_xmtr_rcvr(behavioral)
port map(
tdm_in => rf_in,
tdm_out => rf_out
);
Digitize_Encode1 : entity work.Digitize_Encode_Man
port map(
ch2_in => rudder_cmd,
ch1_in => throttle_cmd,
tdm_out => rf_in
);
filter : entity work.lpf_2_e(simple)
generic map(
f2 => 10.0,
f1 => 10.0
)
port map(
input => rudder_ana,
output => rudder_servo_in
);
t_pw2ana : entity work.pw2ana
port map(
ana_out => throttle_ana,
pw_in => throttle_pw
);
r_pw2ana : entity work.pw2ana
port map(
ana_out => rudder_ana,
pw_in => rudder_pw
);
motor2 : entity work.DC_Motor(basic)
generic map(
r_wind => 2.2,
kt => 3.43e-3,
l => 2.03e-3,
d => 5.63e-6,
j => 168.0e-9
)
port map(
p1 => rudder_mtr_in,
p2 => ELECTRICAL_REF,
shaft_rotv => rudder_mtr_out
);
stop3 : entity work.stop_r(ideal)
generic map(
k_stop => 1.0e6,
ang_max => 1.05,
ang_min => -1.05,
damp_stop => 1.0e2
)
port map(
ang1 => gear_out,
ang2 => ROTATIONAL_REF
);
Decode_PW_Man2 : entity work.Decode_PW_Man
port map(
bit_stream_in => rf_out,
ch2_pw => rudder_pw,
ch1_pw => throttle_pw,
power => XSIG010013
);
end TB_CS5_CC_Rudder;
--
|
library verilog;
use verilog.vl_types.all;
entity Vending_Machine_vlg_vec_tst is
end Vending_Machine_vlg_vec_tst;
|
-------------------------------------------------------------------------------
-- Title : MC613
-- Project : PS2 Basic Protocol
-- Details : www.ic.unicamp.br/~corte/mc613/
-- www.computer-engineering.org/ps2protocol/
-------------------------------------------------------------------------------
-- File : ps2_base.vhd
-- Author : Thiago Borges Abdnur
-- Company : IC - UNICAMP
-- Last update: 2010/04/12
-------------------------------------------------------------------------------
-- Description:
-- PS2 basic control
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
entity ps2_iobase is
generic(
clkfreq : integer -- This is the system clock value in kHz
);
port(
ps2_data : inout std_logic; -- PS2 data pin
ps2_clk : inout std_logic; -- PS2 clock pin
clk : in std_logic; -- system clock (same frequency as defined in
-- 'clkfreq' generic)
en : in std_logic; -- Enable
resetn : in std_logic; -- Reset when '0'
idata_rdy : in std_logic; -- Rise this to signal data is ready to be sent
-- to device
idata : in std_logic_vector(7 downto 0); -- Data to be sent to device
send_rdy : out std_logic; -- '1' if data can be sent to device (wait for
-- this before rising 'idata_rdy'
odata_rdy : out std_logic; -- '1' when data from device has arrived
odata : out std_logic_vector(7 downto 0) -- Data from device
);
end;
architecture rtl of ps2_iobase is
constant CLKSSTABLE : integer := clkfreq / 150;
signal sdata, hdata : std_logic_vector(7 downto 0);
signal sigtrigger, parchecked, sigsending,
sigsendend, sigclkreleased, sigclkheld : std_logic;
begin
-- Trigger for state change to eliminate noise
process(clk, ps2_clk, en, resetn)
variable fcount, rcount : integer range CLKSSTABLE downto 0;
begin
if(rising_edge(clk) and en = '1') then
-- Falling edge noise
if ps2_clk = '0' then
rcount := 0;
if fcount >= CLKSSTABLE then
sigtrigger <= '1';
else
fcount := fcount + 1;
end if;
-- Rising edge noise
elsif ps2_clk = '1' then
fcount := 0;
if rcount >= CLKSSTABLE then
sigtrigger <= '0';
else
rcount := rcount + 1;
end if;
end if;
end if;
if resetn = '0' then
fcount := 0;
rcount := 0;
sigtrigger <= '0';
end if;
end process;
FROMPS2:
process(sigtrigger, sigsending, resetn)
variable count : integer range 0 to 11;
begin
if(rising_edge(sigtrigger) and sigsending = '0') then
if count > 0 and count < 9 then
sdata(count - 1) <= ps2_data;
end if;
if count = 9 then
if (not (sdata(0) xor sdata(1) xor sdata(2) xor sdata(3)
xor sdata(4) xor sdata(5) xor sdata(6) xor sdata(7))) = ps2_data then
parchecked <= '1';
else
parchecked <= '0';
end if;
end if;
count := count + 1;
if count = 11 then
count := 0;
parchecked <= '0';
end if;
end if;
if resetn = '0' or sigsending = '1' then
sdata <= (others => '0');
parchecked <= '0';
count := 0;
end if;
end process;
odata_rdy <= en and parchecked;
odata <= sdata;
-- Edge triggered send register
process(idata_rdy, sigsendend, resetn)
begin
if(rising_edge(idata_rdy)) then
sigsending <= '1';
end if;
if resetn = '0' or sigsendend = '1' then
sigsending <= '0';
end if;
end process;
-- Wait for at least 11ms before allowing to send again
process(clk, sigsending, resetn)
-- clkfreq is the number of clocks within a milisecond
variable countclk : integer range 0 to (12 * clkfreq);
begin
if(rising_edge(clk) and sigsending = '0') then
if countclk = (11 * clkfreq) then
send_rdy <= '1';
else
countclk := countclk + 1;
end if;
end if;
if sigsending = '1' then
send_rdy <= '0';
countclk := 0;
end if;
if resetn = '0' then
send_rdy <= '1';
countclk := 0;
end if;
end process;
-- Host input data register
process(idata_rdy, sigsendend, resetn)
begin
if(rising_edge(idata_rdy)) then
hdata <= idata;
end if;
if resetn = '0' or sigsendend = '1' then
hdata <= (others => '0');
end if;
end process;
-- PS2 clock control
process(clk, sigsendend, resetn)
constant US100CNT : integer := clkfreq / 10;
variable count : integer range 0 to US100CNT + 101;
begin
if(rising_edge(clk) and sigsending = '1') then
if count < US100CNT + 50 then
count := count + 1;
ps2_clk <= '0';
sigclkreleased <= '0';
sigclkheld <= '0';
elsif count < US100CNT + 100 then
count := count + 1;
ps2_clk <= '0';
sigclkreleased <= '0';
sigclkheld <= '1';
else
ps2_clk <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
end if;
end if;
if resetn = '0' or sigsendend = '1' then
ps2_clk <= 'Z';
sigclkreleased <= '1';
sigclkheld <= '0';
count := 0;
end if;
end process;
-- Sending control
TOPS2:
process(sigtrigger, sigsending, sigclkheld, sigclkreleased, resetn)
variable count : integer range 0 to 11;
begin
if(rising_edge(sigtrigger) and sigclkreleased = '1'
and sigsending = '1') then
if count >= 0 and count < 8 then
ps2_data <= hdata(count);
sigsendend <= '0';
end if;
if count = 8 then
ps2_data <= (not (hdata(0) xor hdata(1) xor hdata(2) xor hdata(3)
xor hdata(4) xor hdata(5) xor hdata(6) xor hdata(7)));
sigsendend <= '0';
end if;
if count = 9 then
ps2_data <= 'Z';
sigsendend <= '0';
end if;
if count = 10 then
ps2_data <= 'Z';
sigsendend <= '1';
count := 0;
end if;
count := count + 1;
end if;
if sigclkheld = '1' then
ps2_data <= '0';
sigsendend <= '0';
count := 0;
end if;
if resetn = '0' or sigsending = '0' then
ps2_data <= 'Z';
sigsendend <= '0';
count := 0;
end if;
end process;
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
--
-- ZPUino WB wrapper around NetSID.
--
-- Copyright 2010-2012 Alvaro Lopes - alvieboy@alvie.com
--
-- The FreeBSD license
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above
-- copyright notice, this list of conditions and the following
-- disclaimer in the documentation and/or other materials
-- provided with the distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE ZPU PROJECT ``AS IS'' AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- The views and conclusions contained in the software and documentation
-- are those of the authors and should not be interpreted as representing
-- official policies, either expressed or implied, of the ZPU Project.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
library board;
use board.zpuino_config.all;
use board.zpu_config.all;
use board.zpupkg.all;
entity AUDIO_zpuino_wb_sid6581 is
port (
wishbone_in : in std_logic_vector(61 downto 0);
wishbone_out : out std_logic_vector(33 downto 0);
clk_1MHZ: in std_logic;
audio_data: out std_logic_vector(17 downto 0)
);
end entity AUDIO_zpuino_wb_sid6581;
architecture rtl of AUDIO_zpuino_wb_sid6581 is
component sid6581 is
port (
clk_1MHz : in std_logic; -- main SID clock signal
clk32 : in std_logic; -- main clock signal
clk_DAC : in std_logic; -- DAC clock signal, must be as high as possible for the best results
reset : in std_logic; -- high active signal (reset when reset = '1')
cs : in std_logic; -- "chip select", when this signal is '1' this model can be accessed
we : in std_logic; -- when '1' this model can be written to, otherwise access is considered as read
addr : in std_logic_vector(4 downto 0); -- address lines
di : in std_logic_vector(7 downto 0); -- data in (to chip)
do : out std_logic_vector(7 downto 0); -- data out (from chip)
pot_x : in std_logic; -- paddle input-X
pot_y : in std_logic; -- paddle input-Y
audio_out : out std_logic; -- this line holds the audio-signal in PWM format
audio_data : out std_logic_vector(17 downto 0)
);
end component;
signal cs: std_logic;
signal addr: std_logic_vector(4 downto 0);
signal di: std_logic_vector(7 downto 0);
signal do: std_logic_vector(7 downto 0);
signal ack_i: std_logic;
signal wb_clk_i: std_logic; -- Wishbone clock
signal wb_rst_i: std_logic; -- Wishbone reset (synchronous)
signal wb_dat_i: std_logic_vector(31 downto 0); -- Wishbone data input (32 bits)
signal wb_adr_i: std_logic_vector(26 downto 2); -- Wishbone address input (32 bits)
signal wb_we_i: std_logic; -- Wishbone write enable signal
signal wb_cyc_i: std_logic; -- Wishbone cycle signal
signal wb_stb_i: std_logic; -- Wishbone strobe signal
signal wb_dat_o: std_logic_vector(31 downto 0); -- Wishbone data output (32 bits)
signal wb_ack_o: std_logic; -- Wishbone acknowledge out signal
signal wb_inta_o: std_logic;
begin
-- Unpack the wishbone array into signals so the modules code is not confusing.
wb_clk_i <= wishbone_in(61);
wb_rst_i <= wishbone_in(60);
wb_dat_i <= wishbone_in(59 downto 28);
wb_adr_i <= wishbone_in(27 downto 3);
wb_we_i <= wishbone_in(2);
wb_cyc_i <= wishbone_in(1);
wb_stb_i <= wishbone_in(0);
wishbone_out(33 downto 2) <= wb_dat_o;
wishbone_out(1) <= wb_ack_o;
wishbone_out(0) <= wb_inta_o;
wb_dat_o(wordSize-1 downto 8) <= (others => '0');
wb_dat_o(7 downto 0) <= do;
cs <= (wb_stb_i and wb_cyc_i) and not ack_i;
di <= wb_dat_i(7 downto 0);
addr <= wb_adr_i(6 downto 2);
wb_ack_o <= ack_i;
process(wb_clk_i)
begin
if rising_edge(wb_clk_i) then
if wb_rst_i='1' then
ack_i<='0';
else
ack_i<='0';
if ack_i='0' then
if wb_stb_i='1' and wb_cyc_i='1' then
ack_i <= '1';
end if;
end if;
end if;
end if;
end process;
sid: sid6581
port map (
clk_1MHz => clk_1MHz,
clk32 => wb_clk_i,
clk_DAC => '0',
reset => wb_rst_i,
cs => cs,
we => wb_we_i,
addr => addr,
di => di,
do => do,
pot_x => 'X',
pot_y => 'X',
audio_out => open,
audio_data => audio_data
);
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity state_machine is
port(
clk: in std_logic;
rst: in std_logic;
state: out unsigned(1 downto 0) -- 00=fetch, 01=decode, 10=execute
);
end entity;
architecture a_state_machine of state_machine is
signal state_s: unsigned(1 downto 0);
begin
process(clk,rst)
begin
if rst='1' then
state_s <= "00";
elsif rising_edge(clk) then
if state_s="10" then --se está no ultimo state
state_s <= "00"; -- o prox volta ao zero
else
state_s <= state_s+1; -- senao avanca
end if;
end if;
end process;
state <= state_s;
end architecture;
|
configuration TIMING_FOR_var6 of var6_tb is
for TB_ARCHITECTURE
for UUT : var6
use entity work.var6(behavior);
end for;
for UUT2 : var6
use entity work.var6(structual);
end for;
end for;
end TIMING_FOR_var6;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Check overrides
if a = '1' then
case x is
end case;
end if;
if a = '1' then
case x is
end case;
end if;
-- Check loop statements
if a = '1' then
LOOP_LABEL : loop
end loop;
end if;
if a = '1' then
loop
end loop;
end if;
if a = '1' then
while a = 0
loop
end loop;
end if;
if a = '1' then
for i in 0 to 13
loop
end loop;
end if;
end process;
end architecture RTL;
|
--Practica6 de Diseño Automatico de Sistemas
--Pong El primer Videojuego.
--Control de Teclado PS2.
--Desarrollada por Héctor Gutiérrez Palancarejo.
library ieee;
use ieee.std_logic_1164.all;
entity ps2_interface is
port(
clk : in std_logic;
rst : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
new_data_ack : in std_logic;
data : out std_logic_vector(7 downto 0);
new_data : out std_logic
);
end ps2_interface;
architecture rtl of ps2_interface is
component synchronizer is
port(
x : in std_logic;
rst : in std_logic;
clk : in std_logic;
xsync : out std_logic
);
end component;
component edgedetector is
port(
rst : in std_logic;
x : in std_logic;
clk : in std_logic;
x_falling_edge : out std_logic;
x_rising_edge : out std_logic
);
end component;
type states_ps2 is (esperando_datos,esperando_ack);
signal current_state,next_state : states_ps2;
signal shifter_out : std_logic_vector(10 downto 0);
signal shifter,clear_shifter,valid_data : std_logic;
signal clk_sync : std_logic;
signal ld_reg : std_logic;
signal reg_out : std_logic_vector(7 downto 0);
signal parity : std_logic;
--trimmed signals:
signal trim1 : std_logic;
begin
state : process(clk,rst)
begin
if(rst = '0') then
current_state <= esperando_datos;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
gen_state : process(current_state,clear_shifter,new_data_ack,valid_data)
begin
next_state <= current_state;
case current_state is
when esperando_datos =>
if(valid_data = '1') then
next_state <= esperando_ack;
end if;
when esperando_ack =>
if(new_data_ack = '1') then
next_state <= esperando_datos;
end if;
end case;
end process;
gen_signals : process(current_state,clear_shifter,new_data_ack)
begin
case current_state is
when esperando_datos =>
new_data <= '0';
ld_reg <= '0';
if(clear_shifter = '1') then
ld_reg <= '1';
end if;
when esperando_ack =>
new_data <= '1';
ld_reg <= '0';
end case;
end process;
reg_shifter : process(clk,rst)
begin
if(rst = '0') then
shifter_out <= (others=>'1');
elsif(rising_edge(clk)) then
if(clear_shifter = '1') then
shifter_out <= (others=>'1');
end if;
if(shifter = '1') then
for i in 0 to 9 loop
shifter_out(i) <= shifter_out(i+1);
end loop;
shifter_out(10) <= ps2_data;
end if;
end if;
end process;
reg_data : process(clk,rst)
begin
if(rst = '0') then
reg_out <= (others=>'0');
elsif(rising_edge(clk)) then
if(ld_reg = '1') then
reg_out <= shifter_out(8 downto 1);
end if;
end if;
end process;
data <= reg_out;
parity <= (shifter_out(1) xor shifter_out(2) xor shifter_out(3) xor shifter_out(4)) xor (shifter_out(5) xor
shifter_out(6) xor shifter_out(7) xor shifter_out(8)) xor shifter_out(9);
clear_shifter <= not(shifter_out(0));
valid_data <= clear_shifter and parity;
u_sync_clk : synchronizer port map (x=>ps2_clk,rst=>rst,
clk=>clk,xsync=>clk_sync);
u_edge_clk : edgedetector port map (rst=>rst,x=>clk_sync,
clk=>clk,x_falling_edge=>shifter,x_rising_edge=>trim1);
end rtl; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:06 05/28/2011
-- Design Name:
-- Module Name: sha256_pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_pipeline is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
input : in STD_LOGIC_VECTOR (511 downto 0);
hash : out STD_LOGIC_VECTOR (255 downto 0));
end sha256_pipeline;
architecture Behavioral of sha256_pipeline is
COMPONENT sha256_transform
PORT(
clk : IN std_logic;
w_in : IN std_logic_vector(511 downto 0);
s_in : IN std_logic_vector(255 downto 0);
w_out : OUT std_logic_vector(511 downto 0);
s_out : OUT std_logic_vector(255 downto 0);
k : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
type k_array is array(integer range 0 to 63) of std_logic_vector(31 downto 0);
constant K : k_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
type w_array is array(integer range 0 to 64) of std_logic_vector(511 downto 0);
signal w : w_array;
type s_array is array(integer range 0 to 64) of std_logic_vector(255 downto 0);
signal s : s_array;
begin
w(0) <= input;
s(0) <= state;
hash(255 downto 224) <= state(255 downto 224) + s(2 ** DEPTH)(255 downto 224);
hash(223 downto 192) <= state(223 downto 192) + s(2 ** DEPTH)(223 downto 192);
hash(191 downto 160) <= state(191 downto 160) + s(2 ** DEPTH)(191 downto 160);
hash(159 downto 128) <= state(159 downto 128) + s(2 ** DEPTH)(159 downto 128);
hash(127 downto 96) <= state(127 downto 96) + s(2 ** DEPTH)(127 downto 96);
hash(95 downto 64) <= state(95 downto 64) + s(2 ** DEPTH)(95 downto 64);
hash(63 downto 32) <= state(63 downto 32) + s(2 ** DEPTH)(63 downto 32);
hash(31 downto 0) <= state(31 downto 0) + s(2 ** DEPTH)(31 downto 0);
rounds: for i in 0 to 2 ** DEPTH - 1 generate
signal round_k : std_logic_vector(31 downto 0);
signal round_w : std_logic_vector(511 downto 0);
signal round_s : std_logic_vector(255 downto 0);
begin
round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
round_w <= w(i) when step = "000000" else w(i + 1);
round_s <= s(i) when step = "000000" else s(i + 1);
transform: sha256_transform
port map (
clk => clk,
w_in => round_w,
w_out => w(i + 1),
s_in => round_s,
s_out => s(i + 1),
k => round_k
);
end generate;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:06 05/28/2011
-- Design Name:
-- Module Name: sha256_pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_pipeline is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
input : in STD_LOGIC_VECTOR (511 downto 0);
hash : out STD_LOGIC_VECTOR (255 downto 0));
end sha256_pipeline;
architecture Behavioral of sha256_pipeline is
COMPONENT sha256_transform
PORT(
clk : IN std_logic;
w_in : IN std_logic_vector(511 downto 0);
s_in : IN std_logic_vector(255 downto 0);
w_out : OUT std_logic_vector(511 downto 0);
s_out : OUT std_logic_vector(255 downto 0);
k : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
type k_array is array(integer range 0 to 63) of std_logic_vector(31 downto 0);
constant K : k_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
type w_array is array(integer range 0 to 64) of std_logic_vector(511 downto 0);
signal w : w_array;
type s_array is array(integer range 0 to 64) of std_logic_vector(255 downto 0);
signal s : s_array;
begin
w(0) <= input;
s(0) <= state;
hash(255 downto 224) <= state(255 downto 224) + s(2 ** DEPTH)(255 downto 224);
hash(223 downto 192) <= state(223 downto 192) + s(2 ** DEPTH)(223 downto 192);
hash(191 downto 160) <= state(191 downto 160) + s(2 ** DEPTH)(191 downto 160);
hash(159 downto 128) <= state(159 downto 128) + s(2 ** DEPTH)(159 downto 128);
hash(127 downto 96) <= state(127 downto 96) + s(2 ** DEPTH)(127 downto 96);
hash(95 downto 64) <= state(95 downto 64) + s(2 ** DEPTH)(95 downto 64);
hash(63 downto 32) <= state(63 downto 32) + s(2 ** DEPTH)(63 downto 32);
hash(31 downto 0) <= state(31 downto 0) + s(2 ** DEPTH)(31 downto 0);
rounds: for i in 0 to 2 ** DEPTH - 1 generate
signal round_k : std_logic_vector(31 downto 0);
signal round_w : std_logic_vector(511 downto 0);
signal round_s : std_logic_vector(255 downto 0);
begin
round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
round_w <= w(i) when step = "000000" else w(i + 1);
round_s <= s(i) when step = "000000" else s(i + 1);
transform: sha256_transform
port map (
clk => clk,
w_in => round_w,
w_out => w(i + 1),
s_in => round_s,
s_out => s(i + 1),
k => round_k
);
end generate;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:06 05/28/2011
-- Design Name:
-- Module Name: sha256_pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_pipeline is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
input : in STD_LOGIC_VECTOR (511 downto 0);
hash : out STD_LOGIC_VECTOR (255 downto 0));
end sha256_pipeline;
architecture Behavioral of sha256_pipeline is
COMPONENT sha256_transform
PORT(
clk : IN std_logic;
w_in : IN std_logic_vector(511 downto 0);
s_in : IN std_logic_vector(255 downto 0);
w_out : OUT std_logic_vector(511 downto 0);
s_out : OUT std_logic_vector(255 downto 0);
k : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
type k_array is array(integer range 0 to 63) of std_logic_vector(31 downto 0);
constant K : k_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
type w_array is array(integer range 0 to 64) of std_logic_vector(511 downto 0);
signal w : w_array;
type s_array is array(integer range 0 to 64) of std_logic_vector(255 downto 0);
signal s : s_array;
begin
w(0) <= input;
s(0) <= state;
hash(255 downto 224) <= state(255 downto 224) + s(2 ** DEPTH)(255 downto 224);
hash(223 downto 192) <= state(223 downto 192) + s(2 ** DEPTH)(223 downto 192);
hash(191 downto 160) <= state(191 downto 160) + s(2 ** DEPTH)(191 downto 160);
hash(159 downto 128) <= state(159 downto 128) + s(2 ** DEPTH)(159 downto 128);
hash(127 downto 96) <= state(127 downto 96) + s(2 ** DEPTH)(127 downto 96);
hash(95 downto 64) <= state(95 downto 64) + s(2 ** DEPTH)(95 downto 64);
hash(63 downto 32) <= state(63 downto 32) + s(2 ** DEPTH)(63 downto 32);
hash(31 downto 0) <= state(31 downto 0) + s(2 ** DEPTH)(31 downto 0);
rounds: for i in 0 to 2 ** DEPTH - 1 generate
signal round_k : std_logic_vector(31 downto 0);
signal round_w : std_logic_vector(511 downto 0);
signal round_s : std_logic_vector(255 downto 0);
begin
round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
round_w <= w(i) when step = "000000" else w(i + 1);
round_s <= s(i) when step = "000000" else s(i + 1);
transform: sha256_transform
port map (
clk => clk,
w_in => round_w,
w_out => w(i + 1),
s_in => round_s,
s_out => s(i + 1),
k => round_k
);
end generate;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:22:06 05/28/2011
-- Design Name:
-- Module Name: sha256_pipeline - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity sha256_pipeline is
generic ( DEPTH : integer );
Port ( clk : in STD_LOGIC;
step : in STD_LOGIC_VECTOR (5 downto 0);
state : in STD_LOGIC_VECTOR (255 downto 0);
input : in STD_LOGIC_VECTOR (511 downto 0);
hash : out STD_LOGIC_VECTOR (255 downto 0));
end sha256_pipeline;
architecture Behavioral of sha256_pipeline is
COMPONENT sha256_transform
PORT(
clk : IN std_logic;
w_in : IN std_logic_vector(511 downto 0);
s_in : IN std_logic_vector(255 downto 0);
w_out : OUT std_logic_vector(511 downto 0);
s_out : OUT std_logic_vector(255 downto 0);
k : IN std_logic_vector(31 downto 0)
);
END COMPONENT;
type k_array is array(integer range 0 to 63) of std_logic_vector(31 downto 0);
constant K : k_array := (
x"428a2f98", x"71374491", x"b5c0fbcf", x"e9b5dba5", x"3956c25b", x"59f111f1", x"923f82a4", x"ab1c5ed5",
x"d807aa98", x"12835b01", x"243185be", x"550c7dc3", x"72be5d74", x"80deb1fe", x"9bdc06a7", x"c19bf174",
x"e49b69c1", x"efbe4786", x"0fc19dc6", x"240ca1cc", x"2de92c6f", x"4a7484aa", x"5cb0a9dc", x"76f988da",
x"983e5152", x"a831c66d", x"b00327c8", x"bf597fc7", x"c6e00bf3", x"d5a79147", x"06ca6351", x"14292967",
x"27b70a85", x"2e1b2138", x"4d2c6dfc", x"53380d13", x"650a7354", x"766a0abb", x"81c2c92e", x"92722c85",
x"a2bfe8a1", x"a81a664b", x"c24b8b70", x"c76c51a3", x"d192e819", x"d6990624", x"f40e3585", x"106aa070",
x"19a4c116", x"1e376c08", x"2748774c", x"34b0bcb5", x"391c0cb3", x"4ed8aa4a", x"5b9cca4f", x"682e6ff3",
x"748f82ee", x"78a5636f", x"84c87814", x"8cc70208", x"90befffa", x"a4506ceb", x"bef9a3f7", x"c67178f2"
);
type w_array is array(integer range 0 to 64) of std_logic_vector(511 downto 0);
signal w : w_array;
type s_array is array(integer range 0 to 64) of std_logic_vector(255 downto 0);
signal s : s_array;
begin
w(0) <= input;
s(0) <= state;
hash(255 downto 224) <= state(255 downto 224) + s(2 ** DEPTH)(255 downto 224);
hash(223 downto 192) <= state(223 downto 192) + s(2 ** DEPTH)(223 downto 192);
hash(191 downto 160) <= state(191 downto 160) + s(2 ** DEPTH)(191 downto 160);
hash(159 downto 128) <= state(159 downto 128) + s(2 ** DEPTH)(159 downto 128);
hash(127 downto 96) <= state(127 downto 96) + s(2 ** DEPTH)(127 downto 96);
hash(95 downto 64) <= state(95 downto 64) + s(2 ** DEPTH)(95 downto 64);
hash(63 downto 32) <= state(63 downto 32) + s(2 ** DEPTH)(63 downto 32);
hash(31 downto 0) <= state(31 downto 0) + s(2 ** DEPTH)(31 downto 0);
rounds: for i in 0 to 2 ** DEPTH - 1 generate
signal round_k : std_logic_vector(31 downto 0);
signal round_w : std_logic_vector(511 downto 0);
signal round_s : std_logic_vector(255 downto 0);
begin
round_k <= K(i * 2 ** (6 - DEPTH) + conv_integer(step));
round_w <= w(i) when step = "000000" else w(i + 1);
round_s <= s(i) when step = "000000" else s(i + 1);
transform: sha256_transform
port map (
clk => clk,
w_in => round_w,
w_out => w(i + 1),
s_in => round_s,
s_out => s(i + 1),
k => round_k
);
end generate;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Felix Winterstein, Imperial College London
--
-- Module Name: closest_to_point_top - Behavioral
--
-- Revision 1.01
-- Additional Comments: distributed under a BSD license, see LICENSE.txt
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.math_real.all;
use work.lloyds_algorithm_pkg.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity closest_to_point_top is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
u_in : in node_data_type;
point : in data_type;
point_list_d : in data_type; -- assume FIFO interface !!!
min_point : out data_type;
min_index : out centre_index_type;
min_distance : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end closest_to_point_top;
architecture Behavioral of closest_to_point_top is
type state_type is (idle, processing);
constant LAT_DOT_PRODUCT : integer := 3+2*integer(ceil(log2(real(D))));
constant LAT_SUB : integer := 2;
constant LATENCY : integer := LAT_DOT_PRODUCT+LAT_SUB;
type node_data_delay_type is array(0 to LATENCY-1) of node_data_type;
component compute_distance_top
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
point_1 : in data_type;
point_2 : in data_type;
distance : out coord_type_ext;
point_1_out : out data_type;
point_2_out : out data_type;
rdy : out std_logic
);
end component;
component min_search is
port (
clk : in std_logic;
sclr : in std_logic;
nd : in std_logic;
metric_in : in coord_type_ext;
u_in : in node_data_type;
point_in : in data_type;
min_point : out data_type;
min_index : out centre_index_type;
min_metric : out coord_type_ext;
u_out : out node_data_type;
rdy : out std_logic
);
end component;
signal reg_u_in : node_data_type;
signal reg_point : data_type;
signal reg_point_list_d : data_type;
signal state : state_type;
signal compute_distance_nd : std_logic;
signal compute_distance_rdy : std_logic;
signal distance : coord_type_ext;
signal point_list_d_delayed : data_type;
signal point_list_idx_delayed : centre_index_type;
signal tmp_min_index : centre_index_type;
signal tmp_min_point : data_type;
signal tmp_min_distance : coord_type_ext;
signal tmp_min_search_rdy : std_logic;
signal node_data_delay : node_data_delay_type;
begin
fsm_proc : process(clk)
begin
if rising_edge(clk) then
if sclr = '1' then
state <= idle;
elsif state = idle AND nd='1' then
state <= processing;
elsif state = processing AND nd='0' then
state <= idle;
end if;
end if;
end process fsm_proc;
-- need to delay by one cycle due to state machine
reg_point_list_d_proc : process(clk)
begin
if rising_edge(clk) then
if state = idle AND nd= '1' then
reg_u_in <= u_in;
reg_point <= point;
end if;
reg_point_list_d <= point_list_d;
end if;
end process reg_point_list_d_proc;
compute_distance_nd <= '1' WHEN state = processing ELSE '0';
compute_distance_top_inst : compute_distance_top
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_nd,
point_1 => reg_point,
point_2 => reg_point_list_d,
distance => distance,
point_1_out => open,
point_2_out => point_list_d_delayed,
rdy => compute_distance_rdy
);
-- feed u_in from input of dot-product to output of dot-product
data_delay_proc : process(clk)
begin
if rising_edge(clk) then
node_data_delay(0) <= reg_u_in;
node_data_delay(1 to LATENCY-1) <= node_data_delay(0 to LATENCY-2);
end if;
end process data_delay_proc;
-- search min
min_search_inst : min_search
port map (
clk => clk,
sclr => sclr,
nd => compute_distance_rdy,
metric_in => distance,
u_in => node_data_delay(LATENCY-1),
point_in => point_list_d_delayed,
min_point => tmp_min_point,
min_index => tmp_min_index,
min_metric => tmp_min_distance,
u_out => u_out,
rdy => tmp_min_search_rdy
);
min_point <= tmp_min_point;
min_index <= tmp_min_index;
min_distance <= tmp_min_distance;
rdy <= tmp_min_search_rdy;
end Behavioral;
|
--!
--! @file: exercise9_6.vhd
--! @brief: function bcd_to_ssd
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package exercise9_6 is
function bcd_to_ssd(bcd : std_logic_vector) return std_logic_vector
end package exercise9_6;
------------------------------
package body exercise9_6 is
function bcd_to_ssd(bcd : std_logic_vector) return std_logic_vector is
variable bcd_uns: unsigned range 0 to (2**std_logic_vector'length)-1
variable ssd: std_logic_vector(6 downto 0);
begin
bcd_uns := unsigned(bcd);
-- check for bcd code = 4
assert (bcd'length = 4)
report "not bcd code in input!"
severity failure;
-- bcd to ssd conversion
case1: case bcd_uns is
when 0 => ssd := "0000001";
when 1 => ssd := "1001111";
when 2 => ssd := "0010010";
when 3 => ssd := "0000110";
when 4 => ssd := "1001100";
when 5 => ssd := "0100100";
when 6 => ssd := "0100000";
when 7 => ssd := "0001111";
when 8 => ssd := "0000000";
when 9 => ssd := "0000100";
when others => ssd := "0110000"; -- 'E' on SSD for Error
end case case1;
return ssd;
end function bcd_to_ssd;
end package body exercise9_6;
--------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_852 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_852;
architecture augh of cmp_852 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_852 is
port (
eq : out std_logic;
in1 : in std_logic_vector(31 downto 0);
in0 : in std_logic_vector(31 downto 0)
);
end cmp_852;
architecture augh of cmp_852 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in1 /= in0 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 0;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 1;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 0;
constant FDIV_IMPLEMENT : integer := 0;
constant FSQRT_IMPLEMENT : integer := 0;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 1;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FADD_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (win64) Build 881834 Fri Apr 4 14:15:54 MDT 2014
-- Date : Thu Jul 24 13:40:02 2014
-- Host : CE-2013-124 running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode funcsim
-- D:/SHS/Research/AutoEnetGway/Mine/xc702/aes_xc702/aes_xc702.srcs/sources_1/ip/fifo_generator_0/fifo_generator_0_funcsim.vhdl
-- Design : fifo_generator_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_prim_wrapper is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end fifo_generator_0blk_mem_gen_prim_wrapper;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_prim_wrapper is
signal \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
signal \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : STD_LOGIC;
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "SDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 0,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 0,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(13) => '0',
ADDRARDADDR(12) => '0',
ADDRARDADDR(11) => '0',
ADDRARDADDR(10) => '0',
ADDRARDADDR(9) => '0',
ADDRARDADDR(8 downto 5) => O1(3 downto 0),
ADDRARDADDR(4) => '0',
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8 downto 5) => I1(3 downto 0),
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => rd_clk,
CLKBWRCLK => wr_clk,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9 downto 8) => din(4 downto 3),
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2 downto 0) => din(2 downto 0),
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9 downto 8) => din(9 downto 8),
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2 downto 0) => din(7 downto 5),
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15) => \n_0_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(14) => \n_1_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(13) => \n_2_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(12) => \n_3_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(11) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(10) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(9 downto 8) => dout(4 downto 3),
DOADO(7) => \n_8_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(6) => \n_9_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(5) => \n_10_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(4) => \n_11_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(3) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOADO(2 downto 0) => dout(2 downto 0),
DOBDO(15) => \n_16_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(14) => \n_17_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(13) => \n_18_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(12) => \n_19_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(11) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(10) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(9 downto 8) => dout(9 downto 8),
DOBDO(7) => \n_24_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(6) => \n_25_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(5) => \n_26_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(4) => \n_27_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(3) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOBDO(2 downto 0) => dout(7 downto 5),
DOPADOP(1) => \n_32_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPADOP(0) => \n_33_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(1) => \n_34_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
DOPBDOP(0) => \n_35_DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram\,
ENARDEN => tmp_ram_rd_en,
ENBWREN => E(0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rd_rst,
RSTRAMB => rd_rst,
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => E(0),
WEBWE(2) => E(0),
WEBWE(1) => E(0),
WEBWE(0) => E(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_bin_cntr : entity is "rd_bin_cntr";
end fifo_generator_0rd_bin_cntr;
architecture STRUCTURE of fifo_generator_0rd_bin_cntr is
signal \^o1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair4";
attribute counter : integer;
attribute counter of \gc0.count_reg[0]\ : label is 2;
attribute counter of \gc0.count_reg[1]\ : label is 2;
attribute counter of \gc0.count_reg[2]\ : label is 2;
attribute counter of \gc0.count_reg[3]\ : label is 2;
attribute SOFT_HLUTNM of \rd_pntr_gc[0]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \rd_pntr_gc[1]_i_1\ : label is "soft_lutpair5";
begin
O1(3 downto 0) <= \^o1\(3 downto 0);
Q(3 downto 0) <= \^q\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(1),
I2 => \^q\(0),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \^q\(3),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(2),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(0),
Q => \^o1\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(1),
Q => \^o1\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(2),
Q => \^o1\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => \^q\(3),
Q => \^o1\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => E(0),
D => plusOp(0),
PRE => rd_rst,
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => E(0),
CLR => rd_rst,
D => plusOp(3),
Q => \^q\(3)
);
\rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(1),
I1 => \^o1\(0),
O => D(0)
);
\rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(1),
I1 => \^o1\(2),
O => D(1)
);
\rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^o1\(2),
I1 => \^o1\(3),
O => D(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_handshaking_flags is
port (
valid : out STD_LOGIC;
ram_valid_i : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_handshaking_flags : entity is "rd_handshaking_flags";
end fifo_generator_0rd_handshaking_flags;
architecture STRUCTURE of fifo_generator_0rd_handshaking_flags is
begin
\gv.ram_valid_d1_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => ram_valid_i,
Q => valid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_status_flags_as is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
tmp_ram_rd_en : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_valid_i : out STD_LOGIC;
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_status_flags_as : entity is "rd_status_flags_as";
end fifo_generator_0rd_status_flags_as;
architecture STRUCTURE of fifo_generator_0rd_status_flags_as is
signal \^empty\ : STD_LOGIC;
signal \^p_18_out\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count_d1[3]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gv.ram_valid_d1_i_1\ : label is "soft_lutpair3";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
empty <= \^empty\;
p_18_out <= \^p_18_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"BA"
)
port map (
I0 => rd_rst,
I1 => \^p_18_out\,
I2 => rd_en,
O => tmp_ram_rd_en
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^p_18_out\,
O => E(0)
);
\gv.ram_valid_d1_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => rd_en,
I1 => \^empty\,
O => ram_valid_i
);
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => rd_rst,
Q => \^p_18_out\
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => rd_clk,
CE => '1',
D => I1,
PRE => rd_rst,
Q => \^empty\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0reset_blk_ramfifo is
port (
rst_full_gen_i : out STD_LOGIC;
rst_d2 : out STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0reset_blk_ramfifo : entity is "reset_blk_ramfifo";
end fifo_generator_0reset_blk_ramfifo;
architecture STRUCTURE of fifo_generator_0reset_blk_ramfifo is
signal rst_d1 : STD_LOGIC;
signal \^rst_d2\ : STD_LOGIC;
signal rst_d3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
begin
rst_d2 <= \^rst_d2\;
\grstd1.grst_full.grst_f.RST_FULL_GEN_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => rst_d3,
Q => rst_full_gen_i
);
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => '0',
PRE => wr_rst,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => rst_d1,
PRE => wr_rst,
Q => \^rst_d2\
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => \^rst_d2\,
PRE => wr_rst,
Q => rst_d3
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff;
architecture STRUCTURE of fifo_generator_0synchronizer_ff is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff_0 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff_0 : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff_0;
architecture STRUCTURE of fifo_generator_0synchronizer_ff_0 is
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(0),
Q => Q(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(1),
Q => Q(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(2),
Q => Q(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(3),
Q => Q(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff_1 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff_1 : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff_1;
architecture STRUCTURE of fifo_generator_0synchronizer_ff_1 is
signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(1 downto 0) <= \^d\(1 downto 0);
Q(2 downto 0) <= \^q\(2 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(0),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(1),
Q => \^q\(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(2),
Q => \^q\(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => \^d\(1)
);
\wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^d\(1),
O => \^d\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0synchronizer_ff_2 is
port (
D : out STD_LOGIC_VECTOR ( 1 downto 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0synchronizer_ff_2 : entity is "synchronizer_ff";
end fifo_generator_0synchronizer_ff_2;
architecture STRUCTURE of fifo_generator_0synchronizer_ff_2 is
signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \Q_reg_reg[0]\ : label is std.standard.true;
attribute msgon : string;
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[1]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[2]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG of \Q_reg_reg[3]\ : label is std.standard.true;
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(1 downto 0) <= \^d\(1 downto 0);
Q(2 downto 0) <= \^q\(2 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(0),
Q => \^q\(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(1),
Q => \^q\(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(2),
Q => \^q\(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I1(3),
Q => \^d\(1)
);
\rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(2),
I1 => \^d\(1),
O => \^d\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0wr_bin_cntr is
port (
ram_full_i : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_full_gen_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
p_0_out : in STD_LOGIC;
I1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0wr_bin_cntr : entity is "wr_bin_cntr";
end fifo_generator_0wr_bin_cntr;
architecture STRUCTURE of fifo_generator_0wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal n_0_ram_full_i_i_2 : STD_LOGIC;
signal n_0_ram_full_i_i_3 : STD_LOGIC;
signal n_0_ram_full_i_i_4 : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute RETAIN_INVERTER : boolean;
attribute RETAIN_INVERTER of \gic0.gc0.count[0]_i_1\ : label is std.standard.true;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair7";
attribute counter : integer;
attribute counter of \gic0.gc0.count_reg[0]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[1]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[2]\ : label is 3;
attribute counter of \gic0.gc0.count_reg[3]\ : label is 3;
attribute SOFT_HLUTNM of ram_full_i_i_2 : label is "soft_lutpair6";
begin
Q(2 downto 0) <= \^q\(2 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => wr_pntr_plus2(0),
O => \plusOp__0\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => wr_pntr_plus2(0),
I1 => wr_pntr_plus2(1),
O => \plusOp__0\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => wr_pntr_plus2(1),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(2),
O => \plusOp__0\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => wr_pntr_plus2(0),
I2 => wr_pntr_plus2(1),
I3 => wr_pntr_plus2(3),
O => \plusOp__0\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => wr_pntr_plus2(0),
PRE => wr_rst,
Q => \^q\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(1),
Q => \^q\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(2),
Q => \^q\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => wr_pntr_plus2(3),
Q => p_8_out(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(0),
Q => O1(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(1),
Q => O1(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \^q\(2),
Q => O1(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => p_8_out(3),
Q => O1(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(0),
Q => wr_pntr_plus2(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => E(0),
D => \plusOp__0\(1),
PRE => wr_rst,
Q => wr_pntr_plus2(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(2),
Q => wr_pntr_plus2(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => E(0),
CLR => wr_rst,
D => \plusOp__0\(3),
Q => wr_pntr_plus2(3)
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF800880088008"
)
port map (
I0 => n_0_ram_full_i_i_2,
I1 => n_0_ram_full_i_i_3,
I2 => O3(1),
I3 => wr_pntr_plus2(1),
I4 => n_0_ram_full_i_i_4,
I5 => I1,
O => ram_full_i
);
ram_full_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => wr_pntr_plus2(2),
I1 => O3(2),
I2 => wr_pntr_plus2(0),
I3 => O3(0),
O => n_0_ram_full_i_i_2
);
ram_full_i_i_3: unisim.vcomponents.LUT5
generic map(
INIT => X"00000900"
)
port map (
I0 => wr_pntr_plus2(3),
I1 => O3(3),
I2 => rst_full_gen_i,
I3 => wr_en,
I4 => p_0_out,
O => n_0_ram_full_i_i_3
);
ram_full_i_i_4: unisim.vcomponents.LUT3
generic map(
INIT => X"09"
)
port map (
I0 => p_8_out(3),
I1 => O3(3),
I2 => rst_full_gen_i,
O => n_0_ram_full_i_i_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0wr_status_flags_as is
port (
full : out STD_LOGIC;
p_0_out : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_full_i : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
wr_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0wr_status_flags_as : entity is "wr_status_flags_as";
end fifo_generator_0wr_status_flags_as;
architecture STRUCTURE of fifo_generator_0wr_status_flags_as is
signal \^p_0_out\ : STD_LOGIC;
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
p_0_out <= \^p_0_out\;
\DEVICE_7SERIES.NO_BMM_INFO.SDP.WIDE_PRIM18.ram_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => wr_en,
I1 => \^p_0_out\,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => \^p_0_out\
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => wr_clk,
CE => '1',
D => ram_full_i,
PRE => rst_d2,
Q => full
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_prim_width is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end fifo_generator_0blk_mem_gen_prim_width;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.fifo_generator_0blk_mem_gen_prim_wrapper
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0clk_x_pntrs is
port (
O1 : out STD_LOGIC;
O2 : out STD_LOGIC;
O3 : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_en : in STD_LOGIC;
p_18_out : in STD_LOGIC;
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I2 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I3 : in STD_LOGIC_VECTOR ( 2 downto 0 );
I4 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0clk_x_pntrs : entity is "clk_x_pntrs";
end fifo_generator_0clk_x_pntrs;
architecture STRUCTURE of fifo_generator_0clk_x_pntrs is
signal \^o3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal Q : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \n_0_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_0_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal n_0_ram_empty_i_i_2 : STD_LOGIC;
signal n_0_ram_empty_i_i_3 : STD_LOGIC;
signal n_0_ram_empty_i_i_4 : STD_LOGIC;
signal n_0_ram_empty_i_i_5 : STD_LOGIC;
signal \n_0_rd_pntr_bin[0]_i_1\ : STD_LOGIC;
signal \n_0_rd_pntr_bin[1]_i_1\ : STD_LOGIC;
signal \n_1_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_1_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_2_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[1].wr_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_3_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].rd_stg_inst\ : STD_LOGIC;
signal \n_4_gsync_stage[2].wr_stg_inst\ : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_in1_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_1_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \rd_pntr_bin[0]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \rd_pntr_bin[1]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \wr_pntr_bin[0]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_bin[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \wr_pntr_gc[1]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \wr_pntr_gc[2]_i_1\ : label is "soft_lutpair2";
begin
O3(3 downto 0) <= \^o3\(3 downto 0);
\gsync_stage[1].rd_stg_inst\: entity work.fifo_generator_0synchronizer_ff
port map (
I1(3 downto 0) => wr_pntr_gc(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[1].wr_stg_inst\: entity work.fifo_generator_0synchronizer_ff_0
port map (
I1(3 downto 0) => rd_pntr_gc(3 downto 0),
Q(3) => \n_0_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_1_gsync_stage[1].wr_stg_inst\,
Q(1) => \n_2_gsync_stage[1].wr_stg_inst\,
Q(0) => \n_3_gsync_stage[1].wr_stg_inst\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gsync_stage[2].rd_stg_inst\: entity work.fifo_generator_0synchronizer_ff_1
port map (
D(1 downto 0) => p_0_in(3 downto 2),
I1(3 downto 0) => Q(3 downto 0),
Q(2) => \n_2_gsync_stage[2].rd_stg_inst\,
Q(1) => \n_3_gsync_stage[2].rd_stg_inst\,
Q(0) => \n_4_gsync_stage[2].rd_stg_inst\,
rd_clk => rd_clk,
rd_rst => rd_rst
);
\gsync_stage[2].wr_stg_inst\: entity work.fifo_generator_0synchronizer_ff_2
port map (
D(1) => \n_0_gsync_stage[2].wr_stg_inst\,
D(0) => \n_1_gsync_stage[2].wr_stg_inst\,
I1(3) => \n_0_gsync_stage[1].wr_stg_inst\,
I1(2) => \n_1_gsync_stage[1].wr_stg_inst\,
I1(1) => \n_2_gsync_stage[1].wr_stg_inst\,
I1(0) => \n_3_gsync_stage[1].wr_stg_inst\,
Q(2) => \n_2_gsync_stage[2].wr_stg_inst\,
Q(1) => \n_3_gsync_stage[2].wr_stg_inst\,
Q(0) => \n_4_gsync_stage[2].wr_stg_inst\,
wr_clk => wr_clk,
wr_rst => wr_rst
);
ram_empty_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0010FFFF00100010"
)
port map (
I0 => n_0_ram_empty_i_i_2,
I1 => n_0_ram_empty_i_i_3,
I2 => rd_en,
I3 => p_18_out,
I4 => n_0_ram_empty_i_i_4,
I5 => n_0_ram_empty_i_i_5,
O => O1
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(1),
I1 => I2(1),
I2 => p_1_out(0),
I3 => I2(0),
O => n_0_ram_empty_i_i_2
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(2),
I1 => I2(2),
I2 => p_1_out(3),
I3 => I2(3),
O => n_0_ram_empty_i_i_3
);
ram_empty_i_i_4: unisim.vcomponents.LUT4
generic map(
INIT => X"6FF6"
)
port map (
I0 => p_1_out(0),
I1 => I1(0),
I2 => p_1_out(2),
I3 => I1(2),
O => n_0_ram_empty_i_i_4
);
ram_empty_i_i_5: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => p_1_out(1),
I1 => I1(1),
I2 => p_1_out(3),
I3 => I1(3),
O => n_0_ram_empty_i_i_5
);
ram_full_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^o3\(2),
I1 => I3(2),
I2 => \^o3\(1),
I3 => I3(1),
I4 => I3(0),
I5 => \^o3\(0),
O => O2
);
\rd_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_3_gsync_stage[2].wr_stg_inst\,
I1 => \n_4_gsync_stage[2].wr_stg_inst\,
I2 => \n_0_gsync_stage[2].wr_stg_inst\,
I3 => \n_2_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[0]_i_1\
);
\rd_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_2_gsync_stage[2].wr_stg_inst\,
I1 => \n_3_gsync_stage[2].wr_stg_inst\,
I2 => \n_0_gsync_stage[2].wr_stg_inst\,
O => \n_0_rd_pntr_bin[1]_i_1\
);
\rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[0]_i_1\,
Q => \^o3\(0)
);
\rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_rd_pntr_bin[1]_i_1\,
Q => \^o3\(1)
);
\rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_1_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(2)
);
\rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => \n_0_gsync_stage[2].wr_stg_inst\,
Q => \^o3\(3)
);
\rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(0),
Q => rd_pntr_gc(0)
);
\rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(1),
Q => rd_pntr_gc(1)
);
\rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => D(2),
Q => rd_pntr_gc(2)
);
\rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => I1(3),
Q => rd_pntr_gc(3)
);
\wr_pntr_bin[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => \n_3_gsync_stage[2].rd_stg_inst\,
I1 => \n_4_gsync_stage[2].rd_stg_inst\,
I2 => p_0_in(3),
I3 => \n_2_gsync_stage[2].rd_stg_inst\,
O => p_0_in(0)
);
\wr_pntr_bin[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \n_2_gsync_stage[2].rd_stg_inst\,
I1 => \n_3_gsync_stage[2].rd_stg_inst\,
I2 => p_0_in(3),
O => p_0_in(1)
);
\wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(0),
Q => p_1_out(0)
);
\wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(1),
Q => p_1_out(1)
);
\wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(2),
Q => p_1_out(2)
);
\wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => rd_clk,
CE => '1',
CLR => rd_rst,
D => p_0_in(3),
Q => p_1_out(3)
);
\wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I4(0),
I1 => I4(1),
O => p_0_in1_out(0)
);
\wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I4(1),
I1 => I4(2),
O => p_0_in1_out(1)
);
\wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => I4(2),
I1 => I4(3),
O => p_0_in1_out(2)
);
\wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in1_out(0),
Q => wr_pntr_gc(0)
);
\wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in1_out(1),
Q => wr_pntr_gc(1)
);
\wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => p_0_in1_out(2),
Q => wr_pntr_gc(2)
);
\wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => wr_clk,
CE => '1',
CLR => wr_rst,
D => I4(3),
Q => wr_pntr_gc(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0rd_logic is
port (
empty : out STD_LOGIC;
p_18_out : out STD_LOGIC;
valid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
tmp_ram_rd_en : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0rd_logic : entity is "rd_logic";
end fifo_generator_0rd_logic;
architecture STRUCTURE of fifo_generator_0rd_logic is
signal p_14_out : STD_LOGIC;
signal ram_valid_i : STD_LOGIC;
begin
\gras.rsts\: entity work.fifo_generator_0rd_status_flags_as
port map (
E(0) => p_14_out,
I1 => I1,
empty => empty,
p_18_out => p_18_out,
ram_valid_i => ram_valid_i,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en
);
\grhf.rhf\: entity work.fifo_generator_0rd_handshaking_flags
port map (
ram_valid_i => ram_valid_i,
rd_clk => rd_clk,
rd_rst => rd_rst,
valid => valid
);
rpntr: entity work.fifo_generator_0rd_bin_cntr
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => p_14_out,
O1(3 downto 0) => O1(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0wr_logic is
port (
full : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
O1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_clk : in STD_LOGIC;
rst_d2 : in STD_LOGIC;
O3 : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_full_gen_i : in STD_LOGIC;
wr_en : in STD_LOGIC;
I1 : in STD_LOGIC;
wr_rst : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0wr_logic : entity is "wr_logic";
end fifo_generator_0wr_logic;
architecture STRUCTURE of fifo_generator_0wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out : STD_LOGIC;
signal ram_full_i : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.fifo_generator_0wr_status_flags_as
port map (
E(0) => \^e\(0),
full => full,
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_d2 => rst_d2,
wr_clk => wr_clk,
wr_en => wr_en
);
wpntr: entity work.fifo_generator_0wr_bin_cntr
port map (
E(0) => \^e\(0),
I1 => I1,
O1(3 downto 0) => O1(3 downto 0),
O3(3 downto 0) => O3(3 downto 0),
Q(2 downto 0) => Q(2 downto 0),
p_0_out => p_0_out,
ram_full_i => ram_full_i,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_generic_cstr is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end fifo_generator_0blk_mem_gen_generic_cstr;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.fifo_generator_0blk_mem_gen_prim_width
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_top is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_top : entity is "blk_mem_gen_top";
end fifo_generator_0blk_mem_gen_top;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_top is
begin
\valid.cstr\: entity work.fifo_generator_0blk_mem_gen_generic_cstr
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0blk_mem_gen_v8_2_synth is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end fifo_generator_0blk_mem_gen_v8_2_synth;
architecture STRUCTURE of fifo_generator_0blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.fifo_generator_0blk_mem_gen_top
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_0blk_mem_gen_v8_2__parameterized0\ is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_0blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
end \fifo_generator_0blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \fifo_generator_0blk_mem_gen_v8_2__parameterized0\ is
begin
inst_blk_mem_gen: entity work.fifo_generator_0blk_mem_gen_v8_2_synth
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0memory is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
tmp_ram_rd_en : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
rd_rst : in STD_LOGIC;
O1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
I1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
din : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0memory : entity is "memory";
end fifo_generator_0memory;
architecture STRUCTURE of fifo_generator_0memory is
begin
\gbm.gbmg.gbmga.ngecc.bmg\: entity work.\fifo_generator_0blk_mem_gen_v8_2__parameterized0\
port map (
E(0) => E(0),
I1(3 downto 0) => I1(3 downto 0),
O1(3 downto 0) => O1(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0fifo_generator_ramfifo is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
valid : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0fifo_generator_ramfifo : entity is "fifo_generator_ramfifo";
end fifo_generator_0fifo_generator_ramfifo;
architecture STRUCTURE of fifo_generator_0fifo_generator_ramfifo is
signal \n_0_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_10_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_1_gntv_or_sync_fifo.gcx.clkx\ : STD_LOGIC;
signal \n_8_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal \n_9_gntv_or_sync_fifo.gl0.rd\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_20_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_3_out : STD_LOGIC;
signal p_8_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_9_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal rst_d2 : STD_LOGIC;
signal rst_full_gen_i : STD_LOGIC;
signal tmp_ram_rd_en : STD_LOGIC;
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.fifo_generator_0clk_x_pntrs
port map (
D(2) => \n_8_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_9_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_10_gntv_or_sync_fifo.gl0.rd\,
I1(3 downto 0) => p_20_out(3 downto 0),
I2(3 downto 0) => rd_pntr_plus1(3 downto 0),
I3(2 downto 0) => p_8_out(2 downto 0),
I4(3 downto 0) => p_9_out(3 downto 0),
O1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O2 => \n_1_gntv_or_sync_fifo.gcx.clkx\,
O3(3 downto 0) => p_0_out(3 downto 0),
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
wr_clk => wr_clk,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.gl0.rd\: entity work.fifo_generator_0rd_logic
port map (
D(2) => \n_8_gntv_or_sync_fifo.gl0.rd\,
D(1) => \n_9_gntv_or_sync_fifo.gl0.rd\,
D(0) => \n_10_gntv_or_sync_fifo.gl0.rd\,
I1 => \n_0_gntv_or_sync_fifo.gcx.clkx\,
O1(3 downto 0) => p_20_out(3 downto 0),
Q(3 downto 0) => rd_pntr_plus1(3 downto 0),
empty => empty,
p_18_out => p_18_out,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
valid => valid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.fifo_generator_0wr_logic
port map (
E(0) => p_3_out,
I1 => \n_1_gntv_or_sync_fifo.gcx.clkx\,
O1(3 downto 0) => p_9_out(3 downto 0),
O3(3 downto 0) => p_0_out(3 downto 0),
Q(2 downto 0) => p_8_out(2 downto 0),
full => full,
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
\gntv_or_sync_fifo.mem\: entity work.fifo_generator_0memory
port map (
E(0) => p_3_out,
I1(3 downto 0) => p_9_out(3 downto 0),
O1(3 downto 0) => p_20_out(3 downto 0),
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
rd_clk => rd_clk,
rd_rst => rd_rst,
tmp_ram_rd_en => tmp_ram_rd_en,
wr_clk => wr_clk
);
rstblk: entity work.fifo_generator_0reset_blk_ramfifo
port map (
rst_d2 => rst_d2,
rst_full_gen_i => rst_full_gen_i,
wr_clk => wr_clk,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0fifo_generator_top is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
valid : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0fifo_generator_top : entity is "fifo_generator_top";
end fifo_generator_0fifo_generator_top;
architecture STRUCTURE of fifo_generator_0fifo_generator_top is
begin
\grf.rf\: entity work.fifo_generator_0fifo_generator_ramfifo
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0fifo_generator_v12_0_synth is
port (
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
empty : out STD_LOGIC;
valid : out STD_LOGIC;
full : out STD_LOGIC;
wr_en : in STD_LOGIC;
rd_clk : in STD_LOGIC;
wr_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_rst : in STD_LOGIC;
rd_en : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of fifo_generator_0fifo_generator_v12_0_synth : entity is "fifo_generator_v12_0_synth";
end fifo_generator_0fifo_generator_v12_0_synth;
architecture STRUCTURE of fifo_generator_0fifo_generator_v12_0_synth is
begin
\gconvfifo.rf\: entity work.fifo_generator_0fifo_generator_top
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \fifo_generator_0fifo_generator_v12_0__parameterized0\ is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 3 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 3 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 15 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 15 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "fifo_generator_v12_0";
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "BlankString";
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 13;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 12;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_VALID_LOW : integer;
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attribute C_AXI_BUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_AXI_RUSER_WIDTH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1;
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attribute C_HAS_AXIS_TUSER : integer;
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attribute C_AXIS_TSTRB_WIDTH : integer;
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attribute C_APPLICATION_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_APPLICATION_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_PRIM_FIFO_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is "512x36";
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attribute C_USE_ECC_WACH : integer;
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attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
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attribute C_ERROR_INJECTION_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
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attribute C_DIN_WIDTH_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 2;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 64;
attribute C_DIN_WIDTH_AXIS : integer;
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attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1024;
attribute C_WR_PNTR_WIDTH_WACH : integer;
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attribute C_WR_PNTR_WIDTH_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 4;
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attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 10;
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attribute C_HAS_DATA_COUNTS_WACH : integer;
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attribute C_HAS_DATA_COUNTS_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
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attribute C_HAS_DATA_COUNTS_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
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attribute C_HAS_PROG_FLAGS_AXIS : integer;
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attribute C_PROG_FULL_TYPE_WACH : integer;
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attribute C_PROG_FULL_TYPE_WDCH : integer;
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attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
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attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
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attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
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attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
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attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
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attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
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attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 1022;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \fifo_generator_0fifo_generator_v12_0__parameterized0\ : entity is 0;
end \fifo_generator_0fifo_generator_v12_0__parameterized0\;
architecture STRUCTURE of \fifo_generator_0fifo_generator_v12_0__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const1>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const1>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const1>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(10) <= \<const0>\;
axi_r_data_count(9) <= \<const0>\;
axi_r_data_count(8) <= \<const0>\;
axi_r_data_count(7) <= \<const0>\;
axi_r_data_count(6) <= \<const0>\;
axi_r_data_count(5) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const1>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(10) <= \<const0>\;
axi_r_rd_data_count(9) <= \<const0>\;
axi_r_rd_data_count(8) <= \<const0>\;
axi_r_rd_data_count(7) <= \<const0>\;
axi_r_rd_data_count(6) <= \<const0>\;
axi_r_rd_data_count(5) <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(10) <= \<const0>\;
axi_r_wr_data_count(9) <= \<const0>\;
axi_r_wr_data_count(8) <= \<const0>\;
axi_r_wr_data_count(7) <= \<const0>\;
axi_r_wr_data_count(6) <= \<const0>\;
axi_r_wr_data_count(5) <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(10) <= \<const0>\;
axi_w_data_count(9) <= \<const0>\;
axi_w_data_count(8) <= \<const0>\;
axi_w_data_count(7) <= \<const0>\;
axi_w_data_count(6) <= \<const0>\;
axi_w_data_count(5) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const1>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(10) <= \<const0>\;
axi_w_rd_data_count(9) <= \<const0>\;
axi_w_rd_data_count(8) <= \<const0>\;
axi_w_rd_data_count(7) <= \<const0>\;
axi_w_rd_data_count(6) <= \<const0>\;
axi_w_rd_data_count(5) <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(10) <= \<const0>\;
axi_w_wr_data_count(9) <= \<const0>\;
axi_w_wr_data_count(8) <= \<const0>\;
axi_w_wr_data_count(7) <= \<const0>\;
axi_w_wr_data_count(6) <= \<const0>\;
axi_w_wr_data_count(5) <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const1>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
m_axi_araddr(31) <= \<const0>\;
m_axi_araddr(30) <= \<const0>\;
m_axi_araddr(29) <= \<const0>\;
m_axi_araddr(28) <= \<const0>\;
m_axi_araddr(27) <= \<const0>\;
m_axi_araddr(26) <= \<const0>\;
m_axi_araddr(25) <= \<const0>\;
m_axi_araddr(24) <= \<const0>\;
m_axi_araddr(23) <= \<const0>\;
m_axi_araddr(22) <= \<const0>\;
m_axi_araddr(21) <= \<const0>\;
m_axi_araddr(20) <= \<const0>\;
m_axi_araddr(19) <= \<const0>\;
m_axi_araddr(18) <= \<const0>\;
m_axi_araddr(17) <= \<const0>\;
m_axi_araddr(16) <= \<const0>\;
m_axi_araddr(15) <= \<const0>\;
m_axi_araddr(14) <= \<const0>\;
m_axi_araddr(13) <= \<const0>\;
m_axi_araddr(12) <= \<const0>\;
m_axi_araddr(11) <= \<const0>\;
m_axi_araddr(10) <= \<const0>\;
m_axi_araddr(9) <= \<const0>\;
m_axi_araddr(8) <= \<const0>\;
m_axi_araddr(7) <= \<const0>\;
m_axi_araddr(6) <= \<const0>\;
m_axi_araddr(5) <= \<const0>\;
m_axi_araddr(4) <= \<const0>\;
m_axi_araddr(3) <= \<const0>\;
m_axi_araddr(2) <= \<const0>\;
m_axi_araddr(1) <= \<const0>\;
m_axi_araddr(0) <= \<const0>\;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const0>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arprot(2) <= \<const0>\;
m_axi_arprot(1) <= \<const0>\;
m_axi_arprot(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const0>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_arvalid <= \<const0>\;
m_axi_awaddr(31) <= \<const0>\;
m_axi_awaddr(30) <= \<const0>\;
m_axi_awaddr(29) <= \<const0>\;
m_axi_awaddr(28) <= \<const0>\;
m_axi_awaddr(27) <= \<const0>\;
m_axi_awaddr(26) <= \<const0>\;
m_axi_awaddr(25) <= \<const0>\;
m_axi_awaddr(24) <= \<const0>\;
m_axi_awaddr(23) <= \<const0>\;
m_axi_awaddr(22) <= \<const0>\;
m_axi_awaddr(21) <= \<const0>\;
m_axi_awaddr(20) <= \<const0>\;
m_axi_awaddr(19) <= \<const0>\;
m_axi_awaddr(18) <= \<const0>\;
m_axi_awaddr(17) <= \<const0>\;
m_axi_awaddr(16) <= \<const0>\;
m_axi_awaddr(15) <= \<const0>\;
m_axi_awaddr(14) <= \<const0>\;
m_axi_awaddr(13) <= \<const0>\;
m_axi_awaddr(12) <= \<const0>\;
m_axi_awaddr(11) <= \<const0>\;
m_axi_awaddr(10) <= \<const0>\;
m_axi_awaddr(9) <= \<const0>\;
m_axi_awaddr(8) <= \<const0>\;
m_axi_awaddr(7) <= \<const0>\;
m_axi_awaddr(6) <= \<const0>\;
m_axi_awaddr(5) <= \<const0>\;
m_axi_awaddr(4) <= \<const0>\;
m_axi_awaddr(3) <= \<const0>\;
m_axi_awaddr(2) <= \<const0>\;
m_axi_awaddr(1) <= \<const0>\;
m_axi_awaddr(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const0>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awprot(2) <= \<const0>\;
m_axi_awprot(1) <= \<const0>\;
m_axi_awprot(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const0>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_awvalid <= \<const0>\;
m_axi_bready <= \<const0>\;
m_axi_rready <= \<const0>\;
m_axi_wdata(63) <= \<const0>\;
m_axi_wdata(62) <= \<const0>\;
m_axi_wdata(61) <= \<const0>\;
m_axi_wdata(60) <= \<const0>\;
m_axi_wdata(59) <= \<const0>\;
m_axi_wdata(58) <= \<const0>\;
m_axi_wdata(57) <= \<const0>\;
m_axi_wdata(56) <= \<const0>\;
m_axi_wdata(55) <= \<const0>\;
m_axi_wdata(54) <= \<const0>\;
m_axi_wdata(53) <= \<const0>\;
m_axi_wdata(52) <= \<const0>\;
m_axi_wdata(51) <= \<const0>\;
m_axi_wdata(50) <= \<const0>\;
m_axi_wdata(49) <= \<const0>\;
m_axi_wdata(48) <= \<const0>\;
m_axi_wdata(47) <= \<const0>\;
m_axi_wdata(46) <= \<const0>\;
m_axi_wdata(45) <= \<const0>\;
m_axi_wdata(44) <= \<const0>\;
m_axi_wdata(43) <= \<const0>\;
m_axi_wdata(42) <= \<const0>\;
m_axi_wdata(41) <= \<const0>\;
m_axi_wdata(40) <= \<const0>\;
m_axi_wdata(39) <= \<const0>\;
m_axi_wdata(38) <= \<const0>\;
m_axi_wdata(37) <= \<const0>\;
m_axi_wdata(36) <= \<const0>\;
m_axi_wdata(35) <= \<const0>\;
m_axi_wdata(34) <= \<const0>\;
m_axi_wdata(33) <= \<const0>\;
m_axi_wdata(32) <= \<const0>\;
m_axi_wdata(31) <= \<const0>\;
m_axi_wdata(30) <= \<const0>\;
m_axi_wdata(29) <= \<const0>\;
m_axi_wdata(28) <= \<const0>\;
m_axi_wdata(27) <= \<const0>\;
m_axi_wdata(26) <= \<const0>\;
m_axi_wdata(25) <= \<const0>\;
m_axi_wdata(24) <= \<const0>\;
m_axi_wdata(23) <= \<const0>\;
m_axi_wdata(22) <= \<const0>\;
m_axi_wdata(21) <= \<const0>\;
m_axi_wdata(20) <= \<const0>\;
m_axi_wdata(19) <= \<const0>\;
m_axi_wdata(18) <= \<const0>\;
m_axi_wdata(17) <= \<const0>\;
m_axi_wdata(16) <= \<const0>\;
m_axi_wdata(15) <= \<const0>\;
m_axi_wdata(14) <= \<const0>\;
m_axi_wdata(13) <= \<const0>\;
m_axi_wdata(12) <= \<const0>\;
m_axi_wdata(11) <= \<const0>\;
m_axi_wdata(10) <= \<const0>\;
m_axi_wdata(9) <= \<const0>\;
m_axi_wdata(8) <= \<const0>\;
m_axi_wdata(7) <= \<const0>\;
m_axi_wdata(6) <= \<const0>\;
m_axi_wdata(5) <= \<const0>\;
m_axi_wdata(4) <= \<const0>\;
m_axi_wdata(3) <= \<const0>\;
m_axi_wdata(2) <= \<const0>\;
m_axi_wdata(1) <= \<const0>\;
m_axi_wdata(0) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const0>\;
m_axi_wstrb(7) <= \<const0>\;
m_axi_wstrb(6) <= \<const0>\;
m_axi_wstrb(5) <= \<const0>\;
m_axi_wstrb(4) <= \<const0>\;
m_axi_wstrb(3) <= \<const0>\;
m_axi_wstrb(2) <= \<const0>\;
m_axi_wstrb(1) <= \<const0>\;
m_axi_wstrb(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \<const0>\;
m_axis_tdata(15) <= \<const0>\;
m_axis_tdata(14) <= \<const0>\;
m_axis_tdata(13) <= \<const0>\;
m_axis_tdata(12) <= \<const0>\;
m_axis_tdata(11) <= \<const0>\;
m_axis_tdata(10) <= \<const0>\;
m_axis_tdata(9) <= \<const0>\;
m_axis_tdata(8) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(1) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(1) <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_wready <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
inst_fifo_gen: entity work.fifo_generator_0fifo_generator_v12_0_synth
port map (
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
rd_clk => rd_clk,
rd_en => rd_en,
rd_rst => rd_rst,
valid => valid,
wr_clk => wr_clk,
wr_en => wr_en,
wr_rst => wr_rst
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity fifo_generator_0 is
port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 9 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 9 downto 0 );
full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of fifo_generator_0 : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of fifo_generator_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of fifo_generator_0 : entity is "fifo_generator_v12_0,Vivado 2014.1";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of fifo_generator_0 : entity is "fifo_generator_0,fifo_generator_v12_0,{}";
attribute core_generation_info : string;
attribute core_generation_info of fifo_generator_0 : entity is "fifo_generator_0,fifo_generator_v12_0,{x_ipProduct=Vivado 2014.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=12.0,x_ipCoreRevision=0,x_ipLanguage=VHDL,C_COMMON_CLOCK=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=4,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=10,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=10,C_ENABLE_RLOCS=0,C_FAMILY=zynq,C_FULL_FLAGS_RST_VAL=1,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=0,C_HAS_INT_CLK=0,C_HAS_MEMINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=1,C_HAS_SRST=0,C_HAS_UNDERFLOW=0,C_HAS_VALID=1,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=2,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=1,C_PRELOAD_REGS=0,C_PRIM_FIFO_TYPE=512x36,C_PROG_EMPTY_THRESH_ASSERT_VAL=2,C_PROG_EMPTY_THRESH_NEGATE_VAL=3,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=13,C_PROG_FULL_THRESH_NEGATE_VAL=12,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=4,C_RD_DEPTH=16,C_RD_FREQ=1,C_RD_PNTR_WIDTH=4,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=0,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=4,C_WR_DEPTH=16,C_WR_FREQ=1,C_WR_PNTR_WIDTH=4,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WIDTH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=16,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=2,C_AXIS_TKEEP_WIDTH=2,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=12,C_IMPLEMENTATION_TYPE_WDCH=11,C_IMPLEMENTATION_TYPE_WRCH=12,C_IMPLEMENTATION_TYPE_RACH=12,C_IMPLEMENTATION_TYPE_RDCH=11,C_IMPLEMENTATION_TYPE_AXIS=11,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_ERROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=32,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10,C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
end fifo_generator_0;
architecture STRUCTURE of fifo_generator_0 is
signal NLW_U0_almost_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_almost_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_aw_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_b_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_r_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_w_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axis_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_arvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_awvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_bready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_rready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axi_wvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_m_axis_tvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_overflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_empty_UNCONNECTED : STD_LOGIC;
signal NLW_U0_prog_full_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rd_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axis_tready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_underflow_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_ack_UNCONNECTED : STD_LOGIC;
signal NLW_U0_wr_rst_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_axi_ar_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_ar_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_aw_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_b_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
signal NLW_U0_axi_r_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_r_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axi_w_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_axis_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_araddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_arprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awaddr_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_awprot_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_U0_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axi_wstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_U0_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
signal NLW_U0_m_axis_tdest_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_m_axis_tkeep_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axis_tstrb_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_m_axis_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_rd_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_U0_wr_data_count_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of U0 : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of U0 : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of U0 : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of U0 : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of U0 : label is 16;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of U0 : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of U0 : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of U0 : label is 2;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of U0 : label is 2;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of U0 : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of U0 : label is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of U0 : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of U0 : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of U0 : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of U0 : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of U0 : label is 64;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 1;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of U0 : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of U0 : label is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of U0 : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of U0 : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of U0 : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of U0 : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of U0 : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of U0 : label is 10;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of U0 : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of U0 : label is 32;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of U0 : label is 32;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of U0 : label is 64;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of U0 : label is 2;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of U0 : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of U0 : label is 10;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of U0 : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of U0 : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of U0 : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of U0 : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of U0 : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of U0 : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of U0 : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of U0 : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of U0 : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of U0 : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of U0 : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of U0 : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of U0 : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of U0 : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of U0 : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of U0 : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of U0 : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of U0 : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of U0 : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of U0 : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of U0 : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of U0 : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of U0 : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of U0 : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of U0 : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of U0 : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of U0 : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of U0 : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of U0 : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of U0 : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of U0 : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of U0 : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of U0 : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of U0 : label is 1;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of U0 : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of U0 : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of U0 : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of U0 : label is 2;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of U0 : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of U0 : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of U0 : label is 11;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of U0 : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of U0 : label is 11;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of U0 : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of U0 : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of U0 : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of U0 : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of U0 : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of U0 : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of U0 : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of U0 : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of U0 : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of U0 : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of U0 : label is "1kx18";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of U0 : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of U0 : label is "1kx36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of U0 : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of U0 : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of U0 : label is 1022;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of U0 : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of U0 : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of U0 : label is 13;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of U0 : label is 1023;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of U0 : label is 12;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of U0 : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of U0 : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of U0 : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of U0 : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of U0 : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of U0 : label is 16;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of U0 : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of U0 : label is 4;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of U0 : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of U0 : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of U0 : label is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of U0 : label is 2;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of U0 : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of U0 : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of U0 : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of U0 : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of U0 : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of U0 : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of U0 : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of U0 : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of U0 : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of U0 : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of U0 : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of U0 : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of U0 : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of U0 : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of U0 : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of U0 : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of U0 : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of U0 : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of U0 : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of U0 : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of U0 : label is 4;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of U0 : label is 16;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of U0 : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of U0 : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of U0 : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of U0 : label is 1024;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of U0 : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of U0 : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of U0 : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of U0 : label is 10;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of U0 : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of U0 : label is 1;
begin
U0: entity work.\fifo_generator_0fifo_generator_v12_0__parameterized0\
port map (
almost_empty => NLW_U0_almost_empty_UNCONNECTED,
almost_full => NLW_U0_almost_full_UNCONNECTED,
axi_ar_data_count(4 downto 0) => NLW_U0_axi_ar_data_count_UNCONNECTED(4 downto 0),
axi_ar_dbiterr => NLW_U0_axi_ar_dbiterr_UNCONNECTED,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => NLW_U0_axi_ar_overflow_UNCONNECTED,
axi_ar_prog_empty => NLW_U0_axi_ar_prog_empty_UNCONNECTED,
axi_ar_prog_empty_thresh(3) => '0',
axi_ar_prog_empty_thresh(2) => '0',
axi_ar_prog_empty_thresh(1) => '0',
axi_ar_prog_empty_thresh(0) => '0',
axi_ar_prog_full => NLW_U0_axi_ar_prog_full_UNCONNECTED,
axi_ar_prog_full_thresh(3) => '0',
axi_ar_prog_full_thresh(2) => '0',
axi_ar_prog_full_thresh(1) => '0',
axi_ar_prog_full_thresh(0) => '0',
axi_ar_rd_data_count(4 downto 0) => NLW_U0_axi_ar_rd_data_count_UNCONNECTED(4 downto 0),
axi_ar_sbiterr => NLW_U0_axi_ar_sbiterr_UNCONNECTED,
axi_ar_underflow => NLW_U0_axi_ar_underflow_UNCONNECTED,
axi_ar_wr_data_count(4 downto 0) => NLW_U0_axi_ar_wr_data_count_UNCONNECTED(4 downto 0),
axi_aw_data_count(4 downto 0) => NLW_U0_axi_aw_data_count_UNCONNECTED(4 downto 0),
axi_aw_dbiterr => NLW_U0_axi_aw_dbiterr_UNCONNECTED,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => NLW_U0_axi_aw_overflow_UNCONNECTED,
axi_aw_prog_empty => NLW_U0_axi_aw_prog_empty_UNCONNECTED,
axi_aw_prog_empty_thresh(3) => '0',
axi_aw_prog_empty_thresh(2) => '0',
axi_aw_prog_empty_thresh(1) => '0',
axi_aw_prog_empty_thresh(0) => '0',
axi_aw_prog_full => NLW_U0_axi_aw_prog_full_UNCONNECTED,
axi_aw_prog_full_thresh(3) => '0',
axi_aw_prog_full_thresh(2) => '0',
axi_aw_prog_full_thresh(1) => '0',
axi_aw_prog_full_thresh(0) => '0',
axi_aw_rd_data_count(4 downto 0) => NLW_U0_axi_aw_rd_data_count_UNCONNECTED(4 downto 0),
axi_aw_sbiterr => NLW_U0_axi_aw_sbiterr_UNCONNECTED,
axi_aw_underflow => NLW_U0_axi_aw_underflow_UNCONNECTED,
axi_aw_wr_data_count(4 downto 0) => NLW_U0_axi_aw_wr_data_count_UNCONNECTED(4 downto 0),
axi_b_data_count(4 downto 0) => NLW_U0_axi_b_data_count_UNCONNECTED(4 downto 0),
axi_b_dbiterr => NLW_U0_axi_b_dbiterr_UNCONNECTED,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => NLW_U0_axi_b_overflow_UNCONNECTED,
axi_b_prog_empty => NLW_U0_axi_b_prog_empty_UNCONNECTED,
axi_b_prog_empty_thresh(3) => '0',
axi_b_prog_empty_thresh(2) => '0',
axi_b_prog_empty_thresh(1) => '0',
axi_b_prog_empty_thresh(0) => '0',
axi_b_prog_full => NLW_U0_axi_b_prog_full_UNCONNECTED,
axi_b_prog_full_thresh(3) => '0',
axi_b_prog_full_thresh(2) => '0',
axi_b_prog_full_thresh(1) => '0',
axi_b_prog_full_thresh(0) => '0',
axi_b_rd_data_count(4 downto 0) => NLW_U0_axi_b_rd_data_count_UNCONNECTED(4 downto 0),
axi_b_sbiterr => NLW_U0_axi_b_sbiterr_UNCONNECTED,
axi_b_underflow => NLW_U0_axi_b_underflow_UNCONNECTED,
axi_b_wr_data_count(4 downto 0) => NLW_U0_axi_b_wr_data_count_UNCONNECTED(4 downto 0),
axi_r_data_count(10 downto 0) => NLW_U0_axi_r_data_count_UNCONNECTED(10 downto 0),
axi_r_dbiterr => NLW_U0_axi_r_dbiterr_UNCONNECTED,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => NLW_U0_axi_r_overflow_UNCONNECTED,
axi_r_prog_empty => NLW_U0_axi_r_prog_empty_UNCONNECTED,
axi_r_prog_empty_thresh(9) => '0',
axi_r_prog_empty_thresh(8) => '0',
axi_r_prog_empty_thresh(7) => '0',
axi_r_prog_empty_thresh(6) => '0',
axi_r_prog_empty_thresh(5) => '0',
axi_r_prog_empty_thresh(4) => '0',
axi_r_prog_empty_thresh(3) => '0',
axi_r_prog_empty_thresh(2) => '0',
axi_r_prog_empty_thresh(1) => '0',
axi_r_prog_empty_thresh(0) => '0',
axi_r_prog_full => NLW_U0_axi_r_prog_full_UNCONNECTED,
axi_r_prog_full_thresh(9) => '0',
axi_r_prog_full_thresh(8) => '0',
axi_r_prog_full_thresh(7) => '0',
axi_r_prog_full_thresh(6) => '0',
axi_r_prog_full_thresh(5) => '0',
axi_r_prog_full_thresh(4) => '0',
axi_r_prog_full_thresh(3) => '0',
axi_r_prog_full_thresh(2) => '0',
axi_r_prog_full_thresh(1) => '0',
axi_r_prog_full_thresh(0) => '0',
axi_r_rd_data_count(10 downto 0) => NLW_U0_axi_r_rd_data_count_UNCONNECTED(10 downto 0),
axi_r_sbiterr => NLW_U0_axi_r_sbiterr_UNCONNECTED,
axi_r_underflow => NLW_U0_axi_r_underflow_UNCONNECTED,
axi_r_wr_data_count(10 downto 0) => NLW_U0_axi_r_wr_data_count_UNCONNECTED(10 downto 0),
axi_w_data_count(10 downto 0) => NLW_U0_axi_w_data_count_UNCONNECTED(10 downto 0),
axi_w_dbiterr => NLW_U0_axi_w_dbiterr_UNCONNECTED,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => NLW_U0_axi_w_overflow_UNCONNECTED,
axi_w_prog_empty => NLW_U0_axi_w_prog_empty_UNCONNECTED,
axi_w_prog_empty_thresh(9) => '0',
axi_w_prog_empty_thresh(8) => '0',
axi_w_prog_empty_thresh(7) => '0',
axi_w_prog_empty_thresh(6) => '0',
axi_w_prog_empty_thresh(5) => '0',
axi_w_prog_empty_thresh(4) => '0',
axi_w_prog_empty_thresh(3) => '0',
axi_w_prog_empty_thresh(2) => '0',
axi_w_prog_empty_thresh(1) => '0',
axi_w_prog_empty_thresh(0) => '0',
axi_w_prog_full => NLW_U0_axi_w_prog_full_UNCONNECTED,
axi_w_prog_full_thresh(9) => '0',
axi_w_prog_full_thresh(8) => '0',
axi_w_prog_full_thresh(7) => '0',
axi_w_prog_full_thresh(6) => '0',
axi_w_prog_full_thresh(5) => '0',
axi_w_prog_full_thresh(4) => '0',
axi_w_prog_full_thresh(3) => '0',
axi_w_prog_full_thresh(2) => '0',
axi_w_prog_full_thresh(1) => '0',
axi_w_prog_full_thresh(0) => '0',
axi_w_rd_data_count(10 downto 0) => NLW_U0_axi_w_rd_data_count_UNCONNECTED(10 downto 0),
axi_w_sbiterr => NLW_U0_axi_w_sbiterr_UNCONNECTED,
axi_w_underflow => NLW_U0_axi_w_underflow_UNCONNECTED,
axi_w_wr_data_count(10 downto 0) => NLW_U0_axi_w_wr_data_count_UNCONNECTED(10 downto 0),
axis_data_count(10 downto 0) => NLW_U0_axis_data_count_UNCONNECTED(10 downto 0),
axis_dbiterr => NLW_U0_axis_dbiterr_UNCONNECTED,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => NLW_U0_axis_overflow_UNCONNECTED,
axis_prog_empty => NLW_U0_axis_prog_empty_UNCONNECTED,
axis_prog_empty_thresh(9) => '0',
axis_prog_empty_thresh(8) => '0',
axis_prog_empty_thresh(7) => '0',
axis_prog_empty_thresh(6) => '0',
axis_prog_empty_thresh(5) => '0',
axis_prog_empty_thresh(4) => '0',
axis_prog_empty_thresh(3) => '0',
axis_prog_empty_thresh(2) => '0',
axis_prog_empty_thresh(1) => '0',
axis_prog_empty_thresh(0) => '0',
axis_prog_full => NLW_U0_axis_prog_full_UNCONNECTED,
axis_prog_full_thresh(9) => '0',
axis_prog_full_thresh(8) => '0',
axis_prog_full_thresh(7) => '0',
axis_prog_full_thresh(6) => '0',
axis_prog_full_thresh(5) => '0',
axis_prog_full_thresh(4) => '0',
axis_prog_full_thresh(3) => '0',
axis_prog_full_thresh(2) => '0',
axis_prog_full_thresh(1) => '0',
axis_prog_full_thresh(0) => '0',
axis_rd_data_count(10 downto 0) => NLW_U0_axis_rd_data_count_UNCONNECTED(10 downto 0),
axis_sbiterr => NLW_U0_axis_sbiterr_UNCONNECTED,
axis_underflow => NLW_U0_axis_underflow_UNCONNECTED,
axis_wr_data_count(10 downto 0) => NLW_U0_axis_wr_data_count_UNCONNECTED(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(3 downto 0) => NLW_U0_data_count_UNCONNECTED(3 downto 0),
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
din(9 downto 0) => din(9 downto 0),
dout(9 downto 0) => dout(9 downto 0),
empty => empty,
full => full,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => '0',
m_aclk_en => '0',
m_axi_araddr(31 downto 0) => NLW_U0_m_axi_araddr_UNCONNECTED(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_U0_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_U0_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(0) => NLW_U0_m_axi_arid_UNCONNECTED(0),
m_axi_arlen(7 downto 0) => NLW_U0_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_U0_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => NLW_U0_m_axi_arprot_UNCONNECTED(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_U0_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => '0',
m_axi_arregion(3 downto 0) => NLW_U0_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_U0_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_U0_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => NLW_U0_m_axi_arvalid_UNCONNECTED,
m_axi_awaddr(31 downto 0) => NLW_U0_m_axi_awaddr_UNCONNECTED(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_U0_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_U0_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(0) => NLW_U0_m_axi_awid_UNCONNECTED(0),
m_axi_awlen(7 downto 0) => NLW_U0_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_U0_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => NLW_U0_m_axi_awprot_UNCONNECTED(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_U0_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => '0',
m_axi_awregion(3 downto 0) => NLW_U0_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_U0_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_U0_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => NLW_U0_m_axi_awvalid_UNCONNECTED,
m_axi_bid(0) => '0',
m_axi_bready => NLW_U0_m_axi_bready_UNCONNECTED,
m_axi_bresp(1) => '0',
m_axi_bresp(0) => '0',
m_axi_buser(0) => '0',
m_axi_bvalid => '0',
m_axi_rdata(63) => '0',
m_axi_rdata(62) => '0',
m_axi_rdata(61) => '0',
m_axi_rdata(60) => '0',
m_axi_rdata(59) => '0',
m_axi_rdata(58) => '0',
m_axi_rdata(57) => '0',
m_axi_rdata(56) => '0',
m_axi_rdata(55) => '0',
m_axi_rdata(54) => '0',
m_axi_rdata(53) => '0',
m_axi_rdata(52) => '0',
m_axi_rdata(51) => '0',
m_axi_rdata(50) => '0',
m_axi_rdata(49) => '0',
m_axi_rdata(48) => '0',
m_axi_rdata(47) => '0',
m_axi_rdata(46) => '0',
m_axi_rdata(45) => '0',
m_axi_rdata(44) => '0',
m_axi_rdata(43) => '0',
m_axi_rdata(42) => '0',
m_axi_rdata(41) => '0',
m_axi_rdata(40) => '0',
m_axi_rdata(39) => '0',
m_axi_rdata(38) => '0',
m_axi_rdata(37) => '0',
m_axi_rdata(36) => '0',
m_axi_rdata(35) => '0',
m_axi_rdata(34) => '0',
m_axi_rdata(33) => '0',
m_axi_rdata(32) => '0',
m_axi_rdata(31) => '0',
m_axi_rdata(30) => '0',
m_axi_rdata(29) => '0',
m_axi_rdata(28) => '0',
m_axi_rdata(27) => '0',
m_axi_rdata(26) => '0',
m_axi_rdata(25) => '0',
m_axi_rdata(24) => '0',
m_axi_rdata(23) => '0',
m_axi_rdata(22) => '0',
m_axi_rdata(21) => '0',
m_axi_rdata(20) => '0',
m_axi_rdata(19) => '0',
m_axi_rdata(18) => '0',
m_axi_rdata(17) => '0',
m_axi_rdata(16) => '0',
m_axi_rdata(15) => '0',
m_axi_rdata(14) => '0',
m_axi_rdata(13) => '0',
m_axi_rdata(12) => '0',
m_axi_rdata(11) => '0',
m_axi_rdata(10) => '0',
m_axi_rdata(9) => '0',
m_axi_rdata(8) => '0',
m_axi_rdata(7) => '0',
m_axi_rdata(6) => '0',
m_axi_rdata(5) => '0',
m_axi_rdata(4) => '0',
m_axi_rdata(3) => '0',
m_axi_rdata(2) => '0',
m_axi_rdata(1) => '0',
m_axi_rdata(0) => '0',
m_axi_rid(0) => '0',
m_axi_rlast => '0',
m_axi_rready => NLW_U0_m_axi_rready_UNCONNECTED,
m_axi_rresp(1) => '0',
m_axi_rresp(0) => '0',
m_axi_ruser(0) => '0',
m_axi_rvalid => '0',
m_axi_wdata(63 downto 0) => NLW_U0_m_axi_wdata_UNCONNECTED(63 downto 0),
m_axi_wid(0) => NLW_U0_m_axi_wid_UNCONNECTED(0),
m_axi_wlast => NLW_U0_m_axi_wlast_UNCONNECTED,
m_axi_wready => '0',
m_axi_wstrb(7 downto 0) => NLW_U0_m_axi_wstrb_UNCONNECTED(7 downto 0),
m_axi_wuser(0) => NLW_U0_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => NLW_U0_m_axi_wvalid_UNCONNECTED,
m_axis_tdata(15 downto 0) => NLW_U0_m_axis_tdata_UNCONNECTED(15 downto 0),
m_axis_tdest(0) => NLW_U0_m_axis_tdest_UNCONNECTED(0),
m_axis_tid(0) => NLW_U0_m_axis_tid_UNCONNECTED(0),
m_axis_tkeep(1 downto 0) => NLW_U0_m_axis_tkeep_UNCONNECTED(1 downto 0),
m_axis_tlast => NLW_U0_m_axis_tlast_UNCONNECTED,
m_axis_tready => '0',
m_axis_tstrb(1 downto 0) => NLW_U0_m_axis_tstrb_UNCONNECTED(1 downto 0),
m_axis_tuser(3 downto 0) => NLW_U0_m_axis_tuser_UNCONNECTED(3 downto 0),
m_axis_tvalid => NLW_U0_m_axis_tvalid_UNCONNECTED,
overflow => NLW_U0_overflow_UNCONNECTED,
prog_empty => NLW_U0_prog_empty_UNCONNECTED,
prog_empty_thresh(3) => '0',
prog_empty_thresh(2) => '0',
prog_empty_thresh(1) => '0',
prog_empty_thresh(0) => '0',
prog_empty_thresh_assert(3) => '0',
prog_empty_thresh_assert(2) => '0',
prog_empty_thresh_assert(1) => '0',
prog_empty_thresh_assert(0) => '0',
prog_empty_thresh_negate(3) => '0',
prog_empty_thresh_negate(2) => '0',
prog_empty_thresh_negate(1) => '0',
prog_empty_thresh_negate(0) => '0',
prog_full => NLW_U0_prog_full_UNCONNECTED,
prog_full_thresh(3) => '0',
prog_full_thresh(2) => '0',
prog_full_thresh(1) => '0',
prog_full_thresh(0) => '0',
prog_full_thresh_assert(3) => '0',
prog_full_thresh_assert(2) => '0',
prog_full_thresh_assert(1) => '0',
prog_full_thresh_assert(0) => '0',
prog_full_thresh_negate(3) => '0',
prog_full_thresh_negate(2) => '0',
prog_full_thresh_negate(1) => '0',
prog_full_thresh_negate(0) => '0',
rd_clk => rd_clk,
rd_data_count(3 downto 0) => NLW_U0_rd_data_count_UNCONNECTED(3 downto 0),
rd_en => rd_en,
rd_rst => rd_rst,
rd_rst_busy => NLW_U0_rd_rst_busy_UNCONNECTED,
rst => '0',
s_aclk => '0',
s_aclk_en => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arcache(3) => '0',
s_axi_arcache(2) => '0',
s_axi_arcache(1) => '0',
s_axi_arcache(0) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arlock(0) => '0',
s_axi_arprot(2) => '0',
s_axi_arprot(1) => '0',
s_axi_arprot(0) => '0',
s_axi_arqos(3) => '0',
s_axi_arqos(2) => '0',
s_axi_arqos(1) => '0',
s_axi_arqos(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arregion(3) => '0',
s_axi_arregion(2) => '0',
s_axi_arregion(1) => '0',
s_axi_arregion(0) => '0',
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_aruser(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awcache(3) => '0',
s_axi_awcache(2) => '0',
s_axi_awcache(1) => '0',
s_axi_awcache(0) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awlock(0) => '0',
s_axi_awprot(2) => '0',
s_axi_awprot(1) => '0',
s_axi_awprot(0) => '0',
s_axi_awqos(3) => '0',
s_axi_awqos(2) => '0',
s_axi_awqos(1) => '0',
s_axi_awqos(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awregion(3) => '0',
s_axi_awregion(2) => '0',
s_axi_awregion(1) => '0',
s_axi_awregion(0) => '0',
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awuser(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(0) => NLW_U0_s_axi_bid_UNCONNECTED(0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_buser(0) => NLW_U0_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_rdata(63 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(63 downto 0),
s_axi_rid(0) => NLW_U0_s_axi_rid_UNCONNECTED(0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_ruser(0) => NLW_U0_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wid(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(7) => '0',
s_axi_wstrb(6) => '0',
s_axi_wstrb(5) => '0',
s_axi_wstrb(4) => '0',
s_axi_wstrb(3) => '0',
s_axi_wstrb(2) => '0',
s_axi_wstrb(1) => '0',
s_axi_wstrb(0) => '0',
s_axi_wuser(0) => '0',
s_axi_wvalid => '0',
s_axis_tdata(15) => '0',
s_axis_tdata(14) => '0',
s_axis_tdata(13) => '0',
s_axis_tdata(12) => '0',
s_axis_tdata(11) => '0',
s_axis_tdata(10) => '0',
s_axis_tdata(9) => '0',
s_axis_tdata(8) => '0',
s_axis_tdata(7) => '0',
s_axis_tdata(6) => '0',
s_axis_tdata(5) => '0',
s_axis_tdata(4) => '0',
s_axis_tdata(3) => '0',
s_axis_tdata(2) => '0',
s_axis_tdata(1) => '0',
s_axis_tdata(0) => '0',
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(1) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => NLW_U0_s_axis_tready_UNCONNECTED,
s_axis_tstrb(1) => '0',
s_axis_tstrb(0) => '0',
s_axis_tuser(3) => '0',
s_axis_tuser(2) => '0',
s_axis_tuser(1) => '0',
s_axis_tuser(0) => '0',
s_axis_tvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
srst => '0',
underflow => NLW_U0_underflow_UNCONNECTED,
valid => valid,
wr_ack => NLW_U0_wr_ack_UNCONNECTED,
wr_clk => wr_clk,
wr_data_count(3 downto 0) => NLW_U0_wr_data_count_UNCONNECTED(3 downto 0),
wr_en => wr_en,
wr_rst => wr_rst,
wr_rst_busy => NLW_U0_wr_rst_busy_UNCONNECTED
);
end STRUCTURE;
|
-- Design:
-- Arithmetic Logic unit for the Freon core.
--
-- Authors:
-- Pietro Lorefice <pietro.lorefice@gmail.com>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity alu is
generic (
XLEN : integer := 32 -- # data bits
);
port (
opsel : in std_logic_vector(2 downto 0);
ctrl : in std_logic;
op1, op2 : in std_logic_vector(XLEN-1 downto 0);
res : out std_logic_vector(XLEN-1 downto 0)
);
end entity ; -- alu
architecture beh of alu is
signal op1_s, op2_s : signed(XLEN-1 downto 0) := (others => '0');
signal op1_u, op2_u : unsigned(XLEN-1 downto 0) := (others => '0');
begin
-- Connecting internal signals
op1_s <= signed(op1);
op2_s <= signed(op2);
op1_u <= unsigned(op1);
op2_u <= unsigned(op2);
-- ALU arithmetic operators
process (op1_s, op2_s, op1_u, op2_u, op1, op2, opsel, ctrl)
begin
res <= (others => '0');
case opsel(2 downto 0) is
when "000" => -- ADD/SUB
if (ctrl = '0') then
res <= std_logic_vector(op1_s + op2_s);
else
res <= std_logic_vector(op1_s - op2_s);
end if;
when "010" => -- SLT
if (op1_s < op2_s) then
res(0) <= '1';
end if;
when "011" => -- SLTU
if (op1_u < op2_u) then
res(0) <= '1';
end if;
when "100" => -- XOR
res <= op1 xor op2;
when "110" => -- OR
res <= op1 or op2;
when "111" => -- AND
res <= op1 and op2;
when others => -- irrelevant, not managed by ALU
res <= (others => '0');
end case;
end process;
end architecture ; -- beh
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library ieee_proposed;
use ieee_proposed.fixed_pkg.all;
use ieee_proposed.fixed_float_types.ALL;
use std.textio.all;
use ieee.std_logic_textio.all; -- if you're saving this type of signal
use IEEE.numeric_std.all;
entity top_synth is
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
neuron_model_eventport_out_spike : out STD_LOGIC;
neuron_model_param_voltage_v0 : in sfixed (2 downto -22);
neuron_model_param_none_a : in sfixed (18 downto -13);
neuron_model_param_none_b : in sfixed (18 downto -13);
neuron_model_param_none_c : in sfixed (18 downto -13);
neuron_model_param_none_d : in sfixed (18 downto -13);
neuron_model_param_voltage_thresh : in sfixed (2 downto -22);
neuron_model_param_time_MSEC : in sfixed (6 downto -18);
neuron_model_param_voltage_MVOLT : in sfixed (2 downto -22);
neuron_model_param_time_inv_MSEC_inv : in sfixed (18 downto -6);
neuron_model_param_voltage_inv_MVOLT_inv : in sfixed (22 downto -2);
neuron_model_param_none_div_voltage_b_div_MVOLT : in sfixed (18 downto -13);
neuron_model_exposure_voltage_v : out sfixed (2 downto -22);
neuron_model_exposure_none_U : out sfixed (18 downto -13);
neuron_model_stateCURRENT_voltage_v : out sfixed (2 downto -22);
neuron_model_stateRESTORE_voltage_v : in sfixed (2 downto -22);
neuron_model_stateCURRENT_none_U : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_U : in sfixed (18 downto -13);
neuron_model_param_time_i1_delay : in sfixed (6 downto -18);
neuron_model_param_time_i1_duration : in sfixed (6 downto -18);
neuron_model_param_none_i1_amplitude : in sfixed (18 downto -13);
neuron_model_exposure_none_i1_I : out sfixed (18 downto -13);
neuron_model_stateCURRENT_none_i1_I : out sfixed (18 downto -13);
neuron_model_stateRESTORE_none_i1_I : in sfixed (18 downto -13);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end top_synth;
architecture top of top_synth is
signal step_once_complete_int : STD_LOGIC;
signal seven_steps_done : STD_LOGIC;
signal step_once_go_int : STD_LOGIC := '0';
signal seven_steps_done_shot_done : STD_LOGIC;
signal seven_steps_done_shot : STD_LOGIC;
signal seven_steps_done_shot2 : STD_LOGIC;
signal COUNT : unsigned(2 downto 0) := "110";
signal seven_steps_done_next : STD_LOGIC;
signal COUNT_next : unsigned(2 downto 0) := "110";
signal step_once_go_int_next : STD_LOGIC := '0';
signal neuron_model_eventport_out_spike_int : STD_LOGIC;
signal neuron_model_eventport_out_spike_int2 : STD_LOGIC;
signal neuron_model_eventport_out_spike_int3 : STD_LOGIC;
component neuron_model
Port ( clk : in STD_LOGIC; --SYSTEM CLOCK, THIS ITSELF DOES NOT SIGNIFY TIME STEPS - AKA A SINGLE TIMESTEP MAY TAKE MANY CLOCK CYCLES
init_model: in STD_LOGIC; --SYNCHRONOUS RESET
step_once_go : in STD_LOGIC; --signals to the neuron from the core that a time step is to be simulated
step_once_complete : out STD_LOGIC; --signals to the core that a time step has finished
eventport_in_spike_aggregate : in STD_LOGIC_VECTOR(511 downto 0);
eventport_out_spike : out STD_LOGIC;
param_voltage_v0 : in sfixed (2 downto -22);
param_none_a : in sfixed (18 downto -13);
param_none_b : in sfixed (18 downto -13);
param_none_c : in sfixed (18 downto -13);
param_none_d : in sfixed (18 downto -13);
param_voltage_thresh : in sfixed (2 downto -22);
param_time_MSEC : in sfixed (6 downto -18);
param_voltage_MVOLT : in sfixed (2 downto -22);
param_time_inv_MSEC_inv : in sfixed (18 downto -6);
param_voltage_inv_MVOLT_inv : in sfixed (22 downto -2);
param_none_div_voltage_b_div_MVOLT : in sfixed (18 downto -13);
exposure_voltage_v : out sfixed (2 downto -22);
exposure_none_U : out sfixed (18 downto -13);
statevariable_voltage_v_out : out sfixed (2 downto -22);
statevariable_voltage_v_in : in sfixed (2 downto -22);
statevariable_none_U_out : out sfixed (18 downto -13);
statevariable_none_U_in : in sfixed (18 downto -13);
param_time_i1_delay : in sfixed (6 downto -18);
param_time_i1_duration : in sfixed (6 downto -18);
param_none_i1_amplitude : in sfixed (18 downto -13);
exposure_none_i1_I : out sfixed (18 downto -13);
statevariable_none_i1_I_out : out sfixed (18 downto -13);
statevariable_none_i1_I_in : in sfixed (18 downto -13);
sysparam_time_timestep : sfixed (-6 downto -22);
sysparam_time_simtime : sfixed (6 downto -22)
);
end component;
signal neuron_model_eventport_out_spike_out : STD_LOGIC := '0';
signal neuron_model_statevariable_voltage_v_out_int : sfixed (2 downto -22);signal neuron_model_statevariable_voltage_v_in_int : sfixed (2 downto -22);signal neuron_model_statevariable_none_U_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_U_in_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_i1_I_out_int : sfixed (18 downto -13);signal neuron_model_statevariable_none_i1_I_in_int : sfixed (18 downto -13);
begin
neuron_model_uut : neuron_model
port map ( clk => clk,
init_model=> init_model,
step_once_go => step_once_go_int,
step_once_complete => step_once_complete_int,
eventport_in_spike_aggregate => eventport_in_spike_aggregate,
eventport_out_spike => neuron_model_eventport_out_spike_int ,
param_voltage_v0 => neuron_model_param_voltage_v0 ,
param_none_a => neuron_model_param_none_a ,
param_none_b => neuron_model_param_none_b ,
param_none_c => neuron_model_param_none_c ,
param_none_d => neuron_model_param_none_d ,
param_voltage_thresh => neuron_model_param_voltage_thresh ,
param_time_MSEC => neuron_model_param_time_MSEC ,
param_voltage_MVOLT => neuron_model_param_voltage_MVOLT ,
param_time_inv_MSEC_inv => neuron_model_param_time_inv_MSEC_inv ,
param_voltage_inv_MVOLT_inv => neuron_model_param_voltage_inv_MVOLT_inv ,
param_none_div_voltage_b_div_MVOLT => neuron_model_param_none_div_voltage_b_div_MVOLT ,
statevariable_voltage_v_out => neuron_model_statevariable_voltage_v_out_int,
statevariable_voltage_v_in => neuron_model_statevariable_voltage_v_in_int,
statevariable_none_U_out => neuron_model_statevariable_none_U_out_int,
statevariable_none_U_in => neuron_model_statevariable_none_U_in_int,
param_time_i1_delay => neuron_model_param_time_i1_delay ,
param_time_i1_duration => neuron_model_param_time_i1_duration ,
param_none_i1_amplitude => neuron_model_param_none_i1_amplitude ,
statevariable_none_i1_I_out => neuron_model_statevariable_none_i1_I_out_int,
statevariable_none_i1_I_in => neuron_model_statevariable_none_i1_I_in_int,
sysparam_time_timestep => sysparam_time_timestep,
sysparam_time_simtime => sysparam_time_simtime
);
count_proc_comb:process(init_model,step_once_complete_int,COUNT,step_once_go)
begin
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
if (init_model='1') then
seven_steps_done_next <= '0';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
if step_once_complete_int = '1' then
if (COUNT = "110") then
seven_steps_done_next <= '1';
COUNT_next <= "110";
step_once_go_int_next <= '0';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT + 1;
step_once_go_int_next <= '1';
end if;
elsif step_once_go = '1' then
seven_steps_done_next <= '0';
COUNT_next <= "000";
step_once_go_int_next <= '1';
else
seven_steps_done_next <= '0';
COUNT_next <= COUNT;
step_once_go_int_next <= '0';
end if;
end if;
end process count_proc_comb;
count_proc_syn:process(clk)
begin
if rising_edge(clk) then
if init_model = '1' then
COUNT <= "110";
seven_steps_done <= '1';
step_once_go_int <= '0';
else
COUNT <= COUNT_next;
seven_steps_done <= seven_steps_done_next;
step_once_go_int <= step_once_go_int_next;
end if; end if;
end process count_proc_syn;
shot_process:process(clk)
begin
if rising_edge(clk) then
if (init_model='1') then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '1';
else
if seven_steps_done = '1' and seven_steps_done_shot_done = '0' then
seven_steps_done_shot <= '1';
seven_steps_done_shot_done <= '1';
elsif seven_steps_done_shot = '1' then
seven_steps_done_shot <= '0';
elsif seven_steps_done = '0' then
seven_steps_done_shot <= '0';
seven_steps_done_shot_done <= '0';
end if;
end if;
end if;
end process shot_process;
store_state: process (clk)
begin
if rising_edge(clk) then
neuron_model_eventport_out_spike_int2 <= neuron_model_eventport_out_spike_int; neuron_model_eventport_out_spike_int3 <= neuron_model_eventport_out_spike_int2; seven_steps_done_shot2 <= seven_steps_done_shot; if (init_model='1') then
neuron_model_statevariable_voltage_v_in_int <= neuron_model_stateRESTORE_voltage_v;
neuron_model_statevariable_none_U_in_int <= neuron_model_stateRESTORE_none_U;
neuron_model_statevariable_none_i1_I_in_int <= neuron_model_stateRESTORE_none_i1_I;
neuron_model_eventport_out_spike_out <= '0';
elsif (seven_steps_done_shot='1') then
neuron_model_eventport_out_spike_out <= neuron_model_eventport_out_spike_int3 ;
neuron_model_statevariable_voltage_v_in_int <= neuron_model_statevariable_voltage_v_out_int;
neuron_model_statevariable_none_U_in_int <= neuron_model_statevariable_none_U_out_int;
neuron_model_statevariable_none_i1_I_in_int <= neuron_model_statevariable_none_i1_I_out_int;
else
neuron_model_eventport_out_spike_out <= '0';
end if;
end if;
end process store_state;
neuron_model_stateCURRENT_voltage_v <= neuron_model_statevariable_voltage_v_in_int;
neuron_model_stateCURRENT_none_U <= neuron_model_statevariable_none_U_in_int;
neuron_model_stateCURRENT_none_i1_I <= neuron_model_statevariable_none_i1_I_in_int;
neuron_model_eventport_out_spike <= neuron_model_eventport_out_spike_out;
step_once_complete <= seven_steps_done_shot2;
end top; |
-- ============================================================
-- File Name: data_path.vhd
-- ============================================================
-- ************************************************************
-- THIS IS A AUTO-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 2.0 BUILD. GENERATED ON 2016-11-22
-- ************************************************************
LIBRARY IEEE;
USE ieee.numeric_std.all;
USE ieee.std_logic_1164.all;
ENTITY data_path IS
GENERIC(
data_width: INTEGER := 16);
PORT(
clk: IN STD_LOGIC := '0';
reset: IN STD_LOGIC := '0';
T: IN STD_LOGIC_VECTOR( 0 TO 36 ) := (others => '0');
a: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
d: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
b: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
c: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_0: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_1: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
output_2: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0'));
END ENTITY;
ARCHITECTURE data OF data_path is
SIGNAL clr_REG10, ena_REG10, clk_REG10: STD_LOGIC := '0';
SIGNAL ena_REG8, clk_REG9, clr_REG9, ena_REG9, clr_REG8: STD_LOGIC := '0';
SIGNAL outp_REG9, inp_REG10, outp_REG10, inp_REG9: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL inp_REG7, outp_REG7, inp_REG8, outp_REG8, outp_REG6: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clk_REG7, clr_REG7, ena_REG7, clk_REG8, ena_REG6: STD_LOGIC := '0';
SIGNAL outp_REG4, inp_REG5, outp_REG5, inp_REG6, inp_REG4: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clr_REG5, ena_REG5, clk_REG6, clr_REG6, clk_REG5: STD_LOGIC := '0';
SIGNAL inp_REG2, outp_REG2, inp_REG3, outp_REG3, outp_REG1: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL ena_REG3, clk_REG4, clr_REG4, ena_REG4, clr_REG3: STD_LOGIC := '0';
SIGNAL outp_ALU3, inp_REG0, outp_REG0, inp_REG1, in_2_ALU3: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clk_REG2, clr_REG2, ena_REG2, clk_REG3, ena_REG1: STD_LOGIC := '0';
SIGNAL in_1_ALU2, in_2_ALU2, outp_ALU2, in_1_ALU3, outp_ALU1: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL clr_REG0, ena_REG0, clk_REG1, clr_REG1, clk_REG0: STD_LOGIC := '0';
SIGNAL in_2_ALU0, outp_ALU0, in_1_ALU1, in_2_ALU1, in_1_ALU0: STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
SIGNAL sel_ALU1, sel_ALU2, sel_ALU3, sel_ALU0: STD_LOGIC_VECTOR( 0 TO 2 ) := (others => '0');
COMPONENT ALU IS
GENERIC(
data_width: INTEGER := 16);
PORT(
in_1: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
in_2: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
sel: IN STD_LOGIC_VECTOR( 0 TO 2 ) := (others => '0'));
END COMPONENT;
COMPONENT REG IS
GENERIC(
data_width: INTEGER := 16);
PORT(
inp: IN STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
outp: OUT STD_LOGIC_VECTOR( 0 TO data_width - 1) := (others => '0');
clk: IN STD_LOGIC := '0';
clr: IN STD_LOGIC := '0';
ena: IN STD_LOGIC := '0');
END COMPONENT;
begin
ALU0: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU0,
in_2 => in_2_ALU0,
outp => outp_ALU0,
sel => sel_ALU0
);
ALU1: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU1,
in_2 => in_2_ALU1,
outp => outp_ALU1,
sel => sel_ALU1
);
ALU2: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU2,
in_2 => in_2_ALU2,
outp => outp_ALU2,
sel => sel_ALU2
);
ALU3: ALU
GENERIC MAP(
data_width => data_width
)
PORT MAP(
in_1 => in_1_ALU3,
in_2 => in_2_ALU3,
outp => outp_ALU3,
sel => sel_ALU3
);
REG0: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG0,
outp => outp_REG0,
clk => clk_REG0,
clr => clr_REG0,
ena => ena_REG0
);
REG1: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG1,
outp => outp_REG1,
clk => clk_REG1,
clr => clr_REG1,
ena => ena_REG1
);
REG2: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG2,
outp => outp_REG2,
clk => clk_REG2,
clr => clr_REG2,
ena => ena_REG2
);
REG3: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG3,
outp => outp_REG3,
clk => clk_REG3,
clr => clr_REG3,
ena => ena_REG3
);
REG4: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG4,
outp => outp_REG4,
clk => clk_REG4,
clr => clr_REG4,
ena => ena_REG4
);
REG5: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG5,
outp => outp_REG5,
clk => clk_REG5,
clr => clr_REG5,
ena => ena_REG5
);
REG6: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG6,
outp => outp_REG6,
clk => clk_REG6,
clr => clr_REG6,
ena => ena_REG6
);
REG7: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG7,
outp => outp_REG7,
clk => clk_REG7,
clr => clr_REG7,
ena => ena_REG7
);
REG8: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG8,
outp => outp_REG8,
clk => clk_REG8,
clr => clr_REG8,
ena => ena_REG8
);
REG9: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG9,
outp => outp_REG9,
clk => clk_REG9,
clr => clr_REG9,
ena => ena_REG9
);
REG10: REG
GENERIC MAP(
data_width => data_width
)
PORT MAP(
inp => inp_REG10,
outp => outp_REG10,
clk => clk_REG10,
clr => clr_REG10,
ena => ena_REG10
);
sel_ALU0 <= T ( 0 TO 2 );
sel_ALU1 <= T ( 3 TO 5 );
sel_ALU2 <= T ( 6 TO 8 );
sel_ALU3 <= T ( 9 TO 11 );
clk_REG0 <= clk;
clr_REG0 <= reset;
ena_REG0 <= T(12);
clk_REG1 <= clk;
clr_REG1 <= reset;
ena_REG1 <= T(13);
clk_REG2 <= clk;
clr_REG2 <= reset;
ena_REG2 <= T(14);
clk_REG3 <= clk;
clr_REG3 <= reset;
ena_REG3 <= T(15);
clk_REG4 <= clk;
clr_REG4 <= reset;
ena_REG4 <= T(16);
clk_REG5 <= clk;
clr_REG5 <= reset;
ena_REG5 <= T(17);
clk_REG6 <= clk;
clr_REG6 <= reset;
ena_REG6 <= T(18);
clk_REG7 <= clk;
clr_REG7 <= reset;
ena_REG7 <= T(19);
clk_REG8 <= clk;
clr_REG8 <= reset;
ena_REG8 <= T(20);
clk_REG9 <= clk;
clr_REG9 <= reset;
ena_REG9 <= T(21);
clk_REG10 <= clk;
clr_REG10 <= reset;
ena_REG10 <= T(22);
in_1_ALU0 <= outp_REG8
when (T ( 23 TO 24 ) = "00") else outp_REG9
when (T ( 23 TO 24 ) = "01") else outp_REG2
when (T ( 23 TO 24 ) = "10") else outp_REG6;
in_2_ALU0 <= outp_REG0
when (T ( 25 TO 26 ) = "00") else outp_REG6
when (T ( 25 TO 26 ) = "01") else outp_REG7;
in_1_ALU1 <= outp_REG1
when (T ( 27 TO 28 ) = "00") else outp_REG10
when (T ( 27 TO 28 ) = "01") else outp_REG7;
in_2_ALU1 <= outp_REG9
when (T ( 29 TO 30 ) = "00") else outp_REG3
when (T ( 29 TO 30 ) = "01") else outp_REG6;
in_1_ALU2 <= outp_REG2
when (T ( 31 TO 31 ) = "0") else outp_REG5;
in_2_ALU2 <= outp_REG0
when (T ( 32 TO 32 ) = "0") else outp_REG4;
in_1_ALU3 <= outp_REG1
when (T ( 33 TO 33 ) = "0") else outp_REG7;
in_2_ALU3 <= outp_REG3
when (T ( 34 TO 34 ) = "0") else outp_REG6;
inp_REG0 <= a;
inp_REG1 <= d;
inp_REG2 <= b;
inp_REG3 <= c;
inp_REG4 <= outp_ALU1
when (T ( 35 TO 35 ) = "0") else outp_ALU2;
inp_REG5 <= outp_ALU3;
inp_REG6 <= outp_ALU0;
inp_REG7 <= outp_ALU1;
inp_REG8 <= outp_ALU0;
inp_REG9 <= outp_ALU0
when (T ( 36 TO 36 ) = "0") else outp_ALU1;
inp_REG10 <= outp_ALU2;
output_0 <= outp_REG5;
output_1 <= outp_REG8;
output_2 <= outp_REG4;
END ARCHITECTURE; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3007.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03007pkg is
constant X : real;
end c02s06b00x00p07n01i03007pkg;
package body c02s06b00x00p07n01i03007pkg is
constant X: integer := 1; --Failure_here
end c02s06b00x00p07n01i03007pkg;
ENTITY c02s06b00x00p07n01i03007ent IS
END c02s06b00x00p07n01i03007ent;
ARCHITECTURE c02s06b00x00p07n01i03007arch OF c02s06b00x00p07n01i03007ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03007 - The subtype of constant in the full declaratio does not conform to that given in the deferred constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03007arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3007.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03007pkg is
constant X : real;
end c02s06b00x00p07n01i03007pkg;
package body c02s06b00x00p07n01i03007pkg is
constant X: integer := 1; --Failure_here
end c02s06b00x00p07n01i03007pkg;
ENTITY c02s06b00x00p07n01i03007ent IS
END c02s06b00x00p07n01i03007ent;
ARCHITECTURE c02s06b00x00p07n01i03007arch OF c02s06b00x00p07n01i03007ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03007 - The subtype of constant in the full declaratio does not conform to that given in the deferred constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03007arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3007.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03007pkg is
constant X : real;
end c02s06b00x00p07n01i03007pkg;
package body c02s06b00x00p07n01i03007pkg is
constant X: integer := 1; --Failure_here
end c02s06b00x00p07n01i03007pkg;
ENTITY c02s06b00x00p07n01i03007ent IS
END c02s06b00x00p07n01i03007ent;
ARCHITECTURE c02s06b00x00p07n01i03007arch OF c02s06b00x00p07n01i03007ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03007 - The subtype of constant in the full declaratio does not conform to that given in the deferred constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03007arch;
|
library verilog;
use verilog.vl_types.all;
entity inicial is
generic(
\Fechado\ : vl_logic_vector(0 to 1) := (Hi0, Hi0);
Abrindo : vl_logic_vector(0 to 1) := (Hi0, Hi1);
\Aberto\ : vl_logic_vector(0 to 1) := (Hi1, Hi0);
Fechando : vl_logic_vector(0 to 1) := (Hi1, Hi1)
);
port(
botao : in vl_logic;
aberto : in vl_logic;
fechado : in vl_logic;
motor : in vl_logic;
sentido : in vl_logic;
ledVerde : out vl_logic;
ledVermelho : out vl_logic;
display : out vl_logic_vector(6 downto 0);
clock : in vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of \Fechado\ : constant is 1;
attribute mti_svvh_generic_type of Abrindo : constant is 1;
attribute mti_svvh_generic_type of \Aberto\ : constant is 1;
attribute mti_svvh_generic_type of Fechando : constant is 1;
end inicial;
|
-------------------------------------------------------------------------------
-- Title : Fixed sin-cos DDS
-- Project :
-------------------------------------------------------------------------------
-- File : fixed_dds.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Fixed frequency phase and quadrature DDS for use in tuned DDCs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity fixed_dds is
generic (
g_number_of_points : natural := 148;
g_output_width : natural := 24;
g_dither : boolean := false;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram"
);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0)
);
end entity fixed_dds;
-------------------------------------------------------------------------------
architecture str of fixed_dds is
constant c_bus_size : natural := f_log2_size(g_number_of_points);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0);
component generic_simple_dpram is
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(c_bus_size-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_bus_size-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component generic_simple_dpram;
component lut_sweep is
generic (
g_bus_size : natural;
g_first_address : natural;
g_last_address : natural;
g_sweep_mode : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(c_bus_size-1 downto 0));
end component lut_sweep;
begin -- architecture str
cmp_sin_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_sin_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => sin_o
);
cmp_cos_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_cos_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => cos_o
);
cmp_sweep : lut_sweep
generic map (
g_bus_size => c_bus_size,
g_first_address => 0,
g_last_address => g_number_of_points-1,
g_sweep_mode => "sawtooth")
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
ce_i => ce_i,
address_o => cur_address);
end architecture str;
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- Title : Fixed sin-cos DDS
-- Project :
-------------------------------------------------------------------------------
-- File : fixed_dds.vhd
-- Author : aylons <aylons@LNLS190>
-- Company :
-- Created : 2014-03-07
-- Last update: 2014-03-07
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Fixed frequency phase and quadrature DDS for use in tuned DDCs.
-------------------------------------------------------------------------------
-- Copyright (c) 2014
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2014-03-07 1.0 aylons Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.genram_pkg.all;
-------------------------------------------------------------------------------
entity fixed_dds is
generic (
g_number_of_points : natural := 148;
g_output_width : natural := 24;
g_dither : boolean := false;
g_sin_file : string := "./dds_sin.ram";
g_cos_file : string := "./dds_cos.ram"
);
port (
clk_i : in std_logic;
ce_i : in std_logic;
rst_n_i : in std_logic;
sin_o : out std_logic_vector(g_output_width-1 downto 0);
cos_o : out std_logic_vector(g_output_width-1 downto 0)
);
end entity fixed_dds;
-------------------------------------------------------------------------------
architecture str of fixed_dds is
constant c_bus_size : natural := f_log2_size(g_number_of_points);
signal cur_address : std_logic_vector(c_bus_size-1 downto 0);
component generic_simple_dpram is
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8 -1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic;
aa_i : in std_logic_vector(c_bus_size-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
ab_i : in std_logic_vector(c_bus_size-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component generic_simple_dpram;
component lut_sweep is
generic (
g_bus_size : natural;
g_first_address : natural;
g_last_address : natural;
g_sweep_mode : string);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
ce_i : in std_logic;
address_o : out std_logic_vector(c_bus_size-1 downto 0));
end component lut_sweep;
begin -- architecture str
cmp_sin_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_sin_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => sin_o
);
cmp_cos_lut : generic_simple_dpram
generic map (
g_data_width => g_output_width,
g_size => g_number_of_points,
g_with_byte_enable => false,
g_addr_conflict_resolution => "dont_care",
g_init_file => g_cos_file,
g_dual_clock => false
)
port map (
rst_n_i => rst_n_i,
clka_i => clk_i,
bwea_i => (others => '0'),
wea_i => '0',
aa_i => cur_address,
da_i => (others => '0'),
clkb_i => clk_i,
ab_i => cur_address,
qb_o => cos_o
);
cmp_sweep : lut_sweep
generic map (
g_bus_size => c_bus_size,
g_first_address => 0,
g_last_address => g_number_of_points-1,
g_sweep_mode => "sawtooth")
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
ce_i => ce_i,
address_o => cur_address);
end architecture str;
-------------------------------------------------------------------------------
|
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aSQo7oq231bpjIvzykQ=
`protect end_protected
|
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