content stringlengths 1 1.04M ⌀ |
|---|
-- file: clk_wiz_v3_6_tb.vhd
--
-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- Clocking wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- clocking wizard. Input clocks are toggled, which cause the clocking
-- network to lock and the counters to increment.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity clk_wiz_v3_6_tb is
end clk_wiz_v3_6_tb;
architecture test of clk_wiz_v3_6_tb is
-- Clock to Q delay of 100 ps
constant TCQ : time := 100 ps;
-- timescale is 1ps
constant ONE_NS : time := 1 ns;
-- how many cycles to run
constant COUNT_PHASE : integer := 1024 + 1;
-- we'll be using the period in many locations
constant PER1 : time := 8.000 ns;
-- Declare the input clock signals
signal CLK_IN1 : std_logic := '1';
-- The high bit of the sampling counter
signal COUNT : std_logic;
-- Status and control signals
signal RESET : std_logic := '0';
signal LOCKED : std_logic;
signal COUNTER_RESET : std_logic := '0';
signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0');
-- signal defined to stop mti simulation without severity failure in the report
signal end_of_sim : std_logic := '0';
signal CLK_OUT : std_logic_vector(1 downto 1);
--Freq Check using the M & D values setting and actual Frequency generated
signal period1 : time := 0 ps;
constant ref_period1_clkin1 : time := (8.000*1*3.125/8.000)*1000 ps;
signal prev_rise1 : time := 0 ps;
component clk_wiz_v3_6_exdes
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Reset that only drives logic in example design
COUNTER_RESET : in std_logic;
CLK_OUT : out std_logic_vector(1 downto 1) ;
-- High bits of counters driven by clocks
COUNT : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
begin
-- Input clock generation
--------------------------------------
process begin
CLK_IN1 <= not CLK_IN1; wait for (PER1/2);
end process;
-- Test sequence
process
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
procedure simfreqprint (period : time; clk_num : integer) is
variable outputline : LINE;
variable str1 : string(1 to 16);
variable str2 : integer;
variable str3 : string(1 to 2);
variable str4 : integer;
variable str5 : string(1 to 4);
begin
str1 := "Freq of CLK_OUT(";
str2 := clk_num;
str3 := ") ";
str4 := 1000000 ps/period ;
str5 := " MHz" ;
write(outputline, str1 );
write(outputline, str2);
write(outputline, str3);
write(outputline, str4);
write(outputline, str5);
writeline(output, outputline);
end simfreqprint;
begin
report "Timing checks are not valid" severity note;
RESET <= '1';
wait for (PER1*6);
RESET <= '0';
wait until LOCKED = '1';
wait for (PER1*20);
COUNTER_RESET <= '1';
wait for (PER1*19.5);
COUNTER_RESET <= '0';
wait for (PER1*1);
report "Timing checks are valid" severity note;
wait for (PER1*COUNT_PHASE);
simfreqprint(period1, 1);
assert (((period1 - ref_period1_clkin1) >= -100 ps) and ((period1 - ref_period1_clkin1) <= 100 ps)) report "ERROR: Freq of CLK_OUT(1) is not correct" severity note;
simtimeprint;
end_of_sim <= '1';
wait for 1 ps;
report "Simulation Stopped." severity failure;
wait;
end process;
process (CLK_IN1)
procedure simtimeprint is
variable outline : line;
begin
write(outline, string'("## SYSTEM_CYCLE_COUNTER "));
write(outline, NOW/PER1);
write(outline, string'(" ns"));
writeline(output,outline);
end simtimeprint;
begin
if (CLK_IN1'event and CLK_IN1='1') then
timeout_counter <= timeout_counter + '1';
if (timeout_counter = "10000000000000") then
if (LOCKED /= '1') then
simtimeprint;
report "NO LOCK signal" severity failure;
end if;
end if;
end if;
end process;
-- Instantiation of the example design containing the clock
-- network and sampling counters
-----------------------------------------------------------
dut : clk_wiz_v3_6_exdes
port map
(-- Clock in ports
CLK_IN1 => CLK_IN1,
-- Reset for logic in example design
COUNTER_RESET => COUNTER_RESET,
CLK_OUT => CLK_OUT,
-- High bits of the counters
COUNT => COUNT,
-- Status and control signals
RESET => RESET,
LOCKED => LOCKED);
-- Freq Check
process(CLK_OUT(1))
begin
if (CLK_OUT(1)'event and CLK_OUT(1) = '1') then
if (prev_rise1 /= 0 ps) then
period1 <= NOW - prev_rise1;
end if;
prev_rise1 <= NOW;
end if;
end process;
end test;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity cpuPipeline is
port
(
clk : in std_logic;
reset : in std_logic;
four : INTEGER;
writeToRegisterFile : in std_logic := '0';
writeToMemoryFile : in std_logic := '0'
);
end cpuPipeline;
architecture cpuPipeline_arch of cpuPipeline is
component instructionFetchStage IS
port(
clk : in std_logic;
muxInput0 : in std_logic_vector(31 downto 0);
selectInputs : in std_logic;
four : in INTEGER;
structuralStall : IN STD_LOGIC;
pcStall : IN STD_LOGIC;
selectOutput : out std_logic_vector(31 downto 0);
instructionMemoryOutput : out std_logic_vector(31 downto 0)
);
end component;
component controller is
port(clk : in std_logic;
opcode : in std_logic_vector(5 downto 0);
funct : in std_logic_vector(5 downto 0);
branch: in std_logic;
oldBranch: in std_logic;
ALU1src : out STD_LOGIC;
ALU2src : out STD_LOGIC;
MemRead : out STD_LOGIC;
MemWrite : out STD_LOGIC;
RegWrite : out STD_LOGIC;
MemToReg : out STD_LOGIC;
RType : out std_logic;
JType : out std_logic;
Shift : out std_logic;
structuralStall : out std_logic;
ALUOp : out STD_LOGIC_VECTOR(4 downto 0)
);
end component;
component register_file is
PORT(
clock: IN STD_LOGIC;
rs: IN STD_LOGIC_VECTOR (4 downto 0);
rt: IN STD_LOGIC_VECTOR (4 downto 0);
write_enable: IN STD_LOGIC;
rd: IN STD_LOGIC_VECTOR (4 downto 0);
rd_data: IN STD_LOGIC_VECTOR (31 downto 0);
writeToText : IN STD_LOGIC := '0';
ra_data: OUT STD_LOGIC_VECTOR (31 downto 0);
rb_data: OUT STD_LOGIC_VECTOR (31 downto 0)
);
end component;
component signextender is
PORT (
immediate_in: IN STD_LOGIC_VECTOR (15 DOWNTO 0);
immediate_out: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component mux is
port(
input0 : in std_logic_vector(31 downto 0);
input1 : in std_logic_vector(31 downto 0);
selectInput : in std_logic;
selectOutput : out std_logic_vector(31 downto 0)
);
end component;
component alu is
Port ( input_a : in STD_LOGIC_VECTOR (31 downto 0);
input_b : in STD_LOGIC_VECTOR (31 downto 0);
SEL : in STD_LOGIC_VECTOR (4 downto 0);
out_alu : out STD_LOGIC_VECTOR(31 downto 0));
end component;
component zero is
port (input_a : in std_logic_vector (31 downto 0);
input_b : in std_logic_vector (31 downto 0);
optype : in std_logic_vector (4 downto 0);
result: out std_logic
);
end component;
--MEMORY OBJ FOR MEM STAGE
COMPONENT memory IS
GENERIC(
ram_size : INTEGER := 8192;
mem_delay : time := 10 ns;
clock_period : time := 1 ns
);
PORT (
clock: IN STD_LOGIC;
writedata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
address: IN INTEGER RANGE 0 TO ram_size-1;
memwrite: IN STD_LOGIC := '0';
memread: IN STD_LOGIC := '0';
writeToText : IN STD_LOGIC := '0';
readdata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: OUT STD_LOGIC
);
END COMPONENT;
--MEM STAGE
component mem is
port (clk: in std_logic;
-- Control lines
ctrl_write : in std_logic;
ctrl_read: in std_logic;
ctrl_memtoreg_in: in std_logic;
ctrl_memtoreg_out: out std_logic;
ctrl_regwrite_in: in std_logic;
ctrl_regwrite_out: out std_logic;
ctrl_jal: in std_logic;
--Ports of stage
alu_in : in std_logic_vector (31 downto 0);
alu_out : out std_logic_vector (31 downto 0);
mem_data_in: in std_logic_vector (31 downto 0);
mem_data_out: out std_logic_vector (31 downto 0);
write_addr_in: in std_logic_vector (4 downto 0);
write_addr_out: out std_logic_vector (4 downto 0);
--Memory signals
writedata: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
address: OUT INTEGER RANGE 0 TO 32768 -1;
memwrite: OUT STD_LOGIC := '0';
memread: OUT STD_LOGIC := '0';
readdata: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
waitrequest: IN STD_LOGIC
);
end component;
component wb is
port (ctrl_memtoreg_in: in std_logic;
ctrl_regwrite_in: in std_logic;
ctrl_regwrite_out: out std_logic;
alu_in : in std_logic_vector (31 downto 0);
mem_in: in std_logic_vector (31 downto 0);
mux_out : out std_logic_vector (31 downto 0);
write_addr_in: in std_logic_vector (4 downto 0);
write_addr_out: out std_logic_vector (4 downto 0)
);
end component;
-- STALL SIGNALS
signal IDEXStructuralStall : std_logic;
signal EXMEMStructuralStall : std_logic;
signal structuralStall : std_logic;
signal pcStall : std_logic;
-- TEST SIGNALS
signal muxInput : STD_LOGIC_VECTOR(31 downto 0) := "00000000000000000000000000000000";
signal selectInput : std_logic := '1';
signal fourInt : INTEGER := 4;
-- PIPELINE IFID
--address goes to both IFID and IDEX
signal address : std_logic_vector(31 downto 0);
signal instruction : std_logic_vector(31 downto 0);
signal IFIDaddress : std_logic_vector(31 downto 0);
signal IFIDinstruction : std_logic_vector(31 downto 0);
--PIPELINE IDEX
signal IDEXaddress : std_logic_vector(31 downto 0);
signal IDEXra : std_logic_vector(31 downto 0);
signal IDEXrb : std_logic_vector(31 downto 0);
signal IDEXimmediate : std_logic_vector(31 downto 0);
signal IDEXrd : std_logic_vector (4 downto 0);
signal IDEXALU1srcO, IDEXALU2srcO, IDEXMemReadO, IDEXMeMWriteO, IDEXRegWriteO, IDEXMemToRegO: std_logic;
signal IDEXAluOp : std_logic_vector (4 downto 0);
-- SIGNALS FOR CONTROLLER
signal opcodeInput,functInput : std_logic_vector(5 downto 0);
signal ALU1srcO,ALU2srcO,MemReadO,MemWriteO,RegWriteO,MemToRegO,RType,Jtype,Shift: std_logic;
signal ALUOp : std_logic_vector(4 downto 0);
-- SIGNALS FOR REGISTERS
signal rs,rt,rd,WBrd : std_logic_vector (4 downto 0);
signal rd_data: std_logic_vector(31 downto 0);
signal write_enable : std_logic;
signal ra,rb : std_logic_vector(31 downto 0);
signal shamnt : std_logic_vector(4 downto 0);
signal immediate : std_logic_vector(15 downto 0);
signal immediate_out : std_logic_vector(31 downto 0);
-- SIGNALS FOR EXECUTE STAGE
signal muxOutput1 : std_logic_vector(31 downto 0);
signal muxOutput2 : std_logic_vector(31 downto 0);
signal aluOutput : std_logic_vector(31 downto 0);
signal zeroOutput : std_logic;
-- SIGNALS FOR EXMEM
signal EXMEMBranch : std_logic; -- need the zero variable
signal ctrl_jal : std_logic;
signal EXMEMaluOutput : std_logic_vector(31 downto 0);
signal EXMEMregisterOutput : std_logic_vector(31 downto 0);
signal EXMEMrd : std_logic_vector(4 downto 0);
signal EXMEMMemReadO, EXMEMMeMWriteO, EXMEMRegWriteO, EXMEMMemToRegO: std_logic;
-- MEM SIGNALS
signal MEMWBmemOutput : std_logic_vector(31 downto 0);
signal MEMWBaluOutput : std_logic_vector(31 downto 0);
signal MEMWBrd : std_logic_vector(4 downto 0);
signal memtoReg : std_logic;
signal regWrite : std_logic;
signal MEMwritedata : std_logic_vector(31 downto 0);
signal MEMaddress : INTEGER;
signal MEMmemwrite : STD_LOGIC;
signal MEMmemread : STD_LOGIC;
signal MEMreaddata : std_logic_vector(31 downto 0);
signal MEMwaitrequest : STD_LOGIC;
begin
IFS : instructionFetchStage
port map(
clk => clk,
muxInput0 => EXMEMaluOutput,
selectInputs => EXMEMBranch,
four => fourInt,
structuralStall => structuralStall,
pcStall => pcStall,
selectOutput => address,
instructionMemoryOutput => instruction
);
-- DECODE STAGE
CT : controller
port map(
clk => clk,
opcode => opcodeInput,
funct => functInput,
branch => zeroOutput,
oldBranch => EXMEMBranch,
ALU1src => ALU1srcO,
ALU2src => ALU2srcO,
MemRead => MemReadO,
MemWrite => MemWriteO,
RegWrite => RegWriteO,
MemToReg => MemToRegO,
structuralStall => IDEXStructuralStall,
ALUOp => ALUOp,
Shift => Shift,
RType => RType,
JType => JType
);
RegisterFile : register_file
port map (
clock => clk,
rs => rs,
rt => rt,
write_enable => write_enable,
rd => WBrd,
rd_data => rd_data,
writeToText => writeToRegisterFile,
ra_data => ra,
rb_data => rb
);
se : signextender
port map(
immediate_in => immediate,
immediate_out => immediate_out
);
-- EXECUTE STAGE
exMux1 : mux
port map (
input0 => IDEXra,
input1 => IDEXaddress,
selectInput => IDEXALU1srcO,
selectOutput => muxOutput1
);
exMux2 : mux
port map (
input0 => IDEXimmediate,
input1 => IDEXrb,
selectInput => IDEXALU2srcO,
selectOutput => muxOutput2
);
operator : alu
port map(
input_a => muxOutput1,
input_b => muxOutput2,
SEL => IDEXAluOp,
out_alu => aluOutput
);
zr : zero
port map (
input_a => IDEXra,
input_b => IDEXrb,
optype => IDEXAluOp,
result => zeroOutput
);
memStage : mem
port map (
clk =>clk,
-- Control lines
ctrl_write => EXMEMMemWriteO,
ctrl_read => EXMEMMemReadO,
ctrl_memtoreg_in => EXMEMMemToRegO,
ctrl_memtoreg_out => memtoReg,
ctrl_regwrite_in => EXMEMRegWriteO,
ctrl_regwrite_out => regWrite,
ctrl_jal => ctrl_jal,
--Ports of stage
alu_in => EXMEMaluOutput,
alu_out=> MEMWBaluOutput,
mem_data_in => EXMEMregisterOutput,
mem_data_out => MEMWBmemOutput,
write_addr_in => EXMEMrd,
write_addr_out => MEMWBrd,
--Memory signals
writedata => MEMwritedata,
address => MEMaddress,
memwrite => MEMmemwrite,
memread => MEMmemread,
readdata => MEMreaddata,
waitrequest => MEMwaitrequest
);
memMemory: memory
port map (
clock => clk,
writedata => MEMwritedata,
address => MEMaddress,
memwrite => MEMmemwrite,
memread => MEMmemread,
writeToText => writeToMemoryFile,
readdata => MEMreaddata,
waitrequest => MEMwaitrequest
);
wbStage: wb
port map (ctrl_memtoreg_in => memtoReg,
ctrl_regwrite_in => regWrite,
ctrl_regwrite_out => write_enable,
alu_in => MEMWBaluOutput,
mem_in => MEMWBmemOutput,
mux_out => rd_data,
write_addr_in => MEMWBrd,
write_addr_out => WBrd
);
process(EXMEMStructuralStall)
begin
if EXMEMStructuralStall = '1' then
pcStall <= '1';
else
pcStall <= '0';
end if;
end process;
process (clk)
begin
if (clk'event and clk = '1') then
--PIPELINED VALUE
--IFID
IFIDaddress <= address;
IFIDinstruction <= instruction;
-- IDEX
IDEXaddress <= IFIDaddress;
IDEXrb <= rb;
--FOR IMMEDIATE VALUES
if RType = '1' then
IDEXrd <= rd;
-- FOR JAL
elsif ALUOP = "11010" then
IDEXrd <= "11111";
else
IDEXrd <= rt;
end if;
--FOR SHIFT INSTRUCTIONS
if Shift = '1' then
IDEXra <= rb;
else
IDEXra <= ra;
end if;
--FOR JUMP INSTRUCTIONS
if JType = '1' then
IDEXimmediate <= "000000" & IFIDinstruction(25 downto 0);
else
IDEXimmediate <= immediate_out;
end if;
IDEXALU1srcO <= ALU1srcO;
IDEXALU2srcO <= ALU2srcO;
IDEXMemReadO <= MemReadO;
IDEXMeMWriteO <= MemWriteO;
IDEXRegWriteO <= RegWriteO;
IDEXMemToRegO <= MemToRegO;
IDEXAluOp <= ALUOp;
--EXMEM
EXMEMBranch <= zeroOutput;
EXMEMrd <= IDEXrd;
EXMEMMemReadO <= IDEXMemReadO;
EXMEMMeMWriteO <= IDEXMeMWriteO;
EXMEMRegWriteO <= IDEXRegWriteO;
EXMEMMemToRegO <= IDEXMemToRegO;
EXMEMaluOutput <= aluOutput;
EXMEMStructuralStall <= IDEXStructuralStall;
structuralStall <= EXMEMStructuralStall;
--FOR JAL
if IDEXAluOp = "11010" then
EXMEMregisterOutput <= IDEXaddress;
ctrl_jal <= '1';
else
EXMEMregisterOutput <= IDEXrb;
ctrl_jal <= '0';
end if;
end if ;
end process;
-- controller values
opcodeInput <= IFIDinstruction(31 downto 26);
functInput <= IFIDinstruction(5 downto 0);
-- register values
rs <= IFIDinstruction(25 downto 21);
rt <= IFIDinstruction(20 downto 16);
rd <= IFIDinstruction(15 downto 11);
shamnt <= IFIDinstruction(10 downto 6);
-- EXTENDED
immediate <= IFIDinstruction(15 downto 0);
-- MIGHT NEED TO PUT WRITE ENABLE HERE LATER
-- AND JUMP ADDRESS HERE
end cpuPipeline_arch; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY TRISTATE IS
PORT(EN,DIN:IN STD_LOGIC;
DOUT:OUT STD_LOGIC);
END ENTITY TRISTATE;
ARCHITECTURE ART OF TRISTATE IS
BEGIN
PROCESS(EN,DIN) IS
BEGIN
IF EN='1' THEN
DOUT<=DIN;
ELSE
DOUT<='Z';
END IF;
END PROCESS;
END ARCHITECTURE ART; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Dy8GuSLXgw4Kn/n9FZ0vppRtVveVQji65VfRiXW71BaVWetmn7KGLJDBsDsyWo4YuKKaDuZySmgj
mzNFHmBQ4A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZM2S9AZu7NUjeAfeZVButlYtXToDq6OdAYdMYZPu2Hco0L5uzqE1w6PVSNruBpCo5pXmFPKwMWzk
QslIZZpBJvk+Kt8YwZ8JiEriv4sda8yTXGKZpfH+8ol4HzjyTFKkVCAP673FaMTP/iGSQl5rUb84
jvnaPme8XPlLpOu8aGA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
SfYa1cMbzTWsh9AAaWhH/5SvZXWd9LzrDfk3mL5w7KWlgYspDRSSS62ZxplG9sz17Tw1f08YUuEe
xQ8CHcEFzmPZnazebh3WXbkc/aAhXXr0qVaAHmirpWBUrO4ifEsaeyFWH0qMGJFAXnMba03eT1BM
iq+SbtX09LYyoSk/mRU12QpQA7/kBCavWti/YbLQlHiEBplyhK8c0lk7AmTrQwjydAX4dv+aFnpe
6Tw3KiLzgQFswNlFxf8sS8Ko7YXHSIamBqu02COG4lFyHPti9euSzj+JCY9tyCZUMInJP6JS6fCl
Ykm2WZZdB+uXGHYPXZoBnQSWDnyjK7As6GinKA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
uA3zAb5aDYFygMzilWmjAIqzW00c2khRKEGHdxpGsRoX/E1FxJU+SL7BqD9w9yHhUZO59QUbuFed
Dcvl2yU7BZ5L4umHbLdAfwtaLGMZHrQ5AQlQqCdLld2+woai7FNm0CMlfkQSV0nxxAK0RpgjF9uL
q14cqVTln9u0mqJ6A9c=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gXY7Augo3g9P57bPy+Gcu411PlpVQlr1x5CQoPz7o8u2FKUQ9HZ+5es2mg5/5KdlkJ/0SK9OnCgf
gHmp3lNbWxUIXt1dDl1d+vQ9sXMu6B4/MaTMXnenT4rm27KgVlUB+diIcsFlg7Uh8A6Cu0w6Yvl0
IHzfH2uq420jze3KB+L6Tgw/pBmLCCF2BgJRQed2vrHUB+T0QU/Yv0Xfr9nzn9ky4eu0DC35Xvbo
8wac5j24iwNrec1VwZT4N7L1JWnxWZXG0QVG2eewOPjaK5lUzeY4kNr85UQZnLQTtrZflL8KLu0c
IAtQDV8gqiqwcVy0e4mgumtRR31iZa4KwIzIbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7120)
`protect data_block
R6w3tkyFHGrHJW4XyrgCTdGw+b6pdX+IDOGkktrA8gZ+yrNLE24Nd1uiYGAdBgRt2RfdGVEeP6ab
FsMQv05DxSJ9yQow5+sTc3WFQlw3Out+R3an09wF7CPA+A/A5jgP7Xjxp7w9p/EoQND2HCqS3fX7
Gf6p/K5HmBzX32L/O49ZHy+2dtfo2WgxYtHGMOU1tITE+Vvj3wyzSkWg2kuRxWkCzcS32p4VVrnl
APqIXM4f/nl1Z9pp8ldcfj1zwxvzEkp7Q/CLkeGirttlwM4pI1fm+zx66bXdnasUIHDc1v+ac8En
GwbB/on/P2EhswobCMoKt5vMGpXhbd37aKqlJS9ZwX5cVnwrtb7Fmz8jbqAnjpoS71LdprUbezez
ZW1u5Bz7PRbbzXjGlVG+XTOG6BEjBJN74T2CtmHR0aElItpy7CqYEA1FnaVRnACRC0kMtEneacC6
LwVyYvaPvmcKnw2m+cD0YDITLg7ZKyHDoWT1sDASOC4DhB9jJabPzCFj1CWNn/T9RYXss67ZlnmV
q8X/Sr0OgSs+d+FzKuIBuRNGWu+TQgG/ntoaeJ5Bq9lI6xC2P0RtFA8kjVwU+TlNHKURQGhhGQZN
EUK+zJwC03WGZglDjLn1yYqqMajggRAmdG601AuY2O8dH1eZ7gNxzNNnEa313UXxzx3z8yvCTevB
3bsK0NWhY9qL4zVNYARVj3Ey5xEvIAPW1/vuIJz8O2ynmfi5mqk4f43gYPYB+XNuriCyUmYxc2sD
4tEDrYKVpYUwohLkyGI5Z5nXAYZ7B227s+tCqGFnHwo+xsOYw8nvfZMnDQGJnw5o+BOhDlXPr4a5
oeUWKOf6Hb3hnVYYWIYk5wN46aJjmt2uBt4rexZXqJfM8zcL4v7IVTjgSF4AfVJhw8BNtVkOc/Ly
WmZOvatbzhIhcu/wl3n/ov9JIbdE3U5KUK53qxLz1bh5Zh85AbFEhUFhomZjh+lNn00kWgQiATlM
1cOnlN6cjlIe2a8iujrWVnDtdTvTOSStEHNNNl6h4gCF3udZMyQ3Q/wlWG71rKapqGIr3Zs+NKFc
jvRPsjKvbTJYvL70qxPUKNPNEDxpwTpLFerYAfTHLGBeQziPmgOEMFLIXSbRGK+tRk6PnDk6oiT6
Y3wFtCE0/HnfZ97GhbX+topY75O2wiESv3VTALDaokrEK2W4Z0496ryS2UuEK0G+365jc1tBiMUo
XY11QvEqpCiVJiKLknK/qwuAefxbfWqx2llFN4hU+JIB2S/fBvqt+i4Ja3OLGTToMFxtVnsHKnlx
S7KYLAUEjH1nM6b1Tpu5ZhHajvtllY64nI4db6xSOv+veYYC2z/Xy7Yesbz+F5GRJCTq1mKtIviF
VyVFvRTfolnPdpiBDdAMqUXa22PA3P6JKBSfX4KZsMJSZZjEB+ShO4qC+3MfudGbu7xDNYI05UGU
9HrsLiSpYACWpH5qj7Zb2JVc6ORA2v7jrEPYvsfAngaSs1Ga2VUkH5Vd4kYQV1RaZn0hFf1Vd9Ix
9nXEgNvBqP2K7AsDv8YhPs5BYOnPZlP+dEAxQ3UUzzg9UQ5m3LfeXQct4mEZdwKu13vTVSw93XZO
jJ8qJkl6zLooRxzzzpO5PYKW8wk01N7ECzOdZCP7JHfdv7WsOVsB7zmT6K7kF17nwaAqxUxqZFNz
8zOaptRh6ui+2u5C4SCFFynAQEV5f7jkppQ/fCXYywW7yTw5dk34U4UFF/yiSsri3bJsWLg1n61E
aXtbYVeUqZbCJiMAeU8y+K8H9M6S1TMZxTxxsNY1N7YLZN8j5NU1VulGUdXfG5lsNF7W3VcE2LqG
deML+3U9F8RhVfjwTepmd1JTV0ypkOQa4XVLMHmSMcAU8Zdf4JjUhniZIeMJYigk79wwVXSfsUsb
lvRIrVwEUBhbf+h2bzAV6WWnEpUkx5/WvETLMFoTNC1CYZD05obQJ6zPO/q18Y7nf7BPjrTeUXGg
ps5ia0evfLvd/47YWoDnWXVINeO/JKxIHBB6lxMYwQIOjOTVzEoRdUiplxEGzOtpnCVjItqyeW23
egzVA+OelVr4XsuFWw0tJA7hmBDdLyBi2UI1cCg8kg+8nPyLfdB98pkyVh8g95eywb9/YxbiYpKr
Q+wku1Ao9ncRz+PclZQbdAaE7fG5/Jn4dXekfKmgEBbRIcxAmO0PWsE8WPkz4O+TSRIZhID+di5Y
9UPQPVZ+u5sAUJkaTphk4yxtiOV/tBSfHdtf99RWkptOdndUtssz9RcIFiNu0groG/k4FM2fRPTg
aTEUm+ycwZ+5ehb1BtGFrqrZuy1/AiqgZebxQ1/gLGVtNm2yKrskMMwRTM/rAarKVbm5xPeovQ1m
Qk4xgqHbHxVBfFd+fnEStH7KjFA/H0YsIvK1+JB6YkPopzDv5G3hhehXauCQsmRUI8nGL7tKcVJ3
iaBUxNy210nOv91NlUDWwY93VnjhuX+4+B9TUy1PTiVV2k3dkTSipd9DxHRziUMhP1stUcejaciZ
4tgtWeLDCxIvr2OcsmM3DQXpBHPpMvhcwHrY7qeJam9U3zsVwqtaL6tGcZix2EIehsATGahPefVV
J3Zyl3ShviVKNBz9EMI2toTnLaiInkbLVfjc8ueCUUPF3cu5ExxUQ7NyHvwligPOYF4WsqXhZhDZ
7J9zN5z349ZtwqwTEDM7d4QZGOaa/ZkyUoFJOWMJBoZr8ETX4zO3ps9/qG5oYNFosTLpTDpQG1GW
hFzacPA8k6trFjXPY/e9QmwP9hmtwXZSteR9aVTgmlJB9Zl6gYBE9hFxdYGaqDbky//mhugxBO3o
otuw6KD6WU/5XP7BWpErKIeDCqZSkWYZoN/1dVNbyzwVo2jYgvFefR0BGmmxAunPJqv6oKyJ5TdA
eOD/NtKPwJnKqNx68jOWmNPIwai1pp7EqpwiKgbNjWQ/dLMhBlyBzFGHSYgMQYmIef+NxNnKdOZy
pOhM+iofJayXaRC23lMimQvNBZpntFItZsBjE3ISFW6kz5xvDUd8wSOqOEOmVswPI6KdIfjF8atM
0GUzYWytQIwqMErOHVpzOklqSDtW0GgizrKU8mxyoZBkmdA/HKV43WeqLGTJVqHNRaBL4Kl9Q8A8
jcvW9GT41u5fk5tleLMOKsDvmtcmfaoO5E986OyS7e+PDFFvAYbCG3MlJHWczqDegTQ1i676uOX5
bjyENLvqfKEUH3h2PfJVYG0Y70yjsaRwdTpn5Qi/Lmh2iZLsEV2S4i2AlSt1oqHuT5rIU1C87PPn
D2W7V3wuEiR3WwkGEggODx2wItpGuZjjAX08HEWNF9iJ79yGdzkMagQNhNoQ9/r7wJDaqwfziEQI
hzGJKeDOFhZXCkkxIYYU/ZX0yy/ig+p41cA5zsYMnhXZhcqIGuhTe4pYHCSZTNnixGNlH+BIgYSC
G3vyaXWGeJeij+fnNHE6O/deO9B3X1VSL9uAtyhmlGgr/pBuYPhB4OW1o4g193Wx+d19+m62nL+U
/lc3AQGbZ7lSC0i9BKuTDmKP/XRSTqrbUVyFBmJNfhpjIW4U+HmzJQqpL7Eh1SFlbOkXfQfXCsth
fx3cQUZGAudcfa0CE0v4zT6vcKr0BDk43VOF0ya+IohOTRyoB2BQl2kKB77T1pSf2ayEo3PVzkaI
eHfC8VFljHeCfSGXhuHtNhX+0HmvZN8yV3DUM5z2f0O8phGL1g94rJVpU4T8LFt12XgElLF3ju0Q
veBmr0LbAvKitCYXMD6iL0yGFkMxiCK59pbQY0XzKSbdH2fQJotg+wJ0kd1WUPBVy5jJnOYojrgP
Ch6QZviMKNhDe1TE0XDtAB2hCRXGHZuk5gMH4BqK/N1xEEJWseqpj3L+0rtE2MQpkWLPEXAyjMj/
SHN+Lj0gzIFa7nkAA3kpUXrY1lFOLhZyw0TBRHHzWsMAGMgHnmtp1X1DWR1DrEv/mtdCj6FH957S
GdGNznk7bFDkYQpgaxd+HBfMub/nzeQwzPpABcpMiTjMUDc05NMq3B/NUgpUBI0F3CEXQJDUJ3NT
sYENxN18aK8FWOf4gWyyeEtN/c9jh7W3x62VHYT+dm4E66AF/MpIiiviDg0/YxE6MJoLxzDyyEAb
93SGZSGQ1cvGdS7dD6aakIoz7uVVS/479SVBBMBUhJcZt7NM7bwR10S35cyN2g5tPkHxyQ0+zNqc
3Ip1yl/N9eWbhZsyg+xS84rtKJJngcPztxa3j+Jn4AkSZFF0XoGP2xxcb+4VtfhL9YlPbv37xFV5
c5NAH4Fz1RMfE/aNrCFU0VAylNue03tQElqRjLP4LzpZHE6wN+M6CI4GrFit32oEzZMTyrBz8FGb
zDJQrx7sAHZojwh9oypP7ntsak6z9vAoCgmO7cOLKZ8pU1bc0o1PVKeF9uV6OMe6JgazWr/7GrjD
ZC2Ebs+qnn8F7her4jBb+8ID8hPDkUOVBtUiAV+JXlgAczhcTqYnuZKNlndIhIWhq+AO4TSS+Gyn
YpeQwPgq1mpGjEpFx/N6uSTJP8x5Q702TuC6OXnubfjInKDdkDjkf5kr54TJ2RIi+8wcibPfWl6S
4tJw3v44JkyjEzCr56FFbsCmOZchey9eFu1ePg2yMpgjW34Zdc3ULEk8B62bX3AIvmTyA3/j0Ayp
NILLdNHys21VlJnAU7iqyZXRSerZ+6sib+b9vAkA2WU8cqhDpe9SEkhoU8Y5KguXDbwOgZCvnNnS
jQ0uV6USArUIy0+jVR2KUdlDiEAwMtV2PMs2CZQif14f9u1SjQVBxh0854bKfvo4HszOxP/lTZxq
b1LysahWEWkgQ2zE7LAyMK2W+zhkZ9SHI+CjCRmrMlMPBQRkD+okDauofQTsodBA7czerMclo5Tq
/qjuwDBdkgBQ50aVr+8PGGGMoNjimkjpVpYFEjgrAc+qqjxLYfm/sNqKfATWvRiUX3PPN+RDs2Vn
4y3Z3B2mug4Wi3WbMcFEIOkQNcojb62KPPqWEymk4ia36PNzM5SRtCxKEkCL6igZxHM6/d0g7Iaq
fPyagH7DPOn75yMX0BIi2oVXRzsclE5OK4wiimtKpDmrCwT+qC2v5b6t33YahS/dAWbVLcWXSj3t
h4abhhSenkP4bd+e77LbU0CGSRnb+Q4L8vhruWTj5He066vEXjzoSltcIAye5KHshOI/8EJxjENS
knDrZnuijn+sscDKB0JWQPbxqt6DiDU8CJwA6/TekiqinvjTgwO+4yIrUrmcPOPl2yiT7Loy7hMz
pkbbi/PWAUCSvr7o82kUkdeF58Yj7uKF9o1L3C9ApiTZRPfnOcOIh6XFjY6EX30k8OR2fJXWo7Ep
U+2O8XgyeJdUs8TdoWgTVXu2XMjilR0GUP9FxinQTpMyb4kLzxCm5njo8K4jTvukrVUm3U990KHx
twhs6aRlrUKHE/+zRugRgzS81We1AymEffGMR5d2jz6x4XgTYOEWzwGYpCfwjPTNZy11J50B0UXY
slXRrjakkk5igCuzEuW4sZaAF7JAKCgikDjwzlcdi6D+8fWG2qGsw5irifhkfN3hVSYoG+w+Mf9s
fCe/NlPthM3QynGs77pE8HQO3ONIPHyAORHVL00e8E3D9mZr48F5a2nFadpP10lBPo/rEgcvG6xs
4MPDH/VCVjq+1qidGYX3XYz1JofXS4VUZsCYMsX0QtcLPftzjzKteV2FcenZni5lvJG0DBgWDRtS
Jka19XRTKw0DCwZ1nBLis+sCGXSVDIlymOTLRvZ7PROGjELDOgUbizjz2r/wvKvyMjTemwTFyFJi
uAcgZ0b55zc+uKAafh0mjGEuZwJln8jIH/lnhXPunrIqBbSVUVpBLU5FZmNkbjWerB7vu7sLy9sF
U1mAZ+f+aGBjYv8ZV62HgbmeCTLVpjmGRSA3OPIjoV5Yt33yP7P9T8qUFCHO9VJYAO8BRNtWrdJm
mQExHL/wHAySlBjltPOGgyS8eA26yzwQbBnKpkkBnCAjrqtZlHqxlhnIwSiO0k60VaKCHTLfDXyh
ak9KdQ/WzAhoD+DrzFpvvKo0tJGJmqTW0SJbWqWh4LEX7xCliHdqctNkFIgXnFe6RXkAE3uVeJkb
rMBzwMRcDiqns4teQzuXIbsnidFmZYfcgjADnyXbzJy63ywGyNxYgmJFuW/4cnEP619tkEtQ93qu
2yfR7efkHOOowGKlywoFT49K1JuRqFmvavbDnYE1n1QLoADUtYpwY/pHVkS8nf86kub4ygzo9zmR
FWzOMkAdtgEOT4MWvMNCk0O9xE8xsOsKJpY/N7mwgCdqD0UwgaYmJL1XK+/e0omIERTYKjB8F1Sn
aFViqqkWfG43GFh+WFGISb4esAXzYlXgpZWPKDsDVCcBC4rL10ykZJjWGtTZ8iK5TpyrJyO5cuWm
5+AHxurkSZ1ISN67FFxb15i8rMHzX6JsavTeLzPwpvINW4mSmvMSfbEv6amYiLOjOQU1ij3IF4lW
rm0hPo7gfsB5PCC/69I9rHk/EbolrkzAEutCWyBJv/Tb8rDy1yOCGQjhtTfoSSREpyA5Xrwqqpkp
OuADcc6MQb67GsN0jfi3KHYEoabiPhtN4Wr43TW9wHqaJx0upg6Q3G/6Fb97HcTbMMOe4brMFtH9
Rts0+fO1+sLeaBZUvhx/q7W7Bu2xTvDXlJtXyEymZDGEBaCoQYIRP4CFtAAG0JRquhwAKiF/xPEw
gjqSE0YHqdDYUcymYZ6foamgZwiHwF4pP9nA0Z6onwnpZiK0zKzH0qY9bZyqjNSf1J4d5OzCEKD7
7s72gQ7THMSUP89Qb0Zhw3fzesMFWl/jeTc1VPS6Wb5sOCcYcMFP8k7EwGBeZdLnhRwb8FdxWnHJ
mHg0KhoIw0Ik+E40vyLHuOBVE1a9mM5l0eDT0q5olkQVMHuIqE2YrAkrYsm5lpvqN+J2sp+mhWFk
6SZUya2aHVcjQvhOPpr4Zjkb1pvMI2+9WUrlOFigthwOga+J9705WzhJuJSwHdyeR6ksWRTxzhfG
0AT5S7lFrZAgpEGVIfRfSKouPu0trCR8WtVygc3JILOEPmAShP4iLrn42AYG9b+oCX2C6sxyZh/k
kbjR/W0EFhtj5321vfGK+j7Wvrpsz9M5JclwLiuusenvEqC7xu3ryI5mmH+iZgzNA/JEvtRFpPZV
TWl3+j/7FSXdfbRtrHmiev3txaMkkMhgbsVgGuylyQsIFXi243qDx/MXdqQisHZGg8Pn0ITFDZaV
78j9QEoEr57n9kFJdBLQIBmDsPsrii/i6nDrMMKpihDoLEP3Ol+QZi1mEg465OVZGwBlh6MbczyC
PoKvueUueNLFuCUFZ+cPLUC7LBrEzdtBpjnd295fCYvokuRs+3dtZCHdEvEUli01Uidao4YfRdUo
zYgDB881yYhI5akKvGsP9f1rqNY7o8EzPPITWq6eqkS4hatTX+CzW/g0fZuylDrOfAEpVdjwOWM5
I7snkmvRQgGylULaa2lh1zsFrBcklMyTrvkxWAh0AX20l8scJRiF1j+noWhdw+nMPh9YTKQ0cs+u
/bzyy2niHpME+rbP/lXP+Tv6qeIN+MTUSOTVCqHivX7g+ORm6FP3iH4L63anpdESt9KAeTqVhd7X
hNgRetCkGdnTy3fywS28zsyTON3+jMfjq1jpuxFp01VBW6SXxfMN2WE9rAnWM3GiDFgZFqKpZxhK
gvbXwB0TxkUVnMSSYyg5rhXpfx3/rXkOoo1x+KX31VrIIjs4cu3x4dPURLJo7YCdmDfRw/75sqNj
RtieFYFTqz6ReUzdgNsHLE3GGPFyMz3aQ5vicK3p6mJmTyvZo1/DwuUpt6VSBSLuOAon+WWvdXdI
9Am0AkAqKxdJ0USw+8+DiQZMxBx+QXLXi8zoMYQybc1Yp8A0BtejaDDud2o9rz5q6vxeVnLX0IJG
DgZe2ROeuq7dSW6N84QPYTq+bfM1hr7G2soQeFhQXbT30ROQw8ZCdK7SmFKd91/knumYZjJBKTz2
gXOCk/f3SiinFrGOzTIMO+wqssvqUdYFvXvxR6R0xonPaREpNlv3J9Sx7bv5EsNqjC1qZUu38S+a
A78AhESpyWTUXrF4e68rWj/0IBYA3gQ2uLg70BKbLM7dcec4rLvahkD1L60FxMe1N+Ck4Uojhp5B
HuLc7CWFdRg4SDGc0j22d7Vk7QzuFy6ruLEbrmjd03UPwqlcyooPGkT1KTEiYNslHdqrd0mtEVP7
fi7AD1JusdlBI0RCF10gJ4ySzaYGsC5X8n39I0RFjVPXCzeSHu3XVVBQy2oBzemdjoufpze5l/Gi
cIdHYcufbFEnFN08CcVinrVXOTVftVt+4mWFxeoEPreFHJPhyWLozgvk9RgIK0OY7nKERncNaAXk
2rrrI8pjEmLmkrXCF+qSBdvQok/ZJaFB7dvKFVx9sEqufliJcCpSncm4aXhYTJUarkIJLpL0FuCG
i9bKJwI38ITYjM9iUejqrJxe8sZBD3AxFb90E1tCPEoThOJccP/QAglur5fkTJIhEhGS3sIHqUZs
VoyGn8TsMBJeXe2T/P143VJMEu3qj6JYxsrpbmdwWOtq5buFcznj2YT549UHs8NJeP9CtxCwd48f
iVtN53iqzzwPHL9R470dJkLWJTciV3lQvOwD/845LCnosmZH37udzZsDgZbvFYCa1FeJTCzjlEgl
BczbzVB6Ag+CWe3vBCjY+R3ud+eoZjk+1SdtH2xEpH0VJQ1Uo/zz9Qw8De9YhuHSzBhdVjJFEh5G
T5DwMu/EZe8SVDH8g1YkZsyXQt08rOqvXP9TZ3Astn1ZJiUPUAoK0l/2XSkVSCS0OqkuQe7RJe5n
2npZSU36aPxjs9xl7EQy8Ci6h1B7BYTkjczK63XUNUWJMG9dEvI5xl7DEalbwlX8vdA49nZDGs7E
qd1lz7Eol72yiEYx18bci4K/m0LqaTPq9KbuG7AtCRZFp5w3Mu35VufgmQbhqK7oFwSP46UYqWn0
cVo9XEfhWkgtqmN+uMGCBID5W0sON7BT9wfKv7EFARSZrprlwr9oJG+IOyJcWUbkIS7ZPIR52UxV
Ovc0QqnK0zDkguYHzF2LXoTyM/AMAWCU+IsVdXXjino5Aokveujx8BCwVL8Lw4chT5bvYyoxUkPS
gv6kaMvD4EjaQ9FIOF9iJsPeo9x1B2Ky7y0mBLrkHJkBsInqJD5OJcUn2VESp/0WXXSR98Et0Hkn
pHZnRX1eLAvTKtN80peW8U6YZ9K89ndSIx4qqP9h2ql4x29scqBJWrRwfIMi1Z5qZrSvJnVfhQCd
20ykcpARqVIvu5+xRka+SMVI7fiyBXdpSJqYw1MzO0O0edZ8SdsgeQ0n8Gsj4r744MEpnnI8TNGH
2VTcVumRDYKhJbvVEpyeTLYvCoaFUB8bn/RsEoZhkG1EHUabiPHyPIDs/Qj7lb3m0dku90ceXW1F
nMil/FyK4jFukE6koLj9BvPbK50GCiwjfpdeDOgDFwcg1C4rbuQZqCeFsxWu7N0dqbXTjQ==
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
Dy8GuSLXgw4Kn/n9FZ0vppRtVveVQji65VfRiXW71BaVWetmn7KGLJDBsDsyWo4YuKKaDuZySmgj
mzNFHmBQ4A==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ZM2S9AZu7NUjeAfeZVButlYtXToDq6OdAYdMYZPu2Hco0L5uzqE1w6PVSNruBpCo5pXmFPKwMWzk
QslIZZpBJvk+Kt8YwZ8JiEriv4sda8yTXGKZpfH+8ol4HzjyTFKkVCAP673FaMTP/iGSQl5rUb84
jvnaPme8XPlLpOu8aGA=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
SfYa1cMbzTWsh9AAaWhH/5SvZXWd9LzrDfk3mL5w7KWlgYspDRSSS62ZxplG9sz17Tw1f08YUuEe
xQ8CHcEFzmPZnazebh3WXbkc/aAhXXr0qVaAHmirpWBUrO4ifEsaeyFWH0qMGJFAXnMba03eT1BM
iq+SbtX09LYyoSk/mRU12QpQA7/kBCavWti/YbLQlHiEBplyhK8c0lk7AmTrQwjydAX4dv+aFnpe
6Tw3KiLzgQFswNlFxf8sS8Ko7YXHSIamBqu02COG4lFyHPti9euSzj+JCY9tyCZUMInJP6JS6fCl
Ykm2WZZdB+uXGHYPXZoBnQSWDnyjK7As6GinKA==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
uA3zAb5aDYFygMzilWmjAIqzW00c2khRKEGHdxpGsRoX/E1FxJU+SL7BqD9w9yHhUZO59QUbuFed
Dcvl2yU7BZ5L4umHbLdAfwtaLGMZHrQ5AQlQqCdLld2+woai7FNm0CMlfkQSV0nxxAK0RpgjF9uL
q14cqVTln9u0mqJ6A9c=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
gXY7Augo3g9P57bPy+Gcu411PlpVQlr1x5CQoPz7o8u2FKUQ9HZ+5es2mg5/5KdlkJ/0SK9OnCgf
gHmp3lNbWxUIXt1dDl1d+vQ9sXMu6B4/MaTMXnenT4rm27KgVlUB+diIcsFlg7Uh8A6Cu0w6Yvl0
IHzfH2uq420jze3KB+L6Tgw/pBmLCCF2BgJRQed2vrHUB+T0QU/Yv0Xfr9nzn9ky4eu0DC35Xvbo
8wac5j24iwNrec1VwZT4N7L1JWnxWZXG0QVG2eewOPjaK5lUzeY4kNr85UQZnLQTtrZflL8KLu0c
IAtQDV8gqiqwcVy0e4mgumtRR31iZa4KwIzIbw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7120)
`protect data_block
R6w3tkyFHGrHJW4XyrgCTdGw+b6pdX+IDOGkktrA8gZ+yrNLE24Nd1uiYGAdBgRt2RfdGVEeP6ab
FsMQv05DxSJ9yQow5+sTc3WFQlw3Out+R3an09wF7CPA+A/A5jgP7Xjxp7w9p/EoQND2HCqS3fX7
Gf6p/K5HmBzX32L/O49ZHy+2dtfo2WgxYtHGMOU1tITE+Vvj3wyzSkWg2kuRxWkCzcS32p4VVrnl
APqIXM4f/nl1Z9pp8ldcfj1zwxvzEkp7Q/CLkeGirttlwM4pI1fm+zx66bXdnasUIHDc1v+ac8En
GwbB/on/P2EhswobCMoKt5vMGpXhbd37aKqlJS9ZwX5cVnwrtb7Fmz8jbqAnjpoS71LdprUbezez
ZW1u5Bz7PRbbzXjGlVG+XTOG6BEjBJN74T2CtmHR0aElItpy7CqYEA1FnaVRnACRC0kMtEneacC6
LwVyYvaPvmcKnw2m+cD0YDITLg7ZKyHDoWT1sDASOC4DhB9jJabPzCFj1CWNn/T9RYXss67ZlnmV
q8X/Sr0OgSs+d+FzKuIBuRNGWu+TQgG/ntoaeJ5Bq9lI6xC2P0RtFA8kjVwU+TlNHKURQGhhGQZN
EUK+zJwC03WGZglDjLn1yYqqMajggRAmdG601AuY2O8dH1eZ7gNxzNNnEa313UXxzx3z8yvCTevB
3bsK0NWhY9qL4zVNYARVj3Ey5xEvIAPW1/vuIJz8O2ynmfi5mqk4f43gYPYB+XNuriCyUmYxc2sD
4tEDrYKVpYUwohLkyGI5Z5nXAYZ7B227s+tCqGFnHwo+xsOYw8nvfZMnDQGJnw5o+BOhDlXPr4a5
oeUWKOf6Hb3hnVYYWIYk5wN46aJjmt2uBt4rexZXqJfM8zcL4v7IVTjgSF4AfVJhw8BNtVkOc/Ly
WmZOvatbzhIhcu/wl3n/ov9JIbdE3U5KUK53qxLz1bh5Zh85AbFEhUFhomZjh+lNn00kWgQiATlM
1cOnlN6cjlIe2a8iujrWVnDtdTvTOSStEHNNNl6h4gCF3udZMyQ3Q/wlWG71rKapqGIr3Zs+NKFc
jvRPsjKvbTJYvL70qxPUKNPNEDxpwTpLFerYAfTHLGBeQziPmgOEMFLIXSbRGK+tRk6PnDk6oiT6
Y3wFtCE0/HnfZ97GhbX+topY75O2wiESv3VTALDaokrEK2W4Z0496ryS2UuEK0G+365jc1tBiMUo
XY11QvEqpCiVJiKLknK/qwuAefxbfWqx2llFN4hU+JIB2S/fBvqt+i4Ja3OLGTToMFxtVnsHKnlx
S7KYLAUEjH1nM6b1Tpu5ZhHajvtllY64nI4db6xSOv+veYYC2z/Xy7Yesbz+F5GRJCTq1mKtIviF
VyVFvRTfolnPdpiBDdAMqUXa22PA3P6JKBSfX4KZsMJSZZjEB+ShO4qC+3MfudGbu7xDNYI05UGU
9HrsLiSpYACWpH5qj7Zb2JVc6ORA2v7jrEPYvsfAngaSs1Ga2VUkH5Vd4kYQV1RaZn0hFf1Vd9Ix
9nXEgNvBqP2K7AsDv8YhPs5BYOnPZlP+dEAxQ3UUzzg9UQ5m3LfeXQct4mEZdwKu13vTVSw93XZO
jJ8qJkl6zLooRxzzzpO5PYKW8wk01N7ECzOdZCP7JHfdv7WsOVsB7zmT6K7kF17nwaAqxUxqZFNz
8zOaptRh6ui+2u5C4SCFFynAQEV5f7jkppQ/fCXYywW7yTw5dk34U4UFF/yiSsri3bJsWLg1n61E
aXtbYVeUqZbCJiMAeU8y+K8H9M6S1TMZxTxxsNY1N7YLZN8j5NU1VulGUdXfG5lsNF7W3VcE2LqG
deML+3U9F8RhVfjwTepmd1JTV0ypkOQa4XVLMHmSMcAU8Zdf4JjUhniZIeMJYigk79wwVXSfsUsb
lvRIrVwEUBhbf+h2bzAV6WWnEpUkx5/WvETLMFoTNC1CYZD05obQJ6zPO/q18Y7nf7BPjrTeUXGg
ps5ia0evfLvd/47YWoDnWXVINeO/JKxIHBB6lxMYwQIOjOTVzEoRdUiplxEGzOtpnCVjItqyeW23
egzVA+OelVr4XsuFWw0tJA7hmBDdLyBi2UI1cCg8kg+8nPyLfdB98pkyVh8g95eywb9/YxbiYpKr
Q+wku1Ao9ncRz+PclZQbdAaE7fG5/Jn4dXekfKmgEBbRIcxAmO0PWsE8WPkz4O+TSRIZhID+di5Y
9UPQPVZ+u5sAUJkaTphk4yxtiOV/tBSfHdtf99RWkptOdndUtssz9RcIFiNu0groG/k4FM2fRPTg
aTEUm+ycwZ+5ehb1BtGFrqrZuy1/AiqgZebxQ1/gLGVtNm2yKrskMMwRTM/rAarKVbm5xPeovQ1m
Qk4xgqHbHxVBfFd+fnEStH7KjFA/H0YsIvK1+JB6YkPopzDv5G3hhehXauCQsmRUI8nGL7tKcVJ3
iaBUxNy210nOv91NlUDWwY93VnjhuX+4+B9TUy1PTiVV2k3dkTSipd9DxHRziUMhP1stUcejaciZ
4tgtWeLDCxIvr2OcsmM3DQXpBHPpMvhcwHrY7qeJam9U3zsVwqtaL6tGcZix2EIehsATGahPefVV
J3Zyl3ShviVKNBz9EMI2toTnLaiInkbLVfjc8ueCUUPF3cu5ExxUQ7NyHvwligPOYF4WsqXhZhDZ
7J9zN5z349ZtwqwTEDM7d4QZGOaa/ZkyUoFJOWMJBoZr8ETX4zO3ps9/qG5oYNFosTLpTDpQG1GW
hFzacPA8k6trFjXPY/e9QmwP9hmtwXZSteR9aVTgmlJB9Zl6gYBE9hFxdYGaqDbky//mhugxBO3o
otuw6KD6WU/5XP7BWpErKIeDCqZSkWYZoN/1dVNbyzwVo2jYgvFefR0BGmmxAunPJqv6oKyJ5TdA
eOD/NtKPwJnKqNx68jOWmNPIwai1pp7EqpwiKgbNjWQ/dLMhBlyBzFGHSYgMQYmIef+NxNnKdOZy
pOhM+iofJayXaRC23lMimQvNBZpntFItZsBjE3ISFW6kz5xvDUd8wSOqOEOmVswPI6KdIfjF8atM
0GUzYWytQIwqMErOHVpzOklqSDtW0GgizrKU8mxyoZBkmdA/HKV43WeqLGTJVqHNRaBL4Kl9Q8A8
jcvW9GT41u5fk5tleLMOKsDvmtcmfaoO5E986OyS7e+PDFFvAYbCG3MlJHWczqDegTQ1i676uOX5
bjyENLvqfKEUH3h2PfJVYG0Y70yjsaRwdTpn5Qi/Lmh2iZLsEV2S4i2AlSt1oqHuT5rIU1C87PPn
D2W7V3wuEiR3WwkGEggODx2wItpGuZjjAX08HEWNF9iJ79yGdzkMagQNhNoQ9/r7wJDaqwfziEQI
hzGJKeDOFhZXCkkxIYYU/ZX0yy/ig+p41cA5zsYMnhXZhcqIGuhTe4pYHCSZTNnixGNlH+BIgYSC
G3vyaXWGeJeij+fnNHE6O/deO9B3X1VSL9uAtyhmlGgr/pBuYPhB4OW1o4g193Wx+d19+m62nL+U
/lc3AQGbZ7lSC0i9BKuTDmKP/XRSTqrbUVyFBmJNfhpjIW4U+HmzJQqpL7Eh1SFlbOkXfQfXCsth
fx3cQUZGAudcfa0CE0v4zT6vcKr0BDk43VOF0ya+IohOTRyoB2BQl2kKB77T1pSf2ayEo3PVzkaI
eHfC8VFljHeCfSGXhuHtNhX+0HmvZN8yV3DUM5z2f0O8phGL1g94rJVpU4T8LFt12XgElLF3ju0Q
veBmr0LbAvKitCYXMD6iL0yGFkMxiCK59pbQY0XzKSbdH2fQJotg+wJ0kd1WUPBVy5jJnOYojrgP
Ch6QZviMKNhDe1TE0XDtAB2hCRXGHZuk5gMH4BqK/N1xEEJWseqpj3L+0rtE2MQpkWLPEXAyjMj/
SHN+Lj0gzIFa7nkAA3kpUXrY1lFOLhZyw0TBRHHzWsMAGMgHnmtp1X1DWR1DrEv/mtdCj6FH957S
GdGNznk7bFDkYQpgaxd+HBfMub/nzeQwzPpABcpMiTjMUDc05NMq3B/NUgpUBI0F3CEXQJDUJ3NT
sYENxN18aK8FWOf4gWyyeEtN/c9jh7W3x62VHYT+dm4E66AF/MpIiiviDg0/YxE6MJoLxzDyyEAb
93SGZSGQ1cvGdS7dD6aakIoz7uVVS/479SVBBMBUhJcZt7NM7bwR10S35cyN2g5tPkHxyQ0+zNqc
3Ip1yl/N9eWbhZsyg+xS84rtKJJngcPztxa3j+Jn4AkSZFF0XoGP2xxcb+4VtfhL9YlPbv37xFV5
c5NAH4Fz1RMfE/aNrCFU0VAylNue03tQElqRjLP4LzpZHE6wN+M6CI4GrFit32oEzZMTyrBz8FGb
zDJQrx7sAHZojwh9oypP7ntsak6z9vAoCgmO7cOLKZ8pU1bc0o1PVKeF9uV6OMe6JgazWr/7GrjD
ZC2Ebs+qnn8F7her4jBb+8ID8hPDkUOVBtUiAV+JXlgAczhcTqYnuZKNlndIhIWhq+AO4TSS+Gyn
YpeQwPgq1mpGjEpFx/N6uSTJP8x5Q702TuC6OXnubfjInKDdkDjkf5kr54TJ2RIi+8wcibPfWl6S
4tJw3v44JkyjEzCr56FFbsCmOZchey9eFu1ePg2yMpgjW34Zdc3ULEk8B62bX3AIvmTyA3/j0Ayp
NILLdNHys21VlJnAU7iqyZXRSerZ+6sib+b9vAkA2WU8cqhDpe9SEkhoU8Y5KguXDbwOgZCvnNnS
jQ0uV6USArUIy0+jVR2KUdlDiEAwMtV2PMs2CZQif14f9u1SjQVBxh0854bKfvo4HszOxP/lTZxq
b1LysahWEWkgQ2zE7LAyMK2W+zhkZ9SHI+CjCRmrMlMPBQRkD+okDauofQTsodBA7czerMclo5Tq
/qjuwDBdkgBQ50aVr+8PGGGMoNjimkjpVpYFEjgrAc+qqjxLYfm/sNqKfATWvRiUX3PPN+RDs2Vn
4y3Z3B2mug4Wi3WbMcFEIOkQNcojb62KPPqWEymk4ia36PNzM5SRtCxKEkCL6igZxHM6/d0g7Iaq
fPyagH7DPOn75yMX0BIi2oVXRzsclE5OK4wiimtKpDmrCwT+qC2v5b6t33YahS/dAWbVLcWXSj3t
h4abhhSenkP4bd+e77LbU0CGSRnb+Q4L8vhruWTj5He066vEXjzoSltcIAye5KHshOI/8EJxjENS
knDrZnuijn+sscDKB0JWQPbxqt6DiDU8CJwA6/TekiqinvjTgwO+4yIrUrmcPOPl2yiT7Loy7hMz
pkbbi/PWAUCSvr7o82kUkdeF58Yj7uKF9o1L3C9ApiTZRPfnOcOIh6XFjY6EX30k8OR2fJXWo7Ep
U+2O8XgyeJdUs8TdoWgTVXu2XMjilR0GUP9FxinQTpMyb4kLzxCm5njo8K4jTvukrVUm3U990KHx
twhs6aRlrUKHE/+zRugRgzS81We1AymEffGMR5d2jz6x4XgTYOEWzwGYpCfwjPTNZy11J50B0UXY
slXRrjakkk5igCuzEuW4sZaAF7JAKCgikDjwzlcdi6D+8fWG2qGsw5irifhkfN3hVSYoG+w+Mf9s
fCe/NlPthM3QynGs77pE8HQO3ONIPHyAORHVL00e8E3D9mZr48F5a2nFadpP10lBPo/rEgcvG6xs
4MPDH/VCVjq+1qidGYX3XYz1JofXS4VUZsCYMsX0QtcLPftzjzKteV2FcenZni5lvJG0DBgWDRtS
Jka19XRTKw0DCwZ1nBLis+sCGXSVDIlymOTLRvZ7PROGjELDOgUbizjz2r/wvKvyMjTemwTFyFJi
uAcgZ0b55zc+uKAafh0mjGEuZwJln8jIH/lnhXPunrIqBbSVUVpBLU5FZmNkbjWerB7vu7sLy9sF
U1mAZ+f+aGBjYv8ZV62HgbmeCTLVpjmGRSA3OPIjoV5Yt33yP7P9T8qUFCHO9VJYAO8BRNtWrdJm
mQExHL/wHAySlBjltPOGgyS8eA26yzwQbBnKpkkBnCAjrqtZlHqxlhnIwSiO0k60VaKCHTLfDXyh
ak9KdQ/WzAhoD+DrzFpvvKo0tJGJmqTW0SJbWqWh4LEX7xCliHdqctNkFIgXnFe6RXkAE3uVeJkb
rMBzwMRcDiqns4teQzuXIbsnidFmZYfcgjADnyXbzJy63ywGyNxYgmJFuW/4cnEP619tkEtQ93qu
2yfR7efkHOOowGKlywoFT49K1JuRqFmvavbDnYE1n1QLoADUtYpwY/pHVkS8nf86kub4ygzo9zmR
FWzOMkAdtgEOT4MWvMNCk0O9xE8xsOsKJpY/N7mwgCdqD0UwgaYmJL1XK+/e0omIERTYKjB8F1Sn
aFViqqkWfG43GFh+WFGISb4esAXzYlXgpZWPKDsDVCcBC4rL10ykZJjWGtTZ8iK5TpyrJyO5cuWm
5+AHxurkSZ1ISN67FFxb15i8rMHzX6JsavTeLzPwpvINW4mSmvMSfbEv6amYiLOjOQU1ij3IF4lW
rm0hPo7gfsB5PCC/69I9rHk/EbolrkzAEutCWyBJv/Tb8rDy1yOCGQjhtTfoSSREpyA5Xrwqqpkp
OuADcc6MQb67GsN0jfi3KHYEoabiPhtN4Wr43TW9wHqaJx0upg6Q3G/6Fb97HcTbMMOe4brMFtH9
Rts0+fO1+sLeaBZUvhx/q7W7Bu2xTvDXlJtXyEymZDGEBaCoQYIRP4CFtAAG0JRquhwAKiF/xPEw
gjqSE0YHqdDYUcymYZ6foamgZwiHwF4pP9nA0Z6onwnpZiK0zKzH0qY9bZyqjNSf1J4d5OzCEKD7
7s72gQ7THMSUP89Qb0Zhw3fzesMFWl/jeTc1VPS6Wb5sOCcYcMFP8k7EwGBeZdLnhRwb8FdxWnHJ
mHg0KhoIw0Ik+E40vyLHuOBVE1a9mM5l0eDT0q5olkQVMHuIqE2YrAkrYsm5lpvqN+J2sp+mhWFk
6SZUya2aHVcjQvhOPpr4Zjkb1pvMI2+9WUrlOFigthwOga+J9705WzhJuJSwHdyeR6ksWRTxzhfG
0AT5S7lFrZAgpEGVIfRfSKouPu0trCR8WtVygc3JILOEPmAShP4iLrn42AYG9b+oCX2C6sxyZh/k
kbjR/W0EFhtj5321vfGK+j7Wvrpsz9M5JclwLiuusenvEqC7xu3ryI5mmH+iZgzNA/JEvtRFpPZV
TWl3+j/7FSXdfbRtrHmiev3txaMkkMhgbsVgGuylyQsIFXi243qDx/MXdqQisHZGg8Pn0ITFDZaV
78j9QEoEr57n9kFJdBLQIBmDsPsrii/i6nDrMMKpihDoLEP3Ol+QZi1mEg465OVZGwBlh6MbczyC
PoKvueUueNLFuCUFZ+cPLUC7LBrEzdtBpjnd295fCYvokuRs+3dtZCHdEvEUli01Uidao4YfRdUo
zYgDB881yYhI5akKvGsP9f1rqNY7o8EzPPITWq6eqkS4hatTX+CzW/g0fZuylDrOfAEpVdjwOWM5
I7snkmvRQgGylULaa2lh1zsFrBcklMyTrvkxWAh0AX20l8scJRiF1j+noWhdw+nMPh9YTKQ0cs+u
/bzyy2niHpME+rbP/lXP+Tv6qeIN+MTUSOTVCqHivX7g+ORm6FP3iH4L63anpdESt9KAeTqVhd7X
hNgRetCkGdnTy3fywS28zsyTON3+jMfjq1jpuxFp01VBW6SXxfMN2WE9rAnWM3GiDFgZFqKpZxhK
gvbXwB0TxkUVnMSSYyg5rhXpfx3/rXkOoo1x+KX31VrIIjs4cu3x4dPURLJo7YCdmDfRw/75sqNj
RtieFYFTqz6ReUzdgNsHLE3GGPFyMz3aQ5vicK3p6mJmTyvZo1/DwuUpt6VSBSLuOAon+WWvdXdI
9Am0AkAqKxdJ0USw+8+DiQZMxBx+QXLXi8zoMYQybc1Yp8A0BtejaDDud2o9rz5q6vxeVnLX0IJG
DgZe2ROeuq7dSW6N84QPYTq+bfM1hr7G2soQeFhQXbT30ROQw8ZCdK7SmFKd91/knumYZjJBKTz2
gXOCk/f3SiinFrGOzTIMO+wqssvqUdYFvXvxR6R0xonPaREpNlv3J9Sx7bv5EsNqjC1qZUu38S+a
A78AhESpyWTUXrF4e68rWj/0IBYA3gQ2uLg70BKbLM7dcec4rLvahkD1L60FxMe1N+Ck4Uojhp5B
HuLc7CWFdRg4SDGc0j22d7Vk7QzuFy6ruLEbrmjd03UPwqlcyooPGkT1KTEiYNslHdqrd0mtEVP7
fi7AD1JusdlBI0RCF10gJ4ySzaYGsC5X8n39I0RFjVPXCzeSHu3XVVBQy2oBzemdjoufpze5l/Gi
cIdHYcufbFEnFN08CcVinrVXOTVftVt+4mWFxeoEPreFHJPhyWLozgvk9RgIK0OY7nKERncNaAXk
2rrrI8pjEmLmkrXCF+qSBdvQok/ZJaFB7dvKFVx9sEqufliJcCpSncm4aXhYTJUarkIJLpL0FuCG
i9bKJwI38ITYjM9iUejqrJxe8sZBD3AxFb90E1tCPEoThOJccP/QAglur5fkTJIhEhGS3sIHqUZs
VoyGn8TsMBJeXe2T/P143VJMEu3qj6JYxsrpbmdwWOtq5buFcznj2YT549UHs8NJeP9CtxCwd48f
iVtN53iqzzwPHL9R470dJkLWJTciV3lQvOwD/845LCnosmZH37udzZsDgZbvFYCa1FeJTCzjlEgl
BczbzVB6Ag+CWe3vBCjY+R3ud+eoZjk+1SdtH2xEpH0VJQ1Uo/zz9Qw8De9YhuHSzBhdVjJFEh5G
T5DwMu/EZe8SVDH8g1YkZsyXQt08rOqvXP9TZ3Astn1ZJiUPUAoK0l/2XSkVSCS0OqkuQe7RJe5n
2npZSU36aPxjs9xl7EQy8Ci6h1B7BYTkjczK63XUNUWJMG9dEvI5xl7DEalbwlX8vdA49nZDGs7E
qd1lz7Eol72yiEYx18bci4K/m0LqaTPq9KbuG7AtCRZFp5w3Mu35VufgmQbhqK7oFwSP46UYqWn0
cVo9XEfhWkgtqmN+uMGCBID5W0sON7BT9wfKv7EFARSZrprlwr9oJG+IOyJcWUbkIS7ZPIR52UxV
Ovc0QqnK0zDkguYHzF2LXoTyM/AMAWCU+IsVdXXjino5Aokveujx8BCwVL8Lw4chT5bvYyoxUkPS
gv6kaMvD4EjaQ9FIOF9iJsPeo9x1B2Ky7y0mBLrkHJkBsInqJD5OJcUn2VESp/0WXXSR98Et0Hkn
pHZnRX1eLAvTKtN80peW8U6YZ9K89ndSIx4qqP9h2ql4x29scqBJWrRwfIMi1Z5qZrSvJnVfhQCd
20ykcpARqVIvu5+xRka+SMVI7fiyBXdpSJqYw1MzO0O0edZ8SdsgeQ0n8Gsj4r744MEpnnI8TNGH
2VTcVumRDYKhJbvVEpyeTLYvCoaFUB8bn/RsEoZhkG1EHUabiPHyPIDs/Qj7lb3m0dku90ceXW1F
nMil/FyK4jFukE6koLj9BvPbK50GCiwjfpdeDOgDFwcg1C4rbuQZqCeFsxWu7N0dqbXTjQ==
`protect end_protected
|
library verilog;
use verilog.vl_types.all;
entity cw3_vlg_check_tst is
port(
bcd0 : in vl_logic_vector(3 downto 0);
bcd1 : in vl_logic_vector(3 downto 0);
LED0 : in vl_logic_vector(7 downto 0);
LED1 : in vl_logic_vector(7 downto 0);
LEDG9 : in vl_logic;
sampler_rx : in vl_logic
);
end cw3_vlg_check_tst;
|
library verilog;
use verilog.vl_types.all;
entity cw3_vlg_check_tst is
port(
bcd0 : in vl_logic_vector(3 downto 0);
bcd1 : in vl_logic_vector(3 downto 0);
LED0 : in vl_logic_vector(7 downto 0);
LED1 : in vl_logic_vector(7 downto 0);
LEDG9 : in vl_logic;
sampler_rx : in vl_logic
);
end cw3_vlg_check_tst;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_RSFTPIPE64.VHD ***
--*** ***
--*** Function: Pipelined arithmetic right ***
--*** shift for a 64 bit number ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY hcc_rsftpipe64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_rsftpipe64;
ARCHITECTURE rtl OF hcc_rsftpipe64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (2 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (64 DOWNTO 1);
BEGIN
levzip <= inbus;
-- shift by 0,1,2,3
gaa: FOR k IN 1 TO 61 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(63) AND NOT(shift(2)) AND shift(1)) OR
(levzip(64) AND shift(2));
levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(64) AND ((shift(2)) OR shift(1)));
levone(64) <= levzip(64);
-- shift by 0,4,8,12
gba: FOR k IN 1 TO 52 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
gbb: FOR k IN 53 TO 56 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(64) AND shift(4) AND shift(3));
END GENERATE;
gbc: FOR k IN 57 TO 60 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(64) AND shift(4));
END GENERATE;
gbd: FOR k IN 61 TO 63 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(64) AND (shift(4) OR shift(3)));
END GENERATE;
levtwo(64) <= levone(64);
ppa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
shiftff <= "00";
FOR k IN 1 TO 64 LOOP
levtwoff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
shiftff <= shift(6 DOWNTO 5);
levtwoff <= levtwo;
END IF;
END IF;
END PROCESS;
gca: FOR k IN 1 TO 16 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(k+48) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcb: FOR k IN 17 TO 32 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(k+32) AND shiftff(2) AND NOT(shiftff(1))) OR
(levtwoff(64) AND shiftff(2) AND shiftff(1));
END GENERATE;
gcc: FOR k IN 33 TO 48 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(k+16) AND NOT(shiftff(2)) AND shiftff(1)) OR
(levtwoff(64) AND shiftff(2) );
END GENERATE;
gcd: FOR k IN 49 TO 63 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(2)) AND NOT(shiftff(1))) OR
(levtwoff(64) AND (shiftff(2) OR shiftff(1)));
END GENERATE;
levthr(64) <= levtwoff(64);
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY std;
use ieee.std_logic_textio.all;
use std.textio.all;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
entity state_machine_test is
end state_machine_test;
architecture behavior of state_machine_test is
-- Component Declaration for the Unit Under Test (UUT)
component state_machine
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
state_input : in STD_LOGIC;
tc : out STD_LOGIC);
end component;
signal tb_clk, tb_reset, tb_state_input, tb_tc: STD_LOGIC;
signal clk_te : STD_LOGIC;
-- Clock period definitions
constant clk_period : time := 20 ns;
constant clk_te_period : time := 20 ns;
constant dT : real := 2.0; --ns
constant separator: String(1 to 1) := ";"; -- CSV separator
begin
-- Instantiate the Unit Under Test (UUT)
uut: state_machine PORT MAP (
clk => tb_clk,
reset => tb_reset,
state_input => tb_state_input,
tc => tb_tc
);
-- Clock process definitions
clk_process: process
begin
tb_clk <= '0';
wait for clk_period/2;
tb_clk <= '1';
wait for clk_period/2;
end process clk_process;
-- Clock process definitions
clk_te_process: process
begin
clk_te <= '0';
wait for clk_te_period/2;
clk_te <= '1';
wait for clk_te_period/2;
end process clk_te_process;
-- Stimulus process
stim_proc: process
begin
-- apply the reset signal
tb_reset <= '1';
wait for clk_period*10;
tb_reset <= '0';
-- apply the first input
wait for clk_period*10;
tb_state_input <= '1';
wait for clk_period*10;
tb_state_input <= '0';
-- apply the second input
wait for clk_period*20;
tb_state_input <= '1';
wait for clk_period*10;
tb_state_input <= '0';
wait;
end process stim_proc;
result: process(clk_te)
file filedatas: text open WRITE_MODE is "state_machine.csv";
variable s : line;
variable temps : real := 0.0;
begin
write(s, temps); write(s, separator);
write(s, clk_te); write(s, separator);
write(s, tb_state_input); write(s, separator);
write(s, tb_reset); write(s, separator);
write(s, tb_tc); write(s, separator);
writeline(filedatas,s);
temps := temps + dT;
end process result;
end architecture behavior;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mqMMwuwihGR6UeYKQj/60B2AWf9clX8+kFsa2isPlH6+2kxLIuDt7Rog5tz/0lfUbeoT+pRbl+FK
EFuPUDT9UA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
GQNkFBuWBHbpOmzURG02aJpZ7XKog6XNa8zAE2eQ3xj6PMygKXnkH5nn5URP8M9zfRVrWMk/ENZe
OrfxqKkMYOO2BHpEVUo3Bysl8N94qsiFvMaZpx1aJs3h44WmFkcc5XmHHZzhuvDZMlvkL+NyI0Po
kVi/UVZXCA0LAFo+kas=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rF+726hcpcVvxumQD/VPbCg8OFhPAwhb+Ul/5yt3t/Y1dDwZTrWppNHnLd7vmAtAYPyIF9pMUFUi
G3mui52lmlfF3iqJ/GdKjDzuLAy8lvBhpXuTmK+qQHV7eIdpy0vjzZmPRLup1PQKZeB0M8XENMdB
GkErIZrb4Ee0++t6GDvZKJmokpnSxRpxXqwd3YL+vn+wDME5+EIu3CiA/RlyOJ702F5TvIno7XYn
GZWlK5VFOi4ZO7mokHWasx0j7y2kCik+7zlGTZRSBPLUHxfSfUScQU768U9/S8TWH46Pcc90rek0
BlXcDEWGA0+dPlrMyZBFJ1B7DaJImvasBbrAtQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
x1gF98cy/K84iVqcjCIppYzn0b7EKIDTECh3SrVpndzv98JZp5lbsMBz14Yww8sb3Izl6j0UQ00A
FlIUfOrZq6kV0QyUREmP9Cvgb5uZpeox0nZ9ALThxHbxA/2BuwpdefU1+2M/Jku2Tf+qiFX5nV/y
iw2ehkDuNOx/ZSvhRaU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WBR3rarbr8o9Z9/IjwYqKM1+Ju6cRZUMAYs/BMJgccT/rO8QU6q0PGwSGVFASfTroNwC9xuaU9WW
lzzoJsBD5UNJ83X3kRSkSYOGUlhb2hWBwTp3B8ME7zpu9Li21BSn0JVbUlxJpJYJM5cJO8yY7A0N
5tps9qrfQRpmM3Rpql6m2gzaCGTNKTzHMsYX3RuOxZqVwSZb6QmqO3wbYEeI3fc/5q5gNCK1GD5Z
JwpFNxuUNr3JLMJpwtYHP+DUulxMruMaRvupFJQOWjMj0ihk6TZNl2dHMGLvwFop4foQXoFL3jKW
auopUbvx1BRfHytRSc6XV99/k3rS8+MlNYs5rg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13920)
`protect data_block
IUy5vHafcKg6rErwcdt6Se1WqHGyjVk3DQ3vb/5hCTC/XrHxbqa8oGcP+at55+tDco5ik5o6UzQY
5/tVjPJDIEjPt2ztj3RZvjbcexdmpk45mTlfz27MOR3dWQ/3z1WlhTQwFu+GWK2WLGp83Ti1S/1p
KbrmMTp3QsTSsqenyYy7l+DV7b/a0tcD7i9r1R4kAxQ3ma5xVphOBYbMNzJuWHyfdcchnk41YZfY
xJNrTyAgItXz/eITABo8QVEpIw9krRPiwIOiPg3w58oJHYSPocoh+MBtBxTrlQ7D/2x44b7vsZ6d
6yr47BKve4z7tVjgSU+UA/4P1EHuCCP/Id9g/xLTz8drT4KRjVPUW4N+YDcnennUfUO5U9VZVq6+
+H9MnA4FzsMt9+4BGBi1AsH5l3o0nSS4/M/EnwkTj2BsglY6AchVBL1HnjcT99hiEf1ImHneguIh
QFjcplBcDcNJILs2ZJhiP9U8+oZSqsG9993R6XoTcMB6aXXRbZRaW0JOsLrkjqwRUVDjfxQXhJGk
/HzmoHLNgFT5Ud23xTwREVUF/DJva/gVQEht8alcPaBtYhlKclwi1AqW4U2+qS0/SUXItrOPBqkB
RO3HuoE08taiguK+sJsRR4I/Um/uBoTHE4FG2TeavksyJgvIrj6Ae5hEzchq70PjL5Tn+roIMIxU
bJpgoeaWhrnRbD8073a/EIKUXb5956ecDPdoTlMHVtNVLtZFhvarMvhoGNvHHnF1EkkOCd2xZbUm
MEQl3vOskD/gSbsVG22DlShPPeio6ZhFQuHqcJ49zVOra8RTBKtSOi8m9Rx2D9tdUnVaR59ZKARq
CoqGv+WnlvLC2LVAdiMmipMgY2xkVfLsXI8eWH3363zBfluysGRiGz0DI6v4uyUmU641pGM3Xpsd
DtAD5mVxijOaHeGtIrCTTTZ6QkLQf37FBsaGPKYCQs/XV2zx3gZ6+iQ6bxZh2jO9x4ozk20LWqUk
kI2V6OSZ4MyhFwpnROEjSGmOw+XCBCFzUX6Now0IFkamRR9o1tl6QjqURTVQywh16yDPJGcRKt0M
Tn1Gx3CmpEFAaEUnhYyHk095ATiUKDFONvgMBafLZrTotI9h6dpcpZt8qr59S8a8M0ZZ2M4ICczp
qSV0T0RIdtAdgfpC7vCsMOxxp/KQuCJZaFAKKDr0g8Jg1xaTrZHq09zuJ2zdBZXsZD5/jjc2U8v3
6Kaw8eycGqaNEawFt9a3fAP3RCQDW9cga3rIDSyn9pdI8FnlPYBg+UEIs8uto5gxgBbTdpBBdppE
fiQu1NhMrMtULKDlqHM+QbArqPLhR25+J8MGOSxP/7Z2pA0v8k1r8NMLzWl0qbQ8bx8C2KncvZyJ
JxdXJJ9wHWnsxFdTzj//th962KZXoSKU2zvK8OwGeqhaXHCmNnKsfNukyNXhAyxCsSg0xwpRQDME
krUZUjWhbwf5JVwx+YzNMCoLI10/9F7lumRKAhW2KbH9JKVSY58eFVKV6LDy9kQGjwdG/wPoWiaj
gyuLJWUPgJlBmOo4deOFtdrhBMLPV2NbNcYay4GKXyjHI+5gePrPL2WqNH7rZoXCN8Mlj6GneRYT
OE31IiBubptXbdne9oY3EdMlXFaKImWeffabRWQaBYj+x3Kn5dtzkOV1hvekj4PzbW79VjwCqxlj
1GaKUpyMpY5k0vB5XDiHO2HXq+pQyfKhtny9UBEUp7NIKSq1COvk2wAGl6zwHoR7PpbkJOlW7dlb
IqOSMBowWvkvilry/xiYOPhczTRmMjUX88M0RFFtYX2mFVfsi+PLdhLJRzn6RLyVD+Fg8Bm44Cqk
XCWp1sxS43pb1c0DNPBATzTtcNuYmmziFxQk18uO1fqOKtmgbeERrOiSzaq403G1R8GbVZ+XsbBE
t528S1+UMxK1YVmhSOaNvjnb7EVX5tK37xNpN/OYbJP1fPqrBQTn5/7JWHsVfTEgzjXVbJ5ocaG/
7ul31b/FKOzicLlync7Lmo1HszdSLx5AeNbIWyJAZWW/5f0s2+6kd/SDCuC+UUoxrVZh2RT90rvB
fLrGWz4v2HMYHa4wjKfnwRXFY7iJksacNkkauXAIkD2CwZErhhi2co+Rp04C0bVpR3aVQ/h3CCOM
kgEstHEAvCefLPqdO9OQB3uZxPfzotnxtrYl7s4k7YGTJX3z8a5cd0oNxpib1ZqI9Z1C8DSNxZGA
gx7/y5iOKlXznx6wAxujWey7fjv5yc3Kl2UBsTedlO4Af9njL55pQGZMNTEDXuHryThhJdSL8aZC
gUM73H7jPMVo1gLd7j3LLM6F1TNXMFI3t2pGtkTVzCatQP1ZSA//NLHf9TpX94cCXRRnvahUI2K9
SFUpzmVVfsRkzX5ya2aID4qSWS9WXFfVI7Ef+iqkNIY9MgK7bxaYPzOkCCv1j3qCLFFXwvc//Pas
vigDGLkBlY2YRIwuEfwg17SWyAYF7yXtt+ZiDQW7rRYe6738yEXJzJ9s+/mE31XCowYJ4edd+6op
7H72/4aVbDrDFpvhu7Z515ylga1SBb8xYsCG0nwVoHCb/bwvVD+dG+lGL1BfF2yEAuyrHHCSqo/o
cDpOfIPDLtdsjx3w4N35ynvIeVlybaTukdm1cNvPWG74p8I3+8r/LxOz02L8lRC3H6CKbBtBb0jl
S6+ENM1LDWJ3oeYT00NVpE17CB/MdKy0g9fVUHpJsekb9zpcazoSQE73Ny+ANIRIFyDqsL7s24+2
VUyApyfsFOQmbKyx8+Xfj6X0S+SKCOzQQYzgzyMg8+h9tAC8vcBiTf5hUUnZZ69a6IuLHrdxuoxR
XkGrE7NhGKXF27shBOTwsxQNGyrubHdgzITSMv+cCUWwuyV2v4Vk7J/qQIC3K6DKorXPdXKF+9gp
BjfL/HHg9RIqAwrQN77TXDJ6+YEaoOnOl4GbW0pvV0otEHFpE20ihQO6+jNLhXuFvmyGvxSMyAxX
Lf7HJHwvjynv2uJwYs/jXWwXuP3ToKzjxjmtnrfM4kWIAxZu1BAdk3/1Tg2NH0dCbxWVsBJfQ3RL
Rb/Xehu4/FW/YiHYfCEqoPyYTtp3uM8oKa0MKl2HdwBQVJo0yYSAFD6vY2TvfcXY8WvDSQDUzDFg
+evWg8dvUmFuXeD2NZ9X3GzipY9gcYgvLczTLiD4QtYhjiFT+/TgSiRfB8hBoHWMM2/+V7SIVWNx
vwv2a48iXRmEKZ5m9jk1kNglt+aMKp28DQ4Uu883p4DpFOWU7Urfb7AYXK5YYz6K3hUiqX4rwP73
l7j6vyMfC2rTE5F3dByqMHokEsnAzzwwW/NFqBjzV2Z6pX0BxFgc4DJMfi8Og096QmptzG0bwc3+
s40V5fPf5MZwdtuSW4ZWSVmk30kEn9xJnJzAND9lnnoWb5MMqVh3ty7y7YCtR7JsZuyFfm9tEC98
Eo9I1DPFCdYG1p/EcypwXkf+frFQvaf9+K0lr7/v3pBWHlykb2tvFufN8+pD6lYwpFZvnvG5805w
Qb4WTFZNbzgi6ZhysIpHi31LMIhftcoyR1Lx36JOKEqxPjr/Wvy4ltP22vPvddxLPiMojL/0SpS4
Gjs3D36XZBS0oe1W8EnqJvVOKyFnIr6aMpsKdeWnDja0LHzXKwTRfwlrj/tSpogHFzj/ty9V8P4O
6MdirOqycsOcBpvDAU9U3VS+duc4BMV+onCK0Id6UuATVkRxctVodX6wXumH6oK3PG5PG1Dkj/pf
9ckigwRT5b0hJdb3CtN7s5cHh9EqMfjajcGxeJT1PEPKmS1q4i4gqnvgxVQN9Yo2RT1e84X/a1IE
NXY6hz8olxUqeCyy+p8uT7voAtJ2NGvv3SNiiPxSCtk8k1LC45ytunDfVe/7noMNrs0Sf+J1jC84
hhSZ1s0OfHpcmyYStlnftd044kUjtIuaIetMarjtB0sZOH3KYziCvkTDktmWMaCPi42AvfXo0kik
J8x6LEP7gd4S9JK6InzmYq4Ob5objflosl2kBqsguLo7GTxF105HBnSiJ2FmEvG2OPvk/5PJqyHL
SDNqs/xb4lCuOUWONBdByHntaZDvFts8JBr4ablhsQZ987tOZT15AYulYXSmNVguMUdl1nR+Gzcg
pnqHQThW435b76Yo252r6lt5+V4cDGLEgKPun0BNiAYJMihkY5RnCd+CutyNVfDwwqFdOacI/qom
XqGYBa4smohCaW45Ql+WLrQ46MOq7oqjsASMO1WUyoc47tCQZ1nTFDGgNJWaMS9P5PS0i0GDnm7Q
N37wMjLW2RD9CRSXc85owjtu4FIMJsPmSv143YooByxV00XitMH2iQdHgqOv0A46lzllPCfYKCau
OYUrgz3YC4teyadElu/sjP80VXAZpP/aeY608nT8GvVoNsOdy339yfz3u9I4JTUJNpSsyV8cXIEM
LQuVkUmFa548KWxeGewaroptstbM7tZPLz2hSYVHF+6chTT5aZopp70+wOFhKE3k4pvANfOUkCNA
MynbiJJctkkaYrzOeyCT+A2bE760ROR3ZVYra0ByDbQH3E7rvd1Ttza0wJEtvk4rllxkZXZa9ZMb
OoF9Tna2Aohe3WqW4CUdc3yTKUjn+n/i4mnDt30I5g3fJ/76/ktgg4m6SWd/Zjjjaaspj/A/VArx
P+1evFBnkbOAuak6ybXIKITDWVPsrYV/EEGnGFsoKn8A7zJCxIc2n9fPBzmYfpZumNY/MRndMszd
PB1A/9Sx7W1G346Atfh5I4wDfWNrR9d4Cu4Px7BwpdbNPayNQzlGN0vXudut7S4lXu+G2ojFi7mX
VU/Pq+mIaMDfdYq43wt1XqAeLaUEFFOOLYuw3AnUiWQfRmMh8EF6mOywETMZFnvuoWQrg0V7TqDP
c8WtMkWUdG7iOOVtZICWBRfhvFSqg7pWElsmzwK5K9UjLkv9rS/8Pegq7Vr2bHvKPI5YpPVeeL18
OliXKyrjrKkN14K1kRrOJ8TTwzHDcldX5Vfps28EjokP7WZLpGXvywluXWc2nCWb1Xu3JCmVoC/0
XyJYB04sWAODfP48thi29f23VAefXkqSrc4kfsoJpinxSQZYm2tDq7UG2puArbTqljtmzgLjWl7/
d9tsedDzrejUmeMGpDU0dEN0epynM450xmLpu1w67vlvg+FjgpERd8OovYhEquMy/sMSmQbmavFr
TYSSQ1GoKycT/7NuykBcqzy5Iq5B99IIQGXZk9O004p5YKG4AQYihWGCRzGR/royRi27/tuYcbJJ
2PcYzn8eYBxy09WJS3c8tCVz7ZYK3DS0/KRSygowA85lPvpwCbumpJS2a13oZHCWFJ9cSG0BrXFi
CImqhMvo1xazX/z87bxLU3AKnlYwkq4DGoBwPBb5dEVf1ExpXvhtkJBHYKimstI777itT6FZKWFV
CEqKBIZszKnTXxdggVEOR9jF4jjsX9g9SGeZvo5hMw4VmBN61QHUM0kS5jzrdcTfOwnIns5Dezt9
WWcm48T1Z+EyZDdX80ZL7j0Kh2u3R70vXHI4c2U9U4atjQENvVAy/bgJlFvE3odzghST54igLIJm
6vx9mcEQ7m81IwbbOSBEnDJ0Y3e5MAn9Gric5KBHI3Pax0u4wD33JNhxy3Ztqwt2S/ystIvSKBfO
OFQ1Oht1J/5Ib05SYVPY3dIeAvWXU7TmVMOvq1kC+ktJb6ow5+TEe1kvw8Ap1FsGgFqfZz9eSLPd
LQiOQRsuJHTReaiCewHvvriF0DIdFmPpgsd8/gMYOK1CvaUkqWxp0vXkA505TnkcIrW13N9uSIbe
nH+090DOdViYbrec/95vTaZGU7ormOM7Jsg+m+JnKzjG9Ja8ay4adT8FhaolyzKSvIugak8QKGbS
tM7n6sbOyBhnwkBGuc9YGbDeLWWyW6VV5Di+WirKNixs1tsjDEYLtp3aZNjfuuxTwa8RYs3+PYNU
+azY/RrQSt7gU59WPBDyyRRsd9cIjhZ1RrqpAUM5y7pskghTfpjTOebHA8/yoq1d4OdtpHWc9UOj
g4VpL0Zs1k8LOt1Ysz+reuPRkCIYqyLCKHG33C14WqVXRpjFE3k/kTIJsJs2z4Z8Jf5W5M2PHcXF
3FKfvlLtf2pIRT5ErSbsEMP4Vl+ydMMLrNNLQ5ObFO4AEdFBoRdfMWtz8H5dYHVyF/ijX8+rdlZH
roGmQ59r5dNO6wWJ0DkUHgiw0eqef2OmQPSYbk8BW3GHlbG5SIhkwg+oCmvmSD2hfetTq8I2yZX8
qHC4k4wfiB69Lnv/NV61eQLSunefB5PR2EhmQQFN9dPY2PaDSC4CAtfiv8faaxEgk3gyygv88d7D
n3XwCR3ymnIGvxmG8g1Hv0MWtgtASMaOJgl/gEINBw4vWhq2PbpmwSs6NJBfGCdM+HFTmbpDARQc
XwBqxZ1kTec2tI3MCiKhL4QDUqLFEoy58tFpskuYkNSzCHT5KtdSRn+HBGDUJo6UiAogod/hn/9z
ig6cW/+qNjBBiTkTh3hC7P/Soiuoflf/SEacaujss/DLST3+GTB5+hvWsw7dFqVWryYpzep5ij1x
dHURFTTZ9y0fp6huSII72kAa1OZnspzTrDxp05CMfamaA6JLofTXZrCbnqUnEtCcLw+cR7/RsDHP
0fOhhUSzKDfGbAi+CQGB6aQeVN6j7Wt/pLZekSkcBBl8Pdjj/XX3TrKogyv3NhMXNl8wqFpc4u55
qNTcbdaeD4R6916gvcyg71iU9yrIp8pfo6wfeadbmVZW1k1RxsU0DfbuAd5w02AsK6kiV7Fm+vbb
Rq/GcPplJEncKU7a/Omu8s3lmL6HGkn6vORg4H8hf8yALqG5xLanbjo/NpAloauA+9iB9ue/Pe2l
v/7/8U41yc4wt2HiafQU1aUIVHqchg7mSBadB6Hlrd6g++ADTgXpSozhQjxif02fI9iCHFAenfyM
gGgS94Yg3I0JVJQvaxbQr6Ul9piA08RpbGU0wBRHNPm0qb8wUpYMffBJUsSCcna8FscrtQGi9kII
1qu+i2iVGhbn6kGTTBddYuUAP3LLptJE0/PjLQfswAK8U+pl/pIs8oJ8d/2zRdntNyQolEg5EbzJ
BXUtrjFYG/utbxODzAWWBhM1IVxuommVvrfvGRsivj53PdJe3GuB5c46FhS/o6/rkjrnT89cmJnU
rHa/Kx7zhOaL1qWgHpxh71kWWt0pTYKp6ki8goXDyOGr7ChZHV9ysEiKYK4SbBcYUp6v74OS6kRT
/6LuzJjPSz+2FPXB+YdKxumJALTjMHHZHKibjlmQAstB240JiTGpofkAyRQkg25VCeIdXbLBrGMo
aHjvVkNyH9eXDV+kKsn3EllrJTJf/E8rYksf1Z8eO03Q8ZGnG4o3GEc23nZOCa1St/Bp2kpbtAMh
AEIgl0MLRfz77eH3FG2xCMhEQTYpHvc4UHgK5Qo56BKmMPn0mkbRnQ/4iXoAdaji0s9kN57FCEtp
0ANuhy3Qn0hGmNt131A4QDTxO0tUz6TwiN2GjHTKoVsqOGOglXj9mbns1+VrSsKpDETfXjmUYoNn
Rjt/viMszLJfZqufPuGFTtXaDnYyBnNBbcjoqUG2EcEL/gCB6XxlEuc9A79xX7EtcJXB97D9nsxj
kyMnNLXP/Sb7hqgzI00XpTpwMLkFdL4kidrJAeug6uzv2Gi9liInkQO+J6lm2HvzNrl419WZEx78
FKPfVJQ6S1cSYsJoe53vwIj9dehh/c1K3TbslnOrGAQEnnc1NMaIcsV6L1Jg+/TbGMbycwgzIXna
5xAEfutTemLfLk2BNLZsztkI1lJWQXDfucCpl0aCJUUvu/En15j5fPD6vvlpkhaQPTd0tdDusBmj
pigx3PX/2QViWEhpJilYiBPcMoT0hyfxQ+/dvAHbMh5l6t0GSi2Ll3/qtzP7eC/lGhhuf+4jM5PM
tiYfpKkBsvcpH4L9hNngT4H92GSXR04mOSfJeyYXBGs+AkCWTSmE8LozCE2X/jEKRt7CsKGozYS7
lI08qT3yXYDpNCKq0E6aCDkIcLQ1KJYyUXbGWzd11Q95zt+iqZGaf3WpfRYs3O3zr/CYzcSN4w5N
Lumwn1lJMrkImboRs+TiHkImdfq9R8CZv88opvuIEKpHqzmA7NwO6w106mnhHD+lWDMsze1lu4Y0
LvKYpnXdK8okj1S6CsNJ6ZVOt9x6V7lAeezxPSY6VuzIz8n9UavTAT8ILIoS9sK4BVlKbVeSDvJH
YSSXcUiM7G1DYz/g3WxaPd/jIvLSl6vgtdUrO7jdTCKyGVconhCJinFLoW3b7lxtDkRFzq6dxtcu
l8k3/zP2133ySU/mPIRLeBA05315YomDpsjQXCX/e2NGwDNKV6EPcMEJuPgaZd5f/OhMXFBCQk12
spdCn/rHYlbhp+8KU3C6bprmjM25IdYS7hPFpN17owPTIEZfviUnYhsW9r4MDS+Aapb77AU6cqPl
H+lZZ/sDNWqPDn1tlqwcPLpcJZeB5B0XDjxCFAuyPWJdk39vCg/i/WKjx0r+m9G/cuqlE0k9b5SJ
O6rMjfnUyULv7GJcSziJOx/DEtFw3yyX4JXUBYlqu7rYY0312jKO3XCdk6gvKxfGIZp2sSDKNTkk
zq7SU3peOzEpxPIbm8PkrGhrFcLOGiG25X7ieDwTdRBVglIxZZMn0b/tz3hkTEkuvl/VK85M31JO
qa2BFVvnF9xsfklPjdkNY8Vz8hIwU5K7DQX8VQDOGb/EVH7NxAx/FLTO52ydHCAMBAG4J84K51Fx
HJP0dBlB9xirWq0WPcdZQUdS0BifgZmrcqhlmxCLa2JY5wvLPcPKfrMW9oXt29yqTDhjDaCM+knB
0Cowo2iYYeMloXaeDC7YNbgfxp7EzV4CE6DFdhV6Js/xpAIZd3ktARdcJcej1eOzSlRuVfpAvXS6
oXbUbsm/vi+Zni3J9I/lxOFEwXz0e/LATeeEXgEmVnh+WFFKMiYCcxBOneVipfjbPrHbgd63XN+N
z+MkyQmAcCaC5fVDWRDhlG43pGANM2NIf56XRcG6OBD8qdWXnwBoMMOlx19ZiyyhhBaNbWtyUW0V
I/trlzVqLg86fEFvpfhBQjnObA1ZTab2fsI+Wy64HAY1v6Es84DDKsm6Q5fgJORZzwv1/MAL3Zmy
EVq24xFt7jdU7ohRUH0E68OsHbWu4FUq7okoIg8vs0GdXG4Is7X+08aEHGGOjJiM9+eb+HGnbVHK
kvRC3Zpo42nGcTvuggzq5HmtAERZVlojTABiRtylWmDRj4F+cTvViC+mO0zLfgf3Lkhr2Gs6stCh
YijvSZMOA8DfFx0gbkWhXGZF+x64CtPE20mx+54qcLSVZwelyKJ/Qj+3mBfzdZoaCka19AUgGDTr
k1/SE7luNMjt5tX4Dbtqtp6Ui9+vHdeeN5PZKDhnd3ZfFNPomePoydJ4CDiometLhegW3OUs3zBv
pWPw91kWUtspx3KKTigJ55OoZW4tbYmDwyhw4bs2edsPv13SyI7NMSFPY006PV481U/c27VR94Av
KjcFNTDAzt51GEQ510KprDshs8OyJZO1sYygTUHl2HSuheJLfE/n/dEgCDuJ/EMglE7FgZx5cLcP
alNwnq9Wr1ZwA5ZtVvDYWVR7HCmBCcaBOrTz2NTIzKfdrmdTucsyvfwCO9TcK8iJIrswb+FAZxYI
JBF5Lhw033EYSry3Zy3OPw9kVfDqJ8IPgaVjEcpXd3Hvp/o3dOY3I77vmTRIPhCxsxyHBMebzB4e
xoMUwej+PSbdgUAv+i6LrSSMC+Op+VnpWbnb228BPmMsCwMXYSLXdJL5YjcbEL6CcrwOVu9hHCmp
TUWfYYrTQ8UbiVYVcqIjaw0mntegkpL+7Bb+zb83t4fORzt61Gldg7WYKW8GCk7tApXZxJEoYzbf
o9BhBqXtVkcC28Tvfzjs+rlrbjjokRa0OHnSpSP2beQFCTYaeGmi9kz13Wiq6Fvqj3U5uRro+db+
it5QspA5lqpQo1K2J7HG8n2EUQvcLM/Q+KRwNWA2qkN+I3yo1ORMnuzT5+AEhvzkxzJpl0LC4jAz
KwVxM7zcqc2HJ0kpFGVNeYRmB6A08DY+MpkI0PZ9aQCTAkj3gW3vbwl6lw0JAIxI9+uFKH3gEEPx
tbavrQaKbJkxoku33lcH+s+u0pIHnu808kVa7RsFwj02PD7riStcrqETZnUh2V50wphGSwfVqlo4
Mfv0/wnXzr9HFIn3yqlrGIERNTK7LrviaGC7kZ2nFnMte6HzbLElVSW7cb0NNV8E6dlaXDLQTzQn
gxfKacKJxUrwf7Zft/IAQ0vjN15hzm5M7kdVHPaFh3Iy9mAEwleEMzTqETsohqFopcxix8n4Sez1
wdk9MTF/ufGiRtDA6iyll1VJtJFOSE4uHaZfDsHyO7Jw3SPeOr2H6daWVCcDEZq4hLNgq55jvM9k
tBgSCtiNgNQh4jZrVuLEoQYwBqSyloVN7YmbiH6HzNpxFVmB8d8Hnl2oW0JR9YvikB4Njg/LjZHG
Tlw0gkO9AjwuAl8Gkq/qyhPjt2X2tHUkwsj1sBYvoWyw1BfRbD890MSmG/ZZIgb7M9ZGL7WhgWV5
rE4o0SyeekEED33C+dy4Tup6xIIYPLTjKHVBbDH4vQPLXi9igaRXxc/jZ4o/obR3V0HeiBtuwPR5
zpCQz/zrOVtPxghco19CEY5fCzSd+4Z0LQVlYMwsKSw3xOQuh6O3Ktnjb5RHeQ4YQXoaph3HzteA
4wIWwowTXOgnqmjvw7l9/lmlsR6yzN1ZuLRxHwx3FvX9oi1bt3zBY4VZaBPq/es5y0hxWTSeXjKH
IOfJMkap29p4sHRmfs6te8lfTZbSYHnZQSxvcQdLo/hwtnQoDcrBU7moCT/1FHd3y56usXYz0L1m
VM69o7B+BWGyLbPJwihdDlz6R8nxv9bXBNviNtDkGpgOOoQScuPJOU/x37kzDgamnsd9i4FJ23ly
Qukpgw9rrhzl7NY0ZkQbxkIlPrTBPsPRGZPccNV5KBV71VuQXFhjzk5WGoyFABQ08wJZwuyH4ni4
m5rR7AGTSVMPUrp32pyZAKMrtnHqXKNjLaNg2kudWRE/1NWyCrXuiSAbq3pyFbwOq5zN+xqJ+5L4
UeghK0Rm9CGpgg6SU+0RWVLDfPoIHxWVIrCpK1GnYK6usTijjc7XM+Y6FokZULLuZZ70HWLEzSB8
kJobACDkrNHtadcd8R6E7SK+0EHQaz4fcQ934SZWhC1+DkgblgW0Bd+NLTqk21/rATc6ItbWJt0u
yUAtOS2RZS8vV8OebmD5oZTisfIH6MtIMrzqN+8DITG4o2LhcSO1QWGmdnK5CJY/EFkP2KiWy3q3
pmA48si5kbLodepth9y+j4BRVbDEq1ciOOVHQLU3W6aCczrof9pykncDeXnLSLaoECdF+k2OPnxs
7SIykmcNSZZGO5mtRM9uT+SIRrT7WyHBbnicC7Ef5DiT0p2hgqWrbdKkrXRN7xfMF/6/++NUx5AL
U9GwWMcB801zo8aQRkRTiARbOVHR2qi/VuRfAJlt/x1XN3Pkz8vVxcjUxmG5gotpgkiI1EVW4lqb
BtIepKWfTpRpMsn+HVNv5q6pjNP+NUcJF2YQF+gwM1Uolagy+53cFYew/nJ9/QWP0BjNIUiEGINO
wo9fqPXd7tDLBtl6cP1zpxwr8h3Jc10xPgecRC9ZdnJ+WQCAdfEVOnXiytWh039WddVcXq/oUqDr
MV/NkqkdOS+60Z8Rj+yxjGgrsMrN5jsgTr1K0gtYQMLjVFD3EEcpniRTaLZ3Jkjg/xujOv84xh8A
dCPrCEtYQz81xgF+gdePqktVa9b0ci6bK+xxwYxvRUDiiciNTvlXnNxXIZY6M9meypawkEXErFyL
GcqUW++9PEgr5SY8xGr8LdlYkLoiaZRPJjpGbSlIN3oNNfLMfkzP5RiUVKafz8hYyZDYYa2Pxjel
fmBN+yj5f2PkdA3Myfl1eBIgk2q1pc+2P4sVP2kgLH0CZNuxuGKgssnZ5BniG6/pEj6OF1FrKy9h
Kko+0QC/MxqQYaTganrVpU2XCa45eDJoUDyZZFBstWMFLZs/LDfwOD1/WFQq/5A5uCM3TxH8SM9x
kJwoV/0a7QgLXDglOt0WZgkyjDb3Irwoc69SKyQh8ax/oVCnC35UTqS8zNwsP3zUqLuYdsRSid+l
6mSibEcyPIqE90oo3OEEv5oRhxeFOu33QNqXfZSL+b3tGaxKiLb2X/QbD6zKjP4xGeHzHfayyB9m
6OVFCS3NOCTuFc1V7IigFKLTZmfazCiBLR3u9PSb8z2lQA3H4GCh0xl+JcKslETmrNCfYekniUdX
2pqTojYP07ymDl302/m8dD1ntC6N8Hy1zrVNbBbdtgxWmTvZw+7vUh5RBEuACwSFWU1pgCfPAxkh
fSTnqGkdVSqBZX+Rl2OPEtuORPc8foxVkXTN3CCRZTehxTG1yvHtCduxIKCDsgomscvk+/7ELwUa
sv78BJBPYKnHXU2iMCvEUC6gs2tYlxfN/uJFzGVOm4d3RIKJtUM+KecRfb42yg8FW7knl6nqMMLh
ugiBf7Bn+dSCNzJdv6D/m7OtVhhIKgVeeez6VKocGOEZJ+U/eExx9JA7k1OkaTHBHHLOimC9YaG/
2uXyTDNK9fkuY54VQShyf62VkGksymCE27/bkAvHwy+f5l6ZEgA8JJD7217f9GSkHOuxWqL9ejrV
AGMSHc1IqA7bK4PaoWhIbpybNAX5zbofH5X0a2XWX/Lz3efak3yCOMyEEyK/VcXnFj9IVYXgzusb
ituVTyf6u7f9E1GsQxSp05CxQp5URTGj/Mn2ha9BcYwDKjtRJBWzWSgQaeNZ0ra5NGY7R2lGzylL
b0A8ugqCHiRrTh8pVFnl1aBoZ01NS1UCAoQaD+Ex/gzW3WLNM+IuiKhJC4u/eZuiVLxkTixbzgY9
l91TpVLmEcWtlvu7SBEag3hIRPgKuvJnYI1Ywy657smSf+s08GeqJLUuBKlcfO7OIiOjX4PRf56R
NrHAbVMJ0TqudPq+jBjpl30/4wsaZlIt1j0Fo05CeA7sV4uB33+rtNnQXlCj48NP2KhVj4rgjwOr
Fyuc5b5QgGXLHEusI2f882Zaq+s5RKb9ZljVcqhlJyedUw0f9utJRqvwI86rs9pPQnAupReNZahk
d3bT6BNIfv9CMyhtS21RPmWNUZqhIlGakn+pjx5l4tYzx6JhoJKM+XXWAazd7+9WCLXn/HJbiONq
QPKuJiwyh0BI5NjgCLUICt6va9aUG8KQ1YcDmohO8WSJTLpvf1AehOOmKhZzMVhpdlyZEyjD40ak
BCOcRJ4kTaO/GjwZHjSxi02ePNGf/tyl0bjU1+Z7XYpUz5+4XNem477z0+4raLSvws5eLM45Bo+P
HH5emHBdO4t9kMRXdV8Ku1LSKFnNTBuzSfr0EqR9f5EgNOOfSiCeO7pw1RsskcQvH8+6HH35+UAF
bD7wkABdKDZwCFU3WNvsa0Rv0bAUYPAFQHOtYS9GXvwb5v3dqHfjJX/CC4JcqHgofxhlSMazTwVc
qLXnLQMYxczthb2cm/PTOfY9194L1NtjyaDg/ZoD8KjNmPDo9j0cEmb/qGmJdPpKXUg1x4LS8GNV
wMpvZdbCPO4TnbZmpqNr8lmjd36yhWLiZWj7y3dg1SaRv1QjfBkTKuKNYiKhODGANXNXI3FPzGl0
gyZkCxVOKHstpSle3swo2tIwoMOwAMFYFNBZXqbaOGV4C2APn81eT8/qMaZfYGm1K9cyS3q7tp5M
b6thd5FJnDBSB9nFxDADCH42HDlzSp4QATIRp/dLmIUez5ghBxCRnjCJQmRUZng92udQLCCxWWJg
sDJSpPIRrhQSlIRdy+Oo6HUs1uzRxNv+O3zhNXW8SbTL86lzT0gBOwoDwBIQv+Eba/+vJGPFuRcY
pPzyAcy/ZqgUjHFfDOWd0T5ctiJ3l5x2CCjQghbvB594kR4LyEbJypF1zZlu+/rY4RmnNvGBSe0Q
Q6RzuoBS5+9XHH9iFciBs+cLO79Tv/b2Hd2tHmKXqTLTqCZY1n+e7v3gSU/4TA7zfgXzvzrnrrbf
N4KK10YS6sq3uwt7NUmm5pg538d1tfl9si0asIW89ivgj+idmVkGi7jqd8skOaMADB4fnou94eiz
7ATGHh+65ThSb0ht/GDrzYFGcJJXBx4NjVjTW/QoMYZlV1+8yux24oSmsFrs+aBnMloP3bOjP11Z
o3QRZZXgxZXrw+ygb9ozBqFyEYfL1zjyu3m5EK5X/EYx3cspcfXiVFwzL85zbDoiQ6HC44MwJa5w
WillRd1h1Tr+1m26bMPo3y/yvY9uR7WM1RVPQknPwOeuLebShUT0VTfLei8dZE3T7aCsaYRxbq5R
Pz1h1UxYITvbKzmbTvYXRyCz9qcg/Wd/ItpylMdkf/CtXGl2Y054q6LR8q2l9qhWycKIZGkqlFxU
aJbM3Meekxm9BpONaSHo5gZ3zRgnIjIVA6oGDEQMHnf+X/PBlD4btLpmYIOAqBZWKhenC+bjwDln
zIGLY/s0t+v+cuPfM4fopZLnxJzcLGAkIZjX2lcLpkQN6VMEmSuPjf9xGZRrY5T1O16GXiTUzJ3c
IR8BE9uyraNMSMOXIyNK2bpWa17fzsaO19WUfJY7471LAs+vdC4C2zmQ9VKxaXiiOz/OdAe/1ybA
R2oVSovKMzmvQpyB8MuUl/nTjyOrKrGxldGhzWBSHSoXKBos2uRBiMNge/6veX2LlywUU1jweRba
70HrvXQEERQ/kv+kNTiZhqQae9clDLJgQijy1KO9Tav6I2T64kUu8sx5cB9DsFgX/IJtBOoBgj0g
kcUnQvQuajzT9Ijv+YdzzVHw8NN6SZQTYmunhv5kDhg2o0eh5LcDc9fDp0641ax/0W4YjQ/rvP3a
63fx+J632yP1E+y7UhCMY+p6UCYQYNC2pD6N0sNUWIRwcZSZ7gzmfXtfRGU9I8gx2oSo3P3JpaWS
4i7b8C5LYYqN4s380fSr/ELm9762wxQuFb3OQV35CYrGfZae75wlVaYMdVg0wkUshAwExcwfiyWC
93kC7p4vuX6GZ3U1c2uJiTvKW6nTLTKQRIZj2ZL4beaSqxcyp30JDT2iRP3I/sZh0emTmjbavsYr
fsvDgH0HXkrOF0l0xk4/ghxE7i56nTO6J2s90TF3BvbztnkrpcaA2ZuSajvV3robTc6dZYPaRk0x
jtL9CNFhMJflP3l3zF8XoQXM3z0L/ez8SQ7r7PH5+Cf+1huKUYQ9QYh9Up/N38ByPEg2jnR5beYg
4hMZ6CbxcqC6Hv1N+7jKN1haKib05kiLmW2v87EDiE1aoLDUfn6B8iNseEK44M8jM9z90Vo19LYh
UxMSEVg5/LB7fMnJHvEvhwsdrUAZj+ju22zWEQuQNgcjQST8B8Nuuc5ejj/YUqUNhVUuRq3iV7ki
Tp0XUZifa++4Il0dfnUmDqYnFRwmf6S3c6HciyYm1q1AxPEA6fYeQlEnudF6OZQHYlSboDBn+LHQ
3aPBjg1B/Y7UZWyFk48v2FL1R10yjMNysFAAzdiw/GmBXXr61iwwEqLAoPX9+UndkX/d5IPOzl+t
5g5f3ZgVuestK1pinfrD2sO6qQogUytl1uKigZ1jAEw23/UN8rJXZxUhK1yFl+m3pMGkHOhXYduY
5rDTbWh4WlNsyZbrbaQEoughG5aaMn6+cib5bfBN8AHo72tcmFatoTJSjTgxAi54sXX/Meel/TBN
PHdD5WjlE0Qz1VNtFcdTBBQPiczJXMMi+eVCDWywVOOBXXaopPleEiwjFGo4OY9aNUFi5kjIYp7g
NVe8gvjzku5/g7S2LpdaNywl22Pak8l0BsgsrtW3ohF9qCTwmfouPpiVY2cQwXpNYLNYAU0fCAUl
7pXXBS6JmT1owV2QQo4pBewwlEzcHuhmUW9j8uPOaK+MLIXvsQtY/DsGXUnjRFoAH35ILagdMeHz
yE4XXQaDzgMpIFIGXsB6Uz9CYheIqhNLBRe7PoowvBjodihTlcq/6cYoSCnxjTvi/b1xuvJMZ18o
OW1h8AFQDSf1CgAxccPrVMNfC0uOH8r5X/kFdf/iTh3KkUCyPqNykz91ZVrwj5LmAUQAUKCJrNsT
I+nn+1UmFxMZl8qYyuqCfPiCRIQkbb7fczPBm7NFAnJ4Kn+UV+MsswMK1ltqIIn4/WhHZ83zuxto
rtnmmVEEOXbt1Rdp1yF5NGPexZwvl8mYLrb6z9+zL99+09IA++Hl+Wxx/BRXFMWX0FP/pvVInoGO
DOgh1GOm0E1Cr/XLyww8M+rT/nBYO6FA5TcNE9EVX725w06r29u1z7VT5tMV4qGgbcAokPcuUqPd
UeA++H/FCoiFPaXg3InftV1b1HYGsPbCUQv+ToG6YDco1Q/KFBlrs6F0A7qezumPz4wwamjLE/l5
tNViLWwpy48r2QmSpIxZKJhzeMLESrypI7l5jbprgQe0SAO6iNSa2PF4wRxLYjrbSkN9q4OUo8qc
wCwqtkHeO0YoqCFL2szpSL1W0MCyKko64p44zQhDT5hNoT/OojxMYkJc7v2gfxYhlnNvjZxmzs76
DyUo513FTvKA0S/vSTtcZidI7Cv92pTA1/e9T8XJ7UYJeQmRtBSg/G59LQ2JgplUbTmx9qmt8nlo
OYnQhuTocVSGK/QQwC1+tBZratZDXaFES45ByUFmCAY4j7mrTsNoP+lhBzyq3zfFPlvZ3Cdu0Lqz
g4rR/nQINhZEKMGk0wzDLRKpYJBMHyU7oFiOxYUw3AOeKhjUitpSwCFdOu2bBblMo+RBlai7xW1K
Gtw8gcNxBX0xdoaSfgdgLrMcjQziaNEiKna1HW5iDlOqOEJuH2j8iQx4uXg//+HqXT6C6jdZftpZ
zYQ3uEXpWuYvBHqI4P6JdGAcxgDQ4y60sBb9dtTPHc+M0NerxBv8prHELx2d2PNphyBlGntUNQNy
9VL9PPLyT6bmTKl4DMjzjqqQVdxF3JgZrkwFBiMiDdvoU+x8LCOM1brTqQG84HZnue7IA0e8cept
KjZ07kGWJPCrKUx80lzjX2xd81apqqXU3i1bpArIknViTWfA9Upm4W2FRflFFfx8MxrdmwXs9Y3t
WU/AqABjGU/3KYUTSlMnozrHEedQdmB73JNn/gsowLxaHZnU0w3fglyTBfHX6xyaT9S8KYf/Jl5X
QbCJE6ceJeaEk9or+PXE+IthV5fk0y/JyL2kFlPPr969kDs85CST4+UAy9gHNh5TFMqZKy8Lkfhp
ctP7/guLJN4Y0t+hskm+ZAJ2MCjP1pd5ULxrp7CeZO41YwocxgpP08mMmxCTKzJXNxaWwxbd3c4F
5TKFL0VQUclxJPEn2H+iIXFcj6OIeVX0M6j9FwTsC+lx3y0tvpOmdnvlj4nDHTbsuS68qlPdiXoB
OeqHX/Wj+eHCG+O6f5i/AwDFvUoGZVos8Sv8VLFIrS9auIrz5MzaM+2TvUVVKeDPaQ73oi4lHRMU
F5jL5DQkjDslCxSfd18CwlajR7qz6trVpxEnZPvlS03S1uabj8tsSEfsfXc5j4NOoWqGUlmQ9n1G
avWxb81rNnCmm/ySjQkYE0nwwEEEz1PqJmGKT4m7eYsVWWTb5AT3zYlPoT3pd/A351zaE2mdqTm9
19V+WUv2NSlKmivfH63figXSFFNCJHrVqbY9oQD9bbypt6sOawnfimUllv9ThgSyAbzfF/LOhOFN
UxTuhmx5+0nKaWrv4I87LLTPEv887lcE9hDoNSNnM/b3TQVyNumP6W84KNVmQsAC1d6HQZ/xGHaR
4vxhmw8qhiL00USKFg4O/j/9eW2ZRQ8J2gS1iYrDsxjJKuDNPoxaHBiNSn/wCveMM7blaxyH3+Fu
8/0//tunJS/6Ki0BExtyVW91iQt08SbWfw3IeFOqZUDTUk4PJSnykQf1Zj6gPsXgKE0LYIXjC7f4
IoQlahcMY9aOpXKeyVqL28frm1MT+M0l53wv6yc2CRM+DHjgE1KvlMPXtgnq3oTwyqpEy2LcHMdA
BbBZYi+fULMjqF6aGONqFs/sQhqmmaqbSD5fFnTmW7Mms8MmRdMNsoMz5W4SBjscQkhC3Z0CfbjO
DhPLLe19TjEJWxKIh94rTO9a1kcFzW4RvzadfiBvyWBBWj7M9pPSYD8/Bu5iEBABVjzLO0nXnAX/
U7x+8rWS9nZ0jwsUGpnaZlknChVQ/ETTXm+yhuodEu+zTaImDrPAfzPEmfpLJrlfOYT1/nLI2eVp
XD5+niu4OiWryJq55Ay31ChRAMrvmumcJdyojWE5pAIGLQsBOAEQjNLYr5p6MwOMcUdGCSofwFbv
BGr0fLiMy1EhWFri8EgFsz8iDapK7VvHI2TJthry6A9B624LGPty++0K1n6VOJMo2XKvjWapZV+z
p1ze8vjOOxGjhBjfpuqC2t4KYHidg6RV7hCRvRGu8a0DIWGuWYHkfdPHt+CyrwYU4J1Zlpt9V1tL
aqlSxw7FvMNdf2OsQ4XkcG0T04+um94p7l5J95ehCHTXrNmSUOZbK1n6KpUIeildkAUa9lSjKKyF
FvfvkJBKZl607gIG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mqMMwuwihGR6UeYKQj/60B2AWf9clX8+kFsa2isPlH6+2kxLIuDt7Rog5tz/0lfUbeoT+pRbl+FK
EFuPUDT9UA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
GQNkFBuWBHbpOmzURG02aJpZ7XKog6XNa8zAE2eQ3xj6PMygKXnkH5nn5URP8M9zfRVrWMk/ENZe
OrfxqKkMYOO2BHpEVUo3Bysl8N94qsiFvMaZpx1aJs3h44WmFkcc5XmHHZzhuvDZMlvkL+NyI0Po
kVi/UVZXCA0LAFo+kas=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rF+726hcpcVvxumQD/VPbCg8OFhPAwhb+Ul/5yt3t/Y1dDwZTrWppNHnLd7vmAtAYPyIF9pMUFUi
G3mui52lmlfF3iqJ/GdKjDzuLAy8lvBhpXuTmK+qQHV7eIdpy0vjzZmPRLup1PQKZeB0M8XENMdB
GkErIZrb4Ee0++t6GDvZKJmokpnSxRpxXqwd3YL+vn+wDME5+EIu3CiA/RlyOJ702F5TvIno7XYn
GZWlK5VFOi4ZO7mokHWasx0j7y2kCik+7zlGTZRSBPLUHxfSfUScQU768U9/S8TWH46Pcc90rek0
BlXcDEWGA0+dPlrMyZBFJ1B7DaJImvasBbrAtQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
x1gF98cy/K84iVqcjCIppYzn0b7EKIDTECh3SrVpndzv98JZp5lbsMBz14Yww8sb3Izl6j0UQ00A
FlIUfOrZq6kV0QyUREmP9Cvgb5uZpeox0nZ9ALThxHbxA/2BuwpdefU1+2M/Jku2Tf+qiFX5nV/y
iw2ehkDuNOx/ZSvhRaU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WBR3rarbr8o9Z9/IjwYqKM1+Ju6cRZUMAYs/BMJgccT/rO8QU6q0PGwSGVFASfTroNwC9xuaU9WW
lzzoJsBD5UNJ83X3kRSkSYOGUlhb2hWBwTp3B8ME7zpu9Li21BSn0JVbUlxJpJYJM5cJO8yY7A0N
5tps9qrfQRpmM3Rpql6m2gzaCGTNKTzHMsYX3RuOxZqVwSZb6QmqO3wbYEeI3fc/5q5gNCK1GD5Z
JwpFNxuUNr3JLMJpwtYHP+DUulxMruMaRvupFJQOWjMj0ihk6TZNl2dHMGLvwFop4foQXoFL3jKW
auopUbvx1BRfHytRSc6XV99/k3rS8+MlNYs5rg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13920)
`protect data_block
IUy5vHafcKg6rErwcdt6Se1WqHGyjVk3DQ3vb/5hCTC/XrHxbqa8oGcP+at55+tDco5ik5o6UzQY
5/tVjPJDIEjPt2ztj3RZvjbcexdmpk45mTlfz27MOR3dWQ/3z1WlhTQwFu+GWK2WLGp83Ti1S/1p
KbrmMTp3QsTSsqenyYy7l+DV7b/a0tcD7i9r1R4kAxQ3ma5xVphOBYbMNzJuWHyfdcchnk41YZfY
xJNrTyAgItXz/eITABo8QVEpIw9krRPiwIOiPg3w58oJHYSPocoh+MBtBxTrlQ7D/2x44b7vsZ6d
6yr47BKve4z7tVjgSU+UA/4P1EHuCCP/Id9g/xLTz8drT4KRjVPUW4N+YDcnennUfUO5U9VZVq6+
+H9MnA4FzsMt9+4BGBi1AsH5l3o0nSS4/M/EnwkTj2BsglY6AchVBL1HnjcT99hiEf1ImHneguIh
QFjcplBcDcNJILs2ZJhiP9U8+oZSqsG9993R6XoTcMB6aXXRbZRaW0JOsLrkjqwRUVDjfxQXhJGk
/HzmoHLNgFT5Ud23xTwREVUF/DJva/gVQEht8alcPaBtYhlKclwi1AqW4U2+qS0/SUXItrOPBqkB
RO3HuoE08taiguK+sJsRR4I/Um/uBoTHE4FG2TeavksyJgvIrj6Ae5hEzchq70PjL5Tn+roIMIxU
bJpgoeaWhrnRbD8073a/EIKUXb5956ecDPdoTlMHVtNVLtZFhvarMvhoGNvHHnF1EkkOCd2xZbUm
MEQl3vOskD/gSbsVG22DlShPPeio6ZhFQuHqcJ49zVOra8RTBKtSOi8m9Rx2D9tdUnVaR59ZKARq
CoqGv+WnlvLC2LVAdiMmipMgY2xkVfLsXI8eWH3363zBfluysGRiGz0DI6v4uyUmU641pGM3Xpsd
DtAD5mVxijOaHeGtIrCTTTZ6QkLQf37FBsaGPKYCQs/XV2zx3gZ6+iQ6bxZh2jO9x4ozk20LWqUk
kI2V6OSZ4MyhFwpnROEjSGmOw+XCBCFzUX6Now0IFkamRR9o1tl6QjqURTVQywh16yDPJGcRKt0M
Tn1Gx3CmpEFAaEUnhYyHk095ATiUKDFONvgMBafLZrTotI9h6dpcpZt8qr59S8a8M0ZZ2M4ICczp
qSV0T0RIdtAdgfpC7vCsMOxxp/KQuCJZaFAKKDr0g8Jg1xaTrZHq09zuJ2zdBZXsZD5/jjc2U8v3
6Kaw8eycGqaNEawFt9a3fAP3RCQDW9cga3rIDSyn9pdI8FnlPYBg+UEIs8uto5gxgBbTdpBBdppE
fiQu1NhMrMtULKDlqHM+QbArqPLhR25+J8MGOSxP/7Z2pA0v8k1r8NMLzWl0qbQ8bx8C2KncvZyJ
JxdXJJ9wHWnsxFdTzj//th962KZXoSKU2zvK8OwGeqhaXHCmNnKsfNukyNXhAyxCsSg0xwpRQDME
krUZUjWhbwf5JVwx+YzNMCoLI10/9F7lumRKAhW2KbH9JKVSY58eFVKV6LDy9kQGjwdG/wPoWiaj
gyuLJWUPgJlBmOo4deOFtdrhBMLPV2NbNcYay4GKXyjHI+5gePrPL2WqNH7rZoXCN8Mlj6GneRYT
OE31IiBubptXbdne9oY3EdMlXFaKImWeffabRWQaBYj+x3Kn5dtzkOV1hvekj4PzbW79VjwCqxlj
1GaKUpyMpY5k0vB5XDiHO2HXq+pQyfKhtny9UBEUp7NIKSq1COvk2wAGl6zwHoR7PpbkJOlW7dlb
IqOSMBowWvkvilry/xiYOPhczTRmMjUX88M0RFFtYX2mFVfsi+PLdhLJRzn6RLyVD+Fg8Bm44Cqk
XCWp1sxS43pb1c0DNPBATzTtcNuYmmziFxQk18uO1fqOKtmgbeERrOiSzaq403G1R8GbVZ+XsbBE
t528S1+UMxK1YVmhSOaNvjnb7EVX5tK37xNpN/OYbJP1fPqrBQTn5/7JWHsVfTEgzjXVbJ5ocaG/
7ul31b/FKOzicLlync7Lmo1HszdSLx5AeNbIWyJAZWW/5f0s2+6kd/SDCuC+UUoxrVZh2RT90rvB
fLrGWz4v2HMYHa4wjKfnwRXFY7iJksacNkkauXAIkD2CwZErhhi2co+Rp04C0bVpR3aVQ/h3CCOM
kgEstHEAvCefLPqdO9OQB3uZxPfzotnxtrYl7s4k7YGTJX3z8a5cd0oNxpib1ZqI9Z1C8DSNxZGA
gx7/y5iOKlXznx6wAxujWey7fjv5yc3Kl2UBsTedlO4Af9njL55pQGZMNTEDXuHryThhJdSL8aZC
gUM73H7jPMVo1gLd7j3LLM6F1TNXMFI3t2pGtkTVzCatQP1ZSA//NLHf9TpX94cCXRRnvahUI2K9
SFUpzmVVfsRkzX5ya2aID4qSWS9WXFfVI7Ef+iqkNIY9MgK7bxaYPzOkCCv1j3qCLFFXwvc//Pas
vigDGLkBlY2YRIwuEfwg17SWyAYF7yXtt+ZiDQW7rRYe6738yEXJzJ9s+/mE31XCowYJ4edd+6op
7H72/4aVbDrDFpvhu7Z515ylga1SBb8xYsCG0nwVoHCb/bwvVD+dG+lGL1BfF2yEAuyrHHCSqo/o
cDpOfIPDLtdsjx3w4N35ynvIeVlybaTukdm1cNvPWG74p8I3+8r/LxOz02L8lRC3H6CKbBtBb0jl
S6+ENM1LDWJ3oeYT00NVpE17CB/MdKy0g9fVUHpJsekb9zpcazoSQE73Ny+ANIRIFyDqsL7s24+2
VUyApyfsFOQmbKyx8+Xfj6X0S+SKCOzQQYzgzyMg8+h9tAC8vcBiTf5hUUnZZ69a6IuLHrdxuoxR
XkGrE7NhGKXF27shBOTwsxQNGyrubHdgzITSMv+cCUWwuyV2v4Vk7J/qQIC3K6DKorXPdXKF+9gp
BjfL/HHg9RIqAwrQN77TXDJ6+YEaoOnOl4GbW0pvV0otEHFpE20ihQO6+jNLhXuFvmyGvxSMyAxX
Lf7HJHwvjynv2uJwYs/jXWwXuP3ToKzjxjmtnrfM4kWIAxZu1BAdk3/1Tg2NH0dCbxWVsBJfQ3RL
Rb/Xehu4/FW/YiHYfCEqoPyYTtp3uM8oKa0MKl2HdwBQVJo0yYSAFD6vY2TvfcXY8WvDSQDUzDFg
+evWg8dvUmFuXeD2NZ9X3GzipY9gcYgvLczTLiD4QtYhjiFT+/TgSiRfB8hBoHWMM2/+V7SIVWNx
vwv2a48iXRmEKZ5m9jk1kNglt+aMKp28DQ4Uu883p4DpFOWU7Urfb7AYXK5YYz6K3hUiqX4rwP73
l7j6vyMfC2rTE5F3dByqMHokEsnAzzwwW/NFqBjzV2Z6pX0BxFgc4DJMfi8Og096QmptzG0bwc3+
s40V5fPf5MZwdtuSW4ZWSVmk30kEn9xJnJzAND9lnnoWb5MMqVh3ty7y7YCtR7JsZuyFfm9tEC98
Eo9I1DPFCdYG1p/EcypwXkf+frFQvaf9+K0lr7/v3pBWHlykb2tvFufN8+pD6lYwpFZvnvG5805w
Qb4WTFZNbzgi6ZhysIpHi31LMIhftcoyR1Lx36JOKEqxPjr/Wvy4ltP22vPvddxLPiMojL/0SpS4
Gjs3D36XZBS0oe1W8EnqJvVOKyFnIr6aMpsKdeWnDja0LHzXKwTRfwlrj/tSpogHFzj/ty9V8P4O
6MdirOqycsOcBpvDAU9U3VS+duc4BMV+onCK0Id6UuATVkRxctVodX6wXumH6oK3PG5PG1Dkj/pf
9ckigwRT5b0hJdb3CtN7s5cHh9EqMfjajcGxeJT1PEPKmS1q4i4gqnvgxVQN9Yo2RT1e84X/a1IE
NXY6hz8olxUqeCyy+p8uT7voAtJ2NGvv3SNiiPxSCtk8k1LC45ytunDfVe/7noMNrs0Sf+J1jC84
hhSZ1s0OfHpcmyYStlnftd044kUjtIuaIetMarjtB0sZOH3KYziCvkTDktmWMaCPi42AvfXo0kik
J8x6LEP7gd4S9JK6InzmYq4Ob5objflosl2kBqsguLo7GTxF105HBnSiJ2FmEvG2OPvk/5PJqyHL
SDNqs/xb4lCuOUWONBdByHntaZDvFts8JBr4ablhsQZ987tOZT15AYulYXSmNVguMUdl1nR+Gzcg
pnqHQThW435b76Yo252r6lt5+V4cDGLEgKPun0BNiAYJMihkY5RnCd+CutyNVfDwwqFdOacI/qom
XqGYBa4smohCaW45Ql+WLrQ46MOq7oqjsASMO1WUyoc47tCQZ1nTFDGgNJWaMS9P5PS0i0GDnm7Q
N37wMjLW2RD9CRSXc85owjtu4FIMJsPmSv143YooByxV00XitMH2iQdHgqOv0A46lzllPCfYKCau
OYUrgz3YC4teyadElu/sjP80VXAZpP/aeY608nT8GvVoNsOdy339yfz3u9I4JTUJNpSsyV8cXIEM
LQuVkUmFa548KWxeGewaroptstbM7tZPLz2hSYVHF+6chTT5aZopp70+wOFhKE3k4pvANfOUkCNA
MynbiJJctkkaYrzOeyCT+A2bE760ROR3ZVYra0ByDbQH3E7rvd1Ttza0wJEtvk4rllxkZXZa9ZMb
OoF9Tna2Aohe3WqW4CUdc3yTKUjn+n/i4mnDt30I5g3fJ/76/ktgg4m6SWd/Zjjjaaspj/A/VArx
P+1evFBnkbOAuak6ybXIKITDWVPsrYV/EEGnGFsoKn8A7zJCxIc2n9fPBzmYfpZumNY/MRndMszd
PB1A/9Sx7W1G346Atfh5I4wDfWNrR9d4Cu4Px7BwpdbNPayNQzlGN0vXudut7S4lXu+G2ojFi7mX
VU/Pq+mIaMDfdYq43wt1XqAeLaUEFFOOLYuw3AnUiWQfRmMh8EF6mOywETMZFnvuoWQrg0V7TqDP
c8WtMkWUdG7iOOVtZICWBRfhvFSqg7pWElsmzwK5K9UjLkv9rS/8Pegq7Vr2bHvKPI5YpPVeeL18
OliXKyrjrKkN14K1kRrOJ8TTwzHDcldX5Vfps28EjokP7WZLpGXvywluXWc2nCWb1Xu3JCmVoC/0
XyJYB04sWAODfP48thi29f23VAefXkqSrc4kfsoJpinxSQZYm2tDq7UG2puArbTqljtmzgLjWl7/
d9tsedDzrejUmeMGpDU0dEN0epynM450xmLpu1w67vlvg+FjgpERd8OovYhEquMy/sMSmQbmavFr
TYSSQ1GoKycT/7NuykBcqzy5Iq5B99IIQGXZk9O004p5YKG4AQYihWGCRzGR/royRi27/tuYcbJJ
2PcYzn8eYBxy09WJS3c8tCVz7ZYK3DS0/KRSygowA85lPvpwCbumpJS2a13oZHCWFJ9cSG0BrXFi
CImqhMvo1xazX/z87bxLU3AKnlYwkq4DGoBwPBb5dEVf1ExpXvhtkJBHYKimstI777itT6FZKWFV
CEqKBIZszKnTXxdggVEOR9jF4jjsX9g9SGeZvo5hMw4VmBN61QHUM0kS5jzrdcTfOwnIns5Dezt9
WWcm48T1Z+EyZDdX80ZL7j0Kh2u3R70vXHI4c2U9U4atjQENvVAy/bgJlFvE3odzghST54igLIJm
6vx9mcEQ7m81IwbbOSBEnDJ0Y3e5MAn9Gric5KBHI3Pax0u4wD33JNhxy3Ztqwt2S/ystIvSKBfO
OFQ1Oht1J/5Ib05SYVPY3dIeAvWXU7TmVMOvq1kC+ktJb6ow5+TEe1kvw8Ap1FsGgFqfZz9eSLPd
LQiOQRsuJHTReaiCewHvvriF0DIdFmPpgsd8/gMYOK1CvaUkqWxp0vXkA505TnkcIrW13N9uSIbe
nH+090DOdViYbrec/95vTaZGU7ormOM7Jsg+m+JnKzjG9Ja8ay4adT8FhaolyzKSvIugak8QKGbS
tM7n6sbOyBhnwkBGuc9YGbDeLWWyW6VV5Di+WirKNixs1tsjDEYLtp3aZNjfuuxTwa8RYs3+PYNU
+azY/RrQSt7gU59WPBDyyRRsd9cIjhZ1RrqpAUM5y7pskghTfpjTOebHA8/yoq1d4OdtpHWc9UOj
g4VpL0Zs1k8LOt1Ysz+reuPRkCIYqyLCKHG33C14WqVXRpjFE3k/kTIJsJs2z4Z8Jf5W5M2PHcXF
3FKfvlLtf2pIRT5ErSbsEMP4Vl+ydMMLrNNLQ5ObFO4AEdFBoRdfMWtz8H5dYHVyF/ijX8+rdlZH
roGmQ59r5dNO6wWJ0DkUHgiw0eqef2OmQPSYbk8BW3GHlbG5SIhkwg+oCmvmSD2hfetTq8I2yZX8
qHC4k4wfiB69Lnv/NV61eQLSunefB5PR2EhmQQFN9dPY2PaDSC4CAtfiv8faaxEgk3gyygv88d7D
n3XwCR3ymnIGvxmG8g1Hv0MWtgtASMaOJgl/gEINBw4vWhq2PbpmwSs6NJBfGCdM+HFTmbpDARQc
XwBqxZ1kTec2tI3MCiKhL4QDUqLFEoy58tFpskuYkNSzCHT5KtdSRn+HBGDUJo6UiAogod/hn/9z
ig6cW/+qNjBBiTkTh3hC7P/Soiuoflf/SEacaujss/DLST3+GTB5+hvWsw7dFqVWryYpzep5ij1x
dHURFTTZ9y0fp6huSII72kAa1OZnspzTrDxp05CMfamaA6JLofTXZrCbnqUnEtCcLw+cR7/RsDHP
0fOhhUSzKDfGbAi+CQGB6aQeVN6j7Wt/pLZekSkcBBl8Pdjj/XX3TrKogyv3NhMXNl8wqFpc4u55
qNTcbdaeD4R6916gvcyg71iU9yrIp8pfo6wfeadbmVZW1k1RxsU0DfbuAd5w02AsK6kiV7Fm+vbb
Rq/GcPplJEncKU7a/Omu8s3lmL6HGkn6vORg4H8hf8yALqG5xLanbjo/NpAloauA+9iB9ue/Pe2l
v/7/8U41yc4wt2HiafQU1aUIVHqchg7mSBadB6Hlrd6g++ADTgXpSozhQjxif02fI9iCHFAenfyM
gGgS94Yg3I0JVJQvaxbQr6Ul9piA08RpbGU0wBRHNPm0qb8wUpYMffBJUsSCcna8FscrtQGi9kII
1qu+i2iVGhbn6kGTTBddYuUAP3LLptJE0/PjLQfswAK8U+pl/pIs8oJ8d/2zRdntNyQolEg5EbzJ
BXUtrjFYG/utbxODzAWWBhM1IVxuommVvrfvGRsivj53PdJe3GuB5c46FhS/o6/rkjrnT89cmJnU
rHa/Kx7zhOaL1qWgHpxh71kWWt0pTYKp6ki8goXDyOGr7ChZHV9ysEiKYK4SbBcYUp6v74OS6kRT
/6LuzJjPSz+2FPXB+YdKxumJALTjMHHZHKibjlmQAstB240JiTGpofkAyRQkg25VCeIdXbLBrGMo
aHjvVkNyH9eXDV+kKsn3EllrJTJf/E8rYksf1Z8eO03Q8ZGnG4o3GEc23nZOCa1St/Bp2kpbtAMh
AEIgl0MLRfz77eH3FG2xCMhEQTYpHvc4UHgK5Qo56BKmMPn0mkbRnQ/4iXoAdaji0s9kN57FCEtp
0ANuhy3Qn0hGmNt131A4QDTxO0tUz6TwiN2GjHTKoVsqOGOglXj9mbns1+VrSsKpDETfXjmUYoNn
Rjt/viMszLJfZqufPuGFTtXaDnYyBnNBbcjoqUG2EcEL/gCB6XxlEuc9A79xX7EtcJXB97D9nsxj
kyMnNLXP/Sb7hqgzI00XpTpwMLkFdL4kidrJAeug6uzv2Gi9liInkQO+J6lm2HvzNrl419WZEx78
FKPfVJQ6S1cSYsJoe53vwIj9dehh/c1K3TbslnOrGAQEnnc1NMaIcsV6L1Jg+/TbGMbycwgzIXna
5xAEfutTemLfLk2BNLZsztkI1lJWQXDfucCpl0aCJUUvu/En15j5fPD6vvlpkhaQPTd0tdDusBmj
pigx3PX/2QViWEhpJilYiBPcMoT0hyfxQ+/dvAHbMh5l6t0GSi2Ll3/qtzP7eC/lGhhuf+4jM5PM
tiYfpKkBsvcpH4L9hNngT4H92GSXR04mOSfJeyYXBGs+AkCWTSmE8LozCE2X/jEKRt7CsKGozYS7
lI08qT3yXYDpNCKq0E6aCDkIcLQ1KJYyUXbGWzd11Q95zt+iqZGaf3WpfRYs3O3zr/CYzcSN4w5N
Lumwn1lJMrkImboRs+TiHkImdfq9R8CZv88opvuIEKpHqzmA7NwO6w106mnhHD+lWDMsze1lu4Y0
LvKYpnXdK8okj1S6CsNJ6ZVOt9x6V7lAeezxPSY6VuzIz8n9UavTAT8ILIoS9sK4BVlKbVeSDvJH
YSSXcUiM7G1DYz/g3WxaPd/jIvLSl6vgtdUrO7jdTCKyGVconhCJinFLoW3b7lxtDkRFzq6dxtcu
l8k3/zP2133ySU/mPIRLeBA05315YomDpsjQXCX/e2NGwDNKV6EPcMEJuPgaZd5f/OhMXFBCQk12
spdCn/rHYlbhp+8KU3C6bprmjM25IdYS7hPFpN17owPTIEZfviUnYhsW9r4MDS+Aapb77AU6cqPl
H+lZZ/sDNWqPDn1tlqwcPLpcJZeB5B0XDjxCFAuyPWJdk39vCg/i/WKjx0r+m9G/cuqlE0k9b5SJ
O6rMjfnUyULv7GJcSziJOx/DEtFw3yyX4JXUBYlqu7rYY0312jKO3XCdk6gvKxfGIZp2sSDKNTkk
zq7SU3peOzEpxPIbm8PkrGhrFcLOGiG25X7ieDwTdRBVglIxZZMn0b/tz3hkTEkuvl/VK85M31JO
qa2BFVvnF9xsfklPjdkNY8Vz8hIwU5K7DQX8VQDOGb/EVH7NxAx/FLTO52ydHCAMBAG4J84K51Fx
HJP0dBlB9xirWq0WPcdZQUdS0BifgZmrcqhlmxCLa2JY5wvLPcPKfrMW9oXt29yqTDhjDaCM+knB
0Cowo2iYYeMloXaeDC7YNbgfxp7EzV4CE6DFdhV6Js/xpAIZd3ktARdcJcej1eOzSlRuVfpAvXS6
oXbUbsm/vi+Zni3J9I/lxOFEwXz0e/LATeeEXgEmVnh+WFFKMiYCcxBOneVipfjbPrHbgd63XN+N
z+MkyQmAcCaC5fVDWRDhlG43pGANM2NIf56XRcG6OBD8qdWXnwBoMMOlx19ZiyyhhBaNbWtyUW0V
I/trlzVqLg86fEFvpfhBQjnObA1ZTab2fsI+Wy64HAY1v6Es84DDKsm6Q5fgJORZzwv1/MAL3Zmy
EVq24xFt7jdU7ohRUH0E68OsHbWu4FUq7okoIg8vs0GdXG4Is7X+08aEHGGOjJiM9+eb+HGnbVHK
kvRC3Zpo42nGcTvuggzq5HmtAERZVlojTABiRtylWmDRj4F+cTvViC+mO0zLfgf3Lkhr2Gs6stCh
YijvSZMOA8DfFx0gbkWhXGZF+x64CtPE20mx+54qcLSVZwelyKJ/Qj+3mBfzdZoaCka19AUgGDTr
k1/SE7luNMjt5tX4Dbtqtp6Ui9+vHdeeN5PZKDhnd3ZfFNPomePoydJ4CDiometLhegW3OUs3zBv
pWPw91kWUtspx3KKTigJ55OoZW4tbYmDwyhw4bs2edsPv13SyI7NMSFPY006PV481U/c27VR94Av
KjcFNTDAzt51GEQ510KprDshs8OyJZO1sYygTUHl2HSuheJLfE/n/dEgCDuJ/EMglE7FgZx5cLcP
alNwnq9Wr1ZwA5ZtVvDYWVR7HCmBCcaBOrTz2NTIzKfdrmdTucsyvfwCO9TcK8iJIrswb+FAZxYI
JBF5Lhw033EYSry3Zy3OPw9kVfDqJ8IPgaVjEcpXd3Hvp/o3dOY3I77vmTRIPhCxsxyHBMebzB4e
xoMUwej+PSbdgUAv+i6LrSSMC+Op+VnpWbnb228BPmMsCwMXYSLXdJL5YjcbEL6CcrwOVu9hHCmp
TUWfYYrTQ8UbiVYVcqIjaw0mntegkpL+7Bb+zb83t4fORzt61Gldg7WYKW8GCk7tApXZxJEoYzbf
o9BhBqXtVkcC28Tvfzjs+rlrbjjokRa0OHnSpSP2beQFCTYaeGmi9kz13Wiq6Fvqj3U5uRro+db+
it5QspA5lqpQo1K2J7HG8n2EUQvcLM/Q+KRwNWA2qkN+I3yo1ORMnuzT5+AEhvzkxzJpl0LC4jAz
KwVxM7zcqc2HJ0kpFGVNeYRmB6A08DY+MpkI0PZ9aQCTAkj3gW3vbwl6lw0JAIxI9+uFKH3gEEPx
tbavrQaKbJkxoku33lcH+s+u0pIHnu808kVa7RsFwj02PD7riStcrqETZnUh2V50wphGSwfVqlo4
Mfv0/wnXzr9HFIn3yqlrGIERNTK7LrviaGC7kZ2nFnMte6HzbLElVSW7cb0NNV8E6dlaXDLQTzQn
gxfKacKJxUrwf7Zft/IAQ0vjN15hzm5M7kdVHPaFh3Iy9mAEwleEMzTqETsohqFopcxix8n4Sez1
wdk9MTF/ufGiRtDA6iyll1VJtJFOSE4uHaZfDsHyO7Jw3SPeOr2H6daWVCcDEZq4hLNgq55jvM9k
tBgSCtiNgNQh4jZrVuLEoQYwBqSyloVN7YmbiH6HzNpxFVmB8d8Hnl2oW0JR9YvikB4Njg/LjZHG
Tlw0gkO9AjwuAl8Gkq/qyhPjt2X2tHUkwsj1sBYvoWyw1BfRbD890MSmG/ZZIgb7M9ZGL7WhgWV5
rE4o0SyeekEED33C+dy4Tup6xIIYPLTjKHVBbDH4vQPLXi9igaRXxc/jZ4o/obR3V0HeiBtuwPR5
zpCQz/zrOVtPxghco19CEY5fCzSd+4Z0LQVlYMwsKSw3xOQuh6O3Ktnjb5RHeQ4YQXoaph3HzteA
4wIWwowTXOgnqmjvw7l9/lmlsR6yzN1ZuLRxHwx3FvX9oi1bt3zBY4VZaBPq/es5y0hxWTSeXjKH
IOfJMkap29p4sHRmfs6te8lfTZbSYHnZQSxvcQdLo/hwtnQoDcrBU7moCT/1FHd3y56usXYz0L1m
VM69o7B+BWGyLbPJwihdDlz6R8nxv9bXBNviNtDkGpgOOoQScuPJOU/x37kzDgamnsd9i4FJ23ly
Qukpgw9rrhzl7NY0ZkQbxkIlPrTBPsPRGZPccNV5KBV71VuQXFhjzk5WGoyFABQ08wJZwuyH4ni4
m5rR7AGTSVMPUrp32pyZAKMrtnHqXKNjLaNg2kudWRE/1NWyCrXuiSAbq3pyFbwOq5zN+xqJ+5L4
UeghK0Rm9CGpgg6SU+0RWVLDfPoIHxWVIrCpK1GnYK6usTijjc7XM+Y6FokZULLuZZ70HWLEzSB8
kJobACDkrNHtadcd8R6E7SK+0EHQaz4fcQ934SZWhC1+DkgblgW0Bd+NLTqk21/rATc6ItbWJt0u
yUAtOS2RZS8vV8OebmD5oZTisfIH6MtIMrzqN+8DITG4o2LhcSO1QWGmdnK5CJY/EFkP2KiWy3q3
pmA48si5kbLodepth9y+j4BRVbDEq1ciOOVHQLU3W6aCczrof9pykncDeXnLSLaoECdF+k2OPnxs
7SIykmcNSZZGO5mtRM9uT+SIRrT7WyHBbnicC7Ef5DiT0p2hgqWrbdKkrXRN7xfMF/6/++NUx5AL
U9GwWMcB801zo8aQRkRTiARbOVHR2qi/VuRfAJlt/x1XN3Pkz8vVxcjUxmG5gotpgkiI1EVW4lqb
BtIepKWfTpRpMsn+HVNv5q6pjNP+NUcJF2YQF+gwM1Uolagy+53cFYew/nJ9/QWP0BjNIUiEGINO
wo9fqPXd7tDLBtl6cP1zpxwr8h3Jc10xPgecRC9ZdnJ+WQCAdfEVOnXiytWh039WddVcXq/oUqDr
MV/NkqkdOS+60Z8Rj+yxjGgrsMrN5jsgTr1K0gtYQMLjVFD3EEcpniRTaLZ3Jkjg/xujOv84xh8A
dCPrCEtYQz81xgF+gdePqktVa9b0ci6bK+xxwYxvRUDiiciNTvlXnNxXIZY6M9meypawkEXErFyL
GcqUW++9PEgr5SY8xGr8LdlYkLoiaZRPJjpGbSlIN3oNNfLMfkzP5RiUVKafz8hYyZDYYa2Pxjel
fmBN+yj5f2PkdA3Myfl1eBIgk2q1pc+2P4sVP2kgLH0CZNuxuGKgssnZ5BniG6/pEj6OF1FrKy9h
Kko+0QC/MxqQYaTganrVpU2XCa45eDJoUDyZZFBstWMFLZs/LDfwOD1/WFQq/5A5uCM3TxH8SM9x
kJwoV/0a7QgLXDglOt0WZgkyjDb3Irwoc69SKyQh8ax/oVCnC35UTqS8zNwsP3zUqLuYdsRSid+l
6mSibEcyPIqE90oo3OEEv5oRhxeFOu33QNqXfZSL+b3tGaxKiLb2X/QbD6zKjP4xGeHzHfayyB9m
6OVFCS3NOCTuFc1V7IigFKLTZmfazCiBLR3u9PSb8z2lQA3H4GCh0xl+JcKslETmrNCfYekniUdX
2pqTojYP07ymDl302/m8dD1ntC6N8Hy1zrVNbBbdtgxWmTvZw+7vUh5RBEuACwSFWU1pgCfPAxkh
fSTnqGkdVSqBZX+Rl2OPEtuORPc8foxVkXTN3CCRZTehxTG1yvHtCduxIKCDsgomscvk+/7ELwUa
sv78BJBPYKnHXU2iMCvEUC6gs2tYlxfN/uJFzGVOm4d3RIKJtUM+KecRfb42yg8FW7knl6nqMMLh
ugiBf7Bn+dSCNzJdv6D/m7OtVhhIKgVeeez6VKocGOEZJ+U/eExx9JA7k1OkaTHBHHLOimC9YaG/
2uXyTDNK9fkuY54VQShyf62VkGksymCE27/bkAvHwy+f5l6ZEgA8JJD7217f9GSkHOuxWqL9ejrV
AGMSHc1IqA7bK4PaoWhIbpybNAX5zbofH5X0a2XWX/Lz3efak3yCOMyEEyK/VcXnFj9IVYXgzusb
ituVTyf6u7f9E1GsQxSp05CxQp5URTGj/Mn2ha9BcYwDKjtRJBWzWSgQaeNZ0ra5NGY7R2lGzylL
b0A8ugqCHiRrTh8pVFnl1aBoZ01NS1UCAoQaD+Ex/gzW3WLNM+IuiKhJC4u/eZuiVLxkTixbzgY9
l91TpVLmEcWtlvu7SBEag3hIRPgKuvJnYI1Ywy657smSf+s08GeqJLUuBKlcfO7OIiOjX4PRf56R
NrHAbVMJ0TqudPq+jBjpl30/4wsaZlIt1j0Fo05CeA7sV4uB33+rtNnQXlCj48NP2KhVj4rgjwOr
Fyuc5b5QgGXLHEusI2f882Zaq+s5RKb9ZljVcqhlJyedUw0f9utJRqvwI86rs9pPQnAupReNZahk
d3bT6BNIfv9CMyhtS21RPmWNUZqhIlGakn+pjx5l4tYzx6JhoJKM+XXWAazd7+9WCLXn/HJbiONq
QPKuJiwyh0BI5NjgCLUICt6va9aUG8KQ1YcDmohO8WSJTLpvf1AehOOmKhZzMVhpdlyZEyjD40ak
BCOcRJ4kTaO/GjwZHjSxi02ePNGf/tyl0bjU1+Z7XYpUz5+4XNem477z0+4raLSvws5eLM45Bo+P
HH5emHBdO4t9kMRXdV8Ku1LSKFnNTBuzSfr0EqR9f5EgNOOfSiCeO7pw1RsskcQvH8+6HH35+UAF
bD7wkABdKDZwCFU3WNvsa0Rv0bAUYPAFQHOtYS9GXvwb5v3dqHfjJX/CC4JcqHgofxhlSMazTwVc
qLXnLQMYxczthb2cm/PTOfY9194L1NtjyaDg/ZoD8KjNmPDo9j0cEmb/qGmJdPpKXUg1x4LS8GNV
wMpvZdbCPO4TnbZmpqNr8lmjd36yhWLiZWj7y3dg1SaRv1QjfBkTKuKNYiKhODGANXNXI3FPzGl0
gyZkCxVOKHstpSle3swo2tIwoMOwAMFYFNBZXqbaOGV4C2APn81eT8/qMaZfYGm1K9cyS3q7tp5M
b6thd5FJnDBSB9nFxDADCH42HDlzSp4QATIRp/dLmIUez5ghBxCRnjCJQmRUZng92udQLCCxWWJg
sDJSpPIRrhQSlIRdy+Oo6HUs1uzRxNv+O3zhNXW8SbTL86lzT0gBOwoDwBIQv+Eba/+vJGPFuRcY
pPzyAcy/ZqgUjHFfDOWd0T5ctiJ3l5x2CCjQghbvB594kR4LyEbJypF1zZlu+/rY4RmnNvGBSe0Q
Q6RzuoBS5+9XHH9iFciBs+cLO79Tv/b2Hd2tHmKXqTLTqCZY1n+e7v3gSU/4TA7zfgXzvzrnrrbf
N4KK10YS6sq3uwt7NUmm5pg538d1tfl9si0asIW89ivgj+idmVkGi7jqd8skOaMADB4fnou94eiz
7ATGHh+65ThSb0ht/GDrzYFGcJJXBx4NjVjTW/QoMYZlV1+8yux24oSmsFrs+aBnMloP3bOjP11Z
o3QRZZXgxZXrw+ygb9ozBqFyEYfL1zjyu3m5EK5X/EYx3cspcfXiVFwzL85zbDoiQ6HC44MwJa5w
WillRd1h1Tr+1m26bMPo3y/yvY9uR7WM1RVPQknPwOeuLebShUT0VTfLei8dZE3T7aCsaYRxbq5R
Pz1h1UxYITvbKzmbTvYXRyCz9qcg/Wd/ItpylMdkf/CtXGl2Y054q6LR8q2l9qhWycKIZGkqlFxU
aJbM3Meekxm9BpONaSHo5gZ3zRgnIjIVA6oGDEQMHnf+X/PBlD4btLpmYIOAqBZWKhenC+bjwDln
zIGLY/s0t+v+cuPfM4fopZLnxJzcLGAkIZjX2lcLpkQN6VMEmSuPjf9xGZRrY5T1O16GXiTUzJ3c
IR8BE9uyraNMSMOXIyNK2bpWa17fzsaO19WUfJY7471LAs+vdC4C2zmQ9VKxaXiiOz/OdAe/1ybA
R2oVSovKMzmvQpyB8MuUl/nTjyOrKrGxldGhzWBSHSoXKBos2uRBiMNge/6veX2LlywUU1jweRba
70HrvXQEERQ/kv+kNTiZhqQae9clDLJgQijy1KO9Tav6I2T64kUu8sx5cB9DsFgX/IJtBOoBgj0g
kcUnQvQuajzT9Ijv+YdzzVHw8NN6SZQTYmunhv5kDhg2o0eh5LcDc9fDp0641ax/0W4YjQ/rvP3a
63fx+J632yP1E+y7UhCMY+p6UCYQYNC2pD6N0sNUWIRwcZSZ7gzmfXtfRGU9I8gx2oSo3P3JpaWS
4i7b8C5LYYqN4s380fSr/ELm9762wxQuFb3OQV35CYrGfZae75wlVaYMdVg0wkUshAwExcwfiyWC
93kC7p4vuX6GZ3U1c2uJiTvKW6nTLTKQRIZj2ZL4beaSqxcyp30JDT2iRP3I/sZh0emTmjbavsYr
fsvDgH0HXkrOF0l0xk4/ghxE7i56nTO6J2s90TF3BvbztnkrpcaA2ZuSajvV3robTc6dZYPaRk0x
jtL9CNFhMJflP3l3zF8XoQXM3z0L/ez8SQ7r7PH5+Cf+1huKUYQ9QYh9Up/N38ByPEg2jnR5beYg
4hMZ6CbxcqC6Hv1N+7jKN1haKib05kiLmW2v87EDiE1aoLDUfn6B8iNseEK44M8jM9z90Vo19LYh
UxMSEVg5/LB7fMnJHvEvhwsdrUAZj+ju22zWEQuQNgcjQST8B8Nuuc5ejj/YUqUNhVUuRq3iV7ki
Tp0XUZifa++4Il0dfnUmDqYnFRwmf6S3c6HciyYm1q1AxPEA6fYeQlEnudF6OZQHYlSboDBn+LHQ
3aPBjg1B/Y7UZWyFk48v2FL1R10yjMNysFAAzdiw/GmBXXr61iwwEqLAoPX9+UndkX/d5IPOzl+t
5g5f3ZgVuestK1pinfrD2sO6qQogUytl1uKigZ1jAEw23/UN8rJXZxUhK1yFl+m3pMGkHOhXYduY
5rDTbWh4WlNsyZbrbaQEoughG5aaMn6+cib5bfBN8AHo72tcmFatoTJSjTgxAi54sXX/Meel/TBN
PHdD5WjlE0Qz1VNtFcdTBBQPiczJXMMi+eVCDWywVOOBXXaopPleEiwjFGo4OY9aNUFi5kjIYp7g
NVe8gvjzku5/g7S2LpdaNywl22Pak8l0BsgsrtW3ohF9qCTwmfouPpiVY2cQwXpNYLNYAU0fCAUl
7pXXBS6JmT1owV2QQo4pBewwlEzcHuhmUW9j8uPOaK+MLIXvsQtY/DsGXUnjRFoAH35ILagdMeHz
yE4XXQaDzgMpIFIGXsB6Uz9CYheIqhNLBRe7PoowvBjodihTlcq/6cYoSCnxjTvi/b1xuvJMZ18o
OW1h8AFQDSf1CgAxccPrVMNfC0uOH8r5X/kFdf/iTh3KkUCyPqNykz91ZVrwj5LmAUQAUKCJrNsT
I+nn+1UmFxMZl8qYyuqCfPiCRIQkbb7fczPBm7NFAnJ4Kn+UV+MsswMK1ltqIIn4/WhHZ83zuxto
rtnmmVEEOXbt1Rdp1yF5NGPexZwvl8mYLrb6z9+zL99+09IA++Hl+Wxx/BRXFMWX0FP/pvVInoGO
DOgh1GOm0E1Cr/XLyww8M+rT/nBYO6FA5TcNE9EVX725w06r29u1z7VT5tMV4qGgbcAokPcuUqPd
UeA++H/FCoiFPaXg3InftV1b1HYGsPbCUQv+ToG6YDco1Q/KFBlrs6F0A7qezumPz4wwamjLE/l5
tNViLWwpy48r2QmSpIxZKJhzeMLESrypI7l5jbprgQe0SAO6iNSa2PF4wRxLYjrbSkN9q4OUo8qc
wCwqtkHeO0YoqCFL2szpSL1W0MCyKko64p44zQhDT5hNoT/OojxMYkJc7v2gfxYhlnNvjZxmzs76
DyUo513FTvKA0S/vSTtcZidI7Cv92pTA1/e9T8XJ7UYJeQmRtBSg/G59LQ2JgplUbTmx9qmt8nlo
OYnQhuTocVSGK/QQwC1+tBZratZDXaFES45ByUFmCAY4j7mrTsNoP+lhBzyq3zfFPlvZ3Cdu0Lqz
g4rR/nQINhZEKMGk0wzDLRKpYJBMHyU7oFiOxYUw3AOeKhjUitpSwCFdOu2bBblMo+RBlai7xW1K
Gtw8gcNxBX0xdoaSfgdgLrMcjQziaNEiKna1HW5iDlOqOEJuH2j8iQx4uXg//+HqXT6C6jdZftpZ
zYQ3uEXpWuYvBHqI4P6JdGAcxgDQ4y60sBb9dtTPHc+M0NerxBv8prHELx2d2PNphyBlGntUNQNy
9VL9PPLyT6bmTKl4DMjzjqqQVdxF3JgZrkwFBiMiDdvoU+x8LCOM1brTqQG84HZnue7IA0e8cept
KjZ07kGWJPCrKUx80lzjX2xd81apqqXU3i1bpArIknViTWfA9Upm4W2FRflFFfx8MxrdmwXs9Y3t
WU/AqABjGU/3KYUTSlMnozrHEedQdmB73JNn/gsowLxaHZnU0w3fglyTBfHX6xyaT9S8KYf/Jl5X
QbCJE6ceJeaEk9or+PXE+IthV5fk0y/JyL2kFlPPr969kDs85CST4+UAy9gHNh5TFMqZKy8Lkfhp
ctP7/guLJN4Y0t+hskm+ZAJ2MCjP1pd5ULxrp7CeZO41YwocxgpP08mMmxCTKzJXNxaWwxbd3c4F
5TKFL0VQUclxJPEn2H+iIXFcj6OIeVX0M6j9FwTsC+lx3y0tvpOmdnvlj4nDHTbsuS68qlPdiXoB
OeqHX/Wj+eHCG+O6f5i/AwDFvUoGZVos8Sv8VLFIrS9auIrz5MzaM+2TvUVVKeDPaQ73oi4lHRMU
F5jL5DQkjDslCxSfd18CwlajR7qz6trVpxEnZPvlS03S1uabj8tsSEfsfXc5j4NOoWqGUlmQ9n1G
avWxb81rNnCmm/ySjQkYE0nwwEEEz1PqJmGKT4m7eYsVWWTb5AT3zYlPoT3pd/A351zaE2mdqTm9
19V+WUv2NSlKmivfH63figXSFFNCJHrVqbY9oQD9bbypt6sOawnfimUllv9ThgSyAbzfF/LOhOFN
UxTuhmx5+0nKaWrv4I87LLTPEv887lcE9hDoNSNnM/b3TQVyNumP6W84KNVmQsAC1d6HQZ/xGHaR
4vxhmw8qhiL00USKFg4O/j/9eW2ZRQ8J2gS1iYrDsxjJKuDNPoxaHBiNSn/wCveMM7blaxyH3+Fu
8/0//tunJS/6Ki0BExtyVW91iQt08SbWfw3IeFOqZUDTUk4PJSnykQf1Zj6gPsXgKE0LYIXjC7f4
IoQlahcMY9aOpXKeyVqL28frm1MT+M0l53wv6yc2CRM+DHjgE1KvlMPXtgnq3oTwyqpEy2LcHMdA
BbBZYi+fULMjqF6aGONqFs/sQhqmmaqbSD5fFnTmW7Mms8MmRdMNsoMz5W4SBjscQkhC3Z0CfbjO
DhPLLe19TjEJWxKIh94rTO9a1kcFzW4RvzadfiBvyWBBWj7M9pPSYD8/Bu5iEBABVjzLO0nXnAX/
U7x+8rWS9nZ0jwsUGpnaZlknChVQ/ETTXm+yhuodEu+zTaImDrPAfzPEmfpLJrlfOYT1/nLI2eVp
XD5+niu4OiWryJq55Ay31ChRAMrvmumcJdyojWE5pAIGLQsBOAEQjNLYr5p6MwOMcUdGCSofwFbv
BGr0fLiMy1EhWFri8EgFsz8iDapK7VvHI2TJthry6A9B624LGPty++0K1n6VOJMo2XKvjWapZV+z
p1ze8vjOOxGjhBjfpuqC2t4KYHidg6RV7hCRvRGu8a0DIWGuWYHkfdPHt+CyrwYU4J1Zlpt9V1tL
aqlSxw7FvMNdf2OsQ4XkcG0T04+um94p7l5J95ehCHTXrNmSUOZbK1n6KpUIeildkAUa9lSjKKyF
FvfvkJBKZl607gIG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
mqMMwuwihGR6UeYKQj/60B2AWf9clX8+kFsa2isPlH6+2kxLIuDt7Rog5tz/0lfUbeoT+pRbl+FK
EFuPUDT9UA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
GQNkFBuWBHbpOmzURG02aJpZ7XKog6XNa8zAE2eQ3xj6PMygKXnkH5nn5URP8M9zfRVrWMk/ENZe
OrfxqKkMYOO2BHpEVUo3Bysl8N94qsiFvMaZpx1aJs3h44WmFkcc5XmHHZzhuvDZMlvkL+NyI0Po
kVi/UVZXCA0LAFo+kas=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
rF+726hcpcVvxumQD/VPbCg8OFhPAwhb+Ul/5yt3t/Y1dDwZTrWppNHnLd7vmAtAYPyIF9pMUFUi
G3mui52lmlfF3iqJ/GdKjDzuLAy8lvBhpXuTmK+qQHV7eIdpy0vjzZmPRLup1PQKZeB0M8XENMdB
GkErIZrb4Ee0++t6GDvZKJmokpnSxRpxXqwd3YL+vn+wDME5+EIu3CiA/RlyOJ702F5TvIno7XYn
GZWlK5VFOi4ZO7mokHWasx0j7y2kCik+7zlGTZRSBPLUHxfSfUScQU768U9/S8TWH46Pcc90rek0
BlXcDEWGA0+dPlrMyZBFJ1B7DaJImvasBbrAtQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
x1gF98cy/K84iVqcjCIppYzn0b7EKIDTECh3SrVpndzv98JZp5lbsMBz14Yww8sb3Izl6j0UQ00A
FlIUfOrZq6kV0QyUREmP9Cvgb5uZpeox0nZ9ALThxHbxA/2BuwpdefU1+2M/Jku2Tf+qiFX5nV/y
iw2ehkDuNOx/ZSvhRaU=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
WBR3rarbr8o9Z9/IjwYqKM1+Ju6cRZUMAYs/BMJgccT/rO8QU6q0PGwSGVFASfTroNwC9xuaU9WW
lzzoJsBD5UNJ83X3kRSkSYOGUlhb2hWBwTp3B8ME7zpu9Li21BSn0JVbUlxJpJYJM5cJO8yY7A0N
5tps9qrfQRpmM3Rpql6m2gzaCGTNKTzHMsYX3RuOxZqVwSZb6QmqO3wbYEeI3fc/5q5gNCK1GD5Z
JwpFNxuUNr3JLMJpwtYHP+DUulxMruMaRvupFJQOWjMj0ihk6TZNl2dHMGLvwFop4foQXoFL3jKW
auopUbvx1BRfHytRSc6XV99/k3rS8+MlNYs5rg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13920)
`protect data_block
IUy5vHafcKg6rErwcdt6Se1WqHGyjVk3DQ3vb/5hCTC/XrHxbqa8oGcP+at55+tDco5ik5o6UzQY
5/tVjPJDIEjPt2ztj3RZvjbcexdmpk45mTlfz27MOR3dWQ/3z1WlhTQwFu+GWK2WLGp83Ti1S/1p
KbrmMTp3QsTSsqenyYy7l+DV7b/a0tcD7i9r1R4kAxQ3ma5xVphOBYbMNzJuWHyfdcchnk41YZfY
xJNrTyAgItXz/eITABo8QVEpIw9krRPiwIOiPg3w58oJHYSPocoh+MBtBxTrlQ7D/2x44b7vsZ6d
6yr47BKve4z7tVjgSU+UA/4P1EHuCCP/Id9g/xLTz8drT4KRjVPUW4N+YDcnennUfUO5U9VZVq6+
+H9MnA4FzsMt9+4BGBi1AsH5l3o0nSS4/M/EnwkTj2BsglY6AchVBL1HnjcT99hiEf1ImHneguIh
QFjcplBcDcNJILs2ZJhiP9U8+oZSqsG9993R6XoTcMB6aXXRbZRaW0JOsLrkjqwRUVDjfxQXhJGk
/HzmoHLNgFT5Ud23xTwREVUF/DJva/gVQEht8alcPaBtYhlKclwi1AqW4U2+qS0/SUXItrOPBqkB
RO3HuoE08taiguK+sJsRR4I/Um/uBoTHE4FG2TeavksyJgvIrj6Ae5hEzchq70PjL5Tn+roIMIxU
bJpgoeaWhrnRbD8073a/EIKUXb5956ecDPdoTlMHVtNVLtZFhvarMvhoGNvHHnF1EkkOCd2xZbUm
MEQl3vOskD/gSbsVG22DlShPPeio6ZhFQuHqcJ49zVOra8RTBKtSOi8m9Rx2D9tdUnVaR59ZKARq
CoqGv+WnlvLC2LVAdiMmipMgY2xkVfLsXI8eWH3363zBfluysGRiGz0DI6v4uyUmU641pGM3Xpsd
DtAD5mVxijOaHeGtIrCTTTZ6QkLQf37FBsaGPKYCQs/XV2zx3gZ6+iQ6bxZh2jO9x4ozk20LWqUk
kI2V6OSZ4MyhFwpnROEjSGmOw+XCBCFzUX6Now0IFkamRR9o1tl6QjqURTVQywh16yDPJGcRKt0M
Tn1Gx3CmpEFAaEUnhYyHk095ATiUKDFONvgMBafLZrTotI9h6dpcpZt8qr59S8a8M0ZZ2M4ICczp
qSV0T0RIdtAdgfpC7vCsMOxxp/KQuCJZaFAKKDr0g8Jg1xaTrZHq09zuJ2zdBZXsZD5/jjc2U8v3
6Kaw8eycGqaNEawFt9a3fAP3RCQDW9cga3rIDSyn9pdI8FnlPYBg+UEIs8uto5gxgBbTdpBBdppE
fiQu1NhMrMtULKDlqHM+QbArqPLhR25+J8MGOSxP/7Z2pA0v8k1r8NMLzWl0qbQ8bx8C2KncvZyJ
JxdXJJ9wHWnsxFdTzj//th962KZXoSKU2zvK8OwGeqhaXHCmNnKsfNukyNXhAyxCsSg0xwpRQDME
krUZUjWhbwf5JVwx+YzNMCoLI10/9F7lumRKAhW2KbH9JKVSY58eFVKV6LDy9kQGjwdG/wPoWiaj
gyuLJWUPgJlBmOo4deOFtdrhBMLPV2NbNcYay4GKXyjHI+5gePrPL2WqNH7rZoXCN8Mlj6GneRYT
OE31IiBubptXbdne9oY3EdMlXFaKImWeffabRWQaBYj+x3Kn5dtzkOV1hvekj4PzbW79VjwCqxlj
1GaKUpyMpY5k0vB5XDiHO2HXq+pQyfKhtny9UBEUp7NIKSq1COvk2wAGl6zwHoR7PpbkJOlW7dlb
IqOSMBowWvkvilry/xiYOPhczTRmMjUX88M0RFFtYX2mFVfsi+PLdhLJRzn6RLyVD+Fg8Bm44Cqk
XCWp1sxS43pb1c0DNPBATzTtcNuYmmziFxQk18uO1fqOKtmgbeERrOiSzaq403G1R8GbVZ+XsbBE
t528S1+UMxK1YVmhSOaNvjnb7EVX5tK37xNpN/OYbJP1fPqrBQTn5/7JWHsVfTEgzjXVbJ5ocaG/
7ul31b/FKOzicLlync7Lmo1HszdSLx5AeNbIWyJAZWW/5f0s2+6kd/SDCuC+UUoxrVZh2RT90rvB
fLrGWz4v2HMYHa4wjKfnwRXFY7iJksacNkkauXAIkD2CwZErhhi2co+Rp04C0bVpR3aVQ/h3CCOM
kgEstHEAvCefLPqdO9OQB3uZxPfzotnxtrYl7s4k7YGTJX3z8a5cd0oNxpib1ZqI9Z1C8DSNxZGA
gx7/y5iOKlXznx6wAxujWey7fjv5yc3Kl2UBsTedlO4Af9njL55pQGZMNTEDXuHryThhJdSL8aZC
gUM73H7jPMVo1gLd7j3LLM6F1TNXMFI3t2pGtkTVzCatQP1ZSA//NLHf9TpX94cCXRRnvahUI2K9
SFUpzmVVfsRkzX5ya2aID4qSWS9WXFfVI7Ef+iqkNIY9MgK7bxaYPzOkCCv1j3qCLFFXwvc//Pas
vigDGLkBlY2YRIwuEfwg17SWyAYF7yXtt+ZiDQW7rRYe6738yEXJzJ9s+/mE31XCowYJ4edd+6op
7H72/4aVbDrDFpvhu7Z515ylga1SBb8xYsCG0nwVoHCb/bwvVD+dG+lGL1BfF2yEAuyrHHCSqo/o
cDpOfIPDLtdsjx3w4N35ynvIeVlybaTukdm1cNvPWG74p8I3+8r/LxOz02L8lRC3H6CKbBtBb0jl
S6+ENM1LDWJ3oeYT00NVpE17CB/MdKy0g9fVUHpJsekb9zpcazoSQE73Ny+ANIRIFyDqsL7s24+2
VUyApyfsFOQmbKyx8+Xfj6X0S+SKCOzQQYzgzyMg8+h9tAC8vcBiTf5hUUnZZ69a6IuLHrdxuoxR
XkGrE7NhGKXF27shBOTwsxQNGyrubHdgzITSMv+cCUWwuyV2v4Vk7J/qQIC3K6DKorXPdXKF+9gp
BjfL/HHg9RIqAwrQN77TXDJ6+YEaoOnOl4GbW0pvV0otEHFpE20ihQO6+jNLhXuFvmyGvxSMyAxX
Lf7HJHwvjynv2uJwYs/jXWwXuP3ToKzjxjmtnrfM4kWIAxZu1BAdk3/1Tg2NH0dCbxWVsBJfQ3RL
Rb/Xehu4/FW/YiHYfCEqoPyYTtp3uM8oKa0MKl2HdwBQVJo0yYSAFD6vY2TvfcXY8WvDSQDUzDFg
+evWg8dvUmFuXeD2NZ9X3GzipY9gcYgvLczTLiD4QtYhjiFT+/TgSiRfB8hBoHWMM2/+V7SIVWNx
vwv2a48iXRmEKZ5m9jk1kNglt+aMKp28DQ4Uu883p4DpFOWU7Urfb7AYXK5YYz6K3hUiqX4rwP73
l7j6vyMfC2rTE5F3dByqMHokEsnAzzwwW/NFqBjzV2Z6pX0BxFgc4DJMfi8Og096QmptzG0bwc3+
s40V5fPf5MZwdtuSW4ZWSVmk30kEn9xJnJzAND9lnnoWb5MMqVh3ty7y7YCtR7JsZuyFfm9tEC98
Eo9I1DPFCdYG1p/EcypwXkf+frFQvaf9+K0lr7/v3pBWHlykb2tvFufN8+pD6lYwpFZvnvG5805w
Qb4WTFZNbzgi6ZhysIpHi31LMIhftcoyR1Lx36JOKEqxPjr/Wvy4ltP22vPvddxLPiMojL/0SpS4
Gjs3D36XZBS0oe1W8EnqJvVOKyFnIr6aMpsKdeWnDja0LHzXKwTRfwlrj/tSpogHFzj/ty9V8P4O
6MdirOqycsOcBpvDAU9U3VS+duc4BMV+onCK0Id6UuATVkRxctVodX6wXumH6oK3PG5PG1Dkj/pf
9ckigwRT5b0hJdb3CtN7s5cHh9EqMfjajcGxeJT1PEPKmS1q4i4gqnvgxVQN9Yo2RT1e84X/a1IE
NXY6hz8olxUqeCyy+p8uT7voAtJ2NGvv3SNiiPxSCtk8k1LC45ytunDfVe/7noMNrs0Sf+J1jC84
hhSZ1s0OfHpcmyYStlnftd044kUjtIuaIetMarjtB0sZOH3KYziCvkTDktmWMaCPi42AvfXo0kik
J8x6LEP7gd4S9JK6InzmYq4Ob5objflosl2kBqsguLo7GTxF105HBnSiJ2FmEvG2OPvk/5PJqyHL
SDNqs/xb4lCuOUWONBdByHntaZDvFts8JBr4ablhsQZ987tOZT15AYulYXSmNVguMUdl1nR+Gzcg
pnqHQThW435b76Yo252r6lt5+V4cDGLEgKPun0BNiAYJMihkY5RnCd+CutyNVfDwwqFdOacI/qom
XqGYBa4smohCaW45Ql+WLrQ46MOq7oqjsASMO1WUyoc47tCQZ1nTFDGgNJWaMS9P5PS0i0GDnm7Q
N37wMjLW2RD9CRSXc85owjtu4FIMJsPmSv143YooByxV00XitMH2iQdHgqOv0A46lzllPCfYKCau
OYUrgz3YC4teyadElu/sjP80VXAZpP/aeY608nT8GvVoNsOdy339yfz3u9I4JTUJNpSsyV8cXIEM
LQuVkUmFa548KWxeGewaroptstbM7tZPLz2hSYVHF+6chTT5aZopp70+wOFhKE3k4pvANfOUkCNA
MynbiJJctkkaYrzOeyCT+A2bE760ROR3ZVYra0ByDbQH3E7rvd1Ttza0wJEtvk4rllxkZXZa9ZMb
OoF9Tna2Aohe3WqW4CUdc3yTKUjn+n/i4mnDt30I5g3fJ/76/ktgg4m6SWd/Zjjjaaspj/A/VArx
P+1evFBnkbOAuak6ybXIKITDWVPsrYV/EEGnGFsoKn8A7zJCxIc2n9fPBzmYfpZumNY/MRndMszd
PB1A/9Sx7W1G346Atfh5I4wDfWNrR9d4Cu4Px7BwpdbNPayNQzlGN0vXudut7S4lXu+G2ojFi7mX
VU/Pq+mIaMDfdYq43wt1XqAeLaUEFFOOLYuw3AnUiWQfRmMh8EF6mOywETMZFnvuoWQrg0V7TqDP
c8WtMkWUdG7iOOVtZICWBRfhvFSqg7pWElsmzwK5K9UjLkv9rS/8Pegq7Vr2bHvKPI5YpPVeeL18
OliXKyrjrKkN14K1kRrOJ8TTwzHDcldX5Vfps28EjokP7WZLpGXvywluXWc2nCWb1Xu3JCmVoC/0
XyJYB04sWAODfP48thi29f23VAefXkqSrc4kfsoJpinxSQZYm2tDq7UG2puArbTqljtmzgLjWl7/
d9tsedDzrejUmeMGpDU0dEN0epynM450xmLpu1w67vlvg+FjgpERd8OovYhEquMy/sMSmQbmavFr
TYSSQ1GoKycT/7NuykBcqzy5Iq5B99IIQGXZk9O004p5YKG4AQYihWGCRzGR/royRi27/tuYcbJJ
2PcYzn8eYBxy09WJS3c8tCVz7ZYK3DS0/KRSygowA85lPvpwCbumpJS2a13oZHCWFJ9cSG0BrXFi
CImqhMvo1xazX/z87bxLU3AKnlYwkq4DGoBwPBb5dEVf1ExpXvhtkJBHYKimstI777itT6FZKWFV
CEqKBIZszKnTXxdggVEOR9jF4jjsX9g9SGeZvo5hMw4VmBN61QHUM0kS5jzrdcTfOwnIns5Dezt9
WWcm48T1Z+EyZDdX80ZL7j0Kh2u3R70vXHI4c2U9U4atjQENvVAy/bgJlFvE3odzghST54igLIJm
6vx9mcEQ7m81IwbbOSBEnDJ0Y3e5MAn9Gric5KBHI3Pax0u4wD33JNhxy3Ztqwt2S/ystIvSKBfO
OFQ1Oht1J/5Ib05SYVPY3dIeAvWXU7TmVMOvq1kC+ktJb6ow5+TEe1kvw8Ap1FsGgFqfZz9eSLPd
LQiOQRsuJHTReaiCewHvvriF0DIdFmPpgsd8/gMYOK1CvaUkqWxp0vXkA505TnkcIrW13N9uSIbe
nH+090DOdViYbrec/95vTaZGU7ormOM7Jsg+m+JnKzjG9Ja8ay4adT8FhaolyzKSvIugak8QKGbS
tM7n6sbOyBhnwkBGuc9YGbDeLWWyW6VV5Di+WirKNixs1tsjDEYLtp3aZNjfuuxTwa8RYs3+PYNU
+azY/RrQSt7gU59WPBDyyRRsd9cIjhZ1RrqpAUM5y7pskghTfpjTOebHA8/yoq1d4OdtpHWc9UOj
g4VpL0Zs1k8LOt1Ysz+reuPRkCIYqyLCKHG33C14WqVXRpjFE3k/kTIJsJs2z4Z8Jf5W5M2PHcXF
3FKfvlLtf2pIRT5ErSbsEMP4Vl+ydMMLrNNLQ5ObFO4AEdFBoRdfMWtz8H5dYHVyF/ijX8+rdlZH
roGmQ59r5dNO6wWJ0DkUHgiw0eqef2OmQPSYbk8BW3GHlbG5SIhkwg+oCmvmSD2hfetTq8I2yZX8
qHC4k4wfiB69Lnv/NV61eQLSunefB5PR2EhmQQFN9dPY2PaDSC4CAtfiv8faaxEgk3gyygv88d7D
n3XwCR3ymnIGvxmG8g1Hv0MWtgtASMaOJgl/gEINBw4vWhq2PbpmwSs6NJBfGCdM+HFTmbpDARQc
XwBqxZ1kTec2tI3MCiKhL4QDUqLFEoy58tFpskuYkNSzCHT5KtdSRn+HBGDUJo6UiAogod/hn/9z
ig6cW/+qNjBBiTkTh3hC7P/Soiuoflf/SEacaujss/DLST3+GTB5+hvWsw7dFqVWryYpzep5ij1x
dHURFTTZ9y0fp6huSII72kAa1OZnspzTrDxp05CMfamaA6JLofTXZrCbnqUnEtCcLw+cR7/RsDHP
0fOhhUSzKDfGbAi+CQGB6aQeVN6j7Wt/pLZekSkcBBl8Pdjj/XX3TrKogyv3NhMXNl8wqFpc4u55
qNTcbdaeD4R6916gvcyg71iU9yrIp8pfo6wfeadbmVZW1k1RxsU0DfbuAd5w02AsK6kiV7Fm+vbb
Rq/GcPplJEncKU7a/Omu8s3lmL6HGkn6vORg4H8hf8yALqG5xLanbjo/NpAloauA+9iB9ue/Pe2l
v/7/8U41yc4wt2HiafQU1aUIVHqchg7mSBadB6Hlrd6g++ADTgXpSozhQjxif02fI9iCHFAenfyM
gGgS94Yg3I0JVJQvaxbQr6Ul9piA08RpbGU0wBRHNPm0qb8wUpYMffBJUsSCcna8FscrtQGi9kII
1qu+i2iVGhbn6kGTTBddYuUAP3LLptJE0/PjLQfswAK8U+pl/pIs8oJ8d/2zRdntNyQolEg5EbzJ
BXUtrjFYG/utbxODzAWWBhM1IVxuommVvrfvGRsivj53PdJe3GuB5c46FhS/o6/rkjrnT89cmJnU
rHa/Kx7zhOaL1qWgHpxh71kWWt0pTYKp6ki8goXDyOGr7ChZHV9ysEiKYK4SbBcYUp6v74OS6kRT
/6LuzJjPSz+2FPXB+YdKxumJALTjMHHZHKibjlmQAstB240JiTGpofkAyRQkg25VCeIdXbLBrGMo
aHjvVkNyH9eXDV+kKsn3EllrJTJf/E8rYksf1Z8eO03Q8ZGnG4o3GEc23nZOCa1St/Bp2kpbtAMh
AEIgl0MLRfz77eH3FG2xCMhEQTYpHvc4UHgK5Qo56BKmMPn0mkbRnQ/4iXoAdaji0s9kN57FCEtp
0ANuhy3Qn0hGmNt131A4QDTxO0tUz6TwiN2GjHTKoVsqOGOglXj9mbns1+VrSsKpDETfXjmUYoNn
Rjt/viMszLJfZqufPuGFTtXaDnYyBnNBbcjoqUG2EcEL/gCB6XxlEuc9A79xX7EtcJXB97D9nsxj
kyMnNLXP/Sb7hqgzI00XpTpwMLkFdL4kidrJAeug6uzv2Gi9liInkQO+J6lm2HvzNrl419WZEx78
FKPfVJQ6S1cSYsJoe53vwIj9dehh/c1K3TbslnOrGAQEnnc1NMaIcsV6L1Jg+/TbGMbycwgzIXna
5xAEfutTemLfLk2BNLZsztkI1lJWQXDfucCpl0aCJUUvu/En15j5fPD6vvlpkhaQPTd0tdDusBmj
pigx3PX/2QViWEhpJilYiBPcMoT0hyfxQ+/dvAHbMh5l6t0GSi2Ll3/qtzP7eC/lGhhuf+4jM5PM
tiYfpKkBsvcpH4L9hNngT4H92GSXR04mOSfJeyYXBGs+AkCWTSmE8LozCE2X/jEKRt7CsKGozYS7
lI08qT3yXYDpNCKq0E6aCDkIcLQ1KJYyUXbGWzd11Q95zt+iqZGaf3WpfRYs3O3zr/CYzcSN4w5N
Lumwn1lJMrkImboRs+TiHkImdfq9R8CZv88opvuIEKpHqzmA7NwO6w106mnhHD+lWDMsze1lu4Y0
LvKYpnXdK8okj1S6CsNJ6ZVOt9x6V7lAeezxPSY6VuzIz8n9UavTAT8ILIoS9sK4BVlKbVeSDvJH
YSSXcUiM7G1DYz/g3WxaPd/jIvLSl6vgtdUrO7jdTCKyGVconhCJinFLoW3b7lxtDkRFzq6dxtcu
l8k3/zP2133ySU/mPIRLeBA05315YomDpsjQXCX/e2NGwDNKV6EPcMEJuPgaZd5f/OhMXFBCQk12
spdCn/rHYlbhp+8KU3C6bprmjM25IdYS7hPFpN17owPTIEZfviUnYhsW9r4MDS+Aapb77AU6cqPl
H+lZZ/sDNWqPDn1tlqwcPLpcJZeB5B0XDjxCFAuyPWJdk39vCg/i/WKjx0r+m9G/cuqlE0k9b5SJ
O6rMjfnUyULv7GJcSziJOx/DEtFw3yyX4JXUBYlqu7rYY0312jKO3XCdk6gvKxfGIZp2sSDKNTkk
zq7SU3peOzEpxPIbm8PkrGhrFcLOGiG25X7ieDwTdRBVglIxZZMn0b/tz3hkTEkuvl/VK85M31JO
qa2BFVvnF9xsfklPjdkNY8Vz8hIwU5K7DQX8VQDOGb/EVH7NxAx/FLTO52ydHCAMBAG4J84K51Fx
HJP0dBlB9xirWq0WPcdZQUdS0BifgZmrcqhlmxCLa2JY5wvLPcPKfrMW9oXt29yqTDhjDaCM+knB
0Cowo2iYYeMloXaeDC7YNbgfxp7EzV4CE6DFdhV6Js/xpAIZd3ktARdcJcej1eOzSlRuVfpAvXS6
oXbUbsm/vi+Zni3J9I/lxOFEwXz0e/LATeeEXgEmVnh+WFFKMiYCcxBOneVipfjbPrHbgd63XN+N
z+MkyQmAcCaC5fVDWRDhlG43pGANM2NIf56XRcG6OBD8qdWXnwBoMMOlx19ZiyyhhBaNbWtyUW0V
I/trlzVqLg86fEFvpfhBQjnObA1ZTab2fsI+Wy64HAY1v6Es84DDKsm6Q5fgJORZzwv1/MAL3Zmy
EVq24xFt7jdU7ohRUH0E68OsHbWu4FUq7okoIg8vs0GdXG4Is7X+08aEHGGOjJiM9+eb+HGnbVHK
kvRC3Zpo42nGcTvuggzq5HmtAERZVlojTABiRtylWmDRj4F+cTvViC+mO0zLfgf3Lkhr2Gs6stCh
YijvSZMOA8DfFx0gbkWhXGZF+x64CtPE20mx+54qcLSVZwelyKJ/Qj+3mBfzdZoaCka19AUgGDTr
k1/SE7luNMjt5tX4Dbtqtp6Ui9+vHdeeN5PZKDhnd3ZfFNPomePoydJ4CDiometLhegW3OUs3zBv
pWPw91kWUtspx3KKTigJ55OoZW4tbYmDwyhw4bs2edsPv13SyI7NMSFPY006PV481U/c27VR94Av
KjcFNTDAzt51GEQ510KprDshs8OyJZO1sYygTUHl2HSuheJLfE/n/dEgCDuJ/EMglE7FgZx5cLcP
alNwnq9Wr1ZwA5ZtVvDYWVR7HCmBCcaBOrTz2NTIzKfdrmdTucsyvfwCO9TcK8iJIrswb+FAZxYI
JBF5Lhw033EYSry3Zy3OPw9kVfDqJ8IPgaVjEcpXd3Hvp/o3dOY3I77vmTRIPhCxsxyHBMebzB4e
xoMUwej+PSbdgUAv+i6LrSSMC+Op+VnpWbnb228BPmMsCwMXYSLXdJL5YjcbEL6CcrwOVu9hHCmp
TUWfYYrTQ8UbiVYVcqIjaw0mntegkpL+7Bb+zb83t4fORzt61Gldg7WYKW8GCk7tApXZxJEoYzbf
o9BhBqXtVkcC28Tvfzjs+rlrbjjokRa0OHnSpSP2beQFCTYaeGmi9kz13Wiq6Fvqj3U5uRro+db+
it5QspA5lqpQo1K2J7HG8n2EUQvcLM/Q+KRwNWA2qkN+I3yo1ORMnuzT5+AEhvzkxzJpl0LC4jAz
KwVxM7zcqc2HJ0kpFGVNeYRmB6A08DY+MpkI0PZ9aQCTAkj3gW3vbwl6lw0JAIxI9+uFKH3gEEPx
tbavrQaKbJkxoku33lcH+s+u0pIHnu808kVa7RsFwj02PD7riStcrqETZnUh2V50wphGSwfVqlo4
Mfv0/wnXzr9HFIn3yqlrGIERNTK7LrviaGC7kZ2nFnMte6HzbLElVSW7cb0NNV8E6dlaXDLQTzQn
gxfKacKJxUrwf7Zft/IAQ0vjN15hzm5M7kdVHPaFh3Iy9mAEwleEMzTqETsohqFopcxix8n4Sez1
wdk9MTF/ufGiRtDA6iyll1VJtJFOSE4uHaZfDsHyO7Jw3SPeOr2H6daWVCcDEZq4hLNgq55jvM9k
tBgSCtiNgNQh4jZrVuLEoQYwBqSyloVN7YmbiH6HzNpxFVmB8d8Hnl2oW0JR9YvikB4Njg/LjZHG
Tlw0gkO9AjwuAl8Gkq/qyhPjt2X2tHUkwsj1sBYvoWyw1BfRbD890MSmG/ZZIgb7M9ZGL7WhgWV5
rE4o0SyeekEED33C+dy4Tup6xIIYPLTjKHVBbDH4vQPLXi9igaRXxc/jZ4o/obR3V0HeiBtuwPR5
zpCQz/zrOVtPxghco19CEY5fCzSd+4Z0LQVlYMwsKSw3xOQuh6O3Ktnjb5RHeQ4YQXoaph3HzteA
4wIWwowTXOgnqmjvw7l9/lmlsR6yzN1ZuLRxHwx3FvX9oi1bt3zBY4VZaBPq/es5y0hxWTSeXjKH
IOfJMkap29p4sHRmfs6te8lfTZbSYHnZQSxvcQdLo/hwtnQoDcrBU7moCT/1FHd3y56usXYz0L1m
VM69o7B+BWGyLbPJwihdDlz6R8nxv9bXBNviNtDkGpgOOoQScuPJOU/x37kzDgamnsd9i4FJ23ly
Qukpgw9rrhzl7NY0ZkQbxkIlPrTBPsPRGZPccNV5KBV71VuQXFhjzk5WGoyFABQ08wJZwuyH4ni4
m5rR7AGTSVMPUrp32pyZAKMrtnHqXKNjLaNg2kudWRE/1NWyCrXuiSAbq3pyFbwOq5zN+xqJ+5L4
UeghK0Rm9CGpgg6SU+0RWVLDfPoIHxWVIrCpK1GnYK6usTijjc7XM+Y6FokZULLuZZ70HWLEzSB8
kJobACDkrNHtadcd8R6E7SK+0EHQaz4fcQ934SZWhC1+DkgblgW0Bd+NLTqk21/rATc6ItbWJt0u
yUAtOS2RZS8vV8OebmD5oZTisfIH6MtIMrzqN+8DITG4o2LhcSO1QWGmdnK5CJY/EFkP2KiWy3q3
pmA48si5kbLodepth9y+j4BRVbDEq1ciOOVHQLU3W6aCczrof9pykncDeXnLSLaoECdF+k2OPnxs
7SIykmcNSZZGO5mtRM9uT+SIRrT7WyHBbnicC7Ef5DiT0p2hgqWrbdKkrXRN7xfMF/6/++NUx5AL
U9GwWMcB801zo8aQRkRTiARbOVHR2qi/VuRfAJlt/x1XN3Pkz8vVxcjUxmG5gotpgkiI1EVW4lqb
BtIepKWfTpRpMsn+HVNv5q6pjNP+NUcJF2YQF+gwM1Uolagy+53cFYew/nJ9/QWP0BjNIUiEGINO
wo9fqPXd7tDLBtl6cP1zpxwr8h3Jc10xPgecRC9ZdnJ+WQCAdfEVOnXiytWh039WddVcXq/oUqDr
MV/NkqkdOS+60Z8Rj+yxjGgrsMrN5jsgTr1K0gtYQMLjVFD3EEcpniRTaLZ3Jkjg/xujOv84xh8A
dCPrCEtYQz81xgF+gdePqktVa9b0ci6bK+xxwYxvRUDiiciNTvlXnNxXIZY6M9meypawkEXErFyL
GcqUW++9PEgr5SY8xGr8LdlYkLoiaZRPJjpGbSlIN3oNNfLMfkzP5RiUVKafz8hYyZDYYa2Pxjel
fmBN+yj5f2PkdA3Myfl1eBIgk2q1pc+2P4sVP2kgLH0CZNuxuGKgssnZ5BniG6/pEj6OF1FrKy9h
Kko+0QC/MxqQYaTganrVpU2XCa45eDJoUDyZZFBstWMFLZs/LDfwOD1/WFQq/5A5uCM3TxH8SM9x
kJwoV/0a7QgLXDglOt0WZgkyjDb3Irwoc69SKyQh8ax/oVCnC35UTqS8zNwsP3zUqLuYdsRSid+l
6mSibEcyPIqE90oo3OEEv5oRhxeFOu33QNqXfZSL+b3tGaxKiLb2X/QbD6zKjP4xGeHzHfayyB9m
6OVFCS3NOCTuFc1V7IigFKLTZmfazCiBLR3u9PSb8z2lQA3H4GCh0xl+JcKslETmrNCfYekniUdX
2pqTojYP07ymDl302/m8dD1ntC6N8Hy1zrVNbBbdtgxWmTvZw+7vUh5RBEuACwSFWU1pgCfPAxkh
fSTnqGkdVSqBZX+Rl2OPEtuORPc8foxVkXTN3CCRZTehxTG1yvHtCduxIKCDsgomscvk+/7ELwUa
sv78BJBPYKnHXU2iMCvEUC6gs2tYlxfN/uJFzGVOm4d3RIKJtUM+KecRfb42yg8FW7knl6nqMMLh
ugiBf7Bn+dSCNzJdv6D/m7OtVhhIKgVeeez6VKocGOEZJ+U/eExx9JA7k1OkaTHBHHLOimC9YaG/
2uXyTDNK9fkuY54VQShyf62VkGksymCE27/bkAvHwy+f5l6ZEgA8JJD7217f9GSkHOuxWqL9ejrV
AGMSHc1IqA7bK4PaoWhIbpybNAX5zbofH5X0a2XWX/Lz3efak3yCOMyEEyK/VcXnFj9IVYXgzusb
ituVTyf6u7f9E1GsQxSp05CxQp5URTGj/Mn2ha9BcYwDKjtRJBWzWSgQaeNZ0ra5NGY7R2lGzylL
b0A8ugqCHiRrTh8pVFnl1aBoZ01NS1UCAoQaD+Ex/gzW3WLNM+IuiKhJC4u/eZuiVLxkTixbzgY9
l91TpVLmEcWtlvu7SBEag3hIRPgKuvJnYI1Ywy657smSf+s08GeqJLUuBKlcfO7OIiOjX4PRf56R
NrHAbVMJ0TqudPq+jBjpl30/4wsaZlIt1j0Fo05CeA7sV4uB33+rtNnQXlCj48NP2KhVj4rgjwOr
Fyuc5b5QgGXLHEusI2f882Zaq+s5RKb9ZljVcqhlJyedUw0f9utJRqvwI86rs9pPQnAupReNZahk
d3bT6BNIfv9CMyhtS21RPmWNUZqhIlGakn+pjx5l4tYzx6JhoJKM+XXWAazd7+9WCLXn/HJbiONq
QPKuJiwyh0BI5NjgCLUICt6va9aUG8KQ1YcDmohO8WSJTLpvf1AehOOmKhZzMVhpdlyZEyjD40ak
BCOcRJ4kTaO/GjwZHjSxi02ePNGf/tyl0bjU1+Z7XYpUz5+4XNem477z0+4raLSvws5eLM45Bo+P
HH5emHBdO4t9kMRXdV8Ku1LSKFnNTBuzSfr0EqR9f5EgNOOfSiCeO7pw1RsskcQvH8+6HH35+UAF
bD7wkABdKDZwCFU3WNvsa0Rv0bAUYPAFQHOtYS9GXvwb5v3dqHfjJX/CC4JcqHgofxhlSMazTwVc
qLXnLQMYxczthb2cm/PTOfY9194L1NtjyaDg/ZoD8KjNmPDo9j0cEmb/qGmJdPpKXUg1x4LS8GNV
wMpvZdbCPO4TnbZmpqNr8lmjd36yhWLiZWj7y3dg1SaRv1QjfBkTKuKNYiKhODGANXNXI3FPzGl0
gyZkCxVOKHstpSle3swo2tIwoMOwAMFYFNBZXqbaOGV4C2APn81eT8/qMaZfYGm1K9cyS3q7tp5M
b6thd5FJnDBSB9nFxDADCH42HDlzSp4QATIRp/dLmIUez5ghBxCRnjCJQmRUZng92udQLCCxWWJg
sDJSpPIRrhQSlIRdy+Oo6HUs1uzRxNv+O3zhNXW8SbTL86lzT0gBOwoDwBIQv+Eba/+vJGPFuRcY
pPzyAcy/ZqgUjHFfDOWd0T5ctiJ3l5x2CCjQghbvB594kR4LyEbJypF1zZlu+/rY4RmnNvGBSe0Q
Q6RzuoBS5+9XHH9iFciBs+cLO79Tv/b2Hd2tHmKXqTLTqCZY1n+e7v3gSU/4TA7zfgXzvzrnrrbf
N4KK10YS6sq3uwt7NUmm5pg538d1tfl9si0asIW89ivgj+idmVkGi7jqd8skOaMADB4fnou94eiz
7ATGHh+65ThSb0ht/GDrzYFGcJJXBx4NjVjTW/QoMYZlV1+8yux24oSmsFrs+aBnMloP3bOjP11Z
o3QRZZXgxZXrw+ygb9ozBqFyEYfL1zjyu3m5EK5X/EYx3cspcfXiVFwzL85zbDoiQ6HC44MwJa5w
WillRd1h1Tr+1m26bMPo3y/yvY9uR7WM1RVPQknPwOeuLebShUT0VTfLei8dZE3T7aCsaYRxbq5R
Pz1h1UxYITvbKzmbTvYXRyCz9qcg/Wd/ItpylMdkf/CtXGl2Y054q6LR8q2l9qhWycKIZGkqlFxU
aJbM3Meekxm9BpONaSHo5gZ3zRgnIjIVA6oGDEQMHnf+X/PBlD4btLpmYIOAqBZWKhenC+bjwDln
zIGLY/s0t+v+cuPfM4fopZLnxJzcLGAkIZjX2lcLpkQN6VMEmSuPjf9xGZRrY5T1O16GXiTUzJ3c
IR8BE9uyraNMSMOXIyNK2bpWa17fzsaO19WUfJY7471LAs+vdC4C2zmQ9VKxaXiiOz/OdAe/1ybA
R2oVSovKMzmvQpyB8MuUl/nTjyOrKrGxldGhzWBSHSoXKBos2uRBiMNge/6veX2LlywUU1jweRba
70HrvXQEERQ/kv+kNTiZhqQae9clDLJgQijy1KO9Tav6I2T64kUu8sx5cB9DsFgX/IJtBOoBgj0g
kcUnQvQuajzT9Ijv+YdzzVHw8NN6SZQTYmunhv5kDhg2o0eh5LcDc9fDp0641ax/0W4YjQ/rvP3a
63fx+J632yP1E+y7UhCMY+p6UCYQYNC2pD6N0sNUWIRwcZSZ7gzmfXtfRGU9I8gx2oSo3P3JpaWS
4i7b8C5LYYqN4s380fSr/ELm9762wxQuFb3OQV35CYrGfZae75wlVaYMdVg0wkUshAwExcwfiyWC
93kC7p4vuX6GZ3U1c2uJiTvKW6nTLTKQRIZj2ZL4beaSqxcyp30JDT2iRP3I/sZh0emTmjbavsYr
fsvDgH0HXkrOF0l0xk4/ghxE7i56nTO6J2s90TF3BvbztnkrpcaA2ZuSajvV3robTc6dZYPaRk0x
jtL9CNFhMJflP3l3zF8XoQXM3z0L/ez8SQ7r7PH5+Cf+1huKUYQ9QYh9Up/N38ByPEg2jnR5beYg
4hMZ6CbxcqC6Hv1N+7jKN1haKib05kiLmW2v87EDiE1aoLDUfn6B8iNseEK44M8jM9z90Vo19LYh
UxMSEVg5/LB7fMnJHvEvhwsdrUAZj+ju22zWEQuQNgcjQST8B8Nuuc5ejj/YUqUNhVUuRq3iV7ki
Tp0XUZifa++4Il0dfnUmDqYnFRwmf6S3c6HciyYm1q1AxPEA6fYeQlEnudF6OZQHYlSboDBn+LHQ
3aPBjg1B/Y7UZWyFk48v2FL1R10yjMNysFAAzdiw/GmBXXr61iwwEqLAoPX9+UndkX/d5IPOzl+t
5g5f3ZgVuestK1pinfrD2sO6qQogUytl1uKigZ1jAEw23/UN8rJXZxUhK1yFl+m3pMGkHOhXYduY
5rDTbWh4WlNsyZbrbaQEoughG5aaMn6+cib5bfBN8AHo72tcmFatoTJSjTgxAi54sXX/Meel/TBN
PHdD5WjlE0Qz1VNtFcdTBBQPiczJXMMi+eVCDWywVOOBXXaopPleEiwjFGo4OY9aNUFi5kjIYp7g
NVe8gvjzku5/g7S2LpdaNywl22Pak8l0BsgsrtW3ohF9qCTwmfouPpiVY2cQwXpNYLNYAU0fCAUl
7pXXBS6JmT1owV2QQo4pBewwlEzcHuhmUW9j8uPOaK+MLIXvsQtY/DsGXUnjRFoAH35ILagdMeHz
yE4XXQaDzgMpIFIGXsB6Uz9CYheIqhNLBRe7PoowvBjodihTlcq/6cYoSCnxjTvi/b1xuvJMZ18o
OW1h8AFQDSf1CgAxccPrVMNfC0uOH8r5X/kFdf/iTh3KkUCyPqNykz91ZVrwj5LmAUQAUKCJrNsT
I+nn+1UmFxMZl8qYyuqCfPiCRIQkbb7fczPBm7NFAnJ4Kn+UV+MsswMK1ltqIIn4/WhHZ83zuxto
rtnmmVEEOXbt1Rdp1yF5NGPexZwvl8mYLrb6z9+zL99+09IA++Hl+Wxx/BRXFMWX0FP/pvVInoGO
DOgh1GOm0E1Cr/XLyww8M+rT/nBYO6FA5TcNE9EVX725w06r29u1z7VT5tMV4qGgbcAokPcuUqPd
UeA++H/FCoiFPaXg3InftV1b1HYGsPbCUQv+ToG6YDco1Q/KFBlrs6F0A7qezumPz4wwamjLE/l5
tNViLWwpy48r2QmSpIxZKJhzeMLESrypI7l5jbprgQe0SAO6iNSa2PF4wRxLYjrbSkN9q4OUo8qc
wCwqtkHeO0YoqCFL2szpSL1W0MCyKko64p44zQhDT5hNoT/OojxMYkJc7v2gfxYhlnNvjZxmzs76
DyUo513FTvKA0S/vSTtcZidI7Cv92pTA1/e9T8XJ7UYJeQmRtBSg/G59LQ2JgplUbTmx9qmt8nlo
OYnQhuTocVSGK/QQwC1+tBZratZDXaFES45ByUFmCAY4j7mrTsNoP+lhBzyq3zfFPlvZ3Cdu0Lqz
g4rR/nQINhZEKMGk0wzDLRKpYJBMHyU7oFiOxYUw3AOeKhjUitpSwCFdOu2bBblMo+RBlai7xW1K
Gtw8gcNxBX0xdoaSfgdgLrMcjQziaNEiKna1HW5iDlOqOEJuH2j8iQx4uXg//+HqXT6C6jdZftpZ
zYQ3uEXpWuYvBHqI4P6JdGAcxgDQ4y60sBb9dtTPHc+M0NerxBv8prHELx2d2PNphyBlGntUNQNy
9VL9PPLyT6bmTKl4DMjzjqqQVdxF3JgZrkwFBiMiDdvoU+x8LCOM1brTqQG84HZnue7IA0e8cept
KjZ07kGWJPCrKUx80lzjX2xd81apqqXU3i1bpArIknViTWfA9Upm4W2FRflFFfx8MxrdmwXs9Y3t
WU/AqABjGU/3KYUTSlMnozrHEedQdmB73JNn/gsowLxaHZnU0w3fglyTBfHX6xyaT9S8KYf/Jl5X
QbCJE6ceJeaEk9or+PXE+IthV5fk0y/JyL2kFlPPr969kDs85CST4+UAy9gHNh5TFMqZKy8Lkfhp
ctP7/guLJN4Y0t+hskm+ZAJ2MCjP1pd5ULxrp7CeZO41YwocxgpP08mMmxCTKzJXNxaWwxbd3c4F
5TKFL0VQUclxJPEn2H+iIXFcj6OIeVX0M6j9FwTsC+lx3y0tvpOmdnvlj4nDHTbsuS68qlPdiXoB
OeqHX/Wj+eHCG+O6f5i/AwDFvUoGZVos8Sv8VLFIrS9auIrz5MzaM+2TvUVVKeDPaQ73oi4lHRMU
F5jL5DQkjDslCxSfd18CwlajR7qz6trVpxEnZPvlS03S1uabj8tsSEfsfXc5j4NOoWqGUlmQ9n1G
avWxb81rNnCmm/ySjQkYE0nwwEEEz1PqJmGKT4m7eYsVWWTb5AT3zYlPoT3pd/A351zaE2mdqTm9
19V+WUv2NSlKmivfH63figXSFFNCJHrVqbY9oQD9bbypt6sOawnfimUllv9ThgSyAbzfF/LOhOFN
UxTuhmx5+0nKaWrv4I87LLTPEv887lcE9hDoNSNnM/b3TQVyNumP6W84KNVmQsAC1d6HQZ/xGHaR
4vxhmw8qhiL00USKFg4O/j/9eW2ZRQ8J2gS1iYrDsxjJKuDNPoxaHBiNSn/wCveMM7blaxyH3+Fu
8/0//tunJS/6Ki0BExtyVW91iQt08SbWfw3IeFOqZUDTUk4PJSnykQf1Zj6gPsXgKE0LYIXjC7f4
IoQlahcMY9aOpXKeyVqL28frm1MT+M0l53wv6yc2CRM+DHjgE1KvlMPXtgnq3oTwyqpEy2LcHMdA
BbBZYi+fULMjqF6aGONqFs/sQhqmmaqbSD5fFnTmW7Mms8MmRdMNsoMz5W4SBjscQkhC3Z0CfbjO
DhPLLe19TjEJWxKIh94rTO9a1kcFzW4RvzadfiBvyWBBWj7M9pPSYD8/Bu5iEBABVjzLO0nXnAX/
U7x+8rWS9nZ0jwsUGpnaZlknChVQ/ETTXm+yhuodEu+zTaImDrPAfzPEmfpLJrlfOYT1/nLI2eVp
XD5+niu4OiWryJq55Ay31ChRAMrvmumcJdyojWE5pAIGLQsBOAEQjNLYr5p6MwOMcUdGCSofwFbv
BGr0fLiMy1EhWFri8EgFsz8iDapK7VvHI2TJthry6A9B624LGPty++0K1n6VOJMo2XKvjWapZV+z
p1ze8vjOOxGjhBjfpuqC2t4KYHidg6RV7hCRvRGu8a0DIWGuWYHkfdPHt+CyrwYU4J1Zlpt9V1tL
aqlSxw7FvMNdf2OsQ4XkcG0T04+um94p7l5J95ehCHTXrNmSUOZbK1n6KpUIeildkAUa9lSjKKyF
FvfvkJBKZl607gIG
`protect end_protected
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY unisim;
USE unisim.vcomponents.ALL;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fg_tb_synth IS
-- FIFO interface signal declarations
SIGNAL wr_clk_i : STD_LOGIC;
SIGNAL rd_clk_i : STD_LOGIC;
SIGNAL valid : STD_LOGIC;
SIGNAL rst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(16-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(8-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_s_wr1 : STD_LOGIC := '0';
SIGNAL rst_s_wr2 : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_wr1 : STD_LOGIC := '0';
SIGNAL rst_async_wr2 : STD_LOGIC := '0';
SIGNAL rst_async_wr3 : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_wr3 OR rst_s_wr3;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(rd_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
PROCESS(wr_clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_wr1 <= '1';
rst_async_wr2 <= '1';
rst_async_wr3 <= '1';
ELSIF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_async_wr1 <= RESET;
rst_async_wr2 <= rst_async_wr1;
rst_async_wr3 <= rst_async_wr2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(rd_clk_i)
BEGIN
IF(rd_clk_i'event AND rd_clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(wr_clk_i)
BEGIN
IF(wr_clk_i'event AND wr_clk_i='1') THEN
rst_s_wr1 <= rst_s_rd;
rst_s_wr2 <= rst_s_wr1;
rst_s_wr3 <= rst_s_wr2;
IF(rst_s_wr3 = '1' AND rst_s_wr2 = '0') THEN
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rdclk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
------------------
rst <= RESET OR rst_s_rd AFTER 12 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fg_tb_dgen
GENERIC MAP (
C_DIN_WIDTH => 16,
C_DOUT_WIDTH => 8,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => wr_clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fg_tb_dverif
GENERIC MAP (
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 16,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => rd_clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fg_tb_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 8,
C_DIN_WIDTH => 16,
C_WR_PNTR_WIDTH => 11,
C_RD_PNTR_WIDTH => 12,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fg_inst : Move_FIFO_4KB_top
PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
VALID => valid,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- ipif_reg.vhd
-- Jan Viktorin <xvikto03@stud.fit.vutbr.cz>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils_pkg.all;
entity ipif_reg is
generic (
REG_DWIDTH : integer := 32;
REG_DEFAULT : std_logic_vector;
IPIF_DWIDTH : integer := 32;
IPIF_MODE : integer := IPIF_RW
);
port (
CLK : in std_logic;
RST : in std_logic;
---
-- IPIF access to the register
---
IP2Bus_Data : out std_logic_vector(IPIF_DWIDTH - 1 downto 0);
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
Bus2IP_Data : in std_logic_vector(IPIF_DWIDTH - 1 downto 0);
Bus2IP_BE : in std_logic_vector(IPIF_DWIDTH / 8 - 1 downto 0);
Bus2IP_RNW : in std_logic;
Bus2IP_CS : in std_logic;
---
-- IP access to the register
---
REG_DO : out std_logic_vector(REG_DWIDTH - 1 downto 0);
REG_WE : in std_logic;
REG_DI : in std_logic_vector(REG_DWIDTH - 1 downto 0)
);
end entity;
architecture full of ipif_reg is
signal reg_data_we : std_logic;
signal reg_data_in : std_logic_vector(REG_DWIDTH - 1 downto 0);
signal reg_data : std_logic_vector(REG_DWIDTH - 1 downto 0);
signal reg_data_be : std_logic_vector(width_of_be(REG_DWIDTH) - 1 downto 0);
signal ipif_we : std_logic;
signal ipif_di : std_logic_vector(REG_DWIDTH - 1 downto 0);
signal ipif_be : std_logic_vector(width_of_be(REG_DWIDTH) - 1 downto 0);
begin
assert REG_DWIDTH > 0 and REG_DWIDTH <= IPIF_DWIDTH
report "Invalid register width: " & integer'image(REG_DWIDTH)
severity failure;
-----------------------
reg_datap : process(CLK, RST, reg_data_we, reg_data_be, reg_data_in)
variable DBEG : integer;
variable DEND : integer;
begin
if rising_edge(CLK) then
if RST = '1' then
reg_data <= REG_DEFAULT;
elsif reg_data_we = '1' then
for i in reg_data'range loop
if reg_data_be(i / 8) = '1' then
reg_data(i) <= reg_data_in(i);
end if;
end loop;
end if;
end if;
end process;
-----------------------
reg_data_we <= REG_WE or ipif_we;
reg_data_in <= ipif_di when ipif_we = '1' else
REG_DI when REG_WE = '1';
reg_data_be <= ipif_be when ipif_we = '1' else
(others => '1');
REG_DO <= reg_data;
-----------------------
ipif_access : entity work.ipif_reg_logic
generic map (
REG_DWIDTH => REG_DWIDTH,
IPIF_DWIDTH => IPIF_DWIDTH,
IPIF_MODE => IPIF_MODE
)
port map (
CLK => CLK,
RST => RST,
IP2Bus_Data => IP2Bus_Data,
IP2Bus_WrAck => IP2Bus_WrAck,
IP2Bus_RdAck => IP2Bus_RdAck,
IP2Bus_Error => IP2Bus_Error,
Bus2IP_Data => Bus2IP_Data,
Bus2IP_BE => Bus2IP_BE,
Bus2IP_RNW => Bus2IP_RNW,
Bus2IP_CS => Bus2IP_CS,
REG_DO => reg_data,
REG_BE => ipif_be,
REG_WE => ipif_we,
REG_DI => ipif_di
);
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PKBrZwK2vnS9IAX2yUsPA8owggtCeYCIijEt43eGMIs6BskFWwAF1SsmjEhW1a701odFFZ6Uiv0W
kJwPHC2wLA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
f9gYSGw9T6TKVLxVWncwHKszW7oqtbpwl/t/eA4nKw+rK2Sdc8GngR8YFKCo6J1YEOzadSBYQWyx
Kjwoz95us1DaU704NmSnpCUeRI96W9A2EZf0HPwloeywV39kV2+1o1TZ4dXle/EVUmuQnasx+ANb
bJcfukogtfIt77q8yfI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
liLfrnIHhASbF4o7WF+y/Vzafk/qkzAguBbMfF2WnCviE4Z9Ns4oxsMUjmwyQcKNcTa3O+eq0fI6
gdSpYPCtAvf9q/mD51BosWabl6O6InOyF26gDYlxMvHSbx96JpJVcZPjaE4TzqMkI9G77c1TYks9
D6AuO7f8CW466VThudIBQecvncFKRxr+BoSt8K6r8sWqz1ofGx4JKwXd0KKuq/RK9eGBTWFrlAQJ
PfaNAAnySYiWkLavjm8Fk8b1lK3fzU/wh0+97s4jbgND6+Fi8csipwr8Lq+obacf536N1L33siDR
2BZ4CsxAiT/PbmDJPphRmQsKX39ggFhD9XUFXQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
v7H/SBMc/o+5F7cg/6gT6gWqJCsq6RoAoXg2mTW6GEWviQHiQPjb0TmwYW2GE86rzMnpGGERvB51
XyifjFFv2InOmXIA/eV2K4cpAJSwZjtFeePoBC3alLnRDhj7l7C1Yl4svCYsJwZ3yEm6GCIYBgvu
NBowIvMPQbFDhAkEEac=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fuuk4sDGxKFpcFMkOSixyjaDfOJL8TgZD4y7UpgnaEjwMCX6ELTvZreKNc/pmhyg6lv5/dsR/3xm
4HXXS4XXuTi51C7nEMGywuyn1Yl4jkE3StcmlHa48kIeM02bnJY/31Esz+jiLt8mrnAQZ0hYb90f
Lbc2RXc0RZv6RC/eFp/a1miXaNWZHhWUWZu8Yg4i/cYNBL8PabUzKs4xIbR4IOg3+6yeGtI59LcE
QeeEPNK+Iq3m7fw29kcw+H5QWoxx58YFR/hQPOKKPkbLk6ysl7Ah0SDLQyufXHDyThJ7f6yB1OTk
n2Qn//5elGCD70O2c1Yr4MunleIYAXh1H8KrFQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17568)
`protect data_block
ScFtLEIvsmQ86LMNGv2UrJODc4kiEdpAvDSVjykJsjo2hMmkwnJ+DKPJbKBRsDsRx9tLJZB4jUbc
LeSfP545QLRmAKlxQOjyA0Upg4BCDLOIBruQ+rMVmP5VfyqwePcwha6qhRWoguvWEDy6R6mibR/8
+CzX7MnpXFYzAomyp64G5vOoOBODEQhqqmxZuzmqfInj/3KBvWQi0vjxPJiH9K/+B5QdIs7qt/yy
Xq5i6wBL546TbTbIanIA/ZlfTWr8/Ju+b/Dd8VOyc6ilTUC20yy9qVwyHDWDSQS2rLlKsqROzJk+
vAfNtCGWfeVsPsS5GWHo3CokgqDyz46kE859/64/VCIeq7YOsQ7A/xTAPPbV1pyx5JVUOOnmbH83
WuvBct18OKIp9Xip/4cYtGK09erUkZhc1MHYZJ50YnLlvTsfPMTI0UcyBdHubmCNj3u+A45/B95s
yRNAFMoWzSVQCTlXVZy6aAcZJ7pXdiFhxl0msJjng1wmEGFtiHAsAeqB4boQ1JqeMAFxHpihYSRz
WCtIS6xpsGDHYzjkVqELOnwOIJFPVzwy7/BisUWratukj0SoYrfvA50Pp5mitZ33hfDWUmPiSjQT
1G8MEflh3EyYSrTzkLOfRkw4n3T05e1egJdkSfzEgPu2FdtJeA4zmO13KBExVB4ezpDGrJ8cRIDd
FJ9V1/ByujLNCfEyu6pD1AqgM2cXZO96H7itDlUkgrQanAh1osDi3r16FV9iQObQs/DbIWhfztFI
YswEFhtqEHTfNtYSprGegrttpJnHWdrsP/rZi2J6JfE1dPSDF6/HUb3aGvnmocMDfoXiNTukl7jx
Z4uZNIMPrWikfQfysZRTOAR+wvCNhd6gno2IVFonsxSWUMwXFoKGuKa9/HQR2/3IQ3/44cbOAU67
uahkodLI7U2nxRXySmB2iWz/LWRKvslOlCPfxVWIRbOiTiZETtJ88DPFmwMsjA4gpRfctEmBUi1j
fzyNtQY6sBc+S9zq6mROFDpsOgIvi0xISUWqHxIdsP5JEC3/R5BkpDv6VB/e0h3WE6FS5HG+koBe
Rn6Ug55wqJg0ngY2XioUMrd4lJxtNpBRzgVqcQfClvVo975JnIu+KxaPbp3bLpUNy0mGnPYk7yX1
ipvxdlzQWolh+xgaMmDM9O+Ly6je2z6+JsVu+x0afQg3xd93wYwZBapB4UW0QP74Aop1SaNCTq8h
vQ2tTzWuLHYxmprPCngeb5lyPxXu3NGBn+1F2r7M2iAEwz1cJpohH8DkBcp0+VoqVIlKVMDj1gKM
MM6QW5SrWAj3zweS0H0JBqyW0u6JQ23R0P01zSwf+hnwXTMmdW35bo2M4QkcYm/9gwD0g25Q+R4a
9OnSq+JaVGl3eqOhFC8NtFf8Mlh4PEbfdD/QUpUBHVK9vYhcZF8gbdYI8b0Jj8rwvFM8OMwcwfNn
JVtlCrAiDWxU07gwe6reWcqm4JkncmnQ2tVdzEnfCGqitUjfpT8fuktrrnITM+kDxmQaED/kKSAx
vllUDZwxV1akKx5lHfWFbh6DJKllyEz/Jvn/3x5kNNkAs/v0muwPxO/T5emyH/jszbuIWALm+vK0
bSNPlVx8odPA9toNV+//06xdKRNq4Q3Cm0HhsY3lsOnSGBIjpgPZ5NZlag2KLO4jjKFPsI2wWcYb
MRn4HJp7JCIgiF7DDUClMPQbRxXau0s4JtzKlzqgG7nV8nAyflE0vIbX1uONkvvz6lbKxhXY0fwg
w3mAlq9TWdIM4xcHszJ5ovXlWDydhlYLCCDfTtvBffSbJuKhXxYQpvrcDkvsNer3TcpLoTi9WfvU
6DXoegd3Z9Q7PxsHOw7Mpt4GAiwxsgkn+pudc90nYW8LFD58dNkh97t6EiGIc9dwKlCjI3IvnzeL
7VuYaMMZtF0AtJHLRNOliXLdIFa1oqa328AjCCdkfk0scilZUgQmWymqRU35c1weoGnY+PEthe8H
u7fLGFMxPeQo/q5KhgLPjQZ2tMvbsBycokm5Ip6Osxum7vN8gQKg2hBVGDvNSBVtxGEedZWqVeRa
V4thaG+S5G/LtDyBwp/gPa3hgtGGekH0FVHzVCsM04uhdbNcv1n6v0HmAQj+t03Z/59+0E6N775C
rhrVErob4i+ZFoX4DI2fDcdUv8ogWF/owk0xbLMi4fRGXRdfUwidEBHvpAu3r3arDiQ8Ki8szwDS
sKXOYENN8XYO4funkr0q0w5Yob+DFRCwyWeHDTN/PEHkGZn+Jq+R8jhXIbtNvk534Gar0aVu4qJ7
A0pHSEGheQ/qGo9DKlroOAvxkSPgHtRnat0pPqHyE0MX0rIyppNM6fMwjc7sUESDqK3ICMMcgb+u
iH7e2Sozl49zZWYLA1hVY+IDMIwwHNB2rjx5+uKL/BQJ8Oi9xjLeHFe+MRP8rAVaiaBBvteY+Pj5
CXDDS4QEtGRSkuZI69xW5Q4/ld+CyjR4K3fZfFF4hZfCYahOgBgWbi7G1L/HyjK+F6NLcAnXLZFW
DcHb6SFYdWzeVqndtdtcawExmNZxlS/kiuH551vb7kKoEFmWQKWEp2bLNg9PbpF66LXLFsLZbUIt
74nfonE7+FyLrbNyrSlf7eOyFWmXwOUvFDLv9oRo8mPkgvs4qsKKd/RNPcB4XBPseJdaG8+BF+ie
T8URM3fJDsxw+AP9MMPhutOCMXXOVHFp++6h+yIpejw2CEUdF7CsL9cYcApobPYPz7gDUF1TvSQv
83wlpWiFCT1yDgqP+bxhGHOxxJ94omFIrOQfHNiJjGvvdx64vwJKq6mwHCsSbVbT5Sngy7fczQnn
ZwYVIb6ihs11vi9XjBg2JfMLDSBX+pV+aXM1l6C0NQ+l8r46qb1iNQJGm34hraEYWX0YTuBebL/y
UVQHNNS7Iqv1oqptUw9ttLq4erSAzITqHCCQCsdjKvMzAI7rrhsmIF4sB2HNHZNKp1ufHI5J8GM9
JFbHOZr7S4Y1vBjdiI6R65TZXGnLT7G/5y1oYmuFa3HxpEfU70urkfx48R+Gx19EeXu883ccu915
LNUmKyJAeGGdpZYSBq8OysPLdUgoDlY4FkBOgomcTn7A98zehkr5mNHdfDWqtYVJQXXBY+MMCG0Z
4ZGcSsWG/26s1+95tSSJJwlB+rbdTfrWBZV+Ob9ofOy+t8Zb0tzyU1gJp6GENuvmP6vfElkMa8H8
SBjSqCgC7nI4AneoHCoT4QYCLd4VnyZGNeGXr9klABjDMfjc3s6YlJ6c/itSyV4hlsz4UwCo+W1F
2l/ewSw3yP30o3Z5IOEZt9OoOJ1wquToaYHrNjBRMxUoMmrZNh2Ipa26MMhgPSTcYzFoH/cL/LTd
ghc9dOXftSGPxeXKhJcN+wMLrJrqjvdE70X5P6Lg7smUlY6zFe1KUzbpILngGQwQLZujszWPDGaZ
2wVWJbCJYNLeAqdnArLRPj0C3NPMzZxuSPE0gOrs1/YPVmhl9rtyootPkcIa6qnuWnp4cifoKqfE
Ph8EizNosr9pMLBeCX4y5lMQSJWC/ls5QQajhIppfG1EjJbadCmC2+cLzihFgx82z31mRZznrlHF
1EiF0vOT7i710WGHqKx1/u65Djq86qm33cr/chWvWMz+oqkXRQBxbuYwfhSrKzTd2kzVHOtqq7QE
VthTzvoSbHV17Tt57qGod4dPxlrCQnQyzSELeg1sSAa7YCuMzR0O2oF2vUOM9K0Rv6OgkelBojhl
UwsgLuUsTirPawtI3bBGfO4NLJgt2E2y/rgy+P8xOZixGNKZCxXo898fRrwE9vC/BCsV1F1zalXq
CLbDw01IMFJgJJjiC9ya11EpWpeRcWGm9wmkTrVnlbQHd2xu+TNqABwGw9JX6bPZNkudPpKI2+rM
Oc2JeukGUghtbIaMwGbm+LfPT9cLMX4ci4ZjxEUgGFHnWH73PWs3HvYU8e7GD0skO9NleLITpZ5j
DJf+Iiq4IXjIS4PBp1Yg/d5gaBe+QpNhbXhwBHB6vt6WizMvrTbNH+OC7RjYZp/tlx6alxDgU9W1
vRPj42S5qrFkUM+8Q6O3zchJQnNKG1hbwpcNF+A2Ntdo5AvOJRqdsmdVKg7Jh9CQOGM2WutAT+yL
kBSmT7OSgwIstmLRLciPsD6g6IgWnZG76KQA1H2IbkKVlXYjnsZKRltK69cZdWzVcCJiuKKcZuy5
+pzPsFprvgWA0MXi4HneCMcSo+j7WsgEs1MdHDyDPdu53HW0MD9XFRTICE6+hKisTDX/nY48lhJZ
QR+UEo9XQA94meI2VNotiuR5TRZCyqwWExTmWAMKWMxA43sexNdKLlQiX6G+Cn5E7KpxOx2uyPIE
haR0cy1nyM4eh8JiNMFfb5iyI6Tcd6semfs4hn5hHpicvv2esB0tMR0RnAunTsaxuhHsORdy9P9B
iM6WuX80fXImKezy3DDxpch7fGulLCES++UCG2Rdm83kHYO4hVtPmG9gvKmp/V9c4fq4U47PnLQ1
uqscN2Scch4cm5GehOgVWa4M4k64LoMDP06+DexbWGtob2mbU4NvO4bOEcNmby0sGaGlR7/jwdGD
nYmhQwYDYkCtGSEZyNXYwTfh7FxNcbOY8+uAMc8Q4Q0FGyiS2mbl8FLQYrQL3V9wawCs+SaEvUc0
EwOFD0nqQg4AcxSC/6eZJqgYmBAbLC1tN2qqCXA8wBJj4J5XfF36lIyr+t6VmnX3dV9glGlrz993
lbQ9ZoXsuTz24GNtwvV+PaDIdpkmP20lEY/JNX7KOuCNI9dfm8QS2sEGNEQhvir0oeK8OGpkTxd+
3cqxpynqV1o5OUiOx7IhDfhYCjO82Hvle2S67ErR5km/tQ8Tylx68HHb0FWaoIVPtcr2sY9J+whG
By3jmkGgoV2iV/eYhKOymMiNQe7Nf11/XnX34wGVXvvEWZlQRgAyLZ++CDwJx6oFQ5Kj+DamPmGu
YMqJyy/aR1en3vfH4Y0WcxIKnb2lPFzefQpnqUIX4UwiFhhDsCroHIGx4brY7fvEgyVHjCU7a5Xj
1b5wNRYeGkBoDRfw+GV4qlR4/GHALmtfoQ5RuEqwhudNzUxrhKB+8HDKYTeHcA97ZeCad4JfLQuU
8JDBCOMjgkDKjlsGGwP7B8SKs++XpmI5QMz6poJYYp2bnhpg3XV7rMtgptBjI/6CE1G503kvlwek
CCG4WhGqkbrmK/scHMM1zL+uzNylNhzZ3C+Rki3UpJ7L+xVrGVuVqDYMiLMcRnGf++G44MPo4QDs
LC02/a1PT80hetKQuzmjW7+PpNe65Yac9XmcmTul7T4Bxw7nfHDS3cUZ3ZLivwmE70EQGGlc9i0H
zZTv3LK1X9QOD53VgNppKULd6lexycoaXHj1zRCp0vtW6fmdH0HCGFOKpHsURlAHFjiW1ZY7oUnp
+DeutSZVBSo4aM+GYU5nb65Nm6BAG+WBFBNug6gobpa3RpQS+OCrPE3UvX0uFOjbMOV3tjcZkBA1
MNEbdfsK/FBIPdmod28uYbZFBJFn6RoS0vrEr6N20/Rq8uhvS6mY3zy6efPg8+qnPMSql8RG/Kwf
wCloRHyvS8/aWZfawTTj54T6l0NAjg9l3lS8ooZcDoe2Gjo14BT0pXVQAlq7f5iPJsSKy7raVRqC
18Q5Obc4Xt6LZg8gPhLOwoT3i4PyEeDetu9/ykuv4Y/0HxQrMVPXj4KXw0TD8S0VAXGchaSNvN4e
uRjK20XiM2zv+q/3U+V1rITTNPiFMShfr36iW3X1d3STSNjeBhiYU0Iaor+56bndJJXuAhkHtyMo
9f61QttdnL8h+aRQG1+O4fq9fXXMn/nLdZUji5RvriCs68OI8grQcAh0pFxiTYxQNtVAA/R1E+Hh
lmMjOnJiO7h7RSivrbcYUtpi5wTuIgqF47AvrOMbSTqnDiSqqDWcnObUOnkQXl6wcyFBJ95pb41p
iYyYgYQ/fs+K8POH6Jx+gVG2Lc16Ex6wqx90Wcs3NrDfyMvEuohcTrRj0ZU3rOmUzHI8tEZyLdcS
sDTjnmF0Dt87vo11BeH3Nd4Tzv/t0l+b40lPnJbSTTOWrdHwmKT4WoAzEnvxspYNodGrCYlS1p8B
HdYF9b0TKRQypAM4Hy6uDpw/eJhdXvDV7eNqyfBk80Q4774Ho838bUSzTCXbeI8E4DAK/hNItI8Z
DVxXiVdLBtRelCvLzM3fA+ckATxi4xmmg4y3rB7n3GN+X0AfcyF7swrx6eHOzCMSuUqM8NlBytU9
tVVh2DJV2+3ZZmk9RfFYsItsSiVdLIOGAPFOQpSCPC/BeiOZ6ugNLBAUNIZDNBoM9XqquIuKmrjo
9MpzJ0zEyZIglqSDcdJoU9dDxsLk1N6DYBQWHG5GH1hHBzenM7jFmp5cit1gTSLfrtcpfc7SXruX
cHDuy1m3cKfFCdyhV99HbgE2jIzu8gcWNaywdHiogJFkaaMdVP+qNqMyESGIF6yngO4DeqXHRp/n
QXvfD0Jnsc8xtlVo1ZQc0G54oIoxLTN8A9wibAwGdA20riKTtp43KgY3QbUYeKisFdsuSJDj5W7d
a5ZD23B5LQ8d0r0Ewm6v9fBovl8EVBhiQCJ6H08qcTrbFfYMAKc8IpsEeQ+dqU8An4tou55ceRW4
F8KvEZxzlbq9O/AjdiuftvJwRYOpaqyhzMzBJpZvMT+daSXbYuH/OBF7I1gqMiT+tL8YeCJ8+X8k
9XgiDsstdIIpuUJOClqkxqOxMAxlEl2iSe5cor8c6SMZQZBhfkj7KKub35odXqHdXwz0fgFcLSXi
0Juy663hWBajrSvt7Dc7qn08sGxpIoE70Aoi6sqG+y1g6OAUkIefGkOvwgXwvPS54jUhXwNnCjur
JK8boz38FxiognIjcXQh+xgJ08y7vZeo6PVQGD9tEwvOHiAM5nM/mD0HwRfqUTz1M6BEZj7JOKzG
SuICXTIjLuyvBhVE+Aghbwy1cxl1f9N2oSJrEhA4gwceBr0hvsKmLYk/O4t7xGabX0hagIiYaDJW
ZOa9gR3mIYYN1Cadole34ioHLLYCj4mSDPOh30PrGRLQRiuIyg0PPIDLp1zNQqtsoo1ag3cciDkU
jI71hKNvneC9lCtfsVTbDWHbzXsBt4QbDsPzEI4J61Rwjba2884DRiv1o2yJnbyh6NIZwiwzfgZo
bPGTka8pg6+mhybbOI1vrGW49Ob0CrKtSo9WhtBKB3irOydksAHqoV2MjTshw1G4YUfQkAv5BHMp
AFpL/QA/uvKfsLoX3AOsJDBfYlXyv46BtIaBqNTOsMrmmi+jhHO2blhEV2psrB+xyg8gCp98diye
fBoLf3804GOacvjWTLf31RK9ADhkctJ658zpWnFL8aqvMlK2f3qhthc1BZoJP9j5f2Wc4ExRxx+Z
OkhqJCTcb2Xzkd08U8bHg3FHoUrdaD93GTRhocg+jFxelPRO9SsV/ABLFU4Ledeb6/h4b56VXzCq
QKlTIyUhrSFogsnb6eJqgams4287rUnYcpfFPK0bY9lKtdrraOwt46CmncqjyAw7IHixllKpb2Gu
JRVjA2xKONfaNC/6hjyxN71vD+Q4Tcrw1efa5NgvfxlHdL3F8mE9cDNAwHbn6o/wGSXn61O0UJXN
9YzoOnCTUMXkc12DJmyrruL+X7THAnpct8l7W+b6jAF3xWvW8uQ7Ycim/aPJYLpbCweAhXvifaWa
+HEZyZMbClu6jNMjvjZOLspp9lwdSykG9Tye9Jgo/kfY1DxDTTdOet2+OWtsCZEj7jPq3VEggxJ2
CWQjTj34bwisj2Mcvaaz6q1BtaYH8wxFvfwIo0XY8V3fLxOZXveJN4qmi2OsB2CCIPSTnxHxAhon
XrTI3Mkl7g20L6EvdWYE65iNMINFrYJio89k0U6cMdfJdquEwT7VnsF4Ew9LAC3qv1tB9rXG4GSm
B6Ga+057FVi/Xhdw46YHlIrYQmfP6Qw944s/ekkFIw2DhJvxfreHj8SSQXxmmucXTyEAYSJMeZEl
sOpWR2+FYXAbjWOJwhl9cBqdb3qjYcBtvtXnAvo9rnjw8JmER1Gr4qqu/b/qICmTdB0SkmKPWgt9
JlYJgiwwdURQ894PjEnGYrUMyS6IDs+mAnwMqrtbxc/ZMfZgYSV1/O2xUWd06AIXxj9rS8l6m3SZ
v+v68FD0bd+WNQ2EU0C8ZwHNdZrFL94aS5VmjcWVPoZQIzgJMay1nPjdhrK+8A30QzSKfajejwaP
gf+x5e8TVNPQHE0ME8G9zAqKpjC3a5bp0B8zf77IqC/yHqo1PF0Kji7pfrympncdPmtCsPWg7Euh
kTGusxFzX6w8eLSmgVH2KBTjZ7FSsxsWZKzUF7a8W+UmGtibbfZn5JqrbSrU4pdFhkPcjbv6rJgE
75FdDYPaWuaL2h86Z4jvHsWrcho9eyYJDRi32XH9rn0XtW6eKVi2AJT3ZnYljyreSn6y2Gd3sbrT
BHGcTtm0jc3aQmlsH7wmToFg1rw4Y/yp3c+MZ40yfWuIicLdxarPubADMQuzN6IMrmYeblU1utuL
HB6X9mmzDAlxlOb+LKHfiyxio1daMfU1+zpN0v0+27Q+dUZgm8RUfbQiD/o6/QCllUXmDvSoUAKz
g0562eJAdQmpDTCtlb90eFEHdLn6gb9Jnap3mhw6xNTrLAcQZyag0eNL7TMruDKbWryYTHaJv/1L
kGGrs+hTk5YW65z+1RjomwANRcM7N3D9OqbnXURekbEWkYd6gO8FG+DctlYX0zQyGeTj2MqVndn8
GRVjuAwNSI2LEoQ3J8ANdpZgbSOj6jeAkrR4NqK3d+wOI46qC5h4LoKYTgj0hnJni/XgNpRHOgO5
jX1JDZeOig76ajFVypEtkRQCgm/2dFrESKqmQV/UGMZ0uRXc6aEKqiHGZYgoTxpKDLy3pB0fe9Ax
Cg0zhzCZkju8c5JsCqo+HzrQRIFKrO2nQlR43CtxlvzC/8GGdDTiCvr9YpQc60hz7flKUcHOj9qs
sDNnpG6UErhLy/IakDOwFouOAZRun7GHk0pYlxNh41rkxX3BUDX2LRh1cGlkD4LUhr7GZnJkzRJc
Iyd1Wtyg54mPhOtleAb6NpOOq+VwAZb7CA0poFuDmGImFuN8O4Mee7GdKCTGNvVYpkh5iBAvEuzj
u3sJ8iqVPHltc/aeCHB0tvVMkoPmzQIs0LASUTpQrPl3hK6D/OUUMXNHWdNwifylxWfXLWAn4Qp5
a2AialGXYATqcNU3aqvB5jlAYvoWo0fpOGwkBYDe875p5n7Agvu6SfmcXto0Hci6vysQJ/a89/vc
lFK5n2DP2M6frzQW1LHA+nljQK3FfmuYIItontK+yJQRuiyqvukOi9Unvxg6di0lNuRgPlSC3GbE
iQEbG5FlTwkS99lwBhovcinVbfLOa0q8aS3XX2aMLpVDacoZhEHXhskOY4j0G3Ybuzo+Pdxi9cK9
Z6vCxTqTgaqfAvcbjYMN0KQja44q7dcNVZwO7fXBau4zw4GGNOkALFQEnGl7tgf/566XEQ3xw8tz
QIIvfQZOHATBMbdbHqP9BHJkq/nKhQzHV3N1p+DpxlUgRwE9+EsfObkyuyPJr6KlZJNAAx8mwelP
prFHgqz74g21zKuhXibI6Y//GAqH2V+4YU/3JNgl/RqZJkZoZN5k+0CqOCgFBYx5vhnKo8elYhjm
R4KbG9R16cL5U4YQUKocynga+BONcUzRetePInX3qUjm2NxIYllW7UVBYZebzz+2tLObaf3YYE+j
gxrOaWgAQ867Y0hiJmOUF62xj4G2Z2/pIm8WX54DbwvJYpZU9Q68U0Ch9cSjOhj3Ngyq2Ef59itB
/3f59uu7TQvYx+IGJx9vcZPhGbM5wz1oa/9CCUffRa85DJYVVP7LnsfdQTYfTpGfNznc+1MxIjaW
J3GMs1fgHC5aKjY7JhTsgoLwoTL5bJ9ZtRlrsToDNohUCTO1gh70/2T6eJNENf+azfjPGMAtdbGS
5WvrUzzVnQWD16cGJJOQdhJXgJ4eKSwN2wLhIrTF0dVBKr7r79FN/m3c4YNyG+vJHUz+eAF50Fnz
zIyuu0ZXc8fgE+QlwgEQjE/AUsFWZC2BRC6SsuVTFZhCLLd7hlCaZmUs6LKK+dqDYUMpgHRpTcYY
qkEhlFprPXsF5LywmiOJYHqgtBDeSc7463uvPE0tj8mrF3Toy40Eq0grwBX0QJAFT2rwfyBVZWc5
rHB8NWzTLQwSTAkxOrtmN0wfiC8tmtlHO+frvtd8X4Fw4EOdoMUL1AFYNB5bLpDGq8UNSJnZ1vn/
/uCeiociMt0D1M7CPelwrPnHl/A08ZH5UzKR4T3sbFOM9RvFjlm8pxDOrp+3R9Iu18OHxNjxrZ3o
U7rtLgi2dvw4dGX/t010W1uCcp1UgBLj6rnbRxpL9iBYZrH420udejx23uuRbiC5aTR0dWR9Id16
2DLsiguB9rtBGzmh5bm77NMqRnKIBd/5IOHTz+gUcz9ssBaXGtk7yw9ytBESpf/iUwBNAZ/HiBEA
Xgi3DrvUm/T7HbmetfXBWkSJ3wrokXbcadZk4zcUHCBNFKYp3nbj+HzV5X/EyVsLQGMrYZkYvXlp
zv3gYvpWDZ7mFM3wyxjEdeYhySDN2mmPHL7hf4ekGOMG9YQ1e4QIMQ6gHGWB+L6QydMrGRsT0zSD
f6Ro6L+NAkfpo/yZGbWAM8y4Mnjr09P2cHfVb10AVRCf2E3t6+7zSVJwPyHGGGyklPg1lUOWY/2O
Y2CBGm1I6TRTCr/f7b7fN+uq3mGjMXRwOpx4grHaj5I5+qVlIiXEE/3wAA5S+iU6Lfl9ablcxc9b
6wMqvt/8g8ORdVNkE4S57ZINv9CTdA0dUrj8W8Aj4x/8BLh6jajeNG8lGhz2VSQgqKeJO/6PnKCh
91SUP8aJzFF38cJWFeucJmoimAnjZ6Odvty03SrO+aaHuy461eBTd6mlbKZhP2fcb6i0hqgQo3+D
Q+Ux+WUmyy3LqzvOxsmqXPAu0SJdRAiLKxX5SoH6DM7QlsfP59XDVciIl+adP8CHr/iazd45CU3f
SK08H9CVf4qXRlksYxftcDS0T4ggth2STUXsQ//55tO92rWMzsVNQ17Ef5IGNnIQLXLRsoeqmp9J
jtRXUHFlUQq8FeynOVnmbQEFIFOLkcLq1M0iDxwuYbMHO1zBeaE6Ywr9XUoYtr8j42amEa6FUxKU
girKjW7xMCsiAfBVrYglpv6kO6DKfc5IBDy1IAPJ75hKi4dgKokRn/MCKAkVIPHfXYv7c6AO4OS/
zKUKALtGbzdIdD1/Y9WVJ7Yt55OT0t+/OyuOOxGHS0p4UpjjLD7jD1CXjd6QBYGLb2R1FYUefMMA
7UBWQtHD8UdZa/odbhMMdvW4CtXh5eySPh1tgJYscejZ5u6QVKgRlLXuyI2MZmkq9rNf0L9/aco8
f+zSTD6dKlE6MVFYjh7vTYqSawERnu3RCHxMTyw/6KrhOwMEVLYnkpi2NvcT+DPot+UA3VGx9qTG
w7fvUJJngzEyAXPMxRZzCYN/8+007R/i9Z+/g2Z2p8sFEA9jXBLuqfxR2IJIZAW/DWNtO0nnsPf1
tCSDnya+P4QjDfVQM4Le72YV68mUqh4G/bh347S7/6vwuSnBXJepzPa9sCJAYtxqaB+FBp9w/1jH
VcfAOcYWl7c2DYIti9X3e8uatC76Nql1aP2+2vqZWaLZpDng4KnMEEgWSpyDLmA0sfhJEQ15f7+g
VLN4fHE0vYWunVlwig0L9M46HZIkKFefjk4KEIR+e6XYs/x6ZeVBierj5BBfqVE9L4r0GXsqnZFd
7JI8Gm2aqGhxA6y/JVrLqPDE/inpMKn/u8XF6rdJpDNUPdupjCTGw3JPmn+Ox4FRT2vprA9yT+jf
MaA/L3+dV5+W2+TDStrFOouvZQAYZgI0D2LQh5A1O3r5o7mTLxcvyCR0Ab8xYguhe3Pb75/LXv3K
fR6m4wQlul+D2eO2raenBnfl334iZHo/Os12yoZTDSRVuMtgo/pmWFEkGEvtNGZiL+L+PYu9fxfW
kbfY+6K4AQLh2tVJ/QLSDG2LuuPKvkfgAsvfKWuS/Sdsp8JzkoQgiFnWcNYyc3QvouwJC3rhFdSj
50cUiqsvozBBDyVeEwTqYBCUStEcmS7qtM+JfWvCSBuDMOj+e2rcEJ+JW9i7Fj6jSQ8o7Jtqxr1d
qRGfL9cp24Xk9GWsaHBA6lV4TQcaVcx79VtUwBMhw7rgxMkVrIvxyDIhxX8B01ICN8yyNfuSfbzU
MkTwLJsKPadPWe1S2W+sPRkT/iYjdxZ2rzv+Kq5n4p11qqsTIarWbu6tuf4brtjgmgF5orV8rkoG
7PKYnD0bsIIm7wKr1Fz2KC+nIY3HFac7NDMse3E47qd1J7SAUZXWafmHfxpBleUjMqLcLbPQ483Q
4g10FncfswoefV/4KyC5OOfGXxIhD5EcT7sMG68TRPCGpueOLjvRFRhM8/4ApFLbSNJOUbObqCIo
F7rLUJxIdzBNVtCNFlISMlZEAtaokLJYPNNjdyptq5aqKcvsvyn4Td85cbjVnGl8DhxG6F3d4BEo
K/VoIY1JBoEHqlRLZ8BB+6ZUjpH7C9OAK5NudZaFLGEcxyVDaMlSbhHwCrXz7pNTuBhE0NTikRZX
RPtbmtS28EDLttTEwNYHqsstJW3TIeqwNO1LIjUuzy0ya8/5RQQJaF+iemC0ceEYMQt9iVNSnMYN
olCE3ctAr0Uy5QAHfZ/uMZOTx6/qT4NRWUreytOwQO9EOCJPCm9jdqbZ8MW+4qKdIG/tFEir1TXp
XQ3grCJwtPf+RXFc0Hy2pfQnDDS2kimR+y9U48DaRIM2nY5MahGJWoyXxeClHnlVZcvo4vb3PRAS
KGFg/pGsKvv6agbz02rhWQE8koqAlWlGhiZZMVX2TE9Lz5NiQL7d0WKyOQsKEGc2koCoVMqiCZuS
pocJf9MtR0T+W3rRSyJJ9bvO8RoC0GjeHeRm3V4W4RdqoOj/7ZzRbk989OhIX+0mvkzYfKZ5VuCf
i5TZv3hl2ssTmqx6quS9z17RkOOiqmCKSa98SFnhidWcaTZtoeOzkbS3mYZ0agGF+lyExE8YVYqG
eiTwGJfc9Utlc4/V3M8cEon1AS66bfbNuDbJ0YHaZifBKt1TiRdpWF5pG3+kvFzbHdIxdqHGdcAa
+L0xNPfdw/6n2Keu5mPRjNzpPqYDAJGBzdmatf1kZg8o1XFnN1fdwtnIKU+YQ58IqSkfhxeu7dxS
4AFwJHgBczZx1Lhw3Q9RapP69K6XUU1+pMigTChiaS6koh8xlksI1oVnEXIt/toHjQrE0HKnjPV1
YBElIuBFPwKyQTkBpLaE+3lI/WtMZEH1dEL3CdRqOViu8q2i8DL9cV6JkEQgFNc2tEtl5WDOYfpL
HXCMe24cWZn838680uiQy4NmvyhEGHSmJKwhbIkZCxgXdo4ZhxrmUkTWcNJDFjcc24hfuBCXzETy
GXHEsmxN9DxV4iubE3GyxT+nCjWEcxXYSb069/QDllOjQFLgKOib4/TV7iVnG4I30AKyNU7pQJ2r
DjnTGL0XKNdsElE4FZ5Kjke91Ym2n/mafTcUdZUtr48tUMNFZy5e5fVGaQZYwyqhQYQEpcRIInTk
+ZuZg3avBf/P5q7IKxLlbuxzCMd2r+ehYTsyt+31c2uX0VICyuxW/9NWYFpbk+b98wGqN1P30C+F
vsmtf0wlPA0yfyf7Oq0vcf9I9FFl9hXIQMDoFWWBTw1y3df/cRTEg4H5jaj0zzinheGY4DAz2Io1
KNjNLALOr29xfn8JJEmM+YOzLr4JB/l/mUysqc3BP3gm4kkXTHY2v0AQS6dzEV3dQhUQJX2nVHvt
jEQCJ2+WKmooW7L3ZH39nmKZYYxa3BcIujwcMlhXQHG+xE0t6YwCrOtflY2hWa1MKczMhDSJ45XQ
O1B8VHubc1nbnCtKvMZFADAbnhDq29oT50XQnv0tGCdKY4oumLp4FiJ/jc0Cl/8kV6dHOfgy7ay5
vH3OaL3abi6aiQzIISqqjCx9N4I8J6dxH5aAAOThjTJuAMal0ncHqU3vsEGR5JIBThn/zxgglSTC
p9rITu4iLa2HX0o/ClMOGT14wuVXfzoIXUFTob2ZiXWsV+EDLFbd481VuP7MTXU9zjKlS582ueRd
dGxtqyj560giM+0oZmM1bzIHF0cg/JTsHxkxxdRtgWSmaP6omLzjtTgOwQuyYkv5fQDAaVvJH8sj
lkfba5US28p9bqHgFm41QUY85pSR6LgaYXvgFNdhr5yUN1P2i4ZQtk5jARa6JCgf5HKnvZdp+mSl
kUzvsGs3px0bM/9M9t+TBhvA8uJu6S4XXSmEIbVs6M7Pu93FPEmqWAzIQZzEAnyRVXz7bD2nabBq
f3vMUliXp8KEoa507FRI7+UdpltHbJASrsjOEdutXwdOejs9Wk2RmX+yLHCaN/F/EM9ckiMUwvM8
9REmbc2EZn829M/yG1DiwF60PaWPLNauzwQ4THp8GVZv3ldgPYGwyh3LfKjC+dFzRLVmUM1Y1T+J
I3xMGy8MWYI4XdIGzETbfwrwTvht0eSqfeomfCvTjsCWkc2PRrxNx8OWprQFusF2/1LnRp3LU9aE
pc5SJlT4BXG//AX7B5ER8Sb1ikN3AVhK/AfV2bLfC65qm3LotjA72Fb82eQITe0PbrthdTcQKL4i
VlCeqNlceHd1kgv4BhNVIfcV7dklHF9DJn6YyO4HLbZyvNwdWidnZyQN+FvMAmmLh8lDmdOJq5dr
XC3Z051lwO8yG9wdbpjaBqYDjJ+CXDe9FtwRJn+om5lYhaGUr41R4WkUeP3yWOcHSa3iVOyvAwcS
scJK29kPhWCh+0YweXzXfXazfVPmt6LIgvjYqqlyUfDOPqQA7S3fUoNHBhcjpVmGem2hFQRqtf7x
QcDudN6RX80pueLLdCGPByihuVKpsGMseUPgopsOQhsyFElIe/INC6VGsf2pr88l+Fy7nd4CRtl8
//b9vdRYAqVhzb1Ms8P8ldypi5x95kESb+sMHqE4GtK7WS9X6dN90Mx8dUeL+hBsjj/tVgmzouk7
zIyZcWEI96T2ZFxAVXUKiBC2tLaF+aE7Xgrb40nsHXjswfpKavK20mwaMVMmSfz/ZYP5rGkoDZsu
L/KtUKYEk6Zk56qo5S/exwoUVX8sFpYBxc7zPc+ntYO7jjnYl5LmO1aYkelQ0Umr37MxANFLdsBn
buXrDrnz9oDY6KUJoXfp66xwegjaNuBrN7lkw3FR3FOR12THUjF8BgvYqN8SOlww6GjpEyYNBuH/
scslij2Oa4VRQ9UITnVOOyhEpvAvyX91jrUd8FUT7W3JJeYgTkKa2JCw8myiFVbbQapRGMN/7nkS
AZAJKLtQP3nEBUSiwwUlDxTCyptel+p7Y2/T+sEPsmr36TKL9MiPND+DhbLpHpCb5AtCXSXxFwuH
IW0daTM2kyYaMpbFRgBYeqjwbXCKb4ibQw9QMI33uhW0IFFW3HKZCd07niDC3HMW3gJty5NXSj/o
CKjNI888bD/7uRU6SRNZkeOXkPROwZH5yGgI6p/2THIgVD/KXw83IxCM3B7oAMV4Jn2H+oEqQHKO
kVhESIr15XsAY+2bZhUvmcnav78p01KJTFlD7qMlzgJdiH2GlB843yjhq0pjCs2c/ECnFXdsomfP
vp0E5xgUPZmXU+gvLoVGR1yQEVc+PmeSisY1dSPEEVsJjuFNsGEPtvF7C0jM28Hri03VzJtKKn3b
O2ceiKhSgSElzliiMwuZZOyfcOLgu6cmM2/mZm0/Eo6ePwW8jgjSc8/GuwRls7cZcAbWxlQbd1Eq
9XqnatM3EQ1YnYq6eZbQn9NQmxL1ltX7kMTZ9SDJUjI1Y+855qh3VISOKN4qMwEeKDdbOZ0rVprb
JmZPxhN8E5afmlLpDuexpOTZB/0K9eLyo39dT6f0zMa6velcmmUxeHXoBEuOoU+cb7kDtc+JQ27f
akLY/UyX7g7WD11mJO7QpUqru67c9Vbw2qM4cWzMUraO4AQZlRKoJLiRFVqwcfZQ/hiUzqszeGGK
c3UpGqlVdimoipWq5PY6ALF6KMmP1ZzqxjV58Rh71R17kTPyVmWo1NKakinM0mtGbzmQqfwi3y0o
Py0Jini8h0jbpol9HUB43FUJFPhQABxj5kBk1E9hltIJWXePeo8j8tU4hfImAXMBx2rjKEbER1Bi
MJ1jTuvPbePDjBpSMG4/kUQTbtR1meIC3C35tf3cQE4j17IJkZHo9HrqeyzQEjzqLW/xMEPIxPsX
2SHBikNoNxmyDIlwH9IwkQ9ek+vlbVqlJ58CuTRx8Yzr+of4EjOvcZDISRrc5gffj5HvMdt/VQb6
1KYzfUebhC4CZs0tF7YVqkdIXSdGiTf1meDKgXFs9bCH20xxQuTWU6/cDDTeToeKtjM5P3EA+n53
4iopQAubOxux3MpAN1GiWY/29j2dnavnfN00iwdsukScbacFMQPPvO0XcOdLbzyi8qoHedfmGTEO
8AzoSRoSRcQczMliWjG5qlAHMfLtaQipIw7JgFsPv12rIo6xYhUCBTZPKkqVZgh5W4IHvWwP6jPx
icZAOoT9iI3NKKCBzKnQ96NU1O29C2PgowpIjXfiDJSSrHOEXWxrazi9zQCTjTSAas6ar4vyIl+t
lhxrJrsM/X6zOdz/pee8/fI64OYW1hgonnUAVtqV0tJYn6I3Ag7NIlUQcPLB7CHWwfJslKMJVD5r
gm4XMlNh09GbtVfpsSWYRwJwYWy0aPdcJBIs1dloaFTFYP01eZFM9xRi4bmMEy31Kahl0NtR3Jxp
wCQYeKUIpGu6iW7s1rY2EP+eQfHOf/QuCAKZuPcRXuPDz3rpMokl3DCCL7SPpAIDEPcjWsjyJWh2
PPxxjHTnILdXigluwPnCcSyqF0qoCIH8aYj4WvQNM8GJZDnZ6Sfa5lyKvy1Kfzv00Wiw7F/gfPKh
Yk5BMVrBPbsrj0KLKQqQhry1N5dxG9oTTpjnUTqii6cNf4slu2ez0PNXQEdBWM8moQqCTlCbaTEf
X+g8U5Q6MG8cMqSJk3XlbhxofoJGlC7wuqns9ysFP1Z3ddQFZvV2F3k381C6u+KPFfk/djSDxWfR
5b6A+2V/ANX3ATR/RFAGTG0fG6QBwS/sWPgltVov8B6U+FgGsh9z4g4jpPgF9hqMG5z/z4M2PLvX
4+9O1fLc/YOPCowsGCIHBztVvAjwMJiG/x9CUsyqAE4FFmZR/X9rM716XW+/KpE6kd0s8qjkJN7i
FWZQSaQBhbj/CnExt0cBdLfP+Wgk7N/KMFsPqowLn2pqddkxs7T2N/djsa46vsRQXMPVH8anN9MK
xnfW+ukujoHYmWIhk6HSkJU1MdH6fTtKCHEv+ySSDPzmLAMyCY6kvS1SjWCTGmppCg73fa0bLEmU
PQzuZ931ICHtmUVQmU3wMvas+xTyQkZr9pAf0xgYvMDuSJxkRwuCn3rs12nDdNVO7gjvoyGF5CX5
N+5+Y18RIEwXyVsHr2WijenfhFm+lpIbGfa87el+hZEEcQdO+WmwFo5V2G3/8nRNx14QzDnURyPu
nKRu4EjA65OvhDEDwt4/T8ypNG8UDOW5TeQeDedd5xNChoK/uF8g2kr7ytKwGdPUWY5tzQztLoaV
yT0HI2ru6l7Xa8A6hbLSl+bONkD6a73dg3sjgaNub7MxyTSjV3r/wUNuuuu77/T9UYyEJCLlIrak
uClegVebiCsp+h400oHIy3XaJYHeAP+O4/Q6Mle9vNd420LPQapIEaLdlkOQsqEr4W+K4ws+X9+E
EKuVpvRqv9//ZKB24PAQW2K8o4gOOlHe6wtEytilyiY/iYsGxU3h4on5Sh2Q7e+O1Ln9zAzeuOyE
MX4TfxOQe3x36b121xKEOtzPzT2YU+GmtBURwk98z8Q3r5NRyXYXDqUx4qW5mOZP+z4/3rpLxFNZ
+lslKHWoOsFGOWL6kTl+8qju1467fBPp3zPVQ/3wUllwRA+HdF/LmRtateze9PBrJljyvicSWZHQ
xL/xNevVEEf6li3JPoI7zhnI0KOHBiugyWTgfkZ9VQGrMk41nVP3GOMI0idSFUAHXahydNR89/QH
ZkAVanfFT1cBSwBByr+ynU/V0dVRPNMCiHrcIXUStfn8ZzeBhaOXAJ6cPKYyNG0o0Ia8lEglqHN0
BI7MBXxf+KD1/bPhY7koSDKD5+JbdvpG6/t4QTKmitPSFg/InTjliTbbFnbnB5SwBKViBiftttGS
DPQbAWv8lHhrIoBFcKyMvf8L2aANPoQlSvPGEHMY2Hh5Lh6mRLSdXKDJ33MTJA3NtVvtibd3aB1u
NxJcc1tIox/wj+ENpmaBAZsgY3tuQdV92ozs8LAo9SHk6KlBNAeN2eCmeN2c89HftZqhVF+CdbpE
i1arCJbVuhFK4jkmVABHres1oEg4mvTAdwVGXRynEbRUZ6k2/Hzr7kO2zYyuDYZQdA1rAlRLw12t
PomgLYDnuV1w0DAjtMj3/ZzbA3Fl64/4JHdTjbP46tp1/vB/UWWrcD40u8a1Vbua2I/QStjEEplT
IBqIlp3B/FsGHibrQaJANBkSRtHf09orYMR8PFm59Jp1H+BihJ/cF7usQnL+P/DdHEWHQE4V4Sp7
Phryv8KPVZW79Lg5AsgAQrdc/Rl02QG2U1YA0Jff01Pfk75DQ5SUQvCCSGaQ0/ruCR3c+gtgFUO9
GWpauw+LocwZZdkxCJgzLiE7klPeKe9Q+Id0pWwj22agaPtSHrRtxEJl96Fr1Mycejd3ujNW3GcL
48JR6aAJ3p0bTrXU397KFw2uGwqrYkj4Xxd1i2cDx8u+UBSpi+AEbqJrLBhmzENkXmAwuhyfnfN+
SIZlMLckTpJy+ERUjjpbyJIJZ0MiMXnFGpfwWytZ/jhJB6e4q96y9xRgwqnO3yZQN44ZmgQaYQFc
tp4Dxzf0ee6k8HoIgcVn4hNxAq1vcJe16/34cv16+laSfJI7kzmp1B/AhvADJczv4HT2JJEo4iYU
FjGvReNysJgDDJaApfkFU3wjok/+/sQqp5dF8piWWh4r+n0agMermUj3C4qT23MsGOPJ/5PXrInM
UZ03eETb6adwQGlZnPmi8n+FmzWxV5ivWYJZBqid638QZurVT5BCiL47XjZcEAmbXSNrfiVKrZsg
8DDQTXqcItJeP2VqtDkgDlFeVu3VyTz/zYhhzSdnT74ofj9Bxy70ZeYdRX0O5vuTawlnKmz0gNRP
T8ulrr1+igzjknX3Z8V4824Fi1uG7530YGLOiDK8zjgTEDeO5WSlSMUMchEN34SJy5wNhyLUDm5/
P0sp/hsWJOZou+UbzCmXRTAXB76/eAjCf7qnz8EzCLNWd8KJ0X0cly60YhifVvPvcK5y3yUyaomT
RhxbOdZpJN78Z7ecCoROwsGoSWV3e3iBoIxN0RZL9ldL5npeJSxdSa0tcox3Xto0txpayr2awRZB
NzT5PdkR0YUItP0UWj23HXRryHLjBuqXjuqyFjPmgni5nGb8DEVJAUl8swxm4lj6aKjoM4T5stYf
/H4f8U88nNpWJhh8xvzVbN58XkgSIY1q9LTpHmDxyx/cAKWehoj4wDdL9+TjKLIDdt0KM/k3Bm+R
P1TvBE9w5MXJoA2l0Xlvwer82VFNKJyJZGIo7rJ59B7TVz4CX71z+ndBoF1Xf/BFprzRWHDEsHOy
W0/TN4RcmfGVFchPpM/0o6vyniYk8dAX5KjK/Xev0jADztb4BCrGiL8QJfVXXIEnfTaNX5N5xiDa
JCqrIKWVp0w+TfabxizZEtaFPDIeFmmAAbN5nT58h90YewxPTTybLJf2CfFMcMYjaFZowVhfX/3q
L5LGMNOQilYA9LZOi4b0BTvbhNgwyYV/bXHtFrO2kgRMU9Yle5gDbx3KxbgeP8H3fH4YwwIDQ5Tn
o/lGdTk7+Skj77kobcUK0M/GgO4T4Pt4B9eCr/2hxr9KLgRC8dPpphQgtxveMGFVC5npY1bNNADe
JlY9XuNHQpClzP67OoC8T9j1cnzKNAXZuXKZltkk2VjiKBiW2oZ13c2j2bk+8AIkM+laZxxUztIo
7fLCN4CjVXx9sCbXN4xGCfLRHD6+1DF4pgiRTkntw1/GgJ/O28AK/Cgv8aXwUQA5XjCZWZBTOf0C
dbyqFSTWQf2bshqyjEiLeXqb5OFfcnuCANXcDMvyZnxv6fRhDChjbLJfQ3nnek4yYW/wbTgSTAQ4
rFl6CGMf2cmLjOBH2buTwtyk5EscDpraozuvEJqOYdn9eUjmJm2Pj11/Bm3czM3+yt15DDITW4Kk
OyhgMXh1de5J1zAjRUbUHUMF1hGV7N/8i63Kni6/q3+lRV9R+pfTA33uLNY+xGW2IevxySJsbFLA
zd9LSRPuTNmwx2GNCEIaSYZi9UjDbVrUu4LCuRFJlRdMen8btmFZlXcUjs8RjRIRsILkDWHO+7KB
SsQyzYDOzejhdVT0ZbRm7xDTUfh2jm7DWxEy1Yb3BufpUbBFeyzAfu2jljpwrYZ91WAX+/sm9To7
WJTQbgzWxJl6S4Fz7tFx9IHPAAL0PgV+zPNsoMat+HeJ2PJoSeXIg9VYKZh8CvTjklk5sjyWUvq8
IAjMwHDhM8hATCv7025uU+n0pOYDQPELyn48Xj91mrYsNx0AsOMIwmbCumlg4RCua12udUEGZmrv
25G1Iktx1n/bIkllzfbpXuV9nMoCdGRI3Z+ky6dKU21A/d4bOVOfpZsok/zNyEzlvSheSSoZ3K71
6wXnnhAhbkMh0EnGQURJOKuwAE+wFXtK/b2rMv5kvytmzT8o7bnLYK5jKtJ3AwTDU2SZ0XZuGxn3
ivouPVk4x+Jpog8Xv88NQp2vAygnzzji4I1t3R5fLiQBXzdtSHD/YBJFLoCIlVYy85FjY6AB3C7M
G5z6zeiCBPFI+tVoL12CzyyhldP6g751AOLrhJe3uV/l9AZ4wnNq68Jdrc7AMVKSlUN9qzvYjK+G
okn1Ly1Cdg9jH+3bJMcBRjy6cEuqZl4PhvMdyLy2MHjULjd/duujdYHzI2KqWU07uimtNRdvAyE3
5D9s0pIf68kFKV2I8UarUfOvAlUr2ZLi8CJ8OXe29VxBczqIztmy1boHJ0ovUQYm0NEV6E7TtN6D
oC/8A3guB0Qufw2JSBM7sKizh1OF2pS78tj1Fm2xe8RY5HtX784J57qRNYutQfAGejR91mGMZ0S4
cCL/CjA4VaDtbWv9AqxUmeatoy1+n2rE90GPkNQmV7aLwldLbUNjeubLqqW1UUYKXawNvGls9Dbm
WdbS2iLMmlE7WDLI78WaNf3VKm8ld+FUexFR8+PWkOsmYEZK288QC5I5ZxXCnqUjrVLgiRpMBzBA
0umI2JiHwp+Afuos2alctcPqKx92IwKz0e+yLkssW6tfLBh0YBpwHX7Sc8PSD+8I7A7hyCIcotVU
3wetPZdZ5sNtQGB0KLi5NBgnnE+Ho2TeE5y/8qD3IzBy1JbAvtrF6yqRyjj+NzBjuivZthk4eLf1
53l5gljYxunCW4pbcBLuBS6nTh2DPSymyMx9JmN1ZdLz53axfL2uXe9jXQCcXDAaFOiqEKv23lWI
7joCz1k0IYyNjnmuoMf8Z839rk1BrMzfwTNjCFjdF3cl9wRIIR7gmAtpcsn8FBhMg+lxcLiu8X+7
ZDQOsoivxs59MXxOydabkveKiEa5LoMg7bwVoUZkexbZvtCOPYenu3ZntXDQta+deICV1pXUzwBZ
zsB2QMZ4qeVDpFaXgtjsLpIlSoFsv1sZOmLmg9RMYkzrI0xT0BD43AzZcRBE1ngtPiBSrsS3LW7/
h44ZbtnIS5BuD3breLMi3B8tP6yNPFe7+0n5joRvKrps1RtNz2Su0nCdtM0gb08AUvI/yMR0wyVN
cxY1DGit5Xaz89xDs6DUk11QHGmX7UewvKPL7vJLzhww8/nwolHheHIYJPJB6R8fMVDcDleV8I4R
a0IFbFDh31AtN50bubNAFkd5U03Md8aw3j9q2phniCDb7cT/nfuyuwP0hjMv6+z9BSs3TuFTjNEe
yBMapTQ38XopcQdJOz5o9BMVuQTOOYsBkr5PuPxYhCQtn7KjzlrYo7bcjf8ANUNe7MTkep6gxqDL
3Ab899XHcpjJrvzOzwov9nxlk/XVIUn1soU2biMZ0ykS2AM5GfzU1lZWWDVN8WnKiULd7ZpLAZtE
Vzz2XrFzGZGtyeFbI5T9KG3tfge8YJGeXlo6E2ni+VrBan+vtX3z0NsQ1X2YZgGFIt8jtbdVA+tu
jYwV7WSj22P5tKotoCBvJdFM1ImlU4VwLFjLDAWo5cq33EmhdVPEcj23QqKGWUlGJz93E68Nxr4e
esESCEHvKp/y6toA3nO1wYdPuec8x/V7GpGXM8zvA8OC0t9Vzfht/VXBhkv3cXMCiMcPVBtrqR2y
V8udjMJ5n/COfQL2b/5QR05NQgzY/+0SR0efhR7osiuvGNTZWzlA7T4p0xto1v8liru4ENQ5yVQ5
aGe/TFd2xodz1GuAB7L2uS9iV12UCJdADBKFE6YVLA0U/ls26bgNWSLhuzEtBryeKBJCETEaYTTG
Q/MPW1Q5yt/qBrAnD9YcNRUlF6o2fs6QIRoQ0tAawA18HnUvDZglmi24i5aB+6PlG0pfEKtoWS57
ZuJa+BEa0TFvesxQ3GNU+Vc/r3ufNmrST4zHPIj3QhOFc16YYtlowFLKBk34sQHFc1pumrWKg6gu
mYZe777AhbEUAzy0esURFQai5cxNipDI63hDLW40sVRBnQDKBIPoqavZ9qpHyIUf6SGyrEb9vPgG
laVTkV2BGKS6wjBcYx6jDJCpVzd8GLc+/4bMaoEf+Z4mG7VZisarLDFYdvv7jSjHq3jz1mGKMvFt
ze9atez+wrm81WxTx2n77iGNpnP0F5SMDOZloDxebF0v0gRwPR3AR/VHK9ThMWWtTvSgeTO1C+Lv
GCnVvNtXbRHTiDwUScPEJnb2FBmNEOPBngHrQW/w/xQ8BDMg309Y3/q5lb2Me62I59tB0bqy6olA
rzoYqz5vsCoCTHVnhB82Cskg+DUY9dT/kVlaIISCx76uMCjjX0499Guoes4uGZ5GQiXM4unAWw60
Pe5Sx5wdxiFcOfHEEsO1E++tjU0s2RSleJauFZ5v/cZSFFaw1kI62vmKLHIIpNYbGYBrA0ETNB+k
DElGpYsJQhBibPpiGqNWZlxYLePm3TRBQUgW3WCKJrg41BiNtgqHOJR/Wf/G1d5INKblbfeqsHbU
wlRxidB8oGS8UyzTZlujNvPu1bnFQkj3dsx3r4oYY39NrNym7AQGsu2AhXPNTwx6o3LYxhGVB1p6
VR3FSSqRVlVXXvJOVALcdFOZK2oQTHVicQ4VUGEMY/05TfIrdRK6gvsvAKF2jbs5XQsZoTpcZGe1
Gld4QSdHlz5xxMXu
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
PKBrZwK2vnS9IAX2yUsPA8owggtCeYCIijEt43eGMIs6BskFWwAF1SsmjEhW1a701odFFZ6Uiv0W
kJwPHC2wLA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
f9gYSGw9T6TKVLxVWncwHKszW7oqtbpwl/t/eA4nKw+rK2Sdc8GngR8YFKCo6J1YEOzadSBYQWyx
Kjwoz95us1DaU704NmSnpCUeRI96W9A2EZf0HPwloeywV39kV2+1o1TZ4dXle/EVUmuQnasx+ANb
bJcfukogtfIt77q8yfI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
liLfrnIHhASbF4o7WF+y/Vzafk/qkzAguBbMfF2WnCviE4Z9Ns4oxsMUjmwyQcKNcTa3O+eq0fI6
gdSpYPCtAvf9q/mD51BosWabl6O6InOyF26gDYlxMvHSbx96JpJVcZPjaE4TzqMkI9G77c1TYks9
D6AuO7f8CW466VThudIBQecvncFKRxr+BoSt8K6r8sWqz1ofGx4JKwXd0KKuq/RK9eGBTWFrlAQJ
PfaNAAnySYiWkLavjm8Fk8b1lK3fzU/wh0+97s4jbgND6+Fi8csipwr8Lq+obacf536N1L33siDR
2BZ4CsxAiT/PbmDJPphRmQsKX39ggFhD9XUFXQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
v7H/SBMc/o+5F7cg/6gT6gWqJCsq6RoAoXg2mTW6GEWviQHiQPjb0TmwYW2GE86rzMnpGGERvB51
XyifjFFv2InOmXIA/eV2K4cpAJSwZjtFeePoBC3alLnRDhj7l7C1Yl4svCYsJwZ3yEm6GCIYBgvu
NBowIvMPQbFDhAkEEac=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fuuk4sDGxKFpcFMkOSixyjaDfOJL8TgZD4y7UpgnaEjwMCX6ELTvZreKNc/pmhyg6lv5/dsR/3xm
4HXXS4XXuTi51C7nEMGywuyn1Yl4jkE3StcmlHa48kIeM02bnJY/31Esz+jiLt8mrnAQZ0hYb90f
Lbc2RXc0RZv6RC/eFp/a1miXaNWZHhWUWZu8Yg4i/cYNBL8PabUzKs4xIbR4IOg3+6yeGtI59LcE
QeeEPNK+Iq3m7fw29kcw+H5QWoxx58YFR/hQPOKKPkbLk6ysl7Ah0SDLQyufXHDyThJ7f6yB1OTk
n2Qn//5elGCD70O2c1Yr4MunleIYAXh1H8KrFQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17568)
`protect data_block
ScFtLEIvsmQ86LMNGv2UrJODc4kiEdpAvDSVjykJsjo2hMmkwnJ+DKPJbKBRsDsRx9tLJZB4jUbc
LeSfP545QLRmAKlxQOjyA0Upg4BCDLOIBruQ+rMVmP5VfyqwePcwha6qhRWoguvWEDy6R6mibR/8
+CzX7MnpXFYzAomyp64G5vOoOBODEQhqqmxZuzmqfInj/3KBvWQi0vjxPJiH9K/+B5QdIs7qt/yy
Xq5i6wBL546TbTbIanIA/ZlfTWr8/Ju+b/Dd8VOyc6ilTUC20yy9qVwyHDWDSQS2rLlKsqROzJk+
vAfNtCGWfeVsPsS5GWHo3CokgqDyz46kE859/64/VCIeq7YOsQ7A/xTAPPbV1pyx5JVUOOnmbH83
WuvBct18OKIp9Xip/4cYtGK09erUkZhc1MHYZJ50YnLlvTsfPMTI0UcyBdHubmCNj3u+A45/B95s
yRNAFMoWzSVQCTlXVZy6aAcZJ7pXdiFhxl0msJjng1wmEGFtiHAsAeqB4boQ1JqeMAFxHpihYSRz
WCtIS6xpsGDHYzjkVqELOnwOIJFPVzwy7/BisUWratukj0SoYrfvA50Pp5mitZ33hfDWUmPiSjQT
1G8MEflh3EyYSrTzkLOfRkw4n3T05e1egJdkSfzEgPu2FdtJeA4zmO13KBExVB4ezpDGrJ8cRIDd
FJ9V1/ByujLNCfEyu6pD1AqgM2cXZO96H7itDlUkgrQanAh1osDi3r16FV9iQObQs/DbIWhfztFI
YswEFhtqEHTfNtYSprGegrttpJnHWdrsP/rZi2J6JfE1dPSDF6/HUb3aGvnmocMDfoXiNTukl7jx
Z4uZNIMPrWikfQfysZRTOAR+wvCNhd6gno2IVFonsxSWUMwXFoKGuKa9/HQR2/3IQ3/44cbOAU67
uahkodLI7U2nxRXySmB2iWz/LWRKvslOlCPfxVWIRbOiTiZETtJ88DPFmwMsjA4gpRfctEmBUi1j
fzyNtQY6sBc+S9zq6mROFDpsOgIvi0xISUWqHxIdsP5JEC3/R5BkpDv6VB/e0h3WE6FS5HG+koBe
Rn6Ug55wqJg0ngY2XioUMrd4lJxtNpBRzgVqcQfClvVo975JnIu+KxaPbp3bLpUNy0mGnPYk7yX1
ipvxdlzQWolh+xgaMmDM9O+Ly6je2z6+JsVu+x0afQg3xd93wYwZBapB4UW0QP74Aop1SaNCTq8h
vQ2tTzWuLHYxmprPCngeb5lyPxXu3NGBn+1F2r7M2iAEwz1cJpohH8DkBcp0+VoqVIlKVMDj1gKM
MM6QW5SrWAj3zweS0H0JBqyW0u6JQ23R0P01zSwf+hnwXTMmdW35bo2M4QkcYm/9gwD0g25Q+R4a
9OnSq+JaVGl3eqOhFC8NtFf8Mlh4PEbfdD/QUpUBHVK9vYhcZF8gbdYI8b0Jj8rwvFM8OMwcwfNn
JVtlCrAiDWxU07gwe6reWcqm4JkncmnQ2tVdzEnfCGqitUjfpT8fuktrrnITM+kDxmQaED/kKSAx
vllUDZwxV1akKx5lHfWFbh6DJKllyEz/Jvn/3x5kNNkAs/v0muwPxO/T5emyH/jszbuIWALm+vK0
bSNPlVx8odPA9toNV+//06xdKRNq4Q3Cm0HhsY3lsOnSGBIjpgPZ5NZlag2KLO4jjKFPsI2wWcYb
MRn4HJp7JCIgiF7DDUClMPQbRxXau0s4JtzKlzqgG7nV8nAyflE0vIbX1uONkvvz6lbKxhXY0fwg
w3mAlq9TWdIM4xcHszJ5ovXlWDydhlYLCCDfTtvBffSbJuKhXxYQpvrcDkvsNer3TcpLoTi9WfvU
6DXoegd3Z9Q7PxsHOw7Mpt4GAiwxsgkn+pudc90nYW8LFD58dNkh97t6EiGIc9dwKlCjI3IvnzeL
7VuYaMMZtF0AtJHLRNOliXLdIFa1oqa328AjCCdkfk0scilZUgQmWymqRU35c1weoGnY+PEthe8H
u7fLGFMxPeQo/q5KhgLPjQZ2tMvbsBycokm5Ip6Osxum7vN8gQKg2hBVGDvNSBVtxGEedZWqVeRa
V4thaG+S5G/LtDyBwp/gPa3hgtGGekH0FVHzVCsM04uhdbNcv1n6v0HmAQj+t03Z/59+0E6N775C
rhrVErob4i+ZFoX4DI2fDcdUv8ogWF/owk0xbLMi4fRGXRdfUwidEBHvpAu3r3arDiQ8Ki8szwDS
sKXOYENN8XYO4funkr0q0w5Yob+DFRCwyWeHDTN/PEHkGZn+Jq+R8jhXIbtNvk534Gar0aVu4qJ7
A0pHSEGheQ/qGo9DKlroOAvxkSPgHtRnat0pPqHyE0MX0rIyppNM6fMwjc7sUESDqK3ICMMcgb+u
iH7e2Sozl49zZWYLA1hVY+IDMIwwHNB2rjx5+uKL/BQJ8Oi9xjLeHFe+MRP8rAVaiaBBvteY+Pj5
CXDDS4QEtGRSkuZI69xW5Q4/ld+CyjR4K3fZfFF4hZfCYahOgBgWbi7G1L/HyjK+F6NLcAnXLZFW
DcHb6SFYdWzeVqndtdtcawExmNZxlS/kiuH551vb7kKoEFmWQKWEp2bLNg9PbpF66LXLFsLZbUIt
74nfonE7+FyLrbNyrSlf7eOyFWmXwOUvFDLv9oRo8mPkgvs4qsKKd/RNPcB4XBPseJdaG8+BF+ie
T8URM3fJDsxw+AP9MMPhutOCMXXOVHFp++6h+yIpejw2CEUdF7CsL9cYcApobPYPz7gDUF1TvSQv
83wlpWiFCT1yDgqP+bxhGHOxxJ94omFIrOQfHNiJjGvvdx64vwJKq6mwHCsSbVbT5Sngy7fczQnn
ZwYVIb6ihs11vi9XjBg2JfMLDSBX+pV+aXM1l6C0NQ+l8r46qb1iNQJGm34hraEYWX0YTuBebL/y
UVQHNNS7Iqv1oqptUw9ttLq4erSAzITqHCCQCsdjKvMzAI7rrhsmIF4sB2HNHZNKp1ufHI5J8GM9
JFbHOZr7S4Y1vBjdiI6R65TZXGnLT7G/5y1oYmuFa3HxpEfU70urkfx48R+Gx19EeXu883ccu915
LNUmKyJAeGGdpZYSBq8OysPLdUgoDlY4FkBOgomcTn7A98zehkr5mNHdfDWqtYVJQXXBY+MMCG0Z
4ZGcSsWG/26s1+95tSSJJwlB+rbdTfrWBZV+Ob9ofOy+t8Zb0tzyU1gJp6GENuvmP6vfElkMa8H8
SBjSqCgC7nI4AneoHCoT4QYCLd4VnyZGNeGXr9klABjDMfjc3s6YlJ6c/itSyV4hlsz4UwCo+W1F
2l/ewSw3yP30o3Z5IOEZt9OoOJ1wquToaYHrNjBRMxUoMmrZNh2Ipa26MMhgPSTcYzFoH/cL/LTd
ghc9dOXftSGPxeXKhJcN+wMLrJrqjvdE70X5P6Lg7smUlY6zFe1KUzbpILngGQwQLZujszWPDGaZ
2wVWJbCJYNLeAqdnArLRPj0C3NPMzZxuSPE0gOrs1/YPVmhl9rtyootPkcIa6qnuWnp4cifoKqfE
Ph8EizNosr9pMLBeCX4y5lMQSJWC/ls5QQajhIppfG1EjJbadCmC2+cLzihFgx82z31mRZznrlHF
1EiF0vOT7i710WGHqKx1/u65Djq86qm33cr/chWvWMz+oqkXRQBxbuYwfhSrKzTd2kzVHOtqq7QE
VthTzvoSbHV17Tt57qGod4dPxlrCQnQyzSELeg1sSAa7YCuMzR0O2oF2vUOM9K0Rv6OgkelBojhl
UwsgLuUsTirPawtI3bBGfO4NLJgt2E2y/rgy+P8xOZixGNKZCxXo898fRrwE9vC/BCsV1F1zalXq
CLbDw01IMFJgJJjiC9ya11EpWpeRcWGm9wmkTrVnlbQHd2xu+TNqABwGw9JX6bPZNkudPpKI2+rM
Oc2JeukGUghtbIaMwGbm+LfPT9cLMX4ci4ZjxEUgGFHnWH73PWs3HvYU8e7GD0skO9NleLITpZ5j
DJf+Iiq4IXjIS4PBp1Yg/d5gaBe+QpNhbXhwBHB6vt6WizMvrTbNH+OC7RjYZp/tlx6alxDgU9W1
vRPj42S5qrFkUM+8Q6O3zchJQnNKG1hbwpcNF+A2Ntdo5AvOJRqdsmdVKg7Jh9CQOGM2WutAT+yL
kBSmT7OSgwIstmLRLciPsD6g6IgWnZG76KQA1H2IbkKVlXYjnsZKRltK69cZdWzVcCJiuKKcZuy5
+pzPsFprvgWA0MXi4HneCMcSo+j7WsgEs1MdHDyDPdu53HW0MD9XFRTICE6+hKisTDX/nY48lhJZ
QR+UEo9XQA94meI2VNotiuR5TRZCyqwWExTmWAMKWMxA43sexNdKLlQiX6G+Cn5E7KpxOx2uyPIE
haR0cy1nyM4eh8JiNMFfb5iyI6Tcd6semfs4hn5hHpicvv2esB0tMR0RnAunTsaxuhHsORdy9P9B
iM6WuX80fXImKezy3DDxpch7fGulLCES++UCG2Rdm83kHYO4hVtPmG9gvKmp/V9c4fq4U47PnLQ1
uqscN2Scch4cm5GehOgVWa4M4k64LoMDP06+DexbWGtob2mbU4NvO4bOEcNmby0sGaGlR7/jwdGD
nYmhQwYDYkCtGSEZyNXYwTfh7FxNcbOY8+uAMc8Q4Q0FGyiS2mbl8FLQYrQL3V9wawCs+SaEvUc0
EwOFD0nqQg4AcxSC/6eZJqgYmBAbLC1tN2qqCXA8wBJj4J5XfF36lIyr+t6VmnX3dV9glGlrz993
lbQ9ZoXsuTz24GNtwvV+PaDIdpkmP20lEY/JNX7KOuCNI9dfm8QS2sEGNEQhvir0oeK8OGpkTxd+
3cqxpynqV1o5OUiOx7IhDfhYCjO82Hvle2S67ErR5km/tQ8Tylx68HHb0FWaoIVPtcr2sY9J+whG
By3jmkGgoV2iV/eYhKOymMiNQe7Nf11/XnX34wGVXvvEWZlQRgAyLZ++CDwJx6oFQ5Kj+DamPmGu
YMqJyy/aR1en3vfH4Y0WcxIKnb2lPFzefQpnqUIX4UwiFhhDsCroHIGx4brY7fvEgyVHjCU7a5Xj
1b5wNRYeGkBoDRfw+GV4qlR4/GHALmtfoQ5RuEqwhudNzUxrhKB+8HDKYTeHcA97ZeCad4JfLQuU
8JDBCOMjgkDKjlsGGwP7B8SKs++XpmI5QMz6poJYYp2bnhpg3XV7rMtgptBjI/6CE1G503kvlwek
CCG4WhGqkbrmK/scHMM1zL+uzNylNhzZ3C+Rki3UpJ7L+xVrGVuVqDYMiLMcRnGf++G44MPo4QDs
LC02/a1PT80hetKQuzmjW7+PpNe65Yac9XmcmTul7T4Bxw7nfHDS3cUZ3ZLivwmE70EQGGlc9i0H
zZTv3LK1X9QOD53VgNppKULd6lexycoaXHj1zRCp0vtW6fmdH0HCGFOKpHsURlAHFjiW1ZY7oUnp
+DeutSZVBSo4aM+GYU5nb65Nm6BAG+WBFBNug6gobpa3RpQS+OCrPE3UvX0uFOjbMOV3tjcZkBA1
MNEbdfsK/FBIPdmod28uYbZFBJFn6RoS0vrEr6N20/Rq8uhvS6mY3zy6efPg8+qnPMSql8RG/Kwf
wCloRHyvS8/aWZfawTTj54T6l0NAjg9l3lS8ooZcDoe2Gjo14BT0pXVQAlq7f5iPJsSKy7raVRqC
18Q5Obc4Xt6LZg8gPhLOwoT3i4PyEeDetu9/ykuv4Y/0HxQrMVPXj4KXw0TD8S0VAXGchaSNvN4e
uRjK20XiM2zv+q/3U+V1rITTNPiFMShfr36iW3X1d3STSNjeBhiYU0Iaor+56bndJJXuAhkHtyMo
9f61QttdnL8h+aRQG1+O4fq9fXXMn/nLdZUji5RvriCs68OI8grQcAh0pFxiTYxQNtVAA/R1E+Hh
lmMjOnJiO7h7RSivrbcYUtpi5wTuIgqF47AvrOMbSTqnDiSqqDWcnObUOnkQXl6wcyFBJ95pb41p
iYyYgYQ/fs+K8POH6Jx+gVG2Lc16Ex6wqx90Wcs3NrDfyMvEuohcTrRj0ZU3rOmUzHI8tEZyLdcS
sDTjnmF0Dt87vo11BeH3Nd4Tzv/t0l+b40lPnJbSTTOWrdHwmKT4WoAzEnvxspYNodGrCYlS1p8B
HdYF9b0TKRQypAM4Hy6uDpw/eJhdXvDV7eNqyfBk80Q4774Ho838bUSzTCXbeI8E4DAK/hNItI8Z
DVxXiVdLBtRelCvLzM3fA+ckATxi4xmmg4y3rB7n3GN+X0AfcyF7swrx6eHOzCMSuUqM8NlBytU9
tVVh2DJV2+3ZZmk9RfFYsItsSiVdLIOGAPFOQpSCPC/BeiOZ6ugNLBAUNIZDNBoM9XqquIuKmrjo
9MpzJ0zEyZIglqSDcdJoU9dDxsLk1N6DYBQWHG5GH1hHBzenM7jFmp5cit1gTSLfrtcpfc7SXruX
cHDuy1m3cKfFCdyhV99HbgE2jIzu8gcWNaywdHiogJFkaaMdVP+qNqMyESGIF6yngO4DeqXHRp/n
QXvfD0Jnsc8xtlVo1ZQc0G54oIoxLTN8A9wibAwGdA20riKTtp43KgY3QbUYeKisFdsuSJDj5W7d
a5ZD23B5LQ8d0r0Ewm6v9fBovl8EVBhiQCJ6H08qcTrbFfYMAKc8IpsEeQ+dqU8An4tou55ceRW4
F8KvEZxzlbq9O/AjdiuftvJwRYOpaqyhzMzBJpZvMT+daSXbYuH/OBF7I1gqMiT+tL8YeCJ8+X8k
9XgiDsstdIIpuUJOClqkxqOxMAxlEl2iSe5cor8c6SMZQZBhfkj7KKub35odXqHdXwz0fgFcLSXi
0Juy663hWBajrSvt7Dc7qn08sGxpIoE70Aoi6sqG+y1g6OAUkIefGkOvwgXwvPS54jUhXwNnCjur
JK8boz38FxiognIjcXQh+xgJ08y7vZeo6PVQGD9tEwvOHiAM5nM/mD0HwRfqUTz1M6BEZj7JOKzG
SuICXTIjLuyvBhVE+Aghbwy1cxl1f9N2oSJrEhA4gwceBr0hvsKmLYk/O4t7xGabX0hagIiYaDJW
ZOa9gR3mIYYN1Cadole34ioHLLYCj4mSDPOh30PrGRLQRiuIyg0PPIDLp1zNQqtsoo1ag3cciDkU
jI71hKNvneC9lCtfsVTbDWHbzXsBt4QbDsPzEI4J61Rwjba2884DRiv1o2yJnbyh6NIZwiwzfgZo
bPGTka8pg6+mhybbOI1vrGW49Ob0CrKtSo9WhtBKB3irOydksAHqoV2MjTshw1G4YUfQkAv5BHMp
AFpL/QA/uvKfsLoX3AOsJDBfYlXyv46BtIaBqNTOsMrmmi+jhHO2blhEV2psrB+xyg8gCp98diye
fBoLf3804GOacvjWTLf31RK9ADhkctJ658zpWnFL8aqvMlK2f3qhthc1BZoJP9j5f2Wc4ExRxx+Z
OkhqJCTcb2Xzkd08U8bHg3FHoUrdaD93GTRhocg+jFxelPRO9SsV/ABLFU4Ledeb6/h4b56VXzCq
QKlTIyUhrSFogsnb6eJqgams4287rUnYcpfFPK0bY9lKtdrraOwt46CmncqjyAw7IHixllKpb2Gu
JRVjA2xKONfaNC/6hjyxN71vD+Q4Tcrw1efa5NgvfxlHdL3F8mE9cDNAwHbn6o/wGSXn61O0UJXN
9YzoOnCTUMXkc12DJmyrruL+X7THAnpct8l7W+b6jAF3xWvW8uQ7Ycim/aPJYLpbCweAhXvifaWa
+HEZyZMbClu6jNMjvjZOLspp9lwdSykG9Tye9Jgo/kfY1DxDTTdOet2+OWtsCZEj7jPq3VEggxJ2
CWQjTj34bwisj2Mcvaaz6q1BtaYH8wxFvfwIo0XY8V3fLxOZXveJN4qmi2OsB2CCIPSTnxHxAhon
XrTI3Mkl7g20L6EvdWYE65iNMINFrYJio89k0U6cMdfJdquEwT7VnsF4Ew9LAC3qv1tB9rXG4GSm
B6Ga+057FVi/Xhdw46YHlIrYQmfP6Qw944s/ekkFIw2DhJvxfreHj8SSQXxmmucXTyEAYSJMeZEl
sOpWR2+FYXAbjWOJwhl9cBqdb3qjYcBtvtXnAvo9rnjw8JmER1Gr4qqu/b/qICmTdB0SkmKPWgt9
JlYJgiwwdURQ894PjEnGYrUMyS6IDs+mAnwMqrtbxc/ZMfZgYSV1/O2xUWd06AIXxj9rS8l6m3SZ
v+v68FD0bd+WNQ2EU0C8ZwHNdZrFL94aS5VmjcWVPoZQIzgJMay1nPjdhrK+8A30QzSKfajejwaP
gf+x5e8TVNPQHE0ME8G9zAqKpjC3a5bp0B8zf77IqC/yHqo1PF0Kji7pfrympncdPmtCsPWg7Euh
kTGusxFzX6w8eLSmgVH2KBTjZ7FSsxsWZKzUF7a8W+UmGtibbfZn5JqrbSrU4pdFhkPcjbv6rJgE
75FdDYPaWuaL2h86Z4jvHsWrcho9eyYJDRi32XH9rn0XtW6eKVi2AJT3ZnYljyreSn6y2Gd3sbrT
BHGcTtm0jc3aQmlsH7wmToFg1rw4Y/yp3c+MZ40yfWuIicLdxarPubADMQuzN6IMrmYeblU1utuL
HB6X9mmzDAlxlOb+LKHfiyxio1daMfU1+zpN0v0+27Q+dUZgm8RUfbQiD/o6/QCllUXmDvSoUAKz
g0562eJAdQmpDTCtlb90eFEHdLn6gb9Jnap3mhw6xNTrLAcQZyag0eNL7TMruDKbWryYTHaJv/1L
kGGrs+hTk5YW65z+1RjomwANRcM7N3D9OqbnXURekbEWkYd6gO8FG+DctlYX0zQyGeTj2MqVndn8
GRVjuAwNSI2LEoQ3J8ANdpZgbSOj6jeAkrR4NqK3d+wOI46qC5h4LoKYTgj0hnJni/XgNpRHOgO5
jX1JDZeOig76ajFVypEtkRQCgm/2dFrESKqmQV/UGMZ0uRXc6aEKqiHGZYgoTxpKDLy3pB0fe9Ax
Cg0zhzCZkju8c5JsCqo+HzrQRIFKrO2nQlR43CtxlvzC/8GGdDTiCvr9YpQc60hz7flKUcHOj9qs
sDNnpG6UErhLy/IakDOwFouOAZRun7GHk0pYlxNh41rkxX3BUDX2LRh1cGlkD4LUhr7GZnJkzRJc
Iyd1Wtyg54mPhOtleAb6NpOOq+VwAZb7CA0poFuDmGImFuN8O4Mee7GdKCTGNvVYpkh5iBAvEuzj
u3sJ8iqVPHltc/aeCHB0tvVMkoPmzQIs0LASUTpQrPl3hK6D/OUUMXNHWdNwifylxWfXLWAn4Qp5
a2AialGXYATqcNU3aqvB5jlAYvoWo0fpOGwkBYDe875p5n7Agvu6SfmcXto0Hci6vysQJ/a89/vc
lFK5n2DP2M6frzQW1LHA+nljQK3FfmuYIItontK+yJQRuiyqvukOi9Unvxg6di0lNuRgPlSC3GbE
iQEbG5FlTwkS99lwBhovcinVbfLOa0q8aS3XX2aMLpVDacoZhEHXhskOY4j0G3Ybuzo+Pdxi9cK9
Z6vCxTqTgaqfAvcbjYMN0KQja44q7dcNVZwO7fXBau4zw4GGNOkALFQEnGl7tgf/566XEQ3xw8tz
QIIvfQZOHATBMbdbHqP9BHJkq/nKhQzHV3N1p+DpxlUgRwE9+EsfObkyuyPJr6KlZJNAAx8mwelP
prFHgqz74g21zKuhXibI6Y//GAqH2V+4YU/3JNgl/RqZJkZoZN5k+0CqOCgFBYx5vhnKo8elYhjm
R4KbG9R16cL5U4YQUKocynga+BONcUzRetePInX3qUjm2NxIYllW7UVBYZebzz+2tLObaf3YYE+j
gxrOaWgAQ867Y0hiJmOUF62xj4G2Z2/pIm8WX54DbwvJYpZU9Q68U0Ch9cSjOhj3Ngyq2Ef59itB
/3f59uu7TQvYx+IGJx9vcZPhGbM5wz1oa/9CCUffRa85DJYVVP7LnsfdQTYfTpGfNznc+1MxIjaW
J3GMs1fgHC5aKjY7JhTsgoLwoTL5bJ9ZtRlrsToDNohUCTO1gh70/2T6eJNENf+azfjPGMAtdbGS
5WvrUzzVnQWD16cGJJOQdhJXgJ4eKSwN2wLhIrTF0dVBKr7r79FN/m3c4YNyG+vJHUz+eAF50Fnz
zIyuu0ZXc8fgE+QlwgEQjE/AUsFWZC2BRC6SsuVTFZhCLLd7hlCaZmUs6LKK+dqDYUMpgHRpTcYY
qkEhlFprPXsF5LywmiOJYHqgtBDeSc7463uvPE0tj8mrF3Toy40Eq0grwBX0QJAFT2rwfyBVZWc5
rHB8NWzTLQwSTAkxOrtmN0wfiC8tmtlHO+frvtd8X4Fw4EOdoMUL1AFYNB5bLpDGq8UNSJnZ1vn/
/uCeiociMt0D1M7CPelwrPnHl/A08ZH5UzKR4T3sbFOM9RvFjlm8pxDOrp+3R9Iu18OHxNjxrZ3o
U7rtLgi2dvw4dGX/t010W1uCcp1UgBLj6rnbRxpL9iBYZrH420udejx23uuRbiC5aTR0dWR9Id16
2DLsiguB9rtBGzmh5bm77NMqRnKIBd/5IOHTz+gUcz9ssBaXGtk7yw9ytBESpf/iUwBNAZ/HiBEA
Xgi3DrvUm/T7HbmetfXBWkSJ3wrokXbcadZk4zcUHCBNFKYp3nbj+HzV5X/EyVsLQGMrYZkYvXlp
zv3gYvpWDZ7mFM3wyxjEdeYhySDN2mmPHL7hf4ekGOMG9YQ1e4QIMQ6gHGWB+L6QydMrGRsT0zSD
f6Ro6L+NAkfpo/yZGbWAM8y4Mnjr09P2cHfVb10AVRCf2E3t6+7zSVJwPyHGGGyklPg1lUOWY/2O
Y2CBGm1I6TRTCr/f7b7fN+uq3mGjMXRwOpx4grHaj5I5+qVlIiXEE/3wAA5S+iU6Lfl9ablcxc9b
6wMqvt/8g8ORdVNkE4S57ZINv9CTdA0dUrj8W8Aj4x/8BLh6jajeNG8lGhz2VSQgqKeJO/6PnKCh
91SUP8aJzFF38cJWFeucJmoimAnjZ6Odvty03SrO+aaHuy461eBTd6mlbKZhP2fcb6i0hqgQo3+D
Q+Ux+WUmyy3LqzvOxsmqXPAu0SJdRAiLKxX5SoH6DM7QlsfP59XDVciIl+adP8CHr/iazd45CU3f
SK08H9CVf4qXRlksYxftcDS0T4ggth2STUXsQ//55tO92rWMzsVNQ17Ef5IGNnIQLXLRsoeqmp9J
jtRXUHFlUQq8FeynOVnmbQEFIFOLkcLq1M0iDxwuYbMHO1zBeaE6Ywr9XUoYtr8j42amEa6FUxKU
girKjW7xMCsiAfBVrYglpv6kO6DKfc5IBDy1IAPJ75hKi4dgKokRn/MCKAkVIPHfXYv7c6AO4OS/
zKUKALtGbzdIdD1/Y9WVJ7Yt55OT0t+/OyuOOxGHS0p4UpjjLD7jD1CXjd6QBYGLb2R1FYUefMMA
7UBWQtHD8UdZa/odbhMMdvW4CtXh5eySPh1tgJYscejZ5u6QVKgRlLXuyI2MZmkq9rNf0L9/aco8
f+zSTD6dKlE6MVFYjh7vTYqSawERnu3RCHxMTyw/6KrhOwMEVLYnkpi2NvcT+DPot+UA3VGx9qTG
w7fvUJJngzEyAXPMxRZzCYN/8+007R/i9Z+/g2Z2p8sFEA9jXBLuqfxR2IJIZAW/DWNtO0nnsPf1
tCSDnya+P4QjDfVQM4Le72YV68mUqh4G/bh347S7/6vwuSnBXJepzPa9sCJAYtxqaB+FBp9w/1jH
VcfAOcYWl7c2DYIti9X3e8uatC76Nql1aP2+2vqZWaLZpDng4KnMEEgWSpyDLmA0sfhJEQ15f7+g
VLN4fHE0vYWunVlwig0L9M46HZIkKFefjk4KEIR+e6XYs/x6ZeVBierj5BBfqVE9L4r0GXsqnZFd
7JI8Gm2aqGhxA6y/JVrLqPDE/inpMKn/u8XF6rdJpDNUPdupjCTGw3JPmn+Ox4FRT2vprA9yT+jf
MaA/L3+dV5+W2+TDStrFOouvZQAYZgI0D2LQh5A1O3r5o7mTLxcvyCR0Ab8xYguhe3Pb75/LXv3K
fR6m4wQlul+D2eO2raenBnfl334iZHo/Os12yoZTDSRVuMtgo/pmWFEkGEvtNGZiL+L+PYu9fxfW
kbfY+6K4AQLh2tVJ/QLSDG2LuuPKvkfgAsvfKWuS/Sdsp8JzkoQgiFnWcNYyc3QvouwJC3rhFdSj
50cUiqsvozBBDyVeEwTqYBCUStEcmS7qtM+JfWvCSBuDMOj+e2rcEJ+JW9i7Fj6jSQ8o7Jtqxr1d
qRGfL9cp24Xk9GWsaHBA6lV4TQcaVcx79VtUwBMhw7rgxMkVrIvxyDIhxX8B01ICN8yyNfuSfbzU
MkTwLJsKPadPWe1S2W+sPRkT/iYjdxZ2rzv+Kq5n4p11qqsTIarWbu6tuf4brtjgmgF5orV8rkoG
7PKYnD0bsIIm7wKr1Fz2KC+nIY3HFac7NDMse3E47qd1J7SAUZXWafmHfxpBleUjMqLcLbPQ483Q
4g10FncfswoefV/4KyC5OOfGXxIhD5EcT7sMG68TRPCGpueOLjvRFRhM8/4ApFLbSNJOUbObqCIo
F7rLUJxIdzBNVtCNFlISMlZEAtaokLJYPNNjdyptq5aqKcvsvyn4Td85cbjVnGl8DhxG6F3d4BEo
K/VoIY1JBoEHqlRLZ8BB+6ZUjpH7C9OAK5NudZaFLGEcxyVDaMlSbhHwCrXz7pNTuBhE0NTikRZX
RPtbmtS28EDLttTEwNYHqsstJW3TIeqwNO1LIjUuzy0ya8/5RQQJaF+iemC0ceEYMQt9iVNSnMYN
olCE3ctAr0Uy5QAHfZ/uMZOTx6/qT4NRWUreytOwQO9EOCJPCm9jdqbZ8MW+4qKdIG/tFEir1TXp
XQ3grCJwtPf+RXFc0Hy2pfQnDDS2kimR+y9U48DaRIM2nY5MahGJWoyXxeClHnlVZcvo4vb3PRAS
KGFg/pGsKvv6agbz02rhWQE8koqAlWlGhiZZMVX2TE9Lz5NiQL7d0WKyOQsKEGc2koCoVMqiCZuS
pocJf9MtR0T+W3rRSyJJ9bvO8RoC0GjeHeRm3V4W4RdqoOj/7ZzRbk989OhIX+0mvkzYfKZ5VuCf
i5TZv3hl2ssTmqx6quS9z17RkOOiqmCKSa98SFnhidWcaTZtoeOzkbS3mYZ0agGF+lyExE8YVYqG
eiTwGJfc9Utlc4/V3M8cEon1AS66bfbNuDbJ0YHaZifBKt1TiRdpWF5pG3+kvFzbHdIxdqHGdcAa
+L0xNPfdw/6n2Keu5mPRjNzpPqYDAJGBzdmatf1kZg8o1XFnN1fdwtnIKU+YQ58IqSkfhxeu7dxS
4AFwJHgBczZx1Lhw3Q9RapP69K6XUU1+pMigTChiaS6koh8xlksI1oVnEXIt/toHjQrE0HKnjPV1
YBElIuBFPwKyQTkBpLaE+3lI/WtMZEH1dEL3CdRqOViu8q2i8DL9cV6JkEQgFNc2tEtl5WDOYfpL
HXCMe24cWZn838680uiQy4NmvyhEGHSmJKwhbIkZCxgXdo4ZhxrmUkTWcNJDFjcc24hfuBCXzETy
GXHEsmxN9DxV4iubE3GyxT+nCjWEcxXYSb069/QDllOjQFLgKOib4/TV7iVnG4I30AKyNU7pQJ2r
DjnTGL0XKNdsElE4FZ5Kjke91Ym2n/mafTcUdZUtr48tUMNFZy5e5fVGaQZYwyqhQYQEpcRIInTk
+ZuZg3avBf/P5q7IKxLlbuxzCMd2r+ehYTsyt+31c2uX0VICyuxW/9NWYFpbk+b98wGqN1P30C+F
vsmtf0wlPA0yfyf7Oq0vcf9I9FFl9hXIQMDoFWWBTw1y3df/cRTEg4H5jaj0zzinheGY4DAz2Io1
KNjNLALOr29xfn8JJEmM+YOzLr4JB/l/mUysqc3BP3gm4kkXTHY2v0AQS6dzEV3dQhUQJX2nVHvt
jEQCJ2+WKmooW7L3ZH39nmKZYYxa3BcIujwcMlhXQHG+xE0t6YwCrOtflY2hWa1MKczMhDSJ45XQ
O1B8VHubc1nbnCtKvMZFADAbnhDq29oT50XQnv0tGCdKY4oumLp4FiJ/jc0Cl/8kV6dHOfgy7ay5
vH3OaL3abi6aiQzIISqqjCx9N4I8J6dxH5aAAOThjTJuAMal0ncHqU3vsEGR5JIBThn/zxgglSTC
p9rITu4iLa2HX0o/ClMOGT14wuVXfzoIXUFTob2ZiXWsV+EDLFbd481VuP7MTXU9zjKlS582ueRd
dGxtqyj560giM+0oZmM1bzIHF0cg/JTsHxkxxdRtgWSmaP6omLzjtTgOwQuyYkv5fQDAaVvJH8sj
lkfba5US28p9bqHgFm41QUY85pSR6LgaYXvgFNdhr5yUN1P2i4ZQtk5jARa6JCgf5HKnvZdp+mSl
kUzvsGs3px0bM/9M9t+TBhvA8uJu6S4XXSmEIbVs6M7Pu93FPEmqWAzIQZzEAnyRVXz7bD2nabBq
f3vMUliXp8KEoa507FRI7+UdpltHbJASrsjOEdutXwdOejs9Wk2RmX+yLHCaN/F/EM9ckiMUwvM8
9REmbc2EZn829M/yG1DiwF60PaWPLNauzwQ4THp8GVZv3ldgPYGwyh3LfKjC+dFzRLVmUM1Y1T+J
I3xMGy8MWYI4XdIGzETbfwrwTvht0eSqfeomfCvTjsCWkc2PRrxNx8OWprQFusF2/1LnRp3LU9aE
pc5SJlT4BXG//AX7B5ER8Sb1ikN3AVhK/AfV2bLfC65qm3LotjA72Fb82eQITe0PbrthdTcQKL4i
VlCeqNlceHd1kgv4BhNVIfcV7dklHF9DJn6YyO4HLbZyvNwdWidnZyQN+FvMAmmLh8lDmdOJq5dr
XC3Z051lwO8yG9wdbpjaBqYDjJ+CXDe9FtwRJn+om5lYhaGUr41R4WkUeP3yWOcHSa3iVOyvAwcS
scJK29kPhWCh+0YweXzXfXazfVPmt6LIgvjYqqlyUfDOPqQA7S3fUoNHBhcjpVmGem2hFQRqtf7x
QcDudN6RX80pueLLdCGPByihuVKpsGMseUPgopsOQhsyFElIe/INC6VGsf2pr88l+Fy7nd4CRtl8
//b9vdRYAqVhzb1Ms8P8ldypi5x95kESb+sMHqE4GtK7WS9X6dN90Mx8dUeL+hBsjj/tVgmzouk7
zIyZcWEI96T2ZFxAVXUKiBC2tLaF+aE7Xgrb40nsHXjswfpKavK20mwaMVMmSfz/ZYP5rGkoDZsu
L/KtUKYEk6Zk56qo5S/exwoUVX8sFpYBxc7zPc+ntYO7jjnYl5LmO1aYkelQ0Umr37MxANFLdsBn
buXrDrnz9oDY6KUJoXfp66xwegjaNuBrN7lkw3FR3FOR12THUjF8BgvYqN8SOlww6GjpEyYNBuH/
scslij2Oa4VRQ9UITnVOOyhEpvAvyX91jrUd8FUT7W3JJeYgTkKa2JCw8myiFVbbQapRGMN/7nkS
AZAJKLtQP3nEBUSiwwUlDxTCyptel+p7Y2/T+sEPsmr36TKL9MiPND+DhbLpHpCb5AtCXSXxFwuH
IW0daTM2kyYaMpbFRgBYeqjwbXCKb4ibQw9QMI33uhW0IFFW3HKZCd07niDC3HMW3gJty5NXSj/o
CKjNI888bD/7uRU6SRNZkeOXkPROwZH5yGgI6p/2THIgVD/KXw83IxCM3B7oAMV4Jn2H+oEqQHKO
kVhESIr15XsAY+2bZhUvmcnav78p01KJTFlD7qMlzgJdiH2GlB843yjhq0pjCs2c/ECnFXdsomfP
vp0E5xgUPZmXU+gvLoVGR1yQEVc+PmeSisY1dSPEEVsJjuFNsGEPtvF7C0jM28Hri03VzJtKKn3b
O2ceiKhSgSElzliiMwuZZOyfcOLgu6cmM2/mZm0/Eo6ePwW8jgjSc8/GuwRls7cZcAbWxlQbd1Eq
9XqnatM3EQ1YnYq6eZbQn9NQmxL1ltX7kMTZ9SDJUjI1Y+855qh3VISOKN4qMwEeKDdbOZ0rVprb
JmZPxhN8E5afmlLpDuexpOTZB/0K9eLyo39dT6f0zMa6velcmmUxeHXoBEuOoU+cb7kDtc+JQ27f
akLY/UyX7g7WD11mJO7QpUqru67c9Vbw2qM4cWzMUraO4AQZlRKoJLiRFVqwcfZQ/hiUzqszeGGK
c3UpGqlVdimoipWq5PY6ALF6KMmP1ZzqxjV58Rh71R17kTPyVmWo1NKakinM0mtGbzmQqfwi3y0o
Py0Jini8h0jbpol9HUB43FUJFPhQABxj5kBk1E9hltIJWXePeo8j8tU4hfImAXMBx2rjKEbER1Bi
MJ1jTuvPbePDjBpSMG4/kUQTbtR1meIC3C35tf3cQE4j17IJkZHo9HrqeyzQEjzqLW/xMEPIxPsX
2SHBikNoNxmyDIlwH9IwkQ9ek+vlbVqlJ58CuTRx8Yzr+of4EjOvcZDISRrc5gffj5HvMdt/VQb6
1KYzfUebhC4CZs0tF7YVqkdIXSdGiTf1meDKgXFs9bCH20xxQuTWU6/cDDTeToeKtjM5P3EA+n53
4iopQAubOxux3MpAN1GiWY/29j2dnavnfN00iwdsukScbacFMQPPvO0XcOdLbzyi8qoHedfmGTEO
8AzoSRoSRcQczMliWjG5qlAHMfLtaQipIw7JgFsPv12rIo6xYhUCBTZPKkqVZgh5W4IHvWwP6jPx
icZAOoT9iI3NKKCBzKnQ96NU1O29C2PgowpIjXfiDJSSrHOEXWxrazi9zQCTjTSAas6ar4vyIl+t
lhxrJrsM/X6zOdz/pee8/fI64OYW1hgonnUAVtqV0tJYn6I3Ag7NIlUQcPLB7CHWwfJslKMJVD5r
gm4XMlNh09GbtVfpsSWYRwJwYWy0aPdcJBIs1dloaFTFYP01eZFM9xRi4bmMEy31Kahl0NtR3Jxp
wCQYeKUIpGu6iW7s1rY2EP+eQfHOf/QuCAKZuPcRXuPDz3rpMokl3DCCL7SPpAIDEPcjWsjyJWh2
PPxxjHTnILdXigluwPnCcSyqF0qoCIH8aYj4WvQNM8GJZDnZ6Sfa5lyKvy1Kfzv00Wiw7F/gfPKh
Yk5BMVrBPbsrj0KLKQqQhry1N5dxG9oTTpjnUTqii6cNf4slu2ez0PNXQEdBWM8moQqCTlCbaTEf
X+g8U5Q6MG8cMqSJk3XlbhxofoJGlC7wuqns9ysFP1Z3ddQFZvV2F3k381C6u+KPFfk/djSDxWfR
5b6A+2V/ANX3ATR/RFAGTG0fG6QBwS/sWPgltVov8B6U+FgGsh9z4g4jpPgF9hqMG5z/z4M2PLvX
4+9O1fLc/YOPCowsGCIHBztVvAjwMJiG/x9CUsyqAE4FFmZR/X9rM716XW+/KpE6kd0s8qjkJN7i
FWZQSaQBhbj/CnExt0cBdLfP+Wgk7N/KMFsPqowLn2pqddkxs7T2N/djsa46vsRQXMPVH8anN9MK
xnfW+ukujoHYmWIhk6HSkJU1MdH6fTtKCHEv+ySSDPzmLAMyCY6kvS1SjWCTGmppCg73fa0bLEmU
PQzuZ931ICHtmUVQmU3wMvas+xTyQkZr9pAf0xgYvMDuSJxkRwuCn3rs12nDdNVO7gjvoyGF5CX5
N+5+Y18RIEwXyVsHr2WijenfhFm+lpIbGfa87el+hZEEcQdO+WmwFo5V2G3/8nRNx14QzDnURyPu
nKRu4EjA65OvhDEDwt4/T8ypNG8UDOW5TeQeDedd5xNChoK/uF8g2kr7ytKwGdPUWY5tzQztLoaV
yT0HI2ru6l7Xa8A6hbLSl+bONkD6a73dg3sjgaNub7MxyTSjV3r/wUNuuuu77/T9UYyEJCLlIrak
uClegVebiCsp+h400oHIy3XaJYHeAP+O4/Q6Mle9vNd420LPQapIEaLdlkOQsqEr4W+K4ws+X9+E
EKuVpvRqv9//ZKB24PAQW2K8o4gOOlHe6wtEytilyiY/iYsGxU3h4on5Sh2Q7e+O1Ln9zAzeuOyE
MX4TfxOQe3x36b121xKEOtzPzT2YU+GmtBURwk98z8Q3r5NRyXYXDqUx4qW5mOZP+z4/3rpLxFNZ
+lslKHWoOsFGOWL6kTl+8qju1467fBPp3zPVQ/3wUllwRA+HdF/LmRtateze9PBrJljyvicSWZHQ
xL/xNevVEEf6li3JPoI7zhnI0KOHBiugyWTgfkZ9VQGrMk41nVP3GOMI0idSFUAHXahydNR89/QH
ZkAVanfFT1cBSwBByr+ynU/V0dVRPNMCiHrcIXUStfn8ZzeBhaOXAJ6cPKYyNG0o0Ia8lEglqHN0
BI7MBXxf+KD1/bPhY7koSDKD5+JbdvpG6/t4QTKmitPSFg/InTjliTbbFnbnB5SwBKViBiftttGS
DPQbAWv8lHhrIoBFcKyMvf8L2aANPoQlSvPGEHMY2Hh5Lh6mRLSdXKDJ33MTJA3NtVvtibd3aB1u
NxJcc1tIox/wj+ENpmaBAZsgY3tuQdV92ozs8LAo9SHk6KlBNAeN2eCmeN2c89HftZqhVF+CdbpE
i1arCJbVuhFK4jkmVABHres1oEg4mvTAdwVGXRynEbRUZ6k2/Hzr7kO2zYyuDYZQdA1rAlRLw12t
PomgLYDnuV1w0DAjtMj3/ZzbA3Fl64/4JHdTjbP46tp1/vB/UWWrcD40u8a1Vbua2I/QStjEEplT
IBqIlp3B/FsGHibrQaJANBkSRtHf09orYMR8PFm59Jp1H+BihJ/cF7usQnL+P/DdHEWHQE4V4Sp7
Phryv8KPVZW79Lg5AsgAQrdc/Rl02QG2U1YA0Jff01Pfk75DQ5SUQvCCSGaQ0/ruCR3c+gtgFUO9
GWpauw+LocwZZdkxCJgzLiE7klPeKe9Q+Id0pWwj22agaPtSHrRtxEJl96Fr1Mycejd3ujNW3GcL
48JR6aAJ3p0bTrXU397KFw2uGwqrYkj4Xxd1i2cDx8u+UBSpi+AEbqJrLBhmzENkXmAwuhyfnfN+
SIZlMLckTpJy+ERUjjpbyJIJZ0MiMXnFGpfwWytZ/jhJB6e4q96y9xRgwqnO3yZQN44ZmgQaYQFc
tp4Dxzf0ee6k8HoIgcVn4hNxAq1vcJe16/34cv16+laSfJI7kzmp1B/AhvADJczv4HT2JJEo4iYU
FjGvReNysJgDDJaApfkFU3wjok/+/sQqp5dF8piWWh4r+n0agMermUj3C4qT23MsGOPJ/5PXrInM
UZ03eETb6adwQGlZnPmi8n+FmzWxV5ivWYJZBqid638QZurVT5BCiL47XjZcEAmbXSNrfiVKrZsg
8DDQTXqcItJeP2VqtDkgDlFeVu3VyTz/zYhhzSdnT74ofj9Bxy70ZeYdRX0O5vuTawlnKmz0gNRP
T8ulrr1+igzjknX3Z8V4824Fi1uG7530YGLOiDK8zjgTEDeO5WSlSMUMchEN34SJy5wNhyLUDm5/
P0sp/hsWJOZou+UbzCmXRTAXB76/eAjCf7qnz8EzCLNWd8KJ0X0cly60YhifVvPvcK5y3yUyaomT
RhxbOdZpJN78Z7ecCoROwsGoSWV3e3iBoIxN0RZL9ldL5npeJSxdSa0tcox3Xto0txpayr2awRZB
NzT5PdkR0YUItP0UWj23HXRryHLjBuqXjuqyFjPmgni5nGb8DEVJAUl8swxm4lj6aKjoM4T5stYf
/H4f8U88nNpWJhh8xvzVbN58XkgSIY1q9LTpHmDxyx/cAKWehoj4wDdL9+TjKLIDdt0KM/k3Bm+R
P1TvBE9w5MXJoA2l0Xlvwer82VFNKJyJZGIo7rJ59B7TVz4CX71z+ndBoF1Xf/BFprzRWHDEsHOy
W0/TN4RcmfGVFchPpM/0o6vyniYk8dAX5KjK/Xev0jADztb4BCrGiL8QJfVXXIEnfTaNX5N5xiDa
JCqrIKWVp0w+TfabxizZEtaFPDIeFmmAAbN5nT58h90YewxPTTybLJf2CfFMcMYjaFZowVhfX/3q
L5LGMNOQilYA9LZOi4b0BTvbhNgwyYV/bXHtFrO2kgRMU9Yle5gDbx3KxbgeP8H3fH4YwwIDQ5Tn
o/lGdTk7+Skj77kobcUK0M/GgO4T4Pt4B9eCr/2hxr9KLgRC8dPpphQgtxveMGFVC5npY1bNNADe
JlY9XuNHQpClzP67OoC8T9j1cnzKNAXZuXKZltkk2VjiKBiW2oZ13c2j2bk+8AIkM+laZxxUztIo
7fLCN4CjVXx9sCbXN4xGCfLRHD6+1DF4pgiRTkntw1/GgJ/O28AK/Cgv8aXwUQA5XjCZWZBTOf0C
dbyqFSTWQf2bshqyjEiLeXqb5OFfcnuCANXcDMvyZnxv6fRhDChjbLJfQ3nnek4yYW/wbTgSTAQ4
rFl6CGMf2cmLjOBH2buTwtyk5EscDpraozuvEJqOYdn9eUjmJm2Pj11/Bm3czM3+yt15DDITW4Kk
OyhgMXh1de5J1zAjRUbUHUMF1hGV7N/8i63Kni6/q3+lRV9R+pfTA33uLNY+xGW2IevxySJsbFLA
zd9LSRPuTNmwx2GNCEIaSYZi9UjDbVrUu4LCuRFJlRdMen8btmFZlXcUjs8RjRIRsILkDWHO+7KB
SsQyzYDOzejhdVT0ZbRm7xDTUfh2jm7DWxEy1Yb3BufpUbBFeyzAfu2jljpwrYZ91WAX+/sm9To7
WJTQbgzWxJl6S4Fz7tFx9IHPAAL0PgV+zPNsoMat+HeJ2PJoSeXIg9VYKZh8CvTjklk5sjyWUvq8
IAjMwHDhM8hATCv7025uU+n0pOYDQPELyn48Xj91mrYsNx0AsOMIwmbCumlg4RCua12udUEGZmrv
25G1Iktx1n/bIkllzfbpXuV9nMoCdGRI3Z+ky6dKU21A/d4bOVOfpZsok/zNyEzlvSheSSoZ3K71
6wXnnhAhbkMh0EnGQURJOKuwAE+wFXtK/b2rMv5kvytmzT8o7bnLYK5jKtJ3AwTDU2SZ0XZuGxn3
ivouPVk4x+Jpog8Xv88NQp2vAygnzzji4I1t3R5fLiQBXzdtSHD/YBJFLoCIlVYy85FjY6AB3C7M
G5z6zeiCBPFI+tVoL12CzyyhldP6g751AOLrhJe3uV/l9AZ4wnNq68Jdrc7AMVKSlUN9qzvYjK+G
okn1Ly1Cdg9jH+3bJMcBRjy6cEuqZl4PhvMdyLy2MHjULjd/duujdYHzI2KqWU07uimtNRdvAyE3
5D9s0pIf68kFKV2I8UarUfOvAlUr2ZLi8CJ8OXe29VxBczqIztmy1boHJ0ovUQYm0NEV6E7TtN6D
oC/8A3guB0Qufw2JSBM7sKizh1OF2pS78tj1Fm2xe8RY5HtX784J57qRNYutQfAGejR91mGMZ0S4
cCL/CjA4VaDtbWv9AqxUmeatoy1+n2rE90GPkNQmV7aLwldLbUNjeubLqqW1UUYKXawNvGls9Dbm
WdbS2iLMmlE7WDLI78WaNf3VKm8ld+FUexFR8+PWkOsmYEZK288QC5I5ZxXCnqUjrVLgiRpMBzBA
0umI2JiHwp+Afuos2alctcPqKx92IwKz0e+yLkssW6tfLBh0YBpwHX7Sc8PSD+8I7A7hyCIcotVU
3wetPZdZ5sNtQGB0KLi5NBgnnE+Ho2TeE5y/8qD3IzBy1JbAvtrF6yqRyjj+NzBjuivZthk4eLf1
53l5gljYxunCW4pbcBLuBS6nTh2DPSymyMx9JmN1ZdLz53axfL2uXe9jXQCcXDAaFOiqEKv23lWI
7joCz1k0IYyNjnmuoMf8Z839rk1BrMzfwTNjCFjdF3cl9wRIIR7gmAtpcsn8FBhMg+lxcLiu8X+7
ZDQOsoivxs59MXxOydabkveKiEa5LoMg7bwVoUZkexbZvtCOPYenu3ZntXDQta+deICV1pXUzwBZ
zsB2QMZ4qeVDpFaXgtjsLpIlSoFsv1sZOmLmg9RMYkzrI0xT0BD43AzZcRBE1ngtPiBSrsS3LW7/
h44ZbtnIS5BuD3breLMi3B8tP6yNPFe7+0n5joRvKrps1RtNz2Su0nCdtM0gb08AUvI/yMR0wyVN
cxY1DGit5Xaz89xDs6DUk11QHGmX7UewvKPL7vJLzhww8/nwolHheHIYJPJB6R8fMVDcDleV8I4R
a0IFbFDh31AtN50bubNAFkd5U03Md8aw3j9q2phniCDb7cT/nfuyuwP0hjMv6+z9BSs3TuFTjNEe
yBMapTQ38XopcQdJOz5o9BMVuQTOOYsBkr5PuPxYhCQtn7KjzlrYo7bcjf8ANUNe7MTkep6gxqDL
3Ab899XHcpjJrvzOzwov9nxlk/XVIUn1soU2biMZ0ykS2AM5GfzU1lZWWDVN8WnKiULd7ZpLAZtE
Vzz2XrFzGZGtyeFbI5T9KG3tfge8YJGeXlo6E2ni+VrBan+vtX3z0NsQ1X2YZgGFIt8jtbdVA+tu
jYwV7WSj22P5tKotoCBvJdFM1ImlU4VwLFjLDAWo5cq33EmhdVPEcj23QqKGWUlGJz93E68Nxr4e
esESCEHvKp/y6toA3nO1wYdPuec8x/V7GpGXM8zvA8OC0t9Vzfht/VXBhkv3cXMCiMcPVBtrqR2y
V8udjMJ5n/COfQL2b/5QR05NQgzY/+0SR0efhR7osiuvGNTZWzlA7T4p0xto1v8liru4ENQ5yVQ5
aGe/TFd2xodz1GuAB7L2uS9iV12UCJdADBKFE6YVLA0U/ls26bgNWSLhuzEtBryeKBJCETEaYTTG
Q/MPW1Q5yt/qBrAnD9YcNRUlF6o2fs6QIRoQ0tAawA18HnUvDZglmi24i5aB+6PlG0pfEKtoWS57
ZuJa+BEa0TFvesxQ3GNU+Vc/r3ufNmrST4zHPIj3QhOFc16YYtlowFLKBk34sQHFc1pumrWKg6gu
mYZe777AhbEUAzy0esURFQai5cxNipDI63hDLW40sVRBnQDKBIPoqavZ9qpHyIUf6SGyrEb9vPgG
laVTkV2BGKS6wjBcYx6jDJCpVzd8GLc+/4bMaoEf+Z4mG7VZisarLDFYdvv7jSjHq3jz1mGKMvFt
ze9atez+wrm81WxTx2n77iGNpnP0F5SMDOZloDxebF0v0gRwPR3AR/VHK9ThMWWtTvSgeTO1C+Lv
GCnVvNtXbRHTiDwUScPEJnb2FBmNEOPBngHrQW/w/xQ8BDMg309Y3/q5lb2Me62I59tB0bqy6olA
rzoYqz5vsCoCTHVnhB82Cskg+DUY9dT/kVlaIISCx76uMCjjX0499Guoes4uGZ5GQiXM4unAWw60
Pe5Sx5wdxiFcOfHEEsO1E++tjU0s2RSleJauFZ5v/cZSFFaw1kI62vmKLHIIpNYbGYBrA0ETNB+k
DElGpYsJQhBibPpiGqNWZlxYLePm3TRBQUgW3WCKJrg41BiNtgqHOJR/Wf/G1d5INKblbfeqsHbU
wlRxidB8oGS8UyzTZlujNvPu1bnFQkj3dsx3r4oYY39NrNym7AQGsu2AhXPNTwx6o3LYxhGVB1p6
VR3FSSqRVlVXXvJOVALcdFOZK2oQTHVicQ4VUGEMY/05TfIrdRK6gvsvAKF2jbs5XQsZoTpcZGe1
Gld4QSdHlz5xxMXu
`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.all;
entity invalid is
port
(
ip0, ip1, ip2, ip3: in std_logic;
op0, op1, op2, op3: out std_logic
);
end;
architecture RTL of invalid is
signal s0, s1, s2, s3 : std_logic;
begin
-- Missing:
-- - s1 in sensitivity list.
process (s0, s3)
begin
case s1 is
when '0' =>
op0 <= s0;
when others =>
op0 <= s1;
end case;
end process;
-- Missing:
-- - s1 in sensitivity list.
-- - s0 in sensitivity list.
process (ip3)
begin
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
end case;
end process;
-- Missing
-- - op1 not defined when (s1 != '0').
process (s0, s1)
begin
op2 <= '0';
case s1 is
when '0' =>
op0 <= s0;
op1 <= (s0 or s1);
when others=>
op0 <= s1;
op2 <= '1';
end case;
end process;
-- Missing
-- - op0 not defined when ((s1 == '0') && (s2 = '0')).
process (s0, s1, s2)
begin
op2 <= '0';
case s1 is
when '0' =>
if (s2 = '0')
then
op0 <= s0;
else
op1 <= s1;
end if;
op1 <= (s0 or s1);
when others =>
op1 <= (s1 or '0');
op0 <= s1;
op2 <= '1';
end case;
end process;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Zedboard Demonstration design
-- Copyright (C) 2012 Fredrik Ringhage, Aeroflex Gaisler
-- Modifed by Jiri Gaisler to provide working AXI interface, 2014-04-05
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.config.all;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.jtag.all;
-- pragma translate_off
use gaisler.sim.all;
-- pragma translate_on
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
testahb : boolean := false
);
port (
processing_system7_0_MIO : inout std_logic_vector(53 downto 0);
processing_system7_0_PS_SRSTB : inout std_logic;
processing_system7_0_PS_CLK : inout std_logic;
processing_system7_0_PS_PORB : inout std_logic;
processing_system7_0_DDR_Clk : inout std_logic;
processing_system7_0_DDR_Clk_n : inout std_logic;
processing_system7_0_DDR_CKE : inout std_logic;
processing_system7_0_DDR_CS_n : inout std_logic;
processing_system7_0_DDR_RAS_n : inout std_logic;
processing_system7_0_DDR_CAS_n : inout std_logic;
processing_system7_0_DDR_WEB_pin : inout std_logic;
processing_system7_0_DDR_BankAddr : inout std_logic_vector(2 downto 0);
processing_system7_0_DDR_Addr : inout std_logic_vector(14 downto 0);
processing_system7_0_DDR_ODT : inout std_logic;
processing_system7_0_DDR_DRSTB : inout std_logic;
processing_system7_0_DDR_DQ : inout std_logic_vector(31 downto 0);
processing_system7_0_DDR_DM : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_DQS_n : inout std_logic_vector(3 downto 0);
processing_system7_0_DDR_VRN : inout std_logic;
processing_system7_0_DDR_VRP : inout std_logic;
button : in std_logic_vector(3 downto 0);
switch : inout std_logic_vector(7 downto 0);
led : out std_logic_vector(7 downto 0)
);
end;
architecture rtl of leon3mp is
component leon3_zedboard_stub
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FCLK_CLK0 : out STD_LOGIC;
FCLK_CLK1 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
S_AXI_GP0_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_arready : out STD_LOGIC;
S_AXI_GP0_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_arvalid : in STD_LOGIC;
S_AXI_GP0_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 ); --
S_AXI_GP0_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 ); --
S_AXI_GP0_awready : out STD_LOGIC;
S_AXI_GP0_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
S_AXI_GP0_awvalid : in STD_LOGIC;
S_AXI_GP0_bid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_bready : in STD_LOGIC;
S_AXI_GP0_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_bvalid : out STD_LOGIC;
S_AXI_GP0_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_rid : out STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_rlast : out STD_LOGIC;
S_AXI_GP0_rready : in STD_LOGIC;
S_AXI_GP0_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
S_AXI_GP0_rvalid : out STD_LOGIC;
S_AXI_GP0_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
S_AXI_GP0_wid : in STD_LOGIC_VECTOR ( 5 downto 0 ); --
S_AXI_GP0_wlast : in STD_LOGIC;
S_AXI_GP0_wready : out STD_LOGIC;
S_AXI_GP0_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
S_AXI_GP0_wvalid : in STD_LOGIC
);
end component;
constant maxahbm : integer := (CFG_LEON3*CFG_NCPU)+CFG_AHB_JTAG;
constant maxahbs : integer := 8;
constant maxapbs : integer := 16;
signal vcc, gnd : std_logic;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rsti, rst : std_ulogic;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to CFG_NCPU-1);
signal irqo : irq_out_vector(0 to CFG_NCPU-1);
signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal rxd1 : std_logic;
signal txd1 : std_logic;
signal gpti : gptimer_in_type;
signal gpto : gptimer_out_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
constant BOARD_FREQ : integer := 83333; -- CLK0 frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ;
signal stati : ahbstat_in_type;
constant CIDSZ : integer := 6;
constant CLENSZ : integer := 4;
signal S_AXI_GP0_araddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_arburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_arcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_arid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_arlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_arlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_arprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_awqos : STD_LOGIC_VECTOR ( 3 downto 0 ); --
signal S_AXI_GP0_arready : STD_LOGIC;
signal S_AXI_GP0_arsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_arvalid : STD_LOGIC;
signal S_AXI_GP0_awaddr : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_awburst : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_awcache : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_awid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_awlen : STD_LOGIC_VECTOR ( CLENSZ-1 downto 0 );
signal S_AXI_GP0_awlock : STD_LOGIC_VECTOR ( 1 downto 0 ); --
signal S_AXI_GP0_awprot : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awready : STD_LOGIC;
signal S_AXI_GP0_awsize : STD_LOGIC_VECTOR ( 2 downto 0 );
signal S_AXI_GP0_awvalid : STD_LOGIC;
signal S_AXI_GP0_bid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_bready : STD_LOGIC;
signal S_AXI_GP0_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_bvalid : STD_LOGIC;
signal S_AXI_GP0_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_rid : STD_LOGIC_VECTOR ( CIDSZ-1 downto 0 );
signal S_AXI_GP0_rlast : STD_LOGIC;
signal S_AXI_GP0_rready : STD_LOGIC;
signal S_AXI_GP0_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal S_AXI_GP0_rvalid : STD_LOGIC;
signal S_AXI_GP0_wdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal S_AXI_GP0_wlast : STD_LOGIC;
signal S_AXI_GP0_wready : STD_LOGIC;
signal S_AXI_GP0_wstrb : STD_LOGIC_VECTOR ( 3 downto 0 );
signal S_AXI_GP0_wvalid : STD_LOGIC;
signal S_AXI_GP0_wid : STD_LOGIC_VECTOR ( 5 downto 0 ); --
begin
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= '1'; gnd <= '0';
reset_pad : inpad generic map (level => cmos, voltage => x18v, tech => padtech)
port map (button(0), rsti);
rstn <= rst and not rsti;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, fpnpen => CFG_FPNPEN,
nahbm => maxahbm, nahbs => maxahbs)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon3_0 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to CFG_NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU*(1-CFG_GRFPUSH), CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP, CFG_NP_ASI, CFG_WRPSR)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
end generate;
nocpu : if CFG_LEON3 = 0 generate dbgo(0) <= dbgo_none; end generate;
led1_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(1), dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= gpioi.din(0);
end generate;
dsuact_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v) port map (led(0), dsuo.active);
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; ahbso(2) <= ahbs_none;
end generate;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_LEON3*CFG_NCPU)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_LEON3*CFG_NCPU),
open, open, open, open, open, open, open, gnd);
end generate;
leon3_zedboard_stub_i : leon3_zedboard_stub
port map (
DDR_ck_p => processing_system7_0_DDR_Clk,
DDR_ck_n => processing_system7_0_DDR_Clk_n,
DDR_cke => processing_system7_0_DDR_CKE,
DDR_cs_n => processing_system7_0_DDR_CS_n,
DDR_ras_n => processing_system7_0_DDR_RAS_n,
DDR_cas_n => processing_system7_0_DDR_CAS_n,
DDR_we_n => processing_system7_0_DDR_WEB_pin,
DDR_ba => processing_system7_0_DDR_BankAddr,
DDR_addr => processing_system7_0_DDR_Addr,
DDR_odt => processing_system7_0_DDR_ODT,
DDR_reset_n => processing_system7_0_DDR_DRSTB,
DDR_dq => processing_system7_0_DDR_DQ,
DDR_dm => processing_system7_0_DDR_DM,
DDR_dqs_p => processing_system7_0_DDR_DQS,
DDR_dqs_n => processing_system7_0_DDR_DQS_n,
FCLK_CLK0 => clkm,
FCLK_RESET0_N => rst,
FIXED_IO_mio => processing_system7_0_MIO,
FIXED_IO_ps_srstb => processing_system7_0_PS_SRSTB,
FIXED_IO_ps_clk => processing_system7_0_PS_CLK,
FIXED_IO_ps_porb => processing_system7_0_PS_PORB,
FIXED_IO_ddr_vrn => processing_system7_0_DDR_VRN,
FIXED_IO_ddr_vrp => processing_system7_0_DDR_VRP,
S_AXI_GP0_araddr => S_AXI_GP0_araddr,
S_AXI_GP0_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
S_AXI_GP0_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
S_AXI_GP0_arid => S_AXI_GP0_arid,
S_AXI_GP0_arlen => S_AXI_GP0_arlen,
S_AXI_GP0_arlock => S_AXI_GP0_arlock,
S_AXI_GP0_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
S_AXI_GP0_arqos => S_AXI_GP0_arqos,
S_AXI_GP0_awqos => S_AXI_GP0_awqos,
S_AXI_GP0_arready => S_AXI_GP0_arready,
S_AXI_GP0_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
S_AXI_GP0_arvalid => S_AXI_GP0_arvalid,
S_AXI_GP0_awaddr => S_AXI_GP0_awaddr,
S_AXI_GP0_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
S_AXI_GP0_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
S_AXI_GP0_awid => S_AXI_GP0_awid,
S_AXI_GP0_awlen => S_AXI_GP0_awlen,
S_AXI_GP0_awlock => S_AXI_GP0_awlock,
S_AXI_GP0_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
S_AXI_GP0_awready => S_AXI_GP0_awready,
S_AXI_GP0_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
S_AXI_GP0_awvalid => S_AXI_GP0_awvalid,
S_AXI_GP0_bid => S_AXI_GP0_bid,
S_AXI_GP0_bready => S_AXI_GP0_bready,
S_AXI_GP0_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
S_AXI_GP0_bvalid => S_AXI_GP0_bvalid,
S_AXI_GP0_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
S_AXI_GP0_rid => S_AXI_GP0_rid,
S_AXI_GP0_rlast => S_AXI_GP0_rlast,
S_AXI_GP0_rready => S_AXI_GP0_rready,
S_AXI_GP0_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
S_AXI_GP0_rvalid => S_AXI_GP0_rvalid,
S_AXI_GP0_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
S_AXI_GP0_wid => S_AXI_GP0_wid,
S_AXI_GP0_wlast => S_AXI_GP0_wlast,
S_AXI_GP0_wready => S_AXI_GP0_wready,
S_AXI_GP0_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
S_AXI_GP0_wvalid => S_AXI_GP0_wvalid
);
ahb2axi0 : entity work.ahb2axi
generic map(
hindex => 3, haddr => 16#400#, hmask => 16#F00#,
pindex => 0, paddr => 0, cidsz => CIDSZ, clensz => CLENSZ)
port map(
rstn => rstn,
clk => clkm,
ahbsi => ahbsi,
ahbso => ahbso(3),
apbi => apbi,
apbo => apbo(0),
M_AXI_araddr => S_AXI_GP0_araddr,
M_AXI_arburst(1 downto 0) => S_AXI_GP0_arburst(1 downto 0),
M_AXI_arcache(3 downto 0) => S_AXI_GP0_arcache(3 downto 0),
M_AXI_arid => S_AXI_GP0_arid,
M_AXI_arlen => S_AXI_GP0_arlen,
M_AXI_arlock => S_AXI_GP0_arlock,
M_AXI_arprot(2 downto 0) => S_AXI_GP0_arprot(2 downto 0),
M_AXI_arqos => S_AXI_GP0_arqos,
M_AXI_arready => S_AXI_GP0_arready,
M_AXI_arsize(2 downto 0) => S_AXI_GP0_arsize(2 downto 0),
M_AXI_arvalid => S_AXI_GP0_arvalid,
M_AXI_awaddr => S_AXI_GP0_awaddr,
M_AXI_awburst(1 downto 0) => S_AXI_GP0_awburst(1 downto 0),
M_AXI_awcache(3 downto 0) => S_AXI_GP0_awcache(3 downto 0),
M_AXI_awid => S_AXI_GP0_awid,
M_AXI_awlen => S_AXI_GP0_awlen,
M_AXI_awlock => S_AXI_GP0_awlock,
M_AXI_awprot(2 downto 0) => S_AXI_GP0_awprot(2 downto 0),
M_AXI_awqos => S_AXI_GP0_awqos,
M_AXI_awready => S_AXI_GP0_awready,
M_AXI_awsize(2 downto 0) => S_AXI_GP0_awsize(2 downto 0),
M_AXI_awvalid => S_AXI_GP0_awvalid,
M_AXI_bid => S_AXI_GP0_bid,
M_AXI_bready => S_AXI_GP0_bready,
M_AXI_bresp(1 downto 0) => S_AXI_GP0_bresp(1 downto 0),
M_AXI_bvalid => S_AXI_GP0_bvalid,
M_AXI_rdata(31 downto 0) => S_AXI_GP0_rdata(31 downto 0),
M_AXI_rid => S_AXI_GP0_rid,
M_AXI_rlast => S_AXI_GP0_rlast,
M_AXI_rready => S_AXI_GP0_rready,
M_AXI_rresp(1 downto 0) => S_AXI_GP0_rresp(1 downto 0),
M_AXI_rvalid => S_AXI_GP0_rvalid,
M_AXI_wdata(31 downto 0) => S_AXI_GP0_wdata(31 downto 0),
M_AXI_wlast => S_AXI_GP0_wlast,
M_AXI_wready => S_AXI_GP0_wready,
M_AXI_wstrb(3 downto 0) => S_AXI_GP0_wstrb(3 downto 0),
M_AXI_wvalid => S_AXI_GP0_wvalid
);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
irqgen : if CFG_LEON3 = 1 generate
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
end generate;
irqctrl : if (CFG_IRQ3_ENABLE + CFG_LEON3) /= 2 generate
x : for i in 0 to CFG_NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW, wdog => 0)
port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
pio_pads : for i in 0 to 7 generate
pio_pad : iopad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (switch(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
end generate;
pio_pads2 : for i in 8 to 10 generate
pio_pad : inpad generic map (tech => padtech, level => cmos, voltage => x18v)
port map (button(i-8+1), gpioi.din(i));
end generate;
pio_pads3 : for i in 11 to 14 generate
pio_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (led(i-11+4), gpioo.dout(i));
end generate;
end generate;
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.rxd <= rxd1;
u1i.ctsn <= '0';
u1i.extclk <= '0';
txd1 <= u1o.txd;
end generate;
noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
hready_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(2), ahbmi.hready);
rsti_pad : outpad generic map (level => cmos, voltage => x33v, tech => padtech)
port map (led(3), rsti);
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- AHB ROM ----------------------------------------------------------
-----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 0, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(0));
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 5, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(5));
end generate;
-----------------------------------------------------------------------
--- Test report module ----------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
test0_gen : if (testahb = true) generate
test0 : ahbrep generic map (hindex => 6, haddr => 16#200#)
port map (rstn, clkm, ahbsi, ahbso(6));
end generate;
-- pragma translate_on
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
nam1 : for i in (maxahbs+1) to NAHBMST-1 generate
ahbmo(i) <= ahbm_none;
end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Xilinx Zedboard Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
--========================================================================
-- alu.vhd :: Nova 16-bit ALU
--
-- (c) Scott L. Baker, Sierra Circuit Design
--========================================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.my_types.all;
entity ALU is
port (
RBUS : out std_logic_vector(15 downto 0); -- Result bus
CBIT : out std_logic; -- carry status flop
ZBIT : out std_logic; -- zero status flop
ABUS : in std_logic_vector(15 downto 0); -- Src reg
BBUS : in std_logic_vector(15 downto 0); -- Dst reg
ALU_OP : in ALU_OP_TYPE; -- ALU op
SHIFT_CTL : in SHIFT_CTL_TYPE; -- Shifter op
CARRY_CTL : in CARRY_CTL_TYPE; -- ALU op
UPDATE_C : in std_logic; -- update Carry flag
UPDATE_Z : in std_logic; -- update Zero flag
RESTORE : in std_logic; -- restore flags
SET_C : in std_logic; -- load CBIT from ACS(0)
RESET : in std_logic; -- reset
FEN : in std_logic; -- clock enable
CLK : in std_logic -- System clock
);
end ALU;
architecture BEHAVIORAL of ALU is
--=================================================================
-- Types, component, and signal definitions
--=================================================================
-- internal busses
signal AX : std_logic_vector(16 downto 0); -- ALU input A
signal BX : std_logic_vector(16 downto 0); -- ALU input B
signal SUM : std_logic_vector(16 downto 0); -- ALU output
signal SHF : std_logic_vector(15 downto 0); -- shifter output
-- internal carries
signal CIN : std_logic;
signal COUT : std_logic;
signal C16 : std_logic;
signal ZOUT : std_logic;
signal ALU_COUT : std_logic;
signal SHF_COUT : std_logic;
signal CBIT_FF : std_logic;
signal ZBIT_FF : std_logic;
signal OLD_CBIT : std_logic;
signal OLD_ZBIT : std_logic;
begin
--================================================================
-- Start of the behavioral description
--================================================================
--========================
-- ALU Opcode Decoding
--========================
ALU_OPCODE_DECODING:
process(ALU_OP, ABUS, BBUS, C16)
begin
-- default values
AX <= ABUS(15) & ABUS;
BX <= (others => '0');
CIN <= '0';
COUT <= '0';
case ALU_OP is
when NEG => -- 2's complement
AX <= not (ABUS(15) & ABUS);
CIN <= '1';
COUT <= C16;
when COM => -- 1's complement
AX <= not (ABUS(15) & ABUS);
when INC => -- Increment
CIN <= '1';
COUT <= C16;
when DEC => -- Decrement
BX <= (others => '1');
COUT <= C16;
when ADC => -- Add complement
AX <= not (ABUS(15) & ABUS);
BX <= BBUS(15) & BBUS;
COUT <= C16;
when SUB => -- Subtract
AX <= not (ABUS(15) & ABUS);
BX <= BBUS(15) & BBUS;
CIN <= '1';
COUT <= C16;
when ADD => -- Add
BX <= BBUS(15) & BBUS;
COUT <= C16;
when ANA => -- Logical And
BX <= BBUS(15) & BBUS;
when others => -- Transfer A
end case;
end process;
--========================
-- The ALU
--========================
ALU:
process(AX, BX, CIN, ALU_OP)
begin
SUM <= AX + BX + CIN;
if (ALU_OP = ANA) then
SUM <= AX and BX;
end if;
end process;
C16 <= SUM(16) xor AX(16) xor BX(16);
--========================
-- The ALU carry out
--========================
ALU_CARRY_CONTROL:
process(CARRY_CTL, COUT, CBIT_FF)
begin
case CARRY_CTL is
when CLEAR =>
ALU_COUT <= COUT;
when SET =>
ALU_COUT <= not COUT;
when INVERT =>
ALU_COUT <= CBIT_FF xnor COUT;
when others =>
ALU_COUT <= CBIT_FF xor COUT;
end case;
end process;
--========================
-- ALU output shifter
--========================
SHIFT_OPCODE_DECODING:
process(SHIFT_CTL, SUM, ALU_COUT)
begin
case SHIFT_CTL is
when LEFT => -- Rotate left
SHF(15 downto 1) <= SUM(14 downto 0);
SHF(0) <= ALU_COUT;
SHF_COUT <= SUM(15);
when RIGHT => -- Rotate right
SHF(14 downto 0) <= SUM(15 downto 1);
SHF(15) <= ALU_COUT;
SHF_COUT <= SUM(0);
when SWAP => -- Swap bytes
SHF(15 downto 8) <= SUM( 7 downto 0);
SHF( 7 downto 0) <= SUM(15 downto 8);
SHF_COUT <= ALU_COUT;
when others => -- No shift
SHF <= SUM(15 downto 0);
SHF_COUT <= ALU_COUT;
end case;
end process;
RBUS <= SHF;
ZOUT <= not (SHF(15) or SHF(14) or SHF(13) or SHF(12) or
SHF(11) or SHF(10) or SHF( 9) or SHF( 8) or
SHF( 7) or SHF( 6) or SHF( 5) or SHF( 4) or
SHF( 3) or SHF( 2) or SHF( 1) or SHF( 0));
--================================================================
-- carry status flip-flop
--================================================================
CARRY_STATUS_FLOP:
process(RESET, CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (UPDATE_C = '1') then
CBIT_FF <= SHF_COUT;
OLD_CBIT <= CBIT_FF;
end if;
if (RESTORE = '1') then
CBIT_FF <= OLD_CBIT;
end if;
if (SET_C = '1') then
CBIT_FF <= ABUS(15);
end if;
end if;
end if;
-- reset state
if (RESET = '1') then
CBIT_FF <= '0';
OLD_CBIT <= '0';
end if;
end process;
--================================================================
-- zero status flip-flop
--================================================================
ZERO_STATUS_FLOP:
process(RESET, CLK)
begin
if (CLK = '0' and CLK'event) then
if (FEN = '1') then
if (UPDATE_Z = '1') then
ZBIT_FF <= ZOUT;
OLD_ZBIT <= ZBIT_FF;
end if;
if (RESTORE = '1') then
ZBIT_FF <= OLD_ZBIT;
end if;
end if;
end if;
-- reset state
if (RESET = '1') then
ZBIT_FF <= '0';
OLD_ZBIT <= '0';
end if;
end process;
CBIT <= CBIT_FF;
ZBIT <= ZBIT_FF;
end BEHAVIORAL;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity SUBT is
port (A, B: in std_logic_vector(7 downto 0);
F : out std_logic_vector(7 downto 0);
Flag: out std_logic_vector(3 downto 0)
);
end SUBT;
architecture c1_estr of SUBT is
signal c, Bin, S: std_logic_vector(7 downto 0);
component fulladder
port (a, b, c: in std_logic;
soma, carry: out std_logic);
end component;
begin
Bin(0) <= B(0) xor '1';
Bin(1) <= B(1) xor '1';
Bin(2) <= B(2) xor '1';
Bin(3) <= B(3) xor '1';
Bin(4) <= B(4) xor '1';
Bin(5) <= B(5) xor '1';
Bin(6) <= B(6) xor '1';
Bin(7) <= B(7) xor '1';
A0: fulladder port map (A(0), Bin(0), '1', S(0), c(0));
A1: fulladder port map (A(1), Bin(1), c(0), S(1), c(1));
A2: fulladder port map (A(2), Bin(2), c(1), S(2), c(2));
A3: fulladder port map (A(3), Bin(3), c(2), S(3), c(3));
A4: fulladder port map (A(4), Bin(4), c(3), S(4), c(4));
A5: fulladder port map (A(5), Bin(5), c(4), S(5), c(5));
A6: fulladder port map (A(6), Bin(6), c(5), S(6), c(6));
A7: fulladder port map (A(7), Bin(7), c(6), S(7), c(7));
Flag(3) <= not (S(7) or S(6) or S(5) or S(4) or S(3) or S(2) or S(1) or S(0));
Flag(2) <= c(7) xor c(6);
Flag(1) <= c(7);
Flag(0) <= S(7);
F <= S;
end c1_estr;
|
architecture RTL of FIFO is
attribute coordinate of all : component is (0.0, 17.5);
attribute coordinate of ALL :component is (0.0, 17.5);
begin
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
use work.logi_primitive_pack.all ;
entity wishbone_gps is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
baudrate : positive := 115_200
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
rx_in : in std_logic
);
end wishbone_gps;
architecture Behavioral of wishbone_gps is
component async_serial is
generic(CLK_FREQ : positive := 100_000_000; BAUDRATE : positive := 115_200; NMEA_HEADER : string := "$GPRMC") ;
port( clk, reset : in std_logic ;
rx : in std_logic ;
tx : out std_logic ;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_ready : out std_logic ;
data_send : in std_logic ;
available : out std_logic
);
end component;
component nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic;
frame_error : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- uart signals
signal rx_register : std_logic_vector(7 downto 0);
signal ctrl_register : std_logic_vector(15 downto 0);
signal send_data, data_ready, uart_available : std_logic ;
-- nmea filter signals
signal new_nmea : std_logic ;
signal nmea_out : std_logic_vector(7 downto 0);
signal frame_error : std_logic ;
-- fifo signals
signal reset_fifo : std_logic ;
signal fifo_empty, fifo_full, pop_fifo : std_logic ;
signal fifo_out : std_logic_vector(15 downto 0);
-- 8 bit to 16 bit logic
signal new_nmea16, mod_count, end_of_frame : std_logic ;
signal char_buffer, nb_available, nmea_frame_size : std_logic_vector(7 downto 0);
signal nmea16 : std_logic_vector(15 downto 0);
-- double buffer signal
signal buffer_use : std_logic_vector(1 downto 0);
signal buffer_read_data : std_logic_vector(15 downto 0);
signal read_address, write_address : std_logic_vector(7 downto 0);
signal buffer_locked, free_buffer, end_of_frame_delayed : std_logic ;
signal write_buffer : std_logic ;
signal buffer_address, char_write_index : std_logic_vector(7 downto 0);
signal buffer_input : std_logic_vector(15 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
reset_fifo <= wbs_writedata(0) when write_ack = '1' else
--- '1' when frame_error = '1' else -- could corrupt ongoing frames ...
gls_reset;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
-- ctrl_register <= (others => '0');
-- wbs_readdata <= (others => '0');
read_ack <= '0' ;
elsif rising_edge(gls_clk) then
-- if read_ack = '1' and (wbs_strobe = '0' and wbs_cycle = '0' ) and wbs_address(4)='0' then -- reset when read
-- pop_fifo <= '1' ;
-- else
-- pop_fifo <= '0' ;
-- end if ;
--
-- ctrl_register(7 downto 0) <= nb_available ;
-- ctrl_register(15 downto 9) <= "0000000" ;
--
-- ctrl_register(8) <= fifo_full ;
--if reset_fifo = '1' then -- RS register for fifo full to detect overun
-- ctrl_register(8) <= '0' ;
-- elsif fifo_full = '1' then
-- ctrl_register(8) <= '1' ;
-- end if ;
-- if wbs_address(4) = '0' then
-- wbs_readdata <= fifo_out ;
-- else
-- wbs_readdata <= ctrl_register ;
-- end if ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1') then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
serial_0 : async_serial
generic map(CLK_FREQ => 100_000_000, BAUDRATE => baudrate)
port map( clk => gls_clk, reset => gls_reset ,
rx => rx_in,
tx => open,
data_out => rx_register,
data_in => (others => '0'),
data_ready => data_ready,
data_send => '0',
available => open
);
filter_nmea : nmea_frame_extractor
generic map(nmea_header => "$GPRMC")
port map(
clk => gls_clk, reset => (gls_reset or reset_fifo),
nmea_byte_in => rx_register,
new_byte_in => data_ready,
nmea_byte_out => nmea_out,
new_byte_out => new_nmea,
frame_size => nmea_frame_size,
end_of_frame => end_of_frame,
frame_error => frame_error
);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
char_buffer <= (others => '0');
mod_count <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
char_buffer <= (others => '0');
mod_count <= '0' ;
elsif new_nmea = '1' then
char_buffer <= nmea_out ;
mod_count <= not mod_count ;
end if ;
end if ;
end process ;
new_nmea16 <= new_nmea and mod_count ;
nmea16 <= nmea_out & char_buffer ;
--
---- handling nb_available manually ...
--process(gls_clk, gls_reset)
--begin
-- if gls_reset = '1' then
-- nb_available <= (others => '0');
-- elsif gls_clk'event and gls_clk = '1' then
-- if reset_fifo = '1' then
-- nb_available <= (others => '0');
-- elsif new_nmea16 = '1' and fifo_full = '0' and pop_fifo = '0' then
-- nb_available <= nb_available + 1 ;
-- elsif pop_fifo = '1' and fifo_empty = '0' and new_nmea16 = '0' then
-- nb_available <= nb_available - 1 ;
-- end if ;
-- end if ;
--end process ;
--
--fifo_0 : small_fifo
--generic map( WIDTH => 16, DEPTH => 64, THRESHOLD => 4)
--port map(clk => gls_clk,
-- resetn => (not reset_fifo),
-- push => new_nmea16,
-- pop => pop_fifo,
-- full => fifo_full,
-- empty => fifo_empty,
-- limit => open,
-- data_in => nmea16,
-- data_out => fifo_out
-- );
-- handle address
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
char_write_index <= (others => '0');
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
char_write_index <= X"01";
elsif new_nmea16 = '1' then
char_write_index <= char_write_index + 1 ;
end if ;
end_of_frame_delayed <= end_of_frame ;
end if ;
end process ;
buffer_address <= (others => '0') when end_of_frame_delayed = '1' else
char_write_index ;
buffer_input <= (X"00" & nmea_frame_size) when end_of_frame_delayed = '1' else
nmea16 ;
write_buffer <= new_nmea16 OR end_of_frame OR end_of_frame_delayed;
buffer_locked <= read_ack ;
wbs_readdata <= buffer_read_data ;
-- ram being used to implement the double buffer memory
ram0 : dpram_NxN
generic map(SIZE => 256, NBIT => 16, ADDR_WIDTH=> 8) -- need to be computed
port map(
clk => gls_clk,
we => write_buffer ,
di => buffer_input,
a => write_address ,
dpra => read_address,
spo => open,
dpo => buffer_read_data
);
-- highest bit select buffer to write to
write_address(write_address'high) <= buffer_use(1) ;
write_address(write_address'high-1 downto 0) <= buffer_address(write_address'high-1 downto 0);
read_address(read_address'high) <= buffer_use(0) ;
read_address(read_address'high-1 downto 0) <= wbs_address(read_address'high-1 downto 0);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
buffer_use <= "01" ;
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
free_buffer <= '1' ;
elsif free_buffer = '1' and buffer_locked = '0' then -- if write and one buffer at least is available
buffer_use <= not buffer_use ;
free_buffer <= '0' ;
end if ;
end if ;
end process ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:06:21 03/22/2014
-- Design Name:
-- Module Name: wishbone_uart - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.logi_utils_pack.all ;
use work.logi_primitive_pack.all ;
entity wishbone_gps is
generic(
wb_size : natural := 16 ; -- Data port size for wishbone
baudrate : positive := 115_200
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( wb_size-1 downto 0);
wbs_readdata : out std_logic_vector( wb_size-1 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic ;
rx_in : in std_logic
);
end wishbone_gps;
architecture Behavioral of wishbone_gps is
component async_serial is
generic(CLK_FREQ : positive := 100_000_000; BAUDRATE : positive := 115_200; NMEA_HEADER : string := "$GPRMC") ;
port( clk, reset : in std_logic ;
rx : in std_logic ;
tx : out std_logic ;
data_out : out std_logic_vector(7 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_ready : out std_logic ;
data_send : in std_logic ;
available : out std_logic
);
end component;
component nmea_frame_extractor is
generic(nmea_header : string := "$GPRMC");
port(
clk, reset : in std_logic ;
nmea_byte_in : in std_logic_vector(7 downto 0);
new_byte_in : in std_logic ;
nmea_byte_out : out std_logic_vector(7 downto 0);
new_byte_out : out std_logic;
frame_size : out std_logic_vector(7 downto 0);
end_of_frame : out std_logic;
frame_error : out std_logic
);
end component;
component small_fifo is
generic( WIDTH : positive := 8 ; DEPTH : positive := 8; THRESHOLD : positive := 4);
port(clk, resetn : in std_logic ;
push, pop : in std_logic ;
full, empty, limit : out std_logic ;
data_in : in std_logic_vector( WIDTH-1 downto 0);
data_out : out std_logic_vector(WIDTH-1 downto 0)
);
end component;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
-- uart signals
signal rx_register : std_logic_vector(7 downto 0);
signal ctrl_register : std_logic_vector(15 downto 0);
signal send_data, data_ready, uart_available : std_logic ;
-- nmea filter signals
signal new_nmea : std_logic ;
signal nmea_out : std_logic_vector(7 downto 0);
signal frame_error : std_logic ;
-- fifo signals
signal reset_fifo : std_logic ;
signal fifo_empty, fifo_full, pop_fifo : std_logic ;
signal fifo_out : std_logic_vector(15 downto 0);
-- 8 bit to 16 bit logic
signal new_nmea16, mod_count, end_of_frame : std_logic ;
signal char_buffer, nb_available, nmea_frame_size : std_logic_vector(7 downto 0);
signal nmea16 : std_logic_vector(15 downto 0);
-- double buffer signal
signal buffer_use : std_logic_vector(1 downto 0);
signal buffer_read_data : std_logic_vector(15 downto 0);
signal read_address, write_address : std_logic_vector(7 downto 0);
signal buffer_locked, free_buffer, end_of_frame_delayed : std_logic ;
signal write_buffer : std_logic ;
signal buffer_address, char_write_index : std_logic_vector(7 downto 0);
signal buffer_input : std_logic_vector(15 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
reset_fifo <= wbs_writedata(0) when write_ack = '1' else
--- '1' when frame_error = '1' else -- could corrupt ongoing frames ...
gls_reset;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
-- ctrl_register <= (others => '0');
-- wbs_readdata <= (others => '0');
read_ack <= '0' ;
elsif rising_edge(gls_clk) then
-- if read_ack = '1' and (wbs_strobe = '0' and wbs_cycle = '0' ) and wbs_address(4)='0' then -- reset when read
-- pop_fifo <= '1' ;
-- else
-- pop_fifo <= '0' ;
-- end if ;
--
-- ctrl_register(7 downto 0) <= nb_available ;
-- ctrl_register(15 downto 9) <= "0000000" ;
--
-- ctrl_register(8) <= fifo_full ;
--if reset_fifo = '1' then -- RS register for fifo full to detect overun
-- ctrl_register(8) <= '0' ;
-- elsif fifo_full = '1' then
-- ctrl_register(8) <= '1' ;
-- end if ;
-- if wbs_address(4) = '0' then
-- wbs_readdata <= fifo_out ;
-- else
-- wbs_readdata <= ctrl_register ;
-- end if ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1') then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
serial_0 : async_serial
generic map(CLK_FREQ => 100_000_000, BAUDRATE => baudrate)
port map( clk => gls_clk, reset => gls_reset ,
rx => rx_in,
tx => open,
data_out => rx_register,
data_in => (others => '0'),
data_ready => data_ready,
data_send => '0',
available => open
);
filter_nmea : nmea_frame_extractor
generic map(nmea_header => "$GPRMC")
port map(
clk => gls_clk, reset => (gls_reset or reset_fifo),
nmea_byte_in => rx_register,
new_byte_in => data_ready,
nmea_byte_out => nmea_out,
new_byte_out => new_nmea,
frame_size => nmea_frame_size,
end_of_frame => end_of_frame,
frame_error => frame_error
);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
char_buffer <= (others => '0');
mod_count <= '0' ;
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
char_buffer <= (others => '0');
mod_count <= '0' ;
elsif new_nmea = '1' then
char_buffer <= nmea_out ;
mod_count <= not mod_count ;
end if ;
end if ;
end process ;
new_nmea16 <= new_nmea and mod_count ;
nmea16 <= nmea_out & char_buffer ;
--
---- handling nb_available manually ...
--process(gls_clk, gls_reset)
--begin
-- if gls_reset = '1' then
-- nb_available <= (others => '0');
-- elsif gls_clk'event and gls_clk = '1' then
-- if reset_fifo = '1' then
-- nb_available <= (others => '0');
-- elsif new_nmea16 = '1' and fifo_full = '0' and pop_fifo = '0' then
-- nb_available <= nb_available + 1 ;
-- elsif pop_fifo = '1' and fifo_empty = '0' and new_nmea16 = '0' then
-- nb_available <= nb_available - 1 ;
-- end if ;
-- end if ;
--end process ;
--
--fifo_0 : small_fifo
--generic map( WIDTH => 16, DEPTH => 64, THRESHOLD => 4)
--port map(clk => gls_clk,
-- resetn => (not reset_fifo),
-- push => new_nmea16,
-- pop => pop_fifo,
-- full => fifo_full,
-- empty => fifo_empty,
-- limit => open,
-- data_in => nmea16,
-- data_out => fifo_out
-- );
-- handle address
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
char_write_index <= (others => '0');
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
char_write_index <= X"01";
elsif new_nmea16 = '1' then
char_write_index <= char_write_index + 1 ;
end if ;
end_of_frame_delayed <= end_of_frame ;
end if ;
end process ;
buffer_address <= (others => '0') when end_of_frame_delayed = '1' else
char_write_index ;
buffer_input <= (X"00" & nmea_frame_size) when end_of_frame_delayed = '1' else
nmea16 ;
write_buffer <= new_nmea16 OR end_of_frame OR end_of_frame_delayed;
buffer_locked <= read_ack ;
wbs_readdata <= buffer_read_data ;
-- ram being used to implement the double buffer memory
ram0 : dpram_NxN
generic map(SIZE => 256, NBIT => 16, ADDR_WIDTH=> 8) -- need to be computed
port map(
clk => gls_clk,
we => write_buffer ,
di => buffer_input,
a => write_address ,
dpra => read_address,
spo => open,
dpo => buffer_read_data
);
-- highest bit select buffer to write to
write_address(write_address'high) <= buffer_use(1) ;
write_address(write_address'high-1 downto 0) <= buffer_address(write_address'high-1 downto 0);
read_address(read_address'high) <= buffer_use(0) ;
read_address(read_address'high-1 downto 0) <= wbs_address(read_address'high-1 downto 0);
process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
buffer_use <= "01" ;
elsif gls_clk'event and gls_clk = '1' then
if end_of_frame_delayed = '1' then
free_buffer <= '1' ;
elsif free_buffer = '1' and buffer_locked = '0' then -- if write and one buffer at least is available
buffer_use <= not buffer_use ;
free_buffer <= '0' ;
end if ;
end if ;
end process ;
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- File: HFD4_5L_LatchingRelay.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- This module is designed to test the relay drive signals for the HFD4/4.5L
-- latching relay on the Zmod Scope family of products. The module checks if
-- timing is respected, checks for illegal drive signal combinations and compares
-- the expected relay state against the state determined based on the drive
-- signals sequence.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity HFD4_5L_LatchingRelay is
Generic (
-- Relay dynamic/static configuration
kExtRelayConfigEn : boolean := false;
-- Relay static configuration option; after initialization the relay state
-- determined based on the relay drive signals must mach kRelayConfigStatic if
-- kExtRelayConfigEn = false.
kRelayConfigStatic : std_logic := '0'
);
Port (
-- Relay dynamic configuration signal; after initialization the relay state
-- determined based on the relay drive signals must mach sRelayConfig if
-- kExtRelayConfigEn = true.
sRelayConfig : in std_logic;
-- Relay drive signals
sRelayDriverH : in std_logic;
sRelayDriverL : in std_logic;
sRelayComH : in std_logic;
sRelayComL : in std_logic
);
end HFD4_5L_LatchingRelay;
architecture Behavioral of HFD4_5L_LatchingRelay is
begin
CheckSetup: process
begin
-- Wait until now /= 0 ps.
-- Check Idle condition
if (now /= 0 ps) then
assert ((sRelayDriverL = '0') and (sRelayDriverH = '0'))
report "Relay drive signals idle state not respected." & LF & HT & HT
severity ERROR;
end if;
-- Wait for first event on the drive signals when exiting idle condition
wait until ((sRelayDriverH'event) or (sRelayDriverL'event));
-- Check timing for set command
if ((sRelayDriverH = '1') and (sRelayDriverL = '0') and (sRelayComH = '0') and (sRelayComL = '1')) then
-- Wait for drive signals to change state (only transitioning to idle state is accepted at this step)
wait until ((sRelayDriverH'event) or (sRelayDriverL'event) or (sRelayComH'event) or (sRelayComL'event));
-- Check that the relay drive signals return to idle state
assert ((sRelayDriverL = '0') and (sRelayDriverH = '0') and (sRelayComL = '0') and (sRelayComH = '0'))
report "Relay drive signals do not return to idle state after relay set/reset operation" & LF & HT & HT
severity ERROR;
assert ((sRelayDriverL'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay driver low." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayDriverL'delayed'last_event)
severity ERROR;
assert ((sRelayDriverH'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay driver high." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayDriverH'delayed'last_event)
severity ERROR;
assert ((sRelayComL'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay com low." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayComH'delayed'last_event)
severity ERROR;
assert ((sRelayComH'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay com high." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayComL'delayed'last_event)
severity ERROR;
if (kExtRelayConfigEn = true) then
-- Check if the command that triggered the event was a relay set command
assert (sRelayConfig = '1')
report "Relay state does not coincide with dynamic prescribed state." & LF & HT & HT &
"RelayState: " & std_logic'image('1') & LF & HT & HT &
"RelayCommand: " & std_logic'image(sRelayConfig) & LF & HT & HT
severity ERROR;
else
assert (kRelayConfigStatic = '1')
report "Relay state does not coincide with static prescribed state." & LF & HT & HT
severity ERROR;
end if;
-- Check timing for reset command
elsif ((sRelayDriverH = '0') and (sRelayDriverL = '1') and (sRelayComH = '1') and (sRelayComL = '0')) then
-- Wait for drive signals to change state (only transitioning to idle state is accepted at this step)
wait until ((sRelayDriverH'event) or (sRelayDriverL'event));
-- Check that the relay drive signals return to idle state
assert ((sRelayDriverL = '0') and (sRelayDriverH = '0') and (sRelayComL = '0') and (sRelayComH = '0'))
report "Relay drive signals do not return to idle state after rela set/reset operation" & LF & HT & HT
severity ERROR;
assert ((sRelayDriverL'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay driver low." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayDriverL'delayed'last_event)
severity ERROR;
assert ((sRelayDriverH'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay driver high." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayDriverH'delayed'last_event)
severity ERROR;
assert ((sRelayComL'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay com low." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayComH'delayed'last_event)
severity ERROR;
assert ((sRelayComH'delayed'last_event >= kRelayConfigTime))
report "Relay configuration time smaller than kRelayConfigTime for relay com high." & LF & HT & HT &
"Expected: " & time'image(kRelayConfigTime) & LF & HT & HT &
"Actual: " & time'image(sRelayComL'delayed'last_event)
severity ERROR;
if (kExtRelayConfigEn = true) then
-- Check if the command that triggered the event was a relay reset command
assert (sRelayConfig = '0')
report "Relay state does not coincide with dynamic prescribed state." & LF & HT & HT &
"RelayState: " & std_logic'image('0') & LF & HT & HT &
"RelayCommand: " & std_logic'image(sRelayConfig) & LF & HT & HT
severity ERROR;
else
assert (kRelayConfigStatic = '0')
report "Relay state does not coincide with static prescribed state." & LF & HT & HT
severity ERROR;
end if;
-- For any other event on the com signals (other relays configured) sRelayDriverH
-- and sRelayDriverL must be '0'
elsif ((sRelayDriverH /= '0') or (sRelayDriverL /= '0')) then
report "Invalid relay driver drive signal combinations." & LF & HT & HT &
"sRelayDriverH: " & std_logic'image(sRelayDriverH) & LF & HT & HT &
"sRelayDriverL: " & std_logic'image(sRelayDriverL) & LF & HT & HT &
"sRelayComH: " & std_logic'image(sRelayComH) & LF & HT & HT &
"sRelayComL: " & std_logic'image(sRelayComL)
severity ERROR;
end if;
end process CheckSetup;
end Behavioral;
|
-- Audio Resampler And Filter for Konami Arcade Chassis Emulator
-- Copyright (C) 2011 Christopher D. Kilgour
--
-- This program is free software; you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 2
-- of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--
-- The main clock is 12288000 Hz, where an 18-bit output audio sample is
-- delivered every 256 clocks at 48000 Hz.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity resampler is
port (
clk: in std_logic;
reset: in std_logic;
psgclk: out std_logic;
psgnew: out std_logic; -- high when a new sample taken
sample_1: in std_logic_vector(7 downto 0);
select_1: out std_logic_vector(1 downto 0);
chan1_en: in std_logic_vector(2 downto 0); -- CBA enables
chan1_filt: in std_logic_vector(5 downto 0); -- 2-bits each for CBA
sample_2: in std_logic_vector(7 downto 0);
select_2: out std_logic_vector(1 downto 0);
chan2_en: in std_logic_vector(2 downto 0); -- CBA enables
chan2_filt: in std_logic_vector(5 downto 0); -- 2-bits each for CBA
audio: out std_logic_vector(17 downto 0);
audio_en: out std_logic -- high for one clock when the samples
-- are taken by the sink
);
attribute SIGIS : string;
attribute SIGIS of clk : signal is "CLK";
attribute SIGIS of reset : signal is "RST";
end entity resampler;
-------------------------------------------------------------------------------
architecture behaviour of resampler is
signal head : unsigned(4 downto 0);
signal local_sample_en, start_filt, output_en : std_logic;
type psgbuf is array (0 to 31) of signed(23 downto 0);
signal psg1a, psg1b, psg1c, psg2a, psg2b, psg2c : psgbuf;
signal clk3of5, clk18432 : std_logic;
signal clk96, clk48 : std_logic;
signal countB : unsigned(7 downto 0);
-- 32 bits in 9.23 format
signal filt1a, filt1b, filt1c,
filt2a, filt2b, filt2c : signed(31 downto 0);
-- indices into filters
signal fix1a, fix1b, fix1c, fix2a, fix2b, fix2c : integer;
begin
-- map filter indices
fix1a <= to_integer(unsigned(chan1_filt(1 downto 0)));
fix1b <= to_integer(unsigned(chan1_filt(3 downto 2)));
fix1c <= to_integer(unsigned(chan1_filt(5 downto 4)));
fix2a <= to_integer(unsigned(chan2_filt(1 downto 0)));
fix2b <= to_integer(unsigned(chan2_filt(3 downto 2)));
fix2c <= to_integer(unsigned(chan2_filt(5 downto 4)));
-- generate a 3-of-5, 96k and 48k
gen3of5 : process( clk, reset ) is
variable countA : unsigned(2 downto 0);
begin
if reset = '1' then
countA := "000";
countB <= X"00";
clk3of5 <= '0';
elsif clk'event and clk = '1' then
countB <= countB - 1;
if countA = 4 then
countA := "000";
else
countA := countA + 1;
end if;
if (countA = 0) or (countA = 2) or (countA = 4) then
clk3of5 <= not clk3of5;
end if;
end if;
end process;
clk96 <= std_logic(countB(6));
clk48 <= std_logic(countB(7));
-- generate clocks for the PSG chips
gen18432 : process( clk3of5, reset ) is
begin
if reset = '1' then
clk18432 <= '0';
elsif clk3of5'event and clk3of5 = '1' then
clk18432 <= not clk18432;
end if;
end process;
-- the PSG sampling runs once every 16 at 115200 kHz
psggen : process( clk18432, reset ) is
variable count : unsigned(3 downto 0);
begin
if reset = '1' then
count := "0000";
local_sample_en <= '0';
elsif clk18432'event and clk18432 = '1' then
if (count = 15) then
local_sample_en <= '1';
else
local_sample_en <= '0';
end if;
count := count + 1;
end if;
end process;
psgclk <= clk18432;
psgnew <= local_sample_en;
-- sample the PSG outputs at 115200 Hz, drop 1-of-6 for 96000 Hz
-- original samples are in 0.8 unsigned format, which are extended to 1.8 format,
-- then multiplied by gain in 1.14 format yielding 2.22 format
psggrab : process( clk, reset ) is
variable decount : unsigned(3 downto 0);
type TSTATE is (IDLE, CHANA, CHANB, CHANC, HALT);
variable state : TSTATE := IDLE;
-- constant gain in 1.14 format
type TGAIN is array(0 to 3) of signed(14 downto 0);
constant GAINS : TGAIN := ( "010" & X"023", -- 1/1.9913, 24kHz
"000" & X"35b", -- 1/19.070, 723Hz
"000" & X"45d", -- 1/14.656, 3386Hz
"000" & X"357" -- 1/19.144, 596Hz
);
begin
if reset = '1' then
head <= "00000";
decount := "0000";
state := IDLE;
select_1 <= "11";
select_2 <= "11";
elsif clk'event and clk = '1' then
case state is
when IDLE =>
if local_sample_en = '1' then
if decount /= 5 then
decount := decount + 1;
select_1 <= "00";
select_2 <= "00";
state := CHANA;
else
decount := "0000";
state := HALT;
end if;
end if;
when CHANA =>
if (chan1_en(0) = '1') then
psg1a(to_integer(head)) <= signed('0' & sample_1) * GAINS(fix1a);
else
psg1a(to_integer(head)) <= (others => '0');
end if;
if (chan2_en(0) = '1') then
psg2a(to_integer(head)) <= signed('0' & sample_2) * GAINS(fix2a);
else
psg2a(to_integer(head)) <= (others => '0');
end if;
select_1 <= "01";
select_2 <= "01";
state := CHANB;
when CHANB =>
if (chan1_en(1) = '1') then
psg1b(to_integer(head)) <= signed('0' & sample_1) * GAINS(fix1b);
else
psg1b(to_integer(head)) <= (others => '0');
end if;
if (chan2_en(1) = '1') then
psg2b(to_integer(head)) <= signed('0' & sample_2) * GAINS(fix2b);
else
psg2b(to_integer(head)) <= (others => '0');
end if;
select_1 <= "10";
select_2 <= "10";
state := CHANC;
when CHANC =>
if (chan1_en(2) = '1') then
psg1c(to_integer(head)) <= signed('0' & sample_1) * GAINS(fix1c);
else
psg1c(to_integer(head)) <= (others => '0');
end if;
if (chan2_en(2) = '1') then
psg2c(to_integer(head)) <= signed('0' & sample_2) * GAINS(fix2c);
else
psg2c(to_integer(head)) <= (others => '0');
end if;
head <= head + 1;
state := HALT;
when HALT =>
if local_sample_en = '0' then
state := IDLE;
end if;
when others => null;
end case;
end if;
end process;
start_filt <= '1' when countB(6 downto 0) = 121 -- selected so as to
-- avoid the sampling of
-- the PSGs
else '0';
-- At 96000 Hz, filter the oldest 17 samples for each channel
-- Scaled PSG audio is available in 2.22 format, here truncated to 2.14 bits
-- and MACed against 2.14 coefficients, each multiplication yields a 4.28
-- result.
filt : process( clk, reset )
-- 16 bits in 2.14 format
type TCOEFF is array(0 to 16) of signed(15 downto 0);
constant FILT24K : TCOEFF := (X"ff2e", -- -0.012820
X"00cb", -- 0.012419
X"004d", -- 0.004739
X"fe9f", -- -0.021598
X"0363", -- 0.052918
X"fb42", -- -0.074142
X"f69d", -- -0.146680
X"253d", -- 0.581888
X"4ca8", -- 1.197806
X"253d", -- 0.581888
X"f69d", -- -0.146680
X"fb42", -- -0.074142
X"0363", -- 0.052918
X"fe9f", -- -0.021598
X"004d", -- 0.004739
X"00cb", -- 0.012419
X"ff2e" -- -0.012820
);
constant FILT723 : TCOEFF := (X"463b", -- 1.097387
X"46d0", -- 1.106476
X"4752", -- 1.114392
X"47c0", -- 1.121121
X"481a", -- 1.126646
X"4861", -- 1.130956
X"4894", -- 1.134042
X"48b2", -- 1.135895
X"48bc", -- 1.136514
X"48b2", -- 1.135895
X"4894", -- 1.134042
X"4861", -- 1.130956
X"481a", -- 1.126646
X"47c0", -- 1.121121
X"4752", -- 1.114392
X"46d0", -- 1.106476
X"463b" -- 1.097387
);
constant FILT3K4 : TCOEFF := (X"1da9", -- 0.463487
X"25bf", -- 0.589803
X"2dae", -- 0.713773
X"3520", -- 0.830105
X"3bc0", -- 0.933647
X"4142", -- 1.019685
X"4563", -- 1.084222
X"47f3", -- 1.124215
X"48d1", -- 1.137762
X"47f3", -- 1.124215
X"4563", -- 1.084222
X"4142", -- 1.019685
X"3bc0", -- 0.933647
X"3520", -- 0.830105
X"2dae", -- 0.713773
X"25bf", -- 0.589803
X"1da9" -- 0.463487
);
constant FILT596 : TCOEFF := (X"4702", -- 1.109511
X"4767", -- 1.115719
X"47c0", -- 1.121119
X"480b", -- 1.125701
X"4849", -- 1.129460
X"4879", -- 1.132389
X"489b", -- 1.134485
X"48b0", -- 1.135743
X"48b6", -- 1.136163
X"48b0", -- 1.135743
X"489b", -- 1.134485
X"4879", -- 1.132389
X"4849", -- 1.129460
X"480b", -- 1.125701
X"47c0", -- 1.121119
X"4767", -- 1.115719
X"4702" -- 1.109511
);
type TFILTS is array(0 to 3) of TCOEFF;
variable FILTERS : TFILTS;
variable bindex, findex : unsigned(4 downto 0);
variable idle : std_logic;
begin
if reset = '1' then
bindex := "00000";
findex := "00000";
idle := '1';
FILTERS(0) := FILT24K;
FILTERS(1) := FILT723;
FILTERS(2) := FILT3K4;
FILTERS(3) := FILT596;
elsif clk'event and clk = '1' then
-- determine when to kick off
if (idle = '1') then
if (start_filt = '1') then
idle := '0';
findex := "00000";
bindex := head - 1;
filt1a <= (others => '0');
filt1b <= (others => '0');
filt1c <= (others => '0');
filt2a <= (others => '0');
filt2b <= (others => '0');
filt2c <= (others => '0');
end if;
else
-- FIR MACs
filt1a <= filt1a + (psg1a(to_integer(bindex))(23 downto 8) *
filters(fix1a)(to_integer(findex)));
filt1b <= filt1b + (psg1b(to_integer(bindex))(23 downto 8) *
filters(fix1b)(to_integer(findex)));
filt1c <= filt1c + (psg1c(to_integer(bindex))(23 downto 8) *
filters(fix1c)(to_integer(findex)));
filt2a <= filt2a + (psg2a(to_integer(bindex))(23 downto 8) *
filters(fix2a)(to_integer(findex)));
filt2b <= filt2b + (psg2b(to_integer(bindex))(23 downto 8) *
filters(fix2b)(to_integer(findex)));
filt2c <= filt2c + (psg2c(to_integer(bindex))(23 downto 8) *
filters(fix2c)(to_integer(findex)));
-- index update and termination
if (findex = "10000") then
idle := '1';
else
findex := findex + 1;
bindex := bindex - 1;
end if;
end if;
end if;
end process;
-- the mixer combines all six filtered channels to produce a 1.17 result that
-- is scaled at 6/8ths of full-scale
mix : process( clk, reset )
variable count : unsigned(0 downto 0);
variable idle : std_logic;
variable result : signed(17 downto 0);
begin
if reset = '1' then
audio <= "00" & X"0000";
output_en <= '0';
count := "0";
idle := '1';
result := (others => '0');
elsif clk'event and clk = '1' then
if (idle = '1') then
output_en <= '0';
if (start_filt = '1') then
if (count = "1") then
idle := '0';
end if;
result := filt1a(31 downto 14) +
filt1b(31 downto 14) +
filt1c(31 downto 14) +
filt2a(31 downto 14) +
filt2b(31 downto 14) +
filt2c(31 downto 14);
count := count + 1;
end if;
else
if (start_filt = '0') then
idle := '1';
output_en <= '1';
audio <= std_logic_vector( result );
end if;
end if;
end if;
end process;
audio_en <= output_en;
end architecture behaviour;
|
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------
-------------------------------------------------------------------------------
-- Filename: axi_dma_mm2s_mngr.vhd
-- Description: This entity is the top level entity for the AXI DMA MM2S
-- manager.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_dma_v7_1;
use axi_dma_v7_1.axi_dma_pkg.all;
-------------------------------------------------------------------------------
entity axi_dma_mm2s_mngr is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
-----------------------------------------------------------------------
-- Scatter Gather Parameters
-----------------------------------------------------------------------
C_INCLUDE_SG : integer range 0 to 1 := 1;
-- Include or Exclude the Scatter Gather Engine
-- 0 = Exclude SG Engine - Enables Simple DMA Mode
-- 1 = Include SG Engine - Enables Scatter Gather Mode
C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1;
-- Include or Exclude AXI Status and AXI Control Streams
-- 0 = Exclude Status and Control Streams
-- 1 = Include Status and Control Streams
C_SG_INCLUDE_DESC_QUEUE : integer range 0 to 1 := 0;
-- Include or Exclude Scatter Gather Descriptor Queuing
-- 0 = Exclude SG Descriptor Queuing
-- 1 = Include SG Descriptor Queuing
C_SG_LENGTH_WIDTH : integer range 8 to 23 := 14;
-- Descriptor Buffer Length, Transferred Bytes, and Status Stream
-- Rx Length Width. Indicates the least significant valid bits of
-- descriptor buffer length, transferred bytes, or Rx Length value
-- in the status word coincident with tlast.
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- AXI Master Stream in for descriptor fetch
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33;
-- 1 IOC bit + 32 Update Status Bits
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
-----------------------------------------------------------------------
-- Memory Map to Stream (MM2S) Parameters
-----------------------------------------------------------------------
C_INCLUDE_MM2S : integer range 0 to 1 := 1;
-- Include or exclude MM2S primary data path
-- 0 = Exclude MM2S primary data path
-- 1 = Include MM2S primary data path
C_M_AXI_MM2S_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for MM2S Read Port
C_ENABLE_MULTI_CHANNEL : integer range 0 to 1 := 0;
C_MICRO_DMA : integer range 0 to 1 := 0;
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary Clock and Reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary Clock and Reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
soft_reset : in std_logic ; --
--
-- MM2S Control and Status --
mm2s_run_stop : in std_logic ; --
mm2s_keyhole : in std_logic ;
mm2s_halted : in std_logic ; --
mm2s_ftch_idle : in std_logic ; --
mm2s_updt_idle : in std_logic ; --
mm2s_ftch_err_early : in std_logic ; --
mm2s_ftch_stale_desc : in std_logic ; --
mm2s_tailpntr_enble : in std_logic ; --
mm2s_halt : in std_logic ; --
mm2s_halt_cmplt : in std_logic ; --
mm2s_halted_clr : out std_logic ; --
mm2s_halted_set : out std_logic ; --
mm2s_idle_set : out std_logic ; --
mm2s_idle_clr : out std_logic ; --
mm2s_new_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
mm2s_new_curdesc_wren : out std_logic ; --
mm2s_stop : out std_logic ; --
mm2s_desc_flush : out std_logic ; --
cntrl_strm_stop : out std_logic ;
mm2s_all_idle : out std_logic ; --
--
mm2s_error : out std_logic ; --
s2mm_error : in std_logic ; --
-- Simple DMA Mode Signals
mm2s_sa : in std_logic_vector --
(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); --
mm2s_length_wren : in std_logic ; --
mm2s_length : in std_logic_vector --
(C_SG_LENGTH_WIDTH-1 downto 0) ; --
mm2s_smple_done : out std_logic ; --
mm2s_interr_set : out std_logic ; --
mm2s_slverr_set : out std_logic ; --
mm2s_decerr_set : out std_logic ; --
m_axis_mm2s_aclk : in std_logic;
mm2s_strm_tlast : in std_logic;
mm2s_strm_tready : in std_logic;
mm2s_axis_info : out std_logic_vector
(13 downto 0);
--
-- SG MM2S Descriptor Fetch AXI Stream In --
m_axis_mm2s_ftch_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_ftch_tvalid : in std_logic ; --
m_axis_mm2s_ftch_tready : out std_logic ; --
m_axis_mm2s_ftch_tlast : in std_logic ; --
m_axis_mm2s_ftch_tdata_new : in std_logic_vector --
(96+31*0+(0+2)*(C_M_AXI_SG_ADDR_WIDTH-32) downto 0); --
m_axis_mm2s_ftch_tdata_mcdma_new : in std_logic_vector --
(63 downto 0); --
m_axis_mm2s_ftch_tvalid_new : in std_logic ; --
m_axis_ftch1_desc_available : in std_logic;
--
-- SG MM2S Descriptor Update AXI Stream Out --
s_axis_mm2s_updtptr_tdata : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0); --
s_axis_mm2s_updtptr_tvalid : out std_logic ; --
s_axis_mm2s_updtptr_tready : in std_logic ; --
s_axis_mm2s_updtptr_tlast : out std_logic ; --
--
s_axis_mm2s_updtsts_tdata : out std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_mm2s_updtsts_tvalid : out std_logic ; --
s_axis_mm2s_updtsts_tready : in std_logic ; --
s_axis_mm2s_updtsts_tlast : out std_logic ; --
--
-- User Command Interface Ports (AXI Stream) --
s_axis_mm2s_cmd_tvalid : out std_logic ; --
s_axis_mm2s_cmd_tready : in std_logic ; --
s_axis_mm2s_cmd_tdata : out std_logic_vector --
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0);--
--
-- User Status Interface Ports (AXI Stream) --
m_axis_mm2s_sts_tvalid : in std_logic ; --
m_axis_mm2s_sts_tready : out std_logic ; --
m_axis_mm2s_sts_tdata : in std_logic_vector(7 downto 0) ; --
m_axis_mm2s_sts_tkeep : in std_logic_vector(0 downto 0) ; --
mm2s_err : in std_logic ; --
--
ftch_error : in std_logic ; --
updt_error : in std_logic ; --
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_dma_mm2s_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_dma_mm2s_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
attribute mark_debug : string;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Primary DataMover Command signals
signal mm2s_cmnd_wr : std_logic := '0';
signal mm2s_cmnd_data : std_logic_vector
((C_M_AXI_MM2S_ADDR_WIDTH-32+2*32+CMD_BASE_WIDTH+46)-1 downto 0) := (others => '0');
signal mm2s_cmnd_pending : std_logic := '0';
attribute mark_debug of mm2s_cmnd_data : signal is "true";
-- Primary DataMover Status signals
signal mm2s_done : std_logic := '0';
signal mm2s_stop_i : std_logic := '0';
signal mm2s_interr : std_logic := '0';
signal mm2s_slverr : std_logic := '0';
signal mm2s_decerr : std_logic := '0';
attribute mark_debug of mm2s_interr : signal is "true";
attribute mark_debug of mm2s_slverr : signal is "true";
attribute mark_debug of mm2s_decerr : signal is "true";
signal mm2s_tag : std_logic_vector(3 downto 0) := (others => '0');
signal dma_mm2s_error : std_logic := '0';
signal soft_reset_d1 : std_logic := '0';
signal soft_reset_d2 : std_logic := '0';
signal soft_reset_re : std_logic := '0';
signal mm2s_error_i : std_logic := '0';
--signal cntrl_strm_stop : std_logic := '0';
signal mm2s_halted_set_i : std_logic := '0';
signal mm2s_sts_received_clr : std_logic := '0';
signal mm2s_sts_received : std_logic := '0';
signal mm2s_cmnd_idle : std_logic := '0';
signal mm2s_sts_idle : std_logic := '0';
-- Scatter Gather Interface signals
signal desc_fetch_req : std_logic := '0';
signal desc_fetch_done : std_logic := '0';
signal desc_fetch_done_del : std_logic := '0';
signal desc_update_req : std_logic := '0';
signal desc_update_done : std_logic := '0';
signal desc_available : std_logic := '0';
signal packet_in_progress : std_logic := '0';
signal mm2s_desc_baddress : std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_v : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_blength_s : std_logic_vector(BUFFER_LENGTH_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_eof : std_logic := '0';
signal mm2s_desc_sof : std_logic := '0';
signal mm2s_desc_cmplt : std_logic := '0';
signal mm2s_desc_info : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app0 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app1 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app2 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app3 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_app4 : std_logic_vector(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) := (others => '0');
signal mm2s_desc_info_int : std_logic_vector(13 downto 0) := (others => '0');
signal mm2s_strm_tlast_int : std_logic;
signal rd_en_hold, rd_en_hold_int : std_logic;
-- Control Stream Fifo write signals
signal cntrlstrm_fifo_wren : std_logic := '0';
signal cntrlstrm_fifo_full : std_logic := '0';
signal cntrlstrm_fifo_din : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal info_fifo_full : std_logic;
signal info_fifo_empty : std_logic;
signal updt_pending : std_logic := '0';
signal mm2s_cmnd_wr_1 : std_logic := '0';
signal fifo_rst : std_logic;
signal fifo_empty : std_logic;
signal fifo_empty_first : std_logic;
signal fifo_empty_first1 : std_logic;
signal first_read_pulse : std_logic;
signal fifo_read : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Include MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 1 generate
begin
-- Pass out to register module
mm2s_halted_set <= mm2s_halted_set_i;
-------------------------------------------------------------------------------
-- Graceful shut down logic
-------------------------------------------------------------------------------
-- Error from DataMover (DMAIntErr, DMADecErr, or DMASlvErr) or SG Update error
-- or SG Fetch error, or Stale Descriptor Error
mm2s_error_i <= dma_mm2s_error -- Primary data mover reports error
or updt_error -- SG Update engine reports error
or ftch_error -- SG Fetch engine reports error
or mm2s_ftch_err_early -- SG Fetch engine reports early error on mm2s
or mm2s_ftch_stale_desc; -- SG Fetch stale descriptor error
-- pass out to shut down s2mm
mm2s_error <= mm2s_error_i;
-- Clear run/stop and stop state machines due to errors or soft reset
-- Error based on datamover error report or sg update error or sg fetch error
-- SG update error and fetch error included because need to shut down, no way
-- to update descriptors on sg update error and on fetch error descriptor
-- data is corrupt therefor do not want to issue the xfer command to primary datamover
--CR#566306 status for both mm2s and s2mm datamover are masked during shutdown therefore
-- need to stop all processes regardless of the source of the error.
-- mm2s_stop_i <= mm2s_error -- Error
-- or soft_reset; -- Soft Reset issued
mm2s_stop_i <= mm2s_error_i -- Error on MM2S
or s2mm_error -- Error on S2MM
or soft_reset; -- Soft Reset issued
-- Reg stop out
REG_STOP_OUT : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop <= '0';
else
mm2s_stop <= mm2s_stop_i;
end if;
end if;
end process REG_STOP_OUT;
-- Generate DMA Controller For Scatter Gather Mode
GEN_SCATTER_GATHER_MODE : if C_INCLUDE_SG = 1 generate
begin
-- Not Used in SG Mode (Errors are imbedded in updated descriptor and
-- generate error after descriptor update is complete)
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
mm2s_cmnd_wr_1 <= m_axis_mm2s_ftch_tvalid_new;
---------------------------------------------------------------------------
-- MM2S Primary DMA Controller State Machine
---------------------------------------------------------------------------
I_MM2S_SM : entity axi_dma_v7_1.axi_dma_mm2s_sm
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
mm2s_run_stop => mm2s_run_stop ,
mm2s_keyhole => mm2s_keyhole ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
mm2s_stop => mm2s_stop_i ,
mm2s_desc_flush => mm2s_desc_flush ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
desc_update_done => desc_update_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- DataMover Command
mm2s_cmnd_wr => open, --mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
-- Descriptor Fields
mm2s_cache_info => mm2s_desc_info ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof
);
---------------------------------------------------------------------------
-- MM2S Scatter Gather State Machine
---------------------------------------------------------------------------
I_MM2S_SG_IF : entity axi_dma_v7_1.axi_dma_mm2s_sg_if
generic map(
-------------------------------------------------------------------
-- Scatter Gather Parameters
-------------------------------------------------------------------
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_SG_INCLUDE_DESC_QUEUE => C_SG_INCLUDE_DESC_QUEUE ,
C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_S_AXIS_UPDPTR_TDATA_WIDTH => C_S_AXIS_UPDPTR_TDATA_WIDTH ,
C_S_AXIS_UPDSTS_TDATA_WIDTH => C_S_AXIS_UPDSTS_TDATA_WIDTH ,
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL ,
C_MICRO_DMA => C_MICRO_DMA,
C_FAMILY => C_FAMILY
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- SG MM2S Descriptor Fetch AXI Stream In
m_axis_mm2s_ftch_tdata => m_axis_mm2s_ftch_tdata ,
m_axis_mm2s_ftch_tvalid => m_axis_mm2s_ftch_tvalid ,
m_axis_mm2s_ftch_tready => m_axis_mm2s_ftch_tready ,
m_axis_mm2s_ftch_tlast => m_axis_mm2s_ftch_tlast ,
m_axis_mm2s_ftch_tdata_new => m_axis_mm2s_ftch_tdata_new ,
m_axis_mm2s_ftch_tdata_mcdma_new => m_axis_mm2s_ftch_tdata_mcdma_new ,
m_axis_mm2s_ftch_tvalid_new => m_axis_mm2s_ftch_tvalid_new ,
m_axis_ftch1_desc_available => m_axis_ftch1_desc_available ,
-- SG MM2S Descriptor Update AXI Stream Out
s_axis_mm2s_updtptr_tdata => s_axis_mm2s_updtptr_tdata ,
s_axis_mm2s_updtptr_tvalid => s_axis_mm2s_updtptr_tvalid ,
s_axis_mm2s_updtptr_tready => s_axis_mm2s_updtptr_tready ,
s_axis_mm2s_updtptr_tlast => s_axis_mm2s_updtptr_tlast ,
s_axis_mm2s_updtsts_tdata => s_axis_mm2s_updtsts_tdata ,
s_axis_mm2s_updtsts_tvalid => s_axis_mm2s_updtsts_tvalid ,
s_axis_mm2s_updtsts_tready => s_axis_mm2s_updtsts_tready ,
s_axis_mm2s_updtsts_tlast => s_axis_mm2s_updtsts_tlast ,
-- MM2S Descriptor Fetch Request (from mm2s_sm)
desc_available => desc_available ,
desc_fetch_req => desc_fetch_req ,
desc_fetch_done => desc_fetch_done ,
updt_pending => updt_pending ,
packet_in_progress => packet_in_progress ,
-- MM2S Descriptor Update Request
desc_update_done => desc_update_done ,
mm2s_ftch_stale_desc => mm2s_ftch_stale_desc ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
mm2s_done => mm2s_done ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag ,
mm2s_halt => mm2s_halt , -- CR566306
-- Control Stream Output
cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
-- MM2S Descriptor Field Output
mm2s_new_curdesc => mm2s_new_curdesc ,
mm2s_new_curdesc_wren => mm2s_new_curdesc_wren ,
mm2s_desc_baddress => mm2s_desc_baddress ,
mm2s_desc_blength => mm2s_desc_blength ,
mm2s_desc_blength_v => mm2s_desc_blength_v ,
mm2s_desc_blength_s => mm2s_desc_blength_s ,
mm2s_desc_info => mm2s_desc_info ,
mm2s_desc_eof => mm2s_desc_eof ,
mm2s_desc_sof => mm2s_desc_sof ,
mm2s_desc_app0 => mm2s_desc_app0 ,
mm2s_desc_app1 => mm2s_desc_app1 ,
mm2s_desc_app2 => mm2s_desc_app2 ,
mm2s_desc_app3 => mm2s_desc_app3 ,
mm2s_desc_app4 => mm2s_desc_app4
);
cntrlstrm_fifo_full <= '0';
end generate GEN_SCATTER_GATHER_MODE;
-- Generate DMA Controller for Simple DMA Mode
GEN_SIMPLE_DMA_MODE : if C_INCLUDE_SG = 0 generate
begin
-- Scatter Gather signals not used in Simple DMA Mode
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others => '0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others => '0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
desc_available <= '0';
desc_fetch_done <= '0';
packet_in_progress <= '0';
desc_update_done <= '0';
cntrlstrm_fifo_wren <= '0';
cntrlstrm_fifo_din <= (others => '0');
mm2s_new_curdesc <= (others => '0');
mm2s_new_curdesc_wren <= '0';
mm2s_desc_baddress <= (others => '0');
mm2s_desc_blength <= (others => '0');
mm2s_desc_blength_v <= (others => '0');
mm2s_desc_blength_s <= (others => '0');
mm2s_desc_eof <= '0';
mm2s_desc_sof <= '0';
mm2s_desc_cmplt <= '0';
mm2s_desc_app0 <= (others => '0');
mm2s_desc_app1 <= (others => '0');
mm2s_desc_app2 <= (others => '0');
mm2s_desc_app3 <= (others => '0');
mm2s_desc_app4 <= (others => '0');
desc_fetch_req <= '0';
-- Simple DMA State Machine
I_MM2S_SMPL_SM : entity axi_dma_v7_1.axi_dma_smple_sm
generic map(
C_M_AXI_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH ,
C_SG_LENGTH_WIDTH => C_SG_LENGTH_WIDTH,
C_MICRO_DMA => C_MICRO_DMA
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel 1 Control and Status
run_stop => mm2s_run_stop ,
keyhole => mm2s_keyhole ,
stop => mm2s_stop_i ,
cmnd_idle => mm2s_cmnd_idle ,
sts_idle => mm2s_sts_idle ,
-- DataMover Status
sts_received => mm2s_sts_received ,
sts_received_clr => mm2s_sts_received_clr ,
-- DataMover Command
cmnd_wr => mm2s_cmnd_wr_1 ,
cmnd_data => mm2s_cmnd_data ,
cmnd_pending => mm2s_cmnd_pending ,
-- Trasnfer Qualifiers
xfer_length_wren => mm2s_length_wren ,
xfer_address => mm2s_sa ,
xfer_length => mm2s_length
);
-- Pass Done/Error Status out to DMASR
mm2s_interr_set <= mm2s_interr;
mm2s_slverr_set <= mm2s_slverr;
mm2s_decerr_set <= mm2s_decerr;
-- S2MM Simple DMA Transfer Done - used to assert IOC bit in DMASR.
-- Receive clear when not shutting down
mm2s_smple_done <= mm2s_sts_received_clr when mm2s_stop_i = '0'
-- Else halt set prior to halted being set
else mm2s_halted_set_i when mm2s_halted = '0'
else '0';
end generate GEN_SIMPLE_DMA_MODE;
-------------------------------------------------------------------------------
-- MM2S Primary DataMover command status interface
-------------------------------------------------------------------------------
I_MM2S_CMDSTS : entity axi_dma_v7_1.axi_dma_mm2s_cmdsts_if
generic map(
C_M_AXI_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH,
C_ENABLE_MULTI_CHANNEL => C_ENABLE_MULTI_CHANNEL,
C_ENABLE_QUEUE => C_SG_INCLUDE_DESC_QUEUE
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Fetch command write interface from mm2s sm
mm2s_cmnd_wr => mm2s_cmnd_wr_1 ,
mm2s_cmnd_data => mm2s_cmnd_data ,
mm2s_cmnd_pending => mm2s_cmnd_pending ,
mm2s_sts_received_clr => mm2s_sts_received_clr ,
mm2s_sts_received => mm2s_sts_received ,
mm2s_tailpntr_enble => mm2s_tailpntr_enble ,
mm2s_desc_cmplt => mm2s_desc_cmplt ,
-- User Command Interface Ports (AXI Stream)
s_axis_mm2s_cmd_tvalid => s_axis_mm2s_cmd_tvalid ,
s_axis_mm2s_cmd_tready => s_axis_mm2s_cmd_tready ,
s_axis_mm2s_cmd_tdata => s_axis_mm2s_cmd_tdata ,
-- User Status Interface Ports (AXI Stream)
m_axis_mm2s_sts_tvalid => m_axis_mm2s_sts_tvalid ,
m_axis_mm2s_sts_tready => m_axis_mm2s_sts_tready ,
m_axis_mm2s_sts_tdata => m_axis_mm2s_sts_tdata ,
m_axis_mm2s_sts_tkeep => m_axis_mm2s_sts_tkeep ,
-- MM2S Primary DataMover Status
mm2s_err => mm2s_err ,
mm2s_done => mm2s_done ,
mm2s_error => dma_mm2s_error ,
mm2s_interr => mm2s_interr ,
mm2s_slverr => mm2s_slverr ,
mm2s_decerr => mm2s_decerr ,
mm2s_tag => mm2s_tag
);
---------------------------------------------------------------------------
-- Halt / Idle Status Manager
---------------------------------------------------------------------------
I_MM2S_STS_MNGR : entity axi_dma_v7_1.axi_dma_mm2s_sts_mngr
generic map(
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC
)
port map(
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- dma control and sg engine status signals
mm2s_run_stop => mm2s_run_stop ,
mm2s_ftch_idle => mm2s_ftch_idle ,
mm2s_updt_idle => mm2s_updt_idle ,
mm2s_cmnd_idle => mm2s_cmnd_idle ,
mm2s_sts_idle => mm2s_sts_idle ,
-- stop and halt control/status
mm2s_stop => mm2s_stop_i ,
mm2s_halt_cmplt => mm2s_halt_cmplt ,
-- system state and control
mm2s_all_idle => mm2s_all_idle ,
mm2s_halted_clr => mm2s_halted_clr ,
mm2s_halted_set => mm2s_halted_set_i ,
mm2s_idle_set => mm2s_idle_set ,
mm2s_idle_clr => mm2s_idle_clr
);
-- MM2S Control Stream Included
GEN_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 1 and C_INCLUDE_SG = 1 generate
begin
-- Register soft reset to create rising edge pulse to use for shut down.
-- soft_reset from DMACR does not clear until after all reset processes
-- are done. This causes stop to assert too long causing issue with
-- status stream skid buffer.
REG_SFT_RST : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
else
soft_reset_d1 <= soft_reset;
soft_reset_d2 <= soft_reset_d1;
end if;
end if;
end process REG_SFT_RST;
-- Rising edge soft reset pulse
soft_reset_re <= soft_reset_d1 and not soft_reset_d2;
-- Control Stream module stop requires rising edge of soft reset to
-- shut down due to DMACR.SoftReset does not deassert on internal hard reset
-- It clears after therefore do not want to issue another stop to cntrl strm
-- skid buffer.
cntrl_strm_stop <= mm2s_error_i -- Error
or soft_reset_re; -- Soft Reset issued
-- Control stream interface
-- I_MM2S_CNTRL_STREAM : entity axi_dma_v7_1.axi_dma_mm2s_cntrl_strm
-- generic map(
-- C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
-- C_PRMY_CMDFIFO_DEPTH => C_PRMY_CMDFIFO_DEPTH ,
-- C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH ,
-- C_FAMILY => C_FAMILY
-- )
-- port map(
-- -- Secondary clock / reset
-- m_axi_sg_aclk => m_axi_sg_aclk ,
-- m_axi_sg_aresetn => m_axi_sg_aresetn ,
--
-- -- Primary clock / reset
-- axi_prmry_aclk => axi_prmry_aclk ,
-- p_reset_n => p_reset_n ,
--
-- -- MM2S Error
-- mm2s_stop => cntrl_strm_stop ,
--
-- -- Control Stream input
---- cntrlstrm_fifo_wren => cntrlstrm_fifo_wren ,
-- cntrlstrm_fifo_full => cntrlstrm_fifo_full ,
-- cntrlstrm_fifo_din => cntrlstrm_fifo_din ,
--
-- -- Memory Map to Stream Control Stream Interface
-- m_axis_mm2s_cntrl_tdata => m_axis_mm2s_cntrl_tdata ,
-- m_axis_mm2s_cntrl_tkeep => m_axis_mm2s_cntrl_tkeep ,
-- m_axis_mm2s_cntrl_tvalid => m_axis_mm2s_cntrl_tvalid ,
-- m_axis_mm2s_cntrl_tready => m_axis_mm2s_cntrl_tready ,
-- m_axis_mm2s_cntrl_tlast => m_axis_mm2s_cntrl_tlast
--
-- );
end generate GEN_CNTRL_STREAM;
-- MM2S Control Stream Excluded
GEN_NO_CNTRL_STREAM : if C_SG_INCLUDE_STSCNTRL_STRM = 0 or C_INCLUDE_SG = 0 generate
begin
soft_reset_d1 <= '0';
soft_reset_d2 <= '0';
soft_reset_re <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_CNTRL_STREAM;
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
end generate GEN_MM2S_DMA_CONTROL;
-------------------------------------------------------------------------------
-- Exclude MM2S State Machine and support logic
-------------------------------------------------------------------------------
GEN_NO_MM2S_DMA_CONTROL : if C_INCLUDE_MM2S = 0 generate
begin
m_axis_mm2s_ftch_tready <= '0';
s_axis_mm2s_updtptr_tdata <= (others =>'0');
s_axis_mm2s_updtptr_tvalid <= '0';
s_axis_mm2s_updtptr_tlast <= '0';
s_axis_mm2s_updtsts_tdata <= (others =>'0');
s_axis_mm2s_updtsts_tvalid <= '0';
s_axis_mm2s_updtsts_tlast <= '0';
mm2s_new_curdesc <= (others =>'0');
mm2s_new_curdesc_wren <= '0';
s_axis_mm2s_cmd_tvalid <= '0';
s_axis_mm2s_cmd_tdata <= (others =>'0');
m_axis_mm2s_sts_tready <= '0';
mm2s_halted_clr <= '0';
mm2s_halted_set <= '0';
mm2s_idle_set <= '0';
mm2s_idle_clr <= '0';
m_axis_mm2s_cntrl_tdata <= (others => '0');
m_axis_mm2s_cntrl_tkeep <= (others => '0');
m_axis_mm2s_cntrl_tvalid <= '0';
m_axis_mm2s_cntrl_tlast <= '0';
mm2s_stop <= '0';
mm2s_desc_flush <= '0';
mm2s_all_idle <= '1';
mm2s_error <= '0'; -- CR#570587
mm2s_interr_set <= '0';
mm2s_slverr_set <= '0';
mm2s_decerr_set <= '0';
mm2s_smple_done <= '0';
cntrl_strm_stop <= '0';
end generate GEN_NO_MM2S_DMA_CONTROL;
TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 1) generate
process (m_axi_sg_aclk)
begin
if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
desc_fetch_done_del <= '0';
else --if (m_axi_sg_aclk'event and m_axi_sg_aclk = '1') then
desc_fetch_done_del <= desc_fetch_done;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty <= '0';
else
fifo_empty <= info_fifo_empty;
end if;
end if;
end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (m_axi_sg_aresetn = '0') then
fifo_empty_first <= '0';
fifo_empty_first1 <= '0';
else
if (fifo_empty_first = '0' and (info_fifo_empty = '0' and fifo_empty = '1')) then
fifo_empty_first <= '1';
end if;
fifo_empty_first1 <= fifo_empty_first;
end if;
end if;
end process;
first_read_pulse <= fifo_empty_first and (not fifo_empty_first1);
fifo_read <= first_read_pulse or rd_en_hold;
mm2s_desc_info_int <= mm2s_desc_info (19 downto 16) & mm2s_desc_info (12 downto 8) & mm2s_desc_info (4 downto 0);
-- mm2s_strm_tlast_int <= mm2s_strm_tlast and (not info_fifo_empty);
-- process (m_axis_mm2s_aclk)
-- begin
-- if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
-- if (p_reset_n = '0') then
-- rd_en_hold <= '0';
-- rd_en_hold_int <= '0';
-- else
-- if (rd_en_hold = '1') then
-- rd_en_hold <= '0';
-- elsif (info_fifo_empty = '0' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
-- rd_en_hold <= '1';
-- rd_en_hold_int <= '0';
-- else
-- rd_en_hold <= rd_en_hold;
-- rd_en_hold_int <= rd_en_hold_int;
-- end if;
-- end if;
-- end if;
-- end process;
process (m_axis_mm2s_aclk)
begin
if (m_axis_mm2s_aclk'event and m_axis_mm2s_aclk = '1') then
if (p_reset_n = '0') then
rd_en_hold <= '0';
rd_en_hold_int <= '0';
else
if (info_fifo_empty = '1' and mm2s_strm_tlast = '1' and mm2s_strm_tready = '1') then
rd_en_hold <= '1';
rd_en_hold_int <= '0';
elsif (info_fifo_empty = '0') then
rd_en_hold <= mm2s_strm_tlast and mm2s_strm_tready;
rd_en_hold_int <= rd_en_hold;
else
rd_en_hold <= rd_en_hold;
rd_en_hold_int <= rd_en_hold_int;
end if;
end if;
end if;
end process;
fifo_rst <= not (m_axi_sg_aresetn);
-- Following FIFO is used to store the Tuser, Tid and xCache info
I_INFO_FIFO : entity axi_dma_v7_1.axi_dma_afifo_autord
generic map(
C_DWIDTH => 14,
C_DEPTH => 31 ,
C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => 0,
C_USE_AUTORD => 1,
C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => fifo_rst ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => desc_fetch_done_del ,
AFIFO_Din => mm2s_desc_info_int ,
AFIFO_Rd_clk => m_axis_mm2s_aclk ,
AFIFO_Rd_en => rd_en_hold_int, --fifo_read, --mm2s_strm_tlast_int ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => open ,
AFIFO_Dout => mm2s_axis_info ,
AFIFO_Full => info_fifo_full ,
AFIFO_Empty => info_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
end generate TDEST_FIFO;
NO_TDEST_FIFO : if (C_ENABLE_MULTI_CHANNEL = 0) generate
mm2s_axis_info <= (others => '0');
end generate NO_TDEST_FIFO;
end implementation;
|
architecture rtl of StateSelectionGate is
signal CfgValue : std_logic_vector(StateWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => StateWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
Match_o <= '1' when State_i = CfgValue else '0';
end rtl; -- of StateSelectionGate
|
architecture rtl of StateSelectionGate is
signal CfgValue : std_logic_vector(StateWidth-1 downto 0);
begin -- rtl
Cfg : ConfigRegister
generic map (
Width => StateWidth)
port map (
Reset_n_i => Reset_n_i,
Output_o => CfgValue,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o);
Match_o <= '1' when State_i = CfgValue else '0';
end rtl; -- of StateSelectionGate
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1431.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01431ent IS
END c08s07b00x00p02n01i01431ent;
ARCHITECTURE c08s07b00x00p02n01i01431arch OF c08s07b00x00p02n01i01431ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Misspelled reserved word 'if'
fi (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01431 - misspelled reserved word 'if'"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01431arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1431.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01431ent IS
END c08s07b00x00p02n01i01431ent;
ARCHITECTURE c08s07b00x00p02n01i01431arch OF c08s07b00x00p02n01i01431ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Misspelled reserved word 'if'
fi (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01431 - misspelled reserved word 'if'"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01431arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1431.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s07b00x00p02n01i01431ent IS
END c08s07b00x00p02n01i01431ent;
ARCHITECTURE c08s07b00x00p02n01i01431arch OF c08s07b00x00p02n01i01431ent IS
begin
TEST_PROCESS: process
variable I : INTEGER := 47;
begin
-- Misspelled reserved word 'if'
fi (I = 47) then
NULL;
end if;
assert FALSE
report "***FAILED TEST: c08s07b00x00p02n01i01431 - misspelled reserved word 'if'"
severity ERROR;
wait;
end process TEST_PROCESS;
END c08s07b00x00p02n01i01431arch;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: K.31
-- \ \ Application: netgen
-- / / Filename: Subsys_Adder_synthesis.vhd
-- /___/ /\ Timestamp: Sun Apr 12 03:25:34 2009
-- \ \ / \
-- \___\/\___\
--
-- Command : -intstyle ise -ar Structure -tm Subsys_Adder -w -dir netgen/synthesis -ofmt vhdl -sim Subsys_Adder.ngc Subsys_Adder_synthesis.vhd
-- Device : xc3s500e-4-fg320
-- Input file : Subsys_Adder.ngc
-- Output file : C:\Users\Ben\Desktop\FPGAprojects\Subsystems\Subsys_Adder\netgen\synthesis\Subsys_Adder_synthesis.vhd
-- # of Entities : 1
-- Design Name : Subsys_Adder
-- Xilinx : C:\Xilinx\10.1\ISE
--
-- Purpose:
-- This VHDL netlist is a verification model and uses simulation
-- primitives which may not represent the true implementation of the
-- device, however the netlist is functionally correct and should not
-- be modified. This file cannot be synthesized and should only be used
-- with supported simulation tools.
--
-- Reference:
-- Development System Reference Guide, Chapter 23
-- Synthesis and Simulation Design Guide, Chapter 6
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
use UNISIM.VPKG.ALL;
entity Subsys_Adder is
port (
CLK1 : in STD_LOGIC := 'X';
CLK2 : in STD_LOGIC := 'X';
ano : out STD_LOGIC_VECTOR ( 3 downto 0 );
seg : out STD_LOGIC_VECTOR ( 6 downto 0 );
N1 : in STD_LOGIC_VECTOR ( 3 downto 0 );
N2 : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end Subsys_Adder;
architecture Structure of Subsys_Adder is
signal CLK1_IBUF_1 : STD_LOGIC;
signal CLK2_IBUF_3 : STD_LOGIC;
signal G1_G1_S3 : STD_LOGIC;
signal G1_G2_S3 : STD_LOGIC;
signal G1_G3_S3 : STD_LOGIC;
signal G2_G1_S3 : STD_LOGIC;
signal G2_G2_S3 : STD_LOGIC;
signal G2_G3_S3 : STD_LOGIC;
signal G6_G1_S3 : STD_LOGIC;
signal G6_G2_G4_Q : STD_LOGIC;
signal G6_G2_S3 : STD_LOGIC;
signal G6_G3_G4_Q : STD_LOGIC;
signal G6_G3_G4_Q1_14 : STD_LOGIC;
signal G6_G3_S3 : STD_LOGIC;
signal G6_G4_G4_Q : STD_LOGIC;
signal G6_G4_G4_Q1_17 : STD_LOGIC;
signal G6_G4_S3 : STD_LOGIC;
signal G7_Mrom_seg : STD_LOGIC;
signal G7_Mrom_seg1 : STD_LOGIC;
signal G7_Mrom_seg2 : STD_LOGIC;
signal G7_Mrom_seg3 : STD_LOGIC;
signal G7_Mrom_seg4 : STD_LOGIC;
signal G7_Mrom_seg5 : STD_LOGIC;
signal G7_Mrom_seg6 : STD_LOGIC;
signal N0 : STD_LOGIC;
signal N11 : STD_LOGIC;
signal N1_0_IBUF_31 : STD_LOGIC;
signal N1_1_IBUF_32 : STD_LOGIC;
signal N1_2_IBUF_33 : STD_LOGIC;
signal N2_0_IBUF_37 : STD_LOGIC;
signal N2_1_IBUF_38 : STD_LOGIC;
signal N2_2_IBUF_39 : STD_LOGIC;
signal S1 : STD_LOGIC;
signal S14 : STD_LOGIC;
signal S15 : STD_LOGIC;
signal S16 : STD_LOGIC;
signal S17 : STD_LOGIC;
signal S2 : STD_LOGIC;
signal S3 : STD_LOGIC;
signal S4 : STD_LOGIC;
signal S5 : STD_LOGIC;
signal S6 : STD_LOGIC;
signal S8 : STD_LOGIC;
begin
XST_GND : GND
port map (
G => N0
);
XST_VCC : VCC
port map (
P => N11
);
G6_G4_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S17,
I2 => G6_G4_S3,
O => S17
);
G6_G3_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S16,
I2 => G6_G3_S3,
O => S16
);
G6_G2_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S15,
I2 => G6_G2_S3,
O => S15
);
G6_G1_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S14,
I2 => G6_G1_S3,
O => S14
);
G2_G3_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S6,
I2 => G2_G3_S3,
O => S6
);
G2_G3_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N2_2_IBUF_39,
I2 => G2_G3_S3,
O => G2_G3_S3
);
G2_G2_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S5,
I2 => G2_G2_S3,
O => S5
);
G2_G2_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N2_1_IBUF_38,
I2 => G2_G2_S3,
O => G2_G2_S3
);
G2_G1_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S4,
I2 => G2_G1_S3,
O => S4
);
G2_G1_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N2_0_IBUF_37,
I2 => G2_G1_S3,
O => G2_G1_S3
);
G1_G3_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S3,
I2 => G1_G3_S3,
O => S3
);
G1_G3_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N1_2_IBUF_33,
I2 => G1_G3_S3,
O => G1_G3_S3
);
G1_G2_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S2,
I2 => G1_G2_S3,
O => S2
);
G1_G2_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N1_1_IBUF_32,
I2 => G1_G2_S3,
O => G1_G2_S3
);
G1_G1_G7_Q1 : LUT3
generic map(
INIT => X"4E"
)
port map (
I0 => CLK1_IBUF_1,
I1 => S1,
I2 => G1_G1_S3,
O => S1
);
G1_G1_G4_Q1 : LUT3
generic map(
INIT => X"B1"
)
port map (
I0 => CLK1_IBUF_1,
I1 => N1_0_IBUF_31,
I2 => G1_G1_S3,
O => G1_G1_S3
);
G4_G5_Q1 : LUT4
generic map(
INIT => X"EA80"
)
port map (
I0 => S2,
I1 => S1,
I2 => S4,
I3 => S5,
O => S8
);
G7_Mrom_seg41 : LUT4
generic map(
INIT => X"454C"
)
port map (
I0 => S17,
I1 => S14,
I2 => S15,
I3 => S16,
O => G7_Mrom_seg4
);
G6_G1_G4_Q1 : LUT4
generic map(
INIT => X"EB41"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S1,
I2 => S4,
I3 => G6_G1_S3,
O => G6_G1_S3
);
G7_Mrom_seg21 : LUT4
generic map(
INIT => X"80C2"
)
port map (
I0 => S15,
I1 => S17,
I2 => S16,
I3 => S14,
O => G7_Mrom_seg2
);
G7_Mrom_seg61 : LUT4
generic map(
INIT => X"0941"
)
port map (
I0 => S15,
I1 => S16,
I2 => S17,
I3 => S14,
O => G7_Mrom_seg6
);
G7_Mrom_seg51 : LUT4
generic map(
INIT => X"6032"
)
port map (
I0 => S15,
I1 => S17,
I2 => S14,
I3 => S16,
O => G7_Mrom_seg5
);
G7_Mrom_seg111 : LUT4
generic map(
INIT => X"B860"
)
port map (
I0 => S17,
I1 => S14,
I2 => S16,
I3 => S15,
O => G7_Mrom_seg1
);
G7_Mrom_seg31 : LUT4
generic map(
INIT => X"9086"
)
port map (
I0 => S14,
I1 => S16,
I2 => S15,
I3 => S17,
O => G7_Mrom_seg3
);
G7_Mrom_seg11 : LUT4
generic map(
INIT => X"2812"
)
port map (
I0 => S14,
I1 => S15,
I2 => S16,
I3 => S17,
O => G7_Mrom_seg
);
CLK1_IBUF : IBUF
port map (
I => CLK1,
O => CLK1_IBUF_1
);
CLK2_IBUF : IBUF
port map (
I => CLK2,
O => CLK2_IBUF_3
);
N1_2_IBUF : IBUF
port map (
I => N1(2),
O => N1_2_IBUF_33
);
N1_1_IBUF : IBUF
port map (
I => N1(1),
O => N1_1_IBUF_32
);
N1_0_IBUF : IBUF
port map (
I => N1(0),
O => N1_0_IBUF_31
);
N2_2_IBUF : IBUF
port map (
I => N2(2),
O => N2_2_IBUF_39
);
N2_1_IBUF : IBUF
port map (
I => N2(1),
O => N2_1_IBUF_38
);
N2_0_IBUF : IBUF
port map (
I => N2(0),
O => N2_0_IBUF_37
);
ano_3_OBUF : OBUF
port map (
I => N11,
O => ano(3)
);
ano_2_OBUF : OBUF
port map (
I => N11,
O => ano(2)
);
ano_1_OBUF : OBUF
port map (
I => N11,
O => ano(1)
);
ano_0_OBUF : OBUF
port map (
I => N0,
O => ano(0)
);
seg_6_OBUF : OBUF
port map (
I => G7_Mrom_seg6,
O => seg(6)
);
seg_5_OBUF : OBUF
port map (
I => G7_Mrom_seg5,
O => seg(5)
);
seg_4_OBUF : OBUF
port map (
I => G7_Mrom_seg4,
O => seg(4)
);
seg_3_OBUF : OBUF
port map (
I => G7_Mrom_seg3,
O => seg(3)
);
seg_2_OBUF : OBUF
port map (
I => G7_Mrom_seg2,
O => seg(2)
);
seg_1_OBUF : OBUF
port map (
I => G7_Mrom_seg1,
O => seg(1)
);
seg_0_OBUF : OBUF
port map (
I => G7_Mrom_seg,
O => seg(0)
);
G6_G4_G4_Q1 : LUT4
generic map(
INIT => X"888D"
)
port map (
I0 => CLK2_IBUF_3,
I1 => G6_G4_S3,
I2 => S6,
I3 => S3,
O => G6_G4_G4_Q
);
G6_G4_G4_Q2 : LUT4
generic map(
INIT => X"B1F5"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S3,
I2 => G6_G4_S3,
I3 => S6,
O => G6_G4_G4_Q1_17
);
G6_G4_G4_Q_f5 : MUXF5
port map (
I0 => G6_G4_G4_Q1_17,
I1 => G6_G4_G4_Q,
S => S8,
O => G6_G4_S3
);
G6_G3_G4_Q1 : LUT4
generic map(
INIT => X"BE14"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S6,
I2 => S3,
I3 => G6_G3_S3,
O => G6_G3_G4_Q
);
G6_G3_G4_Q2 : LUT4
generic map(
INIT => X"EB41"
)
port map (
I0 => CLK2_IBUF_3,
I1 => S6,
I2 => S3,
I3 => G6_G3_S3,
O => G6_G3_G4_Q1_14
);
G6_G3_G4_Q_f5 : MUXF5
port map (
I0 => G6_G3_G4_Q1_14,
I1 => G6_G3_G4_Q,
S => S8,
O => G6_G3_S3
);
G6_G2_G4_Q1 : LUT4
generic map(
INIT => X"69A5"
)
port map (
I0 => S2,
I1 => S4,
I2 => S5,
I3 => S1,
O => G6_G2_G4_Q
);
G6_G2_G4_Q_f5 : MUXF5
port map (
I0 => G6_G2_G4_Q,
I1 => G6_G2_S3,
S => CLK2_IBUF_3,
O => G6_G2_S3
);
end Structure;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1078.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01078ent IS
END c06s05b00x00p01n02i01078ent;
ARCHITECTURE c06s05b00x00p01n02i01078arch OF c06s05b00x00p01n02i01078ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL resultt : boolean;
procedure subprogram ( VARIABLE v : IN bit_vector_4; signal result : out boolean ) is
begin
if ( v = B"1010" ) then
result <= true;
else
result <= false;
end if;
end ;
BEGIN
TESTING: PROCESS
VARIABLE v_slice : bit_vector_8 := B"1010_1100";
BEGIN
subprogram ( v_slice ( 0 to 3 ), resultt );
wait for 1 ns;
assert NOT( resultt = true )
report "***PASSED TEST: c06s05b00x00p01n02i01078"
severity NOTE;
assert ( resultt = true )
report "***FAILED TEST: c06s05b00x00p01n02i01078 - A slice of a variable should still be a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01078arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1078.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01078ent IS
END c06s05b00x00p01n02i01078ent;
ARCHITECTURE c06s05b00x00p01n02i01078arch OF c06s05b00x00p01n02i01078ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL resultt : boolean;
procedure subprogram ( VARIABLE v : IN bit_vector_4; signal result : out boolean ) is
begin
if ( v = B"1010" ) then
result <= true;
else
result <= false;
end if;
end ;
BEGIN
TESTING: PROCESS
VARIABLE v_slice : bit_vector_8 := B"1010_1100";
BEGIN
subprogram ( v_slice ( 0 to 3 ), resultt );
wait for 1 ns;
assert NOT( resultt = true )
report "***PASSED TEST: c06s05b00x00p01n02i01078"
severity NOTE;
assert ( resultt = true )
report "***FAILED TEST: c06s05b00x00p01n02i01078 - A slice of a variable should still be a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01078arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1078.vhd,v 1.2 2001-10-26 16:29:38 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s05b00x00p01n02i01078ent IS
END c06s05b00x00p01n02i01078ent;
ARCHITECTURE c06s05b00x00p01n02i01078arch OF c06s05b00x00p01n02i01078ent IS
SUBTYPE bit_vector_4 is bit_vector ( 0 to 3 );
SUBTYPE bit_vector_8 is bit_vector ( 0 to 7 );
SIGNAL resultt : boolean;
procedure subprogram ( VARIABLE v : IN bit_vector_4; signal result : out boolean ) is
begin
if ( v = B"1010" ) then
result <= true;
else
result <= false;
end if;
end ;
BEGIN
TESTING: PROCESS
VARIABLE v_slice : bit_vector_8 := B"1010_1100";
BEGIN
subprogram ( v_slice ( 0 to 3 ), resultt );
wait for 1 ns;
assert NOT( resultt = true )
report "***PASSED TEST: c06s05b00x00p01n02i01078"
severity NOTE;
assert ( resultt = true )
report "***FAILED TEST: c06s05b00x00p01n02i01078 - A slice of a variable should still be a variable."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s05b00x00p01n02i01078arch;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.tech_map.all;
entity cachemem is
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end;
architecture rtl of cachemem is
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant ITWIDTH : natural := ITAG_BITS;
constant DTWIDTH : natural := DTAG_BITS;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal itdatain : std_logic_vector(ITAG_BITS -1 downto 0);
signal itdataout : std_logic_vector(ITAG_BITS -1 downto 0);
signal iddatain : std_logic_vector(32 -1 downto 0);
signal iddataout : std_logic_vector(32 -1 downto 0);
signal itenable : std_logic;
signal idenable : std_logic;
signal itwrite : std_logic;
signal idwrite : std_logic;
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal dtdatain : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout : std_logic_vector(DTAG_BITS -1 downto 0);
signal dddatain : std_logic_vector(32 -1 downto 0);
signal dddataout : std_logic_vector(32 -1 downto 0);
signal dtenable : std_logic;
signal ddenable : std_logic;
signal dtwrite : std_logic;
signal ddwrite : std_logic;
signal vcc, gnd : std_logic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.idramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.idramin.address;
itinsel : process(crami)
begin
itdatain(ITAG_BITS - 1 downto 0) <= crami.icramin.itramin.tag &
crami.icramin.itramin.valid;
iddatain(31 downto 0) <= crami.icramin.idramin.data;
dtdatain(DTAG_BITS - 1 downto 0) <= crami.dcramin.dtramin.tag &
crami.dcramin.dtramin.valid;
dddatain(32 - 1 downto 0) <= crami.dcramin.ddramin.data;
end process;
itwrite <= crami.icramin.itramin.write;
idwrite <= crami.icramin.idramin.write;
itenable <= crami.icramin.itramin.enable;
idenable <= crami.icramin.idramin.enable;
dtaddr <= crami.dcramin.ddramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
ddaddr <= crami.dcramin.ddramin.address;
dtwrite <= crami.dcramin.dtramin.write;
ddwrite <= crami.dcramin.ddramin.write;
dtenable <= crami.dcramin.dtramin.enable;
ddenable <= crami.dcramin.ddramin.enable;
itags0 : syncram
generic map ( dbits => ITAG_BITS, abits => IOFFSET_BITS)
port map ( itaddr, clk, itdatain, itdataout, itenable, itwrite);
dtags0 : syncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite);
idata0 : syncram
generic map ( dbits => 32, abits => IOFFSET_BITS+ILINE_BITS)
port map ( idaddr, clk, iddatain, iddataout, idenable, idwrite);
ddata0 : syncram
generic map ( dbits => 32, abits => DOFFSET_BITS+DLINE_BITS)
port map ( ddaddr, clk, dddatain, dddataout, ddenable, ddwrite);
cramo.icramout.itramout.valid <= itdataout(ILINE_SIZE -1 downto 0);
cramo.icramout.itramout.tag <= itdataout(ITAG_BITS-1 downto ILINE_SIZE);
cramo.icramout.idramout.data <= iddataout(31 downto 0);
cramo.dcramout.dtramout.valid <= dtdataout(DLINE_SIZE -1 downto 0);
cramo.dcramout.dtramout.tag <= dtdataout(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.ddramout.data <= dddataout(31 downto 0);
end ;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: cachemem
-- File: cachemem.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: Contains ram cells for both instruction and data caches
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.target.all;
use work.config.all;
use work.iface.all;
use work.macro.all;
use work.tech_map.all;
entity cachemem is
port (
clk : in clk_type;
crami : in cram_in_type;
cramo : out cram_out_type
);
end;
architecture rtl of cachemem is
constant ITDEPTH : natural := 2**IOFFSET_BITS;
constant DTDEPTH : natural := 2**DOFFSET_BITS;
constant ITWIDTH : natural := ITAG_BITS;
constant DTWIDTH : natural := DTAG_BITS;
signal itaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
signal idaddr : std_logic_vector(IOFFSET_BITS + ILINE_BITS -1 downto 0);
signal itdatain : std_logic_vector(ITAG_BITS -1 downto 0);
signal itdataout : std_logic_vector(ITAG_BITS -1 downto 0);
signal iddatain : std_logic_vector(32 -1 downto 0);
signal iddataout : std_logic_vector(32 -1 downto 0);
signal itenable : std_logic;
signal idenable : std_logic;
signal itwrite : std_logic;
signal idwrite : std_logic;
signal dtaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
signal ddaddr : std_logic_vector(DOFFSET_BITS + DLINE_BITS -1 downto 0);
signal dtdatain : std_logic_vector(DTAG_BITS -1 downto 0);
signal dtdataout : std_logic_vector(DTAG_BITS -1 downto 0);
signal dddatain : std_logic_vector(32 -1 downto 0);
signal dddataout : std_logic_vector(32 -1 downto 0);
signal dtenable : std_logic;
signal ddenable : std_logic;
signal dtwrite : std_logic;
signal ddwrite : std_logic;
signal vcc, gnd : std_logic;
begin
vcc <= '1'; gnd <= '0';
itaddr <= crami.icramin.idramin.address(IOFFSET_BITS + ILINE_BITS -1 downto ILINE_BITS);
idaddr <= crami.icramin.idramin.address;
itinsel : process(crami)
begin
itdatain(ITAG_BITS - 1 downto 0) <= crami.icramin.itramin.tag &
crami.icramin.itramin.valid;
iddatain(31 downto 0) <= crami.icramin.idramin.data;
dtdatain(DTAG_BITS - 1 downto 0) <= crami.dcramin.dtramin.tag &
crami.dcramin.dtramin.valid;
dddatain(32 - 1 downto 0) <= crami.dcramin.ddramin.data;
end process;
itwrite <= crami.icramin.itramin.write;
idwrite <= crami.icramin.idramin.write;
itenable <= crami.icramin.itramin.enable;
idenable <= crami.icramin.idramin.enable;
dtaddr <= crami.dcramin.ddramin.address(DOFFSET_BITS + DLINE_BITS -1 downto DLINE_BITS);
ddaddr <= crami.dcramin.ddramin.address;
dtwrite <= crami.dcramin.dtramin.write;
ddwrite <= crami.dcramin.ddramin.write;
dtenable <= crami.dcramin.dtramin.enable;
ddenable <= crami.dcramin.ddramin.enable;
itags0 : syncram
generic map ( dbits => ITAG_BITS, abits => IOFFSET_BITS)
port map ( itaddr, clk, itdatain, itdataout, itenable, itwrite);
dtags0 : syncram
generic map ( dbits => DTAG_BITS, abits => DOFFSET_BITS)
port map ( dtaddr, clk, dtdatain, dtdataout, dtenable, dtwrite);
idata0 : syncram
generic map ( dbits => 32, abits => IOFFSET_BITS+ILINE_BITS)
port map ( idaddr, clk, iddatain, iddataout, idenable, idwrite);
ddata0 : syncram
generic map ( dbits => 32, abits => DOFFSET_BITS+DLINE_BITS)
port map ( ddaddr, clk, dddatain, dddataout, ddenable, ddwrite);
cramo.icramout.itramout.valid <= itdataout(ILINE_SIZE -1 downto 0);
cramo.icramout.itramout.tag <= itdataout(ITAG_BITS-1 downto ILINE_SIZE);
cramo.icramout.idramout.data <= iddataout(31 downto 0);
cramo.dcramout.dtramout.valid <= dtdataout(DLINE_SIZE -1 downto 0);
cramo.dcramout.dtramout.tag <= dtdataout(DTAG_BITS-1 downto DLINE_SIZE);
cramo.dcramout.ddramout.data <= dddataout(31 downto 0);
end ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2457.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02457ent IS
END c07s03b02x02p03n02i02457ent;
ARCHITECTURE c07s03b02x02p03n02i02457arch OF c07s03b02x02p03n02i02457ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
variable V : CONSTRAINED_ARRAY ;
-- check in declaration of constrained array variable.
BEGIN
V := ( others => '$' );
-- check in variable assignment to constrained array object.
wait for 5 ns;
assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02457"
severity NOTE;
assert ( V(1)='$' and V(2)='$' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02457 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02457arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2457.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02457ent IS
END c07s03b02x02p03n02i02457ent;
ARCHITECTURE c07s03b02x02p03n02i02457arch OF c07s03b02x02p03n02i02457ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
variable V : CONSTRAINED_ARRAY ;
-- check in declaration of constrained array variable.
BEGIN
V := ( others => '$' );
-- check in variable assignment to constrained array object.
wait for 5 ns;
assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02457"
severity NOTE;
assert ( V(1)='$' and V(2)='$' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02457 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02457arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2457.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02457ent IS
END c07s03b02x02p03n02i02457ent;
ARCHITECTURE c07s03b02x02p03n02i02457arch OF c07s03b02x02p03n02i02457ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 3 );
variable V : CONSTRAINED_ARRAY ;
-- check in declaration of constrained array variable.
BEGIN
V := ( others => '$' );
-- check in variable assignment to constrained array object.
wait for 5 ns;
assert NOT( V(1)='$' and V(2)='$' and V(3)='$' )
report "***PASSED TEST: c07s03b02x02p03n02i02457"
severity NOTE;
assert ( V(1)='$' and V(2)='$' and V(3)='$' )
report "***FAILED TEST: c07s03b02x02p03n02i02457 - An array aggregate with an others choice may appear as a value expression in an assignment statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02457arch;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY proc_sys_reset_v5_0;
USE proc_sys_reset_v5_0.proc_sys_reset;
ENTITY design_1_rst_processing_system7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_processing_system7_0_100M_0;
ARCHITECTURE design_1_rst_processing_system7_0_100M_0_arch OF design_1_rst_processing_system7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_processing_system7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_processing_system7_0_100M_0_arch;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; MokhtariBehzad@Gmail.com
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Adder
Library IEEE; use IEEE.std_logic_1164.ALL, IEEE.numeric_std.all;
Library manoBasic; use manoBasic.defines.all, manoBasic.devices.all;
entity fulladderBasic is
port(
Ci: in std_logic:='0';
A: in std_logic;
B: in std_logic;
S: out std_logic;
Co: out std_logic
);
end fulladderBasic;
architecture Structure of fulladderBasic is
begin
S <= A xor B xor Ci;
Co <= (A and B) or ((A xor B) and Ci);
end architecture; |
-- This file is part of the Omega CPU Core
-- Copyright 2015 - 2016 Joseph Shetaye
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as
-- published by the Free Software Foundation, either version 3 of the
-- License, or (at your option) any later version.
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library IEEE;
use IEEE.std_logic_1164.all;
use work.Constants.all;
use IEEE.Numeric_std.all;
use std.textio.all;
use work.ghdl_env.all;
entity CPU_TB is
end CPU_TB;
architecture Behavioral of CPU_TB is
component MemoryController is
port (
CLK : in std_logic;
Address : in word;
ToWrite : in word;
FromRead : out word;
Instruction : in word;
Enable : in std_logic;
Reset : in std_logic;
Done : out std_logic);
end component MemoryController;
component PortController is
port (
CLK : in std_logic;
XMit : in Word;
Recv : out Word;
SerialIn : in std_logic;
SerialOut : out std_logic;
instruction : in Word;
CPUReady : in std_logic;
CPUSending: in std_logic;
PortReady: out std_logic;
PortSending: out std_logic;
Done: out std_logic);
end component PortController;
component Control is
port(
CLK : in std_logic;
MemControllerDone : in std_logic;
MemControllerFromRead : in Word;
MemControllerToWrite : out Word;
MemControllerADDR : out Word;
MemControllerEnable : out std_logic;
PortXmit : out Word;
PortRecv : in Word;
PortInstruction : out Word;
PortCPUReady : out std_logic;
PortCPUSending : out std_logic;
PortReady : in std_logic;
PortDone : in std_logic;
PortSending : out std_logic;
IRQ : in std_logic_vector(23 downto 0);
Instr : out Word;
RST : in std_logic);
end component Control;
signal MemControllerDone : std_logic := '0';
signal MemControllerFromRead : Word := (others => '0');
signal MemControllerToWrite : Word := (others => '0');
signal MemControllerADDR : Word := (others => '0');
signal MemControllerEnable : std_logic := '0';
signal Instr : Word := (others => '0');
signal MemoryPassthrough : std_logic := '0';
signal CLK : std_logic := '0';
signal RST : std_logic := '0';
--port
signal PortXmit_s : Word;
signal PortRecv_s : Word;
signal PortInstruction_s : Word;
signal PortCPUReady_s : std_logic;
signal PortCPUSending_s : std_logic;
signal PortReady_s : std_logic;
signal PortDone_s : std_logic;
signal PortSending_s : std_logic;
--mem
signal MemControllerDone_M : std_logic;
signal MemControllerFromRead_M : Word;
signal MemControllerToWrite_M : Word;
signal MemControllerADDR_M : Word;
signal MemControllerReset_M : std_logic := '0';
signal Instr_M : Word;
signal MemControllerEnable_M : std_logic;
signal MemControllerEnable_C : std_logic;
signal MemControllerDone_C : std_logic;
signal MemControllerFromRead_C : Word;
signal MemControllerToWrite_C : Word;
signal MemControllerADDR_C : Word;
signal Instr_C : Word;
begin
MemoryControllerControl : MemoryController port map (
Address => MemControllerADDR_M,
ToWrite => MemControllerToWrite_M,
FromRead => MemControllerFromRead_M,
Enable => MemControllerEnable_M,
Instruction => Instr_M,
Reset => MemControllerReset_M,
Done => MemControllerDone_M,
CLK => CLK);
PortControl : PortController port map (
CLK => CLK,
XMit => PortXMit_s,
Recv => PortRecv_s,
instruction => Instr_C,
CPUReady => PortCPUReady_s,
CPUSending => PortCPUSending_s,
SerialIn => '0',
PortReady => PortReady_s,
Done => PortDone_s,
PortSending => PortSending_s);
ControlTB : Control port map (
CLK => CLK,
MemControllerDone => MemControllerDone_C,
MemControllerFromRead => MemControllerFromRead_C,
MemControllerToWrite => MemControllerToWrite_C,
MemControllerADDR => MemControllerADDR_C,
MemControllerEnable => MemControllerEnable_C,
PortXmit => PortXmit_s,
PortRecv => PortRecv_s,
PortInstruction => PortInstruction_s,
PortCPUReady => PortCPUReady_s,
PortCPUSending => PortCPUSending_s,
PortReady => PortReady_s,
PortDone => PortDone_s,
PortSending => PortSending_s,
IRQ => (others => '0'),
RST => RST,
Instr => Instr_C);
file_io:
process is
file programInput : text is in getenv("PROGRAM");
variable in_line : line;
variable out_line : line;
variable in_vector : bit_vector(31 downto 0) := (others => '0');
variable outputI : integer := 0;
variable Counter : integer := 0;
variable NextWord : Word := (others => '0');
begin -- Behiavioral
while not endfile(programInput) loop
readline(programInput, in_line);
if in_line'length = 32 then
read(in_line, in_vector);
NextWord := to_stdlogicvector(in_vector);
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(7 downto 0)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
wait for 1 ns;
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(15 downto 8)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter + 1, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
wait for 1 ns;
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(23 downto 16)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter + 2, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
wait for 1 ns;
MemControllerToWrite <= std_logic_vector(resize(unsigned(NextWord(31 downto 24)), 32));
Instr <= OpcodeMemory & StoreByte & "00000" & "000000000000000000000";
MemControllerADDR <= std_logic_vector(to_unsigned(Counter + 3, 32));
wait for 1 ns;
MemControllerEnable <= '1';
wait for 1 ns;
MemControllerEnable <= '0';
Counter := Counter + 4;
else
writeline(output,in_line);
end if;
end loop;
wait for 2 ns;
MemoryPassthrough <= '1';
RST <= '1';
wait for 2 ns;
RST <= '0';
loop
wait for 100 ns;
CLK <= '1';
wait for 100 ns;
CLK <= '0';
end loop; -- N
wait;
end process;
Passthrough: process (MemControllerDone,MemControllerFromRead,MemControllerToWrite,MemControllerADDR,Instr,MemControllerEnable_C,MemControllerEnable,MemoryPassthrough,MemControllerADDR_C,Instr_C,MemControllerToWrite_C,MemControllerDone_M,MemControllerFromRead_M) is
begin
if MemoryPassthrough = '1' then
MemControllerADDR_M <= MemControllerADDR_C;
Instr_M <= Instr_C;
MemControllerToWrite_M <= MemControllerToWrite_C;
MemControllerDone_C <= MemControllerDone_M;
MemControllerFromRead_C <= MemControllerFromRead_M;
MemControllerEnable_M <= MemControllerEnable_C;
else
MemControllerADDR_M <= MemControllerADDR;
Instr_M <= Instr;
MemControllerEnable_M <= MemControllerEnable;
MemControllerToWrite_M <= MemControllerToWrite;
MemControllerDone <= MemControllerDone_M;
MemControllerFromRead <= MemControllerFromRead_M;
MemControllerDone_C <= '0';
MemControllerFromRead_C <= (others => '0');
end if;
end process;
end Behavioral;
|
-------------------------------------------------------------------------------
-- File Name: s25fl064a.vhd
-------------------------------------------------------------------------------
-- Copyright (C) 2005-2007 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 G.Gojanovic 05 May 11 Inital Release
-- V1.1 D.Randjelovic 06 Apr 11 MSB of latched address is ignored
-- V1.2 D.Randjelovic 06 May 04 Page Program Command used with the
-- single byte data corrected.
-- Release from Deep Power Down when
-- Electronic Signature is not read
-- fixed
-- V1.3 D.Stanojkovic 07 Jul 02 Correction to enable testing in NCSim
--
-------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FLASH
-- Technology: Flash Memory
-- Part: S25FL064A
--
-- Description: 64 Megabit Serial Flash Memory with 50MHz SPI Bus Interface
--
-------------------------------------------------------------------------------
-- Comments :
-- When testing with NCSim default value for TimingModel in
-- generic list should be removed, otherwise backannotation of this value
-- will not be done properly
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Known Bugs:
--
-------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE STD.textio.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY s25fl064a IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_SCK : VitalDelayType01 := VitalZeroDelay01;
tipd_SI : VitalDelayType01 := VitalZeroDelay01;
tipd_CSNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_SCK_SO : VitalDelayType01Z := UnitDelay01Z;--tV
tpd_CSNeg_SO : VitalDelayType01Z := UnitDelay01Z;--tDIS
tpd_HOLDNeg_SO : VitalDelayType01Z := UnitDelay01Z;--tLZ,tHZ
--tsetup values
tsetup_SI_SCK : VitalDelayType := UnitDelay; --tsuDAT /
tsetup_CSNeg_SCK : VitalDelayType := UnitDelay; --tCSS /
tsetup_HOLDNeg_SCK : VitalDelayType := UnitDelay; --tHD /
tsetup_WNeg_CSNeg : VitalDelayType := UnitDelay; --tWPS \
--thold values
thold_SI_SCK : VitalDelayType := UnitDelay; --thdDAT /
thold_CSNeg_SCK : VitalDelayType := UnitDelay; --tCSH /
thold_HOLDNeg_SCK : VitalDelayType := UnitDelay; --tCD /
thold_WNeg_CSNeg : VitalDelayType := UnitDelay; --tWPH \
--tpw values: pulse width
tpw_SCK_posedge : VitalDelayType := UnitDelay; --tWH
tpw_SCK_negedge : VitalDelayType := UnitDelay; --tWL
tpw_CSNeg_posedge : VitalDelayType := UnitDelay; --tCS
-- tperiod min (calculated as 1/max freq)
tperiod_SCK_rd : VitalDelayType := UnitDelay; -- fSCK=33MHz
tperiod_SCK_fast_rd : VitalDelayType := UnitDelay; -- fSCK=50MHz
-- tdevice values: values for internal delays
-- Page Program Operation
tdevice_PP : VitalDelayType := 3 ms; --tPP
--Sector Erase Operation
tdevice_SE : VitalDelayType := 3 sec; --tSE
--Bulk Erase Operation
tdevice_BE : VitalDelayType := 384 sec; --tBE
--Write Status Register Operation
tdevice_WR : VitalDelayType := 60 ms; --tW
--Deep Power Down
tdevice_DP : VitalDelayType := 3 us; --tDP
--Release from Software Protect Mode
tdevice_RES : VitalDelayType := 30 us; --tRES
--VCC (min) to CS# Low
tdevice_PU : VitalDelayType := 10 ms;
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
-- memory file to be loaded
mem_file_name : STRING := "s25fl064a.mem";
UserPreload : BOOLEAN := FALSE; --TRUE;
LongTimming : BOOLEAN := TRUE;
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
SCK : IN std_ulogic := 'U'; --serial clock input
SI : IN std_ulogic := 'U'; --serial data input
CSNeg : IN std_ulogic := 'U'; -- chip select input
HOLDNeg : IN std_ulogic := 'U'; -- hold input
WNeg : IN std_ulogic := 'U'; -- write protect input
SO : OUT std_ulogic := 'U' --serial data output
);
ATTRIBUTE VITAL_LEVEL0 of s25fl064a : ENTITY IS TRUE;
END s25fl064a;
-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of s25fl064a IS
ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT PartID : STRING := "s25fl064a";
CONSTANT MaxData : NATURAL := 16#FF#; --255;
CONSTANT SecSize : NATURAL := 16#FFFF#; --65535
CONSTANT SecNum : NATURAL := 127;
CONSTANT HiAddrBit : NATURAL := 22;
CONSTANT AddrRANGE : NATURAL := 16#7FFFFF#;
CONSTANT BYTE : NATURAL := 8;
--Electronic Signature
CONSTANT ES : NATURAL := 16#16#;
--Device ID
--Manufacturer Identification && Memory Type && Memory Capacity
CONSTANT DeviceID : NATURAL := 16#010216#;
-- interconnect path delay signals
SIGNAL SCK_ipd : std_ulogic := 'U';
SIGNAL SI_ipd : std_ulogic := 'U';
SIGNAL CSNeg_ipd : std_ulogic := 'U';
SIGNAL HOLDNeg_ipd : std_ulogic := 'U';
SIGNAL WNeg_ipd : std_ulogic := 'U';
--- internal delays
SIGNAL PP_in : std_ulogic := '0';
SIGNAL PP_out : std_ulogic := '0';
SIGNAL PU_in : std_ulogic := '0';
SIGNAL PU_out : std_ulogic := '0';
SIGNAL SE_in : std_ulogic := '0';
SIGNAL SE_out : std_ulogic := '0';
SIGNAL BE_in : std_ulogic := '0';
SIGNAL BE_out : std_ulogic := '0';
SIGNAL WR_in : std_ulogic := '0';
SIGNAL WR_out : std_ulogic := '0';
SIGNAL DP_in : std_ulogic := '0';
SIGNAL DP_out : std_ulogic := '0';
SIGNAL RES_in : std_ulogic := '0';
SIGNAL RES_out : std_ulogic := '0';
BEGIN
---------------------------------------------------------------------------
-- Internal Delays
---------------------------------------------------------------------------
-- Artificial VITAL primitives to incorporate internal delays
PP :VitalBuf(PP_out, PP_in, (tdevice_PP ,UnitDelay));
PU :VitalBuf(PU_out, PU_in, (tdevice_PU ,UnitDelay));
SE :VitalBuf(SE_out, SE_in, (tdevice_SE ,UnitDelay));
BE :VitalBuf(BE_out, BE_in, (tdevice_BE ,UnitDelay));
WR :VitalBuf(WR_out, WR_in, (tdevice_WR ,UnitDelay));
DP :VitalBuf(DP_out, DP_in, (tdevice_DP ,UnitDelay));
RES :VitalBuf(RES_out, RES_in, (tdevice_RES ,UnitDelay));
---------------------------------------------------------------------------
-- Wire Delays
---------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (SCK_ipd, SCK, tipd_SCK);
w_2 : VitalWireDelay (SI_ipd, SI, tipd_SI);
w_3 : VitalWireDelay (CSNeg_ipd, CSNeg, tipd_CSNeg);
w_4 : VitalWireDelay (HOLDNeg_ipd, HOLDNeg, tipd_HOLDNeg);
w_5 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
END BLOCK;
---------------------------------------------------------------------------
-- Main Behavior Block
---------------------------------------------------------------------------
Behavior: BLOCK
-- State Machine : State_Type
TYPE state_type IS (IDLE,
DP_DOWN,
WRITE_SR,
SECTOR_ER,
BULK_ER,
PAGE_PG
);
-- Instruction Type
TYPE instruction_type IS (NONE,
WREN,
WRDI,
WRSR,
RDSR,
READ,
RDID,
FAST_READ,
SE,
BE,
PP,
DP,
RES_READ_ES
);
TYPE WByteType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
--Flash Memory Array
TYPE MemArray IS ARRAY (0 TO AddrRANGE) OF INTEGER RANGE -1 TO MaxData;
---------------------------------------------------------------------------
-- memory declaration
---------------------------------------------------------------------------
SHARED VARIABLE Mem : MemArray := (OTHERS => MaxData);
-- states
SIGNAL current_state : state_type;
SIGNAL next_state : state_type;
SIGNAL WByte : WByteType := (others => 0);
SIGNAL Instruct : instruction_type;
--zero delay signal
SIGNAL SO_zd : std_logic :='Z';
--HOLD delay on output data
SIGNAL SO_z : std_logic :='Z';
-- powerup
SIGNAL PoweredUp : std_logic := '0';
SHARED VARIABLE Status_reg : std_logic_vector(7 downto 0)
:= (others => '0');
SIGNAL Status_reg_in : std_logic_vector(7 downto 0)
:= (others => '0');
ALIAS WEL :std_logic IS Status_reg(1);
ALIAS WIP :std_logic IS Status_reg(0);
ALIAS BP0 :std_logic IS Status_reg(2);
ALIAS BP1 :std_logic IS Status_reg(3);
ALIAS BP2 :std_logic IS Status_reg(4);
ALIAS SRWD :std_logic IS Status_reg(7);
--Command Register
SIGNAL write : std_logic := '0';
SIGNAL read_out : std_logic := '0';
SIGNAL fast_rd : boolean := true;
SIGNAL rd : boolean := false;
SIGNAL change_addr : std_logic := '0';
--FSM control signals
SIGNAL PDONE : std_logic := '1'; -- Page Prog. Done
SIGNAL PSTART : std_logic := '0'; --Start Page Programming
SIGNAL WDONE : std_logic := '1'; -- Write. Done
SIGNAL WSTART : std_logic := '0'; --Start Write
SIGNAL ESTART : std_logic := '0'; --Start Erase
SIGNAL EDONE : std_logic := '1'; --Erase Done
SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0;
SIGNAL Byte_number : NATURAL RANGE 0 TO 255 := 0;
SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) :=
(OTHERS => '0');
SIGNAL Address : NATURAL RANGE 0 TO AddrRANGE := 0;
-- timing check violation
SIGNAL Viol : X01 := '0';
PROCEDURE ADDRHILO_SEC(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE sector : NATURAL RANGE 0 TO SecNum;
BEGIN
sector := Addr/16#10000#;
AddrLOW := sector*16#10000#;
AddrHIGH := sector*16#10000# + 16#0FFFF#;
END AddrHILO_SEC;
PROCEDURE ADDRHILO_PG(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE page : NATURAL RANGE 0 TO 65535;
BEGIN
page := Addr/16#100#;
AddrLOW := Page*16#100#;
AddrHIGH := Page*16#100# + 16#FF#;
END AddrHILO_PG;
BEGIN
----------------------------------------------------------------------------
--Power Up time;
---------------------------------------------------------------------------
PoweredUp <= '1' AFTER tdevice_PU;
---------------------------------------------------------------------------
-- VITAL Timing Checks Procedures
---------------------------------------------------------------------------
VITALTimingCheck: PROCESS(SI_ipd, SCK_ipd, CSNeg_ipd, HOLDNeg_ipd,
WNeg_ipd)
-- Timing Check Variables
VARIABLE Tviol_SI_SCK : X01 := '0';
VARIABLE TD_SI_SCK : VitalTimingDataType;
VARIABLE Tviol_HOLD_SCK : X01 := '0';
VARIABLE TD_HOLD_SCK : VitalTimingDataType;
VARIABLE Tviol_CS_SCK : X01 := '0';
VARIABLE TD_CS_SCK : VitalTimingDataType;
VARIABLE Tviol_WS_CS : X01 := '0';
VARIABLE TD_WS_CS : VitalTimingDataType;
VARIABLE Tviol_WH_CS : X01 := '0';
VARIABLE TD_WH_CS : VitalTimingDataType;
VARIABLE Pviol_CS : X01 := '0';
VARIABLE PD_CS : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_SCK : X01 := '0';
VARIABLE PD_SCK : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_SCK_rd : X01 := '0';
VARIABLE PD_SCK_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_SCK_fast_rd: X01 := '0';
VARIABLE PD_SCK_fast_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Violation : X01 := '0';
BEGIN
---------------------------------------------------------------------------
-- Timing Check Section
---------------------------------------------------------------------------
IF (TimingChecksOn) THEN
-- Setup/Hold Check between SI and SCK
VitalSetupHoldCheck (
TestSignal => SI_ipd,
TestSignalName => "SI",
RefSignal => SCK_ipd,
RefSignalName => "SCK",
SetupHigh => tsetup_SI_SCK,
SetupLow => tsetup_SI_SCK,
HoldHigh => thold_SI_SCK,
HoldLow => thold_SI_SCK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_SI_SCK,
Violation => Tviol_SI_SCK
);
-- Setup/Hold Check between HOLD# and SCK /
VitalSetupHoldCheck (
TestSignal => HOLDNeg_ipd,
TestSignalName => "HOLD#",
RefSignal => SCK_ipd,
RefSignalName => "SCK",
SetupLow => tsetup_HOLDNeg_SCK,
HoldLow => thold_HOLDNeg_SCK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_HOLD_SCK,
Violation => Tviol_HOLD_SCK
);
-- Setup/Hold Check between CS# and SCK
VitalSetupHoldCheck (
TestSignal => CSNeg_ipd,
TestSignalName => "CS#",
RefSignal => SCK_ipd,
RefSignalName => "SCK",
SetupHigh => tsetup_CSNeg_SCK,
SetupLow => tsetup_CSNeg_SCK,
HoldHigh => thold_CSNeg_SCK,
HoldLow => thold_CSNeg_SCK,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_CS_SCK,
Violation => Tviol_CS_SCK
);
-- Setup Check between W# and CS# \
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => CSNeg_ipd,
RefSignalName => "CS#",
SetupHigh => tsetup_WNeg_CSNeg,
CheckEnabled => true,
RefTransition => '\',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WS_CS,
Violation => Tviol_WS_CS
);
-- Hold Check between W# and CS# /
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => CSNeg_ipd,
RefSignalName => "CS#",
HoldHigh => thold_WNeg_CSNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WH_CS,
Violation => Tviol_WH_CS
);
-- Period Check CS# m
VitalPeriodPulseCheck (
TestSignal => CSNeg_ipd,
TestSignalName => "CS#",
PulseWidthHigh => tpw_CSNeg_posedge,
PeriodData => PD_CS,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_CS,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check SCK for everything but READ
VitalPeriodPulseCheck (
TestSignal => SCK_ipd,
TestSignalName => "SCK",
PulseWidthLow => tpw_SCK_negedge,
PulseWidthHigh => tpw_SCK_posedge,
PeriodData => PD_SCK,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_SCK,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check SCK for READ
VitalPeriodPulseCheck (
TestSignal => SCK_ipd,
TestSignalName => "SCK",
Period => tperiod_SCK_rd,
PeriodData => PD_SCK_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_SCK_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => rd );
-- Period Check SCK for other than READ
VitalPeriodPulseCheck (
TestSignal => SCK_ipd,
TestSignalName => "SCK",
Period => tperiod_SCK_fast_rd,
PeriodData => PD_SCK_fast_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_SCK_fast_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => fast_rd );
Violation := Tviol_SI_SCK OR
Tviol_HOLD_SCK OR
Tviol_CS_SCK OR
Tviol_WS_CS OR
Tviol_WH_CS OR
Pviol_SCK OR
Pviol_SCK_rd OR
Pviol_SCK_fast_rd OR
Pviol_CS;
Viol <= Violation;
ASSERT Violation = '0'
REPORT InstancePath & partID & ": simulation may be" &
" inaccurate due to timing violations"
SEVERITY WARNING;
END IF;
END PROCESS VITALTimingCheck;
----------------------------------------------------------------------------
-- sequential process for FSM state transition
----------------------------------------------------------------------------
StateTransition : PROCESS(next_state, PoweredUp)
BEGIN
IF PoweredUp = '1' THEN
current_state <= next_state;
END IF;
END PROCESS StateTransition;
---------------------------------------------------------------------------
-- Write cycle decode
---------------------------------------------------------------------------
BusCycleDecode : PROCESS(SCK_ipd, CSNeg_ipd, HOLDNeg_ipd, SI_ipd, RES_in)
TYPE bus_cycle_type IS (STAND_BY,
CODE_BYTE,
ADDRESS_BYTES,
DUMMY_BYTES,
DATA_BYTES
);
VARIABLE bus_cycle_state : bus_cycle_type;
VARIABLE data_cnt : NATURAL := 0;
VARIABLE addr_cnt : NATURAL := 0;
VARIABLE code_cnt : NATURAL := 0;
VARIABLE dummy_cnt : NATURAL := 0;
VARIABLE bit_cnt : NATURAL := 0;
VARIABLE Data_in : std_logic_vector(2047 downto 0)
:= (others => '0');
VARIABLE code : std_logic_vector(7 downto 0);
VARIABLE code_in : std_logic_vector(7 downto 0);
VARIABLE Byte_slv : std_logic_vector(7 downto 0);
VARIABLE addr_bytes : std_logic_vector(HiAddrBit downto 0);
VARIABLE Address_in : std_logic_vector(23 downto 0);
BEGIN
CASE bus_cycle_state IS
WHEN STAND_BY =>
IF falling_edge(CSNeg_ipd) THEN
Instruct <= NONE;
write <= '1';
code_cnt := 0;
addr_cnt := 0;
data_cnt := 0;
dummy_cnt := 0;
bus_cycle_state := CODE_BYTE;
END IF;
WHEN CODE_BYTE =>
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
Code_in(code_cnt) := SI_ipd;
code_cnt := code_cnt + 1;
IF code_cnt = BYTE THEN
--MSB first
FOR I IN 7 DOWNTO 0 LOOP
code(i) := code_in(7-i);
END LOOP;
CASE code IS
WHEN "00000110" =>
Instruct <= WREN;
bus_cycle_state := DATA_BYTES;
WHEN "00000100" =>
Instruct <= WRDI;
bus_cycle_state := DATA_BYTES;
WHEN "00000001" =>
Instruct <= WRSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000101" =>
Instruct <= RDSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000011" =>
Instruct <= READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "00001011" =>
Instruct <= FAST_READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10011111" =>
Instruct <= RDID;
bus_cycle_state := DATA_BYTES;
WHEN "10101011" =>
Instruct <= RES_READ_ES;
bus_cycle_state := DUMMY_BYTES;
WHEN "11011000" =>
Instruct <= SE;
bus_cycle_state := ADDRESS_BYTES;
WHEN "11000111" =>
Instruct <= BE;
bus_cycle_state := DATA_BYTES;
WHEN "00000010" =>
Instruct <= PP;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10111001" =>
Instruct <= DP;
bus_cycle_state := DATA_BYTES;
WHEN others =>
null;
END CASE;
END IF;
END IF;
WHEN ADDRESS_BYTES =>
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
Address_in(addr_cnt) := SI_ipd;
addr_cnt := addr_cnt + 1;
IF addr_cnt = 3*BYTE THEN
FOR I IN 23 DOWNTO 23-HiAddrBit LOOP
addr_bytes(23-i) := Address_in(i);
END LOOP;
Address <= to_nat(addr_bytes);
change_addr <= '1','0' AFTER 1 ns;
IF Instruct = FAST_READ THEN
bus_cycle_state := DUMMY_BYTES;
ELSE
bus_cycle_state := DATA_BYTES;
END IF;
END IF;
END IF;
WHEN DUMMY_BYTES =>
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
dummy_cnt := dummy_cnt + 1;
IF dummy_cnt = BYTE THEN
IF Instruct = FAST_READ THEN
bus_cycle_state := DATA_BYTES;
END IF;
ELSIF dummy_cnt = 3*BYTE THEN
bus_cycle_state := DATA_BYTES;
END IF;
END IF;
IF rising_edge(CSNeg_ipd) THEN
bus_cycle_state := STAND_BY;
IF HOLDNeg_ipd = '1' AND Instruct = RES_READ_ES THEN
write <= '0';
END IF;
END IF;
WHEN DATA_BYTES =>
IF falling_edge(SCK_ipd) AND CSNeg_ipd = '0'
AND HOLDNeg_ipd = '1' THEN
IF Instruct = READ OR Instruct = RES_READ_ES
OR Instruct = FAST_READ OR Instruct = RDSR
OR Instruct = RDID THEN
read_out <= '1', '0' AFTER 1 ns;
END IF;
END IF;
IF rising_edge(SCK_ipd) AND HOLDNeg_ipd = '1' THEN
IF data_cnt > 2047 THEN
--In case of PP, if more than 256 bytes are
--sent to the device
IF bit_cnt = 0 THEN
FOR I IN 0 TO (255*BYTE - 1) LOOP
Data_in(i) := Data_in(i+8);
END LOOP;
END IF;
Data_in(2040 + bit_cnt) := SI_ipd;
bit_cnt := bit_cnt + 1;
IF bit_cnt = 8 THEN
bit_cnt := 0;
END IF;
data_cnt := data_cnt + 1;
ELSE
Data_in(data_cnt) := SI_ipd;
data_cnt := data_cnt + 1;
bit_cnt := 0;
END IF;
END IF;
IF rising_edge(CSNeg_ipd) THEN
bus_cycle_state := STAND_BY;
IF HOLDNeg_ipd = '1' THEN
CASE Instruct IS
WHEN WREN | WRDI | DP | BE | SE =>
IF data_cnt = 0 THEN
write <= '0';
END IF;
WHEN RDID | RES_READ_ES =>
write <= '0';
WHEN WRSR =>
IF data_cnt = 8 THEN
write <= '0';
Status_reg_in <= Data_in(7 downto 0);
--MSB first
END IF;
WHEN PP =>
IF ((data_cnt mod 8) = 0 AND
data_cnt > 0) THEN
write <= '0';
FOR I IN 0 TO 255 LOOP
FOR J IN 7 DOWNTO 0 LOOP
Byte_slv(j) :=
Data_in((i*8) + (7-j));
END LOOP;
WByte(i) <= to_nat(Byte_slv);
END LOOP;
IF data_cnt > 256*BYTE THEN
Byte_number <= 255;
ELSE
Byte_number <= data_cnt/8-1;
END IF;
END IF;
WHEN others =>
null;
END CASE;
END IF;
END IF;
END CASE;
END PROCESS BusCycleDecode;
---------------------------------------------------------------------------
-- Timing control for the Page Program
---------------------------------------------------------------------------
ProgTime : PROCESS(PSTART)
VARIABLE pob : time;
BEGIN
IF LongTimming THEN
pob := tdevice_PP;
ELSE
pob := tdevice_PP / 100;
END IF;
IF rising_edge(PSTART) AND PDONE = '1' THEN
IF NOT Sec_Prot(SA) = '1' THEN
PDONE <= '0', '1' AFTER pob;
END IF;
END IF;
END PROCESS ProgTime;
---------------------------------------------------------------------------
-- Timing control for the Write Status Register
---------------------------------------------------------------------------
WriteTime : PROCESS(WSTART)
VARIABLE wob : time;
BEGIN
IF LongTimming THEN
wob := tdevice_WR;
ELSE
wob := tdevice_WR / 100;
END IF;
IF rising_edge(WSTART) AND WDONE = '1' THEN
WDONE <= '0', '1' AFTER wob;
END IF;
END PROCESS WriteTime;
---------------------------------------------------------------------------
-- Timing control for the Bulk Erase
---------------------------------------------------------------------------
ErsTime : PROCESS(ESTART)
VARIABLE seo : time;
VARIABLE beo : time;
VARIABLE duration : time;
BEGIN
IF LongTimming THEN
seo := tdevice_SE;
beo := tdevice_BE;
ELSE
seo := tdevice_SE / 100;
beo := tdevice_BE / 100;
END IF;
IF rising_edge(ESTART) AND EDONE = '1' THEN
IF Instruct = BE THEN
duration := beo;
ELSE --Instruct = SE
duration := seo;
END IF;
EDONE <= '0', '1' AFTER duration;
END IF;
END PROCESS ErsTime;
CheckCEOnPowerUP :PROCESS
BEGIN
IF CSNeg /= '1' THEN
REPORT InstancePath & partID &
": Device is selected during Power Up"
SEVERITY WARNING;
END IF;
WAIT;
END PROCESS;
---------------------------------------------------------------------------
-- Main Behavior Process
-- combinational process for next state generation
---------------------------------------------------------------------------
StateGen :PROCESS(write, CSNeg, WDONE, PDONE, EDONE)
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) THEN
IF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
next_state <= WRITE_SR;
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= PAGE_PG;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= SECTOR_ER;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
next_state <= BULK_ER;
ELSIF Instruct = DP THEN
next_state <= DP_DOWN;
ELSE
next_state <= IDLE;
END IF;
END IF;
WHEN WRITE_SR =>
IF rising_edge(WDONE) THEN
next_state <= IDLE;
END IF;
WHEN PAGE_PG =>
IF rising_edge(PDONE) THEN
next_state <= IDLE;
END IF;
WHEN BULK_ER | SECTOR_ER =>
IF rising_edge(EDONE) THEN
next_state <= IDLE;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) AND Instruct = RES_READ_ES THEN
next_state <= IDLE;
END IF;
END CASE;
END PROCESS StateGen;
---------------------------------------------------------------------------
--FSM Output generation and general funcionality
---------------------------------------------------------------------------
Functional : PROCESS(write,read_out, WDONE, PDONE, EDONE, current_state,
CSNeg_ipd, HOLDNeg_ipd, Instruct, Address, WByte,
RES_out, change_addr, PoweredUp, WNeg_ipd)
TYPE WDataType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
VARIABLE WData : WDataType:= (OTHERS => 0);
VARIABLE oe : boolean := FALSE;
VARIABLE AddrLo : NATURAL;
VARIABLE AddrHi : NATURAL;
VARIABLE Addr : NATURAL;
VARIABLE read_cnt : NATURAL;
VARIABLE read_addr : NATURAL RANGE 0 TO AddrRANGE;
VARIABLE data_out : std_logic_vector(7 downto 0);
VARIABLE ident_out : std_logic_vector(23 downto 0);
VARIABLE old_bit : std_logic_vector(7 downto 0);
VARIABLE new_bit : std_logic_vector(7 downto 0);
VARIABLE old_int : INTEGER RANGE -1 to MaxData;
VARIABLE new_int : INTEGER RANGE -1 to MaxData;
VARIABLE wr_cnt : NATURAL RANGE 0 TO 255;
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
VARIABLE BP : std_logic_vector(2 downto 0) := "000";
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
oe := rising_edge(read_out) AND PoweredUp = '1';
IF Instruct'EVENT THEN
read_cnt := 0;
fast_rd <= true;
rd <= false;
END IF;
IF rising_edge(change_addr) THEN
read_addr := Address;
END IF;
IF RES_out'EVENT AND RES_out = '1' THEN
RES_in <= '0';
END IF;
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) THEN
read_cnt := 0;
IF RES_in = '1' THEN
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
IF Instruct = WREN THEN
WEL := '1';
ELSIF Instruct = WRDI THEN
WEL := '0';
ELSIF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg_ipd = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
WSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
PSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
SA <= sect;
Addr := Address;
wr_cnt := Byte_number;
FOR I IN wr_cnt DOWNTO 0 LOOP
IF Viol /= '0' AND Sec_Prot(SA) /= '0' THEN
WData(i) := -1;
ELSE
WData(i) := WByte(i);
END IF;
END LOOP;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
Addr := Address;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
END IF;
ELSIF oe AND RES_in = '0' THEN
IF Instruct = RDSR THEN
--Read Status Register
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ELSIF Instruct = READ OR Instruct = FAST_READ THEN
--Read Memory array
IF Instruct = READ THEN
fast_rd <= false;
rd <= true;
END IF;
data_out := to_slv(Mem(read_addr),8);
SO_zd <= data_out(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
IF read_addr = AddrRANGE THEN
read_addr := 0;
ELSE
read_addr := read_addr + 1;
END IF;
END IF;
ELSIF Instruct = RDID THEN
--Read Device ID
--can be terminated by driving CSNeg high
--at any time
ident_out := to_slv(DeviceID,24);
SO_zd <= ident_out(23-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 24 THEN
read_cnt := 0;
END IF;
ELSIF Instruct = RES_READ_ES THEN
--Read Electronic Signature
data_out := to_slv(ES,8);
SO_zd <= data_out(7 - read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ELSIF oe AND RES_in = '1' THEN
SO_zd <= 'X';
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
WHEN WRITE_SR =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
IF WDONE = '1' THEN
WIP := '0';
WEL := '0';
SRWD := Status_reg_in(0);--MSB first
BP2 := Status_reg_in(3);
BP1 := Status_reg_in(4);
BP0 := Status_reg_in(5);
BP := BP2 & BP1 & BP0;
CASE BP IS
WHEN "000" =>
Sec_Prot := (others => '0');
WHEN "001" =>
Sec_Prot(127) := '1';
Sec_Prot(126) := '1';
Sec_Prot(125 downto 0) := (others => '0');
WHEN "010" =>
Sec_Prot(127 downto 124):= (others => '1');
Sec_Prot(123 downto 0) := (others => '0');
WHEN "011" =>
Sec_Prot(127 downto 120):= to_slv(16#FF#,8);
Sec_Prot(119 downto 0) := (others => '0');
WHEN "100" =>
Sec_Prot(127 downto 112):= to_slv(16#FFFF#,16);
Sec_Prot(111 downto 0) := (others => '0');
WHEN "101" =>
Sec_Prot(127 downto 112):= to_slv(16#FFFF#,16);
Sec_Prot(111 downto 96):= to_slv(16#FFFF#,16);
Sec_Prot(95 downto 0) := (others => '0');
WHEN "110" =>
Sec_Prot(127 downto 112):= to_slv(16#FFFF#,16);
Sec_Prot(111 downto 96):= to_slv(16#FFFF#,16);
Sec_Prot(95 downto 80):= to_slv(16#FFFF#,16);
Sec_Prot(79 downto 64):= to_slv(16#FFFF#,16);
Sec_Prot(63 downto 0) := (others => '0');
WHEN others =>
Sec_Prot := (others => '1');
END CASE;
END IF;
WHEN PAGE_PG =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_PG(AddrLo, AddrHi, Addr);
IF (Addr + wr_cnt) > AddrHi THEN
wr_cnt := AddrHi - Addr;
END IF;
FOR I IN Addr TO Addr + wr_cnt LOOP
new_int := WData(i-Addr);
old_int := Mem(i);
IF new_int > -1 THEN
new_bit := to_slv(new_int,8);
IF old_int > -1 THEN
old_bit := to_slv(old_int,8);
FOR j IN 0 TO 7 LOOP
IF old_bit(j) = '0' THEN
new_bit(j) := '0';
END IF;
END LOOP;
new_int := to_nat(new_bit);
END IF;
WData(i-Addr) := new_int;
ELSE
WData(i-Addr) := -1;
END IF;
END LOOP;
FOR I IN Addr TO Addr + wr_cnt LOOP
Mem (i) := -1;
END LOOP;
IF PDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN Addr TO Addr + wr_cnt LOOP
Mem(i) := WData(i-Addr);
END LOOP;
END IF;
WHEN SECTOR_ER =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_SEC(AddrLo, AddrHi, Addr);
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN BULK_ER =>
IF oe AND Instruct = RDSR THEN
SO_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) THEN
IF Instruct = RES_READ_ES THEN
RES_in <= '1';
END IF;
ELSIF oe AND Instruct = RES_READ_ES THEN
--Read Electronic Signature
data_out := to_slv(ES,8);
SO_zd <= data_out(7 - read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
END CASE;
--Output Disable Control
IF (CSNeg_ipd = '1') THEN
SO_zd <= 'Z';
END IF;
END PROCESS Functional;
HOLD_FRAME_ON_SO_ZD : PROCESS( SO_zd, HOLDNeg_ipd)
BEGIN
IF (HOLDNeg_ipd = '0') THEN
SO_z <= 'Z';
ELSE
SO_z <= SO_zd;
END IF;
END PROCESS HOLD_FRAME_ON_SO_ZD;
---------------------------------------------------------------------------
---- File Read Section - Preload Control
---------------------------------------------------------------------------
MemPreload : PROCESS
-- text file input variables
FILE mem_file : text is mem_file_name;
VARIABLE ind : NATURAL := 0;
VARIABLE buf : line;
BEGIN
---------------------------------------------------------------------------
--s25fl016a memory preload file format -----------------------------------
---------------------------------------------------------------------------
-- / - comment
-- @aaaaaa - <aaaaaa> stands for address
-- dd - <dd> is byte to be written at Mem(aaaaaa++)
-- (aaaaaa is incremented at every load)
-- only first 1-7 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
---------------------------------------------------------------------------
-- memory preload
IF (mem_file_name /= "none" AND UserPreload) THEN
ind := 0;
Mem := (OTHERS => MaxData);
WHILE (not ENDFILE (mem_file)) LOOP
READLINE (mem_file, buf);
IF buf(1) = '/' THEN
NEXT;
ELSIF buf(1) = '@' THEN
ind := h(buf(2 to 7)); --address
IF ind > AddrRANGE THEN
ASSERT false
REPORT "Given preload address is out of" &
"memory address range"
SEVERITY warning;
END IF;
ELSE
IF ind <= AddrRANGE THEN
Mem(ind) := h(buf(1 to 2));
END IF;
IF ind < AddrRANGE THEN
ind := ind + 1;
END IF;
END IF;
END LOOP;
END IF;
WAIT;
END PROCESS MemPreload;
SO_OUT: PROCESS(SO_z)
VARIABLE SO_GlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01Z (
OutSignal => SO,
OutSignalName => "SO",
OutTemp => SO_z,
GlitchData => SO_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => SCK_ipd'LAST_EVENT,
PathDelay => VitalExtendtofillDelay(tpd_SCK_SO),
PathCondition => SO_z /= 'Z'),
1 => (InputChangeTime => CSNeg_ipd'LAST_EVENT,
PathDelay => tpd_CSNeg_SO,
PathCondition => CSNeg_ipd = '1'),
2 => (InputChangeTime => HOLDNeg_ipd'LAST_EVENT,
PathDelay => tpd_HOLDNeg_SO,
PathCondition => TRUE)
)
);
END PROCESS SO_OUT;
END BLOCK behavior;
END vhdl_behavioral;
|
-- Revision history:
-- 03.08.2015 Carlos Minamisava Faria created
-- 03.08.2015 Carlos Minamisava Faria entity MemoryStage
-- 04.08.2015 Carlos Minamisava Faria architecture MemoryStage
-- 05.08.2015 Carlos Minamisava Faria first working version
-- 11.08.2015 Lukas Jaeger fixed a bug in memory access
library IEEE;
use IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
library WORK;
use WORK.all;
entity MemoryStage is
port(
clk: in std_logic;
rst: in std_logic;
aluResult_in: in std_logic_vector(31 downto 0); --CPU_DATA_WIDTH-1 downto 0); -- ALU results from Execution Stage
data_in: in std_logic_vector(31 downto 0);--CPU_DATA_WIDTH-1 downto 0); -- Data from execution stage
-- Memory Read/Write decision comes from the FSS
data_addr: out std_logic_vector(31 downto 0);--CPU_ADDR_WIDTH-1 downto 0); -- Memory address output for memory r/w
data_from_cpu: out std_logic_vector(31 downto 0);--CPU_DATA_WIDTH-1 downto 0); -- Memory data out.
data_to_cpu: in std_logic_vector(31 downto 0);--CPU_DATA_WIDTH-1 downto 0); -- Read data from memory.
--not needed-- data_stall : in std_logic; -- data stall - cpu input
mux_decision: in std_logic; -- FSS decision for writeback output. ALU results or memory data can be forwarded to writeback
writeback: out std_logic_vector( 31 downto 0);--CPU_DATA_WIDTH-1 downto 0); -- Data to send to next stage: Writeback
reg_dest_in: in std_logic_vector(4 downto 0);--CPU_REG_ADDR_WIDTH-1 downto 0); -- k.A.
reg_dest_out: out std_logic_vector(4 downto 0));--CPU_REG_ADDR_WIDTH-1 downto 0)); -- k.A.
end entity MemoryStage;
architecture behavioral of MemoryStage is
-- signal memory_buffer: std_logic_vector(31 downto 0);--CPU_DATA_WIDTH-1 downto 0);
begin
-- Data address and data are always routed out.
data_addr <= aluResult_in;
data_from_cpu <= data_in;
-- reg_dest is forwarded
reg_dest_out <= reg_dest_in;
output: process (rst, aluResult_in,data_in, data_to_cpu, mux_decision, reg_dest_in)is
begin
if (rst='1') then -- reset condition
writeback <= x"00_00_00_00";
else
if (mux_decision ='0') then -- mux_decision choses between the two possible outputs: the result from ALU of the read memory
writeback <= aluResult_in; -- output is the aluResult_in
else
writeback <= data_to_cpu; -- output is the memory_buffer, which carries the memory read value.
end if;
end if;
end process output;
end architecture behavioral;
-- FSM-signal-Howto:
--
-- mux_decision:
-- 0: to forward aluResult
-- 1: to forward memory data
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity counter is
port ( clk : in bit; count : out natural );
end entity counter;
--------------------------------------------------
architecture behavior of counter is
begin
incrementer : process is
variable count_value : natural := 0;
begin
count <= count_value;
loop
wait until clk = '1';
count_value := (count_value + 1) mod 16;
count <= count_value;
end loop;
end process incrementer;
end architecture behavior;
|
--/**************************************************************************************************************
--*
--* L Z R W 1 E N C O D E R C O R E
--*
--* A high throughput loss less data compression core.
--*
--* Copyright 2012-2013 Lukas Schrittwieser (LS)
--*
--* This program is free software: you can redistribute it and/or modify
--* it under the terms of the GNU General Public License as published by
--* the Free Software Foundation, either version 2 of the License, or
--* (at your option) any later version.
--*
--* This program is distributed in the hope that it will be useful,
--* but WITHOUT ANY WARRANTY; without even the implied warranty of
--* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--* GNU General Public License for more details.
--*
--* You should have received a copy of the GNU General Public License
--* along with this program; if not, write to the Free Software
--* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
--* Or see <http://www.gnu.org/licenses/>
--*
--***************************************************************************************************************
--*
--* Change Log:
--*
--* Version 1.0 - 2012/8/12 - LS
--* started file
--*
--* Version 1.0 - 2013/4/5 - LS
--* release
--*
--***************************************************************************************************************
--*
--* Naming convention: http://dz.ee.ethz.ch/en/information/hdl-help/vhdl-naming-conventions.html
--*
--***************************************************************************************************************
--*
--* Test bench for outputFIFO.vhd
--*
--***************************************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity outputFIFO_tb is
end outputFIFO_tb;
architecture tb of outputFIFO_tb is
component outputFIFO
generic (
frameSize : integer);
port (
ClkxCI : in std_logic;
RstxRI : in std_logic;
BodyDataxDI : in std_logic_vector(7 downto 0);
BodyStrobexSI : in std_logic;
HeaderDataxDI : in std_logic_vector(frameSize-1 downto 0);
HeaderStrobexSI : in std_logic;
BuffersEmptyxSO : out std_logic;
BufOutxDO : out std_logic_vector(7 downto 0);
OutputValidxSO : out std_logic;
RdStrobexSI : in std_logic;
LengthxDO : out integer range 0 to 1024);
end component;
-- component generics
constant frameSize : integer := 8;
-- component ports
signal ClkxCI : std_logic;
signal RstxRI : std_logic := '1';
signal BodyDataxDI : std_logic_vector(7 downto 0) := (others => '0');
signal BodyStrobexSI : std_logic := '0';
signal HeaderDataxDI : std_logic_vector(frameSize-1 downto 0) := (others => '0');
signal HeaderStrobexSI : std_logic := '0';
signal BuffersEmptyxSO : std_logic;
signal BufOutxDO : std_logic_vector(7 downto 0);
signal OutputValidxSO : std_logic;
signal RdStrobexSI : std_logic := '0';
signal LengthxDO : integer range 0 to 1024;
-- clock
signal Clk : std_logic := '1';
constant PERIOD : time := 20ns;
begin -- tb
-- component instantiation
DUT : outputFIFO
generic map (
frameSize => frameSize)
port map (
ClkxCI => ClkxCI,
RstxRI => RstxRI,
BodyDataxDI => BodyDataxDI,
BodyStrobexSI => BodyStrobexSI,
HeaderDataxDI => HeaderDataxDI,
HeaderStrobexSI => HeaderStrobexSI,
BuffersEmptyxSO => BuffersEmptyxSO,
BufOutxDO => BufOutxDO,
OutputValidxSO => OutputValidxSO,
RdStrobexSI => RdStrobexSI,
LengthxDO => LengthxDO);
-- clock generation
Clk <= not Clk after PERIOD/2;
ClkxCI <= Clk;
-- waveform generation
WaveGen_Proc : process
begin
wait for 20 ns;
wait until ClkxCI'event and ClkxCI = '1';
RstxRI <= '0';
-- send a data frame with an odd number of bytes (header and body)
BodyDataxDI <= x"00";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"01";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"00";
BodyStrobexSI <= '0';
HeaderDataxDI <= x"0f";
HeaderStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"00";
BodyStrobexSI <= '0';
HeaderDataxDI <= x"00";
HeaderStrobexSI <= '0';
-- send a data frame to the input buffer
BodyDataxDI <= x"10";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"11";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"12";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"13";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"14";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"15";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"16";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"17";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyDataxDI <= x"18";
HeaderDataxDI <= x"1f";
HeaderStrobexSI <= '1';
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
HeaderStrobexSI <= '0';
HeaderDataxDI <= x"00";
BodyDataxDI <= x"00";
-- send a short frame (this is allowed for the last frame only)
BodyDataxDI <= x"ff";
BodyStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '1';
HeaderStrobexSI <= '1';
HeaderDataxDI <= x"ff";
BodyDataxDI <= x"ff";
wait until ClkxCI'event and ClkxCI = '1';
BodyStrobexSI <= '0';
HeaderStrobexSI <= '0';
HeaderDataxDI <= x"00";
BodyDataxDI <= x"00";
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '1';
wait for 15 * PERIOD;
RdStrobexSI <= '0';
wait until ClkxCI'event and ClkxCI = '1';
wait until ClkxCI'event and ClkxCI = '1';
-- try illegal read
RdStrobexSI <= '1';
wait until ClkxCI'event and ClkxCI = '1';
RdStrobexSI <= '0';
wait;
end process WaveGen_Proc;
end tb;
configuration outputFIFO_tb_tb_cfg of outputFIFO_tb is
for tb
end for;
end outputFIFO_tb_tb_cfg;
|
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end entity fifo;
-- Failures below
entity fifo is
generic (
gen_dec1 : integer := 0; -- Comment
gen_dec2 : integer := 1; -- Comment
gen_dec3 : integer := 2 -- Comment
);
port (
sig1 : std_logic; -- Comment
sig2 : std_logic; -- Comment
sig3 : std_logic -- Comment
);
end entity fifo;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
-- LRU Cache Replacement Algorithm
library ieee;
use ieee.std_logic_1164.all;
use work.cpu_l1mem_inst_cache_replace_lru_pkg.all;
entity cpu_l1mem_inst_cache_replace_lru is
port (
clk : in std_ulogic;
rstn : in std_ulogic;
cpu_l1mem_inst_cache_replace_lru_ctrl_in : in cpu_l1mem_inst_cache_replace_lru_ctrl_in_type;
cpu_l1mem_inst_cache_replace_lru_ctrl_out : out cpu_l1mem_inst_cache_replace_lru_ctrl_out_type;
cpu_l1mem_inst_cache_replace_lru_dp_in : in cpu_l1mem_inst_cache_replace_lru_dp_in_type;
cpu_l1mem_inst_cache_replace_lru_dp_out : out cpu_l1mem_inst_cache_replace_lru_dp_out_type
);
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
agqEJQkmewFCXHSVPn1cTFukw9jsPnAZXHaWLPFuwgR0UcR/vvLcbx7vWPF349Nx8Y8mfv6fbDj2
GO+xKUtQag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iEzXIY8dlehLk2ui2MGeS2mZU9X/4SY2u/QlOajOVvhSX6FdPYZF2RY74hxJ3VAKvDcs2IvNU5yw
Txesjym2m1RAxoYFfgqAYB20HHCGfw/yJg0B+eNljX/IJSEgTRGsc8cBaU5R+sDVVjILddzexLma
kzFR4F8cp9Rr1dgUI1w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fZOY2COHmP8B3Uf/UtDLITmeyaFSVbm7mD3CpQYunQhM19vFYNVdiueZqK0F/C2tHwtnxKcUcWJr
T/xwusWtGDYDkGd7TD0dT0WBlMEi4W9WF/8Cqd9ufFvrigyeDIc0sXiB9ub8YQMjkc0gQ8KEM0FH
gxQIdSQVbS8TgNZI5NzGu6B4Xs20yQ2fXVViz3B4klOVrC/EoVLsG+xni85uwaZmoXzRtHBuxeyZ
dQ/4+RsukSucBB99rLyOHvmnBbugNfnuOskGB9Yu8h6MU/iZGNtEyCxj0bOxRcUrhBRDwdQ9fc9P
nK9I/1NPbvPsNKnFimD/iUjcPPI6HzxwFarZlQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aLA/4xNQENA3IXJPNw1LySyNrAnA7FHhfjoK2YsJV499eH6p3fQlh9EyLQcma16Wj7k9SJBCSwt1
ylIYfoxoPGpFUdGNH1lkVrqjsUwtYIe+2kq4PVwXI6Sbyte30dUPg7RfdHvlvQDm1ir1VDGA4Mjh
vCCxKzEXk+eb65dOWrQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OoJJ/ZsCWiAeDh0F4uvmYC6tiHl2QWBCwrtW2LvFf8CVu4ZLYU7wvaf262Q6dcCmSG8YDJJbN2q0
zinUgcX6s7pRL2QtSTRRJif3HWp+s1aw2PFT6j2SbwOBKRLA9ecRFZvG46lZZJC+CFrQmZUMfWFb
Yef5QACDI1hQ2UjdogMi6RZnWu9AOYCI3G0twT7h3lwKGbERh4suOvAlxEvFQsbcYUHONdlGNao4
7JjWc3XXk+XZK7EjiIOSGPaYWwxTLLN0K8dYm9yLOWbOtl+toMzZL3HtWIkgyZHQLCUYkOSkioEz
WGokz8LZvj7rmIRYWMQH7DW00ZsAIRNZNm56Sg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10592)
`protect data_block
F4ULIPQlNZxTyCiE1UgKI5NdoMFv1mUlM2NvuWYhUBfXuWL33/h+Jaybc1XQqcsGyelqtDpbO6cr
BLb6RK8hYZZ98wmnHpNlw2fx+F/Vx7rnAmqQvs0xB2OAAh1QcfasxEq+cu2bPyT8oMBVaUg2wjun
od78+BSUBlVi7/kFRtffA/qTpSua8E1W3/3C19MkBgt5UN7MyXFqk1ZiJnMq6NCo0FKFlDgvB/uN
dCZk7RxDKAJSMS/ccpwAj6FWepP1F5I1n/0KCsdN0YJWw/fKLrxQcrTR0I1DP1lLOwW1sFOLEKQ4
fo3r4fyCkNAEAEeMzSWAtznUBzyUehQznT/hyQGm3D8PTLTlTgHaX0Z/P6o0ndwv6zYeW8wmHLdq
yGcpm+0aL66TXyEOvnSPqbc/FLCuar0myTKPC2l4q8ZHFIvvfddLvkQ9NMtjR3R2r6m8Ke2/rPHU
o9wjtbWtiEe8mx3j7M3iy6NjnxewylR8p2LECnu+Sn1And+T1CnodxZhpaJ5QctW/JgpSIIBCMxG
Cku0PYfR50+lEE/xhyV9AANHEUnxHeGNBxaKwnWYfKOzxm8VaCYrLAtngWZivOjtwllASOQAc9J+
MWmrxKBtm2H4HYuOjGGr0CbtOXc6OqjbrmmwXfaMlNOTPxn5tCDaQJm1VlbZrMlyrSW4iJNPMnfF
3ZPlZX+EelEXNTfKypJp+jUGodK8lchszEBzBn+vxERBNPKNP+PlsPSzupA40E3V4qfIXlo8CKng
zoIOKlbMH2MGqNxn3uzfcRQl9vbAzax77p895UAfpfws9OQ4Iq34IyDruCWQnNs2VYww7tha2G5O
I4I27UcVo0yRic6lxHoNlt9qe1+w7C7Gl3KVZJT0zicviPEXCRN64bGdXOcnhS54Rw+oXEUIKf2x
eKkdRDdQ2mdmNCbz/nSiYic9vtWhQnGzbzj9Z5juLq2rbs6Skt3xGpeDSEXK0XNcVOSnnfQPEChu
ELY+8VT1vFDSVGuSQa1cfpJdVobdT3gtC+ZyhqSYm2Q2B7F3Z84zaK3HNOx6Mn1nYV1zLN2EhLPi
RJqymWTTX7Xk2gxFIKa+qBdcZT1D9Ovts7PpHcszRUGWMvdFVvgubr9TrSgKO3P3AVOHxG7jZaht
G25S7ES5rM6CucUqwKFaEYDY1NYKN07QRep7nbIldRHo1NIRJQfH7Qet7VzXjx2OK4YYYAXjreG/
ZwJC9Fk85r7ei4aOz3rUefLQJ/c5QrwxfrpEHtOt04Hqmqk6jcM3fpRaPBHkHU1wi46L9xf7QJl+
qQjlN//UknrsLnPOPMNMOzIcgltGCPgkcvV4ow49ZoHVOGRcNIUsrh39jCRHbf2Wb7xv8Gj0ELpA
SnluW+DMFQTyDCrlC4LP/kthQ+HcJRnrQvzIwjEr3IXl+pvodsy8ts1Cu6By+/xPGLf/JE+kJmAu
4lJvCeL2iwJ+uTcV+hAFYsN5JAeV/M+UaJO0c+5oELRZ6/d2z+S5QwqBTxLNpwxqcxE1nY2y6gjt
sb1wnvgKwLkV5qgph3Pgu+LQ3FGiydEUxASZ2VPfBlVKbObDsYDo3FRKJk+gDQ0VEIaf7OhfEImu
0kjzxCWvqiNIevvlMpPRfy+t/PVnW/a/g5R8iKl/qoqStwKAELWsSPKZQrajQnCgb4TW7SYpJvUS
H1668G8mpVXBVd55lS0Lmy3d/LLKf8tLsI8RxwRIZzLKsxG9f160MuPEWdaMAXXHnDb6NMpExnG6
XbE+SRn6gzYOPfwuLXIajut6Wft8UGJaP+thsH4Rzv0XNSbhcS5evzQ4ygr1NNzYtexYC2srBweT
2BQqqGhJrTsQBrQXhLTpDqw92eIV2ytEvdnYqgyPBgWiB5fNqY0erbJ0redfiWEeVkSo71B3N0JX
cPtdBg65PZgCSBVS5Iq82Gezg2jF9pmqefcI15+9bqNeB/f1Cg5ESD6j0/Qbh2EPCHKkUmMAGdtA
qkzqZm2vfqYLhlYTvSu0bjwI32RSTjW8fSUd4FQW+RWFkYm+miMKO8cBG7j4j8VMEeKL7mQ1qHiJ
AowRRAYtBhgLOFUjPUfq/wUjHP7xxWJn5FMRP0aPytRySuWw4XL1cOQx9WI94q+bNobeKH2FC7kf
6b7obeMo5LqDwo//AOwzW4d37z81KiCVYhvMx1++C/Omendx6MS1qiYiBw/1tILnSWlti+5mONfF
3sLuEwZNgsrZ7/yswIR5IX+/FL9iup99s2rNFALKEMTd6T95lCukwmX6ORrS1Nh+bXBI184/hGmy
fK8hdT870Pzq9sgGgq8IiMo6rH6v0nf3aXbieENH6bJ4yFoecqDE7OvjTwsu2bdhtMNaAfJz5w8p
egSTP1sU/m9Yd3yu8HczBuwAAPiPRPnobkwpDFum33LCkrgwVYA+DlJvrsFwuXqGMNooXSXvJiOZ
ZH1F8A2+qS5cDesCFQrNaPrehNBh4uhuqE6oz+ij3wtnTR7WW63vJBV8IprMwaflusyD6y+1+eGU
3cHU01DiWhOjVC3mmg92HQoAGiUmUULKzgvderQzpUbYVHX8LCV9z4+A4LCXC5BrJMKyS4N7IhMI
o9Jo/ZqonaQmcE5fnLyMcqkjxaiNAm2DIfnfS+5qg8km+KEAMWmEHtiSZX0GXAqD8XTQZ6MTQw+D
WGYBV50iW090kyDxALQ4c53MCh8+fVH0AogoRRZnQouQaEGpScmjjekCcmHtXDFsMGycMbeGMiPH
G3xLOK6oCgyDUCkl6hxz1XguLtLvbfvKnpUXHVhNOJVuUQOcCZDuEubYb4LYKnQWn2f/jb9vlfCc
I2FN8YTvP6UgzllYscBJayB1QWv5iyhxkuDHaoQxj1hoUD8hpQiz34Awia/nGv0ms1p8obhcdC5j
De0NiHWPXejY52Q/Fdf6G+Nxs+9/KHX4/vfTRUkNhIqzWyjv5Yp4Kohlxa27oUF9qDMHRBtg1MyE
4IpXkuk/+KSzcqTQS9O0bgq6QPYmdlB2DgupRcXzfKaBl8FftuXqyHqf0rKQ7LeIVKpBQw0pi62n
a1HgHw8cTpkhMHASqvXSx4VdenjDt6x7l+cBhKiYzbx6hDIJGLkzqxUnvP5aWNFCi6CTgrYcAeob
yFQYtMlo1kb7/2PZwUI5XGEDGInkxw5ZTXg3LYEcdcyLGMRacdskjcOs2S0JKwKaz8kG2WZEsjF0
95X0oFcWEnNIyR9sB7sO2RyU5H8mJx8s4jzz0XSGDguaDpsE6+rUWGfdAxAuIdGjgoaqU8zqvic6
joX/XPrEWnOeP/64f3ydin0Y5B/U9VhNyuaVYepJqwyjcrv3Z0lCOZNVUDDV6IR6Jb9wO9GKA6ib
dXiUltDMA3mUhpZueLHaa7HRKKq/MLdTATSLmL3nRhszafQwrx0B/WGWVaMyyebNiRUJS1F34mma
SX4Dl3E1AkbYiIlt8bpRL2LLJxP1+Gp1Sg28OUt3ahwd8iAXM/10N4KSRJsDLahSTcsUyvc7JiAS
eq8FnPS2hprq/I/DoetLIY1IuZkQYFAgY58gvNoFK2dlj6xA3JRheXVki9O3Cf1+kF79Y42lJ68K
l45ipuj1fje5xf6hK8jBixQjlrkfo7KYF2XMczsIBiPj9HUaRdfRQaU+Zn6OTHuBbiBOXpCTRVII
aSQPCrNtqXeEgDMnEAWLz11B5IW0QcCntqVQVUjB/XfDs8zVegiHKALVaIqVhZuUhYAc/keRAD9b
K3qZcrcqT1SiITk331lEocjHpKtvOwzZlWIVNsD5fDuKQTSktb1W4L2Fb64mU7FGE57rlJC76Wyk
zrTwzT7t4BlJIVS+ognN2qtKqTT2je8Zluw3jPHrPUQx4maSe8jcdnWsFWBacddbhVShuEh5oX3m
WjWF/2BGSERpOpqCoZxbcSX0f+ImGGfzTmaPuVwlYI+Jzlufbp10S0NA+KK0KPsAjpCk45/HzZ1F
gg9ht30v4VNqGRrDBTWC3+rfj+MuSEHX1ckdCtVuaGhR4l3JYmbAZVVuuGSkigRhL8buPR9lyq3O
KFcjAnK1mC4W1Snlq2GtmX3qGMhHviSd49mm+3Rhy9zy8dXrRoKkV/M+waf0X5MwcvTePYNv/2A7
FV/Q0vA0HmStDdax/27CfqGcS/M69Kaf9X1sc703uF+qB/qGJ9oLy/13Qafa/EAmVN7G5chxMi+K
s+4+Z/E/xR5nAfsbqo5JxE56+5psGWew8D1xW7qSm0PqTGTKUExhEaBx8kRXVkEZGhhfC6VhVOGg
Tf3aBS2tL/dfG9zDXDd0d37cXN0KwzCRT8tvCTLuC+1nz9pxNS1/6mGfXXXBST1JR7wj3ZdXozg1
EE7P6mvcNoPZb2Eb333iLVUJhtE3/fJHVty3rguw+b6PtNO6zyUkjLB5CsRRmxgOxH3sLPRXToB3
wRKUU3VRZryMWvC+zylSkqeOgeUdXv2wW7GzFEHyp2JtHC9oVevd6meh1O9OMBHBPRBlbpgvaVqB
5dHVOHtSO9yktc0iz0qar62vSE7mg4BF+WKBmMTi/M4OUNND6hO2TrT7WypvABpJ1DHmz6ZFfPH1
2sWkPMKgPARTiY+1jZxkY56myHSAqOfQ3YTUuKjaC/7Ou2SxIAS/ljK30byjekbAYemkqXD9tqXo
mzbTg4zV/BGMHfb8ewl+MRXpzXIWoFt7eqIff/sX8Q+G/Hp+/sNBXm98Ii0TUnaNNYE71Cy74YjY
2OAfkBy8I+zK+Rtr9/urBWEZbhbvXReXV4rjLrc5sR5wBTjBs3P5081j2z21NQ/Hl5lv1MPvL4Zv
3gvlZc2HF6dSDEbuTnOtGDbHP9CNBljnG1L2Nwi8vgjZzyUoGllv/p3Qx+SxXLwOImuHFgXRgBmb
wnF+bY+9v12khY3RjSSQE9GTaHRVeUL0YgPM3i0bMKAlH/OZcYqgWXulxVRCOin55f8P4QGSVe8i
sL1Wola9vHLJYil/O/wt6lWM82/JXO4q5u/qtYmgrQnl4p01r/hfFmyXa1RzjYoct+A1YazDvuJP
aYMAidZjJsHiRDcDsdZqyAgWrP9wOv/Hp8z3qzjhtCLjQjwPsA86GiJtLz5mx2MyJUQuFi3e/n+3
FcgtMUgy9sjVJVb2HEvgcikOqfJYrvvUmMp6bo/UGRDnTjtdca6ocuGwTncfRyRXVExTB9h0MKEn
UL5g2G0hMQBmL94pZljbKIfLlvr9Sz1kj2b3wMWMaY8h2KHkltVcwQVZRN3AJ02BegBFTbRHpQhK
hjaTiYquxoEiyTbF0Kg0K/t0LhjNijtTdl5IhCwY+AGAaPkFY26yMDv5soXc2kUZwxBNMOJYxpTW
o3Du9ioEZqAFa2C++PXd3RVJvX5gSOhQqMtBPXByG54pn/wMPLXEFjQj3W4A9paUIVr/4lowlulv
J1wrlOcmva1BATXQq1rcsoHKL63cvTD3W8FuO8s8xMgLid39AEQdKz7Zw/JFDD0ltVlMTThsy8NZ
nnNhOeVE8xs2LWA5pAq1Lj0d0w/FnUSjmB8SgHi4/o2Apo/alVUNuK7M+6HFGhMivz5eCtVx1eqd
rhA81snacXGzSMW7/58zsM2MkyafjdFsypMRedNrIe34Zr1mFJdgq5bBkrjjrhYX3wrBnh4WGf84
lgjWtwGrJOEeIWlnWHZLTX2ZlYIrqIFuvGkSFCDZOdN+b/Pk0nPl72wxQCuMLOifdKz8t4IGhxHd
gzELBFTSGAHDfw5c4CYDP4os8CnZ1Mi7i2XKOeyohQ3at5I6ABdssRrjCNh3jxpp5Sh7i2dPce9y
6aXLE7BA2lFJc/uaOJ7nF6DcnFsTLVPlnCDNAXJruryC5XTIi5GClZ8cua88NE+aqRs/CIsk72o2
aC4aWUReGN3mYoWJdb01dbt1EpECpMyl5NX5W3C+xhllOQ4l91m8h0sF9tRQYpJsKYT/A/w0rx6d
5fbgaeZm3KlmMac5kkJLYZC1pl8ujTPkHZCA9IrvPfSz6sKEQH5jzkbpSHKEBdTdFL/k0mSdFAIQ
H/9T2MKeqULu6VVYforM1FkxWe2VGaY3Cs2/CnHsnciX/WSJ3H7aXO2ESTQMzCGLULxFKIi467m1
Wd/G6ButAVpit4/RKXVVy/F9CLISmco8LPJzr2fadeqnLmZ6sON65OIhZ2RF2/dkWHFL8AtwcumE
f0qAkT2ogxcCpm7yXJa1f1+9Qody97kOes7YER3esXzGlm0dNxMrvZdLQ5/GEk4jKi7Ca6K4pQCL
dsZIJN4xtrpTvGg7FlUw9J16HRPVUSZ/QT/OFacAvL+lwdavSlNghSDxQ5WcOtKhK91w6pSksMGw
8IGPo/2uwYPdjYPIStltc5FbYjL5MC615rCyYCLAGHzLsRW/TqJix45qmdxodPk5ipDvOFex5eel
kn3KWIojC35lcX+hoFj/LamK32kKJ42KNtQ0rqFWYz3rhMUD3Sg8oz9LCBzQLngCmiw1CPTX7HZG
ZmlZB0M1IFEa60MV5BYfUeosHF6j8+K8yIgCJXXRs+5d3mF8ioDCEKiuafLtAm+GF7JkFS62td6W
kx3yo0Y3QtPRc0kBqZMDCCooy1mQjEgEv5/UaqvOhIWZFaP6/l/iGKTuIVc5TySXe/b4fOV5Gj/M
7sqNBHOkVnAJsBWnGnku12X0cD4NQBWZYG2t3DGhZPTFJvA/atrvbC9zh8eTi5m+EMMPsYEVgrlP
2ZqEr42MxwKRV9PJUFuJYX7LTugyCRbSkjMUcHaYO3/KemXtK3z5HceAdmHCSi6YVumr1zpgFJtY
UtY6ZenwYb2VmaEkAv7faaudNpEM43YIiBsJx3Ke4uwxdQSZOT35c9pG0FByqgYNfooSwMVdoL1y
xnULt/uFSPeQswqDkpFz2MNm7hKnhDvTnBL1bJaNUfHt0KzZj7yELvTcvGj4wKK8kMpe74uJey+Z
CI+IjhEkUUkQnnsMQsoi0t+E21REAy3jL3FErflCy+Etu5KCINByFvbQYapLIpLxwYEFPbngp2l+
B7/nkWHMBCa9G2yJVA/Sg1sVyCCDTqGGijfRh0IV08DqRhuUSmi+u/82jtphgAVOGu70V4T1j6Ui
COrGYrOjsShfG0xavHzCaYTZabCODwz2dncV1hzdzYouTZZWbv5mNKJGLo46WbHOBf1lHgKSpHnL
oUtNaVoLZFeAHxwBE+dmsySK0UamPxtwv53iW7BgResEQQ1/lk64Ps1xXHh4rScJWAtGStuKeioO
LHGeJ3WEnVWD9WVTfyb1gymzm7yGpLuZ378A1xxLXINbNOovTKIcc2rjTIWyxcQkuUXCkgxJvZd7
dZ8PsBhWmc91KwZPaKjkCDvl1WuR20nKOIOCprsnsBCgRhqa481x7J1TAkPzIhc4SWxwCBtzWLqf
MO9wkfA9c/7m/5kFJZfll7fjUL/7y90fpQvlSlnrWlfvoEG8IqVk9w748MgNT2NpxfwjIWL2cYZo
c2/S6501cJ15q1MsUSjDvZuHJOWzIqvCvdLu8aQKjEVtIJjND+Et9CtR5aMMDrJ5tTitM0rGONWQ
lHozTk9pq/HPu6kP35yJvJOv032N7D3vt6jXoSIJJrQQv51oTvzmKfQIpeQqASGocn48CmwX5CUv
YNGnJN+2aNBh+ARdgqn0sjJK7eZG+Ajx0koMJYixhFPcvoc0Za9EvVck81nPBZAnDUtwJLEXcffh
yIvj2CyJU5PMGOmKdAC6siXB60ZieFtdd4koVFZqIgMV6kW4HFkXGOtd9YlE4F8CgdIiAvBAL2TO
4SLAd4uPaLsDGEACZc7HnydTDO5zvVCG8i9K1U7+bM050RI4q1R6DcH9qG+yy9yMiceq0sQGNFQC
GyhN9fxIYYEYxRUCXepHX75e0VygxKojuYfvi3QFWM1jNNOb50b9b9fnh9vHNxV4G/pYvqkC4SFL
V73TWABLQ1xA+4w/eL7z0TJgpM+T0d5BILYUkxAjRSramOOQA8ypbwoVM3UxEmBqcBJG+4KX2yPt
s1MWYbYnKWsh0jd5Aq3HLF0zPIaYB1UiRHFkG9284TKf+n6hkk/QiedJAJwxb3EVVoiLZX4RXF+B
LwRzQJ5QrlbS+9PXWbiW1L3XmdRYWo4BWIYDqajmuJhV02Ga3e1fIxHfSeoprIWCUkxO0hnq7Cdl
H8sy/F46lbvnaAJL3VblGuYEzOuXrPl9/aoeBFj4Oy/YXzcS14luPX76zfT4xNFrZDpWmLryRBcB
9+BoWQ1mSUnkq4yr1Pm4yLKeErAsjR1yk9sU9I6Qm2jb72FopJTWmcpfnvXBRPEJSILRFV8PXvMt
JA6dzTNNrEKBwBA9XSAoctXSXcmPTjn2NX7jXpYAPnAa469jSrB9090wVApq4WgTW7X480tIQEHz
9E278Cc7ZXOUw/0mhFAt7W4z7Tvo31E82upeSA0k/dEv+WG0tu1LZrR13vUP5ZXD0slMGSa9RG2n
j1F88x3BGPNKPHVfujliLiHaIMsweg8n3KZpVGOQAuvJNIZyzCs/fuLfxSHKqbLX/aJAbShp+pbr
Ya+bAc3GH0pjzXk28wztxNrBhuSO2jTHrD7o1ljpUilr2c597gE9KgoOta6oC1CvH0TB05aNVebz
/6gE5HgLc4KAnVDLkleL4RmVR4YVuokT5lOjrrD7x0TSth4tBvxa7OgL3oZ4w3msCnWv5/FGydSR
quo/Gib2vBjViF4rq68lMtDiuyR5YBeMXTP3pdcbeBlcVdYVNsVN2dTTlUxB3W5Eo5t02x4D16mG
RPsfRhf0PpqFxwH+fsFPKMcPPxkB+sxMNRgVmvdez6jMdjR3YAbiaC1IUFRmEqB+EgOS4u7eQQeG
g5y/K7t8/tNCDivc/rSCyxXrbTb/vg3EKJ1/cIeQjOqym2YpwtgBhp6EPV+CWn4dcEpkkUqwJG9w
4+ou+H6+x92Oag4TToRYSkLFrsN7SvMpjkKaFbRtj2XXirPvd6pnNwp63cror+mgQd+s2shTnvb8
ewSNT7w52XFsvCyn5hUfcV52D1YxUYjVsRhskBhb0Ruq0XK+jBpkcyXMuJX2lpCMNFUgi/BVXdsv
tFXx1DUjAVgBR0LuWoo9PP/Y3QzGbdsQbnZA47Mell4Z4etweuA27lRPsgMPIhMextiN/foWJ3S1
POfX1ZO9bAVxxXiFhhs4xGQTkvjmKSiJBfs7gjd58NiWij3TQ+wghSJ2WHsS9Im9ZTkCMuKDQBML
x6sSWFJfQ2X+idpzZL6VevMLZS76AFMTLUiRMbqLMmeL4039v0iHBS9yJWYMz0GYNBYeIrW6Nac3
YbLQYlorlUHgT0B4NUhlytb0rfqB9+pSrNO7Q0t4s44OlB0QC16vxkAJrMjlK/MZ40rRv+s2hLG8
lUmmyTYvkv58e/KAL2zOwd8HFSa/0m4rK2fZjMUOXjOPpU3sLTJmO+d/rqlHUBLev+v+mJ000W0q
uFgrMHRvlWO2TlXFF1NH7J1ESC/8NxOL/h0IT4pibin8rzfwkX4Oo50/rQioDdZRBj8KFGplj+8p
V/sMVTpzK57eLkQFViDPIIrPLmKQxMkh5fxzMoFaTdGgoUXvzP9WyiV124fkTNLLngljKGzVbyyK
Jn+H31ffWCrQjcmRyTMBZUxhDwEWMuUinuVvcd8Kyrpi/RyKG2NCx+4y8go2oavWM+R4OpKZ6BOh
nnADmbGaEHaN5TD8+SN4OzXG+A17y+r1Vl+zgqxTnfX3zSj9ho8JuoXVzVbs+jHEoNhqszbyopil
WqsNKSAAvm7XIi/4ioLqReTb6B7XTw3GrpkDMOu0qYGjsfezKOPT57o27XPMi4h2FqEO1eG3rJpp
9nECdvb0eWM2ZPMBfgbgmucC1uP/9RSl+kqsoyNwrjQYMz2lsfcttTqxQXLJBPvGECZ+d+SU/f6u
PIHsArnPYxhauk072krnwtLrfqWXDSAjUnRHtH/aLHpOFDXLDxYwwStQUWDXgEm4NzP++qmKzsL/
JTg42vP7km42ZA1o+TbVUWdk6F1KNY1C8eZnI3/dVyvsbk3k4kD3ZSgkgtGNAuuCZ6JBVMLSnwGy
PDCWBWCdu3fPtB67Q0wNCnkzJYlGUU+kSBRbzrXFEe/wIyIXoKChKEk4p6p5uFTv0CxNLquL+pPN
PbgPnu+01kinpxdtXDn6iEQPyi+k6Zy6Qla/rrhaOTobdpSsyPlKlx4L2CY+x2Cjj6sJCU1tr/aM
2KJKV//WQlYsQ6F7AUNR6g7pbxJGsZ4exI3Bn+BE9SiQuanDDFnQx+54zTyB+E2dmSam7UK4x8vH
rCRw8oEh/fkkSE9k5UrimFyTYJMhQ7tiv76eXo8sOz3QxQx9Tve30U0mSx8ZCHcu34523r4MVqXt
GOl+SIPHQBlYPcV73xMr8kUUZ0kpBXrTPdux3Ypg1iGH8umPKrJY8gEJYLYg+xyUnk3y0OxR4o6e
Yl7+9pLF6js49lJng/aUCmLgLYFK9FRLMG4fGqzLaXeI0cU3bBx7cjrlFNktGl2hspEJtO7dyzRd
Ny2var7qLb/aCUq/WjBIJel1AmCP8YA8U9qzA2oLkEitAD1ONQK7B+DgMz+tRoOajFu3iCVVt4E0
ioDqBFyP28kslOiTgowDthy33hT/WC1M5FRtyqJDe0q0hiRt2dh0Be3o8VjjzP0W8qhVkeJd1OUw
qhsMKIEg2dbJp/Sy1+tBI6eCIN2d50+GpKnF+64AFxLq40M/a5cFbsEcBNM/xZnltwCjysCth7ef
y5fnYQjKiQJb+8RN7WHtCyddNX/Ud62j1AeGZCCrNmfb/9QoNkCkjGbC0AptAiuBcZeyojvmny7A
4HO3gUegSkvrsxzWtdiqUXDwLlSDkYje8p6fnrcedGk2KDGQIRP7D+PtwmEJhgt0zeoWN2MX98y1
TQjCM7F29fMASecUfaJ70E7Eg7Yt3S9QELIutSp2w9jHHBpngz+2gV8CcKT124wm2iGuQD11kriv
13vR4S6kyAQxIuD3kucbb+KGWWT++ToCEn8yGYjV0x4buKFZPH1tTirwQyT+aP/bRMmBCvsm2wJD
lZD0AewDlYIWVOf3E9xmONG+/X1YJqgWyVXv6J0ZixRkgkiI7kTwFU1J16CfGxeEkprdG5HRFv+7
dIKB3CmwJmOtMl6sIBGy627jdugiL8tDrGanNcjBkoynRTXFCC2sHei5mMWb3CiahLFeTjWLcnVW
EMua/Cb4InPYryi+RfpTv6KuM4dkOM4zxJFhcQYMGoNCP/Ax4zqZskSxOPxM0oCN/Z4PVpf8fDiz
m6meDxLToImF9T1radgl3WNKb6xkxEh2+o5JY34CxfyqyKw+vGp/7lB0E+eogHf3Xtevj017NTNM
7I0KPEaCnVQdv88tfbDnsgShsjyzNhl2tMTtreRoqRNIMHmKIvla9sBlTvIR2RuTK65u2XyJCpDN
YDVpCxuBoP8aCb8ba0JJtTUb3uOlYPQNBYlaM0mLSnM9/4vMVUHqmS/QEzzBWsZH07l8VxiAsHN8
VPtMJ3//3eRUw5ye0a/CdYRJFX4tVefScadVxFouASA8SnHtSOWi6Dgrhwc1WPNvPNUIPYWA5/UJ
ygGhNX32ea1bbZNn7Wq3ZEajaLVe79L8zKQ2a7yLL7CBQp3fZeYMM92Pi1z5NOaRkrmyl2K3XaYo
3Rzve/XvCMi6AVxp+D3OBSBd6WIYDd9YDTIeXb+C9AU1rsTfgRQ+TAeoz7JNR4pcsSvw3ntwX64F
L29j3UZvc68rLSstYX9rGGCL+BzLju/jJZiTu2jTJVHhZr/aqVYaBDL6eG/fd7HNY8cVNiqNFcTu
Eaq4BmUSKU+uazTUyRL1Mwj+NUFaZn8kRsKF3NfebVw+AqR6HLH5G0hPAQAsIsb0t3/rlO58LsJu
jPKqvt9CYzjWsLog6RLcdZGkw2q0kRKECmKZc6dExPbSuT7ZIm7oSByUeMT2gGykZP0u1BSS2qMf
3mBmtqlovA4lhOiz0W2bbiM864nSsEX7oqJlNjPPxYCy+zUV6Yv6JbT1oZlke7VwX+js5XUC8yrv
EL67eNyZLMVRQsmRuyCNxZOhvhYI2r10MZEqRhUSQqt9DSlRK6+spj6YZ8GzGsSQ7CXYDlWKKBqz
+96pBI9anAFdjRSDi8ch49a5YuH5MhNdYajfcKtc+kRbvcdm5g36cli+LVShVNs9HvbsMB5+Ty0f
+K2vWuYOpOFl7Ux5f6Q5ns0f//37DKlg9GHg+Io8381o9de6Cminz151mov7JraRMMEiXTXW1UsG
3gm+Fw3d7fe9EfESX0pH3WBWy4FdmSVmxgR5err8+f7+XAn+8/vj/O/dPo0WvILJXViT6/N3L6ae
ReCAC1Ll7nHXBiHNAITdoEDrveeokttn2XI5glXeR0+hZUpZ9gEmmQWA2zd4L2D8NDYR5KU1glmH
bZ6GJsooqvhkuMtYLlsYzkotBXujDpin5bLX+DGsFqhulNco3eByWMl9a7dJvXx0qSN/ij+bwzJR
9khcXpWZhAXcdNzwQvhCTnZ0faXsk7sy8YcYLfU2pOhdsxEtdEMXgDzQ+tC9iVRJnw/SMe1ytb89
tzHTl+QwxJJKrnctcDybVSJ8rxs7MIDs5j/dEZgoxhxSSpjBHiUY2ppkqFeBVoen9QY15okcJ9jq
43dy7S9WnaHV51FZ7G1qmN5CCtv8ok8JLf4rNeNO51MXjLVJJua4T9NReeLK/moRjiKjo7F0MA9p
Z0m/O9MY0xHpsnJEhPPDVIpBwo7l43vzqvgaTJc0j6QvDNTkZVvghW+kwD6N1//Zu8DpKWcqDomM
pnBGCoMt5Hrk+iA/4hWYelHaD6DEcu5aLkoEaf8gAcZ1jgLYPwkOXiZ5ANUzN3Wl7Li2YFPFu2PK
vzdlna0o8bRjUbq87k33GbzKXqomS1Zc0XsgWwlsVJwir59YU1M6ZOO66wXqPQ8vsQeslMVLFo8x
nEfDow9ybfyrIhH90Q6845nOgOCEIt/SQGPBR4xUfAtfab5Ix+dgtJpCfUZxiI9ogG0yNjwazvN5
hzb6jM2n2n4qH86xemL+mMvAAAVNHonWvJqNImBF/QXW7WpJawH+3lalZoA7XsuY9sfBw6lHT7Gh
LU1omAh7yCLypirMdEVtTay3k5epiCj+Nvh41zB/+/yLA0OIh//cHP8dqRsDEQ6s+i6OCVrqNNQI
OZLCsyqzVAQWfjJZeXDWJdIjUQaps7NGqP8nriKg1pcRSKaU370v+JRPqulhJNlrGnrq2OGiQnvQ
URvp9wTTk2tdszowQgEDoAmc2juMlXgqKDzVLii+sgv4SR325tfaLdLYzeYjwSIVlyKJGFxqxkfK
eGlosoKuZtCuAtp5aq2Jl9CppLb/g/jE1hOq+VFwKw6Q/BkC31ZMVOc+Ufsx+INnyrc/jYXgt90Z
bShTPgPmUh4RDQXevvaw2evR4CFRqYlsk9mAlvmI/pAbqOjYyX8t0H8dvJgibmSsqeOMTKNe2s+a
M8UTXlomh63pFlbfeBm+bjurDRq1fkIdR4+T1S3Zphc+ZmVgDEuvh7HXJjHF9wEXOMNSQQ+Bl8qQ
unYOIu4YboytfvOG5ReyG919cF0UNXQY0mwG3/nHNzxRyNDipLU/FzcAXpQsrNavzLtNRUwn9EcT
MpjBf6F5BrMYpYIPZBWkz8m/PGZKNXTfG84rsJqrlb4W6GfiyC6gh3uaQTOuw3YoiXcLF7REsiJp
EgNugU99XUwvKFa+7kFaRA9gInaKIKzB1/IfZ+t4rPOo8qHQBmoA1jBbIO9THbg5BGRUuf78ujjw
82rrkjWCykziJDSpeL41OarfFwCALxPzdDHE3+SxTw596sTjhkvTtdRoqhZinVY/EZQJB/rbDgTv
Wr2i3PQ+Z9Q7IUkxjovat1yj6T2U/84bu29kA2TwFuJxoEGjzCMW+0A5iA2z+VCTXrUHBziE55/V
RqxC+H5+Q3jSf1NYIN+8udbeXbmOPQdrrzZ2JVSvj36L6I0xx+dKe78rUrqk2BGXXNol589VYP4+
enZB6dTDEQ2WAmeIVd6b10DclCGzUJQPO+Nx42HSVbpP6cnTrRzjNh1aIe/1M2I/CrIh9o6HZgXN
6K5DYzR1nLigv5tfI4jPBeUIYj23Jz4wYZe75yckadyj/4SeJH43L0w1m8Kvc14=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
agqEJQkmewFCXHSVPn1cTFukw9jsPnAZXHaWLPFuwgR0UcR/vvLcbx7vWPF349Nx8Y8mfv6fbDj2
GO+xKUtQag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iEzXIY8dlehLk2ui2MGeS2mZU9X/4SY2u/QlOajOVvhSX6FdPYZF2RY74hxJ3VAKvDcs2IvNU5yw
Txesjym2m1RAxoYFfgqAYB20HHCGfw/yJg0B+eNljX/IJSEgTRGsc8cBaU5R+sDVVjILddzexLma
kzFR4F8cp9Rr1dgUI1w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fZOY2COHmP8B3Uf/UtDLITmeyaFSVbm7mD3CpQYunQhM19vFYNVdiueZqK0F/C2tHwtnxKcUcWJr
T/xwusWtGDYDkGd7TD0dT0WBlMEi4W9WF/8Cqd9ufFvrigyeDIc0sXiB9ub8YQMjkc0gQ8KEM0FH
gxQIdSQVbS8TgNZI5NzGu6B4Xs20yQ2fXVViz3B4klOVrC/EoVLsG+xni85uwaZmoXzRtHBuxeyZ
dQ/4+RsukSucBB99rLyOHvmnBbugNfnuOskGB9Yu8h6MU/iZGNtEyCxj0bOxRcUrhBRDwdQ9fc9P
nK9I/1NPbvPsNKnFimD/iUjcPPI6HzxwFarZlQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aLA/4xNQENA3IXJPNw1LySyNrAnA7FHhfjoK2YsJV499eH6p3fQlh9EyLQcma16Wj7k9SJBCSwt1
ylIYfoxoPGpFUdGNH1lkVrqjsUwtYIe+2kq4PVwXI6Sbyte30dUPg7RfdHvlvQDm1ir1VDGA4Mjh
vCCxKzEXk+eb65dOWrQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OoJJ/ZsCWiAeDh0F4uvmYC6tiHl2QWBCwrtW2LvFf8CVu4ZLYU7wvaf262Q6dcCmSG8YDJJbN2q0
zinUgcX6s7pRL2QtSTRRJif3HWp+s1aw2PFT6j2SbwOBKRLA9ecRFZvG46lZZJC+CFrQmZUMfWFb
Yef5QACDI1hQ2UjdogMi6RZnWu9AOYCI3G0twT7h3lwKGbERh4suOvAlxEvFQsbcYUHONdlGNao4
7JjWc3XXk+XZK7EjiIOSGPaYWwxTLLN0K8dYm9yLOWbOtl+toMzZL3HtWIkgyZHQLCUYkOSkioEz
WGokz8LZvj7rmIRYWMQH7DW00ZsAIRNZNm56Sg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10592)
`protect data_block
F4ULIPQlNZxTyCiE1UgKI5NdoMFv1mUlM2NvuWYhUBfXuWL33/h+Jaybc1XQqcsGyelqtDpbO6cr
BLb6RK8hYZZ98wmnHpNlw2fx+F/Vx7rnAmqQvs0xB2OAAh1QcfasxEq+cu2bPyT8oMBVaUg2wjun
od78+BSUBlVi7/kFRtffA/qTpSua8E1W3/3C19MkBgt5UN7MyXFqk1ZiJnMq6NCo0FKFlDgvB/uN
dCZk7RxDKAJSMS/ccpwAj6FWepP1F5I1n/0KCsdN0YJWw/fKLrxQcrTR0I1DP1lLOwW1sFOLEKQ4
fo3r4fyCkNAEAEeMzSWAtznUBzyUehQznT/hyQGm3D8PTLTlTgHaX0Z/P6o0ndwv6zYeW8wmHLdq
yGcpm+0aL66TXyEOvnSPqbc/FLCuar0myTKPC2l4q8ZHFIvvfddLvkQ9NMtjR3R2r6m8Ke2/rPHU
o9wjtbWtiEe8mx3j7M3iy6NjnxewylR8p2LECnu+Sn1And+T1CnodxZhpaJ5QctW/JgpSIIBCMxG
Cku0PYfR50+lEE/xhyV9AANHEUnxHeGNBxaKwnWYfKOzxm8VaCYrLAtngWZivOjtwllASOQAc9J+
MWmrxKBtm2H4HYuOjGGr0CbtOXc6OqjbrmmwXfaMlNOTPxn5tCDaQJm1VlbZrMlyrSW4iJNPMnfF
3ZPlZX+EelEXNTfKypJp+jUGodK8lchszEBzBn+vxERBNPKNP+PlsPSzupA40E3V4qfIXlo8CKng
zoIOKlbMH2MGqNxn3uzfcRQl9vbAzax77p895UAfpfws9OQ4Iq34IyDruCWQnNs2VYww7tha2G5O
I4I27UcVo0yRic6lxHoNlt9qe1+w7C7Gl3KVZJT0zicviPEXCRN64bGdXOcnhS54Rw+oXEUIKf2x
eKkdRDdQ2mdmNCbz/nSiYic9vtWhQnGzbzj9Z5juLq2rbs6Skt3xGpeDSEXK0XNcVOSnnfQPEChu
ELY+8VT1vFDSVGuSQa1cfpJdVobdT3gtC+ZyhqSYm2Q2B7F3Z84zaK3HNOx6Mn1nYV1zLN2EhLPi
RJqymWTTX7Xk2gxFIKa+qBdcZT1D9Ovts7PpHcszRUGWMvdFVvgubr9TrSgKO3P3AVOHxG7jZaht
G25S7ES5rM6CucUqwKFaEYDY1NYKN07QRep7nbIldRHo1NIRJQfH7Qet7VzXjx2OK4YYYAXjreG/
ZwJC9Fk85r7ei4aOz3rUefLQJ/c5QrwxfrpEHtOt04Hqmqk6jcM3fpRaPBHkHU1wi46L9xf7QJl+
qQjlN//UknrsLnPOPMNMOzIcgltGCPgkcvV4ow49ZoHVOGRcNIUsrh39jCRHbf2Wb7xv8Gj0ELpA
SnluW+DMFQTyDCrlC4LP/kthQ+HcJRnrQvzIwjEr3IXl+pvodsy8ts1Cu6By+/xPGLf/JE+kJmAu
4lJvCeL2iwJ+uTcV+hAFYsN5JAeV/M+UaJO0c+5oELRZ6/d2z+S5QwqBTxLNpwxqcxE1nY2y6gjt
sb1wnvgKwLkV5qgph3Pgu+LQ3FGiydEUxASZ2VPfBlVKbObDsYDo3FRKJk+gDQ0VEIaf7OhfEImu
0kjzxCWvqiNIevvlMpPRfy+t/PVnW/a/g5R8iKl/qoqStwKAELWsSPKZQrajQnCgb4TW7SYpJvUS
H1668G8mpVXBVd55lS0Lmy3d/LLKf8tLsI8RxwRIZzLKsxG9f160MuPEWdaMAXXHnDb6NMpExnG6
XbE+SRn6gzYOPfwuLXIajut6Wft8UGJaP+thsH4Rzv0XNSbhcS5evzQ4ygr1NNzYtexYC2srBweT
2BQqqGhJrTsQBrQXhLTpDqw92eIV2ytEvdnYqgyPBgWiB5fNqY0erbJ0redfiWEeVkSo71B3N0JX
cPtdBg65PZgCSBVS5Iq82Gezg2jF9pmqefcI15+9bqNeB/f1Cg5ESD6j0/Qbh2EPCHKkUmMAGdtA
qkzqZm2vfqYLhlYTvSu0bjwI32RSTjW8fSUd4FQW+RWFkYm+miMKO8cBG7j4j8VMEeKL7mQ1qHiJ
AowRRAYtBhgLOFUjPUfq/wUjHP7xxWJn5FMRP0aPytRySuWw4XL1cOQx9WI94q+bNobeKH2FC7kf
6b7obeMo5LqDwo//AOwzW4d37z81KiCVYhvMx1++C/Omendx6MS1qiYiBw/1tILnSWlti+5mONfF
3sLuEwZNgsrZ7/yswIR5IX+/FL9iup99s2rNFALKEMTd6T95lCukwmX6ORrS1Nh+bXBI184/hGmy
fK8hdT870Pzq9sgGgq8IiMo6rH6v0nf3aXbieENH6bJ4yFoecqDE7OvjTwsu2bdhtMNaAfJz5w8p
egSTP1sU/m9Yd3yu8HczBuwAAPiPRPnobkwpDFum33LCkrgwVYA+DlJvrsFwuXqGMNooXSXvJiOZ
ZH1F8A2+qS5cDesCFQrNaPrehNBh4uhuqE6oz+ij3wtnTR7WW63vJBV8IprMwaflusyD6y+1+eGU
3cHU01DiWhOjVC3mmg92HQoAGiUmUULKzgvderQzpUbYVHX8LCV9z4+A4LCXC5BrJMKyS4N7IhMI
o9Jo/ZqonaQmcE5fnLyMcqkjxaiNAm2DIfnfS+5qg8km+KEAMWmEHtiSZX0GXAqD8XTQZ6MTQw+D
WGYBV50iW090kyDxALQ4c53MCh8+fVH0AogoRRZnQouQaEGpScmjjekCcmHtXDFsMGycMbeGMiPH
G3xLOK6oCgyDUCkl6hxz1XguLtLvbfvKnpUXHVhNOJVuUQOcCZDuEubYb4LYKnQWn2f/jb9vlfCc
I2FN8YTvP6UgzllYscBJayB1QWv5iyhxkuDHaoQxj1hoUD8hpQiz34Awia/nGv0ms1p8obhcdC5j
De0NiHWPXejY52Q/Fdf6G+Nxs+9/KHX4/vfTRUkNhIqzWyjv5Yp4Kohlxa27oUF9qDMHRBtg1MyE
4IpXkuk/+KSzcqTQS9O0bgq6QPYmdlB2DgupRcXzfKaBl8FftuXqyHqf0rKQ7LeIVKpBQw0pi62n
a1HgHw8cTpkhMHASqvXSx4VdenjDt6x7l+cBhKiYzbx6hDIJGLkzqxUnvP5aWNFCi6CTgrYcAeob
yFQYtMlo1kb7/2PZwUI5XGEDGInkxw5ZTXg3LYEcdcyLGMRacdskjcOs2S0JKwKaz8kG2WZEsjF0
95X0oFcWEnNIyR9sB7sO2RyU5H8mJx8s4jzz0XSGDguaDpsE6+rUWGfdAxAuIdGjgoaqU8zqvic6
joX/XPrEWnOeP/64f3ydin0Y5B/U9VhNyuaVYepJqwyjcrv3Z0lCOZNVUDDV6IR6Jb9wO9GKA6ib
dXiUltDMA3mUhpZueLHaa7HRKKq/MLdTATSLmL3nRhszafQwrx0B/WGWVaMyyebNiRUJS1F34mma
SX4Dl3E1AkbYiIlt8bpRL2LLJxP1+Gp1Sg28OUt3ahwd8iAXM/10N4KSRJsDLahSTcsUyvc7JiAS
eq8FnPS2hprq/I/DoetLIY1IuZkQYFAgY58gvNoFK2dlj6xA3JRheXVki9O3Cf1+kF79Y42lJ68K
l45ipuj1fje5xf6hK8jBixQjlrkfo7KYF2XMczsIBiPj9HUaRdfRQaU+Zn6OTHuBbiBOXpCTRVII
aSQPCrNtqXeEgDMnEAWLz11B5IW0QcCntqVQVUjB/XfDs8zVegiHKALVaIqVhZuUhYAc/keRAD9b
K3qZcrcqT1SiITk331lEocjHpKtvOwzZlWIVNsD5fDuKQTSktb1W4L2Fb64mU7FGE57rlJC76Wyk
zrTwzT7t4BlJIVS+ognN2qtKqTT2je8Zluw3jPHrPUQx4maSe8jcdnWsFWBacddbhVShuEh5oX3m
WjWF/2BGSERpOpqCoZxbcSX0f+ImGGfzTmaPuVwlYI+Jzlufbp10S0NA+KK0KPsAjpCk45/HzZ1F
gg9ht30v4VNqGRrDBTWC3+rfj+MuSEHX1ckdCtVuaGhR4l3JYmbAZVVuuGSkigRhL8buPR9lyq3O
KFcjAnK1mC4W1Snlq2GtmX3qGMhHviSd49mm+3Rhy9zy8dXrRoKkV/M+waf0X5MwcvTePYNv/2A7
FV/Q0vA0HmStDdax/27CfqGcS/M69Kaf9X1sc703uF+qB/qGJ9oLy/13Qafa/EAmVN7G5chxMi+K
s+4+Z/E/xR5nAfsbqo5JxE56+5psGWew8D1xW7qSm0PqTGTKUExhEaBx8kRXVkEZGhhfC6VhVOGg
Tf3aBS2tL/dfG9zDXDd0d37cXN0KwzCRT8tvCTLuC+1nz9pxNS1/6mGfXXXBST1JR7wj3ZdXozg1
EE7P6mvcNoPZb2Eb333iLVUJhtE3/fJHVty3rguw+b6PtNO6zyUkjLB5CsRRmxgOxH3sLPRXToB3
wRKUU3VRZryMWvC+zylSkqeOgeUdXv2wW7GzFEHyp2JtHC9oVevd6meh1O9OMBHBPRBlbpgvaVqB
5dHVOHtSO9yktc0iz0qar62vSE7mg4BF+WKBmMTi/M4OUNND6hO2TrT7WypvABpJ1DHmz6ZFfPH1
2sWkPMKgPARTiY+1jZxkY56myHSAqOfQ3YTUuKjaC/7Ou2SxIAS/ljK30byjekbAYemkqXD9tqXo
mzbTg4zV/BGMHfb8ewl+MRXpzXIWoFt7eqIff/sX8Q+G/Hp+/sNBXm98Ii0TUnaNNYE71Cy74YjY
2OAfkBy8I+zK+Rtr9/urBWEZbhbvXReXV4rjLrc5sR5wBTjBs3P5081j2z21NQ/Hl5lv1MPvL4Zv
3gvlZc2HF6dSDEbuTnOtGDbHP9CNBljnG1L2Nwi8vgjZzyUoGllv/p3Qx+SxXLwOImuHFgXRgBmb
wnF+bY+9v12khY3RjSSQE9GTaHRVeUL0YgPM3i0bMKAlH/OZcYqgWXulxVRCOin55f8P4QGSVe8i
sL1Wola9vHLJYil/O/wt6lWM82/JXO4q5u/qtYmgrQnl4p01r/hfFmyXa1RzjYoct+A1YazDvuJP
aYMAidZjJsHiRDcDsdZqyAgWrP9wOv/Hp8z3qzjhtCLjQjwPsA86GiJtLz5mx2MyJUQuFi3e/n+3
FcgtMUgy9sjVJVb2HEvgcikOqfJYrvvUmMp6bo/UGRDnTjtdca6ocuGwTncfRyRXVExTB9h0MKEn
UL5g2G0hMQBmL94pZljbKIfLlvr9Sz1kj2b3wMWMaY8h2KHkltVcwQVZRN3AJ02BegBFTbRHpQhK
hjaTiYquxoEiyTbF0Kg0K/t0LhjNijtTdl5IhCwY+AGAaPkFY26yMDv5soXc2kUZwxBNMOJYxpTW
o3Du9ioEZqAFa2C++PXd3RVJvX5gSOhQqMtBPXByG54pn/wMPLXEFjQj3W4A9paUIVr/4lowlulv
J1wrlOcmva1BATXQq1rcsoHKL63cvTD3W8FuO8s8xMgLid39AEQdKz7Zw/JFDD0ltVlMTThsy8NZ
nnNhOeVE8xs2LWA5pAq1Lj0d0w/FnUSjmB8SgHi4/o2Apo/alVUNuK7M+6HFGhMivz5eCtVx1eqd
rhA81snacXGzSMW7/58zsM2MkyafjdFsypMRedNrIe34Zr1mFJdgq5bBkrjjrhYX3wrBnh4WGf84
lgjWtwGrJOEeIWlnWHZLTX2ZlYIrqIFuvGkSFCDZOdN+b/Pk0nPl72wxQCuMLOifdKz8t4IGhxHd
gzELBFTSGAHDfw5c4CYDP4os8CnZ1Mi7i2XKOeyohQ3at5I6ABdssRrjCNh3jxpp5Sh7i2dPce9y
6aXLE7BA2lFJc/uaOJ7nF6DcnFsTLVPlnCDNAXJruryC5XTIi5GClZ8cua88NE+aqRs/CIsk72o2
aC4aWUReGN3mYoWJdb01dbt1EpECpMyl5NX5W3C+xhllOQ4l91m8h0sF9tRQYpJsKYT/A/w0rx6d
5fbgaeZm3KlmMac5kkJLYZC1pl8ujTPkHZCA9IrvPfSz6sKEQH5jzkbpSHKEBdTdFL/k0mSdFAIQ
H/9T2MKeqULu6VVYforM1FkxWe2VGaY3Cs2/CnHsnciX/WSJ3H7aXO2ESTQMzCGLULxFKIi467m1
Wd/G6ButAVpit4/RKXVVy/F9CLISmco8LPJzr2fadeqnLmZ6sON65OIhZ2RF2/dkWHFL8AtwcumE
f0qAkT2ogxcCpm7yXJa1f1+9Qody97kOes7YER3esXzGlm0dNxMrvZdLQ5/GEk4jKi7Ca6K4pQCL
dsZIJN4xtrpTvGg7FlUw9J16HRPVUSZ/QT/OFacAvL+lwdavSlNghSDxQ5WcOtKhK91w6pSksMGw
8IGPo/2uwYPdjYPIStltc5FbYjL5MC615rCyYCLAGHzLsRW/TqJix45qmdxodPk5ipDvOFex5eel
kn3KWIojC35lcX+hoFj/LamK32kKJ42KNtQ0rqFWYz3rhMUD3Sg8oz9LCBzQLngCmiw1CPTX7HZG
ZmlZB0M1IFEa60MV5BYfUeosHF6j8+K8yIgCJXXRs+5d3mF8ioDCEKiuafLtAm+GF7JkFS62td6W
kx3yo0Y3QtPRc0kBqZMDCCooy1mQjEgEv5/UaqvOhIWZFaP6/l/iGKTuIVc5TySXe/b4fOV5Gj/M
7sqNBHOkVnAJsBWnGnku12X0cD4NQBWZYG2t3DGhZPTFJvA/atrvbC9zh8eTi5m+EMMPsYEVgrlP
2ZqEr42MxwKRV9PJUFuJYX7LTugyCRbSkjMUcHaYO3/KemXtK3z5HceAdmHCSi6YVumr1zpgFJtY
UtY6ZenwYb2VmaEkAv7faaudNpEM43YIiBsJx3Ke4uwxdQSZOT35c9pG0FByqgYNfooSwMVdoL1y
xnULt/uFSPeQswqDkpFz2MNm7hKnhDvTnBL1bJaNUfHt0KzZj7yELvTcvGj4wKK8kMpe74uJey+Z
CI+IjhEkUUkQnnsMQsoi0t+E21REAy3jL3FErflCy+Etu5KCINByFvbQYapLIpLxwYEFPbngp2l+
B7/nkWHMBCa9G2yJVA/Sg1sVyCCDTqGGijfRh0IV08DqRhuUSmi+u/82jtphgAVOGu70V4T1j6Ui
COrGYrOjsShfG0xavHzCaYTZabCODwz2dncV1hzdzYouTZZWbv5mNKJGLo46WbHOBf1lHgKSpHnL
oUtNaVoLZFeAHxwBE+dmsySK0UamPxtwv53iW7BgResEQQ1/lk64Ps1xXHh4rScJWAtGStuKeioO
LHGeJ3WEnVWD9WVTfyb1gymzm7yGpLuZ378A1xxLXINbNOovTKIcc2rjTIWyxcQkuUXCkgxJvZd7
dZ8PsBhWmc91KwZPaKjkCDvl1WuR20nKOIOCprsnsBCgRhqa481x7J1TAkPzIhc4SWxwCBtzWLqf
MO9wkfA9c/7m/5kFJZfll7fjUL/7y90fpQvlSlnrWlfvoEG8IqVk9w748MgNT2NpxfwjIWL2cYZo
c2/S6501cJ15q1MsUSjDvZuHJOWzIqvCvdLu8aQKjEVtIJjND+Et9CtR5aMMDrJ5tTitM0rGONWQ
lHozTk9pq/HPu6kP35yJvJOv032N7D3vt6jXoSIJJrQQv51oTvzmKfQIpeQqASGocn48CmwX5CUv
YNGnJN+2aNBh+ARdgqn0sjJK7eZG+Ajx0koMJYixhFPcvoc0Za9EvVck81nPBZAnDUtwJLEXcffh
yIvj2CyJU5PMGOmKdAC6siXB60ZieFtdd4koVFZqIgMV6kW4HFkXGOtd9YlE4F8CgdIiAvBAL2TO
4SLAd4uPaLsDGEACZc7HnydTDO5zvVCG8i9K1U7+bM050RI4q1R6DcH9qG+yy9yMiceq0sQGNFQC
GyhN9fxIYYEYxRUCXepHX75e0VygxKojuYfvi3QFWM1jNNOb50b9b9fnh9vHNxV4G/pYvqkC4SFL
V73TWABLQ1xA+4w/eL7z0TJgpM+T0d5BILYUkxAjRSramOOQA8ypbwoVM3UxEmBqcBJG+4KX2yPt
s1MWYbYnKWsh0jd5Aq3HLF0zPIaYB1UiRHFkG9284TKf+n6hkk/QiedJAJwxb3EVVoiLZX4RXF+B
LwRzQJ5QrlbS+9PXWbiW1L3XmdRYWo4BWIYDqajmuJhV02Ga3e1fIxHfSeoprIWCUkxO0hnq7Cdl
H8sy/F46lbvnaAJL3VblGuYEzOuXrPl9/aoeBFj4Oy/YXzcS14luPX76zfT4xNFrZDpWmLryRBcB
9+BoWQ1mSUnkq4yr1Pm4yLKeErAsjR1yk9sU9I6Qm2jb72FopJTWmcpfnvXBRPEJSILRFV8PXvMt
JA6dzTNNrEKBwBA9XSAoctXSXcmPTjn2NX7jXpYAPnAa469jSrB9090wVApq4WgTW7X480tIQEHz
9E278Cc7ZXOUw/0mhFAt7W4z7Tvo31E82upeSA0k/dEv+WG0tu1LZrR13vUP5ZXD0slMGSa9RG2n
j1F88x3BGPNKPHVfujliLiHaIMsweg8n3KZpVGOQAuvJNIZyzCs/fuLfxSHKqbLX/aJAbShp+pbr
Ya+bAc3GH0pjzXk28wztxNrBhuSO2jTHrD7o1ljpUilr2c597gE9KgoOta6oC1CvH0TB05aNVebz
/6gE5HgLc4KAnVDLkleL4RmVR4YVuokT5lOjrrD7x0TSth4tBvxa7OgL3oZ4w3msCnWv5/FGydSR
quo/Gib2vBjViF4rq68lMtDiuyR5YBeMXTP3pdcbeBlcVdYVNsVN2dTTlUxB3W5Eo5t02x4D16mG
RPsfRhf0PpqFxwH+fsFPKMcPPxkB+sxMNRgVmvdez6jMdjR3YAbiaC1IUFRmEqB+EgOS4u7eQQeG
g5y/K7t8/tNCDivc/rSCyxXrbTb/vg3EKJ1/cIeQjOqym2YpwtgBhp6EPV+CWn4dcEpkkUqwJG9w
4+ou+H6+x92Oag4TToRYSkLFrsN7SvMpjkKaFbRtj2XXirPvd6pnNwp63cror+mgQd+s2shTnvb8
ewSNT7w52XFsvCyn5hUfcV52D1YxUYjVsRhskBhb0Ruq0XK+jBpkcyXMuJX2lpCMNFUgi/BVXdsv
tFXx1DUjAVgBR0LuWoo9PP/Y3QzGbdsQbnZA47Mell4Z4etweuA27lRPsgMPIhMextiN/foWJ3S1
POfX1ZO9bAVxxXiFhhs4xGQTkvjmKSiJBfs7gjd58NiWij3TQ+wghSJ2WHsS9Im9ZTkCMuKDQBML
x6sSWFJfQ2X+idpzZL6VevMLZS76AFMTLUiRMbqLMmeL4039v0iHBS9yJWYMz0GYNBYeIrW6Nac3
YbLQYlorlUHgT0B4NUhlytb0rfqB9+pSrNO7Q0t4s44OlB0QC16vxkAJrMjlK/MZ40rRv+s2hLG8
lUmmyTYvkv58e/KAL2zOwd8HFSa/0m4rK2fZjMUOXjOPpU3sLTJmO+d/rqlHUBLev+v+mJ000W0q
uFgrMHRvlWO2TlXFF1NH7J1ESC/8NxOL/h0IT4pibin8rzfwkX4Oo50/rQioDdZRBj8KFGplj+8p
V/sMVTpzK57eLkQFViDPIIrPLmKQxMkh5fxzMoFaTdGgoUXvzP9WyiV124fkTNLLngljKGzVbyyK
Jn+H31ffWCrQjcmRyTMBZUxhDwEWMuUinuVvcd8Kyrpi/RyKG2NCx+4y8go2oavWM+R4OpKZ6BOh
nnADmbGaEHaN5TD8+SN4OzXG+A17y+r1Vl+zgqxTnfX3zSj9ho8JuoXVzVbs+jHEoNhqszbyopil
WqsNKSAAvm7XIi/4ioLqReTb6B7XTw3GrpkDMOu0qYGjsfezKOPT57o27XPMi4h2FqEO1eG3rJpp
9nECdvb0eWM2ZPMBfgbgmucC1uP/9RSl+kqsoyNwrjQYMz2lsfcttTqxQXLJBPvGECZ+d+SU/f6u
PIHsArnPYxhauk072krnwtLrfqWXDSAjUnRHtH/aLHpOFDXLDxYwwStQUWDXgEm4NzP++qmKzsL/
JTg42vP7km42ZA1o+TbVUWdk6F1KNY1C8eZnI3/dVyvsbk3k4kD3ZSgkgtGNAuuCZ6JBVMLSnwGy
PDCWBWCdu3fPtB67Q0wNCnkzJYlGUU+kSBRbzrXFEe/wIyIXoKChKEk4p6p5uFTv0CxNLquL+pPN
PbgPnu+01kinpxdtXDn6iEQPyi+k6Zy6Qla/rrhaOTobdpSsyPlKlx4L2CY+x2Cjj6sJCU1tr/aM
2KJKV//WQlYsQ6F7AUNR6g7pbxJGsZ4exI3Bn+BE9SiQuanDDFnQx+54zTyB+E2dmSam7UK4x8vH
rCRw8oEh/fkkSE9k5UrimFyTYJMhQ7tiv76eXo8sOz3QxQx9Tve30U0mSx8ZCHcu34523r4MVqXt
GOl+SIPHQBlYPcV73xMr8kUUZ0kpBXrTPdux3Ypg1iGH8umPKrJY8gEJYLYg+xyUnk3y0OxR4o6e
Yl7+9pLF6js49lJng/aUCmLgLYFK9FRLMG4fGqzLaXeI0cU3bBx7cjrlFNktGl2hspEJtO7dyzRd
Ny2var7qLb/aCUq/WjBIJel1AmCP8YA8U9qzA2oLkEitAD1ONQK7B+DgMz+tRoOajFu3iCVVt4E0
ioDqBFyP28kslOiTgowDthy33hT/WC1M5FRtyqJDe0q0hiRt2dh0Be3o8VjjzP0W8qhVkeJd1OUw
qhsMKIEg2dbJp/Sy1+tBI6eCIN2d50+GpKnF+64AFxLq40M/a5cFbsEcBNM/xZnltwCjysCth7ef
y5fnYQjKiQJb+8RN7WHtCyddNX/Ud62j1AeGZCCrNmfb/9QoNkCkjGbC0AptAiuBcZeyojvmny7A
4HO3gUegSkvrsxzWtdiqUXDwLlSDkYje8p6fnrcedGk2KDGQIRP7D+PtwmEJhgt0zeoWN2MX98y1
TQjCM7F29fMASecUfaJ70E7Eg7Yt3S9QELIutSp2w9jHHBpngz+2gV8CcKT124wm2iGuQD11kriv
13vR4S6kyAQxIuD3kucbb+KGWWT++ToCEn8yGYjV0x4buKFZPH1tTirwQyT+aP/bRMmBCvsm2wJD
lZD0AewDlYIWVOf3E9xmONG+/X1YJqgWyVXv6J0ZixRkgkiI7kTwFU1J16CfGxeEkprdG5HRFv+7
dIKB3CmwJmOtMl6sIBGy627jdugiL8tDrGanNcjBkoynRTXFCC2sHei5mMWb3CiahLFeTjWLcnVW
EMua/Cb4InPYryi+RfpTv6KuM4dkOM4zxJFhcQYMGoNCP/Ax4zqZskSxOPxM0oCN/Z4PVpf8fDiz
m6meDxLToImF9T1radgl3WNKb6xkxEh2+o5JY34CxfyqyKw+vGp/7lB0E+eogHf3Xtevj017NTNM
7I0KPEaCnVQdv88tfbDnsgShsjyzNhl2tMTtreRoqRNIMHmKIvla9sBlTvIR2RuTK65u2XyJCpDN
YDVpCxuBoP8aCb8ba0JJtTUb3uOlYPQNBYlaM0mLSnM9/4vMVUHqmS/QEzzBWsZH07l8VxiAsHN8
VPtMJ3//3eRUw5ye0a/CdYRJFX4tVefScadVxFouASA8SnHtSOWi6Dgrhwc1WPNvPNUIPYWA5/UJ
ygGhNX32ea1bbZNn7Wq3ZEajaLVe79L8zKQ2a7yLL7CBQp3fZeYMM92Pi1z5NOaRkrmyl2K3XaYo
3Rzve/XvCMi6AVxp+D3OBSBd6WIYDd9YDTIeXb+C9AU1rsTfgRQ+TAeoz7JNR4pcsSvw3ntwX64F
L29j3UZvc68rLSstYX9rGGCL+BzLju/jJZiTu2jTJVHhZr/aqVYaBDL6eG/fd7HNY8cVNiqNFcTu
Eaq4BmUSKU+uazTUyRL1Mwj+NUFaZn8kRsKF3NfebVw+AqR6HLH5G0hPAQAsIsb0t3/rlO58LsJu
jPKqvt9CYzjWsLog6RLcdZGkw2q0kRKECmKZc6dExPbSuT7ZIm7oSByUeMT2gGykZP0u1BSS2qMf
3mBmtqlovA4lhOiz0W2bbiM864nSsEX7oqJlNjPPxYCy+zUV6Yv6JbT1oZlke7VwX+js5XUC8yrv
EL67eNyZLMVRQsmRuyCNxZOhvhYI2r10MZEqRhUSQqt9DSlRK6+spj6YZ8GzGsSQ7CXYDlWKKBqz
+96pBI9anAFdjRSDi8ch49a5YuH5MhNdYajfcKtc+kRbvcdm5g36cli+LVShVNs9HvbsMB5+Ty0f
+K2vWuYOpOFl7Ux5f6Q5ns0f//37DKlg9GHg+Io8381o9de6Cminz151mov7JraRMMEiXTXW1UsG
3gm+Fw3d7fe9EfESX0pH3WBWy4FdmSVmxgR5err8+f7+XAn+8/vj/O/dPo0WvILJXViT6/N3L6ae
ReCAC1Ll7nHXBiHNAITdoEDrveeokttn2XI5glXeR0+hZUpZ9gEmmQWA2zd4L2D8NDYR5KU1glmH
bZ6GJsooqvhkuMtYLlsYzkotBXujDpin5bLX+DGsFqhulNco3eByWMl9a7dJvXx0qSN/ij+bwzJR
9khcXpWZhAXcdNzwQvhCTnZ0faXsk7sy8YcYLfU2pOhdsxEtdEMXgDzQ+tC9iVRJnw/SMe1ytb89
tzHTl+QwxJJKrnctcDybVSJ8rxs7MIDs5j/dEZgoxhxSSpjBHiUY2ppkqFeBVoen9QY15okcJ9jq
43dy7S9WnaHV51FZ7G1qmN5CCtv8ok8JLf4rNeNO51MXjLVJJua4T9NReeLK/moRjiKjo7F0MA9p
Z0m/O9MY0xHpsnJEhPPDVIpBwo7l43vzqvgaTJc0j6QvDNTkZVvghW+kwD6N1//Zu8DpKWcqDomM
pnBGCoMt5Hrk+iA/4hWYelHaD6DEcu5aLkoEaf8gAcZ1jgLYPwkOXiZ5ANUzN3Wl7Li2YFPFu2PK
vzdlna0o8bRjUbq87k33GbzKXqomS1Zc0XsgWwlsVJwir59YU1M6ZOO66wXqPQ8vsQeslMVLFo8x
nEfDow9ybfyrIhH90Q6845nOgOCEIt/SQGPBR4xUfAtfab5Ix+dgtJpCfUZxiI9ogG0yNjwazvN5
hzb6jM2n2n4qH86xemL+mMvAAAVNHonWvJqNImBF/QXW7WpJawH+3lalZoA7XsuY9sfBw6lHT7Gh
LU1omAh7yCLypirMdEVtTay3k5epiCj+Nvh41zB/+/yLA0OIh//cHP8dqRsDEQ6s+i6OCVrqNNQI
OZLCsyqzVAQWfjJZeXDWJdIjUQaps7NGqP8nriKg1pcRSKaU370v+JRPqulhJNlrGnrq2OGiQnvQ
URvp9wTTk2tdszowQgEDoAmc2juMlXgqKDzVLii+sgv4SR325tfaLdLYzeYjwSIVlyKJGFxqxkfK
eGlosoKuZtCuAtp5aq2Jl9CppLb/g/jE1hOq+VFwKw6Q/BkC31ZMVOc+Ufsx+INnyrc/jYXgt90Z
bShTPgPmUh4RDQXevvaw2evR4CFRqYlsk9mAlvmI/pAbqOjYyX8t0H8dvJgibmSsqeOMTKNe2s+a
M8UTXlomh63pFlbfeBm+bjurDRq1fkIdR4+T1S3Zphc+ZmVgDEuvh7HXJjHF9wEXOMNSQQ+Bl8qQ
unYOIu4YboytfvOG5ReyG919cF0UNXQY0mwG3/nHNzxRyNDipLU/FzcAXpQsrNavzLtNRUwn9EcT
MpjBf6F5BrMYpYIPZBWkz8m/PGZKNXTfG84rsJqrlb4W6GfiyC6gh3uaQTOuw3YoiXcLF7REsiJp
EgNugU99XUwvKFa+7kFaRA9gInaKIKzB1/IfZ+t4rPOo8qHQBmoA1jBbIO9THbg5BGRUuf78ujjw
82rrkjWCykziJDSpeL41OarfFwCALxPzdDHE3+SxTw596sTjhkvTtdRoqhZinVY/EZQJB/rbDgTv
Wr2i3PQ+Z9Q7IUkxjovat1yj6T2U/84bu29kA2TwFuJxoEGjzCMW+0A5iA2z+VCTXrUHBziE55/V
RqxC+H5+Q3jSf1NYIN+8udbeXbmOPQdrrzZ2JVSvj36L6I0xx+dKe78rUrqk2BGXXNol589VYP4+
enZB6dTDEQ2WAmeIVd6b10DclCGzUJQPO+Nx42HSVbpP6cnTrRzjNh1aIe/1M2I/CrIh9o6HZgXN
6K5DYzR1nLigv5tfI4jPBeUIYj23Jz4wYZe75yckadyj/4SeJH43L0w1m8Kvc14=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
agqEJQkmewFCXHSVPn1cTFukw9jsPnAZXHaWLPFuwgR0UcR/vvLcbx7vWPF349Nx8Y8mfv6fbDj2
GO+xKUtQag==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
iEzXIY8dlehLk2ui2MGeS2mZU9X/4SY2u/QlOajOVvhSX6FdPYZF2RY74hxJ3VAKvDcs2IvNU5yw
Txesjym2m1RAxoYFfgqAYB20HHCGfw/yJg0B+eNljX/IJSEgTRGsc8cBaU5R+sDVVjILddzexLma
kzFR4F8cp9Rr1dgUI1w=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
fZOY2COHmP8B3Uf/UtDLITmeyaFSVbm7mD3CpQYunQhM19vFYNVdiueZqK0F/C2tHwtnxKcUcWJr
T/xwusWtGDYDkGd7TD0dT0WBlMEi4W9WF/8Cqd9ufFvrigyeDIc0sXiB9ub8YQMjkc0gQ8KEM0FH
gxQIdSQVbS8TgNZI5NzGu6B4Xs20yQ2fXVViz3B4klOVrC/EoVLsG+xni85uwaZmoXzRtHBuxeyZ
dQ/4+RsukSucBB99rLyOHvmnBbugNfnuOskGB9Yu8h6MU/iZGNtEyCxj0bOxRcUrhBRDwdQ9fc9P
nK9I/1NPbvPsNKnFimD/iUjcPPI6HzxwFarZlQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
aLA/4xNQENA3IXJPNw1LySyNrAnA7FHhfjoK2YsJV499eH6p3fQlh9EyLQcma16Wj7k9SJBCSwt1
ylIYfoxoPGpFUdGNH1lkVrqjsUwtYIe+2kq4PVwXI6Sbyte30dUPg7RfdHvlvQDm1ir1VDGA4Mjh
vCCxKzEXk+eb65dOWrQ=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OoJJ/ZsCWiAeDh0F4uvmYC6tiHl2QWBCwrtW2LvFf8CVu4ZLYU7wvaf262Q6dcCmSG8YDJJbN2q0
zinUgcX6s7pRL2QtSTRRJif3HWp+s1aw2PFT6j2SbwOBKRLA9ecRFZvG46lZZJC+CFrQmZUMfWFb
Yef5QACDI1hQ2UjdogMi6RZnWu9AOYCI3G0twT7h3lwKGbERh4suOvAlxEvFQsbcYUHONdlGNao4
7JjWc3XXk+XZK7EjiIOSGPaYWwxTLLN0K8dYm9yLOWbOtl+toMzZL3HtWIkgyZHQLCUYkOSkioEz
WGokz8LZvj7rmIRYWMQH7DW00ZsAIRNZNm56Sg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10592)
`protect data_block
F4ULIPQlNZxTyCiE1UgKI5NdoMFv1mUlM2NvuWYhUBfXuWL33/h+Jaybc1XQqcsGyelqtDpbO6cr
BLb6RK8hYZZ98wmnHpNlw2fx+F/Vx7rnAmqQvs0xB2OAAh1QcfasxEq+cu2bPyT8oMBVaUg2wjun
od78+BSUBlVi7/kFRtffA/qTpSua8E1W3/3C19MkBgt5UN7MyXFqk1ZiJnMq6NCo0FKFlDgvB/uN
dCZk7RxDKAJSMS/ccpwAj6FWepP1F5I1n/0KCsdN0YJWw/fKLrxQcrTR0I1DP1lLOwW1sFOLEKQ4
fo3r4fyCkNAEAEeMzSWAtznUBzyUehQznT/hyQGm3D8PTLTlTgHaX0Z/P6o0ndwv6zYeW8wmHLdq
yGcpm+0aL66TXyEOvnSPqbc/FLCuar0myTKPC2l4q8ZHFIvvfddLvkQ9NMtjR3R2r6m8Ke2/rPHU
o9wjtbWtiEe8mx3j7M3iy6NjnxewylR8p2LECnu+Sn1And+T1CnodxZhpaJ5QctW/JgpSIIBCMxG
Cku0PYfR50+lEE/xhyV9AANHEUnxHeGNBxaKwnWYfKOzxm8VaCYrLAtngWZivOjtwllASOQAc9J+
MWmrxKBtm2H4HYuOjGGr0CbtOXc6OqjbrmmwXfaMlNOTPxn5tCDaQJm1VlbZrMlyrSW4iJNPMnfF
3ZPlZX+EelEXNTfKypJp+jUGodK8lchszEBzBn+vxERBNPKNP+PlsPSzupA40E3V4qfIXlo8CKng
zoIOKlbMH2MGqNxn3uzfcRQl9vbAzax77p895UAfpfws9OQ4Iq34IyDruCWQnNs2VYww7tha2G5O
I4I27UcVo0yRic6lxHoNlt9qe1+w7C7Gl3KVZJT0zicviPEXCRN64bGdXOcnhS54Rw+oXEUIKf2x
eKkdRDdQ2mdmNCbz/nSiYic9vtWhQnGzbzj9Z5juLq2rbs6Skt3xGpeDSEXK0XNcVOSnnfQPEChu
ELY+8VT1vFDSVGuSQa1cfpJdVobdT3gtC+ZyhqSYm2Q2B7F3Z84zaK3HNOx6Mn1nYV1zLN2EhLPi
RJqymWTTX7Xk2gxFIKa+qBdcZT1D9Ovts7PpHcszRUGWMvdFVvgubr9TrSgKO3P3AVOHxG7jZaht
G25S7ES5rM6CucUqwKFaEYDY1NYKN07QRep7nbIldRHo1NIRJQfH7Qet7VzXjx2OK4YYYAXjreG/
ZwJC9Fk85r7ei4aOz3rUefLQJ/c5QrwxfrpEHtOt04Hqmqk6jcM3fpRaPBHkHU1wi46L9xf7QJl+
qQjlN//UknrsLnPOPMNMOzIcgltGCPgkcvV4ow49ZoHVOGRcNIUsrh39jCRHbf2Wb7xv8Gj0ELpA
SnluW+DMFQTyDCrlC4LP/kthQ+HcJRnrQvzIwjEr3IXl+pvodsy8ts1Cu6By+/xPGLf/JE+kJmAu
4lJvCeL2iwJ+uTcV+hAFYsN5JAeV/M+UaJO0c+5oELRZ6/d2z+S5QwqBTxLNpwxqcxE1nY2y6gjt
sb1wnvgKwLkV5qgph3Pgu+LQ3FGiydEUxASZ2VPfBlVKbObDsYDo3FRKJk+gDQ0VEIaf7OhfEImu
0kjzxCWvqiNIevvlMpPRfy+t/PVnW/a/g5R8iKl/qoqStwKAELWsSPKZQrajQnCgb4TW7SYpJvUS
H1668G8mpVXBVd55lS0Lmy3d/LLKf8tLsI8RxwRIZzLKsxG9f160MuPEWdaMAXXHnDb6NMpExnG6
XbE+SRn6gzYOPfwuLXIajut6Wft8UGJaP+thsH4Rzv0XNSbhcS5evzQ4ygr1NNzYtexYC2srBweT
2BQqqGhJrTsQBrQXhLTpDqw92eIV2ytEvdnYqgyPBgWiB5fNqY0erbJ0redfiWEeVkSo71B3N0JX
cPtdBg65PZgCSBVS5Iq82Gezg2jF9pmqefcI15+9bqNeB/f1Cg5ESD6j0/Qbh2EPCHKkUmMAGdtA
qkzqZm2vfqYLhlYTvSu0bjwI32RSTjW8fSUd4FQW+RWFkYm+miMKO8cBG7j4j8VMEeKL7mQ1qHiJ
AowRRAYtBhgLOFUjPUfq/wUjHP7xxWJn5FMRP0aPytRySuWw4XL1cOQx9WI94q+bNobeKH2FC7kf
6b7obeMo5LqDwo//AOwzW4d37z81KiCVYhvMx1++C/Omendx6MS1qiYiBw/1tILnSWlti+5mONfF
3sLuEwZNgsrZ7/yswIR5IX+/FL9iup99s2rNFALKEMTd6T95lCukwmX6ORrS1Nh+bXBI184/hGmy
fK8hdT870Pzq9sgGgq8IiMo6rH6v0nf3aXbieENH6bJ4yFoecqDE7OvjTwsu2bdhtMNaAfJz5w8p
egSTP1sU/m9Yd3yu8HczBuwAAPiPRPnobkwpDFum33LCkrgwVYA+DlJvrsFwuXqGMNooXSXvJiOZ
ZH1F8A2+qS5cDesCFQrNaPrehNBh4uhuqE6oz+ij3wtnTR7WW63vJBV8IprMwaflusyD6y+1+eGU
3cHU01DiWhOjVC3mmg92HQoAGiUmUULKzgvderQzpUbYVHX8LCV9z4+A4LCXC5BrJMKyS4N7IhMI
o9Jo/ZqonaQmcE5fnLyMcqkjxaiNAm2DIfnfS+5qg8km+KEAMWmEHtiSZX0GXAqD8XTQZ6MTQw+D
WGYBV50iW090kyDxALQ4c53MCh8+fVH0AogoRRZnQouQaEGpScmjjekCcmHtXDFsMGycMbeGMiPH
G3xLOK6oCgyDUCkl6hxz1XguLtLvbfvKnpUXHVhNOJVuUQOcCZDuEubYb4LYKnQWn2f/jb9vlfCc
I2FN8YTvP6UgzllYscBJayB1QWv5iyhxkuDHaoQxj1hoUD8hpQiz34Awia/nGv0ms1p8obhcdC5j
De0NiHWPXejY52Q/Fdf6G+Nxs+9/KHX4/vfTRUkNhIqzWyjv5Yp4Kohlxa27oUF9qDMHRBtg1MyE
4IpXkuk/+KSzcqTQS9O0bgq6QPYmdlB2DgupRcXzfKaBl8FftuXqyHqf0rKQ7LeIVKpBQw0pi62n
a1HgHw8cTpkhMHASqvXSx4VdenjDt6x7l+cBhKiYzbx6hDIJGLkzqxUnvP5aWNFCi6CTgrYcAeob
yFQYtMlo1kb7/2PZwUI5XGEDGInkxw5ZTXg3LYEcdcyLGMRacdskjcOs2S0JKwKaz8kG2WZEsjF0
95X0oFcWEnNIyR9sB7sO2RyU5H8mJx8s4jzz0XSGDguaDpsE6+rUWGfdAxAuIdGjgoaqU8zqvic6
joX/XPrEWnOeP/64f3ydin0Y5B/U9VhNyuaVYepJqwyjcrv3Z0lCOZNVUDDV6IR6Jb9wO9GKA6ib
dXiUltDMA3mUhpZueLHaa7HRKKq/MLdTATSLmL3nRhszafQwrx0B/WGWVaMyyebNiRUJS1F34mma
SX4Dl3E1AkbYiIlt8bpRL2LLJxP1+Gp1Sg28OUt3ahwd8iAXM/10N4KSRJsDLahSTcsUyvc7JiAS
eq8FnPS2hprq/I/DoetLIY1IuZkQYFAgY58gvNoFK2dlj6xA3JRheXVki9O3Cf1+kF79Y42lJ68K
l45ipuj1fje5xf6hK8jBixQjlrkfo7KYF2XMczsIBiPj9HUaRdfRQaU+Zn6OTHuBbiBOXpCTRVII
aSQPCrNtqXeEgDMnEAWLz11B5IW0QcCntqVQVUjB/XfDs8zVegiHKALVaIqVhZuUhYAc/keRAD9b
K3qZcrcqT1SiITk331lEocjHpKtvOwzZlWIVNsD5fDuKQTSktb1W4L2Fb64mU7FGE57rlJC76Wyk
zrTwzT7t4BlJIVS+ognN2qtKqTT2je8Zluw3jPHrPUQx4maSe8jcdnWsFWBacddbhVShuEh5oX3m
WjWF/2BGSERpOpqCoZxbcSX0f+ImGGfzTmaPuVwlYI+Jzlufbp10S0NA+KK0KPsAjpCk45/HzZ1F
gg9ht30v4VNqGRrDBTWC3+rfj+MuSEHX1ckdCtVuaGhR4l3JYmbAZVVuuGSkigRhL8buPR9lyq3O
KFcjAnK1mC4W1Snlq2GtmX3qGMhHviSd49mm+3Rhy9zy8dXrRoKkV/M+waf0X5MwcvTePYNv/2A7
FV/Q0vA0HmStDdax/27CfqGcS/M69Kaf9X1sc703uF+qB/qGJ9oLy/13Qafa/EAmVN7G5chxMi+K
s+4+Z/E/xR5nAfsbqo5JxE56+5psGWew8D1xW7qSm0PqTGTKUExhEaBx8kRXVkEZGhhfC6VhVOGg
Tf3aBS2tL/dfG9zDXDd0d37cXN0KwzCRT8tvCTLuC+1nz9pxNS1/6mGfXXXBST1JR7wj3ZdXozg1
EE7P6mvcNoPZb2Eb333iLVUJhtE3/fJHVty3rguw+b6PtNO6zyUkjLB5CsRRmxgOxH3sLPRXToB3
wRKUU3VRZryMWvC+zylSkqeOgeUdXv2wW7GzFEHyp2JtHC9oVevd6meh1O9OMBHBPRBlbpgvaVqB
5dHVOHtSO9yktc0iz0qar62vSE7mg4BF+WKBmMTi/M4OUNND6hO2TrT7WypvABpJ1DHmz6ZFfPH1
2sWkPMKgPARTiY+1jZxkY56myHSAqOfQ3YTUuKjaC/7Ou2SxIAS/ljK30byjekbAYemkqXD9tqXo
mzbTg4zV/BGMHfb8ewl+MRXpzXIWoFt7eqIff/sX8Q+G/Hp+/sNBXm98Ii0TUnaNNYE71Cy74YjY
2OAfkBy8I+zK+Rtr9/urBWEZbhbvXReXV4rjLrc5sR5wBTjBs3P5081j2z21NQ/Hl5lv1MPvL4Zv
3gvlZc2HF6dSDEbuTnOtGDbHP9CNBljnG1L2Nwi8vgjZzyUoGllv/p3Qx+SxXLwOImuHFgXRgBmb
wnF+bY+9v12khY3RjSSQE9GTaHRVeUL0YgPM3i0bMKAlH/OZcYqgWXulxVRCOin55f8P4QGSVe8i
sL1Wola9vHLJYil/O/wt6lWM82/JXO4q5u/qtYmgrQnl4p01r/hfFmyXa1RzjYoct+A1YazDvuJP
aYMAidZjJsHiRDcDsdZqyAgWrP9wOv/Hp8z3qzjhtCLjQjwPsA86GiJtLz5mx2MyJUQuFi3e/n+3
FcgtMUgy9sjVJVb2HEvgcikOqfJYrvvUmMp6bo/UGRDnTjtdca6ocuGwTncfRyRXVExTB9h0MKEn
UL5g2G0hMQBmL94pZljbKIfLlvr9Sz1kj2b3wMWMaY8h2KHkltVcwQVZRN3AJ02BegBFTbRHpQhK
hjaTiYquxoEiyTbF0Kg0K/t0LhjNijtTdl5IhCwY+AGAaPkFY26yMDv5soXc2kUZwxBNMOJYxpTW
o3Du9ioEZqAFa2C++PXd3RVJvX5gSOhQqMtBPXByG54pn/wMPLXEFjQj3W4A9paUIVr/4lowlulv
J1wrlOcmva1BATXQq1rcsoHKL63cvTD3W8FuO8s8xMgLid39AEQdKz7Zw/JFDD0ltVlMTThsy8NZ
nnNhOeVE8xs2LWA5pAq1Lj0d0w/FnUSjmB8SgHi4/o2Apo/alVUNuK7M+6HFGhMivz5eCtVx1eqd
rhA81snacXGzSMW7/58zsM2MkyafjdFsypMRedNrIe34Zr1mFJdgq5bBkrjjrhYX3wrBnh4WGf84
lgjWtwGrJOEeIWlnWHZLTX2ZlYIrqIFuvGkSFCDZOdN+b/Pk0nPl72wxQCuMLOifdKz8t4IGhxHd
gzELBFTSGAHDfw5c4CYDP4os8CnZ1Mi7i2XKOeyohQ3at5I6ABdssRrjCNh3jxpp5Sh7i2dPce9y
6aXLE7BA2lFJc/uaOJ7nF6DcnFsTLVPlnCDNAXJruryC5XTIi5GClZ8cua88NE+aqRs/CIsk72o2
aC4aWUReGN3mYoWJdb01dbt1EpECpMyl5NX5W3C+xhllOQ4l91m8h0sF9tRQYpJsKYT/A/w0rx6d
5fbgaeZm3KlmMac5kkJLYZC1pl8ujTPkHZCA9IrvPfSz6sKEQH5jzkbpSHKEBdTdFL/k0mSdFAIQ
H/9T2MKeqULu6VVYforM1FkxWe2VGaY3Cs2/CnHsnciX/WSJ3H7aXO2ESTQMzCGLULxFKIi467m1
Wd/G6ButAVpit4/RKXVVy/F9CLISmco8LPJzr2fadeqnLmZ6sON65OIhZ2RF2/dkWHFL8AtwcumE
f0qAkT2ogxcCpm7yXJa1f1+9Qody97kOes7YER3esXzGlm0dNxMrvZdLQ5/GEk4jKi7Ca6K4pQCL
dsZIJN4xtrpTvGg7FlUw9J16HRPVUSZ/QT/OFacAvL+lwdavSlNghSDxQ5WcOtKhK91w6pSksMGw
8IGPo/2uwYPdjYPIStltc5FbYjL5MC615rCyYCLAGHzLsRW/TqJix45qmdxodPk5ipDvOFex5eel
kn3KWIojC35lcX+hoFj/LamK32kKJ42KNtQ0rqFWYz3rhMUD3Sg8oz9LCBzQLngCmiw1CPTX7HZG
ZmlZB0M1IFEa60MV5BYfUeosHF6j8+K8yIgCJXXRs+5d3mF8ioDCEKiuafLtAm+GF7JkFS62td6W
kx3yo0Y3QtPRc0kBqZMDCCooy1mQjEgEv5/UaqvOhIWZFaP6/l/iGKTuIVc5TySXe/b4fOV5Gj/M
7sqNBHOkVnAJsBWnGnku12X0cD4NQBWZYG2t3DGhZPTFJvA/atrvbC9zh8eTi5m+EMMPsYEVgrlP
2ZqEr42MxwKRV9PJUFuJYX7LTugyCRbSkjMUcHaYO3/KemXtK3z5HceAdmHCSi6YVumr1zpgFJtY
UtY6ZenwYb2VmaEkAv7faaudNpEM43YIiBsJx3Ke4uwxdQSZOT35c9pG0FByqgYNfooSwMVdoL1y
xnULt/uFSPeQswqDkpFz2MNm7hKnhDvTnBL1bJaNUfHt0KzZj7yELvTcvGj4wKK8kMpe74uJey+Z
CI+IjhEkUUkQnnsMQsoi0t+E21REAy3jL3FErflCy+Etu5KCINByFvbQYapLIpLxwYEFPbngp2l+
B7/nkWHMBCa9G2yJVA/Sg1sVyCCDTqGGijfRh0IV08DqRhuUSmi+u/82jtphgAVOGu70V4T1j6Ui
COrGYrOjsShfG0xavHzCaYTZabCODwz2dncV1hzdzYouTZZWbv5mNKJGLo46WbHOBf1lHgKSpHnL
oUtNaVoLZFeAHxwBE+dmsySK0UamPxtwv53iW7BgResEQQ1/lk64Ps1xXHh4rScJWAtGStuKeioO
LHGeJ3WEnVWD9WVTfyb1gymzm7yGpLuZ378A1xxLXINbNOovTKIcc2rjTIWyxcQkuUXCkgxJvZd7
dZ8PsBhWmc91KwZPaKjkCDvl1WuR20nKOIOCprsnsBCgRhqa481x7J1TAkPzIhc4SWxwCBtzWLqf
MO9wkfA9c/7m/5kFJZfll7fjUL/7y90fpQvlSlnrWlfvoEG8IqVk9w748MgNT2NpxfwjIWL2cYZo
c2/S6501cJ15q1MsUSjDvZuHJOWzIqvCvdLu8aQKjEVtIJjND+Et9CtR5aMMDrJ5tTitM0rGONWQ
lHozTk9pq/HPu6kP35yJvJOv032N7D3vt6jXoSIJJrQQv51oTvzmKfQIpeQqASGocn48CmwX5CUv
YNGnJN+2aNBh+ARdgqn0sjJK7eZG+Ajx0koMJYixhFPcvoc0Za9EvVck81nPBZAnDUtwJLEXcffh
yIvj2CyJU5PMGOmKdAC6siXB60ZieFtdd4koVFZqIgMV6kW4HFkXGOtd9YlE4F8CgdIiAvBAL2TO
4SLAd4uPaLsDGEACZc7HnydTDO5zvVCG8i9K1U7+bM050RI4q1R6DcH9qG+yy9yMiceq0sQGNFQC
GyhN9fxIYYEYxRUCXepHX75e0VygxKojuYfvi3QFWM1jNNOb50b9b9fnh9vHNxV4G/pYvqkC4SFL
V73TWABLQ1xA+4w/eL7z0TJgpM+T0d5BILYUkxAjRSramOOQA8ypbwoVM3UxEmBqcBJG+4KX2yPt
s1MWYbYnKWsh0jd5Aq3HLF0zPIaYB1UiRHFkG9284TKf+n6hkk/QiedJAJwxb3EVVoiLZX4RXF+B
LwRzQJ5QrlbS+9PXWbiW1L3XmdRYWo4BWIYDqajmuJhV02Ga3e1fIxHfSeoprIWCUkxO0hnq7Cdl
H8sy/F46lbvnaAJL3VblGuYEzOuXrPl9/aoeBFj4Oy/YXzcS14luPX76zfT4xNFrZDpWmLryRBcB
9+BoWQ1mSUnkq4yr1Pm4yLKeErAsjR1yk9sU9I6Qm2jb72FopJTWmcpfnvXBRPEJSILRFV8PXvMt
JA6dzTNNrEKBwBA9XSAoctXSXcmPTjn2NX7jXpYAPnAa469jSrB9090wVApq4WgTW7X480tIQEHz
9E278Cc7ZXOUw/0mhFAt7W4z7Tvo31E82upeSA0k/dEv+WG0tu1LZrR13vUP5ZXD0slMGSa9RG2n
j1F88x3BGPNKPHVfujliLiHaIMsweg8n3KZpVGOQAuvJNIZyzCs/fuLfxSHKqbLX/aJAbShp+pbr
Ya+bAc3GH0pjzXk28wztxNrBhuSO2jTHrD7o1ljpUilr2c597gE9KgoOta6oC1CvH0TB05aNVebz
/6gE5HgLc4KAnVDLkleL4RmVR4YVuokT5lOjrrD7x0TSth4tBvxa7OgL3oZ4w3msCnWv5/FGydSR
quo/Gib2vBjViF4rq68lMtDiuyR5YBeMXTP3pdcbeBlcVdYVNsVN2dTTlUxB3W5Eo5t02x4D16mG
RPsfRhf0PpqFxwH+fsFPKMcPPxkB+sxMNRgVmvdez6jMdjR3YAbiaC1IUFRmEqB+EgOS4u7eQQeG
g5y/K7t8/tNCDivc/rSCyxXrbTb/vg3EKJ1/cIeQjOqym2YpwtgBhp6EPV+CWn4dcEpkkUqwJG9w
4+ou+H6+x92Oag4TToRYSkLFrsN7SvMpjkKaFbRtj2XXirPvd6pnNwp63cror+mgQd+s2shTnvb8
ewSNT7w52XFsvCyn5hUfcV52D1YxUYjVsRhskBhb0Ruq0XK+jBpkcyXMuJX2lpCMNFUgi/BVXdsv
tFXx1DUjAVgBR0LuWoo9PP/Y3QzGbdsQbnZA47Mell4Z4etweuA27lRPsgMPIhMextiN/foWJ3S1
POfX1ZO9bAVxxXiFhhs4xGQTkvjmKSiJBfs7gjd58NiWij3TQ+wghSJ2WHsS9Im9ZTkCMuKDQBML
x6sSWFJfQ2X+idpzZL6VevMLZS76AFMTLUiRMbqLMmeL4039v0iHBS9yJWYMz0GYNBYeIrW6Nac3
YbLQYlorlUHgT0B4NUhlytb0rfqB9+pSrNO7Q0t4s44OlB0QC16vxkAJrMjlK/MZ40rRv+s2hLG8
lUmmyTYvkv58e/KAL2zOwd8HFSa/0m4rK2fZjMUOXjOPpU3sLTJmO+d/rqlHUBLev+v+mJ000W0q
uFgrMHRvlWO2TlXFF1NH7J1ESC/8NxOL/h0IT4pibin8rzfwkX4Oo50/rQioDdZRBj8KFGplj+8p
V/sMVTpzK57eLkQFViDPIIrPLmKQxMkh5fxzMoFaTdGgoUXvzP9WyiV124fkTNLLngljKGzVbyyK
Jn+H31ffWCrQjcmRyTMBZUxhDwEWMuUinuVvcd8Kyrpi/RyKG2NCx+4y8go2oavWM+R4OpKZ6BOh
nnADmbGaEHaN5TD8+SN4OzXG+A17y+r1Vl+zgqxTnfX3zSj9ho8JuoXVzVbs+jHEoNhqszbyopil
WqsNKSAAvm7XIi/4ioLqReTb6B7XTw3GrpkDMOu0qYGjsfezKOPT57o27XPMi4h2FqEO1eG3rJpp
9nECdvb0eWM2ZPMBfgbgmucC1uP/9RSl+kqsoyNwrjQYMz2lsfcttTqxQXLJBPvGECZ+d+SU/f6u
PIHsArnPYxhauk072krnwtLrfqWXDSAjUnRHtH/aLHpOFDXLDxYwwStQUWDXgEm4NzP++qmKzsL/
JTg42vP7km42ZA1o+TbVUWdk6F1KNY1C8eZnI3/dVyvsbk3k4kD3ZSgkgtGNAuuCZ6JBVMLSnwGy
PDCWBWCdu3fPtB67Q0wNCnkzJYlGUU+kSBRbzrXFEe/wIyIXoKChKEk4p6p5uFTv0CxNLquL+pPN
PbgPnu+01kinpxdtXDn6iEQPyi+k6Zy6Qla/rrhaOTobdpSsyPlKlx4L2CY+x2Cjj6sJCU1tr/aM
2KJKV//WQlYsQ6F7AUNR6g7pbxJGsZ4exI3Bn+BE9SiQuanDDFnQx+54zTyB+E2dmSam7UK4x8vH
rCRw8oEh/fkkSE9k5UrimFyTYJMhQ7tiv76eXo8sOz3QxQx9Tve30U0mSx8ZCHcu34523r4MVqXt
GOl+SIPHQBlYPcV73xMr8kUUZ0kpBXrTPdux3Ypg1iGH8umPKrJY8gEJYLYg+xyUnk3y0OxR4o6e
Yl7+9pLF6js49lJng/aUCmLgLYFK9FRLMG4fGqzLaXeI0cU3bBx7cjrlFNktGl2hspEJtO7dyzRd
Ny2var7qLb/aCUq/WjBIJel1AmCP8YA8U9qzA2oLkEitAD1ONQK7B+DgMz+tRoOajFu3iCVVt4E0
ioDqBFyP28kslOiTgowDthy33hT/WC1M5FRtyqJDe0q0hiRt2dh0Be3o8VjjzP0W8qhVkeJd1OUw
qhsMKIEg2dbJp/Sy1+tBI6eCIN2d50+GpKnF+64AFxLq40M/a5cFbsEcBNM/xZnltwCjysCth7ef
y5fnYQjKiQJb+8RN7WHtCyddNX/Ud62j1AeGZCCrNmfb/9QoNkCkjGbC0AptAiuBcZeyojvmny7A
4HO3gUegSkvrsxzWtdiqUXDwLlSDkYje8p6fnrcedGk2KDGQIRP7D+PtwmEJhgt0zeoWN2MX98y1
TQjCM7F29fMASecUfaJ70E7Eg7Yt3S9QELIutSp2w9jHHBpngz+2gV8CcKT124wm2iGuQD11kriv
13vR4S6kyAQxIuD3kucbb+KGWWT++ToCEn8yGYjV0x4buKFZPH1tTirwQyT+aP/bRMmBCvsm2wJD
lZD0AewDlYIWVOf3E9xmONG+/X1YJqgWyVXv6J0ZixRkgkiI7kTwFU1J16CfGxeEkprdG5HRFv+7
dIKB3CmwJmOtMl6sIBGy627jdugiL8tDrGanNcjBkoynRTXFCC2sHei5mMWb3CiahLFeTjWLcnVW
EMua/Cb4InPYryi+RfpTv6KuM4dkOM4zxJFhcQYMGoNCP/Ax4zqZskSxOPxM0oCN/Z4PVpf8fDiz
m6meDxLToImF9T1radgl3WNKb6xkxEh2+o5JY34CxfyqyKw+vGp/7lB0E+eogHf3Xtevj017NTNM
7I0KPEaCnVQdv88tfbDnsgShsjyzNhl2tMTtreRoqRNIMHmKIvla9sBlTvIR2RuTK65u2XyJCpDN
YDVpCxuBoP8aCb8ba0JJtTUb3uOlYPQNBYlaM0mLSnM9/4vMVUHqmS/QEzzBWsZH07l8VxiAsHN8
VPtMJ3//3eRUw5ye0a/CdYRJFX4tVefScadVxFouASA8SnHtSOWi6Dgrhwc1WPNvPNUIPYWA5/UJ
ygGhNX32ea1bbZNn7Wq3ZEajaLVe79L8zKQ2a7yLL7CBQp3fZeYMM92Pi1z5NOaRkrmyl2K3XaYo
3Rzve/XvCMi6AVxp+D3OBSBd6WIYDd9YDTIeXb+C9AU1rsTfgRQ+TAeoz7JNR4pcsSvw3ntwX64F
L29j3UZvc68rLSstYX9rGGCL+BzLju/jJZiTu2jTJVHhZr/aqVYaBDL6eG/fd7HNY8cVNiqNFcTu
Eaq4BmUSKU+uazTUyRL1Mwj+NUFaZn8kRsKF3NfebVw+AqR6HLH5G0hPAQAsIsb0t3/rlO58LsJu
jPKqvt9CYzjWsLog6RLcdZGkw2q0kRKECmKZc6dExPbSuT7ZIm7oSByUeMT2gGykZP0u1BSS2qMf
3mBmtqlovA4lhOiz0W2bbiM864nSsEX7oqJlNjPPxYCy+zUV6Yv6JbT1oZlke7VwX+js5XUC8yrv
EL67eNyZLMVRQsmRuyCNxZOhvhYI2r10MZEqRhUSQqt9DSlRK6+spj6YZ8GzGsSQ7CXYDlWKKBqz
+96pBI9anAFdjRSDi8ch49a5YuH5MhNdYajfcKtc+kRbvcdm5g36cli+LVShVNs9HvbsMB5+Ty0f
+K2vWuYOpOFl7Ux5f6Q5ns0f//37DKlg9GHg+Io8381o9de6Cminz151mov7JraRMMEiXTXW1UsG
3gm+Fw3d7fe9EfESX0pH3WBWy4FdmSVmxgR5err8+f7+XAn+8/vj/O/dPo0WvILJXViT6/N3L6ae
ReCAC1Ll7nHXBiHNAITdoEDrveeokttn2XI5glXeR0+hZUpZ9gEmmQWA2zd4L2D8NDYR5KU1glmH
bZ6GJsooqvhkuMtYLlsYzkotBXujDpin5bLX+DGsFqhulNco3eByWMl9a7dJvXx0qSN/ij+bwzJR
9khcXpWZhAXcdNzwQvhCTnZ0faXsk7sy8YcYLfU2pOhdsxEtdEMXgDzQ+tC9iVRJnw/SMe1ytb89
tzHTl+QwxJJKrnctcDybVSJ8rxs7MIDs5j/dEZgoxhxSSpjBHiUY2ppkqFeBVoen9QY15okcJ9jq
43dy7S9WnaHV51FZ7G1qmN5CCtv8ok8JLf4rNeNO51MXjLVJJua4T9NReeLK/moRjiKjo7F0MA9p
Z0m/O9MY0xHpsnJEhPPDVIpBwo7l43vzqvgaTJc0j6QvDNTkZVvghW+kwD6N1//Zu8DpKWcqDomM
pnBGCoMt5Hrk+iA/4hWYelHaD6DEcu5aLkoEaf8gAcZ1jgLYPwkOXiZ5ANUzN3Wl7Li2YFPFu2PK
vzdlna0o8bRjUbq87k33GbzKXqomS1Zc0XsgWwlsVJwir59YU1M6ZOO66wXqPQ8vsQeslMVLFo8x
nEfDow9ybfyrIhH90Q6845nOgOCEIt/SQGPBR4xUfAtfab5Ix+dgtJpCfUZxiI9ogG0yNjwazvN5
hzb6jM2n2n4qH86xemL+mMvAAAVNHonWvJqNImBF/QXW7WpJawH+3lalZoA7XsuY9sfBw6lHT7Gh
LU1omAh7yCLypirMdEVtTay3k5epiCj+Nvh41zB/+/yLA0OIh//cHP8dqRsDEQ6s+i6OCVrqNNQI
OZLCsyqzVAQWfjJZeXDWJdIjUQaps7NGqP8nriKg1pcRSKaU370v+JRPqulhJNlrGnrq2OGiQnvQ
URvp9wTTk2tdszowQgEDoAmc2juMlXgqKDzVLii+sgv4SR325tfaLdLYzeYjwSIVlyKJGFxqxkfK
eGlosoKuZtCuAtp5aq2Jl9CppLb/g/jE1hOq+VFwKw6Q/BkC31ZMVOc+Ufsx+INnyrc/jYXgt90Z
bShTPgPmUh4RDQXevvaw2evR4CFRqYlsk9mAlvmI/pAbqOjYyX8t0H8dvJgibmSsqeOMTKNe2s+a
M8UTXlomh63pFlbfeBm+bjurDRq1fkIdR4+T1S3Zphc+ZmVgDEuvh7HXJjHF9wEXOMNSQQ+Bl8qQ
unYOIu4YboytfvOG5ReyG919cF0UNXQY0mwG3/nHNzxRyNDipLU/FzcAXpQsrNavzLtNRUwn9EcT
MpjBf6F5BrMYpYIPZBWkz8m/PGZKNXTfG84rsJqrlb4W6GfiyC6gh3uaQTOuw3YoiXcLF7REsiJp
EgNugU99XUwvKFa+7kFaRA9gInaKIKzB1/IfZ+t4rPOo8qHQBmoA1jBbIO9THbg5BGRUuf78ujjw
82rrkjWCykziJDSpeL41OarfFwCALxPzdDHE3+SxTw596sTjhkvTtdRoqhZinVY/EZQJB/rbDgTv
Wr2i3PQ+Z9Q7IUkxjovat1yj6T2U/84bu29kA2TwFuJxoEGjzCMW+0A5iA2z+VCTXrUHBziE55/V
RqxC+H5+Q3jSf1NYIN+8udbeXbmOPQdrrzZ2JVSvj36L6I0xx+dKe78rUrqk2BGXXNol589VYP4+
enZB6dTDEQ2WAmeIVd6b10DclCGzUJQPO+Nx42HSVbpP6cnTrRzjNh1aIe/1M2I/CrIh9o6HZgXN
6K5DYzR1nLigv5tfI4jPBeUIYj23Jz4wYZe75yckadyj/4SeJH43L0w1m8Kvc14=
`protect end_protected
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff1.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff1 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff1;
ARCHITECTURE SYN OF lpm_dff1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "TFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "TFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff1.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff1 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff1;
ARCHITECTURE SYN OF lpm_dff1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "TFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "TFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff1.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff1 IS
PORT
(
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC
);
END lpm_dff1;
ARCHITECTURE SYN OF lpm_dff1 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire1 <= sub_wire0(0);
q <= sub_wire1;
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "TFF",
lpm_type => "LPM_FF",
lpm_width => 1
)
PORT MAP (
clock => clock,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "1"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "TFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff1_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:06:47 11/12/2015
-- Design Name:
-- Module Name: read_circuit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity read_circuit is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
pa : in STD_LOGIC;
sc : in STD_LOGIC;
rd_cpu: in STD_LOGIC;
rdy: out STD_LOGIC;
IOR: out STD_LOGIC;
data_bus: in STD_LOGIC_VECTOR (15 downto 0);
data_out_cpu : out STD_LOGIC_VECTOR (3 downto 0)
);
end read_circuit;
architecture Behavioral of read_circuit is
component re_control is
Port ( c_clk : in STD_LOGIC;
c_rst : in STD_LOGIC;
cpu_rd : in STD_LOGIC;
cpu_sc : in STD_LOGIC;
cpu_pa : in STD_LOGIC;
ready : out STD_LOGIC;
rd_enable : out STD_LOGIC;
mux_enable : out std_logic_vector (2 downto 0);
rd_strobe : out STD_LOGIC );
end component;
component reg_read is
port( re_clk: in std_logic;
re_rst: in std_logic;
re_ld: in std_logic;
re_reg_in: in std_logic_vector(15 downto 0);
re_reg_out: out std_logic_vector(15 downto 0)
);
end component;
component mux_out is
port( mux_in: in std_logic_vector(15 downto 0); -- data read from hard drive
mux_enable: in std_logic_vector (2 downto 0);
mux_out: out std_logic_vector(3 downto 0) -- data to cpu
);
end component;
signal rd_enable_s : std_logic;
signal mux_enable_s : std_logic_vector(2 downto 0);
signal data_read_s: std_logic_vector(15 downto 0);
begin
re_cntrl: re_control
port map (clk , reset, rd_cpu, sc, pa, rdy, rd_enable_s , mux_enable_s, IOR);
REG_RD: reg_read
port map (clk , reset, rd_enable_s, data_bus, data_read_s);
mux_rd: mux_out -- read to cpu
port map ( data_read_s, mux_enable_s, data_out_cpu);
end Behavioral;
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity integer_array_write is
end integer_array_write;
architecture test0 of integer_array_write is
type integer_array_type is array (0 to 9) of integer;
constant integer_array : integer_array_type := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
type integer_array_file is file of integer_array_type;
begin
doit: process
file fileout : integer_array_file open write_mode is "integer_array_write.out";
begin
write(fileout, integer_array);
assert false
report "PASSED TEST: integer_array_write."
severity note;
wait;
end process;
end test0;
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity integer_array_write is
end integer_array_write;
architecture test0 of integer_array_write is
type integer_array_type is array (0 to 9) of integer;
constant integer_array : integer_array_type := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
type integer_array_file is file of integer_array_type;
begin
doit: process
file fileout : integer_array_file open write_mode is "integer_array_write.out";
begin
write(fileout, integer_array);
assert false
report "PASSED TEST: integer_array_write."
severity note;
wait;
end process;
end test0;
|
-- Copyright (C) Clifton Labs. All rights reserved.
-- CLIFTON LABS MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE
-- SUITABILITY OF THE SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT
-- NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
-- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. CLIFTON LABS SHALL NOT BE
-- LIABLE FOR ANY DAMAGES SUFFERED BY LICENSEE AS A RESULT OF USING, RESULT
-- OF USING, MODIFYING OR DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES.
-- By using or copying this Software, Licensee agrees to abide by the
-- intellectual property laws, and all other applicable laws of the U.S.,
-- and the terms of this license.
-- You may modify, distribute, and use the software contained in this
-- package under the terms of the GNU General Public License as published
-- by the Free Software Foundation; version 2 of the License.
-- You should have received a copy of the GNU General Public License along
-- with this software; if not, write to the Free Software Foundation, Inc.,
-- 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity integer_array_write is
end integer_array_write;
architecture test0 of integer_array_write is
type integer_array_type is array (0 to 9) of integer;
constant integer_array : integer_array_type := (0, 1, 2, 3, 4, 5, 6, 7, 8, 9);
type integer_array_file is file of integer_array_type;
begin
doit: process
file fileout : integer_array_file open write_mode is "integer_array_write.out";
begin
write(fileout, integer_array);
assert false
report "PASSED TEST: integer_array_write."
severity note;
wait;
end process;
end test0;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/16/2016 09:56:37 PM
-- Design Name:
-- Module Name: test2 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test2 is
-- Port ( );
end test2;
architecture Behavioral of test2 is
begin
end Behavioral;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: %version
-- \ \ Application: MIG
-- / / Filename: write_data_path.vhd
-- /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:28 $
-- \ \ / \ Date Created: Jul 03 2009
-- \___\/\___\
--
-- Device: Spartan6
-- Design Name: DDR/DDR2/DDR3/LPDDR
-- Purpose: This is top level of write path.
-- Reference:
-- Revision History:
--*****************************************************************************
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity write_data_path is
generic (
TCQ : TIME := 100 ps;
MEM_BURST_LEN : integer := 8;
FAMILY : string := "SPARTAN6";
ADDR_WIDTH : integer := 32;
DWIDTH : integer := 32;
DATA_PATTERN : string := "DGEN_ALL"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : integer := 8;
SEL_VICTIM_LINE : integer := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
MEM_COL_WIDTH : integer := 10;
EYE_TEST : string := "FALSE"
);
port (
clk_i : in std_logic;
rst_i : in std_logic_vector(9 downto 0);
cmd_rdy_o : out std_logic;
cmd_valid_i : in std_logic;
cmd_validB_i : in std_logic;
cmd_validC_i : in std_logic;
prbs_fseed_i : in std_logic_vector(31 downto 0);
data_mode_i : in std_logic_vector(3 downto 0);
-- m_addr_i : in std_logic_vector(31 downto 0);
fixed_data_i : in std_logic_vector(DWIDTH-1 downto 0);
addr_i : in std_logic_vector(31 downto 0);
bl_i : in std_logic_vector(5 downto 0);
-- input [5:0] port_data_counts_i,// connect to data port fifo counts
data_rdy_i : in std_logic;
data_valid_o : out std_logic;
last_word_wr_o : out std_logic;
data_o : out std_logic_vector(DWIDTH - 1 downto 0);
data_mask_o : out std_logic_vector((DWIDTH / 8) - 1 downto 0);
data_wr_end_o : out std_logic );
end entity write_data_path;
architecture trans of write_data_path is
COMPONENT wr_data_gen IS
GENERIC (
TCQ : TIME := 100 ps;
FAMILY : STRING := "SPARTAN6"; -- "SPARTAN6", "VIRTEX6"
MODE : STRING := "WR"; --"WR", "RD"
MEM_BURST_LEN : integer := 8;
ADDR_WIDTH : INTEGER := 32;
BL_WIDTH : INTEGER := 6;
DWIDTH : INTEGER := 32;
DATA_PATTERN : STRING := "DGEN_PRBS"; --"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
NUM_DQ_PINS : INTEGER := 8;
SEL_VICTIM_LINE : INTEGER := 3; -- VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
COLUMN_WIDTH : INTEGER := 10;
EYE_TEST : STRING := "FALSE"
);
PORT (
clk_i : IN STD_LOGIC;
rst_i : in STD_LOGIC_VECTOR(4 downto 0);
prbs_fseed_i : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
data_mode_i : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cmd_rdy_o : OUT STD_LOGIC;
cmd_valid_i : IN STD_LOGIC;
cmd_validB_i : IN STD_LOGIC;
cmd_validC_i : IN STD_LOGIC;
last_word_o : OUT STD_LOGIC;
fixed_data_i : IN std_logic_vector(DWIDTH-1 downto 0);
-- m_addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
addr_i : IN STD_LOGIC_VECTOR(ADDR_WIDTH - 1 DOWNTO 0);
bl_i : IN STD_LOGIC_VECTOR(BL_WIDTH - 1 DOWNTO 0);
data_rdy_i : IN STD_LOGIC;
data_valid_o : OUT STD_LOGIC;
data_o : OUT STD_LOGIC_VECTOR(DWIDTH - 1 DOWNTO 0);
data_wr_end_o : OUT STD_LOGIC
);
END COMPONENT;
signal data_valid : std_logic;
signal cmd_rdy : std_logic;
-- Declare intermediate signals for referenced outputs
signal cmd_rdy_o_xhdl0 : std_logic;
signal last_word_wr_o_xhdl3 : std_logic;
signal data_o_xhdl1 : std_logic_vector(DWIDTH - 1 downto 0);
signal data_wr_end_o_xhdl2 : std_logic;
begin
-- Drive referenced outputs
cmd_rdy_o <= cmd_rdy_o_xhdl0;
last_word_wr_o <= last_word_wr_o_xhdl3;
data_o <= data_o_xhdl1;
data_wr_end_o <= data_wr_end_o_xhdl2;
data_valid_o <= data_valid and data_rdy_i;
-- data_mask_o <= "0000"; -- for now
data_mask_o <= (others => '0');
wr_data_gen_inst : wr_data_gen
generic map (
TCQ => TCQ,
family => FAMILY,
num_dq_pins => NUM_DQ_PINS,
sel_victim_line => SEL_VICTIM_LINE,
MEM_BURST_LEN => MEM_BURST_LEN,
data_pattern => DATA_PATTERN,
dwidth => DWIDTH,
column_width => MEM_COL_WIDTH,
eye_test => EYE_TEST
)
port map (
clk_i => clk_i,
rst_i => rst_i(9 downto 5),
prbs_fseed_i => prbs_fseed_i,
data_mode_i => data_mode_i,
cmd_rdy_o => cmd_rdy_o_xhdl0,
cmd_valid_i => cmd_valid_i,
cmd_validb_i => cmd_validB_i,
cmd_validc_i => cmd_validC_i,
last_word_o => last_word_wr_o_xhdl3,
-- .port_data_counts_i (port_data_counts_i),
-- m_addr_i => m_addr_i,
fixed_data_i => fixed_data_i,
addr_i => addr_i,
bl_i => bl_i,
data_rdy_i => data_rdy_i,
data_valid_o => data_valid,
data_o => data_o_xhdl1,
data_wr_end_o => data_wr_end_o_xhdl2
);
end architecture trans;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.STD_LOGIC_ARITH.all;
entity MODULUS_2x_32b is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
start : in STD_LOGIC;
flush : in std_logic;
holdn : in std_ulogic;
INPUT_1 : in STD_LOGIC_VECTOR(31 downto 0);
INPUT_2 : in STD_LOGIC_VECTOR(31 downto 0);
ready : out std_logic;
nready : out std_logic;
icc : out std_logic_vector(3 downto 0);
OUTPUT_1 : out STD_LOGIC_VECTOR(31 downto 0)
);
END;
architecture behav of MODULUS_2x_32b is
constant SIZE : INTEGER := 32;
signal buf : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
signal dbuf : STD_LOGIC_VECTOR((SIZE - 1) downto 0);
signal sm : INTEGER range 0 to SIZE;
alias buf1 is buf((2 * SIZE - 1) downto SIZE);
alias buf2 is buf((SIZE - 1) downto 0);
BEGIN
process(rst, clk)
variable sready, snready : std_logic;
variable tbuf : STD_LOGIC_VECTOR((2*SIZE - 1) downto 0);
variable xx1 : std_logic;
variable xx2 : std_logic;
variable yy : STD_LOGIC_VECTOR((2 * SIZE - 1) downto 0);
begin
sready := '0';
snready := '0';
-- Si l'on recoit une demande de reset alors on reinitialise
if rst = '0' then
OUTPUT_1 <= (others => '0');
sm <= 0;
ready <= '0';
ready <= sready;
nready <= snready;
-- En cas de front montant de l'horloge alors on calcule
elsif rising_edge(clk) then
-- Si Flush alors on reset le composant
if (flush = '1') then
sm <= 0;
-- Si le signal de maintient est actif alors on gel l'execution
elsif (holdn = '0') then
sm <= sm;
-- Sinon on déroule l'execution de la division
else
case sm is
-- Etat d'attente du signal start
when 0 =>
OUTPUT_1 <= buf1;
if start = '1' then
buf1 <= (others => '0');
buf2 <= INPUT_1;
dbuf <= INPUT_2;
sm <= sm + 1; -- le calcul est en cours
else
sm <= sm;
end if;
when others =>
sready := '1'; -- le calcul est en cours
sm <= 0;
-- ON TRAITE LE PREMIER BIT DE L'ITERATION
if buf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
tbuf((2 * SIZE - 1) downto SIZE) := '0' & (buf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
tbuf((SIZE - 1) downto 0) := buf2((SIZE - 2) downto 0) & '1'; -- ON POUSSE LE RESULTAT
else
tbuf := buf((2 * SIZE - 2) downto 0) & '0';
end if;
-- ON TRAITE LE SECOND BIT DE L'ITERATION
if tbuf((2 * SIZE - 2) downto (SIZE - 1)) >= dbuf then
buf1 <= '0' & (tbuf((2 * SIZE - 3) downto (SIZE - 1)) - dbuf((SIZE - 2) downto 0));
buf2 <= tbuf((SIZE - 2) downto 0) & '1';
else
buf <= tbuf((2 * SIZE - 2) downto 0) & '0';
end if;
-- EN FONCTION DE LA VALEUR DU COMPTEUR ON CHOISI NOTRE DESTIN
if sm /= 16 then
sm <= sm + 1;
snready := '0'; -- le resultat n'est pas disponible
else
snready := '1'; -- le resultat du calcul est disponible
sm <= 0;
end if;
end case;
-- On transmet les signaux au systeme
ready <= sready;
nready <= snready;
end if;
end if;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s04b02x00p02n01i03065ent IS
END c12s04b02x00p02n01i03065ent;
ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS
type intvector is array (natural range <>) of integer;
signal V2 : intvector(1 to 5);
signal V0 : integer := 66;
BEGIN
FG2: for i in V2'range generate
IG1: if i = V2'left generate
V2(i) <= V0 after 1 ns;
end generate;
IG2: if i /= V2'left generate
V2(i) <= V2(i-1) after 1 ns;
end generate;
-- ..., V2(2) <= V2(1), V2(1) <= V0
end generate;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( V2 = (66,66,66,66,66) )
report "***PASSED TEST: c12s04b02x00p02n01i03065"
severity NOTE;
assert ( V2 = (66,66,66,66,66) )
report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed."
severity ERROR;
END PROCESS TESTING;
END c12s04b02x00p02n01i03065arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s04b02x00p02n01i03065ent IS
END c12s04b02x00p02n01i03065ent;
ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS
type intvector is array (natural range <>) of integer;
signal V2 : intvector(1 to 5);
signal V0 : integer := 66;
BEGIN
FG2: for i in V2'range generate
IG1: if i = V2'left generate
V2(i) <= V0 after 1 ns;
end generate;
IG2: if i /= V2'left generate
V2(i) <= V2(i-1) after 1 ns;
end generate;
-- ..., V2(2) <= V2(1), V2(1) <= V0
end generate;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( V2 = (66,66,66,66,66) )
report "***PASSED TEST: c12s04b02x00p02n01i03065"
severity NOTE;
assert ( V2 = (66,66,66,66,66) )
report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed."
severity ERROR;
END PROCESS TESTING;
END c12s04b02x00p02n01i03065arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3065.vhd,v 1.2 2001-10-26 16:30:04 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s04b02x00p02n01i03065ent IS
END c12s04b02x00p02n01i03065ent;
ARCHITECTURE c12s04b02x00p02n01i03065arch OF c12s04b02x00p02n01i03065ent IS
type intvector is array (natural range <>) of integer;
signal V2 : intvector(1 to 5);
signal V0 : integer := 66;
BEGIN
FG2: for i in V2'range generate
IG1: if i = V2'left generate
V2(i) <= V0 after 1 ns;
end generate;
IG2: if i /= V2'left generate
V2(i) <= V2(i-1) after 1 ns;
end generate;
-- ..., V2(2) <= V2(1), V2(1) <= V0
end generate;
TESTING: PROCESS
BEGIN
wait for 50 ns;
assert NOT( V2 = (66,66,66,66,66) )
report "***PASSED TEST: c12s04b02x00p02n01i03065"
severity NOTE;
assert ( V2 = (66,66,66,66,66) )
report "***FAILED TEST: c12s04b02x00p02n01i03065 - Generate statement semantic test failed."
severity ERROR;
END PROCESS TESTING;
END c12s04b02x00p02n01i03065arch;
|
-- This file tests package declarative items.
package pkg is
type BIT is ('0', '1');
-- subprogram_declaration
procedure proc_a;
function func_a return BIT;
-- subprogram_instantiation_declaration
procedure proc_b is new proc_a;
function func_b is new func_a;
-- package_declaration
package pkg_a is end;
-- package_instantiation_declaration
package pkg_b is new pkg_a;
-- type_declaration
type NUM is range 0 to 100;
-- subtype_declaration
subtype ANS is NUM range 0 to 42;
-- constant_declaration
--constant const_a : BIT;
-- signal_declaration
--signal sig_a : BIT;
-- variable_declaration
--variable shvar_a : BIT;
-- file_declaration
--file file_a : BIT;
-- alias_declaration
--alias alias_a is pkg_a;
-- component_declaration
--component comp_a is
--end component;
-- attribute_declaration
--attribute attr_a : BIT;
-- attribute_specification
--attribute attr_a of NUM : type is '0';
-- disconnection_specification
--disconnect all : BIT after 0;
-- use_clause
use work.pkg.all;
-- group_template_declaration
--group grp_tmp_a is (signal, signal);
-- group_declaration
--group grp_a : grp_tmp_a (sig_a, sig_a);
end;
library work;
use work.pkg.all;
entity foo is end;
architecture bar of foo is
-- Currently the architecture is required to trigger typeck of the entire
-- library.
begin end;
-- @elab foo
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.