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library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GNNKZSYI73 is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "000000000000000000000000";
width : natural := 24);
port(
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GNNKZSYI73 is
Begin
-- Constant
output <= "000000000000000000000000";
end architecture; |
entity sub is
port (
a : in bit_vector );
end entity;
architecture test of sub is
begin
process (a)
begin
report a'path_name & " range is " & integer'image(a'left)
& " to " & integer'image(a'right) ;
end process;
end architecture;
-------------------------------------------------------------------------------
entity elab10 is
end entity;
architecture test of elab10 is
signal x : bit_vector(1 to 5);
signal y : bit_vector(6 to 10);
begin
sub1_i: entity work.sub
port map ( x );
sub2_i: entity work.sub
port map ( y );
process is
begin
y <= not y after 1 ns;
wait;
end process;
end architecture;
|
entity test is
subtype t is baz."=" foo'bar;
end;
|
----------------------------------------------------------------------------------
-- Company: University of Genoa
-- Engineer: Alessio Leoncini
--
-- Create Date: 14:28:47 10/06/2011
-- Design Name:
-- Module Name: CaosComb - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Random Bit Generator based on a chaotic map
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CaosComb is
Port ( res : in STD_LOGIC;
out0 : out STD_LOGIC);
end CaosComb;
architecture Behavioral of CaosComb is
-- Integer part is ALWAYS 2 bits
constant nbit : integer := 128; -- total bits num
signal reg_in : signed(nbit-1 downto 0);
signal reg_out : signed(nbit-1 downto 0);
-- Supposing 2 integer bits and two's complement, one and minus one values
constant zero : signed(nbit-1 downto 0) := (others => '0');
constant one : signed(nbit-1 downto 0) := (nbit-2 => '1', others => '0');
constant minusone : signed(nbit-1 downto 0) := (nbit-1 => '1', nbit-2 => '1', others => '0');
-- x0 = 0.5
constant x0 : signed(nbit-1 downto 0) := (nbit-3 => '1', others => '0');
begin
-- only sign of register in output
out0 <= reg_out(nbit-1);
-- map
proc_map: process(reg_in)
begin
-- 1.875 * reg = (2*reg) - (reg/8) = (reg<<1) - (reg>>3)
if (reg_in < zero) then
-- if reg<1, reg = 1.875 * reg + 1
reg_out <= (( reg_in(nbit-2 downto 0) & '0' ) - ( "111" & reg_in(nbit-1 downto 3) )) + one;
else
-- else, reg = 1.875 * reg - 1
reg_out <= (( reg_in(nbit-2 downto 0)&'0' ) - ( "000" & reg_in(nbit-1 downto 3) )) + minusone;
end if;
end process;
-- init condition and loop processing
proc_loop: process(reg_out,res)
begin
if res = '0' then
-- normal behavior (loop)
reg_in <= reg_out;
else
-- if reset, init with specified x0
reg_in <= x0;
end if;
end process;
end Behavioral; |
-- ==============================================
-- Copyright © 2014 Ali M. Al-Bayaty
--
-- Video-Game-Engine is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- any later version.
--
-- Video-Game-Engine is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- ==============================================
--
-- Video Game Engine Project
-- ( EDK: VGA 40x30 Resolution, User Logic VHDL )
--
-- MSEE student: Ali M. Al-Bayaty
-- EE659: System-On-Chip
-- Personal website: <http://albayaty.github.io/>
-- Source code link: <https://github.com/albayaty/Video-Game-Engine.git>
--
-- ==============================================
--
------------------------------------------------------------------------------
-- user_logic.vhd - entity/architecture pair
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: user_logic.vhd
-- Version: 1.00.a
-- Description: User logic.
-- Date: Wed Oct 19 14:01:59 2011 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
-- DO NOT EDIT BELOW THIS LINE --------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
-- DO NOT EDIT ABOVE THIS LINE --------------------
--USER libraries added here
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SLV_DWIDTH -- Slave interface data bus width
-- C_NUM_REG -- Number of software accessible registers
--
-- Definition of Ports:
-- Bus2IP_Clk -- Bus to IP clock
-- Bus2IP_Reset -- Bus to IP reset
-- Bus2IP_Data -- Bus to IP data bus
-- Bus2IP_BE -- Bus to IP byte enables
-- Bus2IP_RdCE -- Bus to IP read chip enable
-- Bus2IP_WrCE -- Bus to IP write chip enable
-- IP2Bus_Data -- IP to Bus data bus
-- IP2Bus_RdAck -- IP to Bus read transfer acknowledgement
-- IP2Bus_WrAck -- IP to Bus write transfer acknowledgement
-- IP2Bus_Error -- IP to Bus error response
------------------------------------------------------------------------------
entity user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 7
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
hsync: out std_logic;
vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "CLK";
attribute SIGIS of Bus2IP_Reset : signal is "RST";
end entity user_logic;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of user_logic is
--USER signal declarations added here, as needed for user logic
component vga
port (
clk: in std_logic;
hsync, vsync: out std_logic;
rgb: out std_logic_vector(0 to 2);
we: in std_logic;
add_bus1: in std_logic_vector(0 to 10);
add_bus2: in std_logic_vector(0 to 10);
add_bus3: in std_logic_vector(0 to 10);
data_bus1: in std_logic_vector(0 to 4);
data_bus2: in std_logic_vector(0 to 4);
data_bus3: in std_logic_vector(0 to 3) );
end component;
------------------------------------------
-- Signals for user logic slave model s/w accessible register example
------------------------------------------
signal slv_reg0 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg1 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg2 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg3 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg4 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg5 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg6 : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_reg_write_sel : std_logic_vector(0 to 6);
signal slv_reg_read_sel : std_logic_vector(0 to 6);
signal slv_ip2bus_data : std_logic_vector(0 to C_SLV_DWIDTH-1);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
begin
--USER logic implementation added here
vgamodule: vga port map(
clk => Bus2IP_Clk,
hsync => hsync,
vsync => vsync,
rgb => rgb,
we => slv_reg0(31),
add_bus1 => slv_reg1(21 to 31),
add_bus2 => slv_reg2(21 to 31),
add_bus3 => slv_reg3(21 to 31),
data_bus1 => slv_reg4(27 to 31),
data_bus2 => slv_reg5(27 to 31),
data_bus3 => slv_reg6(28 to 31)
);
------------------------------------------
-- Example code to read/write user logic slave model s/w accessible registers
--
-- Note:
-- The example code presented here is to show you one way of reading/writing
-- software accessible registers implemented in the user logic slave model.
-- Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
-- to one software accessible register by the top level template. For example,
-- if you have four 32 bit software accessible registers in the user logic,
-- you are basically operating on the following memory mapped registers:
--
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
--
------------------------------------------
slv_reg_write_sel <= Bus2IP_WrCE(0 to 6);
slv_reg_read_sel <= Bus2IP_RdCE(0 to 6);
slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1) or Bus2IP_WrCE(2) or Bus2IP_WrCE(3) or Bus2IP_WrCE(4) or Bus2IP_WrCE(5) or Bus2IP_WrCE(6);
slv_read_ack <= Bus2IP_RdCE(0) or Bus2IP_RdCE(1) or Bus2IP_RdCE(2) or Bus2IP_RdCE(3) or Bus2IP_RdCE(4) or Bus2IP_RdCE(5) or Bus2IP_RdCE(6);
-- implement slave model software accessible register(s)
SLAVE_REG_WRITE_PROC : process( Bus2IP_Clk ) is
begin
if Bus2IP_Clk'event and Bus2IP_Clk = '1' then
if Bus2IP_Reset = '1' then
slv_reg0 <= (others => '0');
slv_reg1 <= (others => '0');
slv_reg2 <= (others => '0');
slv_reg3 <= (others => '0');
slv_reg4 <= (others => '0');
slv_reg5 <= (others => '0');
slv_reg6 <= (others => '0');
else
case slv_reg_write_sel is
when "1000000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg0(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0100000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg1(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0010000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg2(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0001000" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg3(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000100" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg4(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000010" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg5(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when "0000001" =>
for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop
if ( Bus2IP_BE(byte_index) = '1' ) then
slv_reg6(byte_index*8 to byte_index*8+7) <= Bus2IP_Data(byte_index*8 to byte_index*8+7);
end if;
end loop;
when others => null;
end case;
end if;
end if;
end process SLAVE_REG_WRITE_PROC;
-- implement slave model software accessible register(s) read mux
SLAVE_REG_READ_PROC : process( slv_reg_read_sel, slv_reg0, slv_reg1, slv_reg2, slv_reg3, slv_reg4, slv_reg5, slv_reg6 ) is
begin
case slv_reg_read_sel is
when "1000000" => slv_ip2bus_data <= slv_reg0;
when "0100000" => slv_ip2bus_data <= slv_reg1;
when "0010000" => slv_ip2bus_data <= slv_reg2;
when "0001000" => slv_ip2bus_data <= slv_reg3;
when "0000100" => slv_ip2bus_data <= slv_reg4;
when "0000010" => slv_ip2bus_data <= slv_reg5;
when "0000001" => slv_ip2bus_data <= slv_reg6;
when others => slv_ip2bus_data <= (others => '0');
end case;
end process SLAVE_REG_READ_PROC;
------------------------------------------
-- Example code to drive IP to Bus signals
------------------------------------------
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else
(others => '0');
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
end IMP;
|
package body fifo_pkg is
end package body fifo_pkg;
package BODY fifo_pkg is
end package body fifo_pkg;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright IEEE P1076 WG. Licensed Apache 2.0";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright IEEE P1076 WG. Licensed Apache 2.0";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
|
-- -----------------------------------------------------------------
--
-- Copyright 2019 IEEE P1076 WG Authors
--
-- See the LICENSE file distributed with this work for copyright and
-- licensing information and the AUTHORS file.
--
-- This file to you under the Apache License, Version 2.0 (the "License").
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-- implied. See the License for the specific language governing
-- permissions and limitations under the License.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright IEEE P1076 WG. Licensed Apache 2.0";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
end package MATH_REAL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2452.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02452ent IS
END c07s03b02x02p03n02i02452ent;
ARCHITECTURE c07s03b02x02p03n02i02452arch OF c07s03b02x02p03n02i02452ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 5 );
function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
begin
return A;
end F;
function F2 return CONSTRAINED_ARRAY is
begin
return F( ( others => 'c' ) );
-- sole "others" choice is legal.
end F2;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F2;
assert NOT(k="ccccc")
report "***PASSED TEST: c07s03b02x02p03n02i02452"
severity NOTE;
assert (k="ccccc")
report "***FAILED TEST: c07s03b02x02p03n02i02452 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02452arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2452.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02452ent IS
END c07s03b02x02p03n02i02452ent;
ARCHITECTURE c07s03b02x02p03n02i02452arch OF c07s03b02x02p03n02i02452ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 5 );
function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
begin
return A;
end F;
function F2 return CONSTRAINED_ARRAY is
begin
return F( ( others => 'c' ) );
-- sole "others" choice is legal.
end F2;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F2;
assert NOT(k="ccccc")
report "***PASSED TEST: c07s03b02x02p03n02i02452"
severity NOTE;
assert (k="ccccc")
report "***FAILED TEST: c07s03b02x02p03n02i02452 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02452arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2452.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x02p03n02i02452ent IS
END c07s03b02x02p03n02i02452ent;
ARCHITECTURE c07s03b02x02p03n02i02452arch OF c07s03b02x02p03n02i02452ent IS
BEGIN
TESTING: PROCESS
type UNCONSTRAINED_ARRAY is array ( integer range <> ) of character;
subtype CONSTRAINED_ARRAY is UNCONSTRAINED_ARRAY ( 1 to 5 );
function F (A:CONSTRAINED_ARRAY) return CONSTRAINED_ARRAY is
begin
return A;
end F;
function F2 return CONSTRAINED_ARRAY is
begin
return F( ( others => 'c' ) );
-- sole "others" choice is legal.
end F2;
variable k : CONSTRAINED_ARRAY;
BEGIN
k := F2;
assert NOT(k="ccccc")
report "***PASSED TEST: c07s03b02x02p03n02i02452"
severity NOTE;
assert (k="ccccc")
report "***FAILED TEST: c07s03b02x02p03n02i02452 - Others is used in an aggregate which corresponds to an unconstrained formal parameter."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x02p03n02i02452arch;
|
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-- NEED RESULT: ARCH00051: One or more elsif's are allowed in if statement passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00051
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.6 (2)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00051)
-- ENT00051_Test_Bench(ARCH00051_Test_Bench)
--
-- REVISION HISTORY:
--
-- 1-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00051 of E00000 is
signal Dummy : boolean := false ;
begin
P1 :
process ( Dummy )
variable correct : boolean := false ;
begin
for i in 1 to 10 loop
if i = 1 then
correct := (i = 1) ;
elsif i = 2 then
correct := (i = 2) ;
elsif i = 3 then
correct := (i = 3) ;
elsif i = 4 then
correct := (i = 4) ;
elsif i = 5 then
correct := (i = 5) ;
elsif i = 6 then
correct := (i = 6) ;
elsif i = 7 then
correct := (i = 7) ;
elsif i = 8 then
correct := (i = 8) ;
elsif i = 9 then
correct := (i = 9) ;
else
correct := (i = 10) ;
end if ;
test_report ( "ARCH00051" ,
"One or more elsif's are allowed in if statement" ,
correct ) ;
end loop ;
end process P1 ;
end ARCH00051 ;
entity ENT00051_Test_Bench is
end ENT00051_Test_Bench ;
architecture ARCH00051_Test_Bench of ENT00051_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00051 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00051_Test_Bench ;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity ex2_hot is
port(
clock: in std_logic;
input: in std_logic_vector(1 downto 0);
output: out std_logic_vector(1 downto 0)
);
end ex2_hot;
architecture behaviour of ex2_hot is
constant s1: std_logic_vector(18 downto 0) := "1000000000000000000";
constant s2: std_logic_vector(18 downto 0) := "0100000000000000000";
constant s4: std_logic_vector(18 downto 0) := "0010000000000000000";
constant s0: std_logic_vector(18 downto 0) := "0001000000000000000";
constant s3: std_logic_vector(18 downto 0) := "0000100000000000000";
constant s6: std_logic_vector(18 downto 0) := "0000010000000000000";
constant s9: std_logic_vector(18 downto 0) := "0000001000000000000";
constant s7: std_logic_vector(18 downto 0) := "0000000100000000000";
constant s8: std_logic_vector(18 downto 0) := "0000000010000000000";
constant s5: std_logic_vector(18 downto 0) := "0000000001000000000";
constant s10: std_logic_vector(18 downto 0) := "0000000000100000000";
constant s11: std_logic_vector(18 downto 0) := "0000000000010000000";
constant s13: std_logic_vector(18 downto 0) := "0000000000001000000";
constant s12: std_logic_vector(18 downto 0) := "0000000000000100000";
constant s15: std_logic_vector(18 downto 0) := "0000000000000010000";
constant s18: std_logic_vector(18 downto 0) := "0000000000000001000";
constant s16: std_logic_vector(18 downto 0) := "0000000000000000100";
constant s17: std_logic_vector(18 downto 0) := "0000000000000000010";
constant s14: std_logic_vector(18 downto 0) := "0000000000000000001";
signal current_state, next_state: std_logic_vector(18 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-------------------"; output <= "--";
case current_state is
when s1 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s4; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s3; output <= "--";
end if;
when s2 =>
if std_match(input, "00") then next_state <= s6; output <= "--";
elsif std_match(input, "01") then next_state <= s9; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s3 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s7; output <= "--";
elsif std_match(input, "11") then next_state <= s8; output <= "--";
end if;
when s4 =>
if std_match(input, "00") then next_state <= s2; output <= "--";
elsif std_match(input, "01") then next_state <= s1; output <= "--";
elsif std_match(input, "10") then next_state <= s6; output <= "--";
elsif std_match(input, "11") then next_state <= s5; output <= "--";
end if;
when s5 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s6; output <= "--";
end if;
when s6 =>
if std_match(input, "00") then next_state <= s1; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s2; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s7 =>
if std_match(input, "00") then next_state <= s5; output <= "11";
elsif std_match(input, "01") then next_state <= s2; output <= "00";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s8 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s1; output <= "00";
end if;
when s9 =>
if std_match(input, "00") then next_state <= s5; output <= "--";
elsif std_match(input, "01") then next_state <= s3; output <= "11";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s10 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s13; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s12; output <= "--";
end if;
when s11 =>
if std_match(input, "00") then next_state <= s15; output <= "--";
elsif std_match(input, "01") then next_state <= s18; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s12 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s16; output <= "--";
elsif std_match(input, "11") then next_state <= s17; output <= "--";
end if;
when s13 =>
if std_match(input, "00") then next_state <= s11; output <= "--";
elsif std_match(input, "01") then next_state <= s10; output <= "00";
elsif std_match(input, "10") then next_state <= s15; output <= "--";
elsif std_match(input, "11") then next_state <= s14; output <= "--";
end if;
when s14 =>
if std_match(input, "00") then next_state <= s0; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s15; output <= "--";
end if;
when s15 =>
if std_match(input, "00") then next_state <= s10; output <= "00";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s11; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "11";
end if;
when s16 =>
if std_match(input, "00") then next_state <= s14; output <= "11";
elsif std_match(input, "01") then next_state <= s11; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when s17 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s0; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "--";
elsif std_match(input, "11") then next_state <= s10; output <= "00";
end if;
when s18 =>
if std_match(input, "00") then next_state <= s14; output <= "--";
elsif std_match(input, "01") then next_state <= s12; output <= "--";
elsif std_match(input, "10") then next_state <= s0; output <= "11";
elsif std_match(input, "11") then next_state <= s0; output <= "--";
end if;
when others => next_state <= "-------------------"; output <= "--";
end case;
end process;
end behaviour;
|
library IEEE;
use IEEE.numeric_std.all;
use IEEE.std_logic_1164.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
CONTROL : out std_logic_vector(7 downto 0);
KEYB_A : in std_logic_vector(7 downto 0);
KEYB_A2 : in std_logic_vector(3 downto 0);
KEYB_D : out std_logic_vector(7 downto 0);
KEYB_D2 : out std_logic_vector(3 downto 0);
VGA_SEL : in std_logic; -- 0 = Lvov, 1= MIPS
KEYB_DATA : out std_logic_vector(7 downto 0) -- MIPS
);
end keyboard;
architecture Behavioral of keyboard is
signal CODE : std_logic_vector(7 downto 0);
signal DONE : std_logic;
signal ERROR : std_logic;
signal KEY_REL : std_logic;
signal KEY_EXT : std_logic;
type Matrix_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Matrix : Matrix_Image(0 to 7);
type Matrix2_Image is array (natural range <>) of std_logic_vector(3 downto 0);
signal Matrix2 : Matrix2_Image(0 to 3);
begin
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => not RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
DECODER : process(CLK)
variable KEY : std_logic_vector(10 downto 0);
variable KEY2 : std_logic_vector(5 downto 0);
begin
if rising_edge(CLK) then
if RESET = '0' then
Matrix <= (others => (others => '0'));
KEY_REL <= '0';
KEY_EXT <= '0';
CONTROL <= "00000000";
else
CONTROL <= "00000000";
if VGA_SEL = '0' then
-- Lvov
if DONE = '1' then -- ScanCode Readed
if CODE = X"F0" then -- Key Released
KEY_REL <= '1';
elsif CODE = X"E0" then -- Extended Key
KEY_EXT <= '1';
else
KEY := (others => '0');
KEY2 := (others => '0');
case CODE is -- PS2 Set 2 Scancodes
when x"1C" => KEY := "11000010000"; -- A
when x"32" => KEY := "01100000010"; -- B
when x"21" => KEY := "10110000000"; -- C
when x"23" => KEY := "01010000000"; -- D
when x"24" => KEY := "10100010000"; -- E
when x"2B" => KEY := "11010000000"; -- F
when x"34" => KEY := "00100000001"; -- G
when x"33" => KEY := "00101000000"; -- H
when x"43" => KEY := "11100100000"; -- I
when x"3B" => KEY := "10100000100"; -- J
when x"42" => KEY := "10100100000"; -- K
when x"4B" => KEY := "01000000100"; -- L
when x"3A" => KEY := "11101000000"; -- M
when x"31" => KEY := "10100001000"; -- N
when x"44" => KEY := "01000000010"; -- O
when x"4D" => KEY := "11000001000"; -- P
when x"15" => KEY := "11100000010"; -- Q
when x"2D" => KEY := "01000000001"; -- R
when x"1B" => KEY := "11110000000"; -- S
when x"2C" => KEY := "11100010000"; -- T
when x"3C" => KEY := "10101000000"; -- U
when x"2A" => KEY := "01001000000"; -- V
when x"1D" => KEY := "11000100000"; -- W
when x"22" => KEY := "11100001000"; -- X
when x"35" => KEY := "11001000000"; -- Y
when x"1A" => KEY := "00110000000"; -- Z
when x"16" => KEY := "10010000000"; -- 1
when x"1E" => KEY := "10001000000"; -- 2
when x"26" => KEY := "10000100000"; -- 3
when x"25" => KEY := "10000010000"; -- 4
when x"2E" => KEY := "10000001000"; -- 5
when x"36" => KEY := "00000000001"; -- 6
when x"3D" => KEY := "00000000010"; -- 7
when x"3E" => KEY := "00000000100"; -- 8
when x"46" => KEY := "00010000000"; -- 9
when x"45" => KEY := "00001000000"; -- 0
when x"29" => KEY := "01100000001"; -- SPACE
when x"66" => KEY := "01000001000"; -- PACKSPACE | ZB
when x"5A" => KEY := "00100001000"; -- ENTER | WK
when x"58" => KEY := "11000000100"; -- CAPS LOCK | SU
when x"12" =>
if KEY_EXT = '1' then -- Print Screen
if KEY_REL = '0' then -- Lvov Reset
CONTROL(0) <= '1';
end if;
else
KEY := "11100000001"; -- LEFT SHIFT | NR
end if;
when x"59" => KEY := "01100001000"; -- RIGHT SHIFT | WR
when x"0D" => KEY := "00000010000"; -- TAB
when x"41" => KEY := "01110000000"; -- ,
when x"49" => KEY := "01000010000"; -- .
when x"4E" => KEY := "00000100000"; -- -
when x"5D" => KEY := "01000100000"; -- \
when x"55" => KEY := "11100000100"; -- = | ^
when x"0E" => KEY := "00100100000"; -- ' | :
when x"54" => KEY := "00100000010"; -- [
-- when x"76" => KEY := "10000000001"; -- | STR
-- when x"76" => KEY := "10000000001"; -- | @]
when x"5B" => KEY := "00100000100"; -- ]
when x"1f" =>
if KEY_EXT = '1' then -- Left Win
if KEY_REL = '0' then
CONTROL(2) <= '1'; -- Switch to Host Console
end if;
end if;
when x"27" =>
if KEY_EXT = '1' then -- Right Win
if KEY_REL = '0' then
CONTROL(3) <= '1'; -- Switch to Lvov Screen
end if;
end if;
when x"4C" => KEY := "11000000001"; -- ;
when x"4A" => KEY := "01101000000"; -- /
when x"0B" => KEY := "10000000010"; -- F6 | [G]
when x"83" => KEY := "10000000100"; -- F7 | [B]
when x"11" =>
if KEY_EXT = '1' then
KEY := "00100010000"; -- RIGHT ALT | PS
else
KEY := "00000001000"; -- LEFT ALT | GT
end if;
when x"14" =>
if KEY_EXT = '1' then
KEY := "01100100000"; -- RIGHT CTRL | LAT
else
KEY := "11000000010"; -- LEFT CTRL | RUS
end if;
when x"76" => KEY2 := "010010"; -- ESC | F0
when x"05" => KEY2 := "010100"; -- F1
when x"06" => KEY2 := "011000"; -- F2
when x"04" => KEY2 := "101000"; -- F3
when x"0C" => KEY2 := "100100"; -- F4
when x"03" => KEY2 := "100010"; -- F5
when x"0A" => KEY2 := "001000"; -- F8 | [R]
when x"01" => KEY2 := "000100"; -- F9 | DIN
when x"09" => KEY2 := "000010"; -- F10 | CD
when x"78" => KEY2 := "000001"; -- F11 | P4
when x"07" => KEY2 := "010001"; -- F12 | P/D
when x"74" =>
if KEY_EXT = '1' then
KEY2 := "110001"; -- RIGHT
end if;
when x"75" =>
if KEY_EXT = '1' then
KEY2 := "110010"; -- UP
end if;
when x"6B" =>
if KEY_EXT = '1' then
KEY2 := "110100"; -- LEFT
end if;
when x"72" =>
if KEY_EXT = '1' then
KEY2 := "111000"; -- DOWN
end if;
when x"71" =>
if KEY_EXT = '1' then
KEY2 := "100001"; -- DEL | DIA
end if;
when x"7e" => -- ScrollLock
if KEY_REL = '0' then -- Reset to Standard Lvov ROM
CONTROL(0) <= '1';
end if;
when OTHERS => NULL;
end case;
if KEY_REL = '0' then
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) or
std_logic_vector(unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) or
std_logic_vector(unsigned(KEY2(3 downto 0)));
else
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) and
std_logic_vector(not unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) and
std_logic_vector(not unsigned(KEY2(3 downto 0)));
end if;
KEY_REL <= '0';
KEY_EXT <= '0';
end if;
end if;
else
-- MIPS
if DONE = '1' then
if CODE = X"e0" then
-- Extended key code follows
KEY_EXT <= '1';
elsif CODE = X"f0" then
-- Release code follows
KEY_REL <= '1';
else
if KEY_EXT = '1' then
case CODE is
when X"00" => -- X"12"
if KEY_REL = '0' then
CONTROL(1) <= '1'; -- MIPS Reset
end if;
when X"27" => -- Escape For auto switch from File Manager to Console
if KEY_REL = '1' then
CONTROL(3) <= '1'; -- Switch to Lvov screen in left Win release
end if;
when others => null;
end case;
end if;
-- Cancel extended/release flags for next time
if KEY_REL = '1' then
KEYB_DATA <= x"00";
KEY_REL <= '0';
KEY_EXT <= '0';
else
KEYB_DATA <= CODE;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
-- Lvov
KEYB_D <= "11111111" and
( not Matrix(0) or (7 downto 0 => KEYB_A(0)) ) and
( not Matrix(1) or (7 downto 0 => KEYB_A(1)) ) and
( not Matrix(2) or (7 downto 0 => KEYB_A(2)) ) and
( not Matrix(3) or (7 downto 0 => KEYB_A(3)) ) and
( not Matrix(4) or (7 downto 0 => KEYB_A(4)) ) and
( not Matrix(5) or (7 downto 0 => KEYB_A(5)) ) and
( not Matrix(6) or (7 downto 0 => KEYB_A(6)) ) and
( not Matrix(7) or (7 downto 0 => KEYB_A(7)) );
KEYB_D2<= "1111" and
( not Matrix2(0) or (3 downto 0 => KEYB_A2(0)) ) and
( not Matrix2(1) or (3 downto 0 => KEYB_A2(1)) ) and
( not Matrix2(2) or (3 downto 0 => KEYB_A2(2)) ) and
( not Matrix2(3) or (3 downto 0 => KEYB_A2(3)) );
end Behavioral;
|
--
-- Copyright (C) 2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.hex_util.all;
entity conv_16to8_tb is
end entity;
architecture behavioural of conv_16to8_tb is
-- Clocks
signal sysClk : std_logic; -- main system clock
signal dispClk : std_logic; -- display version of sysClk, which transitions 4ns before it
-- 16-bit interface signals
signal data16 : std_logic_vector(15 downto 0);
signal valid16 : std_logic;
signal ready16 : std_logic;
-- 8-bit interface signals
signal data8 : std_logic_vector(7 downto 0);
signal valid8 : std_logic;
signal ready8 : std_logic;
begin
-- Instantiate the memory controller for testing
uut: entity work.conv_16to8
port map(
clk_in => sysClk,
reset_in => '0',
data16_in => data16,
valid16_in => valid16,
ready16_out => ready16,
data8_out => data8,
valid8_out => valid8,
ready8_in => ready8
);
-- Drive the clocks. In simulation, sysClk lags 4ns behind dispClk, to give a visual hold time
-- for signals in GTKWave.
process
begin
sysClk <= '0';
dispClk <= '0';
wait for 16 ns;
loop
dispClk <= not(dispClk); -- first dispClk transitions
wait for 4 ns;
sysClk <= not(sysClk); -- then sysClk transitions, 4ns later
wait for 6 ns;
end loop;
end process;
-- Drive the unit under test. Read stimulus from stimulus.sim and write results to results.sim
process
variable inLine : line;
variable outLine : line;
file inFile : text open read_mode is "stimulus.sim";
file outFile : text open write_mode is "results.sim";
begin
data16 <= (others => 'Z');
valid16 <= '0';
ready8 <= '0';
wait until rising_edge(sysClk);
while ( not endfile(inFile) ) loop
readline(inFile, inLine);
while ( inLine.all'length = 0 or inLine.all(1) = '#' or inLine.all(1) = ht or inLine.all(1) = ' ' ) loop
readline(inFile, inLine);
end loop;
data16 <= to_4(inLine.all(1)) & to_4(inLine.all(2)) & to_4(inLine.all(3)) & to_4(inLine.all(4));
valid16 <= to_1(inLine.all(6));
ready8 <= to_1(inLine.all(8));
wait for 10 ns;
write(outLine, from_4(data8(7 downto 4)) & from_4(data8(3 downto 0)));
write(outLine, ' ');
write(outLine, valid8);
write(outLine, ' ');
write(outLine, ready16);
writeline(outFile, outLine);
wait for 10 ns;
end loop;
data16 <= (others => 'Z');
valid16 <= '0';
ready8 <= '0';
wait;
end process;
end architecture;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 29/06/2015 - 20:31
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY REG IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_C : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END REG;
ARCHITECTURE ARC_REG OF REG IS
TYPE STD_REG IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL REG_1: STD_REG;
SIGNAL REG_2: STD_REG;
BEGIN
--REALIZA A LEITURA NO ENDEREO SELECIONADO
OUT_A <= REG_1(TO_INTEGER(UNSIGNED(IN_A)));
OUT_B <= REG_2(TO_INTEGER(UNSIGNED(IN_B)));
--PROCESSO DE LEITURA
PROCESS(CLK, RESET)
BEGIN
IF RESET = '1' THEN
REG_1(0) <= (OTHERS => '0');
REG_2(0) <= (OTHERS => '0');
--t0
REG_1(8) <= (0 => '1', OTHERS => '0'); --NO TEMOS A FUNO ADDI, ENTO
REG_2(8) <= (0 => '1', OTHERS => '0'); --TEM QUE SER NA FORA BRUTA
--t1
REG_1(9) <= (0 => '1', 1 => '1', OTHERS => '0');
REG_2(9) <= (0 => '1', 1 => '1', OTHERS => '0');
--s1
REG_1(17) <= X"FFFF0000";
REG_2(17) <= X"FFFF0000";
ELSIF CLK'EVENT AND CLK = '0' AND RegWrite = '1' THEN
REG_1(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
REG_2(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
END IF;
END PROCESS;
END ARC_REG;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 29/06/2015 - 20:31
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY REG IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
RegWrite : IN STD_LOGIC;
IN_A : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_B : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_C : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
IN_D : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_A : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
OUT_B : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END REG;
ARCHITECTURE ARC_REG OF REG IS
TYPE STD_REG IS ARRAY(0 TO 31) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
SIGNAL REG_1: STD_REG;
SIGNAL REG_2: STD_REG;
BEGIN
--REALIZA A LEITURA NO ENDEREO SELECIONADO
OUT_A <= REG_1(TO_INTEGER(UNSIGNED(IN_A)));
OUT_B <= REG_2(TO_INTEGER(UNSIGNED(IN_B)));
--PROCESSO DE LEITURA
PROCESS(CLK, RESET)
BEGIN
IF RESET = '1' THEN
REG_1(0) <= (OTHERS => '0');
REG_2(0) <= (OTHERS => '0');
--t0
REG_1(8) <= (0 => '1', OTHERS => '0'); --NO TEMOS A FUNO ADDI, ENTO
REG_2(8) <= (0 => '1', OTHERS => '0'); --TEM QUE SER NA FORA BRUTA
--t1
REG_1(9) <= (0 => '1', 1 => '1', OTHERS => '0');
REG_2(9) <= (0 => '1', 1 => '1', OTHERS => '0');
--s1
REG_1(17) <= X"FFFF0000";
REG_2(17) <= X"FFFF0000";
ELSIF CLK'EVENT AND CLK = '0' AND RegWrite = '1' THEN
REG_1(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
REG_2(TO_INTEGER(UNSIGNED(IN_C))) <= IN_D;
END IF;
END PROCESS;
END ARC_REG;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------------
--
--
-- Definition of Ports
-- FSL_Clk : Synchronous clock
-- FSL_Rst : System reset, should always come from FSL bus
-- FSL_S_Clk : Slave asynchronous clock
-- FSL_S_Read : Read signal, requiring next available input to be read
-- FSL_S_Data : Input data
-- FSL_S_CONTROL : Control Bit, indicating the input data are control word
-- FSL_S_Exists : Data Exist Bit, indicating data exist in the input FSL bus
-- FSL_M_Clk : Master asynchronous clock
-- FSL_M_Write : Write signal, enabling writing to output FSL bus
-- FSL_M_Data : Output data
-- FSL_M_Control : Control Bit, indicating the output data are contol word
-- FSL_M_Full : Full Bit, indicating output FSL bus is full
--
-------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Entity Section
------------------------------------------------------------------------------
entity hw_acc_quicksort is
port
(
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add or delete.
Clk : in std_logic;
RST : in std_logic;
BRAM_A_addr : out std_logic_vector(0 to (32 - 1));
BRAM_A_dIN : in std_logic_vector(0 to (32 - 1));
BRAM_A_dOUT : out std_logic_vector(0 to (32 - 1));
BRAM_A_en : out std_logic;
BRAM_A_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
BRAM_B_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_B_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_B_en : out std_logic ;
BRAM_B_wEN : out std_logic_vector(0 to (32/8) -1);
BRAM_C_dIN : in std_logic_vector(0 to (32 - 1)) ;
BRAM_C_addr : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_dOUT : out std_logic_vector(0 to (32 - 1)) ;
BRAM_C_en : out std_logic ;
BRAM_C_wEN : out std_logic_vector(0 to (32/8) -1);
------------------------------------------------------
FSL0_S_Read : out std_logic;
FSL0_S_Data : in std_logic_vector(0 to 31);
FSL0_S_Exists : in std_logic;
------------------------------------------------------
FSL0_M_Write : out std_logic;
FSL0_M_Data : out std_logic_vector(0 to 31);
FSL0_M_Full : in std_logic;
--This is just used for reseting
FSL1_S_Read : out std_logic;
FSL1_S_Data : in std_logic_vector(0 to 31);
FSL1_S_Exists : in std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end hw_acc_quicksort;
-- *************************
-- Architecture Definition
-- *************************
architecture IMPLEMENTATION of hw_acc_quicksort is
component quicksort is
port
(
array_addr0 : out std_logic_vector(0 to (32 - 1));
array_dIN0 : out std_logic_vector(0 to (32- 1));
array_dOUT0 : in std_logic_vector(0 to (32 - 1));
array_rENA0 : out std_logic;
array_wENA0 : out std_logic_vector(0 to (32/8) -1);
chan1_channelDataIn : out std_logic_vector(0 to (32 - 1));
chan1_channelDataOut : in std_logic_vector(0 to (32 - 1));
chan1_exists : in std_logic;
chan1_full : in std_logic;
chan1_channelRead : out std_logic;
chan1_channelWrite : out std_logic;
clock_sig : in std_logic;
reset_sig : in std_logic
);
end component;
signal reset_sig : std_logic;
-- Architecture Section
begin
reset_sig <= rst or FSL1_S_Exists;
FSL1_S_read <= FSL1_S_Exists ;
uut : quicksort
port map (
array_addr0 => BRAM_A_addr,
array_dIN0 => BRAM_A_dout,
array_dOUT0 => BRAM_A_din,
array_rENA0 => BRAM_A_en,
array_wENA0 => BRAM_A_wen,
chan1_channelDataIn => FSL0_M_Data,
chan1_channelDataOut => FSL0_S_Data,
chan1_exists => FSL0_S_Exists,
chan1_full => FSL0_M_Full,
chan1_channelRead => FSL0_S_Read,
chan1_channelWrite => FSL0_M_Write,
clock_sig => clk,
reset_sig => reset_sig
);
end architecture implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.cart_slot_pkg.all;
entity cart_slot_registers is
generic (
g_rom_base : unsigned(27 downto 0) := X"0F80000";
g_ram_base : unsigned(27 downto 0) := X"0F70000";
g_ram_expansion : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp;
control : out t_cart_control;
status : in t_cart_status );
end entity;
architecture rtl of cart_slot_registers is
signal control_i : t_cart_control;
begin
control <= control_i;
p_bus: process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
control_i.cartridge_kill <= '0';
if io_req.write='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
if io_req.data(2)='1' then
control_i.c64_reset <= '1';
elsif io_req.data(3)='1' then
control_i.c64_reset <= '0';
else
control_i.c64_ultimax <= io_req.data(1);
control_i.c64_nmi <= io_req.data(4);
end if;
when c_cart_c64_stop =>
control_i.c64_stop <= io_req.data(0);
when c_cart_c64_stop_mode =>
control_i.c64_stop_mode <= io_req.data(1 downto 0);
when c_cart_cartridge_type =>
control_i.cartridge_type <= io_req.data(3 downto 0);
when c_cart_cartridge_kill =>
control_i.cartridge_kill <= '1';
when c_cart_kernal_enable =>
control_i.kernal_enable <= io_req.data(0);
when c_cart_reu_enable =>
control_i.reu_enable <= io_req.data(0);
when c_cart_reu_size =>
control_i.reu_size <= io_req.data(2 downto 0);
when c_cart_ethernet_enable =>
control_i.eth_enable <= io_req.data(0);
when c_cart_timing =>
control_i.timing_addr_valid <= unsigned(io_req.data(2 downto 0));
when c_cart_phi2_recover =>
control_i.phi2_edge_recover <= io_req.data(0);
control_i.tick_ntsc <= io_req.data(1);
when c_cart_swap_buttons =>
control_i.swap_buttons <= io_req.data(0);
when c_cart_sampler_enable =>
control_i.sampler_enable <= io_req.data(0);
when others =>
null;
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_cart_c64_mode =>
io_resp.data(1) <= control_i.c64_ultimax;
io_resp.data(2) <= control_i.c64_reset;
io_resp.data(4) <= control_i.c64_nmi;
when c_cart_c64_stop =>
io_resp.data(0) <= control_i.c64_stop;
io_resp.data(1) <= status.c64_stopped;
when c_cart_c64_stop_mode =>
io_resp.data(1 downto 0) <= control_i.c64_stop_mode;
when c_cart_c64_clock_detect =>
io_resp.data(0) <= status.clock_detect;
when c_cart_cartridge_rom_base =>
io_resp.data <= std_logic_vector(g_rom_base(23 downto 16));
when c_cart_cartridge_type =>
io_resp.data(3 downto 0) <= control_i.cartridge_type;
when c_cart_cartridge_active =>
io_resp.data(0) <= status.cart_active;
when c_cart_kernal_enable =>
io_resp.data(0) <= control_i.kernal_enable;
when c_cart_reu_enable =>
io_resp.data(0) <= control_i.reu_enable;
when c_cart_reu_size =>
io_resp.data(2 downto 0) <= control_i.reu_size;
when c_cart_ethernet_enable =>
io_resp.data(0) <= control_i.eth_enable;
when c_cart_sampler_enable =>
io_resp.data(0) <= control_i.sampler_enable;
when c_cart_timing =>
io_resp.data(2 downto 0) <= std_logic_vector(control_i.timing_addr_valid);
when c_cart_phi2_recover =>
io_resp.data(0) <= control_i.phi2_edge_recover;
io_resp.data(1) <= control_i.tick_ntsc;
when c_cart_swap_buttons =>
io_resp.data(0) <= control_i.swap_buttons;
when others =>
null;
end case;
end if;
if reset='1' then
control_i <= c_cart_control_init;
end if;
end if;
end process;
end architecture;
|
-- Copyright (c) 2014 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for 'range, 'reverse_range, 'left and 'right attributes in VHDL.
library ieee;
use ieee.std_logic_1164.all;
use work.vhdl_range_pkg.all;
entity range_entity is
port (gen_vals: in std_logic);
end range_entity;
architecture test of range_entity is
type int_array is array (integer range <>) of integer;
signal ascending : int_array(2 to 4);
signal descending : int_array(9 downto 3);
signal ascending_rev : int_array(8 to 13);
signal descending_rev : int_array(15 downto 10);
signal left_asc, right_asc, left_dsc, right_dsc : integer;
-- There is no limited ranged integer in SystemVerilog, so just see if it compiles
signal int_asc : integer_asc;
signal int_desc : integer_desc;
begin
process(gen_vals) begin
left_asc <= ascending'left;
right_asc <= ascending'right;
left_dsc <= descending'left;
right_dsc <= descending'right;
-- 'range test
for i in ascending'range loop
ascending(i) <= i * 2;
end loop;
for i in descending'range loop
descending(i) <= i * 3;
end loop;
-- 'reverse_range test
for i in ascending_rev'reverse_range loop
ascending_rev(i) <= i * 4;
end loop;
for i in descending_rev'reverse_range loop
descending_rev(i) <= i * 5;
end loop;
end process;
end test;
|
-- megafunction wizard: %RAM: 1-PORT%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altsyncram
-- ============================================================
-- File Name: datamem.vhd
-- Megafunction Name(s):
-- altsyncram
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 18.0.0 Build 614 04/24/2018 SJ Lite Edition
-- ************************************************************
--Copyright (C) 2018 Intel Corporation. All rights reserved.
--Your use of Intel Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Intel Program License
--Subscription Agreement, the Intel Quartus Prime License Agreement,
--the Intel FPGA IP License Agreement, or other applicable license
--agreement, including, without limitation, that your use is for
--the sole purpose of programming logic devices manufactured by
--Intel and sold by Intel or its authorized distributors. Please
--refer to the applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
ENTITY datamem IS
PORT
(
address : IN STD_LOGIC_VECTOR (10 DOWNTO 0);
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '1';
data : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
wren : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END datamem;
ARCHITECTURE SYN OF datamem IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
q <= sub_wire0(7 DOWNTO 0);
altsyncram_component : altsyncram
GENERIC MAP (
clock_enable_input_a => "NORMAL",
clock_enable_output_a => "BYPASS",
intended_device_family => "Cyclone V",
lpm_hint => "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA",
lpm_type => "altsyncram",
numwords_a => 2048,
operation_mode => "SINGLE_PORT",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE",
read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
widthad_a => 11,
width_a => 8,
width_byteena_a => 1
)
PORT MAP (
address_a => address,
clock0 => clock,
clocken0 => clken,
data_a => data,
wren_a => wren,
q_a => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "1"
-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
-- Retrieval info: PRIVATE: Clken NUMERIC "1"
-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "1"
-- Retrieval info: PRIVATE: JTAG_ID STRING "DATA"
-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
-- Retrieval info: PRIVATE: MIFfilename STRING "datamem.mif"
-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
-- Retrieval info: PRIVATE: RegData NUMERIC "1"
-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
-- Retrieval info: PRIVATE: rden NUMERIC "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "NORMAL"
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=DATA"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC "clken"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clocken0 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem.bsf FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL datamem_inst.vhd FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2550.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p08n01i02550ent IS
END c07s03b05x00p08n01i02550ent;
ARCHITECTURE c07s03b05x00p08n01i02550arch OF c07s03b05x00p08n01i02550ent IS
BEGIN
TESTING: PROCESS
type century is array (1 to 5) of integer ;
type millenia is array (5 downto 1) of integer;
variable hundreds : century := (1,1,1,1,1);
variable thousand : millenia ;
BEGIN
thousand := millenia (hundreds);
assert NOT(thousand = (1,1,1,1,1))
report "***PASSED TEST: c07s03b05x00p08n01i02550"
severity NOTE;
assert (thousand = (1,1,1,1,1))
report "***FAILED TEST: c07s03b05x00p08n01i02550 - Operand and the target type should have the same index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p08n01i02550arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2550.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p08n01i02550ent IS
END c07s03b05x00p08n01i02550ent;
ARCHITECTURE c07s03b05x00p08n01i02550arch OF c07s03b05x00p08n01i02550ent IS
BEGIN
TESTING: PROCESS
type century is array (1 to 5) of integer ;
type millenia is array (5 downto 1) of integer;
variable hundreds : century := (1,1,1,1,1);
variable thousand : millenia ;
BEGIN
thousand := millenia (hundreds);
assert NOT(thousand = (1,1,1,1,1))
report "***PASSED TEST: c07s03b05x00p08n01i02550"
severity NOTE;
assert (thousand = (1,1,1,1,1))
report "***FAILED TEST: c07s03b05x00p08n01i02550 - Operand and the target type should have the same index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p08n01i02550arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2550.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p08n01i02550ent IS
END c07s03b05x00p08n01i02550ent;
ARCHITECTURE c07s03b05x00p08n01i02550arch OF c07s03b05x00p08n01i02550ent IS
BEGIN
TESTING: PROCESS
type century is array (1 to 5) of integer ;
type millenia is array (5 downto 1) of integer;
variable hundreds : century := (1,1,1,1,1);
variable thousand : millenia ;
BEGIN
thousand := millenia (hundreds);
assert NOT(thousand = (1,1,1,1,1))
report "***PASSED TEST: c07s03b05x00p08n01i02550"
severity NOTE;
assert (thousand = (1,1,1,1,1))
report "***FAILED TEST: c07s03b05x00p08n01i02550 - Operand and the target type should have the same index type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p08n01i02550arch;
|
-- file: dcm0.vhd
--
-- DISCLAIMER OF LIABILITY
--
-- This file contains proprietary and confidential information of
-- Xilinx, Inc. ("Xilinx"), that is distributed under a license
-- from Xilinx, and may be used, copied and/or disclosed only
-- pursuant to the terms of a valid license agreement with Xilinx.
--
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
-- ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
-- EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
-- LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
-- MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
-- does not warrant that functions included in the Materials will
-- meet the requirements of Licensee, or that the operation of the
-- Materials will be uninterrupted or error-free, or that defects
-- in the Materials will be corrected. Furthermore, Xilinx does
-- not warrant or make any representations regarding use, or the
-- results of the use, of the Materials in terms of correctness,
-- accuracy, reliability or otherwise.
--
-- Xilinx products are not designed or intended to be fail-safe,
-- or for use in any application requiring fail-safe performance,
-- such as life-support or safety devices or systems, Class III
-- medical devices, nuclear facilities, applications related to
-- the deployment of airbags, or any other applications that could
-- lead to death, personal injury or severe property or
-- environmental damage (individually and collectively, "critical
-- applications"). Customer assumes the sole risk and liability
-- of any use of Xilinx products in critical applications,
-- subject only to applicable laws and regulations governing
-- limitations on product liability.
--
-- Copyright 2008, 2009 Xilinx, Inc.
-- All rights reserved.
--
-- This disclaimer and copyright notice must be retained as part
-- of this file at all times.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1 200.000 0.000 N/A 217.125 N/A
-- CLK_OUT2 50.000 0.000 N/A 207.125 N/A
--
------------------------------------------------------------------------------
-- Input Clock Input Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- primary 48.000 0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity dcm0 is
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic;
CLK_VALID : out std_logic
);
end dcm0;
architecture xilinx of dcm0 is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm0,clk_wiz_v1_4,{component_name=dcm0,use_phase_alignment=false,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,diff_ext_feedback=false,primtype_sel=DCM_CLKGEN,num_out_clk=2,clkin1_period=20.83333,clkin2_period=20.83333,use_power_down=false}";
-- Input clock buffering / unused connectors
signal clkin1 : std_logic;
-- Output clock buffering / unused connectors
signal clkfx : std_logic;
signal clkfx180_unused : std_logic;
signal clkfxdv : std_logic;
signal clkfbout : std_logic;
-- Dynamic programming unused signals
signal progdone_unused : std_logic;
signal locked_internal : std_logic;
signal status_internal : std_logic_vector(2 downto 1);
begin
-- Input buffering
--------------------------------------
clkin1_buf : IBUFG
port map
(O => clkin1,
I => CLK_IN1);
-- Clocking primitive
--------------------------------------
-- Instantiation of the DCM primitive
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
dcm_clkgen_inst: DCM_CLKGEN
generic map
(CLKFXDV_DIVIDE => 4,
CLKFX_DIVIDE => 6,
CLKFX_MULTIPLY => 25,
SPREAD_SPECTRUM => "NONE",
STARTUP_WAIT => FALSE,
CLKIN_PERIOD => 20.83333,
CLKFX_MD_MAX => 0.000)
port map
-- Input clock
(CLKIN => clkin1,
-- Output clocks
CLKFX => clkfx,
CLKFX180 => clkfx180_unused,
CLKFXDV => clkfxdv,
-- Ports for dynamic phase shift
PROGCLK => '0',
PROGEN => '0',
PROGDATA => '0',
PROGDONE => progdone_unused,
-- Other control and status signals
FREEZEDCM => '0',
LOCKED => locked_internal,
STATUS => status_internal,
RST => RESET);
LOCKED <= locked_internal;
CLK_VALID <= ( locked_internal and ( not status_internal(2) ) );
-- Output buffering
-------------------------------------
clkout1_buf : AUTOBUF
generic map
(BUFFER_TYPE => "BUFG")
port map
(O => CLK_OUT1,
I => clkfx);
clkout2_buf : AUTOBUF
generic map
(BUFFER_TYPE => "BUFG")
port map
(O => CLK_OUT2,
I => clkfxdv);
end xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
--SPI (no MISO)
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD: in STD_LOGIC; -- Active low
-- VGA
PIXEL : inout STD_LOGIC_VECTOR(7 downto 0);
HSYNC : inout STD_LOGIC;
VSYNC : inout STD_LOGIC;
--CPLD_GPIO : out STD_LOGIC_VECTOR(16 downto 16) := "0";
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SCK : IN std_logic;
SEL : IN std_logic;
MOSI : IN std_logic;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
MISO : OUT std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code
-- Just VGA for now
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
PIXEL : INOUT std_logic_vector(7 downto 0);
HSYNC : INOUT std_logic;
VSYNC : INOUT std_logic;
--CPLD_GPIO : OUT std_logic_vector(16 to 16);
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and VGA output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SCK => EXT_SCK,
SEL => EXT_SEL_CPLD,
MOSI => EXT_MOSI,
MISO => EXT_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
PIXEL => PIXEL,
HSYNC => HSYNC,
VSYNC => VSYNC,
--CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- In/out for top level module
entity VGAtonic_Firmware is
PORT(
CLK : in STD_LOGIC;
--SPI (no MISO)
EXT_SCK : in STD_LOGIC;
EXT_MOSI : in STD_LOGIC;
EXT_MISO : out STD_LOGIC := '0';
EXT_SEL_CPLD: in STD_LOGIC; -- Active low
-- VGA
PIXEL : inout STD_LOGIC_VECTOR(7 downto 0);
HSYNC : inout STD_LOGIC;
VSYNC : inout STD_LOGIC;
--CPLD_GPIO : out STD_LOGIC_VECTOR(16 downto 16) := "0";
-- Memory
DATA : inout STD_LOGIC_VECTOR(7 downto 0);
ADDR : out STD_LOGIC_VECTOR(18 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
end VGAtonic_Firmware;
architecture Behavioral of VGAtonic_Firmware is
-- Handshaking signals from SPI
signal SPI_DATA_CACHE : STD_LOGIC_VECTOR(7 downto 0);
signal SPI_CACHE_FULL_FLAG : STD_LOGIC;
signal SPI_CMD_RESET_FLAG : STD_LOGIC;
-- Handshaking signals to SPI
signal ACK_USER_RESET : STD_LOGIC;
signal ACK_SPI_BYTE : STD_LOGIC;
-- Instantiating our SPI slave code (see earlier entries)
COMPONENT SPI_Slave
PORT(
SCK : IN std_logic;
SEL : IN std_logic;
MOSI : IN std_logic;
ACK_USER_RESET : IN std_logic;
ACK_SPI_BYTE : IN std_logic;
MISO : OUT std_logic;
SPI_DATA_CACHE : OUT std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : OUT std_logic;
SPI_CMD_RESET_FLAG : OUT std_logic
);
END COMPONENT;
-- Instantiating our Display Controller code
-- Just VGA for now
COMPONENT Display_Controller
PORT(
CLK : IN std_logic;
SPI_DATA_CACHE : IN std_logic_vector(7 downto 0);
SPI_CACHE_FULL_FLAG : IN std_logic;
SPI_CMD_RESET_FLAG : IN std_logic;
PIXEL : INOUT std_logic_vector(7 downto 0);
HSYNC : INOUT std_logic;
VSYNC : INOUT std_logic;
--CPLD_GPIO : OUT std_logic_vector(16 to 16);
ACK_USER_RESET : INOUT std_logic;
ACK_SPI_BYTE : OUT std_logic;
ADDR : OUT std_logic_vector(18 downto 0);
DATA : INOUT std_logic_vector(7 downto 0);
OE_LOW : out STD_LOGIC := '1';
WE_LOW : out STD_LOGIC := '1';
CE_LOW : out STD_LOGIC := '1'
);
END COMPONENT;
begin
-- Nothing special here; we don't even really change the names of the signals.
-- Here we map all of the internal and external signals to the respective
-- modules for SPI input and VGA output.
Inst_SPI_Slave: SPI_Slave PORT MAP(
SCK => EXT_SCK,
SEL => EXT_SEL_CPLD,
MOSI => EXT_MOSI,
MISO => EXT_MISO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE
);
Inst_Display_Controller: Display_Controller PORT MAP(
CLK => CLK,
PIXEL => PIXEL,
HSYNC => HSYNC,
VSYNC => VSYNC,
--CPLD_GPIO => CPLD_GPIO,
SPI_DATA_CACHE => SPI_DATA_CACHE,
SPI_CACHE_FULL_FLAG => SPI_CACHE_FULL_FLAG,
SPI_CMD_RESET_FLAG => SPI_CMD_RESET_FLAG,
ACK_USER_RESET => ACK_USER_RESET,
ACK_SPI_BYTE => ACK_SPI_BYTE,
DATA => DATA,
ADDR => ADDR,
OE_LOW => OE_LOW,
WE_LOW => WE_LOW,
CE_LOW => CE_LOW
);
end Behavioral;
|
package synopsys1 is
type std_ulogic_vector is array (natural range <>) of bit;
type line is access string;
type side is (left, right);
subtype width is natural;
end package;
package body synopsys1 is
type char_indexed_by_MVL9 is array (bit) of character;
constant MVL9_to_char: char_indexed_by_MVL9 := "01";
procedure WRITE(L:inout LINE; VALUE:in STD_ULOGIC_VECTOR;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0) is
variable s: string(1 to value'length);
variable m: STD_ULOGIC_VECTOR(1 to value'length) := value;
begin
for i in 1 to value'length loop
s(i) := MVL9_to_char(m(i));
end loop;
--write(l, s, justified, field);
end WRITE;
end package body;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for pads_eastnord
--
-- Generated
-- by: wig
-- on: Thu Jan 19 07:44:48 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -strip -nodelta ../padio2.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: pads_eastnord-e.vhd,v 1.4 2006/01/19 08:50:41 wig Exp $
-- $Date: 2006/01/19 08:50:41 $
-- $Log: pads_eastnord-e.vhd,v $
-- Revision 1.4 2006/01/19 08:50:41 wig
-- Updated testcases, left 6 failing now (constant, bitsplice/X, ...)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.75 2006/01/18 16:59:29 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.43 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- Generated use statements
library work;
use work.vst_5lm_io_components.all;
--
--
-- Start of Generated Entity pads_eastnord
--
entity pads_eastnord is
-- Generics:
-- No Generated Generics for Entity pads_eastnord
-- Generated Port Declaration:
port(
-- Generated Port for Entity pads_eastnord
clkf81_gi : in std_ulogic;
clockdr_i_gi : in std_ulogic;
db2o_10 : inout std_ulogic; -- Flat Panel
db2o_11 : inout std_ulogic; -- Flat Panel
db2o_12 : inout std_ulogic; -- Flat Panel
db2o_13 : inout std_ulogic; -- Flat Panel
db2o_14 : inout std_ulogic; -- Flat Panel
db2o_15 : inout std_ulogic; -- Flat Panel
db2o_i : in std_ulogic_vector(15 downto 10); -- padin
db2o_o : out std_ulogic_vector(15 downto 10); -- padout
dbo_10 : inout std_ulogic; -- Flat Panel
dbo_11 : inout std_ulogic; -- Flat Panel
dbo_12 : inout std_ulogic; -- Flat Panel
dbo_13 : inout std_ulogic; -- Flat Panel
dbo_14 : inout std_ulogic; -- Flat Panel
dbo_15 : inout std_ulogic; -- Flat Panel
dbo_i : in std_ulogic_vector(15 downto 10); -- padin
dbo_o_15_10_go : out std_ulogic_vector(5 downto 0);
default_gi : in std_ulogic;
mode_1_i_gi : in std_ulogic;
mode_2_i_gi : in std_ulogic;
mode_3_i_gi : in std_ulogic;
pmux_sel_por_gi : in std_ulogic;
res_f81_n_gi : in std_ulogic;
rgbout_byp_i_gi : in std_ulogic;
rgbout_iddq_i_gi : in std_ulogic;
rgbout_sio_i_gi : in std_ulogic;
scan_en_i_gi : in std_ulogic;
shiftdr_i_gi : in std_ulogic;
tck_i_gi : in std_ulogic;
updatedr_i_gi : in std_ulogic;
varclk_i_gi : in std_ulogic
-- End of Generated Port for Entity pads_eastnord
);
end pads_eastnord;
--
-- End of Generated Entity pads_eastnord
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
architecture rtl of fifo is
begin
process begin
for x in (11 downto 0) loop end loop;
for x in (11 downto 0) loop end loop;
end process;
end;
|
--================================================================================================================================
-- Copyright 2020 Bitvis
-- Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 and in the provided LICENSE.TXT.
--
-- Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on
-- an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and limitations under the License.
--================================================================================================================================
-- Note : Any functionality not explicitly described in the documentation is subject to change at any time
----------------------------------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
---------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--========================================================================================================================
--========================================================================================================================
package support_pkg is
--========================================================================================================================
-- Types and constants
--========================================================================================================================
-- The preamble & SFD sequence is represented with the LSb transmitted first
constant C_PREAMBLE : std_logic_vector(55 downto 0) := x"55_55_55_55_55_55_55";
constant C_SFD : std_logic_vector( 7 downto 0) := x"D5";
-- Sizes in bytes
constant C_MIN_PAYLOAD_LENGTH : natural := 46;
constant C_MAX_PAYLOAD_LENGTH : natural := 1500;
constant C_MAX_FRAME_LENGTH : natural := C_MAX_PAYLOAD_LENGTH + 18;
constant C_MAX_PACKET_LENGTH : natural := C_MAX_FRAME_LENGTH + 8;
-- IF field index config
constant C_FIELD_IDX_PREAMBLE_AND_SFD : natural := 0;
constant C_FIELD_IDX_MAC_DESTINATION : natural := 1;
constant C_FIELD_IDX_MAC_SOURCE : natural := 2;
constant C_FIELD_IDX_PAYLOAD_LENGTH : natural := 3;
constant C_FIELD_IDX_PAYLOAD : natural := 4;
constant C_FIELD_IDX_FCS : natural := 5;
type t_ethernet_frame is record
mac_destination : unsigned(47 downto 0);
mac_source : unsigned(47 downto 0);
payload_length : integer;
payload : t_byte_array(0 to C_MAX_PAYLOAD_LENGTH-1);
fcs : std_logic_vector(31 downto 0);
end record t_ethernet_frame;
constant C_ETHERNET_FRAME_DEFAULT : t_ethernet_frame := (
mac_destination => (others => '0'),
mac_source => (others => '0'),
payload_length => 0,
payload => (others => (others => '0')),
fcs => (others => '0'));
type t_ethernet_frame_status is record
fcs_error : boolean;
end record t_ethernet_frame_status;
-- Configuration record to be assigned in the test harness
type t_ethernet_protocol_config is record
mac_destination : unsigned(47 downto 0);
mac_source : unsigned(47 downto 0);
fcs_error_severity : t_alert_level;
interpacket_gap_time : time;
end record;
constant C_ETHERNET_PROTOCOL_CONFIG_DEFAULT : t_ethernet_protocol_config := (
mac_destination => (others => '0'),
mac_source => (others => '0'),
fcs_error_severity => ERROR,
interpacket_gap_time => 96 ns -- Standard minimum interpacket gap (Gigabith Ethernet)
);
--========================================================================================================================
-- Functions and procedures
--========================================================================================================================
impure function generate_crc_32(
constant data_array : in t_byte_array
) return std_logic_vector;
impure function check_crc_32(
constant data_array : in t_byte_array
) return boolean;
function get_ethernet_frame_length(
constant payload_length : in positive
) return positive;
function to_string(
constant ethernet_frame : in t_ethernet_frame;
constant frame_field : in t_frame_field
) return string;
function to_string(
constant ethernet_frame : in t_ethernet_frame
) return string;
procedure compare_ethernet_frames(
constant actual : in t_ethernet_frame;
constant expected : in t_ethernet_frame;
constant alert_level : in t_alert_level;
constant msg_id : in t_msg_id;
constant msg : in string;
constant scope : in string;
constant msg_id_panel : in t_msg_id_panel
);
function ethernet_match(
constant actual : in t_ethernet_frame;
constant expected : in t_ethernet_frame
) return boolean;
end package support_pkg;
--========================================================================================================================
--========================================================================================================================
package body support_pkg is
-- Returns the IEEE 802.3 CRC32 for an ascending byte array input with LSb first.
impure function generate_crc_32(
constant data_array : in t_byte_array
) return std_logic_vector is
begin
-- The function generate_crc() generates CRC from high to low (MSb first),
-- however the Ethernet standard uses LSb first for the frame data so we need
-- to reverse the bits in each byte.
return generate_crc(reverse_vectors_in_array(data_array), C_CRC_32_START_VALUE, C_CRC_32_POLYNOMIAL);
end function generate_crc_32;
-- Generates the IEEE 802.3 CRC32 for an ascending byte array containing
-- the frame data and the FCS. Returns true if the result is equal to the
-- expected residue.
impure function check_crc_32(
constant data_array : in t_byte_array
) return boolean is
begin
return generate_crc_32(data_array) = C_CRC_32_RESIDUE;
end function check_crc_32;
-- Returns the complete frame length
function get_ethernet_frame_length(
constant payload_length : in positive
) return positive is
begin
return payload_length + 18;
end function get_ethernet_frame_length;
-- Returns a string with a specific field from the frame
function to_string(
constant ethernet_frame : in t_ethernet_frame;
constant frame_field : in t_frame_field
) return string is
variable payload_string : string(1 to 14*ethernet_frame.payload_length); --[1500]:x"00",
variable v_line : line;
variable v_line_width : natural;
begin
case frame_field is
when HEADER =>
return LF & " MAC destination: " & to_string(ethernet_frame.mac_destination, HEX, KEEP_LEADING_0, INCL_RADIX) &
LF & " MAC source: " & to_string(ethernet_frame.mac_source, HEX, KEEP_LEADING_0, INCL_RADIX) &
LF & " payload length: " & to_string(ethernet_frame.payload_length);
when PAYLOAD =>
write(v_line, string'("[" & to_string(0) & "]:" & to_string(ethernet_frame.payload(0), HEX, AS_IS, INCL_RADIX)));
if ethernet_frame.payload_length > 1 then
for i in 1 to ethernet_frame.payload_length-1 loop
write(v_line, string'(", [" & to_string(i) & "]:" & to_string(ethernet_frame.payload(i), HEX, AS_IS, INCL_RADIX)));
end loop;
end if;
v_line_width := v_line'length;
payload_string(1 to v_line_width) := v_line.all;
deallocate(v_line);
return LF & payload_string(1 to v_line_width);
when CHECKSUM =>
return LF & " FCS: " & to_string(ethernet_frame.fcs, HEX, AS_IS, INCL_RADIX);
when others =>
return "";
end case;
end function to_string;
-- Returns a string with the main frame info (used in scoreboard)
function to_string(
constant ethernet_frame : in t_ethernet_frame
) return string is
begin
return "MAC dest: " & to_string(ethernet_frame.mac_destination, HEX, AS_IS, INCL_RADIX) &
", MAC src: " & to_string(ethernet_frame.mac_source, HEX, AS_IS, INCL_RADIX) &
", payload length: " & to_string(ethernet_frame.payload_length);
end function to_string;
-- Compares two ethernet frames
procedure compare_ethernet_frames(
constant actual : in t_ethernet_frame;
constant expected : in t_ethernet_frame;
constant alert_level : in t_alert_level;
constant msg_id : in t_msg_id;
constant msg : in string;
constant scope : in string;
constant msg_id_panel : in t_msg_id_panel
) is
constant proc_call : string := "compare_ethernet_frames()";
variable v_check_ok : boolean := true;
begin
v_check_ok := v_check_ok and check_value(actual.mac_destination, expected.mac_destination, alert_level, "Verify MAC destination" & LF & msg, scope, HEX, KEEP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
v_check_ok := v_check_ok and check_value(actual.mac_source, expected.mac_source, alert_level, "Verify MAC source" & LF & msg, scope, HEX, KEEP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
v_check_ok := v_check_ok and check_value(actual.payload_length, expected.payload_length, alert_level, "Verify payload length" & LF & msg, scope, ID_NEVER, msg_id_panel, proc_call);
for i in 0 to actual.payload_length-1 loop
v_check_ok := v_check_ok and check_value(actual.payload(i), expected.payload(i), alert_level, "Verify payload byte " & to_string(i) & LF & msg, scope, HEX, KEEP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
end loop;
v_check_ok := v_check_ok and check_value(actual.fcs, expected.fcs, alert_level, "Verify FCS" & LF & msg, scope, HEX, KEEP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
if v_check_ok then
log(msg_id, proc_call & ". " & add_msg_delimiter(msg) & " => OK");
else
log(msg_id, proc_call & ". " & add_msg_delimiter(msg) & " => FAILED");
end if;
end procedure compare_ethernet_frames;
-- Compares two ethernet frames and returns true if they are equal (used in scoreboard)
function ethernet_match(
constant actual : in t_ethernet_frame;
constant expected : in t_ethernet_frame
) return boolean is
begin
return actual.mac_destination = expected.mac_destination and
actual.mac_source = expected.mac_source and
actual.payload_length = expected.payload_length and
actual.payload(0 to actual.payload_length-1) = expected.payload(0 to expected.payload_length-1) and
actual.fcs = expected.fcs;
end function ethernet_match;
end package body support_pkg; |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 09:39:36 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zynq_design_1_axi_bram_ctrl_0_bram_0_stub.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_bram_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,rsta,ena,wea[3:0],addra[31:0],dina[31:0],douta[31:0],clkb,rstb,enb,web[3:0],addrb[31:0],dinb[31:0],doutb[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_3_6,Vivado 2017.2";
begin
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:30:51 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/PSelect/PSelect_funcsim.vhdl
-- Design : PSelect
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end PSelect_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of PSelect_blk_mem_gen_prim_wrapper_init is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"00000",
INIT_B => X"00000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"00000",
SRVAL_B => X"00000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(13 downto 4) => addra(9 downto 0),
ADDRARDADDR(3) => '0',
ADDRARDADDR(2) => '0',
ADDRARDADDR(1) => '0',
ADDRARDADDR(0) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CLKARDCLK => clka,
CLKBWRCLK => clka,
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(15 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOBDO_UNCONNECTED\(15 downto 0),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(1 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM18.ram_DOPBDOP_UNCONNECTED\(1 downto 0),
ENARDEN => '1',
ENBWREN => '0',
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"000000000000000000BBBB888844447777666666667777000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"7F0FE0007F0FE0007F00FFFF7F00FFFF7F00FFFF7F00FFFF0000000000000000",
INIT_13 => X"7F00FFFC7F00FFFC7F0FE0007F0FE0007F0FE0007F0FE0007F0FE0007F0FE000",
INIT_14 => X"F800003FF800003F7F00003F7F00003F7F00003F7F00003F7F00FFFC7F00FFFC",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000111111111111111111111111000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"00001FC000001FC000001FC000001FC000001FC000001FC00000000000000000",
INIT_13 => X"00001FC000001FC000001FC000001FC000001FC000001FC000001FC000001FC0",
INIT_14 => X"000001FF000001FF00001FC000001FC000001FC000001FC000001FC000001FC0",
INIT_15 => X"00000000000000000000003F0000003F0000003F0000003F000001FF000001FF",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"4CCCC44444444000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000044444444444444444444444",
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INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0FFE000000FE000000FE000000FE000000FE0000000000000000000000000000",
INIT_07 => X"00FE0000FFFE0000FFFE0000FFFE0000FFFE00000FFE00000FFE00000FFE0000",
INIT_08 => X"00FE000000FE000000FE000000FE000000FE000000FE000000FE000000FE0000",
INIT_09 => X"00FE000000FE000000FE000000FE000000FE000000FE000000FE000000FE0000",
INIT_0A => X"0000000000FE000000FE000000FE000000FE000000FE000000FE000000FE0000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000007000000070000000700000007000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"555555555FFFF000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000DDDD5555555555557777555",
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"00FE03F8C0FFFF80C0FFFF80C0FFFF80C0FFFF80000000000000000000000000",
INIT_07 => X"00FE03F800FE03F800FE03F800FE03F800FE03F800FE03F800FE03F800FE03F8",
INIT_08 => X"00FE3F8000FFFF8000FFFF8000FFFF8000FFFF8000FE03F800FE03F800FE03F8",
INIT_09 => X"00FE03F800FE03F800FE03F800FE03F800FE03F800FE3F8000FE3F8000FE3F80",
INIT_0A => X"00000000C0FE03F8C0FE03F8C0FE03F8C0FE03F800FE03F800FE03F800FE03F8",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"E0FF1FC000FF1FC000FF1FC000FF1FC000FF1FC000FFFE0000FFFE0000FFFE00",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INIT_A => X"000000000",
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INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"55555DDDD9999000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000444444444444CCCC5555555",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"000000000000000000000DDDD555555555555DDDD555555555555CCCC0000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"FF007F00F8007F00F8007F00F8007F00F8007F00000000000000000000000000",
INIT_07 => X"07F07F0007F07F0007F07F0007F07F0007F07F00FF007F00FF007F00FF007F00",
INIT_08 => X"FFF000FF07F007FF07F007FF07F007FF07F007FF07F07F0007F07F0007F07F00",
INIT_09 => X"07F000FF07F000FF07F000FF07F000FF07F000FFFFF000FFFFF000FFFFF000FF",
INIT_0A => X"0000000007F000FF07F000FF07F000FF07F000FF07F000FF07F000FF07F000FF",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"FFC0003F00000000000000000000000000000000000000000000000000000000",
INIT_39 => X"01FC1FC001FC01FF01FC01FF01FC01FF01FC01FFFFC0003FFFC0003FFFC0003F",
INIT_3A => X"FFC01FC001FC1FC001FC1FC001FC1FC001FC1FC001FC1FC001FC1FC001FC1FC0",
INIT_3B => X"01FC1FC001FC1FFF01FC1FFF01FC1FFF01FC1FFFFFC01FC0FFC01FC0FFC01FC0",
INIT_3C => X"FFC01FC001FC1FC001FC1FC001FC1FC001FC1FC001FC1FC001FC1FC001FC1FC0",
INIT_3D => X"0000000000000000000000000000000000000000FFC01FC0FFC01FC0FFC01FC0",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"9999988888888000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000FFFF9999999999999999999",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"E000003FE0000003E0000003E0000003E0000003000000000000000000000000",
INIT_07 => X"E00001FCE00001FCE00001FCE00001FCE00001FCE000003FE000003FE000003F",
INIT_08 => X"E00001FFE00001FCE00001FCE00001FCE00001FCE00001FCE00001FCE00001FC",
INIT_09 => X"E00001FCE00001FCE00001FCE00001FCE00001FCE00001FFE00001FFE00001FF",
INIT_0A => X"00000000FFFF81FCFFFF81FCFFFF81FCFFFF81FCE00001FCE00001FCE00001FC",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"000000FF00000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3B => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3C => X"000000FF000000FF000000FF000000FF000000FF000000FF000000FF000000FF",
INIT_3D => X"0000000000000000000000000000000000000000000000FF000000FF000000FF",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"6666666666666000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000044444444444444446666666",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"7F00FE0F7FFFE00F7FFFE00F7FFFE00F7FFFE00F000000000000000000000000",
INIT_07 => X"7F00FE0F7F00FE0F7F00FE0F7F00FE0F7F00FE0F7F00FE0F7F00FE0F7F00FE0F",
INIT_08 => X"7F00000F7FFFE00F7FFFE00F7FFFE00F7FFFE00F7F00FE0F7F00FE0F7F00FE0F",
INIT_09 => X"7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F",
INIT_0A => X"000000007F00000F7F00000F7F00000F7F00000F7F00000F7F00000F7F00000F",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"2AAAAAAAA6666000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000EEEE8888444444442222222",
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INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"FC07F0003FFF00003FFF00003FFF00003FFF0000000000000000000000000000",
INIT_07 => X"0007F000FC07F000FC07F000FC07F000FC07F000FC07F000FC07F000FC07F000",
INIT_08 => X"03F80000007F0000007F0000007F0000007F00000007F0000007F0000007F000",
INIT_09 => X"FC0000003F8000003F8000003F8000003F80000003F8000003F8000003F80000",
INIT_0A => X"00000000FFFFF000FFFFF000FFFFF000FFFFF000FC000000FC000000FC000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\ is
signal \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31) => \n_4_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(30) => \n_5_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(29 downto 24) => douta(25 downto 20),
DOADO(23) => \n_12_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(22 downto 16) => douta(19 downto 13),
DOADO(15) => \n_20_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(14) => \n_21_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(13 downto 8) => douta(12 downto 7),
DOADO(7) => \n_28_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOADO(6 downto 0) => douta(6 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => \n_68_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(2) => \n_69_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(1) => \n_70_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPADOP(0) => \n_71_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000100000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000001000000010000000100000001000000010000000100000001",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000100000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000001000000010000000100000001000000010000000100000001",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"333333333BBBB000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000BBBB333333333333BBBB333",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"00000000000000000000044444444000044444444CCCCCCCCCCCC44440000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"007F00FEF07FFFE0F07FFFE0F07FFFE0F07FFFE0000000000000000000000000",
INIT_07 => X"007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE007F00FE",
INIT_08 => X"007F0FE0007FFFE0007FFFE0007FFFE0007FFFE0007F00FE007F00FE007F00FE",
INIT_09 => X"007F00FE007F00FE007F00FE007F00FE007F00FE007F0FE0007F0FE0007F0FE0",
INIT_0A => X"00000000F07F00FEF07F00FEF07F00FEF07F00FE007F00FE007F00FE007F00FE",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"1FC0000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"FFFC0000FFFC0000FFFC0000FFFC0000FFFC00001FC000001FC000001FC00000",
INIT_3A => X"1FC00000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000FFFC0000",
INIT_3B => X"000000001FC000001FC000001FC000001FC000001FC000001FC000001FC00000",
INIT_3C => X"1FC000001FC000001FC000001FC000001FC00000000000000000000000000000",
INIT_3D => X"00000000000000000000000000000000000000001FC000001FC000001FC00000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"6666666667777000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000BBBBAAAAAAAAAAAABBBB666",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000006666666666666666666666666666666666660000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"01FC07F001FC7FF001FC7FF001FC7FF001FC7FF001FC000001FC000001FC0000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"8888888888888000000000000000000000000000000000000000000000000000",
INITP_01 => X"00000000000000000000000000000000000000000EEEE8888888888888888888",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"F800000FF8000000F8000000F8000000F8000000000000000000000000000000",
INIT_07 => X"F80000FFF80000FFF80000FFF80000FFF80000FFF800000FF800000FF800000F",
INIT_08 => X"F80000FFF80000FFF80000FFF80000FFF80000FFF80000FFF80000FFF80000FF",
INIT_09 => X"F80000FFF80000FFF80000FFF80000FFF80000FFF80000FFF80000FFF80000FF",
INIT_0A => X"00000000FFFFE0FFFFFFE0FFFFFFE0FFFFFFE0FFF80000FFF80000FFF80000FF",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"5555555556666000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000044444444444444446666555",
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INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"1FC07F031FFFF8031FFFF8031FFFF8031FFFF803000000000000000000000000",
INIT_07 => X"1FC07F031FC07F031FC07F031FC07F031FC07F031FC07F031FC07F031FC07F03",
INIT_08 => X"1FC000031FFFF8031FFFF8031FFFF8031FFFF8031FC07F031FC07F031FC07F03",
INIT_09 => X"1FC000031FC000031FC000031FC000031FC000031FC000031FC000031FC00003",
INIT_0A => X"000000001FC000031FC000031FC000031FC000031FC000031FC000031FC00003",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\ : entity is "blk_mem_gen_prim_wrapper_init";
end \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\ is
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000888888880000000000008888000000000000000000",
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INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 36,
READ_WIDTH_B => 36,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 36,
WRITE_WIDTH_B => 36
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 5) => addra(9 downto 0),
ADDRARDADDR(4) => '1',
ADDRARDADDR(3) => '1',
ADDRARDADDR(2) => '1',
ADDRARDADDR(1) => '1',
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '0',
ADDRBWRADDR(14) => '0',
ADDRBWRADDR(13) => '0',
ADDRBWRADDR(12) => '0',
ADDRBWRADDR(11) => '0',
ADDRBWRADDR(10) => '0',
ADDRBWRADDR(9) => '0',
ADDRBWRADDR(8) => '0',
ADDRBWRADDR(7) => '0',
ADDRBWRADDR(6) => '0',
ADDRBWRADDR(5) => '0',
ADDRBWRADDR(4) => '0',
ADDRBWRADDR(3) => '0',
ADDRBWRADDR(2) => '0',
ADDRBWRADDR(1) => '0',
ADDRBWRADDR(0) => '0',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31) => '0',
DIADI(30) => '0',
DIADI(29) => '0',
DIADI(28) => '0',
DIADI(27) => '0',
DIADI(26) => '0',
DIADI(25) => '0',
DIADI(24) => '0',
DIADI(23) => '0',
DIADI(22) => '0',
DIADI(21) => '0',
DIADI(20) => '0',
DIADI(19) => '0',
DIADI(18) => '0',
DIADI(17) => '0',
DIADI(16) => '0',
DIADI(15) => '0',
DIADI(14) => '0',
DIADI(13) => '0',
DIADI(12) => '0',
DIADI(11) => '0',
DIADI(10) => '0',
DIADI(9) => '0',
DIADI(8) => '0',
DIADI(7) => '0',
DIADI(6) => '0',
DIADI(5) => '0',
DIADI(4) => '0',
DIADI(3) => '0',
DIADI(2) => '0',
DIADI(1) => '0',
DIADI(0) => '0',
DIBDI(31) => '0',
DIBDI(30) => '0',
DIBDI(29) => '0',
DIBDI(28) => '0',
DIBDI(27) => '0',
DIBDI(26) => '0',
DIBDI(25) => '0',
DIBDI(24) => '0',
DIBDI(23) => '0',
DIBDI(22) => '0',
DIBDI(21) => '0',
DIBDI(20) => '0',
DIBDI(19) => '0',
DIBDI(18) => '0',
DIBDI(17) => '0',
DIBDI(16) => '0',
DIBDI(15) => '0',
DIBDI(14) => '0',
DIBDI(13) => '0',
DIBDI(12) => '0',
DIBDI(11) => '0',
DIBDI(10) => '0',
DIBDI(9) => '0',
DIBDI(8) => '0',
DIBDI(7) => '0',
DIBDI(6) => '0',
DIBDI(5) => '0',
DIBDI(4) => '0',
DIBDI(3) => '0',
DIBDI(2) => '0',
DIBDI(1) => '0',
DIBDI(0) => '0',
DIPADIP(3) => '0',
DIPADIP(2) => '0',
DIPADIP(1) => '0',
DIPADIP(0) => '0',
DIPBDIP(3) => '0',
DIPBDIP(2) => '0',
DIPBDIP(1) => '0',
DIPBDIP(0) => '0',
DOADO(31 downto 24) => douta(34 downto 27),
DOADO(23 downto 16) => douta(25 downto 18),
DOADO(15 downto 8) => douta(16 downto 9),
DOADO(7 downto 0) => douta(7 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3) => douta(35),
DOPADOP(2) => douta(26),
DOPADOP(1) => douta(17),
DOPADOP(0) => douta(8),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => '0',
WEA(2) => '0',
WEA(1) => '0',
WEA(0) => '0',
WEBWE(7) => '0',
WEBWE(6) => '0',
WEBWE(5) => '0',
WEBWE(4) => '0',
WEBWE(3) => '0',
WEBWE(2) => '0',
WEBWE(1) => '0',
WEBWE(0) => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 17 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end PSelect_blk_mem_gen_prim_width;
architecture STRUCTURE of PSelect_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.PSelect_blk_mem_gen_prim_wrapper_init
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized15\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized15\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized15\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized15\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized16\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized16\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized16\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized16\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized17\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized17\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized17\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized17\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized18\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized18\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized18\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized18\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized19\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized19\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized19\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized19\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized20\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized20\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized20\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized20\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized21\ is
port (
douta : out STD_LOGIC_VECTOR ( 25 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized21\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized21\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized21\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(25 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 35 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \PSelect_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \PSelect_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_init.ram\: entity work.\PSelect_blk_mem_gen_prim_wrapper_init__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(35 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end PSelect_blk_mem_gen_generic_cstr;
architecture STRUCTURE of PSelect_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.PSelect_blk_mem_gen_prim_width
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(17 downto 0) => douta(17 downto 0)
);
\ramloop[10].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized9\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(377 downto 342)
);
\ramloop[11].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized10\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(413 downto 378)
);
\ramloop[12].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized11\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(449 downto 414)
);
\ramloop[13].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized12\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(485 downto 450)
);
\ramloop[14].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized13\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(521 downto 486)
);
\ramloop[15].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized14\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(557 downto 522)
);
\ramloop[16].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized15\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(593 downto 558)
);
\ramloop[17].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized16\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(629 downto 594)
);
\ramloop[18].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized17\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(665 downto 630)
);
\ramloop[19].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized18\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(701 downto 666)
);
\ramloop[1].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(53 downto 18)
);
\ramloop[20].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized19\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(737 downto 702)
);
\ramloop[21].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized20\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(773 downto 738)
);
\ramloop[22].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized21\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(25 downto 0) => douta(799 downto 774)
);
\ramloop[2].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized1\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(89 downto 54)
);
\ramloop[3].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized2\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(125 downto 90)
);
\ramloop[4].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized3\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(161 downto 126)
);
\ramloop[5].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized4\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(197 downto 162)
);
\ramloop[6].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized5\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(233 downto 198)
);
\ramloop[7].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized6\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(269 downto 234)
);
\ramloop[8].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized7\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(305 downto 270)
);
\ramloop[9].ram.r\: entity work.\PSelect_blk_mem_gen_prim_width__parameterized8\
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(35 downto 0) => douta(341 downto 306)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_top : entity is "blk_mem_gen_top";
end PSelect_blk_mem_gen_top;
architecture STRUCTURE of PSelect_blk_mem_gen_top is
begin
\valid.cstr\: entity work.PSelect_blk_mem_gen_generic_cstr
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect_blk_mem_gen_v8_2_synth is
port (
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of PSelect_blk_mem_gen_v8_2_synth : entity is "blk_mem_gen_v8_2_synth";
end PSelect_blk_mem_gen_v8_2_synth;
architecture STRUCTURE of PSelect_blk_mem_gen_v8_2_synth is
begin
\gnativebmg.native_blk_mem_gen\: entity work.PSelect_blk_mem_gen_top
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \PSelect_blk_mem_gen_v8_2__parameterized0\ is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
dina : in STD_LOGIC_VECTOR ( 799 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 9 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 799 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 799 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 );
sleep : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 799 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "blk_mem_gen_v8_2";
attribute C_FAMILY : string;
attribute C_FAMILY of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "artix7";
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "./";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "NONE";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 4;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 3;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 9;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "PSelect.mif";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "PSelect.mem";
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "CE";
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "0";
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 800;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 600;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 10;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "ALL";
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is 0;
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "22";
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "1";
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "Estimated Power for IP : 60.4532 mW";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of \PSelect_blk_mem_gen_v8_2__parameterized0\ : entity is "yes";
end \PSelect_blk_mem_gen_v8_2__parameterized0\;
architecture STRUCTURE of \PSelect_blk_mem_gen_v8_2__parameterized0\ is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(799) <= \<const0>\;
doutb(798) <= \<const0>\;
doutb(797) <= \<const0>\;
doutb(796) <= \<const0>\;
doutb(795) <= \<const0>\;
doutb(794) <= \<const0>\;
doutb(793) <= \<const0>\;
doutb(792) <= \<const0>\;
doutb(791) <= \<const0>\;
doutb(790) <= \<const0>\;
doutb(789) <= \<const0>\;
doutb(788) <= \<const0>\;
doutb(787) <= \<const0>\;
doutb(786) <= \<const0>\;
doutb(785) <= \<const0>\;
doutb(784) <= \<const0>\;
doutb(783) <= \<const0>\;
doutb(782) <= \<const0>\;
doutb(781) <= \<const0>\;
doutb(780) <= \<const0>\;
doutb(779) <= \<const0>\;
doutb(778) <= \<const0>\;
doutb(777) <= \<const0>\;
doutb(776) <= \<const0>\;
doutb(775) <= \<const0>\;
doutb(774) <= \<const0>\;
doutb(773) <= \<const0>\;
doutb(772) <= \<const0>\;
doutb(771) <= \<const0>\;
doutb(770) <= \<const0>\;
doutb(769) <= \<const0>\;
doutb(768) <= \<const0>\;
doutb(767) <= \<const0>\;
doutb(766) <= \<const0>\;
doutb(765) <= \<const0>\;
doutb(764) <= \<const0>\;
doutb(763) <= \<const0>\;
doutb(762) <= \<const0>\;
doutb(761) <= \<const0>\;
doutb(760) <= \<const0>\;
doutb(759) <= \<const0>\;
doutb(758) <= \<const0>\;
doutb(757) <= \<const0>\;
doutb(756) <= \<const0>\;
doutb(755) <= \<const0>\;
doutb(754) <= \<const0>\;
doutb(753) <= \<const0>\;
doutb(752) <= \<const0>\;
doutb(751) <= \<const0>\;
doutb(750) <= \<const0>\;
doutb(749) <= \<const0>\;
doutb(748) <= \<const0>\;
doutb(747) <= \<const0>\;
doutb(746) <= \<const0>\;
doutb(745) <= \<const0>\;
doutb(744) <= \<const0>\;
doutb(743) <= \<const0>\;
doutb(742) <= \<const0>\;
doutb(741) <= \<const0>\;
doutb(740) <= \<const0>\;
doutb(739) <= \<const0>\;
doutb(738) <= \<const0>\;
doutb(737) <= \<const0>\;
doutb(736) <= \<const0>\;
doutb(735) <= \<const0>\;
doutb(734) <= \<const0>\;
doutb(733) <= \<const0>\;
doutb(732) <= \<const0>\;
doutb(731) <= \<const0>\;
doutb(730) <= \<const0>\;
doutb(729) <= \<const0>\;
doutb(728) <= \<const0>\;
doutb(727) <= \<const0>\;
doutb(726) <= \<const0>\;
doutb(725) <= \<const0>\;
doutb(724) <= \<const0>\;
doutb(723) <= \<const0>\;
doutb(722) <= \<const0>\;
doutb(721) <= \<const0>\;
doutb(720) <= \<const0>\;
doutb(719) <= \<const0>\;
doutb(718) <= \<const0>\;
doutb(717) <= \<const0>\;
doutb(716) <= \<const0>\;
doutb(715) <= \<const0>\;
doutb(714) <= \<const0>\;
doutb(713) <= \<const0>\;
doutb(712) <= \<const0>\;
doutb(711) <= \<const0>\;
doutb(710) <= \<const0>\;
doutb(709) <= \<const0>\;
doutb(708) <= \<const0>\;
doutb(707) <= \<const0>\;
doutb(706) <= \<const0>\;
doutb(705) <= \<const0>\;
doutb(704) <= \<const0>\;
doutb(703) <= \<const0>\;
doutb(702) <= \<const0>\;
doutb(701) <= \<const0>\;
doutb(700) <= \<const0>\;
doutb(699) <= \<const0>\;
doutb(698) <= \<const0>\;
doutb(697) <= \<const0>\;
doutb(696) <= \<const0>\;
doutb(695) <= \<const0>\;
doutb(694) <= \<const0>\;
doutb(693) <= \<const0>\;
doutb(692) <= \<const0>\;
doutb(691) <= \<const0>\;
doutb(690) <= \<const0>\;
doutb(689) <= \<const0>\;
doutb(688) <= \<const0>\;
doutb(687) <= \<const0>\;
doutb(686) <= \<const0>\;
doutb(685) <= \<const0>\;
doutb(684) <= \<const0>\;
doutb(683) <= \<const0>\;
doutb(682) <= \<const0>\;
doutb(681) <= \<const0>\;
doutb(680) <= \<const0>\;
doutb(679) <= \<const0>\;
doutb(678) <= \<const0>\;
doutb(677) <= \<const0>\;
doutb(676) <= \<const0>\;
doutb(675) <= \<const0>\;
doutb(674) <= \<const0>\;
doutb(673) <= \<const0>\;
doutb(672) <= \<const0>\;
doutb(671) <= \<const0>\;
doutb(670) <= \<const0>\;
doutb(669) <= \<const0>\;
doutb(668) <= \<const0>\;
doutb(667) <= \<const0>\;
doutb(666) <= \<const0>\;
doutb(665) <= \<const0>\;
doutb(664) <= \<const0>\;
doutb(663) <= \<const0>\;
doutb(662) <= \<const0>\;
doutb(661) <= \<const0>\;
doutb(660) <= \<const0>\;
doutb(659) <= \<const0>\;
doutb(658) <= \<const0>\;
doutb(657) <= \<const0>\;
doutb(656) <= \<const0>\;
doutb(655) <= \<const0>\;
doutb(654) <= \<const0>\;
doutb(653) <= \<const0>\;
doutb(652) <= \<const0>\;
doutb(651) <= \<const0>\;
doutb(650) <= \<const0>\;
doutb(649) <= \<const0>\;
doutb(648) <= \<const0>\;
doutb(647) <= \<const0>\;
doutb(646) <= \<const0>\;
doutb(645) <= \<const0>\;
doutb(644) <= \<const0>\;
doutb(643) <= \<const0>\;
doutb(642) <= \<const0>\;
doutb(641) <= \<const0>\;
doutb(640) <= \<const0>\;
doutb(639) <= \<const0>\;
doutb(638) <= \<const0>\;
doutb(637) <= \<const0>\;
doutb(636) <= \<const0>\;
doutb(635) <= \<const0>\;
doutb(634) <= \<const0>\;
doutb(633) <= \<const0>\;
doutb(632) <= \<const0>\;
doutb(631) <= \<const0>\;
doutb(630) <= \<const0>\;
doutb(629) <= \<const0>\;
doutb(628) <= \<const0>\;
doutb(627) <= \<const0>\;
doutb(626) <= \<const0>\;
doutb(625) <= \<const0>\;
doutb(624) <= \<const0>\;
doutb(623) <= \<const0>\;
doutb(622) <= \<const0>\;
doutb(621) <= \<const0>\;
doutb(620) <= \<const0>\;
doutb(619) <= \<const0>\;
doutb(618) <= \<const0>\;
doutb(617) <= \<const0>\;
doutb(616) <= \<const0>\;
doutb(615) <= \<const0>\;
doutb(614) <= \<const0>\;
doutb(613) <= \<const0>\;
doutb(612) <= \<const0>\;
doutb(611) <= \<const0>\;
doutb(610) <= \<const0>\;
doutb(609) <= \<const0>\;
doutb(608) <= \<const0>\;
doutb(607) <= \<const0>\;
doutb(606) <= \<const0>\;
doutb(605) <= \<const0>\;
doutb(604) <= \<const0>\;
doutb(603) <= \<const0>\;
doutb(602) <= \<const0>\;
doutb(601) <= \<const0>\;
doutb(600) <= \<const0>\;
doutb(599) <= \<const0>\;
doutb(598) <= \<const0>\;
doutb(597) <= \<const0>\;
doutb(596) <= \<const0>\;
doutb(595) <= \<const0>\;
doutb(594) <= \<const0>\;
doutb(593) <= \<const0>\;
doutb(592) <= \<const0>\;
doutb(591) <= \<const0>\;
doutb(590) <= \<const0>\;
doutb(589) <= \<const0>\;
doutb(588) <= \<const0>\;
doutb(587) <= \<const0>\;
doutb(586) <= \<const0>\;
doutb(585) <= \<const0>\;
doutb(584) <= \<const0>\;
doutb(583) <= \<const0>\;
doutb(582) <= \<const0>\;
doutb(581) <= \<const0>\;
doutb(580) <= \<const0>\;
doutb(579) <= \<const0>\;
doutb(578) <= \<const0>\;
doutb(577) <= \<const0>\;
doutb(576) <= \<const0>\;
doutb(575) <= \<const0>\;
doutb(574) <= \<const0>\;
doutb(573) <= \<const0>\;
doutb(572) <= \<const0>\;
doutb(571) <= \<const0>\;
doutb(570) <= \<const0>\;
doutb(569) <= \<const0>\;
doutb(568) <= \<const0>\;
doutb(567) <= \<const0>\;
doutb(566) <= \<const0>\;
doutb(565) <= \<const0>\;
doutb(564) <= \<const0>\;
doutb(563) <= \<const0>\;
doutb(562) <= \<const0>\;
doutb(561) <= \<const0>\;
doutb(560) <= \<const0>\;
doutb(559) <= \<const0>\;
doutb(558) <= \<const0>\;
doutb(557) <= \<const0>\;
doutb(556) <= \<const0>\;
doutb(555) <= \<const0>\;
doutb(554) <= \<const0>\;
doutb(553) <= \<const0>\;
doutb(552) <= \<const0>\;
doutb(551) <= \<const0>\;
doutb(550) <= \<const0>\;
doutb(549) <= \<const0>\;
doutb(548) <= \<const0>\;
doutb(547) <= \<const0>\;
doutb(546) <= \<const0>\;
doutb(545) <= \<const0>\;
doutb(544) <= \<const0>\;
doutb(543) <= \<const0>\;
doutb(542) <= \<const0>\;
doutb(541) <= \<const0>\;
doutb(540) <= \<const0>\;
doutb(539) <= \<const0>\;
doutb(538) <= \<const0>\;
doutb(537) <= \<const0>\;
doutb(536) <= \<const0>\;
doutb(535) <= \<const0>\;
doutb(534) <= \<const0>\;
doutb(533) <= \<const0>\;
doutb(532) <= \<const0>\;
doutb(531) <= \<const0>\;
doutb(530) <= \<const0>\;
doutb(529) <= \<const0>\;
doutb(528) <= \<const0>\;
doutb(527) <= \<const0>\;
doutb(526) <= \<const0>\;
doutb(525) <= \<const0>\;
doutb(524) <= \<const0>\;
doutb(523) <= \<const0>\;
doutb(522) <= \<const0>\;
doutb(521) <= \<const0>\;
doutb(520) <= \<const0>\;
doutb(519) <= \<const0>\;
doutb(518) <= \<const0>\;
doutb(517) <= \<const0>\;
doutb(516) <= \<const0>\;
doutb(515) <= \<const0>\;
doutb(514) <= \<const0>\;
doutb(513) <= \<const0>\;
doutb(512) <= \<const0>\;
doutb(511) <= \<const0>\;
doutb(510) <= \<const0>\;
doutb(509) <= \<const0>\;
doutb(508) <= \<const0>\;
doutb(507) <= \<const0>\;
doutb(506) <= \<const0>\;
doutb(505) <= \<const0>\;
doutb(504) <= \<const0>\;
doutb(503) <= \<const0>\;
doutb(502) <= \<const0>\;
doutb(501) <= \<const0>\;
doutb(500) <= \<const0>\;
doutb(499) <= \<const0>\;
doutb(498) <= \<const0>\;
doutb(497) <= \<const0>\;
doutb(496) <= \<const0>\;
doutb(495) <= \<const0>\;
doutb(494) <= \<const0>\;
doutb(493) <= \<const0>\;
doutb(492) <= \<const0>\;
doutb(491) <= \<const0>\;
doutb(490) <= \<const0>\;
doutb(489) <= \<const0>\;
doutb(488) <= \<const0>\;
doutb(487) <= \<const0>\;
doutb(486) <= \<const0>\;
doutb(485) <= \<const0>\;
doutb(484) <= \<const0>\;
doutb(483) <= \<const0>\;
doutb(482) <= \<const0>\;
doutb(481) <= \<const0>\;
doutb(480) <= \<const0>\;
doutb(479) <= \<const0>\;
doutb(478) <= \<const0>\;
doutb(477) <= \<const0>\;
doutb(476) <= \<const0>\;
doutb(475) <= \<const0>\;
doutb(474) <= \<const0>\;
doutb(473) <= \<const0>\;
doutb(472) <= \<const0>\;
doutb(471) <= \<const0>\;
doutb(470) <= \<const0>\;
doutb(469) <= \<const0>\;
doutb(468) <= \<const0>\;
doutb(467) <= \<const0>\;
doutb(466) <= \<const0>\;
doutb(465) <= \<const0>\;
doutb(464) <= \<const0>\;
doutb(463) <= \<const0>\;
doutb(462) <= \<const0>\;
doutb(461) <= \<const0>\;
doutb(460) <= \<const0>\;
doutb(459) <= \<const0>\;
doutb(458) <= \<const0>\;
doutb(457) <= \<const0>\;
doutb(456) <= \<const0>\;
doutb(455) <= \<const0>\;
doutb(454) <= \<const0>\;
doutb(453) <= \<const0>\;
doutb(452) <= \<const0>\;
doutb(451) <= \<const0>\;
doutb(450) <= \<const0>\;
doutb(449) <= \<const0>\;
doutb(448) <= \<const0>\;
doutb(447) <= \<const0>\;
doutb(446) <= \<const0>\;
doutb(445) <= \<const0>\;
doutb(444) <= \<const0>\;
doutb(443) <= \<const0>\;
doutb(442) <= \<const0>\;
doutb(441) <= \<const0>\;
doutb(440) <= \<const0>\;
doutb(439) <= \<const0>\;
doutb(438) <= \<const0>\;
doutb(437) <= \<const0>\;
doutb(436) <= \<const0>\;
doutb(435) <= \<const0>\;
doutb(434) <= \<const0>\;
doutb(433) <= \<const0>\;
doutb(432) <= \<const0>\;
doutb(431) <= \<const0>\;
doutb(430) <= \<const0>\;
doutb(429) <= \<const0>\;
doutb(428) <= \<const0>\;
doutb(427) <= \<const0>\;
doutb(426) <= \<const0>\;
doutb(425) <= \<const0>\;
doutb(424) <= \<const0>\;
doutb(423) <= \<const0>\;
doutb(422) <= \<const0>\;
doutb(421) <= \<const0>\;
doutb(420) <= \<const0>\;
doutb(419) <= \<const0>\;
doutb(418) <= \<const0>\;
doutb(417) <= \<const0>\;
doutb(416) <= \<const0>\;
doutb(415) <= \<const0>\;
doutb(414) <= \<const0>\;
doutb(413) <= \<const0>\;
doutb(412) <= \<const0>\;
doutb(411) <= \<const0>\;
doutb(410) <= \<const0>\;
doutb(409) <= \<const0>\;
doutb(408) <= \<const0>\;
doutb(407) <= \<const0>\;
doutb(406) <= \<const0>\;
doutb(405) <= \<const0>\;
doutb(404) <= \<const0>\;
doutb(403) <= \<const0>\;
doutb(402) <= \<const0>\;
doutb(401) <= \<const0>\;
doutb(400) <= \<const0>\;
doutb(399) <= \<const0>\;
doutb(398) <= \<const0>\;
doutb(397) <= \<const0>\;
doutb(396) <= \<const0>\;
doutb(395) <= \<const0>\;
doutb(394) <= \<const0>\;
doutb(393) <= \<const0>\;
doutb(392) <= \<const0>\;
doutb(391) <= \<const0>\;
doutb(390) <= \<const0>\;
doutb(389) <= \<const0>\;
doutb(388) <= \<const0>\;
doutb(387) <= \<const0>\;
doutb(386) <= \<const0>\;
doutb(385) <= \<const0>\;
doutb(384) <= \<const0>\;
doutb(383) <= \<const0>\;
doutb(382) <= \<const0>\;
doutb(381) <= \<const0>\;
doutb(380) <= \<const0>\;
doutb(379) <= \<const0>\;
doutb(378) <= \<const0>\;
doutb(377) <= \<const0>\;
doutb(376) <= \<const0>\;
doutb(375) <= \<const0>\;
doutb(374) <= \<const0>\;
doutb(373) <= \<const0>\;
doutb(372) <= \<const0>\;
doutb(371) <= \<const0>\;
doutb(370) <= \<const0>\;
doutb(369) <= \<const0>\;
doutb(368) <= \<const0>\;
doutb(367) <= \<const0>\;
doutb(366) <= \<const0>\;
doutb(365) <= \<const0>\;
doutb(364) <= \<const0>\;
doutb(363) <= \<const0>\;
doutb(362) <= \<const0>\;
doutb(361) <= \<const0>\;
doutb(360) <= \<const0>\;
doutb(359) <= \<const0>\;
doutb(358) <= \<const0>\;
doutb(357) <= \<const0>\;
doutb(356) <= \<const0>\;
doutb(355) <= \<const0>\;
doutb(354) <= \<const0>\;
doutb(353) <= \<const0>\;
doutb(352) <= \<const0>\;
doutb(351) <= \<const0>\;
doutb(350) <= \<const0>\;
doutb(349) <= \<const0>\;
doutb(348) <= \<const0>\;
doutb(347) <= \<const0>\;
doutb(346) <= \<const0>\;
doutb(345) <= \<const0>\;
doutb(344) <= \<const0>\;
doutb(343) <= \<const0>\;
doutb(342) <= \<const0>\;
doutb(341) <= \<const0>\;
doutb(340) <= \<const0>\;
doutb(339) <= \<const0>\;
doutb(338) <= \<const0>\;
doutb(337) <= \<const0>\;
doutb(336) <= \<const0>\;
doutb(335) <= \<const0>\;
doutb(334) <= \<const0>\;
doutb(333) <= \<const0>\;
doutb(332) <= \<const0>\;
doutb(331) <= \<const0>\;
doutb(330) <= \<const0>\;
doutb(329) <= \<const0>\;
doutb(328) <= \<const0>\;
doutb(327) <= \<const0>\;
doutb(326) <= \<const0>\;
doutb(325) <= \<const0>\;
doutb(324) <= \<const0>\;
doutb(323) <= \<const0>\;
doutb(322) <= \<const0>\;
doutb(321) <= \<const0>\;
doutb(320) <= \<const0>\;
doutb(319) <= \<const0>\;
doutb(318) <= \<const0>\;
doutb(317) <= \<const0>\;
doutb(316) <= \<const0>\;
doutb(315) <= \<const0>\;
doutb(314) <= \<const0>\;
doutb(313) <= \<const0>\;
doutb(312) <= \<const0>\;
doutb(311) <= \<const0>\;
doutb(310) <= \<const0>\;
doutb(309) <= \<const0>\;
doutb(308) <= \<const0>\;
doutb(307) <= \<const0>\;
doutb(306) <= \<const0>\;
doutb(305) <= \<const0>\;
doutb(304) <= \<const0>\;
doutb(303) <= \<const0>\;
doutb(302) <= \<const0>\;
doutb(301) <= \<const0>\;
doutb(300) <= \<const0>\;
doutb(299) <= \<const0>\;
doutb(298) <= \<const0>\;
doutb(297) <= \<const0>\;
doutb(296) <= \<const0>\;
doutb(295) <= \<const0>\;
doutb(294) <= \<const0>\;
doutb(293) <= \<const0>\;
doutb(292) <= \<const0>\;
doutb(291) <= \<const0>\;
doutb(290) <= \<const0>\;
doutb(289) <= \<const0>\;
doutb(288) <= \<const0>\;
doutb(287) <= \<const0>\;
doutb(286) <= \<const0>\;
doutb(285) <= \<const0>\;
doutb(284) <= \<const0>\;
doutb(283) <= \<const0>\;
doutb(282) <= \<const0>\;
doutb(281) <= \<const0>\;
doutb(280) <= \<const0>\;
doutb(279) <= \<const0>\;
doutb(278) <= \<const0>\;
doutb(277) <= \<const0>\;
doutb(276) <= \<const0>\;
doutb(275) <= \<const0>\;
doutb(274) <= \<const0>\;
doutb(273) <= \<const0>\;
doutb(272) <= \<const0>\;
doutb(271) <= \<const0>\;
doutb(270) <= \<const0>\;
doutb(269) <= \<const0>\;
doutb(268) <= \<const0>\;
doutb(267) <= \<const0>\;
doutb(266) <= \<const0>\;
doutb(265) <= \<const0>\;
doutb(264) <= \<const0>\;
doutb(263) <= \<const0>\;
doutb(262) <= \<const0>\;
doutb(261) <= \<const0>\;
doutb(260) <= \<const0>\;
doutb(259) <= \<const0>\;
doutb(258) <= \<const0>\;
doutb(257) <= \<const0>\;
doutb(256) <= \<const0>\;
doutb(255) <= \<const0>\;
doutb(254) <= \<const0>\;
doutb(253) <= \<const0>\;
doutb(252) <= \<const0>\;
doutb(251) <= \<const0>\;
doutb(250) <= \<const0>\;
doutb(249) <= \<const0>\;
doutb(248) <= \<const0>\;
doutb(247) <= \<const0>\;
doutb(246) <= \<const0>\;
doutb(245) <= \<const0>\;
doutb(244) <= \<const0>\;
doutb(243) <= \<const0>\;
doutb(242) <= \<const0>\;
doutb(241) <= \<const0>\;
doutb(240) <= \<const0>\;
doutb(239) <= \<const0>\;
doutb(238) <= \<const0>\;
doutb(237) <= \<const0>\;
doutb(236) <= \<const0>\;
doutb(235) <= \<const0>\;
doutb(234) <= \<const0>\;
doutb(233) <= \<const0>\;
doutb(232) <= \<const0>\;
doutb(231) <= \<const0>\;
doutb(230) <= \<const0>\;
doutb(229) <= \<const0>\;
doutb(228) <= \<const0>\;
doutb(227) <= \<const0>\;
doutb(226) <= \<const0>\;
doutb(225) <= \<const0>\;
doutb(224) <= \<const0>\;
doutb(223) <= \<const0>\;
doutb(222) <= \<const0>\;
doutb(221) <= \<const0>\;
doutb(220) <= \<const0>\;
doutb(219) <= \<const0>\;
doutb(218) <= \<const0>\;
doutb(217) <= \<const0>\;
doutb(216) <= \<const0>\;
doutb(215) <= \<const0>\;
doutb(214) <= \<const0>\;
doutb(213) <= \<const0>\;
doutb(212) <= \<const0>\;
doutb(211) <= \<const0>\;
doutb(210) <= \<const0>\;
doutb(209) <= \<const0>\;
doutb(208) <= \<const0>\;
doutb(207) <= \<const0>\;
doutb(206) <= \<const0>\;
doutb(205) <= \<const0>\;
doutb(204) <= \<const0>\;
doutb(203) <= \<const0>\;
doutb(202) <= \<const0>\;
doutb(201) <= \<const0>\;
doutb(200) <= \<const0>\;
doutb(199) <= \<const0>\;
doutb(198) <= \<const0>\;
doutb(197) <= \<const0>\;
doutb(196) <= \<const0>\;
doutb(195) <= \<const0>\;
doutb(194) <= \<const0>\;
doutb(193) <= \<const0>\;
doutb(192) <= \<const0>\;
doutb(191) <= \<const0>\;
doutb(190) <= \<const0>\;
doutb(189) <= \<const0>\;
doutb(188) <= \<const0>\;
doutb(187) <= \<const0>\;
doutb(186) <= \<const0>\;
doutb(185) <= \<const0>\;
doutb(184) <= \<const0>\;
doutb(183) <= \<const0>\;
doutb(182) <= \<const0>\;
doutb(181) <= \<const0>\;
doutb(180) <= \<const0>\;
doutb(179) <= \<const0>\;
doutb(178) <= \<const0>\;
doutb(177) <= \<const0>\;
doutb(176) <= \<const0>\;
doutb(175) <= \<const0>\;
doutb(174) <= \<const0>\;
doutb(173) <= \<const0>\;
doutb(172) <= \<const0>\;
doutb(171) <= \<const0>\;
doutb(170) <= \<const0>\;
doutb(169) <= \<const0>\;
doutb(168) <= \<const0>\;
doutb(167) <= \<const0>\;
doutb(166) <= \<const0>\;
doutb(165) <= \<const0>\;
doutb(164) <= \<const0>\;
doutb(163) <= \<const0>\;
doutb(162) <= \<const0>\;
doutb(161) <= \<const0>\;
doutb(160) <= \<const0>\;
doutb(159) <= \<const0>\;
doutb(158) <= \<const0>\;
doutb(157) <= \<const0>\;
doutb(156) <= \<const0>\;
doutb(155) <= \<const0>\;
doutb(154) <= \<const0>\;
doutb(153) <= \<const0>\;
doutb(152) <= \<const0>\;
doutb(151) <= \<const0>\;
doutb(150) <= \<const0>\;
doutb(149) <= \<const0>\;
doutb(148) <= \<const0>\;
doutb(147) <= \<const0>\;
doutb(146) <= \<const0>\;
doutb(145) <= \<const0>\;
doutb(144) <= \<const0>\;
doutb(143) <= \<const0>\;
doutb(142) <= \<const0>\;
doutb(141) <= \<const0>\;
doutb(140) <= \<const0>\;
doutb(139) <= \<const0>\;
doutb(138) <= \<const0>\;
doutb(137) <= \<const0>\;
doutb(136) <= \<const0>\;
doutb(135) <= \<const0>\;
doutb(134) <= \<const0>\;
doutb(133) <= \<const0>\;
doutb(132) <= \<const0>\;
doutb(131) <= \<const0>\;
doutb(130) <= \<const0>\;
doutb(129) <= \<const0>\;
doutb(128) <= \<const0>\;
doutb(127) <= \<const0>\;
doutb(126) <= \<const0>\;
doutb(125) <= \<const0>\;
doutb(124) <= \<const0>\;
doutb(123) <= \<const0>\;
doutb(122) <= \<const0>\;
doutb(121) <= \<const0>\;
doutb(120) <= \<const0>\;
doutb(119) <= \<const0>\;
doutb(118) <= \<const0>\;
doutb(117) <= \<const0>\;
doutb(116) <= \<const0>\;
doutb(115) <= \<const0>\;
doutb(114) <= \<const0>\;
doutb(113) <= \<const0>\;
doutb(112) <= \<const0>\;
doutb(111) <= \<const0>\;
doutb(110) <= \<const0>\;
doutb(109) <= \<const0>\;
doutb(108) <= \<const0>\;
doutb(107) <= \<const0>\;
doutb(106) <= \<const0>\;
doutb(105) <= \<const0>\;
doutb(104) <= \<const0>\;
doutb(103) <= \<const0>\;
doutb(102) <= \<const0>\;
doutb(101) <= \<const0>\;
doutb(100) <= \<const0>\;
doutb(99) <= \<const0>\;
doutb(98) <= \<const0>\;
doutb(97) <= \<const0>\;
doutb(96) <= \<const0>\;
doutb(95) <= \<const0>\;
doutb(94) <= \<const0>\;
doutb(93) <= \<const0>\;
doutb(92) <= \<const0>\;
doutb(91) <= \<const0>\;
doutb(90) <= \<const0>\;
doutb(89) <= \<const0>\;
doutb(88) <= \<const0>\;
doutb(87) <= \<const0>\;
doutb(86) <= \<const0>\;
doutb(85) <= \<const0>\;
doutb(84) <= \<const0>\;
doutb(83) <= \<const0>\;
doutb(82) <= \<const0>\;
doutb(81) <= \<const0>\;
doutb(80) <= \<const0>\;
doutb(79) <= \<const0>\;
doutb(78) <= \<const0>\;
doutb(77) <= \<const0>\;
doutb(76) <= \<const0>\;
doutb(75) <= \<const0>\;
doutb(74) <= \<const0>\;
doutb(73) <= \<const0>\;
doutb(72) <= \<const0>\;
doutb(71) <= \<const0>\;
doutb(70) <= \<const0>\;
doutb(69) <= \<const0>\;
doutb(68) <= \<const0>\;
doutb(67) <= \<const0>\;
doutb(66) <= \<const0>\;
doutb(65) <= \<const0>\;
doutb(64) <= \<const0>\;
doutb(63) <= \<const0>\;
doutb(62) <= \<const0>\;
doutb(61) <= \<const0>\;
doutb(60) <= \<const0>\;
doutb(59) <= \<const0>\;
doutb(58) <= \<const0>\;
doutb(57) <= \<const0>\;
doutb(56) <= \<const0>\;
doutb(55) <= \<const0>\;
doutb(54) <= \<const0>\;
doutb(53) <= \<const0>\;
doutb(52) <= \<const0>\;
doutb(51) <= \<const0>\;
doutb(50) <= \<const0>\;
doutb(49) <= \<const0>\;
doutb(48) <= \<const0>\;
doutb(47) <= \<const0>\;
doutb(46) <= \<const0>\;
doutb(45) <= \<const0>\;
doutb(44) <= \<const0>\;
doutb(43) <= \<const0>\;
doutb(42) <= \<const0>\;
doutb(41) <= \<const0>\;
doutb(40) <= \<const0>\;
doutb(39) <= \<const0>\;
doutb(38) <= \<const0>\;
doutb(37) <= \<const0>\;
doutb(36) <= \<const0>\;
doutb(35) <= \<const0>\;
doutb(34) <= \<const0>\;
doutb(33) <= \<const0>\;
doutb(32) <= \<const0>\;
doutb(31) <= \<const0>\;
doutb(30) <= \<const0>\;
doutb(29) <= \<const0>\;
doutb(28) <= \<const0>\;
doutb(27) <= \<const0>\;
doutb(26) <= \<const0>\;
doutb(25) <= \<const0>\;
doutb(24) <= \<const0>\;
doutb(23) <= \<const0>\;
doutb(22) <= \<const0>\;
doutb(21) <= \<const0>\;
doutb(20) <= \<const0>\;
doutb(19) <= \<const0>\;
doutb(18) <= \<const0>\;
doutb(17) <= \<const0>\;
doutb(16) <= \<const0>\;
doutb(15) <= \<const0>\;
doutb(14) <= \<const0>\;
doutb(13) <= \<const0>\;
doutb(12) <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(799) <= \<const0>\;
s_axi_rdata(798) <= \<const0>\;
s_axi_rdata(797) <= \<const0>\;
s_axi_rdata(796) <= \<const0>\;
s_axi_rdata(795) <= \<const0>\;
s_axi_rdata(794) <= \<const0>\;
s_axi_rdata(793) <= \<const0>\;
s_axi_rdata(792) <= \<const0>\;
s_axi_rdata(791) <= \<const0>\;
s_axi_rdata(790) <= \<const0>\;
s_axi_rdata(789) <= \<const0>\;
s_axi_rdata(788) <= \<const0>\;
s_axi_rdata(787) <= \<const0>\;
s_axi_rdata(786) <= \<const0>\;
s_axi_rdata(785) <= \<const0>\;
s_axi_rdata(784) <= \<const0>\;
s_axi_rdata(783) <= \<const0>\;
s_axi_rdata(782) <= \<const0>\;
s_axi_rdata(781) <= \<const0>\;
s_axi_rdata(780) <= \<const0>\;
s_axi_rdata(779) <= \<const0>\;
s_axi_rdata(778) <= \<const0>\;
s_axi_rdata(777) <= \<const0>\;
s_axi_rdata(776) <= \<const0>\;
s_axi_rdata(775) <= \<const0>\;
s_axi_rdata(774) <= \<const0>\;
s_axi_rdata(773) <= \<const0>\;
s_axi_rdata(772) <= \<const0>\;
s_axi_rdata(771) <= \<const0>\;
s_axi_rdata(770) <= \<const0>\;
s_axi_rdata(769) <= \<const0>\;
s_axi_rdata(768) <= \<const0>\;
s_axi_rdata(767) <= \<const0>\;
s_axi_rdata(766) <= \<const0>\;
s_axi_rdata(765) <= \<const0>\;
s_axi_rdata(764) <= \<const0>\;
s_axi_rdata(763) <= \<const0>\;
s_axi_rdata(762) <= \<const0>\;
s_axi_rdata(761) <= \<const0>\;
s_axi_rdata(760) <= \<const0>\;
s_axi_rdata(759) <= \<const0>\;
s_axi_rdata(758) <= \<const0>\;
s_axi_rdata(757) <= \<const0>\;
s_axi_rdata(756) <= \<const0>\;
s_axi_rdata(755) <= \<const0>\;
s_axi_rdata(754) <= \<const0>\;
s_axi_rdata(753) <= \<const0>\;
s_axi_rdata(752) <= \<const0>\;
s_axi_rdata(751) <= \<const0>\;
s_axi_rdata(750) <= \<const0>\;
s_axi_rdata(749) <= \<const0>\;
s_axi_rdata(748) <= \<const0>\;
s_axi_rdata(747) <= \<const0>\;
s_axi_rdata(746) <= \<const0>\;
s_axi_rdata(745) <= \<const0>\;
s_axi_rdata(744) <= \<const0>\;
s_axi_rdata(743) <= \<const0>\;
s_axi_rdata(742) <= \<const0>\;
s_axi_rdata(741) <= \<const0>\;
s_axi_rdata(740) <= \<const0>\;
s_axi_rdata(739) <= \<const0>\;
s_axi_rdata(738) <= \<const0>\;
s_axi_rdata(737) <= \<const0>\;
s_axi_rdata(736) <= \<const0>\;
s_axi_rdata(735) <= \<const0>\;
s_axi_rdata(734) <= \<const0>\;
s_axi_rdata(733) <= \<const0>\;
s_axi_rdata(732) <= \<const0>\;
s_axi_rdata(731) <= \<const0>\;
s_axi_rdata(730) <= \<const0>\;
s_axi_rdata(729) <= \<const0>\;
s_axi_rdata(728) <= \<const0>\;
s_axi_rdata(727) <= \<const0>\;
s_axi_rdata(726) <= \<const0>\;
s_axi_rdata(725) <= \<const0>\;
s_axi_rdata(724) <= \<const0>\;
s_axi_rdata(723) <= \<const0>\;
s_axi_rdata(722) <= \<const0>\;
s_axi_rdata(721) <= \<const0>\;
s_axi_rdata(720) <= \<const0>\;
s_axi_rdata(719) <= \<const0>\;
s_axi_rdata(718) <= \<const0>\;
s_axi_rdata(717) <= \<const0>\;
s_axi_rdata(716) <= \<const0>\;
s_axi_rdata(715) <= \<const0>\;
s_axi_rdata(714) <= \<const0>\;
s_axi_rdata(713) <= \<const0>\;
s_axi_rdata(712) <= \<const0>\;
s_axi_rdata(711) <= \<const0>\;
s_axi_rdata(710) <= \<const0>\;
s_axi_rdata(709) <= \<const0>\;
s_axi_rdata(708) <= \<const0>\;
s_axi_rdata(707) <= \<const0>\;
s_axi_rdata(706) <= \<const0>\;
s_axi_rdata(705) <= \<const0>\;
s_axi_rdata(704) <= \<const0>\;
s_axi_rdata(703) <= \<const0>\;
s_axi_rdata(702) <= \<const0>\;
s_axi_rdata(701) <= \<const0>\;
s_axi_rdata(700) <= \<const0>\;
s_axi_rdata(699) <= \<const0>\;
s_axi_rdata(698) <= \<const0>\;
s_axi_rdata(697) <= \<const0>\;
s_axi_rdata(696) <= \<const0>\;
s_axi_rdata(695) <= \<const0>\;
s_axi_rdata(694) <= \<const0>\;
s_axi_rdata(693) <= \<const0>\;
s_axi_rdata(692) <= \<const0>\;
s_axi_rdata(691) <= \<const0>\;
s_axi_rdata(690) <= \<const0>\;
s_axi_rdata(689) <= \<const0>\;
s_axi_rdata(688) <= \<const0>\;
s_axi_rdata(687) <= \<const0>\;
s_axi_rdata(686) <= \<const0>\;
s_axi_rdata(685) <= \<const0>\;
s_axi_rdata(684) <= \<const0>\;
s_axi_rdata(683) <= \<const0>\;
s_axi_rdata(682) <= \<const0>\;
s_axi_rdata(681) <= \<const0>\;
s_axi_rdata(680) <= \<const0>\;
s_axi_rdata(679) <= \<const0>\;
s_axi_rdata(678) <= \<const0>\;
s_axi_rdata(677) <= \<const0>\;
s_axi_rdata(676) <= \<const0>\;
s_axi_rdata(675) <= \<const0>\;
s_axi_rdata(674) <= \<const0>\;
s_axi_rdata(673) <= \<const0>\;
s_axi_rdata(672) <= \<const0>\;
s_axi_rdata(671) <= \<const0>\;
s_axi_rdata(670) <= \<const0>\;
s_axi_rdata(669) <= \<const0>\;
s_axi_rdata(668) <= \<const0>\;
s_axi_rdata(667) <= \<const0>\;
s_axi_rdata(666) <= \<const0>\;
s_axi_rdata(665) <= \<const0>\;
s_axi_rdata(664) <= \<const0>\;
s_axi_rdata(663) <= \<const0>\;
s_axi_rdata(662) <= \<const0>\;
s_axi_rdata(661) <= \<const0>\;
s_axi_rdata(660) <= \<const0>\;
s_axi_rdata(659) <= \<const0>\;
s_axi_rdata(658) <= \<const0>\;
s_axi_rdata(657) <= \<const0>\;
s_axi_rdata(656) <= \<const0>\;
s_axi_rdata(655) <= \<const0>\;
s_axi_rdata(654) <= \<const0>\;
s_axi_rdata(653) <= \<const0>\;
s_axi_rdata(652) <= \<const0>\;
s_axi_rdata(651) <= \<const0>\;
s_axi_rdata(650) <= \<const0>\;
s_axi_rdata(649) <= \<const0>\;
s_axi_rdata(648) <= \<const0>\;
s_axi_rdata(647) <= \<const0>\;
s_axi_rdata(646) <= \<const0>\;
s_axi_rdata(645) <= \<const0>\;
s_axi_rdata(644) <= \<const0>\;
s_axi_rdata(643) <= \<const0>\;
s_axi_rdata(642) <= \<const0>\;
s_axi_rdata(641) <= \<const0>\;
s_axi_rdata(640) <= \<const0>\;
s_axi_rdata(639) <= \<const0>\;
s_axi_rdata(638) <= \<const0>\;
s_axi_rdata(637) <= \<const0>\;
s_axi_rdata(636) <= \<const0>\;
s_axi_rdata(635) <= \<const0>\;
s_axi_rdata(634) <= \<const0>\;
s_axi_rdata(633) <= \<const0>\;
s_axi_rdata(632) <= \<const0>\;
s_axi_rdata(631) <= \<const0>\;
s_axi_rdata(630) <= \<const0>\;
s_axi_rdata(629) <= \<const0>\;
s_axi_rdata(628) <= \<const0>\;
s_axi_rdata(627) <= \<const0>\;
s_axi_rdata(626) <= \<const0>\;
s_axi_rdata(625) <= \<const0>\;
s_axi_rdata(624) <= \<const0>\;
s_axi_rdata(623) <= \<const0>\;
s_axi_rdata(622) <= \<const0>\;
s_axi_rdata(621) <= \<const0>\;
s_axi_rdata(620) <= \<const0>\;
s_axi_rdata(619) <= \<const0>\;
s_axi_rdata(618) <= \<const0>\;
s_axi_rdata(617) <= \<const0>\;
s_axi_rdata(616) <= \<const0>\;
s_axi_rdata(615) <= \<const0>\;
s_axi_rdata(614) <= \<const0>\;
s_axi_rdata(613) <= \<const0>\;
s_axi_rdata(612) <= \<const0>\;
s_axi_rdata(611) <= \<const0>\;
s_axi_rdata(610) <= \<const0>\;
s_axi_rdata(609) <= \<const0>\;
s_axi_rdata(608) <= \<const0>\;
s_axi_rdata(607) <= \<const0>\;
s_axi_rdata(606) <= \<const0>\;
s_axi_rdata(605) <= \<const0>\;
s_axi_rdata(604) <= \<const0>\;
s_axi_rdata(603) <= \<const0>\;
s_axi_rdata(602) <= \<const0>\;
s_axi_rdata(601) <= \<const0>\;
s_axi_rdata(600) <= \<const0>\;
s_axi_rdata(599) <= \<const0>\;
s_axi_rdata(598) <= \<const0>\;
s_axi_rdata(597) <= \<const0>\;
s_axi_rdata(596) <= \<const0>\;
s_axi_rdata(595) <= \<const0>\;
s_axi_rdata(594) <= \<const0>\;
s_axi_rdata(593) <= \<const0>\;
s_axi_rdata(592) <= \<const0>\;
s_axi_rdata(591) <= \<const0>\;
s_axi_rdata(590) <= \<const0>\;
s_axi_rdata(589) <= \<const0>\;
s_axi_rdata(588) <= \<const0>\;
s_axi_rdata(587) <= \<const0>\;
s_axi_rdata(586) <= \<const0>\;
s_axi_rdata(585) <= \<const0>\;
s_axi_rdata(584) <= \<const0>\;
s_axi_rdata(583) <= \<const0>\;
s_axi_rdata(582) <= \<const0>\;
s_axi_rdata(581) <= \<const0>\;
s_axi_rdata(580) <= \<const0>\;
s_axi_rdata(579) <= \<const0>\;
s_axi_rdata(578) <= \<const0>\;
s_axi_rdata(577) <= \<const0>\;
s_axi_rdata(576) <= \<const0>\;
s_axi_rdata(575) <= \<const0>\;
s_axi_rdata(574) <= \<const0>\;
s_axi_rdata(573) <= \<const0>\;
s_axi_rdata(572) <= \<const0>\;
s_axi_rdata(571) <= \<const0>\;
s_axi_rdata(570) <= \<const0>\;
s_axi_rdata(569) <= \<const0>\;
s_axi_rdata(568) <= \<const0>\;
s_axi_rdata(567) <= \<const0>\;
s_axi_rdata(566) <= \<const0>\;
s_axi_rdata(565) <= \<const0>\;
s_axi_rdata(564) <= \<const0>\;
s_axi_rdata(563) <= \<const0>\;
s_axi_rdata(562) <= \<const0>\;
s_axi_rdata(561) <= \<const0>\;
s_axi_rdata(560) <= \<const0>\;
s_axi_rdata(559) <= \<const0>\;
s_axi_rdata(558) <= \<const0>\;
s_axi_rdata(557) <= \<const0>\;
s_axi_rdata(556) <= \<const0>\;
s_axi_rdata(555) <= \<const0>\;
s_axi_rdata(554) <= \<const0>\;
s_axi_rdata(553) <= \<const0>\;
s_axi_rdata(552) <= \<const0>\;
s_axi_rdata(551) <= \<const0>\;
s_axi_rdata(550) <= \<const0>\;
s_axi_rdata(549) <= \<const0>\;
s_axi_rdata(548) <= \<const0>\;
s_axi_rdata(547) <= \<const0>\;
s_axi_rdata(546) <= \<const0>\;
s_axi_rdata(545) <= \<const0>\;
s_axi_rdata(544) <= \<const0>\;
s_axi_rdata(543) <= \<const0>\;
s_axi_rdata(542) <= \<const0>\;
s_axi_rdata(541) <= \<const0>\;
s_axi_rdata(540) <= \<const0>\;
s_axi_rdata(539) <= \<const0>\;
s_axi_rdata(538) <= \<const0>\;
s_axi_rdata(537) <= \<const0>\;
s_axi_rdata(536) <= \<const0>\;
s_axi_rdata(535) <= \<const0>\;
s_axi_rdata(534) <= \<const0>\;
s_axi_rdata(533) <= \<const0>\;
s_axi_rdata(532) <= \<const0>\;
s_axi_rdata(531) <= \<const0>\;
s_axi_rdata(530) <= \<const0>\;
s_axi_rdata(529) <= \<const0>\;
s_axi_rdata(528) <= \<const0>\;
s_axi_rdata(527) <= \<const0>\;
s_axi_rdata(526) <= \<const0>\;
s_axi_rdata(525) <= \<const0>\;
s_axi_rdata(524) <= \<const0>\;
s_axi_rdata(523) <= \<const0>\;
s_axi_rdata(522) <= \<const0>\;
s_axi_rdata(521) <= \<const0>\;
s_axi_rdata(520) <= \<const0>\;
s_axi_rdata(519) <= \<const0>\;
s_axi_rdata(518) <= \<const0>\;
s_axi_rdata(517) <= \<const0>\;
s_axi_rdata(516) <= \<const0>\;
s_axi_rdata(515) <= \<const0>\;
s_axi_rdata(514) <= \<const0>\;
s_axi_rdata(513) <= \<const0>\;
s_axi_rdata(512) <= \<const0>\;
s_axi_rdata(511) <= \<const0>\;
s_axi_rdata(510) <= \<const0>\;
s_axi_rdata(509) <= \<const0>\;
s_axi_rdata(508) <= \<const0>\;
s_axi_rdata(507) <= \<const0>\;
s_axi_rdata(506) <= \<const0>\;
s_axi_rdata(505) <= \<const0>\;
s_axi_rdata(504) <= \<const0>\;
s_axi_rdata(503) <= \<const0>\;
s_axi_rdata(502) <= \<const0>\;
s_axi_rdata(501) <= \<const0>\;
s_axi_rdata(500) <= \<const0>\;
s_axi_rdata(499) <= \<const0>\;
s_axi_rdata(498) <= \<const0>\;
s_axi_rdata(497) <= \<const0>\;
s_axi_rdata(496) <= \<const0>\;
s_axi_rdata(495) <= \<const0>\;
s_axi_rdata(494) <= \<const0>\;
s_axi_rdata(493) <= \<const0>\;
s_axi_rdata(492) <= \<const0>\;
s_axi_rdata(491) <= \<const0>\;
s_axi_rdata(490) <= \<const0>\;
s_axi_rdata(489) <= \<const0>\;
s_axi_rdata(488) <= \<const0>\;
s_axi_rdata(487) <= \<const0>\;
s_axi_rdata(486) <= \<const0>\;
s_axi_rdata(485) <= \<const0>\;
s_axi_rdata(484) <= \<const0>\;
s_axi_rdata(483) <= \<const0>\;
s_axi_rdata(482) <= \<const0>\;
s_axi_rdata(481) <= \<const0>\;
s_axi_rdata(480) <= \<const0>\;
s_axi_rdata(479) <= \<const0>\;
s_axi_rdata(478) <= \<const0>\;
s_axi_rdata(477) <= \<const0>\;
s_axi_rdata(476) <= \<const0>\;
s_axi_rdata(475) <= \<const0>\;
s_axi_rdata(474) <= \<const0>\;
s_axi_rdata(473) <= \<const0>\;
s_axi_rdata(472) <= \<const0>\;
s_axi_rdata(471) <= \<const0>\;
s_axi_rdata(470) <= \<const0>\;
s_axi_rdata(469) <= \<const0>\;
s_axi_rdata(468) <= \<const0>\;
s_axi_rdata(467) <= \<const0>\;
s_axi_rdata(466) <= \<const0>\;
s_axi_rdata(465) <= \<const0>\;
s_axi_rdata(464) <= \<const0>\;
s_axi_rdata(463) <= \<const0>\;
s_axi_rdata(462) <= \<const0>\;
s_axi_rdata(461) <= \<const0>\;
s_axi_rdata(460) <= \<const0>\;
s_axi_rdata(459) <= \<const0>\;
s_axi_rdata(458) <= \<const0>\;
s_axi_rdata(457) <= \<const0>\;
s_axi_rdata(456) <= \<const0>\;
s_axi_rdata(455) <= \<const0>\;
s_axi_rdata(454) <= \<const0>\;
s_axi_rdata(453) <= \<const0>\;
s_axi_rdata(452) <= \<const0>\;
s_axi_rdata(451) <= \<const0>\;
s_axi_rdata(450) <= \<const0>\;
s_axi_rdata(449) <= \<const0>\;
s_axi_rdata(448) <= \<const0>\;
s_axi_rdata(447) <= \<const0>\;
s_axi_rdata(446) <= \<const0>\;
s_axi_rdata(445) <= \<const0>\;
s_axi_rdata(444) <= \<const0>\;
s_axi_rdata(443) <= \<const0>\;
s_axi_rdata(442) <= \<const0>\;
s_axi_rdata(441) <= \<const0>\;
s_axi_rdata(440) <= \<const0>\;
s_axi_rdata(439) <= \<const0>\;
s_axi_rdata(438) <= \<const0>\;
s_axi_rdata(437) <= \<const0>\;
s_axi_rdata(436) <= \<const0>\;
s_axi_rdata(435) <= \<const0>\;
s_axi_rdata(434) <= \<const0>\;
s_axi_rdata(433) <= \<const0>\;
s_axi_rdata(432) <= \<const0>\;
s_axi_rdata(431) <= \<const0>\;
s_axi_rdata(430) <= \<const0>\;
s_axi_rdata(429) <= \<const0>\;
s_axi_rdata(428) <= \<const0>\;
s_axi_rdata(427) <= \<const0>\;
s_axi_rdata(426) <= \<const0>\;
s_axi_rdata(425) <= \<const0>\;
s_axi_rdata(424) <= \<const0>\;
s_axi_rdata(423) <= \<const0>\;
s_axi_rdata(422) <= \<const0>\;
s_axi_rdata(421) <= \<const0>\;
s_axi_rdata(420) <= \<const0>\;
s_axi_rdata(419) <= \<const0>\;
s_axi_rdata(418) <= \<const0>\;
s_axi_rdata(417) <= \<const0>\;
s_axi_rdata(416) <= \<const0>\;
s_axi_rdata(415) <= \<const0>\;
s_axi_rdata(414) <= \<const0>\;
s_axi_rdata(413) <= \<const0>\;
s_axi_rdata(412) <= \<const0>\;
s_axi_rdata(411) <= \<const0>\;
s_axi_rdata(410) <= \<const0>\;
s_axi_rdata(409) <= \<const0>\;
s_axi_rdata(408) <= \<const0>\;
s_axi_rdata(407) <= \<const0>\;
s_axi_rdata(406) <= \<const0>\;
s_axi_rdata(405) <= \<const0>\;
s_axi_rdata(404) <= \<const0>\;
s_axi_rdata(403) <= \<const0>\;
s_axi_rdata(402) <= \<const0>\;
s_axi_rdata(401) <= \<const0>\;
s_axi_rdata(400) <= \<const0>\;
s_axi_rdata(399) <= \<const0>\;
s_axi_rdata(398) <= \<const0>\;
s_axi_rdata(397) <= \<const0>\;
s_axi_rdata(396) <= \<const0>\;
s_axi_rdata(395) <= \<const0>\;
s_axi_rdata(394) <= \<const0>\;
s_axi_rdata(393) <= \<const0>\;
s_axi_rdata(392) <= \<const0>\;
s_axi_rdata(391) <= \<const0>\;
s_axi_rdata(390) <= \<const0>\;
s_axi_rdata(389) <= \<const0>\;
s_axi_rdata(388) <= \<const0>\;
s_axi_rdata(387) <= \<const0>\;
s_axi_rdata(386) <= \<const0>\;
s_axi_rdata(385) <= \<const0>\;
s_axi_rdata(384) <= \<const0>\;
s_axi_rdata(383) <= \<const0>\;
s_axi_rdata(382) <= \<const0>\;
s_axi_rdata(381) <= \<const0>\;
s_axi_rdata(380) <= \<const0>\;
s_axi_rdata(379) <= \<const0>\;
s_axi_rdata(378) <= \<const0>\;
s_axi_rdata(377) <= \<const0>\;
s_axi_rdata(376) <= \<const0>\;
s_axi_rdata(375) <= \<const0>\;
s_axi_rdata(374) <= \<const0>\;
s_axi_rdata(373) <= \<const0>\;
s_axi_rdata(372) <= \<const0>\;
s_axi_rdata(371) <= \<const0>\;
s_axi_rdata(370) <= \<const0>\;
s_axi_rdata(369) <= \<const0>\;
s_axi_rdata(368) <= \<const0>\;
s_axi_rdata(367) <= \<const0>\;
s_axi_rdata(366) <= \<const0>\;
s_axi_rdata(365) <= \<const0>\;
s_axi_rdata(364) <= \<const0>\;
s_axi_rdata(363) <= \<const0>\;
s_axi_rdata(362) <= \<const0>\;
s_axi_rdata(361) <= \<const0>\;
s_axi_rdata(360) <= \<const0>\;
s_axi_rdata(359) <= \<const0>\;
s_axi_rdata(358) <= \<const0>\;
s_axi_rdata(357) <= \<const0>\;
s_axi_rdata(356) <= \<const0>\;
s_axi_rdata(355) <= \<const0>\;
s_axi_rdata(354) <= \<const0>\;
s_axi_rdata(353) <= \<const0>\;
s_axi_rdata(352) <= \<const0>\;
s_axi_rdata(351) <= \<const0>\;
s_axi_rdata(350) <= \<const0>\;
s_axi_rdata(349) <= \<const0>\;
s_axi_rdata(348) <= \<const0>\;
s_axi_rdata(347) <= \<const0>\;
s_axi_rdata(346) <= \<const0>\;
s_axi_rdata(345) <= \<const0>\;
s_axi_rdata(344) <= \<const0>\;
s_axi_rdata(343) <= \<const0>\;
s_axi_rdata(342) <= \<const0>\;
s_axi_rdata(341) <= \<const0>\;
s_axi_rdata(340) <= \<const0>\;
s_axi_rdata(339) <= \<const0>\;
s_axi_rdata(338) <= \<const0>\;
s_axi_rdata(337) <= \<const0>\;
s_axi_rdata(336) <= \<const0>\;
s_axi_rdata(335) <= \<const0>\;
s_axi_rdata(334) <= \<const0>\;
s_axi_rdata(333) <= \<const0>\;
s_axi_rdata(332) <= \<const0>\;
s_axi_rdata(331) <= \<const0>\;
s_axi_rdata(330) <= \<const0>\;
s_axi_rdata(329) <= \<const0>\;
s_axi_rdata(328) <= \<const0>\;
s_axi_rdata(327) <= \<const0>\;
s_axi_rdata(326) <= \<const0>\;
s_axi_rdata(325) <= \<const0>\;
s_axi_rdata(324) <= \<const0>\;
s_axi_rdata(323) <= \<const0>\;
s_axi_rdata(322) <= \<const0>\;
s_axi_rdata(321) <= \<const0>\;
s_axi_rdata(320) <= \<const0>\;
s_axi_rdata(319) <= \<const0>\;
s_axi_rdata(318) <= \<const0>\;
s_axi_rdata(317) <= \<const0>\;
s_axi_rdata(316) <= \<const0>\;
s_axi_rdata(315) <= \<const0>\;
s_axi_rdata(314) <= \<const0>\;
s_axi_rdata(313) <= \<const0>\;
s_axi_rdata(312) <= \<const0>\;
s_axi_rdata(311) <= \<const0>\;
s_axi_rdata(310) <= \<const0>\;
s_axi_rdata(309) <= \<const0>\;
s_axi_rdata(308) <= \<const0>\;
s_axi_rdata(307) <= \<const0>\;
s_axi_rdata(306) <= \<const0>\;
s_axi_rdata(305) <= \<const0>\;
s_axi_rdata(304) <= \<const0>\;
s_axi_rdata(303) <= \<const0>\;
s_axi_rdata(302) <= \<const0>\;
s_axi_rdata(301) <= \<const0>\;
s_axi_rdata(300) <= \<const0>\;
s_axi_rdata(299) <= \<const0>\;
s_axi_rdata(298) <= \<const0>\;
s_axi_rdata(297) <= \<const0>\;
s_axi_rdata(296) <= \<const0>\;
s_axi_rdata(295) <= \<const0>\;
s_axi_rdata(294) <= \<const0>\;
s_axi_rdata(293) <= \<const0>\;
s_axi_rdata(292) <= \<const0>\;
s_axi_rdata(291) <= \<const0>\;
s_axi_rdata(290) <= \<const0>\;
s_axi_rdata(289) <= \<const0>\;
s_axi_rdata(288) <= \<const0>\;
s_axi_rdata(287) <= \<const0>\;
s_axi_rdata(286) <= \<const0>\;
s_axi_rdata(285) <= \<const0>\;
s_axi_rdata(284) <= \<const0>\;
s_axi_rdata(283) <= \<const0>\;
s_axi_rdata(282) <= \<const0>\;
s_axi_rdata(281) <= \<const0>\;
s_axi_rdata(280) <= \<const0>\;
s_axi_rdata(279) <= \<const0>\;
s_axi_rdata(278) <= \<const0>\;
s_axi_rdata(277) <= \<const0>\;
s_axi_rdata(276) <= \<const0>\;
s_axi_rdata(275) <= \<const0>\;
s_axi_rdata(274) <= \<const0>\;
s_axi_rdata(273) <= \<const0>\;
s_axi_rdata(272) <= \<const0>\;
s_axi_rdata(271) <= \<const0>\;
s_axi_rdata(270) <= \<const0>\;
s_axi_rdata(269) <= \<const0>\;
s_axi_rdata(268) <= \<const0>\;
s_axi_rdata(267) <= \<const0>\;
s_axi_rdata(266) <= \<const0>\;
s_axi_rdata(265) <= \<const0>\;
s_axi_rdata(264) <= \<const0>\;
s_axi_rdata(263) <= \<const0>\;
s_axi_rdata(262) <= \<const0>\;
s_axi_rdata(261) <= \<const0>\;
s_axi_rdata(260) <= \<const0>\;
s_axi_rdata(259) <= \<const0>\;
s_axi_rdata(258) <= \<const0>\;
s_axi_rdata(257) <= \<const0>\;
s_axi_rdata(256) <= \<const0>\;
s_axi_rdata(255) <= \<const0>\;
s_axi_rdata(254) <= \<const0>\;
s_axi_rdata(253) <= \<const0>\;
s_axi_rdata(252) <= \<const0>\;
s_axi_rdata(251) <= \<const0>\;
s_axi_rdata(250) <= \<const0>\;
s_axi_rdata(249) <= \<const0>\;
s_axi_rdata(248) <= \<const0>\;
s_axi_rdata(247) <= \<const0>\;
s_axi_rdata(246) <= \<const0>\;
s_axi_rdata(245) <= \<const0>\;
s_axi_rdata(244) <= \<const0>\;
s_axi_rdata(243) <= \<const0>\;
s_axi_rdata(242) <= \<const0>\;
s_axi_rdata(241) <= \<const0>\;
s_axi_rdata(240) <= \<const0>\;
s_axi_rdata(239) <= \<const0>\;
s_axi_rdata(238) <= \<const0>\;
s_axi_rdata(237) <= \<const0>\;
s_axi_rdata(236) <= \<const0>\;
s_axi_rdata(235) <= \<const0>\;
s_axi_rdata(234) <= \<const0>\;
s_axi_rdata(233) <= \<const0>\;
s_axi_rdata(232) <= \<const0>\;
s_axi_rdata(231) <= \<const0>\;
s_axi_rdata(230) <= \<const0>\;
s_axi_rdata(229) <= \<const0>\;
s_axi_rdata(228) <= \<const0>\;
s_axi_rdata(227) <= \<const0>\;
s_axi_rdata(226) <= \<const0>\;
s_axi_rdata(225) <= \<const0>\;
s_axi_rdata(224) <= \<const0>\;
s_axi_rdata(223) <= \<const0>\;
s_axi_rdata(222) <= \<const0>\;
s_axi_rdata(221) <= \<const0>\;
s_axi_rdata(220) <= \<const0>\;
s_axi_rdata(219) <= \<const0>\;
s_axi_rdata(218) <= \<const0>\;
s_axi_rdata(217) <= \<const0>\;
s_axi_rdata(216) <= \<const0>\;
s_axi_rdata(215) <= \<const0>\;
s_axi_rdata(214) <= \<const0>\;
s_axi_rdata(213) <= \<const0>\;
s_axi_rdata(212) <= \<const0>\;
s_axi_rdata(211) <= \<const0>\;
s_axi_rdata(210) <= \<const0>\;
s_axi_rdata(209) <= \<const0>\;
s_axi_rdata(208) <= \<const0>\;
s_axi_rdata(207) <= \<const0>\;
s_axi_rdata(206) <= \<const0>\;
s_axi_rdata(205) <= \<const0>\;
s_axi_rdata(204) <= \<const0>\;
s_axi_rdata(203) <= \<const0>\;
s_axi_rdata(202) <= \<const0>\;
s_axi_rdata(201) <= \<const0>\;
s_axi_rdata(200) <= \<const0>\;
s_axi_rdata(199) <= \<const0>\;
s_axi_rdata(198) <= \<const0>\;
s_axi_rdata(197) <= \<const0>\;
s_axi_rdata(196) <= \<const0>\;
s_axi_rdata(195) <= \<const0>\;
s_axi_rdata(194) <= \<const0>\;
s_axi_rdata(193) <= \<const0>\;
s_axi_rdata(192) <= \<const0>\;
s_axi_rdata(191) <= \<const0>\;
s_axi_rdata(190) <= \<const0>\;
s_axi_rdata(189) <= \<const0>\;
s_axi_rdata(188) <= \<const0>\;
s_axi_rdata(187) <= \<const0>\;
s_axi_rdata(186) <= \<const0>\;
s_axi_rdata(185) <= \<const0>\;
s_axi_rdata(184) <= \<const0>\;
s_axi_rdata(183) <= \<const0>\;
s_axi_rdata(182) <= \<const0>\;
s_axi_rdata(181) <= \<const0>\;
s_axi_rdata(180) <= \<const0>\;
s_axi_rdata(179) <= \<const0>\;
s_axi_rdata(178) <= \<const0>\;
s_axi_rdata(177) <= \<const0>\;
s_axi_rdata(176) <= \<const0>\;
s_axi_rdata(175) <= \<const0>\;
s_axi_rdata(174) <= \<const0>\;
s_axi_rdata(173) <= \<const0>\;
s_axi_rdata(172) <= \<const0>\;
s_axi_rdata(171) <= \<const0>\;
s_axi_rdata(170) <= \<const0>\;
s_axi_rdata(169) <= \<const0>\;
s_axi_rdata(168) <= \<const0>\;
s_axi_rdata(167) <= \<const0>\;
s_axi_rdata(166) <= \<const0>\;
s_axi_rdata(165) <= \<const0>\;
s_axi_rdata(164) <= \<const0>\;
s_axi_rdata(163) <= \<const0>\;
s_axi_rdata(162) <= \<const0>\;
s_axi_rdata(161) <= \<const0>\;
s_axi_rdata(160) <= \<const0>\;
s_axi_rdata(159) <= \<const0>\;
s_axi_rdata(158) <= \<const0>\;
s_axi_rdata(157) <= \<const0>\;
s_axi_rdata(156) <= \<const0>\;
s_axi_rdata(155) <= \<const0>\;
s_axi_rdata(154) <= \<const0>\;
s_axi_rdata(153) <= \<const0>\;
s_axi_rdata(152) <= \<const0>\;
s_axi_rdata(151) <= \<const0>\;
s_axi_rdata(150) <= \<const0>\;
s_axi_rdata(149) <= \<const0>\;
s_axi_rdata(148) <= \<const0>\;
s_axi_rdata(147) <= \<const0>\;
s_axi_rdata(146) <= \<const0>\;
s_axi_rdata(145) <= \<const0>\;
s_axi_rdata(144) <= \<const0>\;
s_axi_rdata(143) <= \<const0>\;
s_axi_rdata(142) <= \<const0>\;
s_axi_rdata(141) <= \<const0>\;
s_axi_rdata(140) <= \<const0>\;
s_axi_rdata(139) <= \<const0>\;
s_axi_rdata(138) <= \<const0>\;
s_axi_rdata(137) <= \<const0>\;
s_axi_rdata(136) <= \<const0>\;
s_axi_rdata(135) <= \<const0>\;
s_axi_rdata(134) <= \<const0>\;
s_axi_rdata(133) <= \<const0>\;
s_axi_rdata(132) <= \<const0>\;
s_axi_rdata(131) <= \<const0>\;
s_axi_rdata(130) <= \<const0>\;
s_axi_rdata(129) <= \<const0>\;
s_axi_rdata(128) <= \<const0>\;
s_axi_rdata(127) <= \<const0>\;
s_axi_rdata(126) <= \<const0>\;
s_axi_rdata(125) <= \<const0>\;
s_axi_rdata(124) <= \<const0>\;
s_axi_rdata(123) <= \<const0>\;
s_axi_rdata(122) <= \<const0>\;
s_axi_rdata(121) <= \<const0>\;
s_axi_rdata(120) <= \<const0>\;
s_axi_rdata(119) <= \<const0>\;
s_axi_rdata(118) <= \<const0>\;
s_axi_rdata(117) <= \<const0>\;
s_axi_rdata(116) <= \<const0>\;
s_axi_rdata(115) <= \<const0>\;
s_axi_rdata(114) <= \<const0>\;
s_axi_rdata(113) <= \<const0>\;
s_axi_rdata(112) <= \<const0>\;
s_axi_rdata(111) <= \<const0>\;
s_axi_rdata(110) <= \<const0>\;
s_axi_rdata(109) <= \<const0>\;
s_axi_rdata(108) <= \<const0>\;
s_axi_rdata(107) <= \<const0>\;
s_axi_rdata(106) <= \<const0>\;
s_axi_rdata(105) <= \<const0>\;
s_axi_rdata(104) <= \<const0>\;
s_axi_rdata(103) <= \<const0>\;
s_axi_rdata(102) <= \<const0>\;
s_axi_rdata(101) <= \<const0>\;
s_axi_rdata(100) <= \<const0>\;
s_axi_rdata(99) <= \<const0>\;
s_axi_rdata(98) <= \<const0>\;
s_axi_rdata(97) <= \<const0>\;
s_axi_rdata(96) <= \<const0>\;
s_axi_rdata(95) <= \<const0>\;
s_axi_rdata(94) <= \<const0>\;
s_axi_rdata(93) <= \<const0>\;
s_axi_rdata(92) <= \<const0>\;
s_axi_rdata(91) <= \<const0>\;
s_axi_rdata(90) <= \<const0>\;
s_axi_rdata(89) <= \<const0>\;
s_axi_rdata(88) <= \<const0>\;
s_axi_rdata(87) <= \<const0>\;
s_axi_rdata(86) <= \<const0>\;
s_axi_rdata(85) <= \<const0>\;
s_axi_rdata(84) <= \<const0>\;
s_axi_rdata(83) <= \<const0>\;
s_axi_rdata(82) <= \<const0>\;
s_axi_rdata(81) <= \<const0>\;
s_axi_rdata(80) <= \<const0>\;
s_axi_rdata(79) <= \<const0>\;
s_axi_rdata(78) <= \<const0>\;
s_axi_rdata(77) <= \<const0>\;
s_axi_rdata(76) <= \<const0>\;
s_axi_rdata(75) <= \<const0>\;
s_axi_rdata(74) <= \<const0>\;
s_axi_rdata(73) <= \<const0>\;
s_axi_rdata(72) <= \<const0>\;
s_axi_rdata(71) <= \<const0>\;
s_axi_rdata(70) <= \<const0>\;
s_axi_rdata(69) <= \<const0>\;
s_axi_rdata(68) <= \<const0>\;
s_axi_rdata(67) <= \<const0>\;
s_axi_rdata(66) <= \<const0>\;
s_axi_rdata(65) <= \<const0>\;
s_axi_rdata(64) <= \<const0>\;
s_axi_rdata(63) <= \<const0>\;
s_axi_rdata(62) <= \<const0>\;
s_axi_rdata(61) <= \<const0>\;
s_axi_rdata(60) <= \<const0>\;
s_axi_rdata(59) <= \<const0>\;
s_axi_rdata(58) <= \<const0>\;
s_axi_rdata(57) <= \<const0>\;
s_axi_rdata(56) <= \<const0>\;
s_axi_rdata(55) <= \<const0>\;
s_axi_rdata(54) <= \<const0>\;
s_axi_rdata(53) <= \<const0>\;
s_axi_rdata(52) <= \<const0>\;
s_axi_rdata(51) <= \<const0>\;
s_axi_rdata(50) <= \<const0>\;
s_axi_rdata(49) <= \<const0>\;
s_axi_rdata(48) <= \<const0>\;
s_axi_rdata(47) <= \<const0>\;
s_axi_rdata(46) <= \<const0>\;
s_axi_rdata(45) <= \<const0>\;
s_axi_rdata(44) <= \<const0>\;
s_axi_rdata(43) <= \<const0>\;
s_axi_rdata(42) <= \<const0>\;
s_axi_rdata(41) <= \<const0>\;
s_axi_rdata(40) <= \<const0>\;
s_axi_rdata(39) <= \<const0>\;
s_axi_rdata(38) <= \<const0>\;
s_axi_rdata(37) <= \<const0>\;
s_axi_rdata(36) <= \<const0>\;
s_axi_rdata(35) <= \<const0>\;
s_axi_rdata(34) <= \<const0>\;
s_axi_rdata(33) <= \<const0>\;
s_axi_rdata(32) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.PSelect_blk_mem_gen_v8_2_synth
port map (
addra(9 downto 0) => addra(9 downto 0),
clka => clka,
douta(799 downto 0) => douta(799 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity PSelect is
port (
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 9 downto 0 );
douta : out STD_LOGIC_VECTOR ( 799 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of PSelect : entity is true;
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of PSelect : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of PSelect : entity is "blk_mem_gen_v8_2,Vivado 2014.4";
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of PSelect : entity is "PSelect,blk_mem_gen_v8_2,{}";
attribute core_generation_info : string;
attribute core_generation_info of PSelect : entity is "PSelect,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VHDL,x_ipSimLanguage=VHDL,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=3,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=PSelect.mif,C_INIT_FILE=PSelect.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=0,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=800,C_READ_WIDTH_A=800,C_WRITE_DEPTH_A=600,C_READ_DEPTH_A=600,C_ADDRA_WIDTH=10,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=800,C_READ_WIDTH_B=800,C_WRITE_DEPTH_B=600,C_READ_DEPTH_B=600,C_ADDRB_WIDTH=10,C_HAS_MEM_OUTPUT_REGS_A=1,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=22,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 60.4532 mW}";
end PSelect;
architecture STRUCTURE of PSelect is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 799 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 10;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 10;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "1";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "22";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 60.4532 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "PSelect.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "PSelect.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 3;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 600;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 600;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 800;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 800;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 600;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 600;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 800;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 800;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of U0 : label is std.standard.true;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.\PSelect_blk_mem_gen_v8_2__parameterized0\
port map (
addra(9 downto 0) => addra(9 downto 0),
addrb(9) => '0',
addrb(8) => '0',
addrb(7) => '0',
addrb(6) => '0',
addrb(5) => '0',
addrb(4) => '0',
addrb(3) => '0',
addrb(2) => '0',
addrb(1) => '0',
addrb(0) => '0',
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
dina(799) => '0',
dina(798) => '0',
dina(797) => '0',
dina(796) => '0',
dina(795) => '0',
dina(794) => '0',
dina(793) => '0',
dina(792) => '0',
dina(791) => '0',
dina(790) => '0',
dina(789) => '0',
dina(788) => '0',
dina(787) => '0',
dina(786) => '0',
dina(785) => '0',
dina(784) => '0',
dina(783) => '0',
dina(782) => '0',
dina(781) => '0',
dina(780) => '0',
dina(779) => '0',
dina(778) => '0',
dina(777) => '0',
dina(776) => '0',
dina(775) => '0',
dina(774) => '0',
dina(773) => '0',
dina(772) => '0',
dina(771) => '0',
dina(770) => '0',
dina(769) => '0',
dina(768) => '0',
dina(767) => '0',
dina(766) => '0',
dina(765) => '0',
dina(764) => '0',
dina(763) => '0',
dina(762) => '0',
dina(761) => '0',
dina(760) => '0',
dina(759) => '0',
dina(758) => '0',
dina(757) => '0',
dina(756) => '0',
dina(755) => '0',
dina(754) => '0',
dina(753) => '0',
dina(752) => '0',
dina(751) => '0',
dina(750) => '0',
dina(749) => '0',
dina(748) => '0',
dina(747) => '0',
dina(746) => '0',
dina(745) => '0',
dina(744) => '0',
dina(743) => '0',
dina(742) => '0',
dina(741) => '0',
dina(740) => '0',
dina(739) => '0',
dina(738) => '0',
dina(737) => '0',
dina(736) => '0',
dina(735) => '0',
dina(734) => '0',
dina(733) => '0',
dina(732) => '0',
dina(731) => '0',
dina(730) => '0',
dina(729) => '0',
dina(728) => '0',
dina(727) => '0',
dina(726) => '0',
dina(725) => '0',
dina(724) => '0',
dina(723) => '0',
dina(722) => '0',
dina(721) => '0',
dina(720) => '0',
dina(719) => '0',
dina(718) => '0',
dina(717) => '0',
dina(716) => '0',
dina(715) => '0',
dina(714) => '0',
dina(713) => '0',
dina(712) => '0',
dina(711) => '0',
dina(710) => '0',
dina(709) => '0',
dina(708) => '0',
dina(707) => '0',
dina(706) => '0',
dina(705) => '0',
dina(704) => '0',
dina(703) => '0',
dina(702) => '0',
dina(701) => '0',
dina(700) => '0',
dina(699) => '0',
dina(698) => '0',
dina(697) => '0',
dina(696) => '0',
dina(695) => '0',
dina(694) => '0',
dina(693) => '0',
dina(692) => '0',
dina(691) => '0',
dina(690) => '0',
dina(689) => '0',
dina(688) => '0',
dina(687) => '0',
dina(686) => '0',
dina(685) => '0',
dina(684) => '0',
dina(683) => '0',
dina(682) => '0',
dina(681) => '0',
dina(680) => '0',
dina(679) => '0',
dina(678) => '0',
dina(677) => '0',
dina(676) => '0',
dina(675) => '0',
dina(674) => '0',
dina(673) => '0',
dina(672) => '0',
dina(671) => '0',
dina(670) => '0',
dina(669) => '0',
dina(668) => '0',
dina(667) => '0',
dina(666) => '0',
dina(665) => '0',
dina(664) => '0',
dina(663) => '0',
dina(662) => '0',
dina(661) => '0',
dina(660) => '0',
dina(659) => '0',
dina(658) => '0',
dina(657) => '0',
dina(656) => '0',
dina(655) => '0',
dina(654) => '0',
dina(653) => '0',
dina(652) => '0',
dina(651) => '0',
dina(650) => '0',
dina(649) => '0',
dina(648) => '0',
dina(647) => '0',
dina(646) => '0',
dina(645) => '0',
dina(644) => '0',
dina(643) => '0',
dina(642) => '0',
dina(641) => '0',
dina(640) => '0',
dina(639) => '0',
dina(638) => '0',
dina(637) => '0',
dina(636) => '0',
dina(635) => '0',
dina(634) => '0',
dina(633) => '0',
dina(632) => '0',
dina(631) => '0',
dina(630) => '0',
dina(629) => '0',
dina(628) => '0',
dina(627) => '0',
dina(626) => '0',
dina(625) => '0',
dina(624) => '0',
dina(623) => '0',
dina(622) => '0',
dina(621) => '0',
dina(620) => '0',
dina(619) => '0',
dina(618) => '0',
dina(617) => '0',
dina(616) => '0',
dina(615) => '0',
dina(614) => '0',
dina(613) => '0',
dina(612) => '0',
dina(611) => '0',
dina(610) => '0',
dina(609) => '0',
dina(608) => '0',
dina(607) => '0',
dina(606) => '0',
dina(605) => '0',
dina(604) => '0',
dina(603) => '0',
dina(602) => '0',
dina(601) => '0',
dina(600) => '0',
dina(599) => '0',
dina(598) => '0',
dina(597) => '0',
dina(596) => '0',
dina(595) => '0',
dina(594) => '0',
dina(593) => '0',
dina(592) => '0',
dina(591) => '0',
dina(590) => '0',
dina(589) => '0',
dina(588) => '0',
dina(587) => '0',
dina(586) => '0',
dina(585) => '0',
dina(584) => '0',
dina(583) => '0',
dina(582) => '0',
dina(581) => '0',
dina(580) => '0',
dina(579) => '0',
dina(578) => '0',
dina(577) => '0',
dina(576) => '0',
dina(575) => '0',
dina(574) => '0',
dina(573) => '0',
dina(572) => '0',
dina(571) => '0',
dina(570) => '0',
dina(569) => '0',
dina(568) => '0',
dina(567) => '0',
dina(566) => '0',
dina(565) => '0',
dina(564) => '0',
dina(563) => '0',
dina(562) => '0',
dina(561) => '0',
dina(560) => '0',
dina(559) => '0',
dina(558) => '0',
dina(557) => '0',
dina(556) => '0',
dina(555) => '0',
dina(554) => '0',
dina(553) => '0',
dina(552) => '0',
dina(551) => '0',
dina(550) => '0',
dina(549) => '0',
dina(548) => '0',
dina(547) => '0',
dina(546) => '0',
dina(545) => '0',
dina(544) => '0',
dina(543) => '0',
dina(542) => '0',
dina(541) => '0',
dina(540) => '0',
dina(539) => '0',
dina(538) => '0',
dina(537) => '0',
dina(536) => '0',
dina(535) => '0',
dina(534) => '0',
dina(533) => '0',
dina(532) => '0',
dina(531) => '0',
dina(530) => '0',
dina(529) => '0',
dina(528) => '0',
dina(527) => '0',
dina(526) => '0',
dina(525) => '0',
dina(524) => '0',
dina(523) => '0',
dina(522) => '0',
dina(521) => '0',
dina(520) => '0',
dina(519) => '0',
dina(518) => '0',
dina(517) => '0',
dina(516) => '0',
dina(515) => '0',
dina(514) => '0',
dina(513) => '0',
dina(512) => '0',
dina(511) => '0',
dina(510) => '0',
dina(509) => '0',
dina(508) => '0',
dina(507) => '0',
dina(506) => '0',
dina(505) => '0',
dina(504) => '0',
dina(503) => '0',
dina(502) => '0',
dina(501) => '0',
dina(500) => '0',
dina(499) => '0',
dina(498) => '0',
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dinb(559) => '0',
dinb(558) => '0',
dinb(557) => '0',
dinb(556) => '0',
dinb(555) => '0',
dinb(554) => '0',
dinb(553) => '0',
dinb(552) => '0',
dinb(551) => '0',
dinb(550) => '0',
dinb(549) => '0',
dinb(548) => '0',
dinb(547) => '0',
dinb(546) => '0',
dinb(545) => '0',
dinb(544) => '0',
dinb(543) => '0',
dinb(542) => '0',
dinb(541) => '0',
dinb(540) => '0',
dinb(539) => '0',
dinb(538) => '0',
dinb(537) => '0',
dinb(536) => '0',
dinb(535) => '0',
dinb(534) => '0',
dinb(533) => '0',
dinb(532) => '0',
dinb(531) => '0',
dinb(530) => '0',
dinb(529) => '0',
dinb(528) => '0',
dinb(527) => '0',
dinb(526) => '0',
dinb(525) => '0',
dinb(524) => '0',
dinb(523) => '0',
dinb(522) => '0',
dinb(521) => '0',
dinb(520) => '0',
dinb(519) => '0',
dinb(518) => '0',
dinb(517) => '0',
dinb(516) => '0',
dinb(515) => '0',
dinb(514) => '0',
dinb(513) => '0',
dinb(512) => '0',
dinb(511) => '0',
dinb(510) => '0',
dinb(509) => '0',
dinb(508) => '0',
dinb(507) => '0',
dinb(506) => '0',
dinb(505) => '0',
dinb(504) => '0',
dinb(503) => '0',
dinb(502) => '0',
dinb(501) => '0',
dinb(500) => '0',
dinb(499) => '0',
dinb(498) => '0',
dinb(497) => '0',
dinb(496) => '0',
dinb(495) => '0',
dinb(494) => '0',
dinb(493) => '0',
dinb(492) => '0',
dinb(491) => '0',
dinb(490) => '0',
dinb(489) => '0',
dinb(488) => '0',
dinb(487) => '0',
dinb(486) => '0',
dinb(485) => '0',
dinb(484) => '0',
dinb(483) => '0',
dinb(482) => '0',
dinb(481) => '0',
dinb(480) => '0',
dinb(479) => '0',
dinb(478) => '0',
dinb(477) => '0',
dinb(476) => '0',
dinb(475) => '0',
dinb(474) => '0',
dinb(473) => '0',
dinb(472) => '0',
dinb(471) => '0',
dinb(470) => '0',
dinb(469) => '0',
dinb(468) => '0',
dinb(467) => '0',
dinb(466) => '0',
dinb(465) => '0',
dinb(464) => '0',
dinb(463) => '0',
dinb(462) => '0',
dinb(461) => '0',
dinb(460) => '0',
dinb(459) => '0',
dinb(458) => '0',
dinb(457) => '0',
dinb(456) => '0',
dinb(455) => '0',
dinb(454) => '0',
dinb(453) => '0',
dinb(452) => '0',
dinb(451) => '0',
dinb(450) => '0',
dinb(449) => '0',
dinb(448) => '0',
dinb(447) => '0',
dinb(446) => '0',
dinb(445) => '0',
dinb(444) => '0',
dinb(443) => '0',
dinb(442) => '0',
dinb(441) => '0',
dinb(440) => '0',
dinb(439) => '0',
dinb(438) => '0',
dinb(437) => '0',
dinb(436) => '0',
dinb(435) => '0',
dinb(434) => '0',
dinb(433) => '0',
dinb(432) => '0',
dinb(431) => '0',
dinb(430) => '0',
dinb(429) => '0',
dinb(428) => '0',
dinb(427) => '0',
dinb(426) => '0',
dinb(425) => '0',
dinb(424) => '0',
dinb(423) => '0',
dinb(422) => '0',
dinb(421) => '0',
dinb(420) => '0',
dinb(419) => '0',
dinb(418) => '0',
dinb(417) => '0',
dinb(416) => '0',
dinb(415) => '0',
dinb(414) => '0',
dinb(413) => '0',
dinb(412) => '0',
dinb(411) => '0',
dinb(410) => '0',
dinb(409) => '0',
dinb(408) => '0',
dinb(407) => '0',
dinb(406) => '0',
dinb(405) => '0',
dinb(404) => '0',
dinb(403) => '0',
dinb(402) => '0',
dinb(401) => '0',
dinb(400) => '0',
dinb(399) => '0',
dinb(398) => '0',
dinb(397) => '0',
dinb(396) => '0',
dinb(395) => '0',
dinb(394) => '0',
dinb(393) => '0',
dinb(392) => '0',
dinb(391) => '0',
dinb(390) => '0',
dinb(389) => '0',
dinb(388) => '0',
dinb(387) => '0',
dinb(386) => '0',
dinb(385) => '0',
dinb(384) => '0',
dinb(383) => '0',
dinb(382) => '0',
dinb(381) => '0',
dinb(380) => '0',
dinb(379) => '0',
dinb(378) => '0',
dinb(377) => '0',
dinb(376) => '0',
dinb(375) => '0',
dinb(374) => '0',
dinb(373) => '0',
dinb(372) => '0',
dinb(371) => '0',
dinb(370) => '0',
dinb(369) => '0',
dinb(368) => '0',
dinb(367) => '0',
dinb(366) => '0',
dinb(365) => '0',
dinb(364) => '0',
dinb(363) => '0',
dinb(362) => '0',
dinb(361) => '0',
dinb(360) => '0',
dinb(359) => '0',
dinb(358) => '0',
dinb(357) => '0',
dinb(356) => '0',
dinb(355) => '0',
dinb(354) => '0',
dinb(353) => '0',
dinb(352) => '0',
dinb(351) => '0',
dinb(350) => '0',
dinb(349) => '0',
dinb(348) => '0',
dinb(347) => '0',
dinb(346) => '0',
dinb(345) => '0',
dinb(344) => '0',
dinb(343) => '0',
dinb(342) => '0',
dinb(341) => '0',
dinb(340) => '0',
dinb(339) => '0',
dinb(338) => '0',
dinb(337) => '0',
dinb(336) => '0',
dinb(335) => '0',
dinb(334) => '0',
dinb(333) => '0',
dinb(332) => '0',
dinb(331) => '0',
dinb(330) => '0',
dinb(329) => '0',
dinb(328) => '0',
dinb(327) => '0',
dinb(326) => '0',
dinb(325) => '0',
dinb(324) => '0',
dinb(323) => '0',
dinb(322) => '0',
dinb(321) => '0',
dinb(320) => '0',
dinb(319) => '0',
dinb(318) => '0',
dinb(317) => '0',
dinb(316) => '0',
dinb(315) => '0',
dinb(314) => '0',
dinb(313) => '0',
dinb(312) => '0',
dinb(311) => '0',
dinb(310) => '0',
dinb(309) => '0',
dinb(308) => '0',
dinb(307) => '0',
dinb(306) => '0',
dinb(305) => '0',
dinb(304) => '0',
dinb(303) => '0',
dinb(302) => '0',
dinb(301) => '0',
dinb(300) => '0',
dinb(299) => '0',
dinb(298) => '0',
dinb(297) => '0',
dinb(296) => '0',
dinb(295) => '0',
dinb(294) => '0',
dinb(293) => '0',
dinb(292) => '0',
dinb(291) => '0',
dinb(290) => '0',
dinb(289) => '0',
dinb(288) => '0',
dinb(287) => '0',
dinb(286) => '0',
dinb(285) => '0',
dinb(284) => '0',
dinb(283) => '0',
dinb(282) => '0',
dinb(281) => '0',
dinb(280) => '0',
dinb(279) => '0',
dinb(278) => '0',
dinb(277) => '0',
dinb(276) => '0',
dinb(275) => '0',
dinb(274) => '0',
dinb(273) => '0',
dinb(272) => '0',
dinb(271) => '0',
dinb(270) => '0',
dinb(269) => '0',
dinb(268) => '0',
dinb(267) => '0',
dinb(266) => '0',
dinb(265) => '0',
dinb(264) => '0',
dinb(263) => '0',
dinb(262) => '0',
dinb(261) => '0',
dinb(260) => '0',
dinb(259) => '0',
dinb(258) => '0',
dinb(257) => '0',
dinb(256) => '0',
dinb(255) => '0',
dinb(254) => '0',
dinb(253) => '0',
dinb(252) => '0',
dinb(251) => '0',
dinb(250) => '0',
dinb(249) => '0',
dinb(248) => '0',
dinb(247) => '0',
dinb(246) => '0',
dinb(245) => '0',
dinb(244) => '0',
dinb(243) => '0',
dinb(242) => '0',
dinb(241) => '0',
dinb(240) => '0',
dinb(239) => '0',
dinb(238) => '0',
dinb(237) => '0',
dinb(236) => '0',
dinb(235) => '0',
dinb(234) => '0',
dinb(233) => '0',
dinb(232) => '0',
dinb(231) => '0',
dinb(230) => '0',
dinb(229) => '0',
dinb(228) => '0',
dinb(227) => '0',
dinb(226) => '0',
dinb(225) => '0',
dinb(224) => '0',
dinb(223) => '0',
dinb(222) => '0',
dinb(221) => '0',
dinb(220) => '0',
dinb(219) => '0',
dinb(218) => '0',
dinb(217) => '0',
dinb(216) => '0',
dinb(215) => '0',
dinb(214) => '0',
dinb(213) => '0',
dinb(212) => '0',
dinb(211) => '0',
dinb(210) => '0',
dinb(209) => '0',
dinb(208) => '0',
dinb(207) => '0',
dinb(206) => '0',
dinb(205) => '0',
dinb(204) => '0',
dinb(203) => '0',
dinb(202) => '0',
dinb(201) => '0',
dinb(200) => '0',
dinb(199) => '0',
dinb(198) => '0',
dinb(197) => '0',
dinb(196) => '0',
dinb(195) => '0',
dinb(194) => '0',
dinb(193) => '0',
dinb(192) => '0',
dinb(191) => '0',
dinb(190) => '0',
dinb(189) => '0',
dinb(188) => '0',
dinb(187) => '0',
dinb(186) => '0',
dinb(185) => '0',
dinb(184) => '0',
dinb(183) => '0',
dinb(182) => '0',
dinb(181) => '0',
dinb(180) => '0',
dinb(179) => '0',
dinb(178) => '0',
dinb(177) => '0',
dinb(176) => '0',
dinb(175) => '0',
dinb(174) => '0',
dinb(173) => '0',
dinb(172) => '0',
dinb(171) => '0',
dinb(170) => '0',
dinb(169) => '0',
dinb(168) => '0',
dinb(167) => '0',
dinb(166) => '0',
dinb(165) => '0',
dinb(164) => '0',
dinb(163) => '0',
dinb(162) => '0',
dinb(161) => '0',
dinb(160) => '0',
dinb(159) => '0',
dinb(158) => '0',
dinb(157) => '0',
dinb(156) => '0',
dinb(155) => '0',
dinb(154) => '0',
dinb(153) => '0',
dinb(152) => '0',
dinb(151) => '0',
dinb(150) => '0',
dinb(149) => '0',
dinb(148) => '0',
dinb(147) => '0',
dinb(146) => '0',
dinb(145) => '0',
dinb(144) => '0',
dinb(143) => '0',
dinb(142) => '0',
dinb(141) => '0',
dinb(140) => '0',
dinb(139) => '0',
dinb(138) => '0',
dinb(137) => '0',
dinb(136) => '0',
dinb(135) => '0',
dinb(134) => '0',
dinb(133) => '0',
dinb(132) => '0',
dinb(131) => '0',
dinb(130) => '0',
dinb(129) => '0',
dinb(128) => '0',
dinb(127) => '0',
dinb(126) => '0',
dinb(125) => '0',
dinb(124) => '0',
dinb(123) => '0',
dinb(122) => '0',
dinb(121) => '0',
dinb(120) => '0',
dinb(119) => '0',
dinb(118) => '0',
dinb(117) => '0',
dinb(116) => '0',
dinb(115) => '0',
dinb(114) => '0',
dinb(113) => '0',
dinb(112) => '0',
dinb(111) => '0',
dinb(110) => '0',
dinb(109) => '0',
dinb(108) => '0',
dinb(107) => '0',
dinb(106) => '0',
dinb(105) => '0',
dinb(104) => '0',
dinb(103) => '0',
dinb(102) => '0',
dinb(101) => '0',
dinb(100) => '0',
dinb(99) => '0',
dinb(98) => '0',
dinb(97) => '0',
dinb(96) => '0',
dinb(95) => '0',
dinb(94) => '0',
dinb(93) => '0',
dinb(92) => '0',
dinb(91) => '0',
dinb(90) => '0',
dinb(89) => '0',
dinb(88) => '0',
dinb(87) => '0',
dinb(86) => '0',
dinb(85) => '0',
dinb(84) => '0',
dinb(83) => '0',
dinb(82) => '0',
dinb(81) => '0',
dinb(80) => '0',
dinb(79) => '0',
dinb(78) => '0',
dinb(77) => '0',
dinb(76) => '0',
dinb(75) => '0',
dinb(74) => '0',
dinb(73) => '0',
dinb(72) => '0',
dinb(71) => '0',
dinb(70) => '0',
dinb(69) => '0',
dinb(68) => '0',
dinb(67) => '0',
dinb(66) => '0',
dinb(65) => '0',
dinb(64) => '0',
dinb(63) => '0',
dinb(62) => '0',
dinb(61) => '0',
dinb(60) => '0',
dinb(59) => '0',
dinb(58) => '0',
dinb(57) => '0',
dinb(56) => '0',
dinb(55) => '0',
dinb(54) => '0',
dinb(53) => '0',
dinb(52) => '0',
dinb(51) => '0',
dinb(50) => '0',
dinb(49) => '0',
dinb(48) => '0',
dinb(47) => '0',
dinb(46) => '0',
dinb(45) => '0',
dinb(44) => '0',
dinb(43) => '0',
dinb(42) => '0',
dinb(41) => '0',
dinb(40) => '0',
dinb(39) => '0',
dinb(38) => '0',
dinb(37) => '0',
dinb(36) => '0',
dinb(35) => '0',
dinb(34) => '0',
dinb(33) => '0',
dinb(32) => '0',
dinb(31) => '0',
dinb(30) => '0',
dinb(29) => '0',
dinb(28) => '0',
dinb(27) => '0',
dinb(26) => '0',
dinb(25) => '0',
dinb(24) => '0',
dinb(23) => '0',
dinb(22) => '0',
dinb(21) => '0',
dinb(20) => '0',
dinb(19) => '0',
dinb(18) => '0',
dinb(17) => '0',
dinb(16) => '0',
dinb(15) => '0',
dinb(14) => '0',
dinb(13) => '0',
dinb(12) => '0',
dinb(11) => '0',
dinb(10) => '0',
dinb(9) => '0',
dinb(8) => '0',
dinb(7) => '0',
dinb(6) => '0',
dinb(5) => '0',
dinb(4) => '0',
dinb(3) => '0',
dinb(2) => '0',
dinb(1) => '0',
dinb(0) => '0',
douta(799 downto 0) => douta(799 downto 0),
doutb(799 downto 0) => NLW_U0_doutb_UNCONNECTED(799 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(9 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(9 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rstb => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31) => '0',
s_axi_araddr(30) => '0',
s_axi_araddr(29) => '0',
s_axi_araddr(28) => '0',
s_axi_araddr(27) => '0',
s_axi_araddr(26) => '0',
s_axi_araddr(25) => '0',
s_axi_araddr(24) => '0',
s_axi_araddr(23) => '0',
s_axi_araddr(22) => '0',
s_axi_araddr(21) => '0',
s_axi_araddr(20) => '0',
s_axi_araddr(19) => '0',
s_axi_araddr(18) => '0',
s_axi_araddr(17) => '0',
s_axi_araddr(16) => '0',
s_axi_araddr(15) => '0',
s_axi_araddr(14) => '0',
s_axi_araddr(13) => '0',
s_axi_araddr(12) => '0',
s_axi_araddr(11) => '0',
s_axi_araddr(10) => '0',
s_axi_araddr(9) => '0',
s_axi_araddr(8) => '0',
s_axi_araddr(7) => '0',
s_axi_araddr(6) => '0',
s_axi_araddr(5) => '0',
s_axi_araddr(4) => '0',
s_axi_araddr(3) => '0',
s_axi_araddr(2) => '0',
s_axi_araddr(1) => '0',
s_axi_araddr(0) => '0',
s_axi_arburst(1) => '0',
s_axi_arburst(0) => '0',
s_axi_arid(3) => '0',
s_axi_arid(2) => '0',
s_axi_arid(1) => '0',
s_axi_arid(0) => '0',
s_axi_arlen(7) => '0',
s_axi_arlen(6) => '0',
s_axi_arlen(5) => '0',
s_axi_arlen(4) => '0',
s_axi_arlen(3) => '0',
s_axi_arlen(2) => '0',
s_axi_arlen(1) => '0',
s_axi_arlen(0) => '0',
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2) => '0',
s_axi_arsize(1) => '0',
s_axi_arsize(0) => '0',
s_axi_arvalid => '0',
s_axi_awaddr(31) => '0',
s_axi_awaddr(30) => '0',
s_axi_awaddr(29) => '0',
s_axi_awaddr(28) => '0',
s_axi_awaddr(27) => '0',
s_axi_awaddr(26) => '0',
s_axi_awaddr(25) => '0',
s_axi_awaddr(24) => '0',
s_axi_awaddr(23) => '0',
s_axi_awaddr(22) => '0',
s_axi_awaddr(21) => '0',
s_axi_awaddr(20) => '0',
s_axi_awaddr(19) => '0',
s_axi_awaddr(18) => '0',
s_axi_awaddr(17) => '0',
s_axi_awaddr(16) => '0',
s_axi_awaddr(15) => '0',
s_axi_awaddr(14) => '0',
s_axi_awaddr(13) => '0',
s_axi_awaddr(12) => '0',
s_axi_awaddr(11) => '0',
s_axi_awaddr(10) => '0',
s_axi_awaddr(9) => '0',
s_axi_awaddr(8) => '0',
s_axi_awaddr(7) => '0',
s_axi_awaddr(6) => '0',
s_axi_awaddr(5) => '0',
s_axi_awaddr(4) => '0',
s_axi_awaddr(3) => '0',
s_axi_awaddr(2) => '0',
s_axi_awaddr(1) => '0',
s_axi_awaddr(0) => '0',
s_axi_awburst(1) => '0',
s_axi_awburst(0) => '0',
s_axi_awid(3) => '0',
s_axi_awid(2) => '0',
s_axi_awid(1) => '0',
s_axi_awid(0) => '0',
s_axi_awlen(7) => '0',
s_axi_awlen(6) => '0',
s_axi_awlen(5) => '0',
s_axi_awlen(4) => '0',
s_axi_awlen(3) => '0',
s_axi_awlen(2) => '0',
s_axi_awlen(1) => '0',
s_axi_awlen(0) => '0',
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2) => '0',
s_axi_awsize(1) => '0',
s_axi_awsize(0) => '0',
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(9 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(9 downto 0),
s_axi_rdata(799 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(799 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(799) => '0',
s_axi_wdata(798) => '0',
s_axi_wdata(797) => '0',
s_axi_wdata(796) => '0',
s_axi_wdata(795) => '0',
s_axi_wdata(794) => '0',
s_axi_wdata(793) => '0',
s_axi_wdata(792) => '0',
s_axi_wdata(791) => '0',
s_axi_wdata(790) => '0',
s_axi_wdata(789) => '0',
s_axi_wdata(788) => '0',
s_axi_wdata(787) => '0',
s_axi_wdata(786) => '0',
s_axi_wdata(785) => '0',
s_axi_wdata(784) => '0',
s_axi_wdata(783) => '0',
s_axi_wdata(782) => '0',
s_axi_wdata(781) => '0',
s_axi_wdata(780) => '0',
s_axi_wdata(779) => '0',
s_axi_wdata(778) => '0',
s_axi_wdata(777) => '0',
s_axi_wdata(776) => '0',
s_axi_wdata(775) => '0',
s_axi_wdata(774) => '0',
s_axi_wdata(773) => '0',
s_axi_wdata(772) => '0',
s_axi_wdata(771) => '0',
s_axi_wdata(770) => '0',
s_axi_wdata(769) => '0',
s_axi_wdata(768) => '0',
s_axi_wdata(767) => '0',
s_axi_wdata(766) => '0',
s_axi_wdata(765) => '0',
s_axi_wdata(764) => '0',
s_axi_wdata(763) => '0',
s_axi_wdata(762) => '0',
s_axi_wdata(761) => '0',
s_axi_wdata(760) => '0',
s_axi_wdata(759) => '0',
s_axi_wdata(758) => '0',
s_axi_wdata(757) => '0',
s_axi_wdata(756) => '0',
s_axi_wdata(755) => '0',
s_axi_wdata(754) => '0',
s_axi_wdata(753) => '0',
s_axi_wdata(752) => '0',
s_axi_wdata(751) => '0',
s_axi_wdata(750) => '0',
s_axi_wdata(749) => '0',
s_axi_wdata(748) => '0',
s_axi_wdata(747) => '0',
s_axi_wdata(746) => '0',
s_axi_wdata(745) => '0',
s_axi_wdata(744) => '0',
s_axi_wdata(743) => '0',
s_axi_wdata(742) => '0',
s_axi_wdata(741) => '0',
s_axi_wdata(740) => '0',
s_axi_wdata(739) => '0',
s_axi_wdata(738) => '0',
s_axi_wdata(737) => '0',
s_axi_wdata(736) => '0',
s_axi_wdata(735) => '0',
s_axi_wdata(734) => '0',
s_axi_wdata(733) => '0',
s_axi_wdata(732) => '0',
s_axi_wdata(731) => '0',
s_axi_wdata(730) => '0',
s_axi_wdata(729) => '0',
s_axi_wdata(728) => '0',
s_axi_wdata(727) => '0',
s_axi_wdata(726) => '0',
s_axi_wdata(725) => '0',
s_axi_wdata(724) => '0',
s_axi_wdata(723) => '0',
s_axi_wdata(722) => '0',
s_axi_wdata(721) => '0',
s_axi_wdata(720) => '0',
s_axi_wdata(719) => '0',
s_axi_wdata(718) => '0',
s_axi_wdata(717) => '0',
s_axi_wdata(716) => '0',
s_axi_wdata(715) => '0',
s_axi_wdata(714) => '0',
s_axi_wdata(713) => '0',
s_axi_wdata(712) => '0',
s_axi_wdata(711) => '0',
s_axi_wdata(710) => '0',
s_axi_wdata(709) => '0',
s_axi_wdata(708) => '0',
s_axi_wdata(707) => '0',
s_axi_wdata(706) => '0',
s_axi_wdata(705) => '0',
s_axi_wdata(704) => '0',
s_axi_wdata(703) => '0',
s_axi_wdata(702) => '0',
s_axi_wdata(701) => '0',
s_axi_wdata(700) => '0',
s_axi_wdata(699) => '0',
s_axi_wdata(698) => '0',
s_axi_wdata(697) => '0',
s_axi_wdata(696) => '0',
s_axi_wdata(695) => '0',
s_axi_wdata(694) => '0',
s_axi_wdata(693) => '0',
s_axi_wdata(692) => '0',
s_axi_wdata(691) => '0',
s_axi_wdata(690) => '0',
s_axi_wdata(689) => '0',
s_axi_wdata(688) => '0',
s_axi_wdata(687) => '0',
s_axi_wdata(686) => '0',
s_axi_wdata(685) => '0',
s_axi_wdata(684) => '0',
s_axi_wdata(683) => '0',
s_axi_wdata(682) => '0',
s_axi_wdata(681) => '0',
s_axi_wdata(680) => '0',
s_axi_wdata(679) => '0',
s_axi_wdata(678) => '0',
s_axi_wdata(677) => '0',
s_axi_wdata(676) => '0',
s_axi_wdata(675) => '0',
s_axi_wdata(674) => '0',
s_axi_wdata(673) => '0',
s_axi_wdata(672) => '0',
s_axi_wdata(671) => '0',
s_axi_wdata(670) => '0',
s_axi_wdata(669) => '0',
s_axi_wdata(668) => '0',
s_axi_wdata(667) => '0',
s_axi_wdata(666) => '0',
s_axi_wdata(665) => '0',
s_axi_wdata(664) => '0',
s_axi_wdata(663) => '0',
s_axi_wdata(662) => '0',
s_axi_wdata(661) => '0',
s_axi_wdata(660) => '0',
s_axi_wdata(659) => '0',
s_axi_wdata(658) => '0',
s_axi_wdata(657) => '0',
s_axi_wdata(656) => '0',
s_axi_wdata(655) => '0',
s_axi_wdata(654) => '0',
s_axi_wdata(653) => '0',
s_axi_wdata(652) => '0',
s_axi_wdata(651) => '0',
s_axi_wdata(650) => '0',
s_axi_wdata(649) => '0',
s_axi_wdata(648) => '0',
s_axi_wdata(647) => '0',
s_axi_wdata(646) => '0',
s_axi_wdata(645) => '0',
s_axi_wdata(644) => '0',
s_axi_wdata(643) => '0',
s_axi_wdata(642) => '0',
s_axi_wdata(641) => '0',
s_axi_wdata(640) => '0',
s_axi_wdata(639) => '0',
s_axi_wdata(638) => '0',
s_axi_wdata(637) => '0',
s_axi_wdata(636) => '0',
s_axi_wdata(635) => '0',
s_axi_wdata(634) => '0',
s_axi_wdata(633) => '0',
s_axi_wdata(632) => '0',
s_axi_wdata(631) => '0',
s_axi_wdata(630) => '0',
s_axi_wdata(629) => '0',
s_axi_wdata(628) => '0',
s_axi_wdata(627) => '0',
s_axi_wdata(626) => '0',
s_axi_wdata(625) => '0',
s_axi_wdata(624) => '0',
s_axi_wdata(623) => '0',
s_axi_wdata(622) => '0',
s_axi_wdata(621) => '0',
s_axi_wdata(620) => '0',
s_axi_wdata(619) => '0',
s_axi_wdata(618) => '0',
s_axi_wdata(617) => '0',
s_axi_wdata(616) => '0',
s_axi_wdata(615) => '0',
s_axi_wdata(614) => '0',
s_axi_wdata(613) => '0',
s_axi_wdata(612) => '0',
s_axi_wdata(611) => '0',
s_axi_wdata(610) => '0',
s_axi_wdata(609) => '0',
s_axi_wdata(608) => '0',
s_axi_wdata(607) => '0',
s_axi_wdata(606) => '0',
s_axi_wdata(605) => '0',
s_axi_wdata(604) => '0',
s_axi_wdata(603) => '0',
s_axi_wdata(602) => '0',
s_axi_wdata(601) => '0',
s_axi_wdata(600) => '0',
s_axi_wdata(599) => '0',
s_axi_wdata(598) => '0',
s_axi_wdata(597) => '0',
s_axi_wdata(596) => '0',
s_axi_wdata(595) => '0',
s_axi_wdata(594) => '0',
s_axi_wdata(593) => '0',
s_axi_wdata(592) => '0',
s_axi_wdata(591) => '0',
s_axi_wdata(590) => '0',
s_axi_wdata(589) => '0',
s_axi_wdata(588) => '0',
s_axi_wdata(587) => '0',
s_axi_wdata(586) => '0',
s_axi_wdata(585) => '0',
s_axi_wdata(584) => '0',
s_axi_wdata(583) => '0',
s_axi_wdata(582) => '0',
s_axi_wdata(581) => '0',
s_axi_wdata(580) => '0',
s_axi_wdata(579) => '0',
s_axi_wdata(578) => '0',
s_axi_wdata(577) => '0',
s_axi_wdata(576) => '0',
s_axi_wdata(575) => '0',
s_axi_wdata(574) => '0',
s_axi_wdata(573) => '0',
s_axi_wdata(572) => '0',
s_axi_wdata(571) => '0',
s_axi_wdata(570) => '0',
s_axi_wdata(569) => '0',
s_axi_wdata(568) => '0',
s_axi_wdata(567) => '0',
s_axi_wdata(566) => '0',
s_axi_wdata(565) => '0',
s_axi_wdata(564) => '0',
s_axi_wdata(563) => '0',
s_axi_wdata(562) => '0',
s_axi_wdata(561) => '0',
s_axi_wdata(560) => '0',
s_axi_wdata(559) => '0',
s_axi_wdata(558) => '0',
s_axi_wdata(557) => '0',
s_axi_wdata(556) => '0',
s_axi_wdata(555) => '0',
s_axi_wdata(554) => '0',
s_axi_wdata(553) => '0',
s_axi_wdata(552) => '0',
s_axi_wdata(551) => '0',
s_axi_wdata(550) => '0',
s_axi_wdata(549) => '0',
s_axi_wdata(548) => '0',
s_axi_wdata(547) => '0',
s_axi_wdata(546) => '0',
s_axi_wdata(545) => '0',
s_axi_wdata(544) => '0',
s_axi_wdata(543) => '0',
s_axi_wdata(542) => '0',
s_axi_wdata(541) => '0',
s_axi_wdata(540) => '0',
s_axi_wdata(539) => '0',
s_axi_wdata(538) => '0',
s_axi_wdata(537) => '0',
s_axi_wdata(536) => '0',
s_axi_wdata(535) => '0',
s_axi_wdata(534) => '0',
s_axi_wdata(533) => '0',
s_axi_wdata(532) => '0',
s_axi_wdata(531) => '0',
s_axi_wdata(530) => '0',
s_axi_wdata(529) => '0',
s_axi_wdata(528) => '0',
s_axi_wdata(527) => '0',
s_axi_wdata(526) => '0',
s_axi_wdata(525) => '0',
s_axi_wdata(524) => '0',
s_axi_wdata(523) => '0',
s_axi_wdata(522) => '0',
s_axi_wdata(521) => '0',
s_axi_wdata(520) => '0',
s_axi_wdata(519) => '0',
s_axi_wdata(518) => '0',
s_axi_wdata(517) => '0',
s_axi_wdata(516) => '0',
s_axi_wdata(515) => '0',
s_axi_wdata(514) => '0',
s_axi_wdata(513) => '0',
s_axi_wdata(512) => '0',
s_axi_wdata(511) => '0',
s_axi_wdata(510) => '0',
s_axi_wdata(509) => '0',
s_axi_wdata(508) => '0',
s_axi_wdata(507) => '0',
s_axi_wdata(506) => '0',
s_axi_wdata(505) => '0',
s_axi_wdata(504) => '0',
s_axi_wdata(503) => '0',
s_axi_wdata(502) => '0',
s_axi_wdata(501) => '0',
s_axi_wdata(500) => '0',
s_axi_wdata(499) => '0',
s_axi_wdata(498) => '0',
s_axi_wdata(497) => '0',
s_axi_wdata(496) => '0',
s_axi_wdata(495) => '0',
s_axi_wdata(494) => '0',
s_axi_wdata(493) => '0',
s_axi_wdata(492) => '0',
s_axi_wdata(491) => '0',
s_axi_wdata(490) => '0',
s_axi_wdata(489) => '0',
s_axi_wdata(488) => '0',
s_axi_wdata(487) => '0',
s_axi_wdata(486) => '0',
s_axi_wdata(485) => '0',
s_axi_wdata(484) => '0',
s_axi_wdata(483) => '0',
s_axi_wdata(482) => '0',
s_axi_wdata(481) => '0',
s_axi_wdata(480) => '0',
s_axi_wdata(479) => '0',
s_axi_wdata(478) => '0',
s_axi_wdata(477) => '0',
s_axi_wdata(476) => '0',
s_axi_wdata(475) => '0',
s_axi_wdata(474) => '0',
s_axi_wdata(473) => '0',
s_axi_wdata(472) => '0',
s_axi_wdata(471) => '0',
s_axi_wdata(470) => '0',
s_axi_wdata(469) => '0',
s_axi_wdata(468) => '0',
s_axi_wdata(467) => '0',
s_axi_wdata(466) => '0',
s_axi_wdata(465) => '0',
s_axi_wdata(464) => '0',
s_axi_wdata(463) => '0',
s_axi_wdata(462) => '0',
s_axi_wdata(461) => '0',
s_axi_wdata(460) => '0',
s_axi_wdata(459) => '0',
s_axi_wdata(458) => '0',
s_axi_wdata(457) => '0',
s_axi_wdata(456) => '0',
s_axi_wdata(455) => '0',
s_axi_wdata(454) => '0',
s_axi_wdata(453) => '0',
s_axi_wdata(452) => '0',
s_axi_wdata(451) => '0',
s_axi_wdata(450) => '0',
s_axi_wdata(449) => '0',
s_axi_wdata(448) => '0',
s_axi_wdata(447) => '0',
s_axi_wdata(446) => '0',
s_axi_wdata(445) => '0',
s_axi_wdata(444) => '0',
s_axi_wdata(443) => '0',
s_axi_wdata(442) => '0',
s_axi_wdata(441) => '0',
s_axi_wdata(440) => '0',
s_axi_wdata(439) => '0',
s_axi_wdata(438) => '0',
s_axi_wdata(437) => '0',
s_axi_wdata(436) => '0',
s_axi_wdata(435) => '0',
s_axi_wdata(434) => '0',
s_axi_wdata(433) => '0',
s_axi_wdata(432) => '0',
s_axi_wdata(431) => '0',
s_axi_wdata(430) => '0',
s_axi_wdata(429) => '0',
s_axi_wdata(428) => '0',
s_axi_wdata(427) => '0',
s_axi_wdata(426) => '0',
s_axi_wdata(425) => '0',
s_axi_wdata(424) => '0',
s_axi_wdata(423) => '0',
s_axi_wdata(422) => '0',
s_axi_wdata(421) => '0',
s_axi_wdata(420) => '0',
s_axi_wdata(419) => '0',
s_axi_wdata(418) => '0',
s_axi_wdata(417) => '0',
s_axi_wdata(416) => '0',
s_axi_wdata(415) => '0',
s_axi_wdata(414) => '0',
s_axi_wdata(413) => '0',
s_axi_wdata(412) => '0',
s_axi_wdata(411) => '0',
s_axi_wdata(410) => '0',
s_axi_wdata(409) => '0',
s_axi_wdata(408) => '0',
s_axi_wdata(407) => '0',
s_axi_wdata(406) => '0',
s_axi_wdata(405) => '0',
s_axi_wdata(404) => '0',
s_axi_wdata(403) => '0',
s_axi_wdata(402) => '0',
s_axi_wdata(401) => '0',
s_axi_wdata(400) => '0',
s_axi_wdata(399) => '0',
s_axi_wdata(398) => '0',
s_axi_wdata(397) => '0',
s_axi_wdata(396) => '0',
s_axi_wdata(395) => '0',
s_axi_wdata(394) => '0',
s_axi_wdata(393) => '0',
s_axi_wdata(392) => '0',
s_axi_wdata(391) => '0',
s_axi_wdata(390) => '0',
s_axi_wdata(389) => '0',
s_axi_wdata(388) => '0',
s_axi_wdata(387) => '0',
s_axi_wdata(386) => '0',
s_axi_wdata(385) => '0',
s_axi_wdata(384) => '0',
s_axi_wdata(383) => '0',
s_axi_wdata(382) => '0',
s_axi_wdata(381) => '0',
s_axi_wdata(380) => '0',
s_axi_wdata(379) => '0',
s_axi_wdata(378) => '0',
s_axi_wdata(377) => '0',
s_axi_wdata(376) => '0',
s_axi_wdata(375) => '0',
s_axi_wdata(374) => '0',
s_axi_wdata(373) => '0',
s_axi_wdata(372) => '0',
s_axi_wdata(371) => '0',
s_axi_wdata(370) => '0',
s_axi_wdata(369) => '0',
s_axi_wdata(368) => '0',
s_axi_wdata(367) => '0',
s_axi_wdata(366) => '0',
s_axi_wdata(365) => '0',
s_axi_wdata(364) => '0',
s_axi_wdata(363) => '0',
s_axi_wdata(362) => '0',
s_axi_wdata(361) => '0',
s_axi_wdata(360) => '0',
s_axi_wdata(359) => '0',
s_axi_wdata(358) => '0',
s_axi_wdata(357) => '0',
s_axi_wdata(356) => '0',
s_axi_wdata(355) => '0',
s_axi_wdata(354) => '0',
s_axi_wdata(353) => '0',
s_axi_wdata(352) => '0',
s_axi_wdata(351) => '0',
s_axi_wdata(350) => '0',
s_axi_wdata(349) => '0',
s_axi_wdata(348) => '0',
s_axi_wdata(347) => '0',
s_axi_wdata(346) => '0',
s_axi_wdata(345) => '0',
s_axi_wdata(344) => '0',
s_axi_wdata(343) => '0',
s_axi_wdata(342) => '0',
s_axi_wdata(341) => '0',
s_axi_wdata(340) => '0',
s_axi_wdata(339) => '0',
s_axi_wdata(338) => '0',
s_axi_wdata(337) => '0',
s_axi_wdata(336) => '0',
s_axi_wdata(335) => '0',
s_axi_wdata(334) => '0',
s_axi_wdata(333) => '0',
s_axi_wdata(332) => '0',
s_axi_wdata(331) => '0',
s_axi_wdata(330) => '0',
s_axi_wdata(329) => '0',
s_axi_wdata(328) => '0',
s_axi_wdata(327) => '0',
s_axi_wdata(326) => '0',
s_axi_wdata(325) => '0',
s_axi_wdata(324) => '0',
s_axi_wdata(323) => '0',
s_axi_wdata(322) => '0',
s_axi_wdata(321) => '0',
s_axi_wdata(320) => '0',
s_axi_wdata(319) => '0',
s_axi_wdata(318) => '0',
s_axi_wdata(317) => '0',
s_axi_wdata(316) => '0',
s_axi_wdata(315) => '0',
s_axi_wdata(314) => '0',
s_axi_wdata(313) => '0',
s_axi_wdata(312) => '0',
s_axi_wdata(311) => '0',
s_axi_wdata(310) => '0',
s_axi_wdata(309) => '0',
s_axi_wdata(308) => '0',
s_axi_wdata(307) => '0',
s_axi_wdata(306) => '0',
s_axi_wdata(305) => '0',
s_axi_wdata(304) => '0',
s_axi_wdata(303) => '0',
s_axi_wdata(302) => '0',
s_axi_wdata(301) => '0',
s_axi_wdata(300) => '0',
s_axi_wdata(299) => '0',
s_axi_wdata(298) => '0',
s_axi_wdata(297) => '0',
s_axi_wdata(296) => '0',
s_axi_wdata(295) => '0',
s_axi_wdata(294) => '0',
s_axi_wdata(293) => '0',
s_axi_wdata(292) => '0',
s_axi_wdata(291) => '0',
s_axi_wdata(290) => '0',
s_axi_wdata(289) => '0',
s_axi_wdata(288) => '0',
s_axi_wdata(287) => '0',
s_axi_wdata(286) => '0',
s_axi_wdata(285) => '0',
s_axi_wdata(284) => '0',
s_axi_wdata(283) => '0',
s_axi_wdata(282) => '0',
s_axi_wdata(281) => '0',
s_axi_wdata(280) => '0',
s_axi_wdata(279) => '0',
s_axi_wdata(278) => '0',
s_axi_wdata(277) => '0',
s_axi_wdata(276) => '0',
s_axi_wdata(275) => '0',
s_axi_wdata(274) => '0',
s_axi_wdata(273) => '0',
s_axi_wdata(272) => '0',
s_axi_wdata(271) => '0',
s_axi_wdata(270) => '0',
s_axi_wdata(269) => '0',
s_axi_wdata(268) => '0',
s_axi_wdata(267) => '0',
s_axi_wdata(266) => '0',
s_axi_wdata(265) => '0',
s_axi_wdata(264) => '0',
s_axi_wdata(263) => '0',
s_axi_wdata(262) => '0',
s_axi_wdata(261) => '0',
s_axi_wdata(260) => '0',
s_axi_wdata(259) => '0',
s_axi_wdata(258) => '0',
s_axi_wdata(257) => '0',
s_axi_wdata(256) => '0',
s_axi_wdata(255) => '0',
s_axi_wdata(254) => '0',
s_axi_wdata(253) => '0',
s_axi_wdata(252) => '0',
s_axi_wdata(251) => '0',
s_axi_wdata(250) => '0',
s_axi_wdata(249) => '0',
s_axi_wdata(248) => '0',
s_axi_wdata(247) => '0',
s_axi_wdata(246) => '0',
s_axi_wdata(245) => '0',
s_axi_wdata(244) => '0',
s_axi_wdata(243) => '0',
s_axi_wdata(242) => '0',
s_axi_wdata(241) => '0',
s_axi_wdata(240) => '0',
s_axi_wdata(239) => '0',
s_axi_wdata(238) => '0',
s_axi_wdata(237) => '0',
s_axi_wdata(236) => '0',
s_axi_wdata(235) => '0',
s_axi_wdata(234) => '0',
s_axi_wdata(233) => '0',
s_axi_wdata(232) => '0',
s_axi_wdata(231) => '0',
s_axi_wdata(230) => '0',
s_axi_wdata(229) => '0',
s_axi_wdata(228) => '0',
s_axi_wdata(227) => '0',
s_axi_wdata(226) => '0',
s_axi_wdata(225) => '0',
s_axi_wdata(224) => '0',
s_axi_wdata(223) => '0',
s_axi_wdata(222) => '0',
s_axi_wdata(221) => '0',
s_axi_wdata(220) => '0',
s_axi_wdata(219) => '0',
s_axi_wdata(218) => '0',
s_axi_wdata(217) => '0',
s_axi_wdata(216) => '0',
s_axi_wdata(215) => '0',
s_axi_wdata(214) => '0',
s_axi_wdata(213) => '0',
s_axi_wdata(212) => '0',
s_axi_wdata(211) => '0',
s_axi_wdata(210) => '0',
s_axi_wdata(209) => '0',
s_axi_wdata(208) => '0',
s_axi_wdata(207) => '0',
s_axi_wdata(206) => '0',
s_axi_wdata(205) => '0',
s_axi_wdata(204) => '0',
s_axi_wdata(203) => '0',
s_axi_wdata(202) => '0',
s_axi_wdata(201) => '0',
s_axi_wdata(200) => '0',
s_axi_wdata(199) => '0',
s_axi_wdata(198) => '0',
s_axi_wdata(197) => '0',
s_axi_wdata(196) => '0',
s_axi_wdata(195) => '0',
s_axi_wdata(194) => '0',
s_axi_wdata(193) => '0',
s_axi_wdata(192) => '0',
s_axi_wdata(191) => '0',
s_axi_wdata(190) => '0',
s_axi_wdata(189) => '0',
s_axi_wdata(188) => '0',
s_axi_wdata(187) => '0',
s_axi_wdata(186) => '0',
s_axi_wdata(185) => '0',
s_axi_wdata(184) => '0',
s_axi_wdata(183) => '0',
s_axi_wdata(182) => '0',
s_axi_wdata(181) => '0',
s_axi_wdata(180) => '0',
s_axi_wdata(179) => '0',
s_axi_wdata(178) => '0',
s_axi_wdata(177) => '0',
s_axi_wdata(176) => '0',
s_axi_wdata(175) => '0',
s_axi_wdata(174) => '0',
s_axi_wdata(173) => '0',
s_axi_wdata(172) => '0',
s_axi_wdata(171) => '0',
s_axi_wdata(170) => '0',
s_axi_wdata(169) => '0',
s_axi_wdata(168) => '0',
s_axi_wdata(167) => '0',
s_axi_wdata(166) => '0',
s_axi_wdata(165) => '0',
s_axi_wdata(164) => '0',
s_axi_wdata(163) => '0',
s_axi_wdata(162) => '0',
s_axi_wdata(161) => '0',
s_axi_wdata(160) => '0',
s_axi_wdata(159) => '0',
s_axi_wdata(158) => '0',
s_axi_wdata(157) => '0',
s_axi_wdata(156) => '0',
s_axi_wdata(155) => '0',
s_axi_wdata(154) => '0',
s_axi_wdata(153) => '0',
s_axi_wdata(152) => '0',
s_axi_wdata(151) => '0',
s_axi_wdata(150) => '0',
s_axi_wdata(149) => '0',
s_axi_wdata(148) => '0',
s_axi_wdata(147) => '0',
s_axi_wdata(146) => '0',
s_axi_wdata(145) => '0',
s_axi_wdata(144) => '0',
s_axi_wdata(143) => '0',
s_axi_wdata(142) => '0',
s_axi_wdata(141) => '0',
s_axi_wdata(140) => '0',
s_axi_wdata(139) => '0',
s_axi_wdata(138) => '0',
s_axi_wdata(137) => '0',
s_axi_wdata(136) => '0',
s_axi_wdata(135) => '0',
s_axi_wdata(134) => '0',
s_axi_wdata(133) => '0',
s_axi_wdata(132) => '0',
s_axi_wdata(131) => '0',
s_axi_wdata(130) => '0',
s_axi_wdata(129) => '0',
s_axi_wdata(128) => '0',
s_axi_wdata(127) => '0',
s_axi_wdata(126) => '0',
s_axi_wdata(125) => '0',
s_axi_wdata(124) => '0',
s_axi_wdata(123) => '0',
s_axi_wdata(122) => '0',
s_axi_wdata(121) => '0',
s_axi_wdata(120) => '0',
s_axi_wdata(119) => '0',
s_axi_wdata(118) => '0',
s_axi_wdata(117) => '0',
s_axi_wdata(116) => '0',
s_axi_wdata(115) => '0',
s_axi_wdata(114) => '0',
s_axi_wdata(113) => '0',
s_axi_wdata(112) => '0',
s_axi_wdata(111) => '0',
s_axi_wdata(110) => '0',
s_axi_wdata(109) => '0',
s_axi_wdata(108) => '0',
s_axi_wdata(107) => '0',
s_axi_wdata(106) => '0',
s_axi_wdata(105) => '0',
s_axi_wdata(104) => '0',
s_axi_wdata(103) => '0',
s_axi_wdata(102) => '0',
s_axi_wdata(101) => '0',
s_axi_wdata(100) => '0',
s_axi_wdata(99) => '0',
s_axi_wdata(98) => '0',
s_axi_wdata(97) => '0',
s_axi_wdata(96) => '0',
s_axi_wdata(95) => '0',
s_axi_wdata(94) => '0',
s_axi_wdata(93) => '0',
s_axi_wdata(92) => '0',
s_axi_wdata(91) => '0',
s_axi_wdata(90) => '0',
s_axi_wdata(89) => '0',
s_axi_wdata(88) => '0',
s_axi_wdata(87) => '0',
s_axi_wdata(86) => '0',
s_axi_wdata(85) => '0',
s_axi_wdata(84) => '0',
s_axi_wdata(83) => '0',
s_axi_wdata(82) => '0',
s_axi_wdata(81) => '0',
s_axi_wdata(80) => '0',
s_axi_wdata(79) => '0',
s_axi_wdata(78) => '0',
s_axi_wdata(77) => '0',
s_axi_wdata(76) => '0',
s_axi_wdata(75) => '0',
s_axi_wdata(74) => '0',
s_axi_wdata(73) => '0',
s_axi_wdata(72) => '0',
s_axi_wdata(71) => '0',
s_axi_wdata(70) => '0',
s_axi_wdata(69) => '0',
s_axi_wdata(68) => '0',
s_axi_wdata(67) => '0',
s_axi_wdata(66) => '0',
s_axi_wdata(65) => '0',
s_axi_wdata(64) => '0',
s_axi_wdata(63) => '0',
s_axi_wdata(62) => '0',
s_axi_wdata(61) => '0',
s_axi_wdata(60) => '0',
s_axi_wdata(59) => '0',
s_axi_wdata(58) => '0',
s_axi_wdata(57) => '0',
s_axi_wdata(56) => '0',
s_axi_wdata(55) => '0',
s_axi_wdata(54) => '0',
s_axi_wdata(53) => '0',
s_axi_wdata(52) => '0',
s_axi_wdata(51) => '0',
s_axi_wdata(50) => '0',
s_axi_wdata(49) => '0',
s_axi_wdata(48) => '0',
s_axi_wdata(47) => '0',
s_axi_wdata(46) => '0',
s_axi_wdata(45) => '0',
s_axi_wdata(44) => '0',
s_axi_wdata(43) => '0',
s_axi_wdata(42) => '0',
s_axi_wdata(41) => '0',
s_axi_wdata(40) => '0',
s_axi_wdata(39) => '0',
s_axi_wdata(38) => '0',
s_axi_wdata(37) => '0',
s_axi_wdata(36) => '0',
s_axi_wdata(35) => '0',
s_axi_wdata(34) => '0',
s_axi_wdata(33) => '0',
s_axi_wdata(32) => '0',
s_axi_wdata(31) => '0',
s_axi_wdata(30) => '0',
s_axi_wdata(29) => '0',
s_axi_wdata(28) => '0',
s_axi_wdata(27) => '0',
s_axi_wdata(26) => '0',
s_axi_wdata(25) => '0',
s_axi_wdata(24) => '0',
s_axi_wdata(23) => '0',
s_axi_wdata(22) => '0',
s_axi_wdata(21) => '0',
s_axi_wdata(20) => '0',
s_axi_wdata(19) => '0',
s_axi_wdata(18) => '0',
s_axi_wdata(17) => '0',
s_axi_wdata(16) => '0',
s_axi_wdata(15) => '0',
s_axi_wdata(14) => '0',
s_axi_wdata(13) => '0',
s_axi_wdata(12) => '0',
s_axi_wdata(11) => '0',
s_axi_wdata(10) => '0',
s_axi_wdata(9) => '0',
s_axi_wdata(8) => '0',
s_axi_wdata(7) => '0',
s_axi_wdata(6) => '0',
s_axi_wdata(5) => '0',
s_axi_wdata(4) => '0',
s_axi_wdata(3) => '0',
s_axi_wdata(2) => '0',
s_axi_wdata(1) => '0',
s_axi_wdata(0) => '0',
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
sleep => '0',
wea(0) => '0',
web(0) => '0'
);
end STRUCTURE;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:dist_mem_gen:8.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY dist_mem_gen_v8_0;
USE dist_mem_gen_v8_0.dist_mem_gen_v8_0;
ENTITY Mem IS
PORT (
a : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END Mem;
ARCHITECTURE Mem_arch OF Mem IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF Mem_arch: ARCHITECTURE IS "yes";
COMPONENT dist_mem_gen_v8_0 IS
GENERIC (
C_FAMILY : STRING;
C_ADDR_WIDTH : INTEGER;
C_DEFAULT_DATA : STRING;
C_DEPTH : INTEGER;
C_HAS_CLK : INTEGER;
C_HAS_D : INTEGER;
C_HAS_DPO : INTEGER;
C_HAS_DPRA : INTEGER;
C_HAS_I_CE : INTEGER;
C_HAS_QDPO : INTEGER;
C_HAS_QDPO_CE : INTEGER;
C_HAS_QDPO_CLK : INTEGER;
C_HAS_QDPO_RST : INTEGER;
C_HAS_QDPO_SRST : INTEGER;
C_HAS_QSPO : INTEGER;
C_HAS_QSPO_CE : INTEGER;
C_HAS_QSPO_RST : INTEGER;
C_HAS_QSPO_SRST : INTEGER;
C_HAS_SPO : INTEGER;
C_HAS_WE : INTEGER;
C_MEM_INIT_FILE : STRING;
C_ELABORATION_DIR : STRING;
C_MEM_TYPE : INTEGER;
C_PIPELINE_STAGES : INTEGER;
C_QCE_JOINED : INTEGER;
C_QUALIFY_WE : INTEGER;
C_READ_MIF : INTEGER;
C_REG_A_D_INPUTS : INTEGER;
C_REG_DPRA_INPUT : INTEGER;
C_SYNC_ENABLE : INTEGER;
C_WIDTH : INTEGER;
C_PARSER_TYPE : INTEGER
);
PORT (
a : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
d : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
dpra : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
clk : IN STD_LOGIC;
we : IN STD_LOGIC;
i_ce : IN STD_LOGIC;
qspo_ce : IN STD_LOGIC;
qdpo_ce : IN STD_LOGIC;
qdpo_clk : IN STD_LOGIC;
qspo_rst : IN STD_LOGIC;
qdpo_rst : IN STD_LOGIC;
qspo_srst : IN STD_LOGIC;
qdpo_srst : IN STD_LOGIC;
spo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
dpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
qspo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
qdpo : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END COMPONENT dist_mem_gen_v8_0;
BEGIN
U0 : dist_mem_gen_v8_0
GENERIC MAP (
C_FAMILY => "artix7",
C_ADDR_WIDTH => 9,
C_DEFAULT_DATA => "0",
C_DEPTH => 512,
C_HAS_CLK => 1,
C_HAS_D => 1,
C_HAS_DPO => 1,
C_HAS_DPRA => 1,
C_HAS_I_CE => 0,
C_HAS_QDPO => 0,
C_HAS_QDPO_CE => 0,
C_HAS_QDPO_CLK => 0,
C_HAS_QDPO_RST => 0,
C_HAS_QDPO_SRST => 0,
C_HAS_QSPO => 0,
C_HAS_QSPO_CE => 0,
C_HAS_QSPO_RST => 0,
C_HAS_QSPO_SRST => 0,
C_HAS_SPO => 1,
C_HAS_WE => 1,
C_MEM_INIT_FILE => "Mem.mif",
C_ELABORATION_DIR => "./",
C_MEM_TYPE => 2,
C_PIPELINE_STAGES => 0,
C_QCE_JOINED => 0,
C_QUALIFY_WE => 0,
C_READ_MIF => 1,
C_REG_A_D_INPUTS => 0,
C_REG_DPRA_INPUT => 0,
C_SYNC_ENABLE => 1,
C_WIDTH => 5,
C_PARSER_TYPE => 1
)
PORT MAP (
a => a,
d => d,
dpra => dpra,
clk => clk,
we => we,
i_ce => '1',
qspo_ce => '1',
qdpo_ce => '1',
qdpo_clk => '0',
qspo_rst => '0',
qdpo_rst => '0',
qspo_srst => '0',
qdpo_srst => '0',
spo => spo,
dpo => dpo
);
END Mem_arch;
|
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
|
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
|
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
|
-- mux_onehot_f - arch and entity
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: mux_onehot_f.vhd
--
-- Description: Parameterizable multiplexer with one hot select lines.
--
-- Please refer to the entity interface while reading the
-- remainder of this description.
--
-- If n is the index of the single select line of S(0 to C_NB-1)
-- that is asserted, then
--
-- Y(0 to C_DW-1) <= D(n*C_DW to n*C_DW + C_DW -1)
--
-- That is, Y selects the nth group of C_DW consecutive
-- bits of D.
--
-- Note that C_NB = 1 is handled as a special case in which
-- Y <= D, without regard to the select line, S.
--
-- The Implementation depends on the C_FAMILY parameter.
-- If the target family supports the needed primitives,
-- a carry-chain structure will be implemented. Otherwise,
-- an implementation dependent on synthesis inferral will
-- be generated.
--
-------------------------------------------------------------------------------
-- Structure:
-- mux_onehot_f
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 11/30/05 -- First version derived from mux_onehot.vhd
-- -- by BLT and ALS.
--
-- ~~~~~~
--
-- DET 1/17/2008 v4_0
-- ~~~~~~
-- - Incorporated new disclaimer header
-- ^^^^^^
--
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-------------------------------------------------------------------------------
-- Generic and Port Declaration
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Definition of Generics and Ports
--
-- C_DW: Data width of buses entering the mux. Valid range is 1 to 256.
-- C_NB: Number of data buses entering the mux. Valid range is 1 to 64.
--
-- input D -- input data bus
-- input S -- input select bus
-- output Y -- output bus
--
-- The input data is represented by a one-dimensional bus that is made up
-- of all of the data buses concatenated together. For example, a 4 to 1
-- mux with 2 bit data buses (C_DW=2,C_NB=4) is represented by:
--
-- D = (Bus0Data0, Bus0Data1, Bus1Data0, Bus1Data1, Bus2Data0, Bus2Data1,
-- Bus3Data0, Bus3Data1)
--
-- Y = (Bus0Data0, Bus0Data1) if S(0)=1 else
-- (Bus1Data0, Bus1Data1) if S(1)=1 else
-- (Bus2Data0, Bus2Data1) if S(2)=1 else
-- (Bus3Data0, Bus3Data1) if S(3)=1
--
-- Only one bit of S should be asserted at a time.
--
-------------------------------------------------------------------------------
entity mux_onehot_f is
generic( C_DW: integer := 32;
C_NB: integer := 5;
C_FAMILY : string := "virtexe");
port(
D: in std_logic_vector(0 to C_DW*C_NB-1);
S: in std_logic_vector(0 to C_NB-1);
Y: out std_logic_vector(0 to C_DW-1));
end mux_onehot_f;
library unisim;
use unisim.all; -- Make unisim entities available for default binding.
architecture imp of mux_onehot_f is
constant NLS : natural := 6;--native_lut_size(fam_as_string => C_FAMILY,
-- no_lut_return_val => 2*C_NB);
function lut_val(D, S : std_logic_vector) return std_logic is
variable rn : std_logic := '0';
begin
for i in D'range loop
rn := rn or (S(i) and D(i));
end loop;
return not rn;
end;
function min(i, j : integer) return integer is
begin
if i < j then return i; else return j; end if;
end;
-----------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal Dreord: std_logic_vector(0 to C_DW*C_NB-1);
signal sel: std_logic_vector(0 to C_DW*C_NB-1);
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
component MUXCY
port
(
O : out std_ulogic;
CI : in std_ulogic;
DI : in std_ulogic;
S : in std_ulogic
);
end component;
begin
-- Reorder data buses
WA_GEN : if C_DW > 0 generate -- XST WA
REORD: process( D )
variable m,n: integer;
begin
for m in 0 to C_DW-1 loop
for n in 0 to C_NB-1 loop
Dreord( m*C_NB+n) <= D( n*C_DW+m );
end loop;
end loop;
end process REORD;
end generate;
-------------------------------------------------------------------------------
-- REPSELS_PROCESS
-------------------------------------------------------------------------------
-- The one-hot select bus contains 1-bit for each bus. To more easily
-- parameterize the carry chains and reduce loading on the select bus, these
-- signals are replicated into a bus that replicates the select bits for the
-- data width of the busses
-------------------------------------------------------------------------------
REPSELS_PROCESS : process ( S )
variable i, j : integer;
begin
-- loop through all data bits and busses
for i in 0 to C_DW-1 loop
for j in 0 to C_NB-1 loop
sel(i*C_NB+j) <= S(j);
end loop;
end loop;
end process REPSELS_PROCESS;
GEN: if C_NB > 1 generate
constant BPL : positive := NLS / 2; -- Buses per LUT is the native lut
-- size divided by two.signals per bus.
constant NUMLUTS : positive := (C_NB+(BPL-1))/BPL;
begin
DATA_WIDTH_GEN: for i in 0 to C_DW-1 generate
signal cyout : std_logic_vector(0 to NUMLUTS);
signal lutout : std_logic_vector(0 to NUMLUTS-1);
begin
cyout(0) <= '0';
NUM_BUSES_GEN: for j in 0 to NUMLUTS - 1 generate
constant BTL : positive := min(BPL, C_NB - j*BPL);
-- Number of Buses This Lut (for last LUT this may be less than BPL)
begin
lutout(j) <= lut_val(D => Dreord(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1),
S => sel(i*C_NB+j*BPL to i*C_NB+j*BPL+BTL-1)
);
MUXCY_GEN : if NUMLUTS > 1 generate
MUXCY_I : component MUXCY
port map (CI=>cyout(j),
DI=> '1',
S=>lutout(j),
O=>cyout(j+1));
end generate;
end generate;
Y(i) <= cyout(NUMLUTS) when NUMLUTS > 1 else not lutout(0); -- If just one
-- LUT, then take value from
-- lutout rather than cyout.
end generate;
end generate;
ONE_GEN: if C_NB = 1 generate
Y <= D;
end generate;
end imp;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library std;
use std.textio.all;
library work;
use work.all;
entity tb_uart is
end tb_uart;
architecture behav of tb_uart is
signal rst_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal Din_i : std_logic_vector(7 downto 0) := X"AA";
signal rx_i : std_logic := '0';
signal tx_o : std_logic := '0';
signal ld_i : std_logic := '0';
begin
process
begin
clk_i <= '1', '0' after 166 ns;
wait for 333 ns;
end process;
process
begin
wait for 1*333 ns;
rst_i <= '1';
wait for 3*333 ns;
rst_i <= '0';
wait for 1*333 ns;
Din_i <= X"55";
wait for 4 ms;
Din_i <= X"CD";
wait for 4 ms;
assert false report "done" severity failure;
wait;
end process;
rx_i <= tx_o; --loop back
uart_i: entity work.uart_top_shell
port map(
rst_i => rst_i,
clk_i => clk_i,
Din_i => Din_i,
rx_i => rx_i,
tx_o => tx_o,
ld_i => ld_i
);
end behav;
|
-- GENERADOR DE SENIALES
-- Librerias necesarias
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Definimos la entidad
ENTITY Generador_seniales IS
PORT (
-- Entradas de las distintas opciones seleccionables y el reloj
reloj : IN STD_LOGIC;
formaOnda : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- Tomara valor 00 para senoidal, 01 para triangular y 10 para dientes de sierra
amplitud : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- Tomara valor 00 para 5 V, 01 para 2.5 V y 10 para 1.25
frecuencia : IN STD_LOGIC_VECTOR (1 DOWNTO 0);-- Tomara valor 00 para 100 Hz, 01 para 200 y 10 para 500
-- Convertidor D/A
AB : OUT STD_LOGIC; -- Seleccion de canal
D : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); -- Palabra digital
CS : OUT STD_LOGIC; -- Activo en bajo
WR : OUT STD_LOGIC; -- Activo en bajo, escritura de palabra digital
CLR : OUT STD_LOGIC; -- Pone a 0 la palabra digital de ambos convertidores D/A, y la salida de ambos se pone a 0
LDAC : OUT STD_LOGIC -- Con un flanco descendente ambos convertidores toman el valor de los registros
);
END Generador_seniales;
-- Definimos la arquitectura
ARCHITECTURE arquitectura_Generador_seniales OF Generador_seniales IS
SIGNAL valorFormaOnda : INTEGER RANGE 0 TO 255; -- Posicion en la amplitud (tenemos 8 bits)
SIGNAL valorFormaOndaSeno : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Utilizado para obtener de la memoria el vector con el valor de la amplitud del seno
SIGNAL frecuenciaMuestreo : STD_LOGIC; -- Simula los pulsos de reloj segun la frecuencia seleccionada
SIGNAL valorAmplitud : STD_LOGIC_VECTOR (7 DOWNTO 0); -- Para el valor de la amplitud
SIGNAL posicionMemoria : INTEGER RANGE 0 TO 255 :=0; -- Para la posicion de memoria en el seno
SIGNAL posicionMemoriaVector : STD_lOGIC_VECTOR (7 DOWNTO 0); -- Conversion a vector de la posicion de memoria para la ROM instanciada
-- Instanciamos la memoria del seno
COMPONENT ROM_Seno
PORT(
address : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
inclock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
END COMPONENT;
BEGIN
-- Mapeo de la memoria del seno
Memoria_Seno : ROM_Seno
PORT MAP (posicionMemoriaVector, -- Direccion de la memoria <= Address
frecuenciaMuestreo, -- Sincronizacion de acceso <= Inclock
valorFormaOndaSeno); -- Salida de la memoria <= q
-- Ponemos LDAC a 0 permanente y CLR a 1 permanente
LDAC <= '0';
CLR <= '1';
-- Seleccionamos el DAC
AB <= '0';
-- Sincronizamos CS y WR con nuestra frecuencia de muestreo
CS <= frecuenciaMuestreo;
WR <= frecuenciaMuestreo;
-- Escritura de la palabra digital
D <= valorAmplitud;
-- Proceso utilizado para obtener la posicion de la amplitud (valores desde 0 a 255), a los cuales ya le asignaremos
-- posteriormente en valor en voltios segun la amplitud seleccionada, en funcion de la forma de onda seleccionada
seleccionFormaOnda : PROCESS (formaOnda, frecuenciaMuestreo)
VARIABLE subida : STD_LOGIC := '1'; -- Para marcar la subida y bajada en las seniales
VARIABLE i : INTEGER RANGE 0 TO 255 := 0; -- Para ir contando los 255 valores de amplitud (8 bits)
BEGIN
IF frecuenciaMuestreo'EVENT AND frecuenciaMuestreo = '1' THEN
IF formaOnda = "00" THEN -- Si hemos seleccionado seno
posicionMemoria <= posicionMemoria + 1; -- Aumentamos en 1 la posicion de la memoria a leer y la pasamos a vector
posicionMemoriaVector <= conv_std_logic_vector(posicionMemoria,8);
valorFormaOnda <= conv_integer(valorFormaOndaSeno); -- Guardamos el valor obtenido de la memoria convertido a entero
END IF;
IF formaOnda = "01" THEN -- Si hemos seleccionado triangular
IF subida = '1' THEN -- Si subida esta activado
IF i >= 255 THEN -- Si hemos llegado a la maxima amplitud
subida := '0'; -- Activamos el descenso
ELSE
i := i + 1; -- En caso contrario, continuamos ascendiendo en amplitud
END IF;
ELSE -- Si bajada esta activado
IF i <= 0 THEN -- Si hemos llegado a la minima amplitud
subida := '1'; -- Activamos el ascenso
ELSE
i := i - 1; -- En caso contrario, continuamos descendiendo en amplitud
END IF;
END IF;
valorFormaOnda <= i; -- Almacenamos el valor
END IF;
IF formaOnda = "10" THEN -- Si hemos seleccionado triangular
IF i = 255 THEN -- Si hemos llegado a la maxima amplitud
i := 0; -- Bajamos al primer valor
ELSE
i := i + 1; -- En caso contrario continuamos ascendiendo
END IF;
valorFormaOnda <= i; -- Almacenamos el valor
END IF;
END IF;
END PROCESS;
-- Proceso para obtener la amplitud segun el valor de la senial de seleccion de amplitud y el valor de la muestra en la forma de onda
seleccionAmplitud : PROCESS (amplitud, valorFormaOnda)
VARIABLE valor : STD_LOGIC_VECTOR (7 DOWNTO 0);
BEGIN
valor := conv_std_logic_vector (valorFormaOnda,8); -- Nuestro valor almacenado de la posicion de amplitud lo pasamos a vector
IF amplitud = "00" THEN -- Amplitud de 5 V
valorAmplitud <= valor (7 DOWNTO 0);
END IF;
IF amplitud = "01" THEN -- Amplitud de 2.5 V
valorAmplitud <= '0'&valor (7 DOWNTO 1);
END IF;
IF amplitud = "10" THEN -- Amplitud de 1.25 V
valorAmplitud <= "00"&valor (7 DOWNTO 2);
END IF;
END PROCESS;
-- Proceso para obtener la frecuencia segun el valor de la senial de seleccion de frecuencia de salida
seleccionFrecuencia : PROCESS (frecuencia)
VARIABLE maximoPulsos : INTEGER RANGE 0 TO 300000;
VARIABLE pulsos : INTEGER RANGE 0 TO 300000 := 0;
BEGIN
-- Seleccionamos el numero de pulsos necesario en nuestro reloj interno para que se produzca uno
-- en nuestra frecuencia de salida seleccionada
IF frecuencia = "00" THEN -- Frecuencia de 100 Hz
maximoPulsos := 492;
END IF;
IF frecuencia = "01" THEN -- Frecuencia de 200 Hz
maximoPulsos := 246;
END IF;
IF frecuencia = "10" THEN -- Frecuencia de 500 Hz
maximoPulsos := 98;
END IF;
-- Obtenemos la frecuencia de muestreo
IF reloj'EVENT AND reloj = '1' THEN
IF pulsos = maximoPulsos THEN
frecuenciaMuestreo <= NOT frecuenciaMuestreo;
pulsos := 0;
ELSE
pulsos := pulsos + 1;
END IF;
END IF;
END PROCESS;
END arquitectura_Generador_seniales; |
library IEEE;
use IEEE.Std_Logic_1164.all;
entity DecodeHEX is
port (I: in std_logic_vector(3 downto 0);
O: out std_logic_vector(6 downto 0)
);
end DecodeHEX;
architecture DEC_estr of DecodeHEX is
begin
O <= "1000000" when I = "0000" else
"1111001" when I = "0001" else
"0100100" when I = "0010" else
"0110000" when I = "0011" else
"0011001" when I = "0100" else
"0010010" when I = "0101" else
"0000010" when I = "0110" else
"1111000" when I = "0111" else
"0000000" when I = "1000" else
"0011000" when I = "1001" else
"0001000" when I = "1010" else
"0000011" when I = "1011" else
"1000110" when I = "1100" else
"0100001" when I = "1101" else
"0000110" when I = "1110" else
"0001110";
end DEC_estr; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc228.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00228ent IS
END c03s01b01x00p07n01i00228ent;
ARCHITECTURE c03s01b01x00p07n01i00228arch OF c03s01b01x00p07n01i00228ent IS
type MVL is ('0', '1', 'Z') ;
type MVL1 is ('0', '1', 'Z', 'X') ;
signal S1 : MVL ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 10 ns,
'0' after 20 ns,
'Z' after 50 ns;
wait for 60 ns;
assert NOT( S1 = 'Z' )
report "***PASSED TEST: c03s01b01x00p07n01i00228"
severity NOTE;
assert ( S1 = 'Z' )
report "***FAILED TEST: c03s01b01x00p07n01i00228 - The type of an overloaded enumeration literal is determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00228arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc228.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00228ent IS
END c03s01b01x00p07n01i00228ent;
ARCHITECTURE c03s01b01x00p07n01i00228arch OF c03s01b01x00p07n01i00228ent IS
type MVL is ('0', '1', 'Z') ;
type MVL1 is ('0', '1', 'Z', 'X') ;
signal S1 : MVL ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 10 ns,
'0' after 20 ns,
'Z' after 50 ns;
wait for 60 ns;
assert NOT( S1 = 'Z' )
report "***PASSED TEST: c03s01b01x00p07n01i00228"
severity NOTE;
assert ( S1 = 'Z' )
report "***FAILED TEST: c03s01b01x00p07n01i00228 - The type of an overloaded enumeration literal is determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00228arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc228.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b01x00p07n01i00228ent IS
END c03s01b01x00p07n01i00228ent;
ARCHITECTURE c03s01b01x00p07n01i00228arch OF c03s01b01x00p07n01i00228ent IS
type MVL is ('0', '1', 'Z') ;
type MVL1 is ('0', '1', 'Z', 'X') ;
signal S1 : MVL ;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 10 ns,
'0' after 20 ns,
'Z' after 50 ns;
wait for 60 ns;
assert NOT( S1 = 'Z' )
report "***PASSED TEST: c03s01b01x00p07n01i00228"
severity NOTE;
assert ( S1 = 'Z' )
report "***FAILED TEST: c03s01b01x00p07n01i00228 - The type of an overloaded enumeration literal is determinable from the context."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b01x00p07n01i00228arch;
|
entity issue315 is
generic (
DATA_BITS : integer := 32
);
end entity;
architecture test of issue315 is
type INFO_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
BITS : integer;
end record;
function SET_INFO return INFO_TYPE is
variable info : INFO_TYPE;
variable index : integer;
begin
index := 0;
info.DATA_LO := index;
info.DATA_HI := index + DATA_BITS - 1;
index := index + DATA_BITS;
info.BITS := index;
return info;
end function;
constant INFO : INFO_TYPE := SET_INFO;
signal i_info : bit_vector(INFO.BITS-1 downto 0);
signal o_info : bit_vector(INFO.BITS-1 downto 0);
begin
end architecture;
|
entity issue315 is
generic (
DATA_BITS : integer := 32
);
end entity;
architecture test of issue315 is
type INFO_TYPE is record
DATA_LO : integer;
DATA_HI : integer;
BITS : integer;
end record;
function SET_INFO return INFO_TYPE is
variable info : INFO_TYPE;
variable index : integer;
begin
index := 0;
info.DATA_LO := index;
info.DATA_HI := index + DATA_BITS - 1;
index := index + DATA_BITS;
info.BITS := index;
return info;
end function;
constant INFO : INFO_TYPE := SET_INFO;
signal i_info : bit_vector(INFO.BITS-1 downto 0);
signal o_info : bit_vector(INFO.BITS-1 downto 0);
begin
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien3 is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien3;
architecture generator of alien3 is
type states is (act, wait_clk);
signal state, state_next: states;
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 0;
constant FRAME_DELAY: integer := 100000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_x_next,
origin_y, origin_y_next: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
-- second level aliens need two hits to get killed
signal injured1, injured1_next,
injured2, injured2_next: std_logic_vector(0 to 7);
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(26 downto 0);
signal alien_rgb, alien31_rgb, alien32_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
injured1 <= (others => '0');
injured2 <= (others => '0');
state <= act;
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
injured1 <= injured1_next;
injured2 <= injured2_next;
state <= state_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, position_in_frame,
alive, injured1, injured2, state, frame, restart)
begin
state_next <= state;
destruction <= '0';
alive_next <= alive;
injured1_next <= injured1;
injured2_next <= injured2;
case state is
when act =>
if restart = '1' then
alive_next <= (others => '1');
injured1_next <= (others => '0');
injured2_next <= (others => '0');
elsif missile_arrived = '1' and
frame = '0' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
if injured2(conv_integer(attacked_alien)) = '0' then
if injured1(conv_integer(attacked_alien)) = '0' then
state_next <= wait_clk;
destruction <= '1';
injured1_next(conv_integer(attacked_alien)) <= '1';
else
state_next <= wait_clk;
destruction <= '1';
injured2_next(conv_integer(attacked_alien)) <= '1';
end if;
else
state_next <= wait_clk;
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end if;
when wait_clk =>
state_next <= act;
end case;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien31_rgb when frame = '0' else
alien32_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_31:
entity work.alien31_rom(content)
port map(addr => addr, data => alien31_rgb);
alien_32:
entity work.alien32_rom(content)
port map(addr => addr, data => alien32_rgb);
end generator; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alien3 is
port(
clk, not_reset: in std_logic;
px_x, px_y: in std_logic_vector(9 downto 0);
master_coord_x, master_coord_y: in std_logic_vector(9 downto 0);
missile_coord_x, missile_coord_y: in std_logic_vector(9 downto 0);
restart: in std_logic;
destroyed: out std_logic;
defeated: out std_logic;
explosion_x, explosion_y: out std_logic_vector(9 downto 0);
rgb_pixel: out std_logic_vector(0 to 2)
);
end alien3;
architecture generator of alien3 is
type states is (act, wait_clk);
signal state, state_next: states;
-- width of the alien area (8 * 32)
constant A_WIDTH: integer := 256;
constant A_HEIGHT: integer := 32;
-- 3rd level aliens are at the bottom (64px below master coord)
constant OFFSET: integer := 0;
constant FRAME_DELAY: integer := 100000000;
signal output_enable: std_logic;
-- address is made of row and column adresses
-- addr <= (row_address & col_address);
signal addr: std_logic_vector(9 downto 0);
signal row_address, col_address: std_logic_vector(4 downto 0);
signal origin_x, origin_x_next,
origin_y, origin_y_next: std_logic_vector(9 downto 0);
signal relative_x: std_logic_vector(9 downto 0);
signal missile_relative_x: std_logic_vector(9 downto 0);
signal position_in_frame: std_logic_vector(4 downto 0);
-- whether missile is in alien zone
signal missile_arrived: std_logic;
signal attacked_alien: std_logic_vector(2 downto 0);
signal destruction: std_logic;
-- condition of aliens: left (0) to right (7)
signal alive, alive_next: std_logic_vector(0 to 7);
signal alien_alive: std_logic;
-- second level aliens need two hits to get killed
signal injured1, injured1_next,
injured2, injured2_next: std_logic_vector(0 to 7);
signal frame, frame_next: std_logic;
signal frame_counter, frame_counter_next: std_logic_vector(26 downto 0);
signal alien_rgb, alien31_rgb, alien32_rgb: std_logic_vector(2 downto 0);
-- which alien is currently being drawn
-- leftmost = 0, rightmost = 7
signal alien_number: std_logic_vector(2 downto 0);
begin
process(clk, not_reset)
begin
if not_reset = '0' then
frame <= '0';
frame_counter <= (others => '0');
alive <= (others => '1');
injured1 <= (others => '0');
injured2 <= (others => '0');
state <= act;
elsif falling_edge(clk) then
frame <= frame_next;
frame_counter <= frame_counter_next;
alive <= alive_next;
injured1 <= injured1_next;
injured2 <= injured2_next;
state <= state_next;
end if;
end process;
missile_arrived <= '1' when missile_coord_y < master_coord_y + OFFSET + A_HEIGHT and
missile_coord_x > master_coord_x and
missile_coord_x < master_coord_x + A_WIDTH else
'0';
missile_relative_x <= (missile_coord_x - master_coord_x) when missile_arrived = '1' else
(others => '0');
attacked_alien <= missile_relative_x(7 downto 5) when missile_arrived = '1' else
(others => '0');
position_in_frame <= missile_relative_x(4 downto 0) when missile_arrived = '1' else
(others => '0');
process(missile_coord_x, master_coord_x,
missile_arrived, position_in_frame,
alive, injured1, injured2, state, frame, restart)
begin
state_next <= state;
destruction <= '0';
alive_next <= alive;
injured1_next <= injured1;
injured2_next <= injured2;
case state is
when act =>
if restart = '1' then
alive_next <= (others => '1');
injured1_next <= (others => '0');
injured2_next <= (others => '0');
elsif missile_arrived = '1' and
frame = '0' and
alive(conv_integer(attacked_alien)) = '1' and
position_in_frame > 0 and
position_in_frame < 29
then
if injured2(conv_integer(attacked_alien)) = '0' then
if injured1(conv_integer(attacked_alien)) = '0' then
state_next <= wait_clk;
destruction <= '1';
injured1_next(conv_integer(attacked_alien)) <= '1';
else
state_next <= wait_clk;
destruction <= '1';
injured2_next(conv_integer(attacked_alien)) <= '1';
end if;
else
state_next <= wait_clk;
destruction <= '1';
alive_next(conv_integer(attacked_alien)) <= '0';
end if;
end if;
when wait_clk =>
state_next <= act;
end case;
end process;
relative_x <= px_x - master_coord_x;
alien_number <= relative_x(7 downto 5);
alien_alive <= alive(conv_integer(alien_number));
frame_counter_next <= frame_counter + 1 when frame_counter < FRAME_DELAY else
(others => '0');
frame_next <= (not frame) when frame_counter = 0 else frame;
output_enable <= '1' when (alien_alive = '1' and
px_x >= master_coord_x and
px_x < master_coord_x + A_WIDTH and
px_y >= master_coord_y + OFFSET and
px_y < master_coord_y + OFFSET + A_HEIGHT) else
'0';
row_address <= px_y(4 downto 0) - master_coord_y(4 downto 0);
col_address <= px_x(4 downto 0) - master_coord_x(4 downto 0);
addr <= row_address & col_address;
alien_rgb <= alien31_rgb when frame = '0' else
alien32_rgb;
rgb_pixel <= alien_rgb when output_enable = '1' else
(others => '0');
destroyed <= destruction;
-- attacked alien number is multiplied by 32
origin_x <= master_coord_x + (attacked_alien & "00000");
origin_y <= master_coord_y + OFFSET;
explosion_x <= origin_x;
explosion_y <= origin_y;
defeated <= '1' when alive = 0 else '0';
alien_31:
entity work.alien31_rom(content)
port map(addr => addr, data => alien31_rgb);
alien_32:
entity work.alien32_rom(content)
port map(addr => addr, data => alien32_rgb);
end generator; |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pif_pkg is
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_RX_DATA : integer := 0;
constant C_ADDR_RX_DATA_VALID : integer := 1;
constant C_ADDR_TX_DATA : integer := 2;
constant C_ADDR_TX_READY : integer := 3;
-- Signals from pif to core
type t_p2c is record
awo_tx_data : std_logic_vector(7 downto 0);
awo_tx_data_we : std_logic;
aro_rx_data_re : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_rx_data : std_logic_vector(7 downto 0);
aro_rx_data_valid : std_logic;
aro_tx_ready : std_logic;
end record t_c2p;
end package uart_pif_pkg;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pif_pkg is
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_RX_DATA : integer := 0;
constant C_ADDR_RX_DATA_VALID : integer := 1;
constant C_ADDR_TX_DATA : integer := 2;
constant C_ADDR_TX_READY : integer := 3;
-- Signals from pif to core
type t_p2c is record
awo_tx_data : std_logic_vector(7 downto 0);
awo_tx_data_we : std_logic;
aro_rx_data_re : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_rx_data : std_logic_vector(7 downto 0);
aro_rx_data_valid : std_logic;
aro_tx_ready : std_logic;
end record t_c2p;
end package uart_pif_pkg;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package uart_pif_pkg is
-- Notation for regs: (Included in constant name as info to SW)
-- - RW: Readable and writable reg.
-- - RO: Read only reg. (output from IP)
-- - WO: Write only reg. (typically single cycle strobe to IP)
-- Notation for signals (or fields in record) going between PIF and core:
-- Same notations as for register-constants above, but
-- a preceeding 'a' (e.g. awo) means the register is auxiliary to the PIF.
-- This means no flop in the PIF, but in the core. (Or just a dummy-register with no flop)
constant C_ADDR_RX_DATA : integer := 0;
constant C_ADDR_RX_DATA_VALID : integer := 1;
constant C_ADDR_TX_DATA : integer := 2;
constant C_ADDR_TX_READY : integer := 3;
-- Signals from pif to core
type t_p2c is record
awo_tx_data : std_logic_vector(7 downto 0);
awo_tx_data_we : std_logic;
aro_rx_data_re : std_logic;
end record t_p2c;
-- Signals from core to PIF
type t_c2p is record
aro_rx_data : std_logic_vector(7 downto 0);
aro_rx_data_valid : std_logic;
aro_tx_ready : std_logic;
end record t_c2p;
end package uart_pif_pkg;
|
library verilog;
use verilog.vl_types.all;
entity \IF\ is
port(
clk : in vl_logic;
PCSrc : in vl_logic_vector(1 downto 0);
PC0 : in vl_logic_vector(31 downto 0);
PC1 : in vl_logic_vector(31 downto 0);
PC2 : in vl_logic_vector(31 downto 0);
PC3 : in vl_logic_vector(31 downto 0);
PC_IF_ID_in : out vl_logic_vector(31 downto 0);
IR_out : out vl_logic_vector(31 downto 0)
);
end \IF\;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library BananaCore;
use BananaCore.Instruction.DecodedInstruction;
use BananaCore.InstructionDecoder;
use BananaCore.Instruction.all;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
use BananaCore.LoadInstructionExecutor;
use BananaCore.StoreInstructionExecutor;
use BananaCore.WriteIoInstructionExecutor;
use BananaCore.ReadIoInstructionExecutor;
use BananaCore.AddInstructionExecutor;
use BananaCore.SubtractInstructionExecutor;
use BananaCore.MultiplyInstructionExecutor;
use BananaCore.DivideInstructionExecutor;
use BananaCore.BitwiseAndInstructionExecutor;
use BananaCore.BitwiseOrInstructionExecutor;
use BananaCore.BitwiseNandInstructionExecutor;
use BananaCore.BitwiseNorInstructionExecutor;
use BananaCore.BitwiseXorInstructionExecutor;
use BananaCore.BitwiseNotInstructionExecutor;
use BananaCore.GreaterThanInstructionExecutor;
use BananaCore.GreaterOrEqualThanInstructionExecutor;
use BananaCore.LessThanInstructionExecutor;
use BananaCore.LessOrEqualThanInstructionExecutor;
use BananaCore.EqualInstructionExecutor;
use BananaCore.NotEqualInstructionExecutor;
use BananaCore.JumpInstructionExecutor;
use BananaCore.JumpIfCarryInstructionExecutor;
use BananaCore.HaltInstructionExecutor;
use BananaCore.ResetInstructionExecutor;
-- Decodes a instruction bit stream into a organized and easy to use instruction record
entity InstructionController is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress;
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData;
-- the operation to perform on the memory
memory_operation: out MemoryOperation;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor memory address bus
register_address: out RegisterAddress;
-- the processor memory data bus
register_data_read: in RegisterData;
-- the processor memory data bus
register_data_write: out RegisterData;
-- the processor memory operation signal
register_operation: out RegisterOperation;
-- the processor memory operation signal
register_enable: out std_logic;
-- a flag indicating if a register operation has completed
register_ready: in std_logic;
------------------------------------------
-- IO PORTS
------------------------------------------
-- io port: port0
port0: in IOPortData;
-- io port: port1
port1: out IOPortData
);
end InstructionController;
architecture InstructionControllerImpl of InstructionController is
signal instruction_data: std_logic_vector(0 to 31);
signal current_instruction: DecodedInstruction;
signal program_counter: MemoryAddress := integer_to_memory_address(0);
type state_type is (
read_memory0,
wait_memory0,
read_memory1,
wait_memory1,
read_memory2,
wait_memory2,
read_memory3,
wait_memory3,
decode_instruction,
-- wait_decode_instruction,
execute,
wait_execute
);
signal state: state_type := read_memory0;
signal instruction_enabler: std_logic_vector(0 to 255);
signal instruction_ready: std_logic_vector(0 to 255);
signal memory_address_local: MemoryAddress;
signal memory_data_write_local: MemoryData;
signal memory_operation_local: MemoryOperation;
signal memory_enable_local: std_logic;
signal memory_ready_local: std_logic;
signal register_address_local: RegisterAddress;
signal register_data_local: RegisterData;
signal register_operation_local: RegisterOperation;
signal register_enable_local: std_logic;
attribute keep: boolean;
attribute keep of instruction_ready: signal is true;
attribute keep of instruction_data: signal is true;
attribute keep of current_instruction: signal is true;
attribute keep of state: signal is true;
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--for line in content:
-- cog.outl("signal memory_address_{0}: MemoryAddress;".format(line.lower()))
-- cog.outl("signal memory_enable_{0}: std_logic;".format(line.lower()))
-- cog.outl("signal memory_data_write_{0}: MemoryData;".format(line.lower()))
-- cog.outl("signal memory_operation_{0}: MemoryOperation;".format(line.lower()))
-- cog.outl("signal register_address_{0}: RegisterAddress;".format(line.lower()))
-- cog.outl("signal register_data_write_{0}: RegisterData;".format(line.lower()))
-- cog.outl("signal register_operation_{0}: RegisterOperation := OP_REG_DISABLED;".format(line.lower()))
-- cog.outl("signal register_enable_{0}: std_logic;".format(line.lower()))
-- cog.outl();
--]]]
signal memory_address_load: MemoryAddress;
signal memory_enable_load: std_logic;
signal memory_data_write_load: MemoryData;
signal memory_operation_load: MemoryOperation;
signal register_address_load: RegisterAddress;
signal register_data_write_load: RegisterData;
signal register_operation_load: RegisterOperation := OP_REG_DISABLED;
signal register_enable_load: std_logic;
signal port1_load: MemoryData;
signal memory_address_store: MemoryAddress;
signal memory_enable_store: std_logic;
signal memory_data_write_store: MemoryData;
signal memory_operation_store: MemoryOperation;
signal register_address_store: RegisterAddress;
signal register_data_write_store: RegisterData;
signal register_operation_store: RegisterOperation := OP_REG_DISABLED;
signal register_enable_store: std_logic;
signal port1_store: MemoryData;
signal memory_address_writeio: MemoryAddress;
signal memory_enable_writeio: std_logic;
signal memory_data_write_writeio: MemoryData;
signal memory_operation_writeio: MemoryOperation;
signal register_address_writeio: RegisterAddress;
signal register_data_write_writeio: RegisterData;
signal register_operation_writeio: RegisterOperation := OP_REG_DISABLED;
signal register_enable_writeio: std_logic;
signal port1_writeio: MemoryData;
signal memory_address_readio: MemoryAddress;
signal memory_enable_readio: std_logic;
signal memory_data_write_readio: MemoryData;
signal memory_operation_readio: MemoryOperation;
signal register_address_readio: RegisterAddress;
signal register_data_write_readio: RegisterData;
signal register_operation_readio: RegisterOperation := OP_REG_DISABLED;
signal register_enable_readio: std_logic;
signal port1_readio: MemoryData;
signal memory_address_add: MemoryAddress;
signal memory_enable_add: std_logic;
signal memory_data_write_add: MemoryData;
signal memory_operation_add: MemoryOperation;
signal register_address_add: RegisterAddress;
signal register_data_write_add: RegisterData;
signal register_operation_add: RegisterOperation := OP_REG_DISABLED;
signal register_enable_add: std_logic;
signal port1_add: MemoryData;
signal memory_address_subtract: MemoryAddress;
signal memory_enable_subtract: std_logic;
signal memory_data_write_subtract: MemoryData;
signal memory_operation_subtract: MemoryOperation;
signal register_address_subtract: RegisterAddress;
signal register_data_write_subtract: RegisterData;
signal register_operation_subtract: RegisterOperation := OP_REG_DISABLED;
signal register_enable_subtract: std_logic;
signal port1_subtract: MemoryData;
signal memory_address_multiply: MemoryAddress;
signal memory_enable_multiply: std_logic;
signal memory_data_write_multiply: MemoryData;
signal memory_operation_multiply: MemoryOperation;
signal register_address_multiply: RegisterAddress;
signal register_data_write_multiply: RegisterData;
signal register_operation_multiply: RegisterOperation := OP_REG_DISABLED;
signal register_enable_multiply: std_logic;
signal port1_multiply: MemoryData;
signal memory_address_divide: MemoryAddress;
signal memory_enable_divide: std_logic;
signal memory_data_write_divide: MemoryData;
signal memory_operation_divide: MemoryOperation;
signal register_address_divide: RegisterAddress;
signal register_data_write_divide: RegisterData;
signal register_operation_divide: RegisterOperation := OP_REG_DISABLED;
signal register_enable_divide: std_logic;
signal port1_divide: MemoryData;
signal memory_address_bitwiseand: MemoryAddress;
signal memory_enable_bitwiseand: std_logic;
signal memory_data_write_bitwiseand: MemoryData;
signal memory_operation_bitwiseand: MemoryOperation;
signal register_address_bitwiseand: RegisterAddress;
signal register_data_write_bitwiseand: RegisterData;
signal register_operation_bitwiseand: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwiseand: std_logic;
signal port1_bitwiseand: MemoryData;
signal memory_address_bitwiseor: MemoryAddress;
signal memory_enable_bitwiseor: std_logic;
signal memory_data_write_bitwiseor: MemoryData;
signal memory_operation_bitwiseor: MemoryOperation;
signal register_address_bitwiseor: RegisterAddress;
signal register_data_write_bitwiseor: RegisterData;
signal register_operation_bitwiseor: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwiseor: std_logic;
signal port1_bitwiseor: MemoryData;
signal memory_address_bitwisenand: MemoryAddress;
signal memory_enable_bitwisenand: std_logic;
signal memory_data_write_bitwisenand: MemoryData;
signal memory_operation_bitwisenand: MemoryOperation;
signal register_address_bitwisenand: RegisterAddress;
signal register_data_write_bitwisenand: RegisterData;
signal register_operation_bitwisenand: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisenand: std_logic;
signal port1_bitwisenand: MemoryData;
signal memory_address_bitwisenor: MemoryAddress;
signal memory_enable_bitwisenor: std_logic;
signal memory_data_write_bitwisenor: MemoryData;
signal memory_operation_bitwisenor: MemoryOperation;
signal register_address_bitwisenor: RegisterAddress;
signal register_data_write_bitwisenor: RegisterData;
signal register_operation_bitwisenor: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisenor: std_logic;
signal port1_bitwisenor: MemoryData;
signal memory_address_bitwisexor: MemoryAddress;
signal memory_enable_bitwisexor: std_logic;
signal memory_data_write_bitwisexor: MemoryData;
signal memory_operation_bitwisexor: MemoryOperation;
signal register_address_bitwisexor: RegisterAddress;
signal register_data_write_bitwisexor: RegisterData;
signal register_operation_bitwisexor: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisexor: std_logic;
signal port1_bitwisexor: MemoryData;
signal memory_address_bitwisenot: MemoryAddress;
signal memory_enable_bitwisenot: std_logic;
signal memory_data_write_bitwisenot: MemoryData;
signal memory_operation_bitwisenot: MemoryOperation;
signal register_address_bitwisenot: RegisterAddress;
signal register_data_write_bitwisenot: RegisterData;
signal register_operation_bitwisenot: RegisterOperation := OP_REG_DISABLED;
signal register_enable_bitwisenot: std_logic;
signal port1_bitwisenot: MemoryData;
signal memory_address_greaterthan: MemoryAddress;
signal memory_enable_greaterthan: std_logic;
signal memory_data_write_greaterthan: MemoryData;
signal memory_operation_greaterthan: MemoryOperation;
signal register_address_greaterthan: RegisterAddress;
signal register_data_write_greaterthan: RegisterData;
signal register_operation_greaterthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_greaterthan: std_logic;
signal port1_greaterthan: MemoryData;
signal memory_address_greaterorequalthan: MemoryAddress;
signal memory_enable_greaterorequalthan: std_logic;
signal memory_data_write_greaterorequalthan: MemoryData;
signal memory_operation_greaterorequalthan: MemoryOperation;
signal register_address_greaterorequalthan: RegisterAddress;
signal register_data_write_greaterorequalthan: RegisterData;
signal register_operation_greaterorequalthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_greaterorequalthan: std_logic;
signal port1_greaterorequalthan: MemoryData;
signal memory_address_lessthan: MemoryAddress;
signal memory_enable_lessthan: std_logic;
signal memory_data_write_lessthan: MemoryData;
signal memory_operation_lessthan: MemoryOperation;
signal register_address_lessthan: RegisterAddress;
signal register_data_write_lessthan: RegisterData;
signal register_operation_lessthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_lessthan: std_logic;
signal port1_lessthan: MemoryData;
signal memory_address_lessorequalthan: MemoryAddress;
signal memory_enable_lessorequalthan: std_logic;
signal memory_data_write_lessorequalthan: MemoryData;
signal memory_operation_lessorequalthan: MemoryOperation;
signal register_address_lessorequalthan: RegisterAddress;
signal register_data_write_lessorequalthan: RegisterData;
signal register_operation_lessorequalthan: RegisterOperation := OP_REG_DISABLED;
signal register_enable_lessorequalthan: std_logic;
signal port1_lessorequalthan: MemoryData;
signal memory_address_equal: MemoryAddress;
signal memory_enable_equal: std_logic;
signal memory_data_write_equal: MemoryData;
signal memory_operation_equal: MemoryOperation;
signal register_address_equal: RegisterAddress;
signal register_data_write_equal: RegisterData;
signal register_operation_equal: RegisterOperation := OP_REG_DISABLED;
signal register_enable_equal: std_logic;
signal port1_equal: MemoryData;
signal memory_address_notequal: MemoryAddress;
signal memory_enable_notequal: std_logic;
signal memory_data_write_notequal: MemoryData;
signal memory_operation_notequal: MemoryOperation;
signal register_address_notequal: RegisterAddress;
signal register_data_write_notequal: RegisterData;
signal register_operation_notequal: RegisterOperation := OP_REG_DISABLED;
signal register_enable_notequal: std_logic;
signal port1_notequal: MemoryData;
signal memory_address_jump: MemoryAddress;
signal memory_enable_jump: std_logic;
signal memory_data_write_jump: MemoryData;
signal memory_operation_jump: MemoryOperation;
signal register_address_jump: RegisterAddress;
signal register_data_write_jump: RegisterData;
signal register_operation_jump: RegisterOperation := OP_REG_DISABLED;
signal register_enable_jump: std_logic;
signal port1_jump: MemoryData;
signal memory_address_jumpifcarry: MemoryAddress;
signal memory_enable_jumpifcarry: std_logic;
signal memory_data_write_jumpifcarry: MemoryData;
signal memory_operation_jumpifcarry: MemoryOperation;
signal register_address_jumpifcarry: RegisterAddress;
signal register_data_write_jumpifcarry: RegisterData;
signal register_operation_jumpifcarry: RegisterOperation := OP_REG_DISABLED;
signal register_enable_jumpifcarry: std_logic;
signal port1_jumpifcarry: MemoryData;
signal memory_address_halt: MemoryAddress;
signal memory_enable_halt: std_logic;
signal memory_data_write_halt: MemoryData;
signal memory_operation_halt: MemoryOperation;
signal register_address_halt: RegisterAddress;
signal register_data_write_halt: RegisterData;
signal register_operation_halt: RegisterOperation := OP_REG_DISABLED;
signal register_enable_halt: std_logic;
signal port1_halt: MemoryData;
signal memory_address_reset: MemoryAddress;
signal memory_enable_reset: std_logic;
signal memory_data_write_reset: MemoryData;
signal memory_operation_reset: MemoryOperation;
signal register_address_reset: RegisterAddress;
signal register_data_write_reset: RegisterData;
signal register_operation_reset: RegisterOperation := OP_REG_DISABLED;
signal register_enable_reset: std_logic;
signal port1_reset: MemoryData;
-- [[[end]]]
signal mux_disabled : std_logic := '1';
signal jump_program_counter : MemoryAddress;
signal jump_program_counter_set : std_logic;
signal jump_if_carry_program_counter : MemoryAddress;
signal jump_if_carry_program_counter_set : std_logic;
begin
-- IMPLEMENTATION NOTE: here, we could very easily (and handly) implement a pipeline.
-- While the instruction is being executed we could already start loading the next memory addresses.
-- Though we have to be sure that no other instruction is accessing the memory bus at the same time.
memory_address <=
memory_address_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_address_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_address_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_address_load when instruction_enabler(0) = '1' else
memory_address_store when instruction_enabler(1) = '1' else
memory_address_writeio when instruction_enabler(2) = '1' else
memory_address_readio when instruction_enabler(3) = '1' else
memory_address_add when instruction_enabler(4) = '1' else
memory_address_subtract when instruction_enabler(5) = '1' else
memory_address_multiply when instruction_enabler(6) = '1' else
memory_address_divide when instruction_enabler(7) = '1' else
memory_address_bitwiseand when instruction_enabler(8) = '1' else
memory_address_bitwiseor when instruction_enabler(9) = '1' else
memory_address_bitwisenand when instruction_enabler(10) = '1' else
memory_address_bitwisenor when instruction_enabler(11) = '1' else
memory_address_bitwisexor when instruction_enabler(12) = '1' else
memory_address_bitwisenot when instruction_enabler(13) = '1' else
memory_address_greaterthan when instruction_enabler(14) = '1' else
memory_address_greaterorequalthan when instruction_enabler(15) = '1' else
memory_address_lessthan when instruction_enabler(16) = '1' else
memory_address_lessorequalthan when instruction_enabler(17) = '1' else
memory_address_equal when instruction_enabler(18) = '1' else
memory_address_notequal when instruction_enabler(19) = '1' else
memory_address_jump when instruction_enabler(20) = '1' else
memory_address_jumpifcarry when instruction_enabler(21) = '1' else
memory_address_halt when instruction_enabler(22) = '1' else
memory_address_reset when instruction_enabler(23) = '1';
-- [[[end]]]
memory_data_write <=
memory_data_write_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_data_write_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_data_write_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_data_write_load when instruction_enabler(0) = '1' else
memory_data_write_store when instruction_enabler(1) = '1' else
memory_data_write_writeio when instruction_enabler(2) = '1' else
memory_data_write_readio when instruction_enabler(3) = '1' else
memory_data_write_add when instruction_enabler(4) = '1' else
memory_data_write_subtract when instruction_enabler(5) = '1' else
memory_data_write_multiply when instruction_enabler(6) = '1' else
memory_data_write_divide when instruction_enabler(7) = '1' else
memory_data_write_bitwiseand when instruction_enabler(8) = '1' else
memory_data_write_bitwiseor when instruction_enabler(9) = '1' else
memory_data_write_bitwisenand when instruction_enabler(10) = '1' else
memory_data_write_bitwisenor when instruction_enabler(11) = '1' else
memory_data_write_bitwisexor when instruction_enabler(12) = '1' else
memory_data_write_bitwisenot when instruction_enabler(13) = '1' else
memory_data_write_greaterthan when instruction_enabler(14) = '1' else
memory_data_write_greaterorequalthan when instruction_enabler(15) = '1' else
memory_data_write_lessthan when instruction_enabler(16) = '1' else
memory_data_write_lessorequalthan when instruction_enabler(17) = '1' else
memory_data_write_equal when instruction_enabler(18) = '1' else
memory_data_write_notequal when instruction_enabler(19) = '1' else
memory_data_write_jump when instruction_enabler(20) = '1' else
memory_data_write_jumpifcarry when instruction_enabler(21) = '1' else
memory_data_write_halt when instruction_enabler(22) = '1' else
memory_data_write_reset when instruction_enabler(23) = '1';
-- [[[end]]]
memory_operation <=
memory_operation_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_operation_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_operation_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_operation_load when instruction_enabler(0) = '1' else
memory_operation_store when instruction_enabler(1) = '1' else
memory_operation_writeio when instruction_enabler(2) = '1' else
memory_operation_readio when instruction_enabler(3) = '1' else
memory_operation_add when instruction_enabler(4) = '1' else
memory_operation_subtract when instruction_enabler(5) = '1' else
memory_operation_multiply when instruction_enabler(6) = '1' else
memory_operation_divide when instruction_enabler(7) = '1' else
memory_operation_bitwiseand when instruction_enabler(8) = '1' else
memory_operation_bitwiseor when instruction_enabler(9) = '1' else
memory_operation_bitwisenand when instruction_enabler(10) = '1' else
memory_operation_bitwisenor when instruction_enabler(11) = '1' else
memory_operation_bitwisexor when instruction_enabler(12) = '1' else
memory_operation_bitwisenot when instruction_enabler(13) = '1' else
memory_operation_greaterthan when instruction_enabler(14) = '1' else
memory_operation_greaterorequalthan when instruction_enabler(15) = '1' else
memory_operation_lessthan when instruction_enabler(16) = '1' else
memory_operation_lessorequalthan when instruction_enabler(17) = '1' else
memory_operation_equal when instruction_enabler(18) = '1' else
memory_operation_notequal when instruction_enabler(19) = '1' else
memory_operation_jump when instruction_enabler(20) = '1' else
memory_operation_jumpifcarry when instruction_enabler(21) = '1' else
memory_operation_halt when instruction_enabler(22) = '1' else
memory_operation_reset when instruction_enabler(23) = '1';
-- [[[end]]]
memory_enable <=
memory_enable_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tmemory_enable_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tmemory_enable_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
memory_enable_load when instruction_enabler(0) = '1' else
memory_enable_store when instruction_enabler(1) = '1' else
memory_enable_writeio when instruction_enabler(2) = '1' else
memory_enable_readio when instruction_enabler(3) = '1' else
memory_enable_add when instruction_enabler(4) = '1' else
memory_enable_subtract when instruction_enabler(5) = '1' else
memory_enable_multiply when instruction_enabler(6) = '1' else
memory_enable_divide when instruction_enabler(7) = '1' else
memory_enable_bitwiseand when instruction_enabler(8) = '1' else
memory_enable_bitwiseor when instruction_enabler(9) = '1' else
memory_enable_bitwisenand when instruction_enabler(10) = '1' else
memory_enable_bitwisenor when instruction_enabler(11) = '1' else
memory_enable_bitwisexor when instruction_enabler(12) = '1' else
memory_enable_bitwisenot when instruction_enabler(13) = '1' else
memory_enable_greaterthan when instruction_enabler(14) = '1' else
memory_enable_greaterorequalthan when instruction_enabler(15) = '1' else
memory_enable_lessthan when instruction_enabler(16) = '1' else
memory_enable_lessorequalthan when instruction_enabler(17) = '1' else
memory_enable_equal when instruction_enabler(18) = '1' else
memory_enable_notequal when instruction_enabler(19) = '1' else
memory_enable_jump when instruction_enabler(20) = '1' else
memory_enable_jumpifcarry when instruction_enabler(21) = '1' else
memory_enable_halt when instruction_enabler(22) = '1' else
memory_enable_reset when instruction_enabler(23) = '1';
-- [[[end]]]
register_data_write <=
register_data_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_data_write_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_data_write_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_data_write_load when instruction_enabler(0) = '1' else
register_data_write_store when instruction_enabler(1) = '1' else
register_data_write_writeio when instruction_enabler(2) = '1' else
register_data_write_readio when instruction_enabler(3) = '1' else
register_data_write_add when instruction_enabler(4) = '1' else
register_data_write_subtract when instruction_enabler(5) = '1' else
register_data_write_multiply when instruction_enabler(6) = '1' else
register_data_write_divide when instruction_enabler(7) = '1' else
register_data_write_bitwiseand when instruction_enabler(8) = '1' else
register_data_write_bitwiseor when instruction_enabler(9) = '1' else
register_data_write_bitwisenand when instruction_enabler(10) = '1' else
register_data_write_bitwisenor when instruction_enabler(11) = '1' else
register_data_write_bitwisexor when instruction_enabler(12) = '1' else
register_data_write_bitwisenot when instruction_enabler(13) = '1' else
register_data_write_greaterthan when instruction_enabler(14) = '1' else
register_data_write_greaterorequalthan when instruction_enabler(15) = '1' else
register_data_write_lessthan when instruction_enabler(16) = '1' else
register_data_write_lessorequalthan when instruction_enabler(17) = '1' else
register_data_write_equal when instruction_enabler(18) = '1' else
register_data_write_notequal when instruction_enabler(19) = '1' else
register_data_write_jump when instruction_enabler(20) = '1' else
register_data_write_jumpifcarry when instruction_enabler(21) = '1' else
register_data_write_halt when instruction_enabler(22) = '1' else
register_data_write_reset when instruction_enabler(23) = '1';
-- [[[end]]]
register_operation <=
register_operation_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_operation_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_operation_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_operation_load when instruction_enabler(0) = '1' else
register_operation_store when instruction_enabler(1) = '1' else
register_operation_writeio when instruction_enabler(2) = '1' else
register_operation_readio when instruction_enabler(3) = '1' else
register_operation_add when instruction_enabler(4) = '1' else
register_operation_subtract when instruction_enabler(5) = '1' else
register_operation_multiply when instruction_enabler(6) = '1' else
register_operation_divide when instruction_enabler(7) = '1' else
register_operation_bitwiseand when instruction_enabler(8) = '1' else
register_operation_bitwiseor when instruction_enabler(9) = '1' else
register_operation_bitwisenand when instruction_enabler(10) = '1' else
register_operation_bitwisenor when instruction_enabler(11) = '1' else
register_operation_bitwisexor when instruction_enabler(12) = '1' else
register_operation_bitwisenot when instruction_enabler(13) = '1' else
register_operation_greaterthan when instruction_enabler(14) = '1' else
register_operation_greaterorequalthan when instruction_enabler(15) = '1' else
register_operation_lessthan when instruction_enabler(16) = '1' else
register_operation_lessorequalthan when instruction_enabler(17) = '1' else
register_operation_equal when instruction_enabler(18) = '1' else
register_operation_notequal when instruction_enabler(19) = '1' else
register_operation_jump when instruction_enabler(20) = '1' else
register_operation_jumpifcarry when instruction_enabler(21) = '1' else
register_operation_halt when instruction_enabler(22) = '1' else
register_operation_reset when instruction_enabler(23) = '1';
-- [[[end]]]
register_enable <=
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_enable_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_enable_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_enable_load when instruction_enabler(0) = '1' else
register_enable_store when instruction_enabler(1) = '1' else
register_enable_writeio when instruction_enabler(2) = '1' else
register_enable_readio when instruction_enabler(3) = '1' else
register_enable_add when instruction_enabler(4) = '1' else
register_enable_subtract when instruction_enabler(5) = '1' else
register_enable_multiply when instruction_enabler(6) = '1' else
register_enable_divide when instruction_enabler(7) = '1' else
register_enable_bitwiseand when instruction_enabler(8) = '1' else
register_enable_bitwiseor when instruction_enabler(9) = '1' else
register_enable_bitwisenand when instruction_enabler(10) = '1' else
register_enable_bitwisenor when instruction_enabler(11) = '1' else
register_enable_bitwisexor when instruction_enabler(12) = '1' else
register_enable_bitwisenot when instruction_enabler(13) = '1' else
register_enable_greaterthan when instruction_enabler(14) = '1' else
register_enable_greaterorequalthan when instruction_enabler(15) = '1' else
register_enable_lessthan when instruction_enabler(16) = '1' else
register_enable_lessorequalthan when instruction_enabler(17) = '1' else
register_enable_equal when instruction_enabler(18) = '1' else
register_enable_notequal when instruction_enabler(19) = '1' else
register_enable_jump when instruction_enabler(20) = '1' else
register_enable_jumpifcarry when instruction_enabler(21) = '1' else
register_enable_halt when instruction_enabler(22) = '1' else
register_enable_reset when instruction_enabler(23) = '1' else
-- [[[end]]]
'0';
register_address <=
register_address_local when mux_disabled = '1' else
-- [[[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content[:-1]:
-- cog.outl("\tregister_address_{0} when instruction_enabler({1}) = '1' else".format(line.lower(), counter));
-- counter = counter + 1
--cog.outl("\tregister_address_{0} when instruction_enabler({1}) = '1';".format(content[-1].lower(), counter));
--]]]
register_address_load when instruction_enabler(0) = '1' else
register_address_store when instruction_enabler(1) = '1' else
register_address_writeio when instruction_enabler(2) = '1' else
register_address_readio when instruction_enabler(3) = '1' else
register_address_add when instruction_enabler(4) = '1' else
register_address_subtract when instruction_enabler(5) = '1' else
register_address_multiply when instruction_enabler(6) = '1' else
register_address_divide when instruction_enabler(7) = '1' else
register_address_bitwiseand when instruction_enabler(8) = '1' else
register_address_bitwiseor when instruction_enabler(9) = '1' else
register_address_bitwisenand when instruction_enabler(10) = '1' else
register_address_bitwisenor when instruction_enabler(11) = '1' else
register_address_bitwisexor when instruction_enabler(12) = '1' else
register_address_bitwisenot when instruction_enabler(13) = '1' else
register_address_greaterthan when instruction_enabler(14) = '1' else
register_address_greaterorequalthan when instruction_enabler(15) = '1' else
register_address_lessthan when instruction_enabler(16) = '1' else
register_address_lessorequalthan when instruction_enabler(17) = '1' else
register_address_equal when instruction_enabler(18) = '1' else
register_address_notequal when instruction_enabler(19) = '1' else
register_address_jump when instruction_enabler(20) = '1' else
register_address_jumpifcarry when instruction_enabler(21) = '1' else
register_address_halt when instruction_enabler(22) = '1' else
register_address_reset when instruction_enabler(23) = '1';
-- [[[end]]]
-- [[--[cog
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content:
-- template_vars = {
-- 'LowerName': line.lower(),
-- 'Name': line,
-- 'Index': counter
-- }
-- cog.outl("{LowerName}_instruction_executor: {Name}InstructionExecutor port map(".format(**template_vars))
-- cog.outl("\tclock => clock,".format(**template_vars))
-- cog.outl("\tenable => instruction_enabler({Index}),".format(**template_vars))
-- cog.outl("\targ0_address => current_instruction.reg0,".format(**template_vars))
-- cog.outl("\targ1_address => current_instruction.reg1,".format(**template_vars))
-- cog.outl("\tinstruction_ready => instruction_ready({Index}),".format(**template_vars))
-- cog.outl("\tmemory_address => memory_address_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_data_read => memory_data_read,".format(**template_vars))
-- cog.outl("\tmemory_data_write => memory_data_write_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_operation => memory_operation_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_enable => memory_enable_{LowerName},".format(**template_vars))
-- cog.outl("\tmemory_ready => memory_ready,".format(**template_vars))
-- cog.outl("\tregister_address => register_address_{LowerName},".format(**template_vars))
-- cog.outl("\tregister_operation => register_operation_{LowerName},".format(**template_vars))
-- cog.outl("\tregister_data_read => register_data_read,".format(**template_vars))
-- cog.outl("\tregister_data_write => register_data_write_{LowerName},".format(**template_vars))
-- cog.outl("\tregister_enable => register_enable_{LowerName},".format(**template_vars))
-- cog.outl("\tport0 => port0,".format(**template_vars))
-- cog.outl("\tport1 => port1_{LowerName}".format(**template_vars))
-- cog.outl(");".format(**template_vars))
-- cog.outl()
-- counter = counter + 1
--]]--]
load_instruction_executor: LoadInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(0),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
arg2_address => current_instruction.address,
instruction_ready => instruction_ready(0),
memory_address => memory_address_load,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_load,
memory_operation => memory_operation_load,
memory_enable => memory_enable_load,
memory_ready => memory_ready,
register_address => register_address_load,
register_operation => register_operation_load,
register_data_read => register_data_read,
register_data_write => register_data_write_load,
register_enable => register_enable_load,
register_ready => register_ready
);
store_instruction_executor: StoreInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(1),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
arg2_address => current_instruction.address,
instruction_ready => instruction_ready(1),
memory_address => memory_address_store,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_store,
memory_operation => memory_operation_store,
memory_enable => memory_enable_store,
memory_ready => memory_ready,
register_address => register_address_store,
register_operation => register_operation_store,
register_data_read => register_data_read,
register_data_write => register_data_write_store,
register_enable => register_enable_store,
register_ready => register_ready
);
writeio_instruction_executor: WriteIoInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(2),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(2),
memory_address => memory_address_writeio,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_writeio,
memory_operation => memory_operation_writeio,
memory_enable => memory_enable_writeio,
memory_ready => memory_ready,
register_address => register_address_writeio,
register_operation => register_operation_writeio,
register_data_read => register_data_read,
register_data_write => register_data_write_writeio,
register_enable => register_enable_writeio,
register_ready => register_ready,
port1 => port1
);
readio_instruction_executor: ReadIoInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(3),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(3),
memory_address => memory_address_readio,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_readio,
memory_operation => memory_operation_readio,
memory_enable => memory_enable_readio,
memory_ready => memory_ready,
register_address => register_address_readio,
register_operation => register_operation_readio,
register_data_read => register_data_read,
register_data_write => register_data_write_readio,
register_enable => register_enable_readio,
register_ready => register_ready,
port0 => port0
);
add_instruction_executor: AddInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(4),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(4),
memory_address => memory_address_add,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_add,
memory_operation => memory_operation_add,
memory_enable => memory_enable_add,
memory_ready => memory_ready,
register_address => register_address_add,
register_operation => register_operation_add,
register_data_read => register_data_read,
register_data_write => register_data_write_add,
register_enable => register_enable_add,
register_ready => register_ready
);
subtract_instruction_executor: SubtractInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(5),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(5),
memory_address => memory_address_subtract,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_subtract,
memory_operation => memory_operation_subtract,
memory_enable => memory_enable_subtract,
memory_ready => memory_ready,
register_address => register_address_subtract,
register_operation => register_operation_subtract,
register_data_read => register_data_read,
register_data_write => register_data_write_subtract,
register_enable => register_enable_subtract,
register_ready => register_ready
);
multiply_instruction_executor: MultiplyInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(6),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(6),
memory_address => memory_address_multiply,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_multiply,
memory_operation => memory_operation_multiply,
memory_enable => memory_enable_multiply,
memory_ready => memory_ready,
register_address => register_address_multiply,
register_operation => register_operation_multiply,
register_data_read => register_data_read,
register_data_write => register_data_write_multiply,
register_enable => register_enable_multiply,
register_ready => register_ready
);
divide_instruction_executor: DivideInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(7),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(7),
memory_address => memory_address_divide,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_divide,
memory_operation => memory_operation_divide,
memory_enable => memory_enable_divide,
memory_ready => memory_ready,
register_address => register_address_divide,
register_operation => register_operation_divide,
register_data_read => register_data_read,
register_data_write => register_data_write_divide,
register_enable => register_enable_divide,
register_ready => register_ready
);
bitwiseand_instruction_executor: BitwiseAndInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(8),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(8),
memory_address => memory_address_bitwiseand,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwiseand,
memory_operation => memory_operation_bitwiseand,
memory_enable => memory_enable_bitwiseand,
memory_ready => memory_ready,
register_address => register_address_bitwiseand,
register_operation => register_operation_bitwiseand,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwiseand,
register_enable => register_enable_bitwiseand,
register_ready => register_ready
);
bitwiseor_instruction_executor: BitwiseOrInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(9),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(9),
memory_address => memory_address_bitwiseor,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwiseor,
memory_operation => memory_operation_bitwiseor,
memory_enable => memory_enable_bitwiseor,
memory_ready => memory_ready,
register_address => register_address_bitwiseor,
register_operation => register_operation_bitwiseor,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwiseor,
register_enable => register_enable_bitwiseor,
register_ready => register_ready
);
bitwisenand_instruction_executor: BitwiseNandInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(10),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(10),
memory_address => memory_address_bitwisenand,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisenand,
memory_operation => memory_operation_bitwisenand,
memory_enable => memory_enable_bitwisenand,
memory_ready => memory_ready,
register_address => register_address_bitwisenand,
register_operation => register_operation_bitwisenand,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisenand,
register_enable => register_enable_bitwisenand,
register_ready => register_ready
);
bitwisenor_instruction_executor: BitwiseNorInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(11),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(11),
memory_address => memory_address_bitwisenor,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisenor,
memory_operation => memory_operation_bitwisenor,
memory_enable => memory_enable_bitwisenor,
memory_ready => memory_ready,
register_address => register_address_bitwisenor,
register_operation => register_operation_bitwisenor,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisenor,
register_enable => register_enable_bitwisenor,
register_ready => register_ready
);
bitwisexor_instruction_executor: BitwiseXorInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(12),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(12),
memory_address => memory_address_bitwisexor,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisexor,
memory_operation => memory_operation_bitwisexor,
memory_enable => memory_enable_bitwisexor,
memory_ready => memory_ready,
register_address => register_address_bitwisexor,
register_operation => register_operation_bitwisexor,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisexor,
register_enable => register_enable_bitwisexor,
register_ready => register_ready
);
bitwisenot_instruction_executor: BitwiseNotInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(13),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(13),
memory_address => memory_address_bitwisenot,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_bitwisenot,
memory_operation => memory_operation_bitwisenot,
memory_enable => memory_enable_bitwisenot,
memory_ready => memory_ready,
register_address => register_address_bitwisenot,
register_operation => register_operation_bitwisenot,
register_data_read => register_data_read,
register_data_write => register_data_write_bitwisenot,
register_enable => register_enable_bitwisenot,
register_ready => register_ready
);
greaterthan_instruction_executor: GreaterThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(14),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(14),
memory_address => memory_address_greaterthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_greaterthan,
memory_operation => memory_operation_greaterthan,
memory_enable => memory_enable_greaterthan,
memory_ready => memory_ready,
register_address => register_address_greaterthan,
register_operation => register_operation_greaterthan,
register_data_read => register_data_read,
register_data_write => register_data_write_greaterthan,
register_enable => register_enable_greaterthan,
register_ready => register_ready
);
greaterorequalthan_instruction_executor: GreaterOrEqualThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(15),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(15),
memory_address => memory_address_greaterorequalthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_greaterorequalthan,
memory_operation => memory_operation_greaterorequalthan,
memory_enable => memory_enable_greaterorequalthan,
memory_ready => memory_ready,
register_address => register_address_greaterorequalthan,
register_operation => register_operation_greaterorequalthan,
register_data_read => register_data_read,
register_data_write => register_data_write_greaterorequalthan,
register_enable => register_enable_greaterorequalthan,
register_ready => register_ready
);
lessthan_instruction_executor: LessThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(16),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(16),
memory_address => memory_address_lessthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_lessthan,
memory_operation => memory_operation_lessthan,
memory_enable => memory_enable_lessthan,
memory_ready => memory_ready,
register_address => register_address_lessthan,
register_operation => register_operation_lessthan,
register_data_read => register_data_read,
register_data_write => register_data_write_lessthan,
register_enable => register_enable_lessthan,
register_ready => register_ready
);
lessorequalthan_instruction_executor: LessOrEqualThanInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(17),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(17),
memory_address => memory_address_lessorequalthan,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_lessorequalthan,
memory_operation => memory_operation_lessorequalthan,
memory_enable => memory_enable_lessorequalthan,
memory_ready => memory_ready,
register_address => register_address_lessorequalthan,
register_operation => register_operation_lessorequalthan,
register_data_read => register_data_read,
register_data_write => register_data_write_lessorequalthan,
register_enable => register_enable_lessorequalthan,
register_ready => register_ready
);
equal_instruction_executor: EqualInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(18),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(18),
memory_address => memory_address_equal,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_equal,
memory_operation => memory_operation_equal,
memory_enable => memory_enable_equal,
memory_ready => memory_ready,
register_address => register_address_equal,
register_operation => register_operation_equal,
register_data_read => register_data_read,
register_data_write => register_data_write_equal,
register_enable => register_enable_equal,
register_ready => register_ready
);
notequal_instruction_executor: NotEqualInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(19),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(19),
memory_address => memory_address_notequal,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_notequal,
memory_operation => memory_operation_notequal,
memory_enable => memory_enable_notequal,
memory_ready => memory_ready,
register_address => register_address_notequal,
register_operation => register_operation_notequal,
register_data_read => register_data_read,
register_data_write => register_data_write_notequal,
register_enable => register_enable_notequal,
register_ready => register_ready
);
jump_instruction_executor: JumpInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(20),
arg0_address => current_instruction.address,
instruction_ready => instruction_ready(20),
memory_address => memory_address_jump,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_jump,
memory_operation => memory_operation_jump,
memory_enable => memory_enable_jump,
memory_ready => memory_ready,
register_address => register_address_jump,
register_operation => register_operation_jump,
register_data_read => register_data_read,
register_data_write => register_data_write_jump,
register_enable => register_enable_jump,
program_counter => jump_program_counter,
program_counter_set => jump_program_counter_set,
register_ready => register_ready
);
jumpifcarry_instruction_executor: JumpIfCarryInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(21),
arg0_address => current_instruction.address,
instruction_ready => instruction_ready(21),
memory_address => memory_address_jumpifcarry,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_jumpifcarry,
memory_operation => memory_operation_jumpifcarry,
memory_enable => memory_enable_jumpifcarry,
memory_ready => memory_ready,
register_address => register_address_jumpifcarry,
register_operation => register_operation_jumpifcarry,
register_data_read => register_data_read,
register_data_write => register_data_write_jumpifcarry,
register_enable => register_enable_jumpifcarry,
register_ready => register_ready,
program_counter => jump_if_carry_program_counter,
program_counter_set => jump_if_carry_program_counter_set
);
halt_instruction_executor: HaltInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(22),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(22),
memory_address => memory_address_halt,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_halt,
memory_operation => memory_operation_halt,
memory_enable => memory_enable_halt,
memory_ready => memory_ready,
register_address => register_address_halt,
register_operation => register_operation_halt,
register_data_read => register_data_read,
register_data_write => register_data_write_halt,
register_enable => register_enable_halt,
register_ready => register_ready
);
reset_instruction_executor: ResetInstructionExecutor port map(
clock => clock,
enable => instruction_enabler(23),
arg0_address => current_instruction.reg0,
arg1_address => current_instruction.reg1,
instruction_ready => instruction_ready(23),
memory_address => memory_address_reset,
memory_data_read => memory_data_read,
memory_data_write => memory_data_write_reset,
memory_operation => memory_operation_reset,
memory_enable => memory_enable_reset,
memory_ready => memory_ready,
register_address => register_address_reset,
register_operation => register_operation_reset,
register_data_read => register_data_read,
register_data_write => register_data_write_reset,
register_enable => register_enable_reset,
register_ready => register_ready
);
-- [[[--end]]]
process(clock) begin
if clock'event and clock = '1' then
case state is
when read_memory0 =>
mux_disabled <= '1';
memory_address_local <= program_counter;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory0;
when wait_memory0 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(0 to 7) <= memory_data_read;
memory_enable_local <= '0';
state <= read_memory1;
else
state <= wait_memory0;
end if;
when read_memory1 =>
mux_disabled <= '1';
memory_address_local <= program_counter + 1;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory1;
when wait_memory1 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(8 to 15) <= memory_data_read;
memory_enable_local <= '0';
state <= read_memory2;
else
state <= wait_memory1;
end if;
when read_memory2 =>
mux_disabled <= '1';
memory_address_local <= program_counter + 2;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory2;
when wait_memory2 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(16 to 23) <= memory_data_read;
memory_enable_local <= '0';
state <= read_memory3;
else
state <= wait_memory2;
end if;
when read_memory3 =>
mux_disabled <= '1';
memory_address_local <= program_counter + 3;
memory_operation_local <= MEMORY_OP_READ;
memory_enable_local <= '1';
state <= wait_memory3;
when wait_memory3 =>
mux_disabled <= '1';
if memory_ready = '1' then
instruction_data(24 to 31) <= memory_data_read;
memory_enable_local <= '0';
state <= decode_instruction;
else
state <= wait_memory3;
end if;
when decode_instruction =>
mux_disabled <= '0';
memory_enable_local <= '0';
case instruction_data(0 to 7) is
when "00000000" =>
current_instruction.opcode <= LOAD;
current_instruction.reg0 <= unsigned(instruction_data(8 to 11));
current_instruction.reg1 <= unsigned(instruction_data(12 to 15));
current_instruction.address <= unsigned(instruction_data(16 to 31));
if unsigned(instruction_data(8 to 11)) = 0 then
current_instruction.size <= 3;
elsif unsigned(instruction_data(8 to 11)) = 1 then
current_instruction.size <= 4;
elsif unsigned(instruction_data(8 to 11)) = 2 then
current_instruction.size <= 4;
end if;
when "00000001" =>
current_instruction.opcode <= STORE;
current_instruction.size <= 4;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
current_instruction.address <= unsigned(instruction_data(16 to 31));
when "00000010" =>
current_instruction.opcode <= WRITE_IO;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00000011" =>
current_instruction.opcode <= READ_IO;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010000" =>
current_instruction.opcode <= ADD;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010001" =>
current_instruction.opcode <= SUBTRACT;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010010" =>
current_instruction.opcode <= MULTIPLY;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00010011" =>
current_instruction.opcode <= DIVIDE;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000000" =>
current_instruction.opcode <= BITWISE_AND;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000001" =>
current_instruction.opcode <= BITWISE_OR;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000010" =>
current_instruction.opcode <= BITWISE_NAND;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000011" =>
current_instruction.opcode <= BITWISE_NOR;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000100" =>
current_instruction.opcode <= BITWISE_XOR;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "01000101" =>
current_instruction.opcode <= BITWISE_NOT;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110000" =>
current_instruction.opcode <= GREATER_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110001" =>
current_instruction.opcode <= GREATER_OR_EQUAL_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110010" =>
current_instruction.opcode <= LESS_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110011" =>
current_instruction.opcode <= LESS_OR_EQUAL_THAN;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110100" =>
current_instruction.opcode <= EQUAL;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00110101" =>
current_instruction.opcode <= NOT_EQUAL;
current_instruction.size <= 2;
current_instruction.reg0 <= (unsigned(instruction_data(8 to 11)));
current_instruction.reg1 <= (unsigned(instruction_data(12 to 15)));
when "00100000" =>
current_instruction.opcode <= JUMP;
current_instruction.size <= 3;
current_instruction.address <= bits_to_memory_address(instruction_data(8 to 23));
when "00100010" =>
current_instruction.opcode <= JUMP_IF_CARRY;
current_instruction.size <= 3;
current_instruction.address <= bits_to_memory_address(instruction_data(8 to 23));
when others =>
current_instruction.opcode <= HALT;
current_instruction.size <= 1;
end case;
state <= execute;
when execute =>
mux_disabled <= '0';
program_counter <= program_counter + current_instruction.size;
case current_instruction.opcode is
-- [[[cog
--import re
--
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content:
-- cog.outl("when {0} => instruction_enabler <= ({1} => '1', others => '0');".format(re.sub('([a-z0-9])([A-Z])', r'\1_\2', re.sub('(.)([A-Z][a-z]+)', r'\1_\2', line)).upper(), counter))
-- counter = counter + 1
--]]]
when LOAD => instruction_enabler <= (0 => '1', others => '0');
when STORE => instruction_enabler <= (1 => '1', others => '0');
when WRITE_IO => instruction_enabler <= (2 => '1', others => '0');
when READ_IO => instruction_enabler <= (3 => '1', others => '0');
when ADD => instruction_enabler <= (4 => '1', others => '0');
when SUBTRACT => instruction_enabler <= (5 => '1', others => '0');
when MULTIPLY => instruction_enabler <= (6 => '1', others => '0');
when DIVIDE => instruction_enabler <= (7 => '1', others => '0');
when BITWISE_AND => instruction_enabler <= (8 => '1', others => '0');
when BITWISE_OR => instruction_enabler <= (9 => '1', others => '0');
when BITWISE_NAND => instruction_enabler <= (10 => '1', others => '0');
when BITWISE_NOR => instruction_enabler <= (11 => '1', others => '0');
when BITWISE_XOR => instruction_enabler <= (12 => '1', others => '0');
when BITWISE_NOT => instruction_enabler <= (13 => '1', others => '0');
when GREATER_THAN => instruction_enabler <= (14 => '1', others => '0');
when GREATER_OR_EQUAL_THAN => instruction_enabler <= (15 => '1', others => '0');
when LESS_THAN => instruction_enabler <= (16 => '1', others => '0');
when LESS_OR_EQUAL_THAN => instruction_enabler <= (17 => '1', others => '0');
when EQUAL => instruction_enabler <= (18 => '1', others => '0');
when NOT_EQUAL => instruction_enabler <= (19 => '1', others => '0');
when JUMP => instruction_enabler <= (20 => '1', others => '0');
when JUMP_IF_CARRY => instruction_enabler <= (21 => '1', others => '0');
when HALT => instruction_enabler <= (22 => '1', others => '0');
when RESET => instruction_enabler <= (23 => '1', others => '0');
-- [[[end]]]
when others =>
instruction_enabler <= (others => '0');
end case;
state <= wait_execute;
when wait_execute =>
-- program_counter <=
-- jump_program_counter when jump_program_counter_set = '1' else
-- jump_if_carry_program_counter when jump_if_carry_program_counter_set = '1' else
-- program_counter;
if jump_program_counter_set = '1' then
program_counter <= jump_program_counter;
elsif jump_if_carry_program_counter_set = '1' then
program_counter <= jump_if_carry_program_counter;
else
program_counter <= program_counter;
end if;
case current_instruction.opcode is
-- [[[cog
--import re
--
--content = [line.rstrip('\n') for line in open('instructions.txt')]
--counter=0;
--for line in content:
-- cog.outl("when {0} => ".format(re.sub('([a-z0-9])([A-Z])', r'\1_\2', re.sub('(.)([A-Z][a-z]+)', r'\1_\2', line)).upper(), counter))
-- cog.outl("\tif instruction_ready({0}) = '1' then".format(counter))
-- cog.outl("\t\tinstruction_enabler <= (others => '0');")
-- cog.outl("\t\tmux_disabled <= '1';")
-- cog.outl("\t\tstate <= read_memory0;")
-- cog.outl("\telse")
-- cog.outl("\t\tstate <= wait_execute;")
-- cog.outl("\tend if;")
-- counter = counter + 1
--]]]
when LOAD =>
if instruction_ready(0) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when STORE =>
if instruction_ready(1) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when WRITE_IO =>
if instruction_ready(2) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when READ_IO =>
if instruction_ready(3) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when ADD =>
if instruction_ready(4) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when SUBTRACT =>
if instruction_ready(5) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when MULTIPLY =>
if instruction_ready(6) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when DIVIDE =>
if instruction_ready(7) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_AND =>
if instruction_ready(8) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_OR =>
if instruction_ready(9) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_NAND =>
if instruction_ready(10) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_NOR =>
if instruction_ready(11) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_XOR =>
if instruction_ready(12) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when BITWISE_NOT =>
if instruction_ready(13) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when GREATER_THAN =>
if instruction_ready(14) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when GREATER_OR_EQUAL_THAN =>
if instruction_ready(15) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when LESS_THAN =>
if instruction_ready(16) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when LESS_OR_EQUAL_THAN =>
if instruction_ready(17) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when EQUAL =>
if instruction_ready(18) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when NOT_EQUAL =>
if instruction_ready(19) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when JUMP =>
if instruction_ready(20) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when JUMP_IF_CARRY =>
if instruction_ready(21) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when HALT =>
if instruction_ready(22) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
when RESET =>
if instruction_ready(23) = '1' then
instruction_enabler <= (others => '0');
mux_disabled <= '1';
state <= read_memory0;
else
state <= wait_execute;
end if;
-- [[[end]]]
end case;
end case;
end if;
end process;
end InstructionControllerImpl;
|
library verilog;
use verilog.vl_types.all;
entity cycloneiiigl_post_divider is
generic(
dpa_divider : integer := 1
);
port(
clk : in vl_logic;
reset : in vl_logic;
cout : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of dpa_divider : constant is 1;
end cycloneiiigl_post_divider;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_constant_GN2BKT43XO is
generic ( HDLTYPE : string := "STD_LOGIC_VECTOR";
BitPattern : string := "0000001010000000";
width : natural := 16);
port(
output : out std_logic_vector(15 downto 0));
end entity;
architecture rtl of alt_dspbuilder_constant_GN2BKT43XO is
Begin
-- Constant
output <= "0000001010000000";
end architecture; |
entity test is
end test;
architecture only of test is
type integer_t1 is range 0 to 2;
type integer_t2 is range 2 to 4;
function test_function ( constant param : integer_t1 )
return boolean is
begin
return true;
end function;
function test_function ( constant param : integer_t2 )
return boolean is
begin
return true;
end function;
begin -- only
test: process
variable result : boolean;
variable param1 : integer_t1 := 3;
variable param2 : integer_t2 := 5;
begin -- process
result := test_function( param1 );
result := test_function( param2 );
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
type integer_t1 is range 0 to 2;
type integer_t2 is range 2 to 4;
function test_function ( constant param : integer_t1 )
return boolean is
begin
return true;
end function;
function test_function ( constant param : integer_t2 )
return boolean is
begin
return true;
end function;
begin -- only
test: process
variable result : boolean;
variable param1 : integer_t1 := 3;
variable param2 : integer_t2 := 5;
begin -- process
result := test_function( param1 );
result := test_function( param2 );
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
type integer_t1 is range 0 to 2;
type integer_t2 is range 2 to 4;
function test_function ( constant param : integer_t1 )
return boolean is
begin
return true;
end function;
function test_function ( constant param : integer_t2 )
return boolean is
begin
return true;
end function;
begin -- only
test: process
variable result : boolean;
variable param1 : integer_t1 := 3;
variable param2 : integer_t2 := 5;
begin -- process
result := test_function( param1 );
result := test_function( param2 );
wait;
end process;
end only;
|
----------------------------------------------------------------------------------------------------
-- ENTITY - Elliptic Curve Point Multiplication
--
-- Ports:
-- clk_i - Clock
-- rst_i - Reset flag
-- enable_i - Enable computation
-- xp_i - X part of input point
-- yp_i - Y part of input point
-- k_i - Multiplier k
-- xq_io - X part of output point
-- yq_io - Y part of output point
-- ready_o - Ready flag
--
-- Based on:
-- http://arithmetic-circuits.org/finite-field/vhdl_Models/chapter10_codes/VHDL/K-163/K163_point_multiplication.vhd
--
-- Autor: Lennart Bublies (inf100434)
-- Date: 29.06.2017
----------------------------------------------------------------------------------------------------
------------------------------------------------------------
-- GF(2^M) point multiplication
------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_unsigned.all;
USE work.tld_ecdsa_package.all;
ENTITY e_gf2m_point_multiplication IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0) := ONE
);
PORT (
-- Clock, reset, enable
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
xp_i: IN std_logic_vector(M-1 DOWNTO 0);
yp_i: IN std_logic_vector(M-1 DOWNTO 0);
k_i: IN std_logic_vector(M-1 DOWNTO 0);
xq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
yq_io: INOUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END e_gf2m_point_multiplication;
ARCHITECTURE rtl of e_gf2m_point_multiplication IS
-- Import entity e_gf2m_point_addition
COMPONENT e_gf2m_point_addition IS
GENERIC (
MODULO : std_logic_vector(M DOWNTO 0)
);
PORT(
clk_i: IN std_logic;
rst_i: IN std_logic;
enable_i: IN std_logic;
x1_i: IN std_logic_vector(M-1 DOWNTO 0);
y1_i: IN std_logic_vector(M-1 DOWNTO 0);
x2_i: IN std_logic_vector(M-1 DOWNTO 0);
y2_i: IN std_logic_vector(M-1 DOWNTO 0);
x3_io: INOUT std_logic_vector(M-1 DOWNTO 0);
y3_o: OUT std_logic_vector(M-1 DOWNTO 0);
ready_o: OUT std_logic
);
END COMPONENT;
-- Import entity e_gf2m_classic_squarer
COMPONENT e_gf2m_classic_squarer IS
GENERIC (
MODULO : std_logic_vector(M-1 DOWNTO 0)
);
PORT(
a_i: IN std_logic_vector(M-1 DOWNTO 0);
c_o: OUT std_logic_vector(M-1 DOWNTO 0)
);
END COMPONENT;
-- Internal signals
SIGNAL a, next_a, a_div_2: std_logic_vector(m DOWNTO 0);
SIGNAL b, next_b: std_logic_vector(m-1 DOWNTO 0);
SIGNAL xxP, yyP, next_xQ, next_yQ, xxPxoryyP, square_xxP, square_yyP, y1, x3, y3: std_logic_vector(m-1 DOWNTO 0);
SIGNAL ce_P, ce_Q, ce_ab, load, sel_1, start_addition, addition_done, carry, Q_infinity, aEqual0, bEqual0, a1xorb0: std_logic;
SIGNAL sel_2: std_logic_vector(1 DOWNTO 0);
-- Define all available states
subtype states IS natural RANGE 0 TO 12;
SIGNAL current_state: states;
BEGIN
-- Instantiate point addition entity
-- Calculate (x3, y3) = (xxp, y1) + (xq, yq)
first_component: e_gf2m_point_addition GENERIC MAP (
MODULO => MODULO
) PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable_i => start_addition,
x1_i => xxP,
y1_i => y1,
x2_i => xq_io,
y2_i => yq_io,
x3_io => x3,
y3_o => y3,
ready_o => addition_done
);
-- Instantiate squarer entity for x part
-- Calculate xxp^2
x_squarer: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => xxP,
c_o => square_xxP
);
-- Instantiate squarer entity for y part
-- Calculate yyp^2
y_squarer: e_gf2m_classic_squarer GENERIC MAP (
MODULO => MODULO(M-1 DOWNTO 0)
) PORT MAP(
a_i => yyP,
c_o => square_yyP
);
-- Calculate xxp XOR yyp
xor_gates: FOR i IN 0 TO m-1 GENERATE
xxPxoryyP(i) <= xxP(i) xor yyP(i);
END GENERATE;
WITH sel_1 SELECT y1 <= yyP WHEN '0', xxPxoryyP WHEN OTHERS;
WITH sel_2 SELECT next_yQ <= y3 WHEN "00", yyP WHEN "01", xxPxoryyP WHEN OTHERS;
WITH sel_2 SELECT next_xQ <= x3 WHEN "00", xxP WHEN OTHERS;
register_P: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
xxP <= xp_i;
yyP <= yp_i;
ELSIF ce_P = '1' THEN
xxP <= square_xxP;
yyP <= square_yyP;
END IF;
END IF;
END PROCESS;
register_Q: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
Q_infinity <= '1';
ELSIF ce_Q = '1' THEN
xq_io <= next_xQ;
yq_io <= next_yQ;
Q_infinity <= '0';
END IF;
END IF;
END PROCESS;
divide_by_2: FOR i IN 0 TO m-1 GENERATE
a_div_2(i) <= a(i+1);
END GENERATE;
a_div_2(m) <= a(m);
next_a <= (b(m-1)&b) + a_div_2 + carry;
next_b <= zero - (a_div_2(m-1 DOWNTO 0) + carry);
register_ab: PROCESS(clk_i)
BEGIN
IF clk_i' event and clk_i = '1' THEN
IF load = '1' THEN
a <= ('0'&k_i);
b <= zero;
ELSIF ce_ab = '1' THEN
a <= next_a;
b <= next_b;
END IF;
END IF;
END PROCESS;
aEqual0 <= '1' WHEN a = 0 ELSE '0';
bEqual0 <= '1' WHEN b = 0 ELSE '0';
a1xorb0 <= a(1) xor b(0);
-- State machine
control_unit: PROCESS(clk_i, rst_i, current_state, addition_done, aEqual0, bEqual0, a(0), a1xorb0, Q_infinity)
BEGIN
-- Handle current state
-- 0,1 : Default state
-- 2,3 : Load k, xp, yp, ...
-- 4,5 : Square xxp, yyp, ...
-- 6,7 :
--
CASE current_state IS
WHEN 0 TO 1 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '1';
WHEN 2 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '1'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 3 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 4 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '1'; ce_Q <= '0'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 5 => sel_1 <= '0'; sel_2 <= "01"; carry <= '0'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 6 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '1'; ready_o <= '0';
WHEN 7 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 8 => sel_1 <= '0'; sel_2 <= "00"; carry <= '0'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 9 => sel_1 <= '1'; sel_2 <= "10"; carry <= '1'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
WHEN 10 => sel_1 <= '1'; sel_2 <= "00"; carry <= '1'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '1'; ready_o <= '0';
WHEN 11 => sel_1 <= '1'; sel_2 <= "00"; carry <= '1'; load <= '0'; ce_P <= '0'; ce_Q <= '0'; ce_ab <= '0'; start_addition <= '0'; ready_o <= '0';
WHEN 12 => sel_1 <= '1'; sel_2 <= "00"; carry <= '1'; load <= '0'; ce_P <= '1'; ce_Q <= '1'; ce_ab <= '1'; start_addition <= '0'; ready_o <= '0';
END CASE;
IF rst_i = '1' THEN
-- Reset state if reset is high
current_state <= 0;
ELSIF clk_i'event and clk_i = '1' THEN
-- Set next state
CASE current_state IS
WHEN 0 =>
IF enable_i = '0' THEN
current_state <= 1;
END IF;
WHEN 1 =>
IF enable_i = '1' THEN
current_state <= 2;
END IF;
WHEN 2 =>
current_state <= 3;
WHEN 3 =>
IF (aEqual0 = '1') and (bEqual0 = '1') THEN
current_state <= 0;
ELSIF a(0) = '0' THEN
current_state <= 4;
ELSIF (a1xorb0 = '0') and (Q_infinity = '1') THEN
current_state <= 5;
ELSIF (a1xorb0 = '0') and (Q_infinity = '0') THEN
current_state <= 6;
ELSIF (a1xorb0 = '1') and (Q_infinity = '1') THEN
current_state <= 9;
ELSE
current_state <= 10;
END IF;
WHEN 4 =>
current_state <= 3;
WHEN 5 =>
current_state <= 3;
WHEN 6 =>
current_state <= 7;
WHEN 7 =>
IF addition_done = '1' THEN
current_state <= 8;
END IF;
WHEN 8 =>
current_state <= 3;
WHEN 9 =>
current_state <= 3;
WHEN 10 =>
current_state <= 11;
WHEN 11 =>
IF addition_done = '1' THEN
current_state <= 12;
END IF;
WHEN 12 =>
current_state <= 3;
END CASE;
END IF;
END PROCESS;
END rtl;
|
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils_pkg.all;
entity kitt_lights is
generic
(
-- Number of LEDs
LIGHTS_N : positive;
-- Number of clock cycles to advance an LED
ADVANCE_VAL : positive;
-- Number of bits in the PWM counter
PWM_BITS_N : positive;
-- Number of clock cycles for an LED to decay one PWM step
DECAY_VAL : positive
);
port
(
clk : in std_logic;
reset : in std_logic;
lights_out : out std_logic_vector(LIGHTS_N - 1 downto 0)
);
end entity;
architecture rtl of kitt_lights is
type decay_t is array (lights_out'range)
of unsigned(PWM_BITS_N - 1 downto 0);
signal decay : decay_t;
signal active : std_logic_vector(lights_out'range);
begin
-- Advance currently active LED
advance_p: process(clk, reset)
variable timer : unsigned(ceil_log2(ADVANCE_VAL) downto 0);
variable dir_up : boolean;
begin
if reset = '1' then
active <= (others => '0');
timer := (others => '0');
dir_up := false;
elsif rising_edge(clk) then
-- If all lights are off
if active = (active'range => '0') then
active(0) <= '1';
-- Delay done, advance to next LED
elsif timer = ADVANCE_VAL then
timer := (others => '0');
-- Change direction
if active(active'left) = '1' or active(active'right) = '1' then
dir_up := not dir_up;
end if;
-- Advance
if dir_up = true then
active <= shift_left_vec(active, 1);
else
active <= shift_right_vec(active, 1);
end if;
else
timer := timer + 1;
end if;
end if;
end process;
-- Calculate PWM values for all LEDs and decay them when LED is not active
decay_p: process(clk, reset)
variable counter : unsigned(ceil_log2(DECAY_VAL) downto 0);
begin
if reset = '1' then
decay <= (others => (others => '0'));
counter := (others => '0');
elsif rising_edge(clk) then
-- Delay done, decay PWM values
if counter = DECAY_VAL then
counter := (others => '0');
-- Calculate new PWM values
for i in 0 to decay'high loop
-- LED is currently active, apply full duty cycle
if active(i) = '1' then
decay(i) <= to_unsigned(2**PWM_BITS_N - 1, PWM_BITS_N);
-- LED is not active, decay PWM value
elsif active(i) = '0' then
-- Make sure decay does not wrap
if decay(i) >= 1 then
decay(i) <= decay(i) - to_unsigned(1, PWM_BITS_N);
else
decay(i) <= (others => '0');
end if;
end if;
end loop;
end if;
counter := counter + 1;
end if;
end process;
-- Apply PWM values
pwm_p: process(clk, reset)
variable pwm_timer : unsigned(PWM_BITS_N - 1 downto 0);
begin
if reset = '1' then
pwm_timer := (others => '0');
lights_out <= (others => '0');
elsif rising_edge(clk) then
-- Apply to all LED outputs
for i in 0 to lights_out'high loop
if pwm_timer <= decay(i) and not (decay(i) = 0) then
lights_out(i) <= '1';
else
lights_out(i) <= '0';
end if;
end loop;
pwm_timer := pwm_timer + 1;
end if;
end process;
end;
|
-- ****
-- T80(b) core. In an effort to merge and maintain bug fixes ....
--
--
-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
--
-- MikeJ March 2005
-- Latest version from www.fpgaarcade.com (original www.opencores.org)
--
-- ****
--
-- Z80 compatible microprocessor core
--
-- Version : 0247
--
-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t80/
--
-- Limitations :
--
-- File history :
--
-- 0208 : First complete release
--
-- 0210 : Fixed wait and halt
--
-- 0211 : Fixed Refresh addition and IM 1
--
-- 0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
--
-- 0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
--
-- 0235 : Added clock enable and IM 2 fix by Mike Johnson
--
-- 0237 : Changed 8080 I/O address output, added IntE output
--
-- 0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
--
-- 0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
--
-- 0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
--
-- 0247 : Fixed bus req/ack cycle
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T80_Pack.all;
entity T80 is
generic(
Mode : integer := 0; -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
IOWait : integer := 0; -- 1 => Single cycle I/O, 1 => Std I/O cycle
Flag_C : integer := 0;
Flag_N : integer := 1;
Flag_P : integer := 2;
Flag_X : integer := 3;
Flag_H : integer := 4;
Flag_Y : integer := 5;
Flag_Z : integer := 6;
Flag_S : integer := 7
);
port(
RESET_n : in std_logic;
CLK_n : in std_logic;
CEN : in std_logic;
WAIT_n : in std_logic;
INT_n : in std_logic;
NMI_n : in std_logic;
BUSRQ_n : in std_logic;
M1_n : out std_logic;
IORQ : out std_logic;
NoRead : out std_logic;
Write : out std_logic;
RFSH_n : out std_logic;
HALT_n : out std_logic;
BUSAK_n : out std_logic;
A : out std_logic_vector(15 downto 0);
DInst : in std_logic_vector(7 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
MC : out std_logic_vector(2 downto 0);
TS : out std_logic_vector(2 downto 0);
IntCycle_n : out std_logic;
IntE : out std_logic;
Stop : out std_logic
);
end T80;
architecture rtl of T80 is
-- Registers
signal ACC, F : std_logic_vector(7 downto 0);
signal Ap, Fp : std_logic_vector(7 downto 0);
signal I : std_logic_vector(7 downto 0);
signal R : unsigned(7 downto 0);
signal SP, PC : unsigned(15 downto 0);
signal RegDIH : std_logic_vector(7 downto 0);
signal RegDIL : std_logic_vector(7 downto 0);
signal RegBusA : std_logic_vector(15 downto 0);
signal RegBusB : std_logic_vector(15 downto 0);
signal RegBusC : std_logic_vector(15 downto 0);
signal RegAddrA_r : std_logic_vector(2 downto 0);
signal RegAddrA : std_logic_vector(2 downto 0);
signal RegAddrB_r : std_logic_vector(2 downto 0);
signal RegAddrB : std_logic_vector(2 downto 0);
signal RegAddrC : std_logic_vector(2 downto 0);
signal RegWEH : std_logic;
signal RegWEL : std_logic;
signal Alternate : std_logic;
-- Help Registers
signal TmpAddr : std_logic_vector(15 downto 0); -- Temporary address register
signal IR : std_logic_vector(7 downto 0); -- Instruction register
signal ISet : std_logic_vector(1 downto 0); -- Instruction set selector
signal RegBusA_r : std_logic_vector(15 downto 0);
signal ID16 : signed(15 downto 0);
signal Save_Mux : std_logic_vector(7 downto 0);
signal TState : unsigned(2 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal IntE_FF1 : std_logic;
signal IntE_FF2 : std_logic;
signal Halt_FF : std_logic;
signal BusReq_s : std_logic;
signal BusAck : std_logic;
signal ClkEn : std_logic;
signal NMI_s : std_logic;
signal INT_s : std_logic;
signal IStatus : std_logic_vector(1 downto 0);
signal DI_Reg : std_logic_vector(7 downto 0);
signal T_Res : std_logic;
signal XY_State : std_logic_vector(1 downto 0);
signal Pre_XY_F_M : std_logic_vector(2 downto 0);
signal NextIs_XY_Fetch : std_logic;
signal XY_Ind : std_logic;
signal No_BTR : std_logic;
signal BTR_r : std_logic;
signal Auto_Wait : std_logic;
signal Auto_Wait_t1 : std_logic;
signal Auto_Wait_t2 : std_logic;
signal IncDecZ : std_logic;
-- ALU signals
signal BusB : std_logic_vector(7 downto 0);
signal BusA : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal F_Out : std_logic_vector(7 downto 0);
-- Registered micro code outputs
signal Read_To_Reg_r : std_logic_vector(4 downto 0);
signal Arith16_r : std_logic;
signal Z16_r : std_logic;
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Save_ALU_r : std_logic;
signal PreserveC_r : std_logic;
signal MCycles : std_logic_vector(2 downto 0);
-- Micro code outputs
signal MCycles_d : std_logic_vector(2 downto 0);
signal TStates : std_logic_vector(2 downto 0);
signal IntCycle : std_logic;
signal NMICycle : std_logic;
signal Inc_PC : std_logic;
signal Inc_WZ : std_logic;
signal IncDec_16 : std_logic_vector(3 downto 0);
signal Prefix : std_logic_vector(1 downto 0);
signal Read_To_Acc : std_logic;
signal Read_To_Reg : std_logic;
signal Set_BusB_To : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(3 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Save_ALU : std_logic;
signal PreserveC : std_logic;
signal Arith16 : std_logic;
signal Set_Addr_To : std_logic_vector(2 downto 0);
signal Jump : std_logic;
signal JumpE : std_logic;
signal JumpXY : std_logic;
signal Call : std_logic;
signal RstP : std_logic;
signal LDZ : std_logic;
signal LDW : std_logic;
signal LDSPHL : std_logic;
signal IORQ_i : std_logic;
signal Special_LD : std_logic_vector(2 downto 0);
signal ExchangeDH : std_logic;
signal ExchangeRp : std_logic;
signal ExchangeAF : std_logic;
signal ExchangeRS : std_logic;
signal I_DJNZ : std_logic;
signal I_CPL : std_logic;
signal I_CCF : std_logic;
signal I_SCF : std_logic;
signal I_RETN : std_logic;
signal I_BT : std_logic;
signal I_BC : std_logic;
signal I_BTR : std_logic;
signal I_RLD : std_logic;
signal I_RRD : std_logic;
signal I_INRC : std_logic;
signal SetDI : std_logic;
signal SetEI : std_logic;
signal IMode : std_logic_vector(1 downto 0);
signal Halt : std_logic;
signal XYbit_undoc : std_logic;
begin
mcode : T80_MCode
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
IR => IR,
ISet => ISet,
MCycle => MCycle,
F => F,
NMICycle => NMICycle,
IntCycle => IntCycle,
XY_State => XY_State,
MCycles => MCycles_d,
TStates => TStates,
Prefix => Prefix,
Inc_PC => Inc_PC,
Inc_WZ => Inc_WZ,
IncDec_16 => IncDec_16,
Read_To_Acc => Read_To_Acc,
Read_To_Reg => Read_To_Reg,
Set_BusB_To => Set_BusB_To,
Set_BusA_To => Set_BusA_To,
ALU_Op => ALU_Op,
Save_ALU => Save_ALU,
PreserveC => PreserveC,
Arith16 => Arith16,
Set_Addr_To => Set_Addr_To,
IORQ => IORQ_i,
Jump => Jump,
JumpE => JumpE,
JumpXY => JumpXY,
Call => Call,
RstP => RstP,
LDZ => LDZ,
LDW => LDW,
LDSPHL => LDSPHL,
Special_LD => Special_LD,
ExchangeDH => ExchangeDH,
ExchangeRp => ExchangeRp,
ExchangeAF => ExchangeAF,
ExchangeRS => ExchangeRS,
I_DJNZ => I_DJNZ,
I_CPL => I_CPL,
I_CCF => I_CCF,
I_SCF => I_SCF,
I_RETN => I_RETN,
I_BT => I_BT,
I_BC => I_BC,
I_BTR => I_BTR,
I_RLD => I_RLD,
I_RRD => I_RRD,
I_INRC => I_INRC,
SetDI => SetDI,
SetEI => SetEI,
IMode => IMode,
Halt => Halt,
NoRead => NoRead,
Write => Write,
XYbit_undoc => XYbit_undoc);
alu : T80_ALU
generic map(
Mode => Mode,
Flag_C => Flag_C,
Flag_N => Flag_N,
Flag_P => Flag_P,
Flag_X => Flag_X,
Flag_H => Flag_H,
Flag_Y => Flag_Y,
Flag_Z => Flag_Z,
Flag_S => Flag_S)
port map(
Arith16 => Arith16_r,
Z16 => Z16_r,
ALU_Op => ALU_Op_r,
IR => IR(5 downto 0),
ISet => ISet,
BusA => BusA,
BusB => BusB,
F_In => F,
Q => ALU_Q,
F_Out => F_Out);
ClkEn <= CEN and not BusAck;
T_Res <= '1' when TState = unsigned(TStates) else '0';
NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
((Set_Addr_To = aXY) or
(MCycle = "001" and IR = "11001011") or
(MCycle = "001" and IR = "00110110")) else '0';
Save_Mux <= BusB when ExchangeRp = '1' else
DI_Reg when Save_ALU_r = '0' else
ALU_Q;
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
PC <= (others => '0'); -- Program Counter
A <= (others => '0');
TmpAddr <= (others => '0');
IR <= "00000000";
ISet <= "00";
XY_State <= "00";
IStatus <= "00";
MCycles <= "000";
DO <= "00000000";
ACC <= (others => '1');
F <= (others => '1');
Ap <= (others => '1');
Fp <= (others => '1');
I <= (others => '0');
R <= (others => '0');
SP <= (others => '1');
Alternate <= '0';
Read_To_Reg_r <= "00000";
F <= (others => '1');
Arith16_r <= '0';
BTR_r <= '0';
Z16_r <= '0';
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
PreserveC_r <= '0';
XY_Ind <= '0';
elsif CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
ALU_Op_r <= "0000";
Save_ALU_r <= '0';
Read_To_Reg_r <= "00000";
MCycles <= MCycles_d;
if Mode = 3 then
IStatus <= "10";
elsif IMode /= "11" then
IStatus <= IMode;
end if;
Arith16_r <= Arith16;
PreserveC_r <= PreserveC;
if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
Z16_r <= '1';
else
Z16_r <= '0';
end if;
if MCycle = "001" and TState(2) = '0' then
-- MCycle = 1 and TState = 1, 2, or 3
if TState = 2 and Wait_n = '1' then
if Mode < 2 then
A(7 downto 0) <= std_logic_vector(R);
A(15 downto 8) <= I;
R(6 downto 0) <= R(6 downto 0) + 1;
end if;
if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1') then
PC <= PC + 1;
end if;
if IntCycle = '1' and IStatus = "01" then
IR <= "11111111";
elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1' then
IR <= "00000000";
else
IR <= DInst;
end if;
ISet <= "00";
if Prefix /= "00" then
if Prefix = "11" then
if IR(5) = '1' then
XY_State <= "10";
else
XY_State <= "01";
end if;
else
if Prefix = "10" then
XY_State <= "00";
XY_Ind <= '0';
end if;
ISet <= Prefix;
end if;
else
XY_State <= "00";
XY_Ind <= '0';
end if;
end if;
else
-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
if MCycle = "110" then
XY_Ind <= '1';
if Prefix = "01" then
ISet <= "01";
end if;
end if;
if T_Res = '1' then
BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
if Jump = '1' then
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(DI_Reg);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
elsif JumpXY = '1' then
A <= RegBusC;
PC <= unsigned(RegBusC);
elsif Call = '1' or RstP = '1' then
A <= TmpAddr;
PC <= unsigned(TmpAddr);
elsif MCycle = MCycles and NMICycle = '1' then
A <= "0000000001100110";
PC <= "0000000001100110";
elsif MCycle = "011" and IntCycle = '1' and IStatus = "10" then
A(15 downto 8) <= I;
A(7 downto 0) <= TmpAddr(7 downto 0);
PC(15 downto 8) <= unsigned(I);
PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
else
case Set_Addr_To is
when aXY =>
if XY_State = "00" then
A <= RegBusC;
else
if NextIs_XY_Fetch = '1' then
A <= std_logic_vector(PC);
else
A <= TmpAddr;
end if;
end if;
when aIOA =>
if Mode = 3 then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
elsif Mode = 2 then
-- Duplicate I/O address on 8080
A(15 downto 8) <= DI_Reg;
else
A(15 downto 8) <= ACC;
end if;
A(7 downto 0) <= DI_Reg;
when aSP =>
A <= std_logic_vector(SP);
when aBC =>
if Mode = 3 and IORQ_i = '1' then
-- Memory map I/O on GBZ80
A(15 downto 8) <= (others => '1');
A(7 downto 0) <= RegBusC(7 downto 0);
else
A <= RegBusC;
end if;
when aDE =>
A <= RegBusC;
when aZI =>
if Inc_WZ = '1' then
A <= std_logic_vector(unsigned(TmpAddr) + 1);
else
A(15 downto 8) <= DI_Reg;
A(7 downto 0) <= TmpAddr(7 downto 0);
end if;
when others =>
A <= std_logic_vector(PC);
end case;
end if;
Save_ALU_r <= Save_ALU;
ALU_Op_r <= ALU_Op;
if I_CPL = '1' then
-- CPL
ACC <= not ACC;
F(Flag_Y) <= not ACC(5);
F(Flag_H) <= '1';
F(Flag_X) <= not ACC(3);
F(Flag_N) <= '1';
end if;
if I_CCF = '1' then
-- CCF
F(Flag_C) <= not F(Flag_C);
F(Flag_Y) <= ACC(5);
F(Flag_H) <= F(Flag_C);
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
if I_SCF = '1' then
-- SCF
F(Flag_C) <= '1';
F(Flag_Y) <= ACC(5);
F(Flag_H) <= '0';
F(Flag_X) <= ACC(3);
F(Flag_N) <= '0';
end if;
end if;
if TState = 2 and Wait_n = '1' then
if ISet = "01" and MCycle = "111" then
IR <= DInst;
end if;
if JumpE = '1' then
PC <= unsigned(signed(PC) + signed(DI_Reg));
elsif Inc_PC = '1' then
PC <= PC + 1;
end if;
if BTR_r = '1' then
PC <= PC - 2;
end if;
if RstP = '1' then
TmpAddr <= (others =>'0');
TmpAddr(5 downto 3) <= IR(5 downto 3);
end if;
end if;
if TState = 3 and MCycle = "110" then
TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
end if;
if (TState = 2 and Wait_n = '1') or (TState = 4 and MCycle = "001") then
if IncDec_16(2 downto 0) = "111" then
if IncDec_16(3) = '1' then
SP <= SP - 1;
else
SP <= SP + 1;
end if;
end if;
end if;
if LDSPHL = '1' then
SP <= unsigned(RegBusC);
end if;
if ExchangeAF = '1' then
Ap <= ACC;
ACC <= Ap;
Fp <= F;
F <= Fp;
end if;
if ExchangeRS = '1' then
Alternate <= not Alternate;
end if;
end if;
if TState = 3 then
if LDZ = '1' then
TmpAddr(7 downto 0) <= DI_Reg;
end if;
if LDW = '1' then
TmpAddr(15 downto 8) <= DI_Reg;
end if;
if Special_LD(2) = '1' then
case Special_LD(1 downto 0) is
when "00" =>
ACC <= I;
F(Flag_P) <= IntE_FF2;
if I = X"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= I(7);
when "01" =>
ACC <= std_logic_vector(R);
F(Flag_P) <= IntE_FF2;
if R = X"00" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= R(7);
when "10" =>
I <= ACC;
when others =>
R <= unsigned(ACC);
end case;
end if;
end if;
if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
if Mode = 3 then
F(6) <= F_Out(6);
F(5) <= F_Out(5);
F(7) <= F_Out(7);
if PreserveC_r = '0' then
F(4) <= F_Out(4);
end if;
else
F(7 downto 1) <= F_Out(7 downto 1);
if PreserveC_r = '0' then
F(Flag_C) <= F_Out(0);
end if;
end if;
end if;
if T_Res = '1' and I_INRC = '1' then
F(Flag_H) <= '0';
F(Flag_N) <= '0';
if DI_Reg(7 downto 0) = "00000000" then
F(Flag_Z) <= '1';
else
F(Flag_Z) <= '0';
end if;
F(Flag_S) <= DI_Reg(7);
F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
end if;
if TState = 1 then
DO <= BusB;
if I_RLD = '1' then
DO(3 downto 0) <= BusA(3 downto 0);
DO(7 downto 4) <= BusB(3 downto 0);
end if;
if I_RRD = '1' then
DO(3 downto 0) <= BusB(7 downto 4);
DO(7 downto 4) <= BusA(3 downto 0);
end if;
end if;
if T_Res = '1' then
Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
Read_To_Reg_r(4) <= Read_To_Reg;
if Read_To_Acc = '1' then
Read_To_Reg_r(3 downto 0) <= "0111";
Read_To_Reg_r(4) <= '1';
end if;
end if;
if TState = 1 and I_BT = '1' then
F(Flag_X) <= ALU_Q(3);
F(Flag_Y) <= ALU_Q(1);
F(Flag_H) <= '0';
F(Flag_N) <= '0';
end if;
if I_BC = '1' or I_BT = '1' then
F(Flag_P) <= IncDecZ;
end if;
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10111" =>
ACC <= Save_Mux;
when "10110" =>
DO <= Save_Mux;
when "11000" =>
SP(7 downto 0) <= unsigned(Save_Mux);
when "11001" =>
SP(15 downto 8) <= unsigned(Save_Mux);
when "11011" =>
F <= Save_Mux;
when others =>
end case;
if XYbit_undoc='1' then
DO <= ALU_Q;
end if;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- BC('), DE('), HL('), IX and IY
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
-- Bus A / Write
RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
RegAddrA_r <= XY_State(1) & "11";
end if;
-- Bus B
RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
RegAddrB_r <= XY_State(1) & "11";
end if;
-- Address from register
RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
-- Jump (HL), LD SP,HL
if (JumpXY = '1' or LDSPHL = '1') then
RegAddrC <= Alternate & "10";
end if;
if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
RegAddrC <= XY_State(1) & "11";
end if;
if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
IncDecZ <= F_Out(Flag_Z);
end if;
if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
if ID16 = 0 then
IncDecZ <= '0';
else
IncDecZ <= '1';
end if;
end if;
RegBusA_r <= RegBusA;
end if;
end if;
end process;
RegAddrA <=
-- 16 bit increment/decrement
Alternate & IncDec_16(1 downto 0) when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
XY_State(1) & "11" when (TState = 2 or
(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
-- EX HL,DL
Alternate & "10" when ExchangeDH = '1' and TState = 3 else
Alternate & "01" when ExchangeDH = '1' and TState = 4 else
-- Bus A / Write
RegAddrA_r;
RegAddrB <=
-- EX HL,DL
Alternate & "01" when ExchangeDH = '1' and TState = 3 else
-- Bus B
RegAddrB_r;
ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
signed(RegBusA) + 1;
process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegWEH <= '0';
RegWEL <= '0';
if (TState = 1 and Save_ALU_r = '0') or
(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
case Read_To_Reg_r is
when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
RegWEH <= not Read_To_Reg_r(0);
RegWEL <= Read_To_Reg_r(0);
when others =>
end case;
end if;
if ExchangeDH = '1' and (TState = 3 or TState = 4) then
RegWEH <= '1';
RegWEL <= '1';
end if;
if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
case IncDec_16(1 downto 0) is
when "00" | "01" | "10" =>
RegWEH <= '1';
RegWEL <= '1';
when others =>
end case;
end if;
end process;
process (Save_Mux, RegBusB, RegBusA_r, ID16,
ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
begin
RegDIH <= Save_Mux;
RegDIL <= Save_Mux;
if ExchangeDH = '1' and TState = 3 then
RegDIH <= RegBusB(15 downto 8);
RegDIL <= RegBusB(7 downto 0);
end if;
if ExchangeDH = '1' and TState = 4 then
RegDIH <= RegBusA_r(15 downto 8);
RegDIL <= RegBusA_r(7 downto 0);
end if;
if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
RegDIH <= std_logic_vector(ID16(15 downto 8));
RegDIL <= std_logic_vector(ID16(7 downto 0));
end if;
end process;
Regs : T80_Reg
port map(
Clk => CLK_n,
CEN => ClkEn,
WEH => RegWEH,
WEL => RegWEL,
AddrA => RegAddrA,
AddrB => RegAddrB,
AddrC => RegAddrC,
DIH => RegDIH,
DIL => RegDIL,
DOAH => RegBusA(15 downto 8),
DOAL => RegBusA(7 downto 0),
DOBH => RegBusB(15 downto 8),
DOBL => RegBusB(7 downto 0),
DOCH => RegBusC(15 downto 8),
DOCL => RegBusC(7 downto 0));
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (CLK_n)
begin
if CLK_n'event and CLK_n = '1' then
if ClkEn = '1' then
case Set_BusB_To is
when "0111" =>
BusB <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusB_To(0) = '1' then
BusB <= RegBusB(7 downto 0);
else
BusB <= RegBusB(15 downto 8);
end if;
when "0110" =>
BusB <= DI_Reg;
when "1000" =>
BusB <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusB <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusB <= "00000001";
when "1011" =>
BusB <= F;
when "1100" =>
BusB <= std_logic_vector(PC(7 downto 0));
when "1101" =>
BusB <= std_logic_vector(PC(15 downto 8));
when "1110" =>
BusB <= "00000000";
when others =>
BusB <= "--------";
end case;
case Set_BusA_To is
when "0111" =>
BusA <= ACC;
when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
if Set_BusA_To(0) = '1' then
BusA <= RegBusA(7 downto 0);
else
BusA <= RegBusA(15 downto 8);
end if;
when "0110" =>
BusA <= DI_Reg;
when "1000" =>
BusA <= std_logic_vector(SP(7 downto 0));
when "1001" =>
BusA <= std_logic_vector(SP(15 downto 8));
when "1010" =>
BusA <= "00000000";
when others =>
BusA <= "--------";
end case;
if XYbit_undoc='1' then
BusA <= DI_Reg;
BusB <= DI_Reg;
end if;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Generate external control signals
--
---------------------------------------------------------------------------
process (RESET_n,CLK_n)
begin
if RESET_n = '0' then
RFSH_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
if MCycle = "001" and ((TState = 2 and Wait_n = '1') or TState = 3) then
RFSH_n <= '0';
else
RFSH_n <= '1';
end if;
end if;
end if;
end process;
MC <= std_logic_vector(MCycle);
TS <= std_logic_vector(TState);
DI_Reg <= DI;
HALT_n <= not Halt_FF;
BUSAK_n <= not BusAck;
IntCycle_n <= not IntCycle;
IntE <= IntE_FF1;
IORQ <= IORQ_i;
Stop <= I_DJNZ;
-------------------------------------------------------------------------
--
-- Syncronise inputs
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
variable OldNMI_n : std_logic;
begin
if RESET_n = '0' then
BusReq_s <= '0';
INT_s <= '0';
NMI_s <= '0';
OldNMI_n := '0';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
BusReq_s <= not BUSRQ_n;
INT_s <= not INT_n;
if NMICycle = '1' then
NMI_s <= '0';
elsif NMI_n = '0' and OldNMI_n = '1' then
NMI_s <= '1';
end if;
OldNMI_n := NMI_n;
end if;
end if;
end process;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (RESET_n, CLK_n)
begin
if RESET_n = '0' then
MCycle <= "001";
TState <= "000";
Pre_XY_F_M <= "000";
Halt_FF <= '0';
BusAck <= '0';
NMICycle <= '0';
IntCycle <= '0';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
No_BTR <= '0';
Auto_Wait_t1 <= '0';
Auto_Wait_t2 <= '0';
M1_n <= '1';
elsif CLK_n'event and CLK_n = '1' then
if CEN = '1' then
Auto_Wait_t1 <= Auto_Wait;
Auto_Wait_t2 <= Auto_Wait_t1;
No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
(I_BTR and (not IR(4) or F(Flag_Z)));
if TState = 2 then
if SetEI = '1' then
IntE_FF1 <= '1';
IntE_FF2 <= '1';
end if;
if I_RETN = '1' then
IntE_FF1 <= IntE_FF2;
end if;
end if;
if TState = 3 then
if SetDI = '1' then
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
end if;
if IntCycle = '1' or NMICycle = '1' then
Halt_FF <= '0';
end if;
if MCycle = "001" and TState = 2 and Wait_n = '1' then
M1_n <= '1';
end if;
if BusReq_s = '1' and BusAck = '1' then
else
BusAck <= '0';
if TState = 2 and Wait_n = '0' then
elsif T_Res = '1' then
if Halt = '1' then
Halt_FF <= '1';
end if;
if BusReq_s = '1' then
BusAck <= '1';
else
TState <= "001";
if NextIs_XY_Fetch = '1' then
MCycle <= "110";
Pre_XY_F_M <= MCycle;
if IR = "00110110" and Mode = 0 then
Pre_XY_F_M <= "010";
end if;
elsif (MCycle = "111") or
(MCycle = "110" and Mode = 1 and ISet /= "01") then
MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
elsif (MCycle = MCycles) or
No_BTR = '1' or
(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
M1_n <= '0';
MCycle <= "001";
IntCycle <= '0';
NMICycle <= '0';
if NMI_s = '1' and Prefix = "00" then
NMICycle <= '1';
IntE_FF1 <= '0';
elsif (IntE_FF1 = '1' and INT_s = '1') and Prefix = "00" and SetEI = '0' then
IntCycle <= '1';
IntE_FF1 <= '0';
IntE_FF2 <= '0';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
end if;
else
if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
TState <= TState + 1;
end if;
end if;
end if;
if TState = 0 then
M1_n <= '0';
end if;
end if;
end if;
end process;
process (IntCycle, NMICycle, MCycle)
begin
Auto_Wait <= '0';
if IntCycle = '1' or NMICycle = '1' then
if MCycle = "001" then
Auto_Wait <= '1';
end if;
end if;
end process;
end;
|
-- NEED RESULT: ENT00200: Wait statement longest static prefix check passed
-- NEED RESULT: P1: Wait longest static prefix test completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00200
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.1 (5)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00200(ARCH00200)
-- ENT00200_Test_Bench(ARCH00200_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00200 is
generic (G : integer) ;
--
constant CG : integer := G+1;
attribute attr : integer ;
attribute attr of CG : constant is CG+1;
--
end ENT00200 ;
--
--
architecture ARCH00200 of ENT00200 is
signal s_st_int1 : st_int1
:= c_st_int1_1 ;
--
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_int1 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_int1 : inout st_int1
; variable counter : inout integer
; variable correct : inout boolean
; variable savtime : inout time
; signal chk_st_int1 : out chk_sig_type
)
is
begin
case counter is
when 0
=>
s_st_int1 <= transport
c_st_int1_2 after 10 ns ;
wait until s_st_int1 =
c_st_int1_2 ;
Test_Report (
"ENT00200",
"Wait statement longest static prefix check",
((savtime + 10 ns) = Std.Standard.Now) and
(s_st_int1 =
c_st_int1_2 )) ;
--
when others
=> wait ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time := 0 ns ;
begin
Proc1 (
s_st_int1
, counter
, correct
, savtime
, chk_st_int1
) ;
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_int1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Wait longest static prefix test completed",
chk_st_int1 = 0 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
end ARCH00200 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00200_Test_Bench is
end ENT00200_Test_Bench ;
--
--
architecture ARCH00200_Test_Bench of ENT00200_Test_Bench is
begin
L1:
block
component UUT
generic (G : integer) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00200 ( ARCH00200 ) ;
begin
CIS1 : UUT
generic map (lowb+2)
;
end block L1 ;
end ARCH00200_Test_Bench ;
|
-- NEED RESULT: ARCH00369.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00369: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00369: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00369
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (2)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00369(ARCH00369)
-- ENT00369_Test_Bench(ARCH00369_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00369 is
port (
s_st_rec3 : inout st_rec3
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
end ENT00369 ;
--
--
architecture ARCH00369 of ENT00369 is
subtype chk_time_type is Time ;
signal s_st_rec3_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_rec3_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_rec3_select : select_type := 1 ;
--
begin
CHG1 :
process ( s_st_rec3 )
variable correct : boolean ;
begin
case s_st_rec3_cnt is
when 0
=> null ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00369.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_rec3_select <= transport 2 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_2.f3(lowb,true) after 10 ns ,
-- c_st_rec3_1.f3(lowb,true) after 20 ns ,
-- c_st_rec3_2.f3(lowb,true) after 30 ns ,
-- c_st_rec3_1.f3(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f3(lowb,true) =
c_st_rec3_2.f3(lowb,true) and
(s_st_rec3_savt + 10 ns) = Std.Standard.Now ;
st_rec3_select <= transport 3 ;
-- s_st_rec3.f3(lowb,true) <= transport
-- c_st_rec3_1.f3(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f3(lowb,true) =
c_st_rec3_1.f3(lowb,true) and
(s_st_rec3_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00369" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00369" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00369" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
s_st_rec3_savt <= transport Std.Standard.Now ;
chk_st_rec3 <= transport s_st_rec3_cnt
after (1 us - Std.Standard.Now) ;
s_st_rec3_cnt <= transport s_st_rec3_cnt + 1 ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_rec3 = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_rec3_select select
s_st_rec3.f3(lowb,true) <= transport
c_st_rec3_2.f3(lowb,true) after 10 ns,
c_st_rec3_1.f3(lowb,true) after 20 ns
when 1,
--
c_st_rec3_2.f3(lowb,true) after 10 ns ,
c_st_rec3_1.f3(lowb,true) after 20 ns ,
c_st_rec3_2.f3(lowb,true) after 30 ns ,
c_st_rec3_1.f3(lowb,true) after 40 ns
when 2,
--
c_st_rec3_1.f3(lowb,true) after 5 ns when 3 ;
--
end ARCH00369 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00369_Test_Bench is
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
end ENT00369_Test_Bench ;
--
--
architecture ARCH00369_Test_Bench of ENT00369_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_rec3 : inout st_rec3
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00369 ( ARCH00369 ) ;
begin
CIS1 : UUT
port map (
s_st_rec3
)
;
end block L1 ;
end ARCH00369_Test_Bench ;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
procedure write ( file f : file_type; value : in element_type );
-- end of code from book
procedure write ( file f : file_type; value : in element_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
procedure write ( file f : file_type; value : in element_type );
-- end of code from book
procedure write ( file f : file_type; value : in element_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_03 is
end entity inline_03;
----------------------------------------------------------------
architecture test of inline_03 is
begin
process is
type element_type is (t1, t2, t3);
type file_type is file of element_type;
-- code from book:
procedure write ( file f : file_type; value : in element_type );
-- end of code from book
procedure write ( file f : file_type; value : in element_type ) is
begin
end;
begin
wait;
end process;
end architecture test;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Apr 5 12:50:28 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.1 2006/04/10 15:42:11 wig Exp $
-- $Date: 2006/04/10 15:42:11 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2006/04/10 15:42:11 wig
-- Updated testcase (__TOP__)
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.44 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa_i : inst_xa_e
use configuration work.inst_xa_e_rtl_conf;
end for;
for inst_ab_i : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous ROM; MIPS executable defined as constant, word-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity fpga_ROM is
generic (LOAD_FILE_NAME : string := "prog.bin"); -- not used with FPGA
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
strobe : in std_logic;
addr : in reg32;
data : out reg32);
constant INST_ADDRS_BITS : natural := log2_ceil(INST_MEM_SZ);
subtype rom_address is natural range 0 to ((INST_MEM_SZ / 4) - 1);
end entity fpga_ROM;
architecture rtl of fpga_ROM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component single_port_rom is
generic (N_WORDS : integer);
port (address : in rom_address;
clken : in std_logic;
clock : in std_logic;
q : out std_logic_vector);
end component single_port_rom;
signal instrn : reg32;
signal index : rom_address := 0;
signal waiting, clken : std_logic;
begin -- rtl
U_BUS_WAIT: wait_states generic map (ROM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
clken <= not(sel);
-- >>2 = /4: byte addressed but word indexed
index <= to_integer(unsigned(addr((INST_ADDRS_BITS-1) downto 2)));
U_ROM: single_port_rom generic map (INST_MEM_SZ / 4)
port map (index, clken, strobe, instrn);
U_ROM_ACCESS: process (strobe,instrn,sel)
begin
if sel = '0' then
data <= instrn;
assert (index >= 0) and (index < INST_MEM_SZ/4)
report "rom index out of bounds: " & natural'image(index)
severity failure;
-- assert false -- DEBUG
-- report "romRD["& natural'image(index) &"]="& SLV32HEX(data);
else
data <= (others => 'X');
end if;
end process U_ROM_ACCESS;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Adapted from Altera's design for a ROM that may be synthesized
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.p_wires.all;
entity single_port_rom is
generic (N_WORDS : integer := 32);
port (address : in natural range 0 to (N_WORDS - 1);
clken : in std_logic;
clock : in std_logic;
q : out reg32);
end entity;
architecture rtl of single_port_rom is
-- Build a 2-D array type for the RoM
subtype word_t is std_logic_vector(31 downto 0);
type memory_t is array(0 to (N_WORDS-1)) of word_t;
-- assemble.sh -v mac_lcd.s |\
-- sed -e '1,6d' -e '/^$/d' -e '/^ /!d' -e 's:\t: :g' \
-- -e 's#\(^ *[a-f0-9]*:\) *\(........\) *\(.*\)$#x"\2", -- \1 \3#' \
-- -e '$s:,: :'
constant test_prog : memory_t := (
x"00000000", -- 0: nop
x"3c0f0f00", -- 4: lui $15,0xf00
x"35ef0120", -- 8: ori $15,$15,0x120
x"24100001", -- c: li $16,1
x"adf00000", -- 10: sw $16,0($15)
x"3c040009", -- 14: lui $4,0x9
x"34848968", -- 18: ori $4,$4,0x8968
x"0c0000b7", -- 1c: jal 2dc <delay>
x"00000000", -- 20: nop
x"3c1a0f00", -- 24: lui $26,0xf00
x"375a0160", -- 28: ori $26,$26,0x160
x"24130030", -- 2c: li $19,48
x"af530000", -- 30: sw $19,0($26)
x"24040177", -- 34: li $4,375
x"0c0000b7", -- 38: jal 2dc <delay>
x"00000000", -- 3c: nop
x"24130030", -- 40: li $19,48
x"af530000", -- 44: sw $19,0($26)
x"24040177", -- 48: li $4,375
x"0c0000b7", -- 4c: jal 2dc <delay>
x"00000000", -- 50: nop
x"24130039", -- 54: li $19,57
x"af530000", -- 58: sw $19,0($26)
x"24040177", -- 5c: li $4,375
x"0c0000b7", -- 60: jal 2dc <delay>
x"00000000", -- 64: nop
x"24130014", -- 68: li $19,20
x"af530000", -- 6c: sw $19,0($26)
x"24040177", -- 70: li $4,375
x"0c0000b7", -- 74: jal 2dc <delay>
x"00000000", -- 78: nop
x"24130070", -- 7c: li $19,112
x"af530000", -- 80: sw $19,0($26)
x"24040177", -- 84: li $4,375
x"0c0000b7", -- 88: jal 2dc <delay>
x"00000000", -- 8c: nop
x"24130056", -- 90: li $19,86
x"af530000", -- 94: sw $19,0($26)
x"24040177", -- 98: li $4,375
x"0c0000b7", -- 9c: jal 2dc <delay>
x"00000000", -- a0: nop
x"2413006d", -- a4: li $19,109
x"af530000", -- a8: sw $19,0($26)
x"24040177", -- ac: li $4,375
x"0c0000b7", -- b0: jal 2dc <delay>
x"00000000", -- b4: nop
x"24100002", -- b8: li $16,2
x"adf00000", -- bc: sw $16,0($15)
x"3c0400be", -- c0: lui $4,0xbe
x"3484bc20", -- c4: ori $4,$4,0xbc20
x"0c0000b7", -- c8: jal 2dc <delay>
x"00000000", -- cc: nop
x"3c040026", -- d0: lui $4,0x26
x"348425a0", -- d4: ori $4,$4,0x25a0
x"0c0000b7", -- d8: jal 2dc <delay>
x"00000000", -- dc: nop
x"24100003", -- e0: li $16,3
x"adf00000", -- e4: sw $16,0($15)
x"3c0400be", -- e8: lui $4,0xbe
x"3484bc20", -- ec: ori $4,$4,0xbc20
x"0c0000b7", -- f0: jal 2dc <delay>
x"00000000", -- f4: nop
x"3c1a0f00", -- f8: lui $26,0xf00
x"375a0160", -- fc: ori $26,$26,0x160
x"2413000f", -- 100: li $19,15
x"af530000", -- 104: sw $19,0($26)
x"24040177", -- 108: li $4,375
x"0c0000b7", -- 10c: jal 2dc <delay>
x"00000000", -- 110: nop
x"24130006", -- 114: li $19,6
x"af530000", -- 118: sw $19,0($26)
x"24040177", -- 11c: li $4,375
x"0c0000b7", -- 120: jal 2dc <delay>
x"00000000", -- 124: nop
x"24100004", -- 128: li $16,4
x"adf00000", -- 12c: sw $16,0($15)
x"3c0400be", -- 130: lui $4,0xbe
x"3484bc20", -- 134: ori $4,$4,0xbc20
x"0c0000b7", -- 138: jal 2dc <delay>
x"00000000", -- 13c: nop
x"24130001", -- 140: li $19,1
x"af530000", -- 144: sw $19,0($26)
x"24040177", -- 148: li $4,375
x"0c0000b7", -- 14c: jal 2dc <delay>
x"00000000", -- 150: nop
x"24130080", -- 154: li $19,128
x"af530000", -- 158: sw $19,0($26)
x"24040177", -- 15c: li $4,375
x"0c0000b7", -- 160: jal 2dc <delay>
x"00000000", -- 164: nop
x"24100005", -- 168: li $16,5
x"adf00000", -- 16c: sw $16,0($15)
x"3c0400be", -- 170: lui $4,0xbe
x"3484bc20", -- 174: ori $4,$4,0xbc20
x"0c0000b7", -- 178: jal 2dc <delay>
x"00000000", -- 17c: nop
x"8f530000", -- 180: lw $19,0($26)
x"00000000", -- 184: nop
x"32730080", -- 188: andi $19,$19,0x80
x"1660fffc", -- 18c: bnez $19,180 <check>
x"00000000", -- 190: nop
x"02608021", -- 194: move $16,$19
x"adf00000", -- 198: sw $16,0($15)
x"3c0400be", -- 19c: lui $4,0xbe
x"3484bc20", -- 1a0: ori $4,$4,0xbc20
x"0c0000b7", -- 1a4: jal 2dc <delay>
x"00000000", -- 1a8: nop
x"24130080", -- 1ac: li $19,128
x"af530000", -- 1b0: sw $19,0($26)
x"24040177", -- 1b4: li $4,375
x"0c0000b7", -- 1b8: jal 2dc <delay>
x"00000000", -- 1bc: nop
x"3c046c6c", -- 1c0: lui $4,0x6c6c
x"34846548", -- 1c4: ori $4,$4,0x6548
x"0c000097", -- 1c8: jal 25c <send>
x"00000000", -- 1cc: nop
x"3c046f77", -- 1d0: lui $4,0x6f77
x"3484206f", -- 1d4: ori $4,$4,0x206f
x"0c000097", -- 1d8: jal 25c <send>
x"00000000", -- 1dc: nop
x"3c042164", -- 1e0: lui $4,0x2164
x"34846c72", -- 1e4: ori $4,$4,0x6c72
x"0c000097", -- 1e8: jal 25c <send>
x"00000000", -- 1ec: nop
x"24100007", -- 1f0: li $16,7
x"adf00000", -- 1f4: sw $16,0($15)
x"3c0400be", -- 1f8: lui $4,0xbe
x"3484bc20", -- 1fc: ori $4,$4,0xbc20
x"0c0000b7", -- 200: jal 2dc <delay>
x"00000000", -- 204: nop
x"241300c0", -- 208: li $19,192
x"af530000", -- 20c: sw $19,0($26)
x"24040177", -- 210: li $4,375
x"0c0000b7", -- 214: jal 2dc <delay>
x"00000000", -- 218: nop
x"3c046961", -- 21c: lui $4,0x6961
x"34847320", -- 220: ori $4,$4,0x7320
x"0c000097", -- 224: jal 25c <send>
x"00000000", -- 228: nop
x"3c044d63", -- 22c: lui $4,0x4d63
x"34842064", -- 230: ori $4,$4,0x2064
x"0c000097", -- 234: jal 25c <send>
x"00000000", -- 238: nop
x"3c042053", -- 23c: lui $4,0x2053
x"34845049", -- 240: ori $4,$4,0x5049
x"0c000097", -- 244: jal 25c <send>
x"00000000", -- 248: nop
x"24100008", -- 24c: li $16,8
x"adf00000", -- 250: sw $16,0($15)
x"08000095", -- 254: j 254 <end>
x"00000000", -- 258: nop
x"3c1a0f00", -- 25c: lui $26,0xf00
x"375a0160", -- 260: ori $26,$26,0x160
x"af440004", -- 264: sw $4,4($26)
x"00042202", -- 268: srl $4,$4,0x8
x"240500fa", -- 26c: li $5,250
x"24a5ffff", -- 270: addiu $5,$5,-1
x"00000000", -- 274: nop
x"14a0fffd", -- 278: bnez $5,270 <delay0>
x"00000000", -- 27c: nop
x"af440004", -- 280: sw $4,4($26)
x"00042202", -- 284: srl $4,$4,0x8
x"240500fa", -- 288: li $5,250
x"24a5ffff", -- 28c: addiu $5,$5,-1
x"00000000", -- 290: nop
x"14a0fffd", -- 294: bnez $5,28c <delay1>
x"00000000", -- 298: nop
x"af440004", -- 29c: sw $4,4($26)
x"00042202", -- 2a0: srl $4,$4,0x8
x"240500fa", -- 2a4: li $5,250
x"24a5ffff", -- 2a8: addiu $5,$5,-1
x"00000000", -- 2ac: nop
x"14a0fffd", -- 2b0: bnez $5,2a8 <delay2>
x"00000000", -- 2b4: nop
x"af440004", -- 2b8: sw $4,4($26)
x"00000000", -- 2bc: nop
x"240500fa", -- 2c0: li $5,250
x"24a5ffff", -- 2c4: addiu $5,$5,-1
x"00000000", -- 2c8: nop
x"14a0fffd", -- 2cc: bnez $5,2c4 <delay3>
x"00000000", -- 2d0: nop
x"03e00008", -- 2d4: jr $31
x"00000000", -- 2d8: nop
x"2484ffff", -- 2dc: addiu $4,$4,-1
x"00000000", -- 2e0: nop
x"1480fffd", -- 2e4: bnez $4,2dc <delay>
x"00000000", -- 2e8: nop
x"03e00008", -- 2ec: jr $31
x"00000000", -- 2f0: nop
x"00000000", -- 2f4: nop
x"00000000", -- 2f8: nop
x"00000000", -- 2fc: nop
x"00000000", -- 300: nop
x"00000000", -- 304: nop
x"00000000", -- 308: nop
x"00000000", -- 30c: nop
x"00000000", -- 310: nop
x"00000000", -- 314: nop
x"00000000", -- 318: nop
x"00000000", -- 31c: nop
x"00000000", -- 320: nop
x"00000000", -- 324: nop
x"00000000", -- 328: nop
x"00000000", -- 32c: nop
x"00000000", -- 330: nop
x"00000000", -- 334: nop
x"00000000", -- 338: nop
x"00000000", -- 33c: nop
x"00000000", -- 340: nop
x"00000000", -- 344: nop
x"00000000", -- 348: nop
x"00000000", -- 34c: nop
x"00000000", -- 350: nop
x"00000000", -- 354: nop
x"00000000", -- 358: nop
x"00000000", -- 35c: nop
x"00000000", -- 360: nop
x"00000000", -- 364: nop
x"00000000", -- 368: nop
x"00000000", -- 36c: nop
x"00000000", -- 370: nop
x"00000000", -- 374: nop
x"00000000", -- 378: nop
x"00000000", -- 37c: nop
x"00000000", -- 380: nop
x"00000000", -- 384: nop
x"00000000", -- 388: nop
x"00000000", -- 38c: nop
x"00000000", -- 390: nop
x"00000000", -- 394: nop
x"00000000", -- 398: nop
x"00000000", -- 39c: nop
x"00000000", -- 3a0: nop
x"00000000", -- 3a4: nop
x"00000000", -- 3a8: nop
x"00000000", -- 3ac: nop
x"00000000", -- 3b0: nop
x"00000000", -- 3b4: nop
x"00000000", -- 3b8: nop
x"00000000", -- 3bc: nop
x"00000000", -- 3c0: nop
x"00000000", -- 3c4: nop
x"00000000", -- 3c8: nop
x"00000000", -- 3cc: nop
x"00000000", -- 3d0: nop
x"00000000", -- 3d4: nop
x"00000000", -- 3d8: nop
x"00000000", -- 3dc: nop
x"00000000", -- 3e0: nop
x"00000000", -- 3e4: nop
x"00000000", -- 3e8: nop
x"00000000", -- 3ec: nop
x"00000000", -- 3f0: nop
x"00000000", -- 3f4: nop
x"00000000", -- 3f8: nop
x"00000000" -- 3fc: nop
);
function init_rom
return memory_t is
variable tmp : memory_t := (others => (others => '0'));
variable i_addr : integer;
begin
for addr_pos in test_prog'range loop
tmp(addr_pos) := test_prog(addr_pos);
-- i_addr := addr_pos;
end loop;
for addr_pos in test_prog'high to (N_WORDS - 1) loop
tmp(addr_pos) := x"00000000"; -- nop
end loop;
return tmp;
end init_rom;
-- Declare the ROM signal and specify a default value. Quartus II
-- will create a memory initialization file (ROM.mif) based on the
-- default value.
signal rom : memory_t := init_rom;
begin
process(clock,clken)
begin
if(clken = '1' and rising_edge(clock)) then
q <= rom(address);
end if;
end process;
end rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
--------------------------------------------------------------------------------
--This file is part of fpga_gpib_controller.
--
-- Fpga_gpib_controller is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- Fpga_gpib_controller is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with Fpga_gpib_controller. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Entity: if_func_T_TE
-- Date: 01:04:57 10/01/2011
-- Author: Andrzej Paluch
--------------------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.all;
use work.utilPkg.all;
entity if_func_T_TE is
port(
-- clock
clk : in std_logic; -- clock
-- function settings
isTE : in std_logic;
-- local instruction inputs
pon : in std_logic; -- power on
ton : in std_logic; -- talk only
endOf : in std_logic; -- end of byte string
-- state inputs
ACDS : in std_logic; -- accept data state (AH)
APRS : in std_logic; -- affirmative poll response
LPAS : in std_logic; -- listener primary state (LE)
-- remote instruction inputs
ATN : in std_logic; -- attention
IFC : in std_logic; -- interface clear
SPE : in std_logic; -- serial poll enable
SPD : in std_logic; -- serial poll disable
MTA : in std_logic; -- my talk address
OTA : in std_logic; -- other talk address
MLA : in std_logic; -- my listen address
OSA : in std_logic; -- other secondary address
MSA : in std_logic; -- my secondary address
PCG : in std_logic; -- primary command group
-- remote instruction outputs
END_OF : out std_logic; -- end of data
RQS : out std_logic; -- data accepted
DAB : out std_logic; -- data byte
EOS : out std_logic; -- end of string
STB : out std_logic; -- status byte
-- local instruction outputs
tac : out std_logic; -- talker active
-- reported states
SPAS : out std_logic; -- serial poll active state
TPAS : out std_logic; -- transmitter active state
TADS : out std_logic; -- talker addressed state
TACS : out std_logic -- talker active state
);
end if_func_T_TE;
architecture Behavioral of if_func_T_TE is
-- states
type T_STATE_1 is (
-- talker idle state
ST_TIDS,
-- talker addressed state
ST_TADS,
-- talker active state
ST_TACS,
-- serial poll active state
ST_SPAS
);
type T_STATE_2 is (
-- serial poll idle state
ST_SPIS,
-- seriall poll mode state
ST_SPMS
);
type T_STATE_3 is (
-- talker primary idle state
ST_TPIS,
-- talker primary addressed state
ST_TPAS
);
-- current state
signal current_state_1 : T_STATE_1;
signal current_state_2 : T_STATE_2;
signal current_state_3 : T_STATE_3;
-- events
signal event1_1, event1_2, event1_3, event1_4, event1_5, event1_6 : boolean;
signal event2_1, event2_2, event2_3 : boolean;
signal event3_1, event3_2, event3_3 : boolean;
begin
-- state machine process - T_STATE_1
process(pon, clk) begin
if pon = '1' then
current_state_1 <= ST_TIDS;
elsif rising_edge(clk) then
case current_state_1 is
------------------
when ST_TIDS =>
if event1_6 then
-- no state change
elsif event1_1 then
current_state_1 <= ST_TADS;
end if;
------------------
when ST_TADS =>
if event1_6 then
current_state_1 <= ST_TIDS;
elsif event1_2 then
current_state_1 <= ST_SPAS;
elsif event1_3 then
current_state_1 <= ST_TIDS;
elsif event1_4 then
current_state_1 <= ST_TACS;
end if;
------------------
when ST_SPAS =>
if event1_6 then
current_state_1 <= ST_TIDS;
elsif event1_5 then
current_state_1 <= ST_TADS;
end if;
------------------
when ST_TACS =>
if event1_6 then
current_state_1 <= ST_TIDS;
elsif event1_5 then
current_state_1 <= ST_TADS;
end if;
------------------
when others =>
current_state_1 <= ST_TIDS;
end case;
end if;
end process;
-- state machine process - T_STATE_2
process(pon, clk) begin
if pon = '1' then
current_state_2 <= ST_SPIS;
elsif rising_edge(clk) then
case current_state_2 is
------------------
when ST_SPIS =>
if event2_3 then
-- no state change
elsif event2_1 then
current_state_2 <= ST_SPMS;
end if;
------------------
when ST_SPMS =>
if event2_3 then
current_state_2 <= ST_SPIS;
elsif event2_2 then
current_state_2 <= ST_SPIS;
end if;
------------------
when others =>
current_state_2 <= ST_SPIS;
end case;
end if;
end process;
-- state machine process - T_STATE_3
process(pon, clk) begin
if pon = '1' then
current_state_3 <= ST_TPIS;
elsif rising_edge(clk) then
case current_state_3 is
------------------
when ST_TPIS =>
if event3_3 then
-- no state change
elsif event3_1 then
current_state_3 <= ST_TPAS;
end if;
------------------
when ST_TPAS =>
if event3_3 then
current_state_3 <= ST_TPIS;
elsif event3_2 then
current_state_3 <= ST_TPIS;
end if;
------------------
when others =>
current_state_3 <= ST_TPIS;
end case;
end if;
end process;
-- events
event1_1 <= is_1(
-- TE
(isTE and
(ton or (MSA and ACDS and to_stdl(current_state_3=ST_TPAS)))) or
-- T
(not isTE and
(ton or (MTA and ACDS)))
);
event1_2 <= ATN='0' and current_state_2=ST_SPMS;
event1_3 <=
-- TE
(isTE='1' and ((OTA='1' and ACDS='1') or
(OSA='1' and current_state_3=ST_TPAS and ACDS='1') or
(MSA='1' and LPAS='1' and ACDS='1'))) or
-- T
(isTE='0' and ((OTA='1' and ACDS='1') or (MLA='1' and ACDS='1')));
event1_4 <= ATN='0' and current_state_2/=ST_SPMS;
event1_5 <= ATN='1';
event1_6 <= IFC='1';
event2_1 <= SPE='1' and ACDS='1';
event2_2 <= SPD='1' and ACDS='1';
event2_3 <= IFC='1';
event3_1 <= MTA='1' and ACDS='1';
event3_2 <= PCG='1' and MTA='0' and ACDS='1';
event3_3 <= IFC='1';
-- TADS generator
with current_state_1 select
TADS <=
'1' when ST_TADS,
'0' when others;
-- TACS generator
with current_state_1 select
TACS <=
'1' when ST_TACS,
'0' when others;
-- DAB generator
with current_state_1 select
DAB <=
'1' when ST_TACS,
'0' when others;
-- EOS is kind of DAB
with current_state_1 select
EOS <=
'1' when ST_TACS,
'0' when others;
-- STB generator
with current_state_1 select
STB <=
'1' when ST_SPAS,
'0' when others;
-- SPAS generator
with current_state_1 select
SPAS <=
'1' when ST_SPAS,
'0' when others;
-- TPAS generator
with current_state_3 select
TPAS <=
'1' when ST_TPAS,
'0' when others;
-- tac generator
with current_state_1 select
tac <=
'1' when ST_TACS,
'0' when others;
-- END_OF generator
with current_state_1 select
END_OF <=
endOf when ST_TACS,
endOf when ST_SPAS,
'0' when others;
-- RQS generator
RQS <= APRS when current_state_1=ST_SPAS else '0';
end Behavioral;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity s420_nov is
port(
clock: in std_logic;
input: in std_logic_vector(18 downto 0);
output: out std_logic_vector(1 downto 0)
);
end s420_nov;
architecture behaviour of s420_nov is
constant s1111111111111111: std_logic_vector(4 downto 0) := "11111";
constant s0000000000000000: std_logic_vector(4 downto 0) := "00000";
constant s0001000000000000: std_logic_vector(4 downto 0) := "00011";
constant s0010000000000000: std_logic_vector(4 downto 0) := "00010";
constant s0011000000000000: std_logic_vector(4 downto 0) := "00101";
constant s0100000000000000: std_logic_vector(4 downto 0) := "00100";
constant s0101000000000000: std_logic_vector(4 downto 0) := "00111";
constant s0110000000000000: std_logic_vector(4 downto 0) := "00110";
constant s0111000000000000: std_logic_vector(4 downto 0) := "01001";
constant s1000000000000000: std_logic_vector(4 downto 0) := "01000";
constant s1001000000000000: std_logic_vector(4 downto 0) := "01011";
constant s1010000000000000: std_logic_vector(4 downto 0) := "01010";
constant s1011000000000000: std_logic_vector(4 downto 0) := "01101";
constant s1100000000000000: std_logic_vector(4 downto 0) := "01100";
constant s1101000000000000: std_logic_vector(4 downto 0) := "01111";
constant s1110000000000000: std_logic_vector(4 downto 0) := "01110";
constant s1111000000000000: std_logic_vector(4 downto 0) := "10111";
constant s0000000100000000: std_logic_vector(4 downto 0) := "00001";
signal current_state, next_state: std_logic_vector(4 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "-----"; output <= "--";
case current_state is
when s1111111111111111 =>
if std_match(input, "1----------------1-") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "1----------------00") then next_state <= s0000000000000000; output <= "10";
elsif std_match(input, "1----------------01") then next_state <= s0000000000000000; output <= "11";
elsif std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "10";
end if;
when s0000000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10----------------0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s0001000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0010000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0010000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0010000000000000; output <= "01";
end if;
when s0010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------0-0") then next_state <= s0011000000000000; output <= "00";
elsif std_match(input, "10--------------1-0") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s0011000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s0011000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s0100000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0100000000000000; output <= "00";
end if;
when s0100000000000000 =>
if std_match(input, "10----------------1") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s0101000000000000; output <= "00";
elsif std_match(input, "10-------------1--0") then next_state <= s0101000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------0--1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "-1-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-------------1---") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1---") then next_state <= s0000000000000000; output <= "01";
end if;
when s0101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------10") then next_state <= s0110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0110000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0110000000000000; output <= "01";
end if;
when s0110000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10--------------1--") then next_state <= s0111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s0111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s0111000000000000; output <= "01";
end if;
when s0111000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "10---------------1-") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------01") then next_state <= s1000000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1000000000000000; output <= "00";
end if;
when s1000000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------1---0") then next_state <= s1001000000000000; output <= "01";
elsif std_match(input, "10------------0---0") then next_state <= s1001000000000000; output <= "00";
elsif std_match(input, "01------------0---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------0---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------1---1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01------------1---1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11------------1---0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11------------0---0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1001000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1010000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1010000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
end if;
when s1010000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10--------------1--") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-1") then next_state <= s1011000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1011000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1-0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1011000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------00") then next_state <= s1100000000000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "10----------------1") then next_state <= s1100000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1100000000000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-------------0--1") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "10-------------0--0") then next_state <= s1101000000000000; output <= "00";
elsif std_match(input, "10-------------1---") then next_state <= s1101000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------1") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------0--0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-------------1--0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "01----------------0") then next_state <= s0000000000000000; output <= "00";
end if;
when s1101000000000000 =>
if std_match(input, "0------------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10---------------1-") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s1110000000000000; output <= "00";
elsif std_match(input, "10---------------01") then next_state <= s1110000000000000; output <= "01";
elsif std_match(input, "11---------------1-") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------01") then next_state <= s0000000000000000; output <= "01";
end if;
when s1110000000000000 =>
if std_match(input, "10--------------1--") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "10--------------0-0") then next_state <= s1111000000000000; output <= "00";
elsif std_match(input, "10--------------0-1") then next_state <= s1111000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------1--") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11--------------0-0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11--------------0-1") then next_state <= s0000000000000000; output <= "01";
end if;
when s1111000000000000 =>
if std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------00") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11---------------10") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "00-----------------") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10---------------10") then next_state <= s0000000100000000; output <= "01";
elsif std_match(input, "10---------------00") then next_state <= s0000000100000000; output <= "00";
elsif std_match(input, "10----------------1") then next_state <= s0000000100000000; output <= "01";
end if;
when s0000000100000000 =>
if std_match(input, "00-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "10-----------1-----") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "10-----------0----0") then next_state <= s0001000000000000; output <= "00";
elsif std_match(input, "10-----------0----1") then next_state <= s0001000000000000; output <= "01";
elsif std_match(input, "01-----------------") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11-----------1----0") then next_state <= s0000000000000000; output <= "01";
elsif std_match(input, "11-----------0----0") then next_state <= s0000000000000000; output <= "00";
elsif std_match(input, "11----------------1") then next_state <= s0000000000000000; output <= "01";
end if;
when others => next_state <= "-----"; output <= "--";
end case;
end process;
end behaviour;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/22/2014
--! Module Name: EPROC_IN4
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library ieee, work;
use ieee.std_logic_1164.ALL;
use work.all;
--! E-link processor, 4bit input
entity EPROC_IN4 is
generic (
do_generate : boolean := true;
includeNoEncodingCase : boolean := true
);
port (
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
ENA : in std_logic;
ENCODING : in std_logic_vector (1 downto 0);
EDATA_IN : in std_logic_vector (3 downto 0);
DATA_OUT : out std_logic_vector (9 downto 0);
DATA_RDY : out std_logic;
busyOut : out std_logic
);
end EPROC_IN4;
architecture Behavioral of EPROC_IN4 is
constant zeros10array : std_logic_vector (9 downto 0) := (others=>'0');
--
signal DATA_OUT_direct,DATA_OUT_8b10b_case,DATA_OUT_HDLC_case,DATA_OUT_s : std_logic_vector (9 downto 0);
signal DATA_RDY_direct,DATA_RDY_8b10b_case,DATA_RDY_HDLC_case,DATA_RDY_sig : std_logic;
---
signal RESTART_sig, rst_case00, rst_case01 : std_logic;
---
begin
gen_enabled: if do_generate = true generate
RESTART_sig <= rst or (not ENA); -- comes from clk40 domain
-------------------------------------------------------------------------------------------
-- ENCODING case "00": direct data, no delimeter...
-------------------------------------------------------------------------------------------
direct_data_enabled: if includeNoEncodingCase = true generate
rst_case00 <= RESTART_sig or (ENCODING(1) or ENCODING(0));
EPROC_IN4_direct_inst: entity work.EPROC_IN4_direct
port map(
bitCLK => bitCLK,
bitCLKx4 => bitCLKx4,
rst => rst_case00,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_direct,
dataOUTrdy => DATA_RDY_direct
);
end generate direct_data_enabled;
--
direct_data_disabled: if includeNoEncodingCase = false generate
DATA_RDY_direct <= '0';
DATA_OUT_direct <= (others=>'0');
end generate direct_data_disabled;
--
-------------------------------------------------------------------------------------------
-- ENCODING case "01": DEC8b10b
-------------------------------------------------------------------------------------------
rst_case01 <= RESTART_sig or (ENCODING(1) or (not ENCODING(0)));
--
EPROC_IN4_DEC8b10b_inst: entity work.EPROC_IN4_DEC8b10b
port map(
bitCLK => bitCLK,
bitCLKx2 => bitCLKx2,
bitCLKx4 => bitCLKx4,
rst => rst_case01,
edataIN => EDATA_IN,
dataOUT => DATA_OUT_8b10b_case,
dataOUTrdy => DATA_RDY_8b10b_case,
busyOut => busyOut
);
-------------------------------------------------------------------------------------------
-- ENCODING case "10": HDLC
-------------------------------------------------------------------------------------------
-- TBD
DATA_OUT_HDLC_case <= (others=>'0');
DATA_RDY_HDLC_case <= '0';
-------------------------------------------------------------------------------------------
-- output data/rdy according to the encoding settings
-------------------------------------------------------------------------------------------
DATA_OUT_MUX4_10bit: entity work.MUX4_Nbit
generic map(N=>10)
port map(
data0 => DATA_OUT_direct,
data1 => DATA_OUT_8b10b_case,
data2 => DATA_OUT_HDLC_case,
data3 => zeros10array,
sel => ENCODING,
data_out => DATA_OUT_s
);
DATA_RDY_MUX4: entity work.MUX4
port map(
data0 => DATA_RDY_direct,
data1 => DATA_RDY_8b10b_case,
data2 => DATA_RDY_HDLC_case,
data3 => '0',
sel => ENCODING,
data_out => DATA_RDY_sig
);
DATA_RDY <= DATA_RDY_sig;
DATA_OUT <= DATA_OUT_s;
--------------------
end generate gen_enabled;
--
--
gen_disabled: if do_generate = false generate
DATA_OUT <= (others=>'0');
DATA_RDY <= '0';
busyOut <= '0';
end generate gen_disabled;
end Behavioral;
|
------------------------------------------------------------------------------
-- Special configuration which disconnects the ParamOutReg modules, so that
-- we can drive the values with VHDL'2008 external names in the Reconf.Module
-- wrapper <app>-wrapreconfmodule.vhd.
------------------------------------------------------------------------------
configuration WrapReconfModule_cfg of MAX6682Mean_tb is
for behavior
for DUT : MAX6682Mean
for WrapReconfModule
for MyReconfigLogic_0 : MyReconfigLogic
for struct
for all : ParamOutReg
use entity work.ParamOutReg(rtl)
port map (
Reset_n_i => '0',
Clk_i => '0',
Enable_i => '0',
ParamWrData_i => (others => '0'),
Param_o => open
);
end for;
end for;
end for;
end for;
end for;
end for;
end WrapReconfModule_cfg;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 02/10/2017 11:07:04 AM
-- Design Name:
-- Module Name: Video_Box - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Video_Box is
generic (
-- Users to add parameters here
-- User parameters ends
-- Do not modify the parameters beyond this line
-- Width of S_AXI data bus
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of S_AXI address bus
C_S_AXI_ADDR_WIDTH : integer := 11
);
port (
S_AXI_ARESETN : in std_logic;
slv_reg_wren : in std_logic;
slv_reg_rden : in std_logic;
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
reg_data_out : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
--Bus Clock
S_AXI_ACLK : in std_logic;
--Video
RGB_IN : in std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_IN : in std_logic; -- Active video Flag (optional)
HS_IN : in std_logic; -- Horizontal sync signal (optional)
VS_IN : in std_logic; -- Veritcal sync signal (optional)
-- additional ports here
RGB_OUT : out std_logic_vector(23 downto 0); -- Parallel video data (required)
VDE_OUT : out std_logic; -- Active video Flag (optional)
HS_OUT : out std_logic; -- Horizontal sync signal (optional)
VS_OUT : out std_logic; -- Veritcal sync signal (optional)
PIXEL_CLK : in std_logic;
X_Coord : in std_logic_vector(15 downto 0);
Y_Coord : in std_logic_vector(15 downto 0)
);
end Video_Box;
architecture Behavioral of Video_Box is
attribute BLACK_BOX : string;
attribute BLACK_BOX of Behavioral: architecture is "TRUE";
begin
end Behavioral;
|
architecture RTL of FIFO is
begin
process IS
begin
end process;
-- Violations below
process IS
begin
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- decoder.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- Takes the opcode from the command received by the receiver and decodes it.
-- The decoded command will be executed for one cycle.
--
-- The receiver keeps the cmd output active long enough so all the
-- data is still available on its cmd output when the command has
-- been decoded and sent out to other modules with the next
-- clock cycle. (Maybe this paragraph should go in receiver.vhd?)
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port (
opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigval : out STD_LOGIC_VECTOR (3 downto 0);
wrtrigcfg : out STD_LOGIC_VECTOR (3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out STD_LOGIC;
wrFlags : out std_logic;
arm : out STD_LOGIC;
reset : out STD_LOGIC
);
end decoder;
architecture Behavioral of decoder is
signal exe, exeReg: std_logic;
begin
exe <= execute;
process(clock)
begin
if rising_edge(clock) then
reset <= '0'; arm <= '0';
wrspeed <= '0'; wrsize <= '0'; wrFlags <= '0';
wrtrigmask <= "0000"; wrtrigval <= "0000"; wrtrigcfg <= "0000";
if (exe and not exeReg) = '1' then
case opcode is
-- short commands
when x"00" => reset <= '1';
when x"01" => arm <= '1';
-- long commands
when x"80" => wrspeed <= '1';
when x"81" => wrsize <= '1';
when x"82" => wrFlags <= '1';
when x"C0" => wrtrigmask(0) <= '1';
when x"C1" => wrtrigval(0) <= '1';
when x"C2" => wrtrigcfg(0) <= '1';
when x"C4" => wrtrigmask(1) <= '1';
when x"C5" => wrtrigval(1) <= '1';
when x"C6" => wrtrigcfg(1) <= '1';
when x"C8" => wrtrigmask(2) <= '1';
when x"C9" => wrtrigval(2) <= '1';
when x"CA" => wrtrigcfg(2) <= '1';
when x"CC" => wrtrigmask(3) <= '1';
when x"CD" => wrtrigval(3) <= '1';
when x"CE" => wrtrigcfg(3) <= '1';
when others =>
end case;
end if;
exeReg <= exe;
end if;
end process;
end Behavioral;
|
entity record30 is
end entity;
architecture test of record30 is
type int_ptr is access integer;
type pair is record
x, y : natural;
end record;
type rec is record
x : bit_vector;
y : int_ptr;
z : pair;
end record;
begin
main: process is
variable s : rec(x(1 to 3));
begin
assert s.x = "000";
assert s = (x => "000", y => null, z => (0, 0));
s.x := "101";
assert s.x = "101";
assert s = (x => "101", y => null, z => (0, 0));
s := (x => "111", y => null, z => (0, 0));
assert s.x = "111";
assert s = (x => "111", y => null, z => (0, 0));
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: generic_ddr_phy
-- File: ddr_phy_inferred.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Modified: Magnus Hjorth - Aeroflex Gaisler
-- Description: Generic DDR PHY (simulation only)
------------------------------------------------------------------------------
--###################################################################################
-- Generic DDR1 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb: in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(nclk-1 downto 0);
moben : in std_logic -- Mobile DDR enable
);
end;
architecture rtl of generic_ddr_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
signal ckl: std_logic_vector(nclk-1 downto 0);
signal ckel: std_logic_vector(ncs-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl, rst)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' or rst='0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
-- For mobile SDRAM, force Cke high during reset and reset-delay,
-- For regular SDRAM, force Cke low
-- also disable outgoing clock until we have achieved PLL lock
mobgen: if mobile > 1 generate
ckel <= cke or (cke'range => not locked);
end generate;
nmobgen: if mobile < 2 generate
ckel <= cke and (cke'range => locked);
end generate;
ckl <= ck and (ck'range => lockl);
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2, ncs => ncs, nclk => nclk,
resync => 2 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => open,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba,
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => ckel,
odt => (others => '0'),
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ckl
);
end;
--###################################################################################
-- Generic DDR2 PHY
--###################################################################################
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library grlib;
use grlib.stdlib.all;
entity generic_ddr2_phy_wo_pads is
generic (MHz : integer := 100; rstdelay : integer := 200;
dbits : integer := 16; clk_mul : integer := 2 ;
clk_div : integer := 2; rskew : integer := 0;
eightbanks: integer := 0; abits: integer := 14;
cben: integer := 0; chkbits: integer := 8;
nclk: integer := 3; ncs: integer := 2);
port(
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clk0r : in std_ulogic; -- system clock returned
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0); -- ddr odt
addr : in std_logic_vector (abits-1 downto 0); -- data mask
ba : in std_logic_vector (2 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
odt : in std_logic_vector(1 downto 0)
);
end;
architecture rtl of generic_ddr2_phy_wo_pads is
component sim_pll
generic (
clkmul: integer := 1;
clkdiv1: integer := 1;
clkphase1: integer := 0;
clkdiv2: integer := 1;
clkphase2: integer := 0;
clkdiv3: integer := 1;
clkphase3: integer := 0;
clkdiv4: integer := 1;
clkphase4: integer := 0;
minfreq: integer := 0;
maxfreq: integer := 10000000
);
port (
i: in std_logic;
o1: out std_logic;
o2: out std_logic;
o3: out std_logic;
o4: out std_logic;
lock: out std_logic;
rst: in std_logic
);
end component;
constant freq_khz: integer := (1000*MHz*clk_mul)/(clk_div);
constant freq_mhz: integer := freq_khz / 1000;
constant td90: time := 250 us * (1.0 / real(freq_khz));
signal vcc, gnd : std_logic; -- VCC and GND
signal clk0, clk90r, clk180r, clk270r : std_ulogic;
signal lockl,vlockl,locked: std_ulogic;
signal dqs90,dqs90n: std_logic_vector(dbits/8-1 downto 0);
begin
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------------
-- Clock generation (Only for simulation)
-----------------------------------------------------------------------------------
-- Phase shifted clocks
--pragma translate_off
-- To avoid jitter problems when using ddr2 without sync regs we shift
-- 10 degrees extra.
pll0: sim_pll
generic map (
clkmul => clk_mul,
clkdiv1 => clk_div,
clkphase1 => 0-10+360,
clkdiv2 => clk_div,
clkphase2 => 90-10,
clkdiv3 => clk_div,
clkphase3 => 180-10,
clkdiv4 => clk_div,
clkphase4 => 270-10,
minfreq => MHz*1000,
maxfreq => MHz*1000
)
port map (
i => clk,
o1 => clk0,
o2 => clk90r,
o3 => clk180r,
o4 => clk270r,
lock => lockl,
rst => rst);
--pragma translate_on
-- Clock to DDR controller
clkout <= clk0;
ddr_clk_fb_out <= '0';
-----------------------------------------------------------------------------------
-- Lock delay
-----------------------------------------------------------------------------------
rdel : if rstdelay /= 0 generate
rcnt : process (clk0r, lockl)
variable cnt : std_logic_vector(15 downto 0);
variable vlock, co : std_ulogic;
begin
if rising_edge(clk0r) then
co := cnt(15);
vlockl <= vlock;
if lockl = '0' then
cnt := conv_std_logic_vector(rstdelay*FREQ_MHZ, 16); vlock := '0';
else
if vlock = '0' then
cnt := cnt -1; vlock := cnt(15) and not co;
end if;
end if;
end if;
if lockl = '0' then
vlock := '0';
end if;
end process;
end generate;
locked <= lockl when rstdelay = 0 else vlockl;
lock <= locked;
-----------------------------------------------------------------------------
-- DQS shifting
-----------------------------------------------------------------------------
-- pragma translate_off
dqs90 <= transport ddr_dqs_in after td90;
dqs90n <= not dqs90;
-- pragma translate_on
-----------------------------------------------------------------------------
-- Data path
-----------------------------------------------------------------------------
dp0: ddrphy_datapath
generic map (
regtech => inferred, dbits => dbits, abits => abits,
bankbits => 2+EIGHTBANKS, ncs => ncs, nclk => nclk,
resync => 0 )
port map (
clk0 => clk0r,
clk90 => clk90r,
clk180 => clk180r,
clk270 => clk270r,
clkresync => gnd,
ddr_clk => ddr_clk,
ddr_clkb => ddr_clkb,
ddr_dq_in => ddr_dq_in,
ddr_dq_out => ddr_dq_out,
ddr_dq_oen => ddr_dq_oen,
ddr_dqs_in90 => dqs90,
ddr_dqs_in90n => dqs90n,
ddr_dqs_out => ddr_dqs_out,
ddr_dqs_oen => ddr_dqs_oen,
ddr_cke => ddr_cke,
ddr_csb => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dm => ddr_dm,
ddr_odt => ddr_odt,
dqin => dqin,
dqout => dqout,
addr => addr,
ba => ba(1+eightbanks downto 0),
dm => dm,
oen => oen,
rasn => rasn,
casn => casn,
wen => wen,
csn => csn,
cke => cke,
odt => odt,
dqs_en => dqs,
dqs_oen => dqsoen,
ddrclk_en => ck(nclk-1 downto 0)
);
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity var02 is
port (clk : std_logic;
mask : std_logic_vector (3 downto 0);
val : std_logic_vector (31 downto 0);
res : out std_logic_vector (31 downto 0));
end var02;
architecture behav of var02 is
signal r : std_logic_vector (31 downto 0) := (others => '0');
signal r_up : std_logic_vector (31 downto 0) := (others => '0');
begin
process (all)
variable t : std_logic_vector (31 downto 0) := (others => '0');
variable hi, lo : natural;
begin
t := r;
for i in 0 to 3 loop
if mask (i) = '1' then
lo := i * 8;
hi := lo + 7;
t (hi downto lo) := val (hi downto lo);
end if;
end loop;
r_up <= t;
end process;
process (clk)
begin
if rising_edge (clk) then
r <= r_up;
end if;
end process;
res <= r;
end behav;
|
-- **********************************************
-- * Autómata finito (máquina de estado finito) *
-- **********************************************
library ieee;
use ieee.std_logic_1164.all;
entity ej_af is
port(
clk, rst: in std_logic;
a, b: in std_logic;
y0, y1: out std_logic
);
end ej_af;
architecture arq_dos_seg of ej_af is
type tipo_est_ej is (s0, s1, s2); -- Lista (enumera) los valores simbólicos
signal est_reg, est_sig: tipo_est_ej;
begin
-- Registro de estado
process(clk, rst)
begin
if (rst='0') then
est_reg <= s0;
elsif (clk'event and clk='1') then
est_reg <= est_sig;
end if;
end process;
-- Lógica del siguiente estado/salida
process(est_reg, a, b)
begin
est_sig <= est_reg; -- Volver al mismo estado por defecto
y0 <= '0'; -- Por defecto 0
y1 <= '0'; -- Por defecto 0
case est_reg is
when s0 =>
y1 <= '1';
if a='1' then
if b='1' then
est_sig <= s2;
y0 <= '1';
else
est_sig <= s1;
end if;
-- sin else ya que s0 se mantiene para a=0
end if;
when s1 =>
y1 <= '1';
if (a='1') then
est_sig <= s0;
-- sin else ya que s1 se mantiene para a=0
end if;
when s2 =>
est_sig <= s0;
end case;
end process;
end arq_dos_seg; |
entity t3 is
end t3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of t3 is
signal s : std_logic;
begin
b: block
port (p : out std_logic := '0');
port map (p => s);
begin
end block;
assert s = '0' severity failure;
end behav;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x1k_sp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 0
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 1024
-- C_READ_DEPTH_A : 1024
-- C_ADDRA_WIDTH : 10
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x1k_sp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x1k_sp_prod;
ARCHITECTURE xilinx OF ram_16x1k_sp_prod IS
COMPONENT ram_16x1k_sp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x1k_sp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA
);
END xilinx;
|
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