content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc211.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00211ent IS
END c03s01b00x00p09n01i00211ent;
ARCHITECTURE c03s01b00x00p09n01i00211arch OF c03s01b00x00p09n01i00211ent IS
type ascending_range is range 0 to 10 ;
type descending_range is range 10 downto 0 ;
subtype ascending_subrange is descending_range range 2 to 5 ;
subtype descending_subrange is ascending_range range 5 downto 2 ;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2))
report "***PASSED TEST: c03s01b00x00p09n01i00211"
severity NOTE;
assert ((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2))
report "***FAILED TEST: c03s01b00x00p09n01i00211 - The type of expression is not the same as the base type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00211arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc211.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00211ent IS
END c03s01b00x00p09n01i00211ent;
ARCHITECTURE c03s01b00x00p09n01i00211arch OF c03s01b00x00p09n01i00211ent IS
type ascending_range is range 0 to 10 ;
type descending_range is range 10 downto 0 ;
subtype ascending_subrange is descending_range range 2 to 5 ;
subtype descending_subrange is ascending_range range 5 downto 2 ;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2))
report "***PASSED TEST: c03s01b00x00p09n01i00211"
severity NOTE;
assert ((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2))
report "***FAILED TEST: c03s01b00x00p09n01i00211 - The type of expression is not the same as the base type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00211arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc211.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b00x00p09n01i00211ent IS
END c03s01b00x00p09n01i00211ent;
ARCHITECTURE c03s01b00x00p09n01i00211arch OF c03s01b00x00p09n01i00211ent IS
type ascending_range is range 0 to 10 ;
type descending_range is range 10 downto 0 ;
subtype ascending_subrange is descending_range range 2 to 5 ;
subtype descending_subrange is ascending_range range 5 downto 2 ;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2))
report "***PASSED TEST: c03s01b00x00p09n01i00211"
severity NOTE;
assert ((ascending_range'left = 0) and(descending_range'left = 10) and(ascending_subrange'right = 5) and (descending_subrange'right = 2))
report "***FAILED TEST: c03s01b00x00p09n01i00211 - The type of expression is not the same as the base type."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b00x00p09n01i00211arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:32:02 04/01/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/disp_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: header_display
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY disp_test IS
END disp_test;
ARCHITECTURE behavior OF disp_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT header_display
PORT(
char : OUT std_logic_vector(7 downto 0);
char_we : OUT std_logic;
clk : IN std_logic;
ram_clk : OUT std_logic;
ram_enable : OUT std_logic;
ram_output : IN std_logic_vector(7 downto 0);
start : IN std_logic;
reset : IN std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal ram_output : std_logic_vector(7 downto 0) := (others => '0');
signal start : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal char : std_logic_vector(7 downto 0);
signal char_we : std_logic;
signal ram_clk : std_logic;
signal ram_enable : std_logic;
-- Clock period definitions
constant clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: header_display PORT MAP (
char => char,
char_we => char_we,
clk => clk,
ram_clk => ram_clk,
ram_enable => ram_enable,
ram_output => ram_output,
start => start,
reset => reset
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
start <= '0', '1' after 50 ns, '0' after 100 ns;
END;
|
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';
concurrent_wr_en_b <= '0' when rd_en = '1' ELSE '1';
end architecture rtl;
|
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- Engineer: Darci Luiz Tomasi Junior
-- E-mail: dltj007@gmail.com
-- Date : 25/06/2015 - 19:35
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY CTRL IS
PORT(
OPCode : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
RegDst : OUT STD_LOGIC;
Jump : OUT STD_LOGIC;
Branch : OUT STD_LOGIC;
MemRead : OUT STD_LOGIC;
MemtoReg : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
ALUOp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
MemWrite : OUT STD_LOGIC;
ALUSrc : OUT STD_LOGIC;
RegWrite : OUT STD_LOGIC
);
END CTRL;
ARCHITECTURE ARC_CTRL OF CTRL IS
BEGIN
PROCESS(OPCode)
BEGIN
CASE OPCode IS
--TYPE R
WHEN "000000" => RegDst <= '1';
Jump <= '0';
ALUSrc <= '0';
MemtoReg <= "00";
RegWrite <= '1';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
ALUOp(1) <= '1';
ALUOp(0) <= '0';
--TYPE LW
WHEN "100011" => RegDst <= '0';
Jump <= '0';
ALUSrc <= '1';
MemtoReg <= "01";
RegWrite <= '1';
MemRead <= '1';
MemWrite <= '0';
Branch <= '0';
ALUOp(1) <= '0';
ALUOp(0) <= '0';
--TYPE SW
WHEN "101011" => RegDst <= '0'; --X
Jump <= '0';
ALUSrc <= '1';
MemtoReg <= "00"; --X
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '1';
Branch <= '0';
ALUOp(1) <= '0';
ALUOp(0) <= '0';
--TYPE LUI
WHEN "001111" => RegDst <= '0'; --X
Jump <= '0';
ALUSrc <= '0'; --X
MemtoReg <= "10";
RegWrite <= '1';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
ALUOp(1) <= '0'; --X
ALUOp(0) <= '0'; --X
--TYPE ADDI
WHEN "001000" => RegDst <= '0'; --X
Jump <= '0';
ALUSrc <= '1'; --X
MemtoReg <= "00";
RegWrite <= '1';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
ALUOp(1) <= '0';
ALUOp(0) <= '0';
--TYPE JUMP
WHEN "000010" => RegDst <= '0'; --X
Jump <= '1';
ALUSrc <= '0';
MemtoReg <= "00"; --X
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '0';
ALUOp(1) <= '1';
ALUOp(0) <= '0';
--TYPE BEQ
--TYPE BEQ
WHEN OTHERS => RegDst <= '0'; --X
Jump <= '0';
ALUSrc <= '0';
MemtoReg <= "00"; --X
RegWrite <= '0';
MemRead <= '0';
MemWrite <= '0';
Branch <= '1';
ALUOp(1) <= '0';
ALUOp(0) <= '1';
END CASE;
END PROCESS;
END ARC_CTRL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2139.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02139ent IS
END c07s02b04x00p21n01i02139ent;
ARCHITECTURE c07s02b04x00p21n01i02139arch OF c07s02b04x00p21n01i02139ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive_null;
variable r_operand : positive := 1 ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02139"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02139 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02139arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2139.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02139ent IS
END c07s02b04x00p21n01i02139ent;
ARCHITECTURE c07s02b04x00p21n01i02139arch OF c07s02b04x00p21n01i02139ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive_null;
variable r_operand : positive := 1 ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02139"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02139 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02139arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2139.vhd,v 1.2 2001-10-26 16:29:46 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p21n01i02139ent IS
END c07s02b04x00p21n01i02139ent;
ARCHITECTURE c07s02b04x00p21n01i02139arch OF c07s02b04x00p21n01i02139ent IS
TYPE positive_v is array (integer range <>) of positive;
SUBTYPE positive_1 is positive_v (1 to 1);
SUBTYPE positive_null is positive_v (1 to 0);
BEGIN
TESTING: PROCESS
variable result : positive_1;
variable l_operand : positive_null;
variable r_operand : positive := 1 ;
BEGIN
--
-- The element is treated as an implicit single element array !
--
result := l_operand & r_operand;
wait for 5 ns;
assert NOT( result(1) = 1 )
report "***PASSED TEST: c07s02b04x00p21n01i02139"
severity NOTE;
assert ( result(1) = 1 )
report "***FAILED TEST: c07s02b04x00p21n01i02139 - Concatenation of null and POSITIVE element failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p21n01i02139arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QLOOoKlGeTs3w0jXG0JqRwtHZ6ZjMLpVm5gbg83RVaMB6qCMyHD5NAuvGh/R1T6ZlQp0NMh7Bnk2
5AdHD7cJjA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oiLZfYUeAPLDA1mPt1oWE8FJuiWI9nQq70AHCVDv7/+/ko3oL+RM55qvzg78ir0IIow9o1QQnZzi
/QnPM3je+PmrMbklYC8hbnc/6WwoYTDYWBjwmnT4WuTu79zT5Dz2iwvQ7UO87XDo6Vccxhk/KNba
ZrIF5dUtbh9SBfEo1pc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHdof/KFp2koF/o91nEi7LW4+89e3FRu/nu4NfaWjoFf23t/IPwz0N/ZySSZXeZj7NpcOCWZtivU
DSFNkcNUoxn1xhwZjydQXsRPzt7zggpp1RwvhW+chmFxHP6jaXMEqUkO5g6sEZrtVQtnMb5nqceA
2nqbftFy9y4Jt7UmohJJDYMVVeIXLbWZ+sM9wnfgB7VManZH1vBNIzUmC7EzVRugcadqTAPkQuML
c+Zvth8zYTGwbqF7L7DymzQB8U0Jap19ompCBbL4q3fT1HLAOoCqWtUDTR7MfugbLBGTA07mp/hW
apZVGF7Ua5AJ+LWqKRW3am2rKk+mVP16uzjX2g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cQW6+AQd3QOZ1YlcrM/LQugKHjz+MqOUuR5a7MVb+w/h0VQ2EpwCS5QaTg5R6MyncLujB8RUugJT
TvCpchFxnZKs10+1mFZC2KrxQFUIaFzvxV/edf3kLHqviBvAcROXFgSetBEx4AKxc/qvQlm8TYvH
FrL3s45jp51A+vkmnio=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nKmftmxJaLdDTM8ApbRpeOSEHVHDWxzh224hvKHxX106ZVfuSqNl6gPbiSpYnnR+hX/i6n0KWBzO
TP+ubtn7uZgVs+/SfxIy3/Sdm0XgcPm9XNcKemx6b5YMwbBewBHzaMu0r1SlSZZn1kPD1zp7f3Kq
IbDj+od/lSq1wO/ibX6+NVPKJDfdGA5UBJAJ9ilvb44fl5kcPiTZ9MEMDFejktkyD1kuL0Yo5hTT
EjD4BJ5PwJzHRhFo+XbaTkDvpT+ZbuwQUta1UAU1w8L4yXTcvQ3sK/w+bsHey1SeQdRQsQojNILe
OocVq6DYPk84FzehGQJInNjaO2duAcIei9xAKg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
oV0B01WlfOfwc65hHQyPonQOH8xjSJSgdAwbXD5rL4TD4D111/TiNKKXxh6TgXHovRC940qcZar9
P0mrOXcGDb/l2ZGaJjjXyKNi5MBEu6Iz5vo+vUigHa8Q0I5PjyUaKP8USieT+4j0BY5gj2y49aJe
1fSdSw/c9SyioHSzXLkOy0phkEkqYlG89kyPzsR1nXbOJOl35IppKY8VT/r6om9zCQUvHUpVeg4u
3S39qOWVv9lp5GZPzBynEGS1mdxeRm0dyrwFAETJRcG0+4ZuE46JhOhoaeOfRIW721WML0VXdcm6
0YIj22eWcgH2egIeQmsKb6w5wJ2A4aZabT+buWSaW+Sc4WLOHXI3AYz/HR5XOxuLgMmNOzl9TT9A
ANdcF/hDKi3osGFrWlL0sAaJHW3b+6YTsk8uy3ToimYkLrX/KAG8soVNDkeIn2m3MxqzyY/cSIEN
AHmTuJRDZPxlFUq+iHv07Mw2gbguTBxunDhPG5PE1kBt+iZzs/sLDBXifMknSWVQnGEu2ETYLlBS
Ye2TyR3xhUHadhzodOtneytHnFyMDd4TsYz/Ym1AmcxH9iAhoGQS5EzBDW6FfgKLprFOCNlr3Ogz
8E8rRzZnkS3Scu2mA1zieEAXOONeEVxrB4WBdJYY3CtVsUqdc+QGUaN2Cg/tt0NGtsbPFwPYb8x9
Ok1aXiaTk87Eqn7ObpCQA5wvvZut9TEWUeDtVf7nw1MQchDRWGJZFgfo8zNRT1JBkxYNaStRxHcv
NXyZwIFpzJ9l8g9fLizHUNqHMsyQ0D0uXDHYWr+jjN61Tmoi3eSW09/mq20lwL8pHO880Bfjifz+
7FgrOP0ARh3sZ6TmAHCuSFx+g9BWZp6nEJufaLG4X8IC3sXzJiTOU4octt/xU8km5N4jpytU7fVQ
Zs8YbzubQKrRhIVZJNKbeM9HdJijNja0AwRf2Yvp7qEk4KEWisWO6OtSGUgnUa+rQaYWjBs6Hcu1
xGSB0zV1RR2+w9uifUNuJN3WU+HTl1QVQrFP8NSa0AcTQ6Or0x1JKGS44F9sQiPavST55BbJYocE
t6NXd9TYhcX6fSQ5/gr8OwRTCOW5cEPPimy0vFeTR/vcobN1cLVSwGysZp3lv0NO6x51vdQnsKqH
X4BYhXGHxZgFUmMNK/rCm19l2SQBr1DWeRaKfy5/0oM2oqTUCIiMPgoyt6j0wHejsJqWPwHWciX5
YnV4ZZETzLBuC7GCswQ5W1eP3/c1Stk5xr+yTWQoa+IXI6526qt+b+Ywx7j+vrd2+N8irEXwnVTV
hGiVZvkZ0978ypphj56l54i54mKlUJXNMl0R7P3yrb2og9MyxruSax8EtyN3iMyYwDCyIFLXHwab
hghXFA3mIU5foJXDtbK3p9iwK6ZpEAxNyFGWGfjdCGF0z10jqZxQ9WW75RrmW3cZ8+ZM0OijutFg
WZrpAsygehs9uCDzh/Oh2KhSo6D8qM3spREZbYYG/Yl6o6D1H24ehSmZBqSfQll46XcUjMMBQgT3
98Ku1C5uc5UFP0ryVbJz0660n/QFhOReefgVDk+hU6VC+l7+AehVTd7TyX6anmDnl4NGYeIgCbZh
WTQ+TrrdM7k+uVrwlpE5iD2v9Hk084hKc5d/0tH8p5arGpowpoBDmtLsuxoNNDS7oqC/3dMkI5Ke
cFykzmAcIlb98bfnmfy/MzCN83VQsxlKFtgZd3AIeFtZtXAoiukHZzFEw8aic7fEyiBlHXiJ0Zzs
q43M/XitituQuBR+fqaFYzwcJ9G3NnETXWDoDffFwIyn1f4wQX76/UU/vuwfLtY5kfPrtskvpwn6
ZpuqQK0nQyfJXwbLkFEnmpJ1YsZd5+c6EBr7zLKSP+BUtjC7Zz14Lh01Pz7YsmuD6l9H8VpdPdBX
SFKjmOnaEU3aQpxJmOVIaogz6qO2ce/TJaEukKXi4+ntHRT+WLoAESyShmgw7OL5d7P/AQcbanTC
tJkUWHRSoqWMHb0rD1kXjp/bUEpoQ0pLgtfuDuHr5eOREbkMDESDJJ6pET7GBLmcokobCqtgWejU
/kXJU5yFNQ4/5qZFfB4vqbnAEgeXciv+KKRnzrj4LGQ06EpS8t306C41Qxf4ogh/vs7IeejABz4D
1IPDXwm5jJFMCMU2dsZLzx2u2sqgNE1N875is4kUmkeFmfsxDV/R5M2kQFGlXkrnn/4jD1MoPAZy
oGJe2CEOUEzyCC9H0FzHpTzKr5flgZ2XfCH1SreaysB4UIA41/00cwT4z+PXoK9MWAyebelcO0yC
rJFEyf/W+gtIBK0O3yklP5gwSsiK4felu3Vz1/UqqZ7y9HtSYCUevDup9xONpLe3F8cnjNNDRgl+
acMuPH9ATgxJIzHKhjLWt/hT4c1J64Ov8rCPbvko8BNyhak6sThbusbkCAbXJkvhD6SHfYgeJn5u
aJfFRDez2gajS57Px2QFyMvW42v0+fF2+lZPa3TYqIDqhVpxPyyNcfeIGZwUvw/q3hX4go2g8zTu
WnNAb+whbq1LM/qgtvFqECDm27Kq9B8YLATQVQ7zFqm+n4vdP+ViRvspNy3uh6aRiH+bj5ll3+TE
Ud88Sr0pZnRdc9mt7eDujN/lSyPTxhhtDRkd/E5UIQYrUUwr6JC5qf+0pfsPILtuxWw59fVZzRjv
oCckP8slbojSDY9sG7buIVgOnN1vF9Q8lCvBSeXxi54Mspv+QZmMESN9G+VHA/YGEGCmlaIyC6Gd
R7aTrDydSPJ+K54fRYHKXYcyy7UksjaShbwCcp7lq8qY2cvUueuchC8mLI0FPJvUCDFY9bhPeDWK
JXZt4LZmD3B/uq+Jl0UqlAXLs9eJJzynhpfKLgH1sTwmQ6zlUInD91mQguDZrtT8s2TTv8z+ke1a
DiiDtK56K90dCz9ZeAFonengbwFy6EmrRNyj0IzqMF1IfIXQTMATSyxK+3LL/JylP9pBYVGeRLu1
ScJNTLe15Mxx+NOYj9pAa+5SecZhn6/4rDl6ITvm8jglY+DjStaTA3ED0sq9tjCGMeqbTFEM/Mq0
erVAs6NSKTtaKt15HP2Dohok4JG1wsGudOU4RcIYwXRTNoiGzqTmIDAFyKWMzxGd3cYxcXctxX9/
uo+p4QIQC+XOw6HGlJ931C0kVHAvoKlhmjBTS+10EBBGU1//b2cZOxEITxxRjbg2xbA0Gbhes+BY
4kbDb2bMX2yQozoUuCPx0ngWzZNxmoA9csSLVl7gAVZUkCLzTSXO+inrX1GbMoaAjAt+mGp+5eVS
m30aC0xk8QjwJqmZqwQz2xiLBLRqTiYMPb+mH9cBN7UgRxp7pw1mgsgTNjmEjDT/0SvDbUuSGcej
aIbVeCAyJ32TOjkzbKDYccFFOcCHbOMacz5HyQpMQgc6idOrdebmTM12fAru/Mu0T9C8w5kf9FZT
M3woCgfOTpQhrswuCB3kvsYCzCncQL2BE5Rsw1P84/kgNfR+sSFNugy6kFyN1yno3ur6JtsH4EUn
yO7n21QnpbvVE7jf2llPNkSZZ5Iw7PD3r+diZX3avI4yda0P1E5JxuxfLVvK0oSmVNyJrtsDIE2E
HmDx3J3w536qmRz7UXBn3C7rYGGZs5gXTxFQhIHOc64Ox3eygWU/S2ZKteJ8LzZXBPBzWjj5feWO
H8aFZS6d9y5OOdnGuwJnbSW/cSFD96fJrvN42wgbnEPTwySP+g/gVfctI1wwYPnHk32vZQgF4H17
kX9pgrPPEJCtmBsfc0BA9HbrDt/IWBMyP1QDF0TGyYL766V3TSPXkTjK3IuA8y7pzxnD7V+jxbAO
kzjbhI0Kn7tuIb8ogB1YLzOI0ywqV6Y6tAmLDy2PWKDRam6I9oXEwI0fYKzLisb6Js/WM6/91vN6
w8a+OeKKtmF1PLVyEYPJukm4jrR/2j8PnX5rqCXwQVomraG7Gqzv1P2kLO1THK1ml5eViqELuMQh
VvGE0OBueqSlSsJA63hmrbsxb/uNI5pyWdGx9KBvk9GHCcVw8Qa2POihO7t4DkYTH0r+yHbC+gj5
lMl/lT2QuJHFuDegdW7DJPx8fPbrZXkMr7k+X1Ug+1UB9YggxkVFLf4uBEOGLc1qSqG8+NSckuBV
IOY9ihA4oB4V257L5QmxHeGk3BktdpBuKQr+HRPLl1fgPdCu8So9ybCLNBuBL+E6uqBWMii//WMd
wmnqk67bt1DmuuDQqgHjNUzSSjrZUOmNgpKqbD6npzB3yl8nC42a+n0QpaPjT/smnd+Z6Em+uyht
9t2BV5CFd7eICPhgyeLtlO1BiRHrhyf8G32KJmHcGxHysG7vXpE72z8uUvUIj9ZfWT3ZI5/oKYt2
SvP6N0EZflfvJbVcI7ojFemX60G2qJP8To/fv1pPmiCRzNF+jGabHbwQ/gspG22q7t+wNq8oF/eq
XtjjnhpT3hqVnJ4XOs1WAhh1oLs12aHkwrXjj8Kwk+VvjA2VZqo5WOpqGGBAbZn0Pf0B6WTihaz4
PdOBPzGOK29wO06lJ0cOlieki/bcDKZ4C3/ggJIm8V6xw36QYWsNFWDljdfb8Nz2+DzcRuKuJ4xk
FXbpv5doHN3QwCqhWTdFz7WfHDul3EWWuaN/r+k/FtJFUS867ScyULoqPafqSGzwMHwgpaVtfT4s
X5YKI7f3vPK4f7bQqIOaMUxoX6iL8ShFIb+bZghxhEMxANc0MSrnOVxkNFm45eITrQjIxQ4pRZV5
m/+pocblXBph2M8E4HavO5irPKu2RXxQziJrIsBzjha6GjxgJh+QgBIn09hbsTG5S7eMwQu3fzpF
0ZwcTqhg+0iSPUhjsbEX2Ev/EFv2jbAUemtVrTxRojXX5ywmFCTIrGACNyIzoCzPtHyHjYEs9G08
OQfN2qvfhBGZZw1TITCSKssq0IHZs6MBYk7gTGK6HC/E/9HHBehoo4t030YrlWxDZ10HeZNc6HmL
kKspX4/0s+wj4G6qh6wx2v9IT24R9vTx5UCwzF5otHxqKEHowvFhPDKnf1B3/k+WIHDXBhn7xE+Y
JAcbCOWqSUbj+YRaowu0NouDoa34N+ypq7m+Zjo9pMfu880SsKekFwcgjhEZ/gaoslKK+yudt9EC
NF3dy4M5K3A9AMGw4Mipq7XRF60xYEPbQEyjSj3Uvck0wklCpBoccorgr9JA/3cDSIT8Dxp3yloJ
cPDacUeRBcTvGW1gnz0FxZmnZNE+6zRdSEbcNy6xvfFfjRRkh/B7FqKJyWTiM0dCrycPvP8vwvCj
m/MwDlkR386Wq95DobRF6Maub8rABBku+z/UCp8fgGkvNl29TVpD01ANanMdIPVdpYFSXIc2A8MS
9JOeRTLuo4WjWaSZpYlMC6YPvzbbds8rwlY+8SBNXnUKDD5oDcSoBJeyEdTjqmU8oWkuaN7SCMry
uk3J3HplIIS/xr8JuvByw7bHcDYziCWL+Ssjgvcrrbh3Pm4a66nqF+BOBxcc1ws2+uc2C1orhp04
THt1HuzqA1RaqXf55tL/IscqbQj7+LcuVdym7u6Y8rYs4VB0vEUFJpXx7FJ9h/nyExmi5LwAzDs0
X9Cjl5IBCovFu/qHv9Kk8PUMUu7XuslxrbXCKqWVii7ttd4927C8RxhZBGuIY9o+Af/0M2BlSdL6
OC22iaT0WMUBOEm4FAko3z4SNCgCgcadtocktNO1M4FjzQJ+tnAm2asu2TrQTppg8F0R1Z6wc5tf
mbNsVF7mOgYCwzDaSb6BsmoPCuCBaWzBwSEjk0mUQCjAsEhN1cfmAq/LPUbMG8KtN5u9NmmB1jSW
t617AtXy5wgc0m5akVo5G5CqQV6TKVIMAKUDRXZ7vPvv1qBcBnc9+LsYX5Zhspz1KopCqpy3Lqwu
re4QavJZbcr5p8HDg0lETRGjz+mGukzPtZ/WsAD9NyG9gkl11znBDl6M4RwmQPe4NVN/pdLeHzSg
+0i2BMdolGPLneMpdIbXqZlBi/FiNppmgxMDbRiR4vDsmKQRgTQdzxO2Jd2RvFk3db0kbqu0Sa4V
aMaZ4F0xbOy6Se7fXQMx7BWIuVmchQMFHzs8DRHOBHr0cmyS3VKaF1TPEToIfWFWNg+dISLv6ksF
sFKnh9hrCtWlRSoc5RmEDNwSlLYcf2xD9EmqF8cqlWFQrhzbNTsF9qM7CT7YDSIEvnJZDKBLUDRg
OmnOMns6rHoe2IrZNiwEAgvH9q7Y7kayfmZQS6A4kXodDlEPxu49HwME8iRfbSDHd0AZYDVjoleG
ccF8mfi5NocqNaQJpbxg3bbNU/kqYfNlzmN4Y3l6HKbdQwG3JIsC9LWl6t3gHI5Vy77vFkvf34oE
2nM0Anyn1QzuW7CMUyMo39WewwTruMos7SjCnn5qsa2+PH20iBwScVotruGZ64A9gfhUePYKy3dz
RTw/+6rp0LqaU9nkJhqsxPYdp8ucRebtFJw8zBCGh+fr6/h13Nsy2Xy1ek0Buc+Q0ccszGxJffAj
tO6liaqh3vVqjk2Jw4v8tBXHAEpPDJ0Np2nEiueu61JwLiOuSERmEFp/OlbhcmBoAHoQav9XZBw6
YZJeTedwZ4anCGmjsFS8Ae1E3ufBgIFU08J1kG05YNj7ROrxADqDOfNTTpOns/vW0XoXro2wR/sP
LqfbehKiPMYox4PS1jeFGC2bDMn4/1pfHNPYsfL5AEbNiTcfB2rBLXnfPwt9DwGLu2jwZhjGsPpa
DnaRji6JbJmU1BUBLAajCtgrn8rJGXAvnvF3AtU4y2c0tdfygTBlMHfFYrLXPzZLoQ0oQb4HnXgF
Z0SFM3cdCoNHI/bG3Af+vQNVsFnyph4ecCzHSBvcYInmSER00re4rnFYJD4v+9TI7KDZsoTuCGu5
mvnMNNqZVV95Z5tGR4FTJrD1YfzlsNbV9JhIRLMpwg7M8vDqfvq6QqP4Dh/uO2UPfV1QzH14+ItT
zJn47GupE9HIFQ0hCEwDmQjFcfiEkL3wU13PoSCwX8cG6kjk2tKIIyEKdfVw1ZT1PwsRyhp53en5
y/lVF2MtQkuYl+Y60xYoa0iR6qdmryXX9OiBBNmYy8ZS8GGt3ArvAsmGIV12Q66MKxOHxdSH5hb2
uaC6iVcGF24iOkndTmUNsrzxmHI7OPNRJx82fpkl7pe9tywZtTVlLE0JEBeY3kPCUQI3Ij37FlFa
Ej7kvpSHhi79MCBO69uSUvi4tzehpHYR6ebmlDtW6E3HjRyM3/xDeyWXwdGWlsBup6RrJ0LYhmaT
yWik1/OzVAeBVUlH/aiyBvrQMkAGeLqBsPjGkg0XEP77Mz2/hyVNuAieBPhd4gZBezB6p9w1jbd5
qL5O3tEtshT884p+7BEsNil+0IYvBnP39H1rv2vt9m1QZPjSmt5TTtTOLyyqEq/1hKNhG9SFkUln
iN1LNmaBCBuS7XgLAvqKz0z4jcRvwOGjarhSg5nNiMd8IDtOkZjiqtz5eKgEZKn8dvvo6xFN1gsc
QniLLjHe5FJCH85sW6yebbr6rR8JRISXpXgkRqDK
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QLOOoKlGeTs3w0jXG0JqRwtHZ6ZjMLpVm5gbg83RVaMB6qCMyHD5NAuvGh/R1T6ZlQp0NMh7Bnk2
5AdHD7cJjA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oiLZfYUeAPLDA1mPt1oWE8FJuiWI9nQq70AHCVDv7/+/ko3oL+RM55qvzg78ir0IIow9o1QQnZzi
/QnPM3je+PmrMbklYC8hbnc/6WwoYTDYWBjwmnT4WuTu79zT5Dz2iwvQ7UO87XDo6Vccxhk/KNba
ZrIF5dUtbh9SBfEo1pc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHdof/KFp2koF/o91nEi7LW4+89e3FRu/nu4NfaWjoFf23t/IPwz0N/ZySSZXeZj7NpcOCWZtivU
DSFNkcNUoxn1xhwZjydQXsRPzt7zggpp1RwvhW+chmFxHP6jaXMEqUkO5g6sEZrtVQtnMb5nqceA
2nqbftFy9y4Jt7UmohJJDYMVVeIXLbWZ+sM9wnfgB7VManZH1vBNIzUmC7EzVRugcadqTAPkQuML
c+Zvth8zYTGwbqF7L7DymzQB8U0Jap19ompCBbL4q3fT1HLAOoCqWtUDTR7MfugbLBGTA07mp/hW
apZVGF7Ua5AJ+LWqKRW3am2rKk+mVP16uzjX2g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cQW6+AQd3QOZ1YlcrM/LQugKHjz+MqOUuR5a7MVb+w/h0VQ2EpwCS5QaTg5R6MyncLujB8RUugJT
TvCpchFxnZKs10+1mFZC2KrxQFUIaFzvxV/edf3kLHqviBvAcROXFgSetBEx4AKxc/qvQlm8TYvH
FrL3s45jp51A+vkmnio=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nKmftmxJaLdDTM8ApbRpeOSEHVHDWxzh224hvKHxX106ZVfuSqNl6gPbiSpYnnR+hX/i6n0KWBzO
TP+ubtn7uZgVs+/SfxIy3/Sdm0XgcPm9XNcKemx6b5YMwbBewBHzaMu0r1SlSZZn1kPD1zp7f3Kq
IbDj+od/lSq1wO/ibX6+NVPKJDfdGA5UBJAJ9ilvb44fl5kcPiTZ9MEMDFejktkyD1kuL0Yo5hTT
EjD4BJ5PwJzHRhFo+XbaTkDvpT+ZbuwQUta1UAU1w8L4yXTcvQ3sK/w+bsHey1SeQdRQsQojNILe
OocVq6DYPk84FzehGQJInNjaO2duAcIei9xAKg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
oV0B01WlfOfwc65hHQyPonQOH8xjSJSgdAwbXD5rL4TD4D111/TiNKKXxh6TgXHovRC940qcZar9
P0mrOXcGDb/l2ZGaJjjXyKNi5MBEu6Iz5vo+vUigHa8Q0I5PjyUaKP8USieT+4j0BY5gj2y49aJe
1fSdSw/c9SyioHSzXLkOy0phkEkqYlG89kyPzsR1nXbOJOl35IppKY8VT/r6om9zCQUvHUpVeg4u
3S39qOWVv9lp5GZPzBynEGS1mdxeRm0dyrwFAETJRcG0+4ZuE46JhOhoaeOfRIW721WML0VXdcm6
0YIj22eWcgH2egIeQmsKb6w5wJ2A4aZabT+buWSaW+Sc4WLOHXI3AYz/HR5XOxuLgMmNOzl9TT9A
ANdcF/hDKi3osGFrWlL0sAaJHW3b+6YTsk8uy3ToimYkLrX/KAG8soVNDkeIn2m3MxqzyY/cSIEN
AHmTuJRDZPxlFUq+iHv07Mw2gbguTBxunDhPG5PE1kBt+iZzs/sLDBXifMknSWVQnGEu2ETYLlBS
Ye2TyR3xhUHadhzodOtneytHnFyMDd4TsYz/Ym1AmcxH9iAhoGQS5EzBDW6FfgKLprFOCNlr3Ogz
8E8rRzZnkS3Scu2mA1zieEAXOONeEVxrB4WBdJYY3CtVsUqdc+QGUaN2Cg/tt0NGtsbPFwPYb8x9
Ok1aXiaTk87Eqn7ObpCQA5wvvZut9TEWUeDtVf7nw1MQchDRWGJZFgfo8zNRT1JBkxYNaStRxHcv
NXyZwIFpzJ9l8g9fLizHUNqHMsyQ0D0uXDHYWr+jjN61Tmoi3eSW09/mq20lwL8pHO880Bfjifz+
7FgrOP0ARh3sZ6TmAHCuSFx+g9BWZp6nEJufaLG4X8IC3sXzJiTOU4octt/xU8km5N4jpytU7fVQ
Zs8YbzubQKrRhIVZJNKbeM9HdJijNja0AwRf2Yvp7qEk4KEWisWO6OtSGUgnUa+rQaYWjBs6Hcu1
xGSB0zV1RR2+w9uifUNuJN3WU+HTl1QVQrFP8NSa0AcTQ6Or0x1JKGS44F9sQiPavST55BbJYocE
t6NXd9TYhcX6fSQ5/gr8OwRTCOW5cEPPimy0vFeTR/vcobN1cLVSwGysZp3lv0NO6x51vdQnsKqH
X4BYhXGHxZgFUmMNK/rCm19l2SQBr1DWeRaKfy5/0oM2oqTUCIiMPgoyt6j0wHejsJqWPwHWciX5
YnV4ZZETzLBuC7GCswQ5W1eP3/c1Stk5xr+yTWQoa+IXI6526qt+b+Ywx7j+vrd2+N8irEXwnVTV
hGiVZvkZ0978ypphj56l54i54mKlUJXNMl0R7P3yrb2og9MyxruSax8EtyN3iMyYwDCyIFLXHwab
hghXFA3mIU5foJXDtbK3p9iwK6ZpEAxNyFGWGfjdCGF0z10jqZxQ9WW75RrmW3cZ8+ZM0OijutFg
WZrpAsygehs9uCDzh/Oh2KhSo6D8qM3spREZbYYG/Yl6o6D1H24ehSmZBqSfQll46XcUjMMBQgT3
98Ku1C5uc5UFP0ryVbJz0660n/QFhOReefgVDk+hU6VC+l7+AehVTd7TyX6anmDnl4NGYeIgCbZh
WTQ+TrrdM7k+uVrwlpE5iD2v9Hk084hKc5d/0tH8p5arGpowpoBDmtLsuxoNNDS7oqC/3dMkI5Ke
cFykzmAcIlb98bfnmfy/MzCN83VQsxlKFtgZd3AIeFtZtXAoiukHZzFEw8aic7fEyiBlHXiJ0Zzs
q43M/XitituQuBR+fqaFYzwcJ9G3NnETXWDoDffFwIyn1f4wQX76/UU/vuwfLtY5kfPrtskvpwn6
ZpuqQK0nQyfJXwbLkFEnmpJ1YsZd5+c6EBr7zLKSP+BUtjC7Zz14Lh01Pz7YsmuD6l9H8VpdPdBX
SFKjmOnaEU3aQpxJmOVIaogz6qO2ce/TJaEukKXi4+ntHRT+WLoAESyShmgw7OL5d7P/AQcbanTC
tJkUWHRSoqWMHb0rD1kXjp/bUEpoQ0pLgtfuDuHr5eOREbkMDESDJJ6pET7GBLmcokobCqtgWejU
/kXJU5yFNQ4/5qZFfB4vqbnAEgeXciv+KKRnzrj4LGQ06EpS8t306C41Qxf4ogh/vs7IeejABz4D
1IPDXwm5jJFMCMU2dsZLzx2u2sqgNE1N875is4kUmkeFmfsxDV/R5M2kQFGlXkrnn/4jD1MoPAZy
oGJe2CEOUEzyCC9H0FzHpTzKr5flgZ2XfCH1SreaysB4UIA41/00cwT4z+PXoK9MWAyebelcO0yC
rJFEyf/W+gtIBK0O3yklP5gwSsiK4felu3Vz1/UqqZ7y9HtSYCUevDup9xONpLe3F8cnjNNDRgl+
acMuPH9ATgxJIzHKhjLWt/hT4c1J64Ov8rCPbvko8BNyhak6sThbusbkCAbXJkvhD6SHfYgeJn5u
aJfFRDez2gajS57Px2QFyMvW42v0+fF2+lZPa3TYqIDqhVpxPyyNcfeIGZwUvw/q3hX4go2g8zTu
WnNAb+whbq1LM/qgtvFqECDm27Kq9B8YLATQVQ7zFqm+n4vdP+ViRvspNy3uh6aRiH+bj5ll3+TE
Ud88Sr0pZnRdc9mt7eDujN/lSyPTxhhtDRkd/E5UIQYrUUwr6JC5qf+0pfsPILtuxWw59fVZzRjv
oCckP8slbojSDY9sG7buIVgOnN1vF9Q8lCvBSeXxi54Mspv+QZmMESN9G+VHA/YGEGCmlaIyC6Gd
R7aTrDydSPJ+K54fRYHKXYcyy7UksjaShbwCcp7lq8qY2cvUueuchC8mLI0FPJvUCDFY9bhPeDWK
JXZt4LZmD3B/uq+Jl0UqlAXLs9eJJzynhpfKLgH1sTwmQ6zlUInD91mQguDZrtT8s2TTv8z+ke1a
DiiDtK56K90dCz9ZeAFonengbwFy6EmrRNyj0IzqMF1IfIXQTMATSyxK+3LL/JylP9pBYVGeRLu1
ScJNTLe15Mxx+NOYj9pAa+5SecZhn6/4rDl6ITvm8jglY+DjStaTA3ED0sq9tjCGMeqbTFEM/Mq0
erVAs6NSKTtaKt15HP2Dohok4JG1wsGudOU4RcIYwXRTNoiGzqTmIDAFyKWMzxGd3cYxcXctxX9/
uo+p4QIQC+XOw6HGlJ931C0kVHAvoKlhmjBTS+10EBBGU1//b2cZOxEITxxRjbg2xbA0Gbhes+BY
4kbDb2bMX2yQozoUuCPx0ngWzZNxmoA9csSLVl7gAVZUkCLzTSXO+inrX1GbMoaAjAt+mGp+5eVS
m30aC0xk8QjwJqmZqwQz2xiLBLRqTiYMPb+mH9cBN7UgRxp7pw1mgsgTNjmEjDT/0SvDbUuSGcej
aIbVeCAyJ32TOjkzbKDYccFFOcCHbOMacz5HyQpMQgc6idOrdebmTM12fAru/Mu0T9C8w5kf9FZT
M3woCgfOTpQhrswuCB3kvsYCzCncQL2BE5Rsw1P84/kgNfR+sSFNugy6kFyN1yno3ur6JtsH4EUn
yO7n21QnpbvVE7jf2llPNkSZZ5Iw7PD3r+diZX3avI4yda0P1E5JxuxfLVvK0oSmVNyJrtsDIE2E
HmDx3J3w536qmRz7UXBn3C7rYGGZs5gXTxFQhIHOc64Ox3eygWU/S2ZKteJ8LzZXBPBzWjj5feWO
H8aFZS6d9y5OOdnGuwJnbSW/cSFD96fJrvN42wgbnEPTwySP+g/gVfctI1wwYPnHk32vZQgF4H17
kX9pgrPPEJCtmBsfc0BA9HbrDt/IWBMyP1QDF0TGyYL766V3TSPXkTjK3IuA8y7pzxnD7V+jxbAO
kzjbhI0Kn7tuIb8ogB1YLzOI0ywqV6Y6tAmLDy2PWKDRam6I9oXEwI0fYKzLisb6Js/WM6/91vN6
w8a+OeKKtmF1PLVyEYPJukm4jrR/2j8PnX5rqCXwQVomraG7Gqzv1P2kLO1THK1ml5eViqELuMQh
VvGE0OBueqSlSsJA63hmrbsxb/uNI5pyWdGx9KBvk9GHCcVw8Qa2POihO7t4DkYTH0r+yHbC+gj5
lMl/lT2QuJHFuDegdW7DJPx8fPbrZXkMr7k+X1Ug+1UB9YggxkVFLf4uBEOGLc1qSqG8+NSckuBV
IOY9ihA4oB4V257L5QmxHeGk3BktdpBuKQr+HRPLl1fgPdCu8So9ybCLNBuBL+E6uqBWMii//WMd
wmnqk67bt1DmuuDQqgHjNUzSSjrZUOmNgpKqbD6npzB3yl8nC42a+n0QpaPjT/smnd+Z6Em+uyht
9t2BV5CFd7eICPhgyeLtlO1BiRHrhyf8G32KJmHcGxHysG7vXpE72z8uUvUIj9ZfWT3ZI5/oKYt2
SvP6N0EZflfvJbVcI7ojFemX60G2qJP8To/fv1pPmiCRzNF+jGabHbwQ/gspG22q7t+wNq8oF/eq
XtjjnhpT3hqVnJ4XOs1WAhh1oLs12aHkwrXjj8Kwk+VvjA2VZqo5WOpqGGBAbZn0Pf0B6WTihaz4
PdOBPzGOK29wO06lJ0cOlieki/bcDKZ4C3/ggJIm8V6xw36QYWsNFWDljdfb8Nz2+DzcRuKuJ4xk
FXbpv5doHN3QwCqhWTdFz7WfHDul3EWWuaN/r+k/FtJFUS867ScyULoqPafqSGzwMHwgpaVtfT4s
X5YKI7f3vPK4f7bQqIOaMUxoX6iL8ShFIb+bZghxhEMxANc0MSrnOVxkNFm45eITrQjIxQ4pRZV5
m/+pocblXBph2M8E4HavO5irPKu2RXxQziJrIsBzjha6GjxgJh+QgBIn09hbsTG5S7eMwQu3fzpF
0ZwcTqhg+0iSPUhjsbEX2Ev/EFv2jbAUemtVrTxRojXX5ywmFCTIrGACNyIzoCzPtHyHjYEs9G08
OQfN2qvfhBGZZw1TITCSKssq0IHZs6MBYk7gTGK6HC/E/9HHBehoo4t030YrlWxDZ10HeZNc6HmL
kKspX4/0s+wj4G6qh6wx2v9IT24R9vTx5UCwzF5otHxqKEHowvFhPDKnf1B3/k+WIHDXBhn7xE+Y
JAcbCOWqSUbj+YRaowu0NouDoa34N+ypq7m+Zjo9pMfu880SsKekFwcgjhEZ/gaoslKK+yudt9EC
NF3dy4M5K3A9AMGw4Mipq7XRF60xYEPbQEyjSj3Uvck0wklCpBoccorgr9JA/3cDSIT8Dxp3yloJ
cPDacUeRBcTvGW1gnz0FxZmnZNE+6zRdSEbcNy6xvfFfjRRkh/B7FqKJyWTiM0dCrycPvP8vwvCj
m/MwDlkR386Wq95DobRF6Maub8rABBku+z/UCp8fgGkvNl29TVpD01ANanMdIPVdpYFSXIc2A8MS
9JOeRTLuo4WjWaSZpYlMC6YPvzbbds8rwlY+8SBNXnUKDD5oDcSoBJeyEdTjqmU8oWkuaN7SCMry
uk3J3HplIIS/xr8JuvByw7bHcDYziCWL+Ssjgvcrrbh3Pm4a66nqF+BOBxcc1ws2+uc2C1orhp04
THt1HuzqA1RaqXf55tL/IscqbQj7+LcuVdym7u6Y8rYs4VB0vEUFJpXx7FJ9h/nyExmi5LwAzDs0
X9Cjl5IBCovFu/qHv9Kk8PUMUu7XuslxrbXCKqWVii7ttd4927C8RxhZBGuIY9o+Af/0M2BlSdL6
OC22iaT0WMUBOEm4FAko3z4SNCgCgcadtocktNO1M4FjzQJ+tnAm2asu2TrQTppg8F0R1Z6wc5tf
mbNsVF7mOgYCwzDaSb6BsmoPCuCBaWzBwSEjk0mUQCjAsEhN1cfmAq/LPUbMG8KtN5u9NmmB1jSW
t617AtXy5wgc0m5akVo5G5CqQV6TKVIMAKUDRXZ7vPvv1qBcBnc9+LsYX5Zhspz1KopCqpy3Lqwu
re4QavJZbcr5p8HDg0lETRGjz+mGukzPtZ/WsAD9NyG9gkl11znBDl6M4RwmQPe4NVN/pdLeHzSg
+0i2BMdolGPLneMpdIbXqZlBi/FiNppmgxMDbRiR4vDsmKQRgTQdzxO2Jd2RvFk3db0kbqu0Sa4V
aMaZ4F0xbOy6Se7fXQMx7BWIuVmchQMFHzs8DRHOBHr0cmyS3VKaF1TPEToIfWFWNg+dISLv6ksF
sFKnh9hrCtWlRSoc5RmEDNwSlLYcf2xD9EmqF8cqlWFQrhzbNTsF9qM7CT7YDSIEvnJZDKBLUDRg
OmnOMns6rHoe2IrZNiwEAgvH9q7Y7kayfmZQS6A4kXodDlEPxu49HwME8iRfbSDHd0AZYDVjoleG
ccF8mfi5NocqNaQJpbxg3bbNU/kqYfNlzmN4Y3l6HKbdQwG3JIsC9LWl6t3gHI5Vy77vFkvf34oE
2nM0Anyn1QzuW7CMUyMo39WewwTruMos7SjCnn5qsa2+PH20iBwScVotruGZ64A9gfhUePYKy3dz
RTw/+6rp0LqaU9nkJhqsxPYdp8ucRebtFJw8zBCGh+fr6/h13Nsy2Xy1ek0Buc+Q0ccszGxJffAj
tO6liaqh3vVqjk2Jw4v8tBXHAEpPDJ0Np2nEiueu61JwLiOuSERmEFp/OlbhcmBoAHoQav9XZBw6
YZJeTedwZ4anCGmjsFS8Ae1E3ufBgIFU08J1kG05YNj7ROrxADqDOfNTTpOns/vW0XoXro2wR/sP
LqfbehKiPMYox4PS1jeFGC2bDMn4/1pfHNPYsfL5AEbNiTcfB2rBLXnfPwt9DwGLu2jwZhjGsPpa
DnaRji6JbJmU1BUBLAajCtgrn8rJGXAvnvF3AtU4y2c0tdfygTBlMHfFYrLXPzZLoQ0oQb4HnXgF
Z0SFM3cdCoNHI/bG3Af+vQNVsFnyph4ecCzHSBvcYInmSER00re4rnFYJD4v+9TI7KDZsoTuCGu5
mvnMNNqZVV95Z5tGR4FTJrD1YfzlsNbV9JhIRLMpwg7M8vDqfvq6QqP4Dh/uO2UPfV1QzH14+ItT
zJn47GupE9HIFQ0hCEwDmQjFcfiEkL3wU13PoSCwX8cG6kjk2tKIIyEKdfVw1ZT1PwsRyhp53en5
y/lVF2MtQkuYl+Y60xYoa0iR6qdmryXX9OiBBNmYy8ZS8GGt3ArvAsmGIV12Q66MKxOHxdSH5hb2
uaC6iVcGF24iOkndTmUNsrzxmHI7OPNRJx82fpkl7pe9tywZtTVlLE0JEBeY3kPCUQI3Ij37FlFa
Ej7kvpSHhi79MCBO69uSUvi4tzehpHYR6ebmlDtW6E3HjRyM3/xDeyWXwdGWlsBup6RrJ0LYhmaT
yWik1/OzVAeBVUlH/aiyBvrQMkAGeLqBsPjGkg0XEP77Mz2/hyVNuAieBPhd4gZBezB6p9w1jbd5
qL5O3tEtshT884p+7BEsNil+0IYvBnP39H1rv2vt9m1QZPjSmt5TTtTOLyyqEq/1hKNhG9SFkUln
iN1LNmaBCBuS7XgLAvqKz0z4jcRvwOGjarhSg5nNiMd8IDtOkZjiqtz5eKgEZKn8dvvo6xFN1gsc
QniLLjHe5FJCH85sW6yebbr6rR8JRISXpXgkRqDK
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QLOOoKlGeTs3w0jXG0JqRwtHZ6ZjMLpVm5gbg83RVaMB6qCMyHD5NAuvGh/R1T6ZlQp0NMh7Bnk2
5AdHD7cJjA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oiLZfYUeAPLDA1mPt1oWE8FJuiWI9nQq70AHCVDv7/+/ko3oL+RM55qvzg78ir0IIow9o1QQnZzi
/QnPM3je+PmrMbklYC8hbnc/6WwoYTDYWBjwmnT4WuTu79zT5Dz2iwvQ7UO87XDo6Vccxhk/KNba
ZrIF5dUtbh9SBfEo1pc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHdof/KFp2koF/o91nEi7LW4+89e3FRu/nu4NfaWjoFf23t/IPwz0N/ZySSZXeZj7NpcOCWZtivU
DSFNkcNUoxn1xhwZjydQXsRPzt7zggpp1RwvhW+chmFxHP6jaXMEqUkO5g6sEZrtVQtnMb5nqceA
2nqbftFy9y4Jt7UmohJJDYMVVeIXLbWZ+sM9wnfgB7VManZH1vBNIzUmC7EzVRugcadqTAPkQuML
c+Zvth8zYTGwbqF7L7DymzQB8U0Jap19ompCBbL4q3fT1HLAOoCqWtUDTR7MfugbLBGTA07mp/hW
apZVGF7Ua5AJ+LWqKRW3am2rKk+mVP16uzjX2g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cQW6+AQd3QOZ1YlcrM/LQugKHjz+MqOUuR5a7MVb+w/h0VQ2EpwCS5QaTg5R6MyncLujB8RUugJT
TvCpchFxnZKs10+1mFZC2KrxQFUIaFzvxV/edf3kLHqviBvAcROXFgSetBEx4AKxc/qvQlm8TYvH
FrL3s45jp51A+vkmnio=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nKmftmxJaLdDTM8ApbRpeOSEHVHDWxzh224hvKHxX106ZVfuSqNl6gPbiSpYnnR+hX/i6n0KWBzO
TP+ubtn7uZgVs+/SfxIy3/Sdm0XgcPm9XNcKemx6b5YMwbBewBHzaMu0r1SlSZZn1kPD1zp7f3Kq
IbDj+od/lSq1wO/ibX6+NVPKJDfdGA5UBJAJ9ilvb44fl5kcPiTZ9MEMDFejktkyD1kuL0Yo5hTT
EjD4BJ5PwJzHRhFo+XbaTkDvpT+ZbuwQUta1UAU1w8L4yXTcvQ3sK/w+bsHey1SeQdRQsQojNILe
OocVq6DYPk84FzehGQJInNjaO2duAcIei9xAKg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
oV0B01WlfOfwc65hHQyPonQOH8xjSJSgdAwbXD5rL4TD4D111/TiNKKXxh6TgXHovRC940qcZar9
P0mrOXcGDb/l2ZGaJjjXyKNi5MBEu6Iz5vo+vUigHa8Q0I5PjyUaKP8USieT+4j0BY5gj2y49aJe
1fSdSw/c9SyioHSzXLkOy0phkEkqYlG89kyPzsR1nXbOJOl35IppKY8VT/r6om9zCQUvHUpVeg4u
3S39qOWVv9lp5GZPzBynEGS1mdxeRm0dyrwFAETJRcG0+4ZuE46JhOhoaeOfRIW721WML0VXdcm6
0YIj22eWcgH2egIeQmsKb6w5wJ2A4aZabT+buWSaW+Sc4WLOHXI3AYz/HR5XOxuLgMmNOzl9TT9A
ANdcF/hDKi3osGFrWlL0sAaJHW3b+6YTsk8uy3ToimYkLrX/KAG8soVNDkeIn2m3MxqzyY/cSIEN
AHmTuJRDZPxlFUq+iHv07Mw2gbguTBxunDhPG5PE1kBt+iZzs/sLDBXifMknSWVQnGEu2ETYLlBS
Ye2TyR3xhUHadhzodOtneytHnFyMDd4TsYz/Ym1AmcxH9iAhoGQS5EzBDW6FfgKLprFOCNlr3Ogz
8E8rRzZnkS3Scu2mA1zieEAXOONeEVxrB4WBdJYY3CtVsUqdc+QGUaN2Cg/tt0NGtsbPFwPYb8x9
Ok1aXiaTk87Eqn7ObpCQA5wvvZut9TEWUeDtVf7nw1MQchDRWGJZFgfo8zNRT1JBkxYNaStRxHcv
NXyZwIFpzJ9l8g9fLizHUNqHMsyQ0D0uXDHYWr+jjN61Tmoi3eSW09/mq20lwL8pHO880Bfjifz+
7FgrOP0ARh3sZ6TmAHCuSFx+g9BWZp6nEJufaLG4X8IC3sXzJiTOU4octt/xU8km5N4jpytU7fVQ
Zs8YbzubQKrRhIVZJNKbeM9HdJijNja0AwRf2Yvp7qEk4KEWisWO6OtSGUgnUa+rQaYWjBs6Hcu1
xGSB0zV1RR2+w9uifUNuJN3WU+HTl1QVQrFP8NSa0AcTQ6Or0x1JKGS44F9sQiPavST55BbJYocE
t6NXd9TYhcX6fSQ5/gr8OwRTCOW5cEPPimy0vFeTR/vcobN1cLVSwGysZp3lv0NO6x51vdQnsKqH
X4BYhXGHxZgFUmMNK/rCm19l2SQBr1DWeRaKfy5/0oM2oqTUCIiMPgoyt6j0wHejsJqWPwHWciX5
YnV4ZZETzLBuC7GCswQ5W1eP3/c1Stk5xr+yTWQoa+IXI6526qt+b+Ywx7j+vrd2+N8irEXwnVTV
hGiVZvkZ0978ypphj56l54i54mKlUJXNMl0R7P3yrb2og9MyxruSax8EtyN3iMyYwDCyIFLXHwab
hghXFA3mIU5foJXDtbK3p9iwK6ZpEAxNyFGWGfjdCGF0z10jqZxQ9WW75RrmW3cZ8+ZM0OijutFg
WZrpAsygehs9uCDzh/Oh2KhSo6D8qM3spREZbYYG/Yl6o6D1H24ehSmZBqSfQll46XcUjMMBQgT3
98Ku1C5uc5UFP0ryVbJz0660n/QFhOReefgVDk+hU6VC+l7+AehVTd7TyX6anmDnl4NGYeIgCbZh
WTQ+TrrdM7k+uVrwlpE5iD2v9Hk084hKc5d/0tH8p5arGpowpoBDmtLsuxoNNDS7oqC/3dMkI5Ke
cFykzmAcIlb98bfnmfy/MzCN83VQsxlKFtgZd3AIeFtZtXAoiukHZzFEw8aic7fEyiBlHXiJ0Zzs
q43M/XitituQuBR+fqaFYzwcJ9G3NnETXWDoDffFwIyn1f4wQX76/UU/vuwfLtY5kfPrtskvpwn6
ZpuqQK0nQyfJXwbLkFEnmpJ1YsZd5+c6EBr7zLKSP+BUtjC7Zz14Lh01Pz7YsmuD6l9H8VpdPdBX
SFKjmOnaEU3aQpxJmOVIaogz6qO2ce/TJaEukKXi4+ntHRT+WLoAESyShmgw7OL5d7P/AQcbanTC
tJkUWHRSoqWMHb0rD1kXjp/bUEpoQ0pLgtfuDuHr5eOREbkMDESDJJ6pET7GBLmcokobCqtgWejU
/kXJU5yFNQ4/5qZFfB4vqbnAEgeXciv+KKRnzrj4LGQ06EpS8t306C41Qxf4ogh/vs7IeejABz4D
1IPDXwm5jJFMCMU2dsZLzx2u2sqgNE1N875is4kUmkeFmfsxDV/R5M2kQFGlXkrnn/4jD1MoPAZy
oGJe2CEOUEzyCC9H0FzHpTzKr5flgZ2XfCH1SreaysB4UIA41/00cwT4z+PXoK9MWAyebelcO0yC
rJFEyf/W+gtIBK0O3yklP5gwSsiK4felu3Vz1/UqqZ7y9HtSYCUevDup9xONpLe3F8cnjNNDRgl+
acMuPH9ATgxJIzHKhjLWt/hT4c1J64Ov8rCPbvko8BNyhak6sThbusbkCAbXJkvhD6SHfYgeJn5u
aJfFRDez2gajS57Px2QFyMvW42v0+fF2+lZPa3TYqIDqhVpxPyyNcfeIGZwUvw/q3hX4go2g8zTu
WnNAb+whbq1LM/qgtvFqECDm27Kq9B8YLATQVQ7zFqm+n4vdP+ViRvspNy3uh6aRiH+bj5ll3+TE
Ud88Sr0pZnRdc9mt7eDujN/lSyPTxhhtDRkd/E5UIQYrUUwr6JC5qf+0pfsPILtuxWw59fVZzRjv
oCckP8slbojSDY9sG7buIVgOnN1vF9Q8lCvBSeXxi54Mspv+QZmMESN9G+VHA/YGEGCmlaIyC6Gd
R7aTrDydSPJ+K54fRYHKXYcyy7UksjaShbwCcp7lq8qY2cvUueuchC8mLI0FPJvUCDFY9bhPeDWK
JXZt4LZmD3B/uq+Jl0UqlAXLs9eJJzynhpfKLgH1sTwmQ6zlUInD91mQguDZrtT8s2TTv8z+ke1a
DiiDtK56K90dCz9ZeAFonengbwFy6EmrRNyj0IzqMF1IfIXQTMATSyxK+3LL/JylP9pBYVGeRLu1
ScJNTLe15Mxx+NOYj9pAa+5SecZhn6/4rDl6ITvm8jglY+DjStaTA3ED0sq9tjCGMeqbTFEM/Mq0
erVAs6NSKTtaKt15HP2Dohok4JG1wsGudOU4RcIYwXRTNoiGzqTmIDAFyKWMzxGd3cYxcXctxX9/
uo+p4QIQC+XOw6HGlJ931C0kVHAvoKlhmjBTS+10EBBGU1//b2cZOxEITxxRjbg2xbA0Gbhes+BY
4kbDb2bMX2yQozoUuCPx0ngWzZNxmoA9csSLVl7gAVZUkCLzTSXO+inrX1GbMoaAjAt+mGp+5eVS
m30aC0xk8QjwJqmZqwQz2xiLBLRqTiYMPb+mH9cBN7UgRxp7pw1mgsgTNjmEjDT/0SvDbUuSGcej
aIbVeCAyJ32TOjkzbKDYccFFOcCHbOMacz5HyQpMQgc6idOrdebmTM12fAru/Mu0T9C8w5kf9FZT
M3woCgfOTpQhrswuCB3kvsYCzCncQL2BE5Rsw1P84/kgNfR+sSFNugy6kFyN1yno3ur6JtsH4EUn
yO7n21QnpbvVE7jf2llPNkSZZ5Iw7PD3r+diZX3avI4yda0P1E5JxuxfLVvK0oSmVNyJrtsDIE2E
HmDx3J3w536qmRz7UXBn3C7rYGGZs5gXTxFQhIHOc64Ox3eygWU/S2ZKteJ8LzZXBPBzWjj5feWO
H8aFZS6d9y5OOdnGuwJnbSW/cSFD96fJrvN42wgbnEPTwySP+g/gVfctI1wwYPnHk32vZQgF4H17
kX9pgrPPEJCtmBsfc0BA9HbrDt/IWBMyP1QDF0TGyYL766V3TSPXkTjK3IuA8y7pzxnD7V+jxbAO
kzjbhI0Kn7tuIb8ogB1YLzOI0ywqV6Y6tAmLDy2PWKDRam6I9oXEwI0fYKzLisb6Js/WM6/91vN6
w8a+OeKKtmF1PLVyEYPJukm4jrR/2j8PnX5rqCXwQVomraG7Gqzv1P2kLO1THK1ml5eViqELuMQh
VvGE0OBueqSlSsJA63hmrbsxb/uNI5pyWdGx9KBvk9GHCcVw8Qa2POihO7t4DkYTH0r+yHbC+gj5
lMl/lT2QuJHFuDegdW7DJPx8fPbrZXkMr7k+X1Ug+1UB9YggxkVFLf4uBEOGLc1qSqG8+NSckuBV
IOY9ihA4oB4V257L5QmxHeGk3BktdpBuKQr+HRPLl1fgPdCu8So9ybCLNBuBL+E6uqBWMii//WMd
wmnqk67bt1DmuuDQqgHjNUzSSjrZUOmNgpKqbD6npzB3yl8nC42a+n0QpaPjT/smnd+Z6Em+uyht
9t2BV5CFd7eICPhgyeLtlO1BiRHrhyf8G32KJmHcGxHysG7vXpE72z8uUvUIj9ZfWT3ZI5/oKYt2
SvP6N0EZflfvJbVcI7ojFemX60G2qJP8To/fv1pPmiCRzNF+jGabHbwQ/gspG22q7t+wNq8oF/eq
XtjjnhpT3hqVnJ4XOs1WAhh1oLs12aHkwrXjj8Kwk+VvjA2VZqo5WOpqGGBAbZn0Pf0B6WTihaz4
PdOBPzGOK29wO06lJ0cOlieki/bcDKZ4C3/ggJIm8V6xw36QYWsNFWDljdfb8Nz2+DzcRuKuJ4xk
FXbpv5doHN3QwCqhWTdFz7WfHDul3EWWuaN/r+k/FtJFUS867ScyULoqPafqSGzwMHwgpaVtfT4s
X5YKI7f3vPK4f7bQqIOaMUxoX6iL8ShFIb+bZghxhEMxANc0MSrnOVxkNFm45eITrQjIxQ4pRZV5
m/+pocblXBph2M8E4HavO5irPKu2RXxQziJrIsBzjha6GjxgJh+QgBIn09hbsTG5S7eMwQu3fzpF
0ZwcTqhg+0iSPUhjsbEX2Ev/EFv2jbAUemtVrTxRojXX5ywmFCTIrGACNyIzoCzPtHyHjYEs9G08
OQfN2qvfhBGZZw1TITCSKssq0IHZs6MBYk7gTGK6HC/E/9HHBehoo4t030YrlWxDZ10HeZNc6HmL
kKspX4/0s+wj4G6qh6wx2v9IT24R9vTx5UCwzF5otHxqKEHowvFhPDKnf1B3/k+WIHDXBhn7xE+Y
JAcbCOWqSUbj+YRaowu0NouDoa34N+ypq7m+Zjo9pMfu880SsKekFwcgjhEZ/gaoslKK+yudt9EC
NF3dy4M5K3A9AMGw4Mipq7XRF60xYEPbQEyjSj3Uvck0wklCpBoccorgr9JA/3cDSIT8Dxp3yloJ
cPDacUeRBcTvGW1gnz0FxZmnZNE+6zRdSEbcNy6xvfFfjRRkh/B7FqKJyWTiM0dCrycPvP8vwvCj
m/MwDlkR386Wq95DobRF6Maub8rABBku+z/UCp8fgGkvNl29TVpD01ANanMdIPVdpYFSXIc2A8MS
9JOeRTLuo4WjWaSZpYlMC6YPvzbbds8rwlY+8SBNXnUKDD5oDcSoBJeyEdTjqmU8oWkuaN7SCMry
uk3J3HplIIS/xr8JuvByw7bHcDYziCWL+Ssjgvcrrbh3Pm4a66nqF+BOBxcc1ws2+uc2C1orhp04
THt1HuzqA1RaqXf55tL/IscqbQj7+LcuVdym7u6Y8rYs4VB0vEUFJpXx7FJ9h/nyExmi5LwAzDs0
X9Cjl5IBCovFu/qHv9Kk8PUMUu7XuslxrbXCKqWVii7ttd4927C8RxhZBGuIY9o+Af/0M2BlSdL6
OC22iaT0WMUBOEm4FAko3z4SNCgCgcadtocktNO1M4FjzQJ+tnAm2asu2TrQTppg8F0R1Z6wc5tf
mbNsVF7mOgYCwzDaSb6BsmoPCuCBaWzBwSEjk0mUQCjAsEhN1cfmAq/LPUbMG8KtN5u9NmmB1jSW
t617AtXy5wgc0m5akVo5G5CqQV6TKVIMAKUDRXZ7vPvv1qBcBnc9+LsYX5Zhspz1KopCqpy3Lqwu
re4QavJZbcr5p8HDg0lETRGjz+mGukzPtZ/WsAD9NyG9gkl11znBDl6M4RwmQPe4NVN/pdLeHzSg
+0i2BMdolGPLneMpdIbXqZlBi/FiNppmgxMDbRiR4vDsmKQRgTQdzxO2Jd2RvFk3db0kbqu0Sa4V
aMaZ4F0xbOy6Se7fXQMx7BWIuVmchQMFHzs8DRHOBHr0cmyS3VKaF1TPEToIfWFWNg+dISLv6ksF
sFKnh9hrCtWlRSoc5RmEDNwSlLYcf2xD9EmqF8cqlWFQrhzbNTsF9qM7CT7YDSIEvnJZDKBLUDRg
OmnOMns6rHoe2IrZNiwEAgvH9q7Y7kayfmZQS6A4kXodDlEPxu49HwME8iRfbSDHd0AZYDVjoleG
ccF8mfi5NocqNaQJpbxg3bbNU/kqYfNlzmN4Y3l6HKbdQwG3JIsC9LWl6t3gHI5Vy77vFkvf34oE
2nM0Anyn1QzuW7CMUyMo39WewwTruMos7SjCnn5qsa2+PH20iBwScVotruGZ64A9gfhUePYKy3dz
RTw/+6rp0LqaU9nkJhqsxPYdp8ucRebtFJw8zBCGh+fr6/h13Nsy2Xy1ek0Buc+Q0ccszGxJffAj
tO6liaqh3vVqjk2Jw4v8tBXHAEpPDJ0Np2nEiueu61JwLiOuSERmEFp/OlbhcmBoAHoQav9XZBw6
YZJeTedwZ4anCGmjsFS8Ae1E3ufBgIFU08J1kG05YNj7ROrxADqDOfNTTpOns/vW0XoXro2wR/sP
LqfbehKiPMYox4PS1jeFGC2bDMn4/1pfHNPYsfL5AEbNiTcfB2rBLXnfPwt9DwGLu2jwZhjGsPpa
DnaRji6JbJmU1BUBLAajCtgrn8rJGXAvnvF3AtU4y2c0tdfygTBlMHfFYrLXPzZLoQ0oQb4HnXgF
Z0SFM3cdCoNHI/bG3Af+vQNVsFnyph4ecCzHSBvcYInmSER00re4rnFYJD4v+9TI7KDZsoTuCGu5
mvnMNNqZVV95Z5tGR4FTJrD1YfzlsNbV9JhIRLMpwg7M8vDqfvq6QqP4Dh/uO2UPfV1QzH14+ItT
zJn47GupE9HIFQ0hCEwDmQjFcfiEkL3wU13PoSCwX8cG6kjk2tKIIyEKdfVw1ZT1PwsRyhp53en5
y/lVF2MtQkuYl+Y60xYoa0iR6qdmryXX9OiBBNmYy8ZS8GGt3ArvAsmGIV12Q66MKxOHxdSH5hb2
uaC6iVcGF24iOkndTmUNsrzxmHI7OPNRJx82fpkl7pe9tywZtTVlLE0JEBeY3kPCUQI3Ij37FlFa
Ej7kvpSHhi79MCBO69uSUvi4tzehpHYR6ebmlDtW6E3HjRyM3/xDeyWXwdGWlsBup6RrJ0LYhmaT
yWik1/OzVAeBVUlH/aiyBvrQMkAGeLqBsPjGkg0XEP77Mz2/hyVNuAieBPhd4gZBezB6p9w1jbd5
qL5O3tEtshT884p+7BEsNil+0IYvBnP39H1rv2vt9m1QZPjSmt5TTtTOLyyqEq/1hKNhG9SFkUln
iN1LNmaBCBuS7XgLAvqKz0z4jcRvwOGjarhSg5nNiMd8IDtOkZjiqtz5eKgEZKn8dvvo6xFN1gsc
QniLLjHe5FJCH85sW6yebbr6rR8JRISXpXgkRqDK
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QLOOoKlGeTs3w0jXG0JqRwtHZ6ZjMLpVm5gbg83RVaMB6qCMyHD5NAuvGh/R1T6ZlQp0NMh7Bnk2
5AdHD7cJjA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oiLZfYUeAPLDA1mPt1oWE8FJuiWI9nQq70AHCVDv7/+/ko3oL+RM55qvzg78ir0IIow9o1QQnZzi
/QnPM3je+PmrMbklYC8hbnc/6WwoYTDYWBjwmnT4WuTu79zT5Dz2iwvQ7UO87XDo6Vccxhk/KNba
ZrIF5dUtbh9SBfEo1pc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHdof/KFp2koF/o91nEi7LW4+89e3FRu/nu4NfaWjoFf23t/IPwz0N/ZySSZXeZj7NpcOCWZtivU
DSFNkcNUoxn1xhwZjydQXsRPzt7zggpp1RwvhW+chmFxHP6jaXMEqUkO5g6sEZrtVQtnMb5nqceA
2nqbftFy9y4Jt7UmohJJDYMVVeIXLbWZ+sM9wnfgB7VManZH1vBNIzUmC7EzVRugcadqTAPkQuML
c+Zvth8zYTGwbqF7L7DymzQB8U0Jap19ompCBbL4q3fT1HLAOoCqWtUDTR7MfugbLBGTA07mp/hW
apZVGF7Ua5AJ+LWqKRW3am2rKk+mVP16uzjX2g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cQW6+AQd3QOZ1YlcrM/LQugKHjz+MqOUuR5a7MVb+w/h0VQ2EpwCS5QaTg5R6MyncLujB8RUugJT
TvCpchFxnZKs10+1mFZC2KrxQFUIaFzvxV/edf3kLHqviBvAcROXFgSetBEx4AKxc/qvQlm8TYvH
FrL3s45jp51A+vkmnio=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nKmftmxJaLdDTM8ApbRpeOSEHVHDWxzh224hvKHxX106ZVfuSqNl6gPbiSpYnnR+hX/i6n0KWBzO
TP+ubtn7uZgVs+/SfxIy3/Sdm0XgcPm9XNcKemx6b5YMwbBewBHzaMu0r1SlSZZn1kPD1zp7f3Kq
IbDj+od/lSq1wO/ibX6+NVPKJDfdGA5UBJAJ9ilvb44fl5kcPiTZ9MEMDFejktkyD1kuL0Yo5hTT
EjD4BJ5PwJzHRhFo+XbaTkDvpT+ZbuwQUta1UAU1w8L4yXTcvQ3sK/w+bsHey1SeQdRQsQojNILe
OocVq6DYPk84FzehGQJInNjaO2duAcIei9xAKg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
oV0B01WlfOfwc65hHQyPonQOH8xjSJSgdAwbXD5rL4TD4D111/TiNKKXxh6TgXHovRC940qcZar9
P0mrOXcGDb/l2ZGaJjjXyKNi5MBEu6Iz5vo+vUigHa8Q0I5PjyUaKP8USieT+4j0BY5gj2y49aJe
1fSdSw/c9SyioHSzXLkOy0phkEkqYlG89kyPzsR1nXbOJOl35IppKY8VT/r6om9zCQUvHUpVeg4u
3S39qOWVv9lp5GZPzBynEGS1mdxeRm0dyrwFAETJRcG0+4ZuE46JhOhoaeOfRIW721WML0VXdcm6
0YIj22eWcgH2egIeQmsKb6w5wJ2A4aZabT+buWSaW+Sc4WLOHXI3AYz/HR5XOxuLgMmNOzl9TT9A
ANdcF/hDKi3osGFrWlL0sAaJHW3b+6YTsk8uy3ToimYkLrX/KAG8soVNDkeIn2m3MxqzyY/cSIEN
AHmTuJRDZPxlFUq+iHv07Mw2gbguTBxunDhPG5PE1kBt+iZzs/sLDBXifMknSWVQnGEu2ETYLlBS
Ye2TyR3xhUHadhzodOtneytHnFyMDd4TsYz/Ym1AmcxH9iAhoGQS5EzBDW6FfgKLprFOCNlr3Ogz
8E8rRzZnkS3Scu2mA1zieEAXOONeEVxrB4WBdJYY3CtVsUqdc+QGUaN2Cg/tt0NGtsbPFwPYb8x9
Ok1aXiaTk87Eqn7ObpCQA5wvvZut9TEWUeDtVf7nw1MQchDRWGJZFgfo8zNRT1JBkxYNaStRxHcv
NXyZwIFpzJ9l8g9fLizHUNqHMsyQ0D0uXDHYWr+jjN61Tmoi3eSW09/mq20lwL8pHO880Bfjifz+
7FgrOP0ARh3sZ6TmAHCuSFx+g9BWZp6nEJufaLG4X8IC3sXzJiTOU4octt/xU8km5N4jpytU7fVQ
Zs8YbzubQKrRhIVZJNKbeM9HdJijNja0AwRf2Yvp7qEk4KEWisWO6OtSGUgnUa+rQaYWjBs6Hcu1
xGSB0zV1RR2+w9uifUNuJN3WU+HTl1QVQrFP8NSa0AcTQ6Or0x1JKGS44F9sQiPavST55BbJYocE
t6NXd9TYhcX6fSQ5/gr8OwRTCOW5cEPPimy0vFeTR/vcobN1cLVSwGysZp3lv0NO6x51vdQnsKqH
X4BYhXGHxZgFUmMNK/rCm19l2SQBr1DWeRaKfy5/0oM2oqTUCIiMPgoyt6j0wHejsJqWPwHWciX5
YnV4ZZETzLBuC7GCswQ5W1eP3/c1Stk5xr+yTWQoa+IXI6526qt+b+Ywx7j+vrd2+N8irEXwnVTV
hGiVZvkZ0978ypphj56l54i54mKlUJXNMl0R7P3yrb2og9MyxruSax8EtyN3iMyYwDCyIFLXHwab
hghXFA3mIU5foJXDtbK3p9iwK6ZpEAxNyFGWGfjdCGF0z10jqZxQ9WW75RrmW3cZ8+ZM0OijutFg
WZrpAsygehs9uCDzh/Oh2KhSo6D8qM3spREZbYYG/Yl6o6D1H24ehSmZBqSfQll46XcUjMMBQgT3
98Ku1C5uc5UFP0ryVbJz0660n/QFhOReefgVDk+hU6VC+l7+AehVTd7TyX6anmDnl4NGYeIgCbZh
WTQ+TrrdM7k+uVrwlpE5iD2v9Hk084hKc5d/0tH8p5arGpowpoBDmtLsuxoNNDS7oqC/3dMkI5Ke
cFykzmAcIlb98bfnmfy/MzCN83VQsxlKFtgZd3AIeFtZtXAoiukHZzFEw8aic7fEyiBlHXiJ0Zzs
q43M/XitituQuBR+fqaFYzwcJ9G3NnETXWDoDffFwIyn1f4wQX76/UU/vuwfLtY5kfPrtskvpwn6
ZpuqQK0nQyfJXwbLkFEnmpJ1YsZd5+c6EBr7zLKSP+BUtjC7Zz14Lh01Pz7YsmuD6l9H8VpdPdBX
SFKjmOnaEU3aQpxJmOVIaogz6qO2ce/TJaEukKXi4+ntHRT+WLoAESyShmgw7OL5d7P/AQcbanTC
tJkUWHRSoqWMHb0rD1kXjp/bUEpoQ0pLgtfuDuHr5eOREbkMDESDJJ6pET7GBLmcokobCqtgWejU
/kXJU5yFNQ4/5qZFfB4vqbnAEgeXciv+KKRnzrj4LGQ06EpS8t306C41Qxf4ogh/vs7IeejABz4D
1IPDXwm5jJFMCMU2dsZLzx2u2sqgNE1N875is4kUmkeFmfsxDV/R5M2kQFGlXkrnn/4jD1MoPAZy
oGJe2CEOUEzyCC9H0FzHpTzKr5flgZ2XfCH1SreaysB4UIA41/00cwT4z+PXoK9MWAyebelcO0yC
rJFEyf/W+gtIBK0O3yklP5gwSsiK4felu3Vz1/UqqZ7y9HtSYCUevDup9xONpLe3F8cnjNNDRgl+
acMuPH9ATgxJIzHKhjLWt/hT4c1J64Ov8rCPbvko8BNyhak6sThbusbkCAbXJkvhD6SHfYgeJn5u
aJfFRDez2gajS57Px2QFyMvW42v0+fF2+lZPa3TYqIDqhVpxPyyNcfeIGZwUvw/q3hX4go2g8zTu
WnNAb+whbq1LM/qgtvFqECDm27Kq9B8YLATQVQ7zFqm+n4vdP+ViRvspNy3uh6aRiH+bj5ll3+TE
Ud88Sr0pZnRdc9mt7eDujN/lSyPTxhhtDRkd/E5UIQYrUUwr6JC5qf+0pfsPILtuxWw59fVZzRjv
oCckP8slbojSDY9sG7buIVgOnN1vF9Q8lCvBSeXxi54Mspv+QZmMESN9G+VHA/YGEGCmlaIyC6Gd
R7aTrDydSPJ+K54fRYHKXYcyy7UksjaShbwCcp7lq8qY2cvUueuchC8mLI0FPJvUCDFY9bhPeDWK
JXZt4LZmD3B/uq+Jl0UqlAXLs9eJJzynhpfKLgH1sTwmQ6zlUInD91mQguDZrtT8s2TTv8z+ke1a
DiiDtK56K90dCz9ZeAFonengbwFy6EmrRNyj0IzqMF1IfIXQTMATSyxK+3LL/JylP9pBYVGeRLu1
ScJNTLe15Mxx+NOYj9pAa+5SecZhn6/4rDl6ITvm8jglY+DjStaTA3ED0sq9tjCGMeqbTFEM/Mq0
erVAs6NSKTtaKt15HP2Dohok4JG1wsGudOU4RcIYwXRTNoiGzqTmIDAFyKWMzxGd3cYxcXctxX9/
uo+p4QIQC+XOw6HGlJ931C0kVHAvoKlhmjBTS+10EBBGU1//b2cZOxEITxxRjbg2xbA0Gbhes+BY
4kbDb2bMX2yQozoUuCPx0ngWzZNxmoA9csSLVl7gAVZUkCLzTSXO+inrX1GbMoaAjAt+mGp+5eVS
m30aC0xk8QjwJqmZqwQz2xiLBLRqTiYMPb+mH9cBN7UgRxp7pw1mgsgTNjmEjDT/0SvDbUuSGcej
aIbVeCAyJ32TOjkzbKDYccFFOcCHbOMacz5HyQpMQgc6idOrdebmTM12fAru/Mu0T9C8w5kf9FZT
M3woCgfOTpQhrswuCB3kvsYCzCncQL2BE5Rsw1P84/kgNfR+sSFNugy6kFyN1yno3ur6JtsH4EUn
yO7n21QnpbvVE7jf2llPNkSZZ5Iw7PD3r+diZX3avI4yda0P1E5JxuxfLVvK0oSmVNyJrtsDIE2E
HmDx3J3w536qmRz7UXBn3C7rYGGZs5gXTxFQhIHOc64Ox3eygWU/S2ZKteJ8LzZXBPBzWjj5feWO
H8aFZS6d9y5OOdnGuwJnbSW/cSFD96fJrvN42wgbnEPTwySP+g/gVfctI1wwYPnHk32vZQgF4H17
kX9pgrPPEJCtmBsfc0BA9HbrDt/IWBMyP1QDF0TGyYL766V3TSPXkTjK3IuA8y7pzxnD7V+jxbAO
kzjbhI0Kn7tuIb8ogB1YLzOI0ywqV6Y6tAmLDy2PWKDRam6I9oXEwI0fYKzLisb6Js/WM6/91vN6
w8a+OeKKtmF1PLVyEYPJukm4jrR/2j8PnX5rqCXwQVomraG7Gqzv1P2kLO1THK1ml5eViqELuMQh
VvGE0OBueqSlSsJA63hmrbsxb/uNI5pyWdGx9KBvk9GHCcVw8Qa2POihO7t4DkYTH0r+yHbC+gj5
lMl/lT2QuJHFuDegdW7DJPx8fPbrZXkMr7k+X1Ug+1UB9YggxkVFLf4uBEOGLc1qSqG8+NSckuBV
IOY9ihA4oB4V257L5QmxHeGk3BktdpBuKQr+HRPLl1fgPdCu8So9ybCLNBuBL+E6uqBWMii//WMd
wmnqk67bt1DmuuDQqgHjNUzSSjrZUOmNgpKqbD6npzB3yl8nC42a+n0QpaPjT/smnd+Z6Em+uyht
9t2BV5CFd7eICPhgyeLtlO1BiRHrhyf8G32KJmHcGxHysG7vXpE72z8uUvUIj9ZfWT3ZI5/oKYt2
SvP6N0EZflfvJbVcI7ojFemX60G2qJP8To/fv1pPmiCRzNF+jGabHbwQ/gspG22q7t+wNq8oF/eq
XtjjnhpT3hqVnJ4XOs1WAhh1oLs12aHkwrXjj8Kwk+VvjA2VZqo5WOpqGGBAbZn0Pf0B6WTihaz4
PdOBPzGOK29wO06lJ0cOlieki/bcDKZ4C3/ggJIm8V6xw36QYWsNFWDljdfb8Nz2+DzcRuKuJ4xk
FXbpv5doHN3QwCqhWTdFz7WfHDul3EWWuaN/r+k/FtJFUS867ScyULoqPafqSGzwMHwgpaVtfT4s
X5YKI7f3vPK4f7bQqIOaMUxoX6iL8ShFIb+bZghxhEMxANc0MSrnOVxkNFm45eITrQjIxQ4pRZV5
m/+pocblXBph2M8E4HavO5irPKu2RXxQziJrIsBzjha6GjxgJh+QgBIn09hbsTG5S7eMwQu3fzpF
0ZwcTqhg+0iSPUhjsbEX2Ev/EFv2jbAUemtVrTxRojXX5ywmFCTIrGACNyIzoCzPtHyHjYEs9G08
OQfN2qvfhBGZZw1TITCSKssq0IHZs6MBYk7gTGK6HC/E/9HHBehoo4t030YrlWxDZ10HeZNc6HmL
kKspX4/0s+wj4G6qh6wx2v9IT24R9vTx5UCwzF5otHxqKEHowvFhPDKnf1B3/k+WIHDXBhn7xE+Y
JAcbCOWqSUbj+YRaowu0NouDoa34N+ypq7m+Zjo9pMfu880SsKekFwcgjhEZ/gaoslKK+yudt9EC
NF3dy4M5K3A9AMGw4Mipq7XRF60xYEPbQEyjSj3Uvck0wklCpBoccorgr9JA/3cDSIT8Dxp3yloJ
cPDacUeRBcTvGW1gnz0FxZmnZNE+6zRdSEbcNy6xvfFfjRRkh/B7FqKJyWTiM0dCrycPvP8vwvCj
m/MwDlkR386Wq95DobRF6Maub8rABBku+z/UCp8fgGkvNl29TVpD01ANanMdIPVdpYFSXIc2A8MS
9JOeRTLuo4WjWaSZpYlMC6YPvzbbds8rwlY+8SBNXnUKDD5oDcSoBJeyEdTjqmU8oWkuaN7SCMry
uk3J3HplIIS/xr8JuvByw7bHcDYziCWL+Ssjgvcrrbh3Pm4a66nqF+BOBxcc1ws2+uc2C1orhp04
THt1HuzqA1RaqXf55tL/IscqbQj7+LcuVdym7u6Y8rYs4VB0vEUFJpXx7FJ9h/nyExmi5LwAzDs0
X9Cjl5IBCovFu/qHv9Kk8PUMUu7XuslxrbXCKqWVii7ttd4927C8RxhZBGuIY9o+Af/0M2BlSdL6
OC22iaT0WMUBOEm4FAko3z4SNCgCgcadtocktNO1M4FjzQJ+tnAm2asu2TrQTppg8F0R1Z6wc5tf
mbNsVF7mOgYCwzDaSb6BsmoPCuCBaWzBwSEjk0mUQCjAsEhN1cfmAq/LPUbMG8KtN5u9NmmB1jSW
t617AtXy5wgc0m5akVo5G5CqQV6TKVIMAKUDRXZ7vPvv1qBcBnc9+LsYX5Zhspz1KopCqpy3Lqwu
re4QavJZbcr5p8HDg0lETRGjz+mGukzPtZ/WsAD9NyG9gkl11znBDl6M4RwmQPe4NVN/pdLeHzSg
+0i2BMdolGPLneMpdIbXqZlBi/FiNppmgxMDbRiR4vDsmKQRgTQdzxO2Jd2RvFk3db0kbqu0Sa4V
aMaZ4F0xbOy6Se7fXQMx7BWIuVmchQMFHzs8DRHOBHr0cmyS3VKaF1TPEToIfWFWNg+dISLv6ksF
sFKnh9hrCtWlRSoc5RmEDNwSlLYcf2xD9EmqF8cqlWFQrhzbNTsF9qM7CT7YDSIEvnJZDKBLUDRg
OmnOMns6rHoe2IrZNiwEAgvH9q7Y7kayfmZQS6A4kXodDlEPxu49HwME8iRfbSDHd0AZYDVjoleG
ccF8mfi5NocqNaQJpbxg3bbNU/kqYfNlzmN4Y3l6HKbdQwG3JIsC9LWl6t3gHI5Vy77vFkvf34oE
2nM0Anyn1QzuW7CMUyMo39WewwTruMos7SjCnn5qsa2+PH20iBwScVotruGZ64A9gfhUePYKy3dz
RTw/+6rp0LqaU9nkJhqsxPYdp8ucRebtFJw8zBCGh+fr6/h13Nsy2Xy1ek0Buc+Q0ccszGxJffAj
tO6liaqh3vVqjk2Jw4v8tBXHAEpPDJ0Np2nEiueu61JwLiOuSERmEFp/OlbhcmBoAHoQav9XZBw6
YZJeTedwZ4anCGmjsFS8Ae1E3ufBgIFU08J1kG05YNj7ROrxADqDOfNTTpOns/vW0XoXro2wR/sP
LqfbehKiPMYox4PS1jeFGC2bDMn4/1pfHNPYsfL5AEbNiTcfB2rBLXnfPwt9DwGLu2jwZhjGsPpa
DnaRji6JbJmU1BUBLAajCtgrn8rJGXAvnvF3AtU4y2c0tdfygTBlMHfFYrLXPzZLoQ0oQb4HnXgF
Z0SFM3cdCoNHI/bG3Af+vQNVsFnyph4ecCzHSBvcYInmSER00re4rnFYJD4v+9TI7KDZsoTuCGu5
mvnMNNqZVV95Z5tGR4FTJrD1YfzlsNbV9JhIRLMpwg7M8vDqfvq6QqP4Dh/uO2UPfV1QzH14+ItT
zJn47GupE9HIFQ0hCEwDmQjFcfiEkL3wU13PoSCwX8cG6kjk2tKIIyEKdfVw1ZT1PwsRyhp53en5
y/lVF2MtQkuYl+Y60xYoa0iR6qdmryXX9OiBBNmYy8ZS8GGt3ArvAsmGIV12Q66MKxOHxdSH5hb2
uaC6iVcGF24iOkndTmUNsrzxmHI7OPNRJx82fpkl7pe9tywZtTVlLE0JEBeY3kPCUQI3Ij37FlFa
Ej7kvpSHhi79MCBO69uSUvi4tzehpHYR6ebmlDtW6E3HjRyM3/xDeyWXwdGWlsBup6RrJ0LYhmaT
yWik1/OzVAeBVUlH/aiyBvrQMkAGeLqBsPjGkg0XEP77Mz2/hyVNuAieBPhd4gZBezB6p9w1jbd5
qL5O3tEtshT884p+7BEsNil+0IYvBnP39H1rv2vt9m1QZPjSmt5TTtTOLyyqEq/1hKNhG9SFkUln
iN1LNmaBCBuS7XgLAvqKz0z4jcRvwOGjarhSg5nNiMd8IDtOkZjiqtz5eKgEZKn8dvvo6xFN1gsc
QniLLjHe5FJCH85sW6yebbr6rR8JRISXpXgkRqDK
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QLOOoKlGeTs3w0jXG0JqRwtHZ6ZjMLpVm5gbg83RVaMB6qCMyHD5NAuvGh/R1T6ZlQp0NMh7Bnk2
5AdHD7cJjA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oiLZfYUeAPLDA1mPt1oWE8FJuiWI9nQq70AHCVDv7/+/ko3oL+RM55qvzg78ir0IIow9o1QQnZzi
/QnPM3je+PmrMbklYC8hbnc/6WwoYTDYWBjwmnT4WuTu79zT5Dz2iwvQ7UO87XDo6Vccxhk/KNba
ZrIF5dUtbh9SBfEo1pc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHdof/KFp2koF/o91nEi7LW4+89e3FRu/nu4NfaWjoFf23t/IPwz0N/ZySSZXeZj7NpcOCWZtivU
DSFNkcNUoxn1xhwZjydQXsRPzt7zggpp1RwvhW+chmFxHP6jaXMEqUkO5g6sEZrtVQtnMb5nqceA
2nqbftFy9y4Jt7UmohJJDYMVVeIXLbWZ+sM9wnfgB7VManZH1vBNIzUmC7EzVRugcadqTAPkQuML
c+Zvth8zYTGwbqF7L7DymzQB8U0Jap19ompCBbL4q3fT1HLAOoCqWtUDTR7MfugbLBGTA07mp/hW
apZVGF7Ua5AJ+LWqKRW3am2rKk+mVP16uzjX2g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cQW6+AQd3QOZ1YlcrM/LQugKHjz+MqOUuR5a7MVb+w/h0VQ2EpwCS5QaTg5R6MyncLujB8RUugJT
TvCpchFxnZKs10+1mFZC2KrxQFUIaFzvxV/edf3kLHqviBvAcROXFgSetBEx4AKxc/qvQlm8TYvH
FrL3s45jp51A+vkmnio=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nKmftmxJaLdDTM8ApbRpeOSEHVHDWxzh224hvKHxX106ZVfuSqNl6gPbiSpYnnR+hX/i6n0KWBzO
TP+ubtn7uZgVs+/SfxIy3/Sdm0XgcPm9XNcKemx6b5YMwbBewBHzaMu0r1SlSZZn1kPD1zp7f3Kq
IbDj+od/lSq1wO/ibX6+NVPKJDfdGA5UBJAJ9ilvb44fl5kcPiTZ9MEMDFejktkyD1kuL0Yo5hTT
EjD4BJ5PwJzHRhFo+XbaTkDvpT+ZbuwQUta1UAU1w8L4yXTcvQ3sK/w+bsHey1SeQdRQsQojNILe
OocVq6DYPk84FzehGQJInNjaO2duAcIei9xAKg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
oV0B01WlfOfwc65hHQyPonQOH8xjSJSgdAwbXD5rL4TD4D111/TiNKKXxh6TgXHovRC940qcZar9
P0mrOXcGDb/l2ZGaJjjXyKNi5MBEu6Iz5vo+vUigHa8Q0I5PjyUaKP8USieT+4j0BY5gj2y49aJe
1fSdSw/c9SyioHSzXLkOy0phkEkqYlG89kyPzsR1nXbOJOl35IppKY8VT/r6om9zCQUvHUpVeg4u
3S39qOWVv9lp5GZPzBynEGS1mdxeRm0dyrwFAETJRcG0+4ZuE46JhOhoaeOfRIW721WML0VXdcm6
0YIj22eWcgH2egIeQmsKb6w5wJ2A4aZabT+buWSaW+Sc4WLOHXI3AYz/HR5XOxuLgMmNOzl9TT9A
ANdcF/hDKi3osGFrWlL0sAaJHW3b+6YTsk8uy3ToimYkLrX/KAG8soVNDkeIn2m3MxqzyY/cSIEN
AHmTuJRDZPxlFUq+iHv07Mw2gbguTBxunDhPG5PE1kBt+iZzs/sLDBXifMknSWVQnGEu2ETYLlBS
Ye2TyR3xhUHadhzodOtneytHnFyMDd4TsYz/Ym1AmcxH9iAhoGQS5EzBDW6FfgKLprFOCNlr3Ogz
8E8rRzZnkS3Scu2mA1zieEAXOONeEVxrB4WBdJYY3CtVsUqdc+QGUaN2Cg/tt0NGtsbPFwPYb8x9
Ok1aXiaTk87Eqn7ObpCQA5wvvZut9TEWUeDtVf7nw1MQchDRWGJZFgfo8zNRT1JBkxYNaStRxHcv
NXyZwIFpzJ9l8g9fLizHUNqHMsyQ0D0uXDHYWr+jjN61Tmoi3eSW09/mq20lwL8pHO880Bfjifz+
7FgrOP0ARh3sZ6TmAHCuSFx+g9BWZp6nEJufaLG4X8IC3sXzJiTOU4octt/xU8km5N4jpytU7fVQ
Zs8YbzubQKrRhIVZJNKbeM9HdJijNja0AwRf2Yvp7qEk4KEWisWO6OtSGUgnUa+rQaYWjBs6Hcu1
xGSB0zV1RR2+w9uifUNuJN3WU+HTl1QVQrFP8NSa0AcTQ6Or0x1JKGS44F9sQiPavST55BbJYocE
t6NXd9TYhcX6fSQ5/gr8OwRTCOW5cEPPimy0vFeTR/vcobN1cLVSwGysZp3lv0NO6x51vdQnsKqH
X4BYhXGHxZgFUmMNK/rCm19l2SQBr1DWeRaKfy5/0oM2oqTUCIiMPgoyt6j0wHejsJqWPwHWciX5
YnV4ZZETzLBuC7GCswQ5W1eP3/c1Stk5xr+yTWQoa+IXI6526qt+b+Ywx7j+vrd2+N8irEXwnVTV
hGiVZvkZ0978ypphj56l54i54mKlUJXNMl0R7P3yrb2og9MyxruSax8EtyN3iMyYwDCyIFLXHwab
hghXFA3mIU5foJXDtbK3p9iwK6ZpEAxNyFGWGfjdCGF0z10jqZxQ9WW75RrmW3cZ8+ZM0OijutFg
WZrpAsygehs9uCDzh/Oh2KhSo6D8qM3spREZbYYG/Yl6o6D1H24ehSmZBqSfQll46XcUjMMBQgT3
98Ku1C5uc5UFP0ryVbJz0660n/QFhOReefgVDk+hU6VC+l7+AehVTd7TyX6anmDnl4NGYeIgCbZh
WTQ+TrrdM7k+uVrwlpE5iD2v9Hk084hKc5d/0tH8p5arGpowpoBDmtLsuxoNNDS7oqC/3dMkI5Ke
cFykzmAcIlb98bfnmfy/MzCN83VQsxlKFtgZd3AIeFtZtXAoiukHZzFEw8aic7fEyiBlHXiJ0Zzs
q43M/XitituQuBR+fqaFYzwcJ9G3NnETXWDoDffFwIyn1f4wQX76/UU/vuwfLtY5kfPrtskvpwn6
ZpuqQK0nQyfJXwbLkFEnmpJ1YsZd5+c6EBr7zLKSP+BUtjC7Zz14Lh01Pz7YsmuD6l9H8VpdPdBX
SFKjmOnaEU3aQpxJmOVIaogz6qO2ce/TJaEukKXi4+ntHRT+WLoAESyShmgw7OL5d7P/AQcbanTC
tJkUWHRSoqWMHb0rD1kXjp/bUEpoQ0pLgtfuDuHr5eOREbkMDESDJJ6pET7GBLmcokobCqtgWejU
/kXJU5yFNQ4/5qZFfB4vqbnAEgeXciv+KKRnzrj4LGQ06EpS8t306C41Qxf4ogh/vs7IeejABz4D
1IPDXwm5jJFMCMU2dsZLzx2u2sqgNE1N875is4kUmkeFmfsxDV/R5M2kQFGlXkrnn/4jD1MoPAZy
oGJe2CEOUEzyCC9H0FzHpTzKr5flgZ2XfCH1SreaysB4UIA41/00cwT4z+PXoK9MWAyebelcO0yC
rJFEyf/W+gtIBK0O3yklP5gwSsiK4felu3Vz1/UqqZ7y9HtSYCUevDup9xONpLe3F8cnjNNDRgl+
acMuPH9ATgxJIzHKhjLWt/hT4c1J64Ov8rCPbvko8BNyhak6sThbusbkCAbXJkvhD6SHfYgeJn5u
aJfFRDez2gajS57Px2QFyMvW42v0+fF2+lZPa3TYqIDqhVpxPyyNcfeIGZwUvw/q3hX4go2g8zTu
WnNAb+whbq1LM/qgtvFqECDm27Kq9B8YLATQVQ7zFqm+n4vdP+ViRvspNy3uh6aRiH+bj5ll3+TE
Ud88Sr0pZnRdc9mt7eDujN/lSyPTxhhtDRkd/E5UIQYrUUwr6JC5qf+0pfsPILtuxWw59fVZzRjv
oCckP8slbojSDY9sG7buIVgOnN1vF9Q8lCvBSeXxi54Mspv+QZmMESN9G+VHA/YGEGCmlaIyC6Gd
R7aTrDydSPJ+K54fRYHKXYcyy7UksjaShbwCcp7lq8qY2cvUueuchC8mLI0FPJvUCDFY9bhPeDWK
JXZt4LZmD3B/uq+Jl0UqlAXLs9eJJzynhpfKLgH1sTwmQ6zlUInD91mQguDZrtT8s2TTv8z+ke1a
DiiDtK56K90dCz9ZeAFonengbwFy6EmrRNyj0IzqMF1IfIXQTMATSyxK+3LL/JylP9pBYVGeRLu1
ScJNTLe15Mxx+NOYj9pAa+5SecZhn6/4rDl6ITvm8jglY+DjStaTA3ED0sq9tjCGMeqbTFEM/Mq0
erVAs6NSKTtaKt15HP2Dohok4JG1wsGudOU4RcIYwXRTNoiGzqTmIDAFyKWMzxGd3cYxcXctxX9/
uo+p4QIQC+XOw6HGlJ931C0kVHAvoKlhmjBTS+10EBBGU1//b2cZOxEITxxRjbg2xbA0Gbhes+BY
4kbDb2bMX2yQozoUuCPx0ngWzZNxmoA9csSLVl7gAVZUkCLzTSXO+inrX1GbMoaAjAt+mGp+5eVS
m30aC0xk8QjwJqmZqwQz2xiLBLRqTiYMPb+mH9cBN7UgRxp7pw1mgsgTNjmEjDT/0SvDbUuSGcej
aIbVeCAyJ32TOjkzbKDYccFFOcCHbOMacz5HyQpMQgc6idOrdebmTM12fAru/Mu0T9C8w5kf9FZT
M3woCgfOTpQhrswuCB3kvsYCzCncQL2BE5Rsw1P84/kgNfR+sSFNugy6kFyN1yno3ur6JtsH4EUn
yO7n21QnpbvVE7jf2llPNkSZZ5Iw7PD3r+diZX3avI4yda0P1E5JxuxfLVvK0oSmVNyJrtsDIE2E
HmDx3J3w536qmRz7UXBn3C7rYGGZs5gXTxFQhIHOc64Ox3eygWU/S2ZKteJ8LzZXBPBzWjj5feWO
H8aFZS6d9y5OOdnGuwJnbSW/cSFD96fJrvN42wgbnEPTwySP+g/gVfctI1wwYPnHk32vZQgF4H17
kX9pgrPPEJCtmBsfc0BA9HbrDt/IWBMyP1QDF0TGyYL766V3TSPXkTjK3IuA8y7pzxnD7V+jxbAO
kzjbhI0Kn7tuIb8ogB1YLzOI0ywqV6Y6tAmLDy2PWKDRam6I9oXEwI0fYKzLisb6Js/WM6/91vN6
w8a+OeKKtmF1PLVyEYPJukm4jrR/2j8PnX5rqCXwQVomraG7Gqzv1P2kLO1THK1ml5eViqELuMQh
VvGE0OBueqSlSsJA63hmrbsxb/uNI5pyWdGx9KBvk9GHCcVw8Qa2POihO7t4DkYTH0r+yHbC+gj5
lMl/lT2QuJHFuDegdW7DJPx8fPbrZXkMr7k+X1Ug+1UB9YggxkVFLf4uBEOGLc1qSqG8+NSckuBV
IOY9ihA4oB4V257L5QmxHeGk3BktdpBuKQr+HRPLl1fgPdCu8So9ybCLNBuBL+E6uqBWMii//WMd
wmnqk67bt1DmuuDQqgHjNUzSSjrZUOmNgpKqbD6npzB3yl8nC42a+n0QpaPjT/smnd+Z6Em+uyht
9t2BV5CFd7eICPhgyeLtlO1BiRHrhyf8G32KJmHcGxHysG7vXpE72z8uUvUIj9ZfWT3ZI5/oKYt2
SvP6N0EZflfvJbVcI7ojFemX60G2qJP8To/fv1pPmiCRzNF+jGabHbwQ/gspG22q7t+wNq8oF/eq
XtjjnhpT3hqVnJ4XOs1WAhh1oLs12aHkwrXjj8Kwk+VvjA2VZqo5WOpqGGBAbZn0Pf0B6WTihaz4
PdOBPzGOK29wO06lJ0cOlieki/bcDKZ4C3/ggJIm8V6xw36QYWsNFWDljdfb8Nz2+DzcRuKuJ4xk
FXbpv5doHN3QwCqhWTdFz7WfHDul3EWWuaN/r+k/FtJFUS867ScyULoqPafqSGzwMHwgpaVtfT4s
X5YKI7f3vPK4f7bQqIOaMUxoX6iL8ShFIb+bZghxhEMxANc0MSrnOVxkNFm45eITrQjIxQ4pRZV5
m/+pocblXBph2M8E4HavO5irPKu2RXxQziJrIsBzjha6GjxgJh+QgBIn09hbsTG5S7eMwQu3fzpF
0ZwcTqhg+0iSPUhjsbEX2Ev/EFv2jbAUemtVrTxRojXX5ywmFCTIrGACNyIzoCzPtHyHjYEs9G08
OQfN2qvfhBGZZw1TITCSKssq0IHZs6MBYk7gTGK6HC/E/9HHBehoo4t030YrlWxDZ10HeZNc6HmL
kKspX4/0s+wj4G6qh6wx2v9IT24R9vTx5UCwzF5otHxqKEHowvFhPDKnf1B3/k+WIHDXBhn7xE+Y
JAcbCOWqSUbj+YRaowu0NouDoa34N+ypq7m+Zjo9pMfu880SsKekFwcgjhEZ/gaoslKK+yudt9EC
NF3dy4M5K3A9AMGw4Mipq7XRF60xYEPbQEyjSj3Uvck0wklCpBoccorgr9JA/3cDSIT8Dxp3yloJ
cPDacUeRBcTvGW1gnz0FxZmnZNE+6zRdSEbcNy6xvfFfjRRkh/B7FqKJyWTiM0dCrycPvP8vwvCj
m/MwDlkR386Wq95DobRF6Maub8rABBku+z/UCp8fgGkvNl29TVpD01ANanMdIPVdpYFSXIc2A8MS
9JOeRTLuo4WjWaSZpYlMC6YPvzbbds8rwlY+8SBNXnUKDD5oDcSoBJeyEdTjqmU8oWkuaN7SCMry
uk3J3HplIIS/xr8JuvByw7bHcDYziCWL+Ssjgvcrrbh3Pm4a66nqF+BOBxcc1ws2+uc2C1orhp04
THt1HuzqA1RaqXf55tL/IscqbQj7+LcuVdym7u6Y8rYs4VB0vEUFJpXx7FJ9h/nyExmi5LwAzDs0
X9Cjl5IBCovFu/qHv9Kk8PUMUu7XuslxrbXCKqWVii7ttd4927C8RxhZBGuIY9o+Af/0M2BlSdL6
OC22iaT0WMUBOEm4FAko3z4SNCgCgcadtocktNO1M4FjzQJ+tnAm2asu2TrQTppg8F0R1Z6wc5tf
mbNsVF7mOgYCwzDaSb6BsmoPCuCBaWzBwSEjk0mUQCjAsEhN1cfmAq/LPUbMG8KtN5u9NmmB1jSW
t617AtXy5wgc0m5akVo5G5CqQV6TKVIMAKUDRXZ7vPvv1qBcBnc9+LsYX5Zhspz1KopCqpy3Lqwu
re4QavJZbcr5p8HDg0lETRGjz+mGukzPtZ/WsAD9NyG9gkl11znBDl6M4RwmQPe4NVN/pdLeHzSg
+0i2BMdolGPLneMpdIbXqZlBi/FiNppmgxMDbRiR4vDsmKQRgTQdzxO2Jd2RvFk3db0kbqu0Sa4V
aMaZ4F0xbOy6Se7fXQMx7BWIuVmchQMFHzs8DRHOBHr0cmyS3VKaF1TPEToIfWFWNg+dISLv6ksF
sFKnh9hrCtWlRSoc5RmEDNwSlLYcf2xD9EmqF8cqlWFQrhzbNTsF9qM7CT7YDSIEvnJZDKBLUDRg
OmnOMns6rHoe2IrZNiwEAgvH9q7Y7kayfmZQS6A4kXodDlEPxu49HwME8iRfbSDHd0AZYDVjoleG
ccF8mfi5NocqNaQJpbxg3bbNU/kqYfNlzmN4Y3l6HKbdQwG3JIsC9LWl6t3gHI5Vy77vFkvf34oE
2nM0Anyn1QzuW7CMUyMo39WewwTruMos7SjCnn5qsa2+PH20iBwScVotruGZ64A9gfhUePYKy3dz
RTw/+6rp0LqaU9nkJhqsxPYdp8ucRebtFJw8zBCGh+fr6/h13Nsy2Xy1ek0Buc+Q0ccszGxJffAj
tO6liaqh3vVqjk2Jw4v8tBXHAEpPDJ0Np2nEiueu61JwLiOuSERmEFp/OlbhcmBoAHoQav9XZBw6
YZJeTedwZ4anCGmjsFS8Ae1E3ufBgIFU08J1kG05YNj7ROrxADqDOfNTTpOns/vW0XoXro2wR/sP
LqfbehKiPMYox4PS1jeFGC2bDMn4/1pfHNPYsfL5AEbNiTcfB2rBLXnfPwt9DwGLu2jwZhjGsPpa
DnaRji6JbJmU1BUBLAajCtgrn8rJGXAvnvF3AtU4y2c0tdfygTBlMHfFYrLXPzZLoQ0oQb4HnXgF
Z0SFM3cdCoNHI/bG3Af+vQNVsFnyph4ecCzHSBvcYInmSER00re4rnFYJD4v+9TI7KDZsoTuCGu5
mvnMNNqZVV95Z5tGR4FTJrD1YfzlsNbV9JhIRLMpwg7M8vDqfvq6QqP4Dh/uO2UPfV1QzH14+ItT
zJn47GupE9HIFQ0hCEwDmQjFcfiEkL3wU13PoSCwX8cG6kjk2tKIIyEKdfVw1ZT1PwsRyhp53en5
y/lVF2MtQkuYl+Y60xYoa0iR6qdmryXX9OiBBNmYy8ZS8GGt3ArvAsmGIV12Q66MKxOHxdSH5hb2
uaC6iVcGF24iOkndTmUNsrzxmHI7OPNRJx82fpkl7pe9tywZtTVlLE0JEBeY3kPCUQI3Ij37FlFa
Ej7kvpSHhi79MCBO69uSUvi4tzehpHYR6ebmlDtW6E3HjRyM3/xDeyWXwdGWlsBup6RrJ0LYhmaT
yWik1/OzVAeBVUlH/aiyBvrQMkAGeLqBsPjGkg0XEP77Mz2/hyVNuAieBPhd4gZBezB6p9w1jbd5
qL5O3tEtshT884p+7BEsNil+0IYvBnP39H1rv2vt9m1QZPjSmt5TTtTOLyyqEq/1hKNhG9SFkUln
iN1LNmaBCBuS7XgLAvqKz0z4jcRvwOGjarhSg5nNiMd8IDtOkZjiqtz5eKgEZKn8dvvo6xFN1gsc
QniLLjHe5FJCH85sW6yebbr6rR8JRISXpXgkRqDK
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
QLOOoKlGeTs3w0jXG0JqRwtHZ6ZjMLpVm5gbg83RVaMB6qCMyHD5NAuvGh/R1T6ZlQp0NMh7Bnk2
5AdHD7cJjA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
oiLZfYUeAPLDA1mPt1oWE8FJuiWI9nQq70AHCVDv7/+/ko3oL+RM55qvzg78ir0IIow9o1QQnZzi
/QnPM3je+PmrMbklYC8hbnc/6WwoYTDYWBjwmnT4WuTu79zT5Dz2iwvQ7UO87XDo6Vccxhk/KNba
ZrIF5dUtbh9SBfEo1pc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
IHdof/KFp2koF/o91nEi7LW4+89e3FRu/nu4NfaWjoFf23t/IPwz0N/ZySSZXeZj7NpcOCWZtivU
DSFNkcNUoxn1xhwZjydQXsRPzt7zggpp1RwvhW+chmFxHP6jaXMEqUkO5g6sEZrtVQtnMb5nqceA
2nqbftFy9y4Jt7UmohJJDYMVVeIXLbWZ+sM9wnfgB7VManZH1vBNIzUmC7EzVRugcadqTAPkQuML
c+Zvth8zYTGwbqF7L7DymzQB8U0Jap19ompCBbL4q3fT1HLAOoCqWtUDTR7MfugbLBGTA07mp/hW
apZVGF7Ua5AJ+LWqKRW3am2rKk+mVP16uzjX2g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cQW6+AQd3QOZ1YlcrM/LQugKHjz+MqOUuR5a7MVb+w/h0VQ2EpwCS5QaTg5R6MyncLujB8RUugJT
TvCpchFxnZKs10+1mFZC2KrxQFUIaFzvxV/edf3kLHqviBvAcROXFgSetBEx4AKxc/qvQlm8TYvH
FrL3s45jp51A+vkmnio=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
nKmftmxJaLdDTM8ApbRpeOSEHVHDWxzh224hvKHxX106ZVfuSqNl6gPbiSpYnnR+hX/i6n0KWBzO
TP+ubtn7uZgVs+/SfxIy3/Sdm0XgcPm9XNcKemx6b5YMwbBewBHzaMu0r1SlSZZn1kPD1zp7f3Kq
IbDj+od/lSq1wO/ibX6+NVPKJDfdGA5UBJAJ9ilvb44fl5kcPiTZ9MEMDFejktkyD1kuL0Yo5hTT
EjD4BJ5PwJzHRhFo+XbaTkDvpT+ZbuwQUta1UAU1w8L4yXTcvQ3sK/w+bsHey1SeQdRQsQojNILe
OocVq6DYPk84FzehGQJInNjaO2duAcIei9xAKg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5616)
`protect data_block
oV0B01WlfOfwc65hHQyPonQOH8xjSJSgdAwbXD5rL4TD4D111/TiNKKXxh6TgXHovRC940qcZar9
P0mrOXcGDb/l2ZGaJjjXyKNi5MBEu6Iz5vo+vUigHa8Q0I5PjyUaKP8USieT+4j0BY5gj2y49aJe
1fSdSw/c9SyioHSzXLkOy0phkEkqYlG89kyPzsR1nXbOJOl35IppKY8VT/r6om9zCQUvHUpVeg4u
3S39qOWVv9lp5GZPzBynEGS1mdxeRm0dyrwFAETJRcG0+4ZuE46JhOhoaeOfRIW721WML0VXdcm6
0YIj22eWcgH2egIeQmsKb6w5wJ2A4aZabT+buWSaW+Sc4WLOHXI3AYz/HR5XOxuLgMmNOzl9TT9A
ANdcF/hDKi3osGFrWlL0sAaJHW3b+6YTsk8uy3ToimYkLrX/KAG8soVNDkeIn2m3MxqzyY/cSIEN
AHmTuJRDZPxlFUq+iHv07Mw2gbguTBxunDhPG5PE1kBt+iZzs/sLDBXifMknSWVQnGEu2ETYLlBS
Ye2TyR3xhUHadhzodOtneytHnFyMDd4TsYz/Ym1AmcxH9iAhoGQS5EzBDW6FfgKLprFOCNlr3Ogz
8E8rRzZnkS3Scu2mA1zieEAXOONeEVxrB4WBdJYY3CtVsUqdc+QGUaN2Cg/tt0NGtsbPFwPYb8x9
Ok1aXiaTk87Eqn7ObpCQA5wvvZut9TEWUeDtVf7nw1MQchDRWGJZFgfo8zNRT1JBkxYNaStRxHcv
NXyZwIFpzJ9l8g9fLizHUNqHMsyQ0D0uXDHYWr+jjN61Tmoi3eSW09/mq20lwL8pHO880Bfjifz+
7FgrOP0ARh3sZ6TmAHCuSFx+g9BWZp6nEJufaLG4X8IC3sXzJiTOU4octt/xU8km5N4jpytU7fVQ
Zs8YbzubQKrRhIVZJNKbeM9HdJijNja0AwRf2Yvp7qEk4KEWisWO6OtSGUgnUa+rQaYWjBs6Hcu1
xGSB0zV1RR2+w9uifUNuJN3WU+HTl1QVQrFP8NSa0AcTQ6Or0x1JKGS44F9sQiPavST55BbJYocE
t6NXd9TYhcX6fSQ5/gr8OwRTCOW5cEPPimy0vFeTR/vcobN1cLVSwGysZp3lv0NO6x51vdQnsKqH
X4BYhXGHxZgFUmMNK/rCm19l2SQBr1DWeRaKfy5/0oM2oqTUCIiMPgoyt6j0wHejsJqWPwHWciX5
YnV4ZZETzLBuC7GCswQ5W1eP3/c1Stk5xr+yTWQoa+IXI6526qt+b+Ywx7j+vrd2+N8irEXwnVTV
hGiVZvkZ0978ypphj56l54i54mKlUJXNMl0R7P3yrb2og9MyxruSax8EtyN3iMyYwDCyIFLXHwab
hghXFA3mIU5foJXDtbK3p9iwK6ZpEAxNyFGWGfjdCGF0z10jqZxQ9WW75RrmW3cZ8+ZM0OijutFg
WZrpAsygehs9uCDzh/Oh2KhSo6D8qM3spREZbYYG/Yl6o6D1H24ehSmZBqSfQll46XcUjMMBQgT3
98Ku1C5uc5UFP0ryVbJz0660n/QFhOReefgVDk+hU6VC+l7+AehVTd7TyX6anmDnl4NGYeIgCbZh
WTQ+TrrdM7k+uVrwlpE5iD2v9Hk084hKc5d/0tH8p5arGpowpoBDmtLsuxoNNDS7oqC/3dMkI5Ke
cFykzmAcIlb98bfnmfy/MzCN83VQsxlKFtgZd3AIeFtZtXAoiukHZzFEw8aic7fEyiBlHXiJ0Zzs
q43M/XitituQuBR+fqaFYzwcJ9G3NnETXWDoDffFwIyn1f4wQX76/UU/vuwfLtY5kfPrtskvpwn6
ZpuqQK0nQyfJXwbLkFEnmpJ1YsZd5+c6EBr7zLKSP+BUtjC7Zz14Lh01Pz7YsmuD6l9H8VpdPdBX
SFKjmOnaEU3aQpxJmOVIaogz6qO2ce/TJaEukKXi4+ntHRT+WLoAESyShmgw7OL5d7P/AQcbanTC
tJkUWHRSoqWMHb0rD1kXjp/bUEpoQ0pLgtfuDuHr5eOREbkMDESDJJ6pET7GBLmcokobCqtgWejU
/kXJU5yFNQ4/5qZFfB4vqbnAEgeXciv+KKRnzrj4LGQ06EpS8t306C41Qxf4ogh/vs7IeejABz4D
1IPDXwm5jJFMCMU2dsZLzx2u2sqgNE1N875is4kUmkeFmfsxDV/R5M2kQFGlXkrnn/4jD1MoPAZy
oGJe2CEOUEzyCC9H0FzHpTzKr5flgZ2XfCH1SreaysB4UIA41/00cwT4z+PXoK9MWAyebelcO0yC
rJFEyf/W+gtIBK0O3yklP5gwSsiK4felu3Vz1/UqqZ7y9HtSYCUevDup9xONpLe3F8cnjNNDRgl+
acMuPH9ATgxJIzHKhjLWt/hT4c1J64Ov8rCPbvko8BNyhak6sThbusbkCAbXJkvhD6SHfYgeJn5u
aJfFRDez2gajS57Px2QFyMvW42v0+fF2+lZPa3TYqIDqhVpxPyyNcfeIGZwUvw/q3hX4go2g8zTu
WnNAb+whbq1LM/qgtvFqECDm27Kq9B8YLATQVQ7zFqm+n4vdP+ViRvspNy3uh6aRiH+bj5ll3+TE
Ud88Sr0pZnRdc9mt7eDujN/lSyPTxhhtDRkd/E5UIQYrUUwr6JC5qf+0pfsPILtuxWw59fVZzRjv
oCckP8slbojSDY9sG7buIVgOnN1vF9Q8lCvBSeXxi54Mspv+QZmMESN9G+VHA/YGEGCmlaIyC6Gd
R7aTrDydSPJ+K54fRYHKXYcyy7UksjaShbwCcp7lq8qY2cvUueuchC8mLI0FPJvUCDFY9bhPeDWK
JXZt4LZmD3B/uq+Jl0UqlAXLs9eJJzynhpfKLgH1sTwmQ6zlUInD91mQguDZrtT8s2TTv8z+ke1a
DiiDtK56K90dCz9ZeAFonengbwFy6EmrRNyj0IzqMF1IfIXQTMATSyxK+3LL/JylP9pBYVGeRLu1
ScJNTLe15Mxx+NOYj9pAa+5SecZhn6/4rDl6ITvm8jglY+DjStaTA3ED0sq9tjCGMeqbTFEM/Mq0
erVAs6NSKTtaKt15HP2Dohok4JG1wsGudOU4RcIYwXRTNoiGzqTmIDAFyKWMzxGd3cYxcXctxX9/
uo+p4QIQC+XOw6HGlJ931C0kVHAvoKlhmjBTS+10EBBGU1//b2cZOxEITxxRjbg2xbA0Gbhes+BY
4kbDb2bMX2yQozoUuCPx0ngWzZNxmoA9csSLVl7gAVZUkCLzTSXO+inrX1GbMoaAjAt+mGp+5eVS
m30aC0xk8QjwJqmZqwQz2xiLBLRqTiYMPb+mH9cBN7UgRxp7pw1mgsgTNjmEjDT/0SvDbUuSGcej
aIbVeCAyJ32TOjkzbKDYccFFOcCHbOMacz5HyQpMQgc6idOrdebmTM12fAru/Mu0T9C8w5kf9FZT
M3woCgfOTpQhrswuCB3kvsYCzCncQL2BE5Rsw1P84/kgNfR+sSFNugy6kFyN1yno3ur6JtsH4EUn
yO7n21QnpbvVE7jf2llPNkSZZ5Iw7PD3r+diZX3avI4yda0P1E5JxuxfLVvK0oSmVNyJrtsDIE2E
HmDx3J3w536qmRz7UXBn3C7rYGGZs5gXTxFQhIHOc64Ox3eygWU/S2ZKteJ8LzZXBPBzWjj5feWO
H8aFZS6d9y5OOdnGuwJnbSW/cSFD96fJrvN42wgbnEPTwySP+g/gVfctI1wwYPnHk32vZQgF4H17
kX9pgrPPEJCtmBsfc0BA9HbrDt/IWBMyP1QDF0TGyYL766V3TSPXkTjK3IuA8y7pzxnD7V+jxbAO
kzjbhI0Kn7tuIb8ogB1YLzOI0ywqV6Y6tAmLDy2PWKDRam6I9oXEwI0fYKzLisb6Js/WM6/91vN6
w8a+OeKKtmF1PLVyEYPJukm4jrR/2j8PnX5rqCXwQVomraG7Gqzv1P2kLO1THK1ml5eViqELuMQh
VvGE0OBueqSlSsJA63hmrbsxb/uNI5pyWdGx9KBvk9GHCcVw8Qa2POihO7t4DkYTH0r+yHbC+gj5
lMl/lT2QuJHFuDegdW7DJPx8fPbrZXkMr7k+X1Ug+1UB9YggxkVFLf4uBEOGLc1qSqG8+NSckuBV
IOY9ihA4oB4V257L5QmxHeGk3BktdpBuKQr+HRPLl1fgPdCu8So9ybCLNBuBL+E6uqBWMii//WMd
wmnqk67bt1DmuuDQqgHjNUzSSjrZUOmNgpKqbD6npzB3yl8nC42a+n0QpaPjT/smnd+Z6Em+uyht
9t2BV5CFd7eICPhgyeLtlO1BiRHrhyf8G32KJmHcGxHysG7vXpE72z8uUvUIj9ZfWT3ZI5/oKYt2
SvP6N0EZflfvJbVcI7ojFemX60G2qJP8To/fv1pPmiCRzNF+jGabHbwQ/gspG22q7t+wNq8oF/eq
XtjjnhpT3hqVnJ4XOs1WAhh1oLs12aHkwrXjj8Kwk+VvjA2VZqo5WOpqGGBAbZn0Pf0B6WTihaz4
PdOBPzGOK29wO06lJ0cOlieki/bcDKZ4C3/ggJIm8V6xw36QYWsNFWDljdfb8Nz2+DzcRuKuJ4xk
FXbpv5doHN3QwCqhWTdFz7WfHDul3EWWuaN/r+k/FtJFUS867ScyULoqPafqSGzwMHwgpaVtfT4s
X5YKI7f3vPK4f7bQqIOaMUxoX6iL8ShFIb+bZghxhEMxANc0MSrnOVxkNFm45eITrQjIxQ4pRZV5
m/+pocblXBph2M8E4HavO5irPKu2RXxQziJrIsBzjha6GjxgJh+QgBIn09hbsTG5S7eMwQu3fzpF
0ZwcTqhg+0iSPUhjsbEX2Ev/EFv2jbAUemtVrTxRojXX5ywmFCTIrGACNyIzoCzPtHyHjYEs9G08
OQfN2qvfhBGZZw1TITCSKssq0IHZs6MBYk7gTGK6HC/E/9HHBehoo4t030YrlWxDZ10HeZNc6HmL
kKspX4/0s+wj4G6qh6wx2v9IT24R9vTx5UCwzF5otHxqKEHowvFhPDKnf1B3/k+WIHDXBhn7xE+Y
JAcbCOWqSUbj+YRaowu0NouDoa34N+ypq7m+Zjo9pMfu880SsKekFwcgjhEZ/gaoslKK+yudt9EC
NF3dy4M5K3A9AMGw4Mipq7XRF60xYEPbQEyjSj3Uvck0wklCpBoccorgr9JA/3cDSIT8Dxp3yloJ
cPDacUeRBcTvGW1gnz0FxZmnZNE+6zRdSEbcNy6xvfFfjRRkh/B7FqKJyWTiM0dCrycPvP8vwvCj
m/MwDlkR386Wq95DobRF6Maub8rABBku+z/UCp8fgGkvNl29TVpD01ANanMdIPVdpYFSXIc2A8MS
9JOeRTLuo4WjWaSZpYlMC6YPvzbbds8rwlY+8SBNXnUKDD5oDcSoBJeyEdTjqmU8oWkuaN7SCMry
uk3J3HplIIS/xr8JuvByw7bHcDYziCWL+Ssjgvcrrbh3Pm4a66nqF+BOBxcc1ws2+uc2C1orhp04
THt1HuzqA1RaqXf55tL/IscqbQj7+LcuVdym7u6Y8rYs4VB0vEUFJpXx7FJ9h/nyExmi5LwAzDs0
X9Cjl5IBCovFu/qHv9Kk8PUMUu7XuslxrbXCKqWVii7ttd4927C8RxhZBGuIY9o+Af/0M2BlSdL6
OC22iaT0WMUBOEm4FAko3z4SNCgCgcadtocktNO1M4FjzQJ+tnAm2asu2TrQTppg8F0R1Z6wc5tf
mbNsVF7mOgYCwzDaSb6BsmoPCuCBaWzBwSEjk0mUQCjAsEhN1cfmAq/LPUbMG8KtN5u9NmmB1jSW
t617AtXy5wgc0m5akVo5G5CqQV6TKVIMAKUDRXZ7vPvv1qBcBnc9+LsYX5Zhspz1KopCqpy3Lqwu
re4QavJZbcr5p8HDg0lETRGjz+mGukzPtZ/WsAD9NyG9gkl11znBDl6M4RwmQPe4NVN/pdLeHzSg
+0i2BMdolGPLneMpdIbXqZlBi/FiNppmgxMDbRiR4vDsmKQRgTQdzxO2Jd2RvFk3db0kbqu0Sa4V
aMaZ4F0xbOy6Se7fXQMx7BWIuVmchQMFHzs8DRHOBHr0cmyS3VKaF1TPEToIfWFWNg+dISLv6ksF
sFKnh9hrCtWlRSoc5RmEDNwSlLYcf2xD9EmqF8cqlWFQrhzbNTsF9qM7CT7YDSIEvnJZDKBLUDRg
OmnOMns6rHoe2IrZNiwEAgvH9q7Y7kayfmZQS6A4kXodDlEPxu49HwME8iRfbSDHd0AZYDVjoleG
ccF8mfi5NocqNaQJpbxg3bbNU/kqYfNlzmN4Y3l6HKbdQwG3JIsC9LWl6t3gHI5Vy77vFkvf34oE
2nM0Anyn1QzuW7CMUyMo39WewwTruMos7SjCnn5qsa2+PH20iBwScVotruGZ64A9gfhUePYKy3dz
RTw/+6rp0LqaU9nkJhqsxPYdp8ucRebtFJw8zBCGh+fr6/h13Nsy2Xy1ek0Buc+Q0ccszGxJffAj
tO6liaqh3vVqjk2Jw4v8tBXHAEpPDJ0Np2nEiueu61JwLiOuSERmEFp/OlbhcmBoAHoQav9XZBw6
YZJeTedwZ4anCGmjsFS8Ae1E3ufBgIFU08J1kG05YNj7ROrxADqDOfNTTpOns/vW0XoXro2wR/sP
LqfbehKiPMYox4PS1jeFGC2bDMn4/1pfHNPYsfL5AEbNiTcfB2rBLXnfPwt9DwGLu2jwZhjGsPpa
DnaRji6JbJmU1BUBLAajCtgrn8rJGXAvnvF3AtU4y2c0tdfygTBlMHfFYrLXPzZLoQ0oQb4HnXgF
Z0SFM3cdCoNHI/bG3Af+vQNVsFnyph4ecCzHSBvcYInmSER00re4rnFYJD4v+9TI7KDZsoTuCGu5
mvnMNNqZVV95Z5tGR4FTJrD1YfzlsNbV9JhIRLMpwg7M8vDqfvq6QqP4Dh/uO2UPfV1QzH14+ItT
zJn47GupE9HIFQ0hCEwDmQjFcfiEkL3wU13PoSCwX8cG6kjk2tKIIyEKdfVw1ZT1PwsRyhp53en5
y/lVF2MtQkuYl+Y60xYoa0iR6qdmryXX9OiBBNmYy8ZS8GGt3ArvAsmGIV12Q66MKxOHxdSH5hb2
uaC6iVcGF24iOkndTmUNsrzxmHI7OPNRJx82fpkl7pe9tywZtTVlLE0JEBeY3kPCUQI3Ij37FlFa
Ej7kvpSHhi79MCBO69uSUvi4tzehpHYR6ebmlDtW6E3HjRyM3/xDeyWXwdGWlsBup6RrJ0LYhmaT
yWik1/OzVAeBVUlH/aiyBvrQMkAGeLqBsPjGkg0XEP77Mz2/hyVNuAieBPhd4gZBezB6p9w1jbd5
qL5O3tEtshT884p+7BEsNil+0IYvBnP39H1rv2vt9m1QZPjSmt5TTtTOLyyqEq/1hKNhG9SFkUln
iN1LNmaBCBuS7XgLAvqKz0z4jcRvwOGjarhSg5nNiMd8IDtOkZjiqtz5eKgEZKn8dvvo6xFN1gsc
QniLLjHe5FJCH85sW6yebbr6rR8JRISXpXgkRqDK
`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_FSM is
port (
-- Fixed word for 1st header of TLP: MRd/MWr
TLP_Has_Payload : IN std_logic;
TLP_Hdr_is_4DW : IN std_logic;
DMA_Addr_Inc : IN std_logic;
DMA_BAR_Number : IN std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- FSM control signals
DMA_Start : IN std_logic;
DMA_Start2 : IN std_logic;
DMA_Stop : IN std_logic;
DMA_Stop2 : IN std_logic;
No_More_Bodies : IN std_logic;
ThereIs_Snout : IN std_logic;
ThereIs_Body : IN std_logic;
ThereIs_Tail : IN std_logic;
ThereIs_Dex : IN std_logic;
-- Parameters to be written into ChBuf
DMA_PA_Loaded : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : IN std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : IN std_logic;
DMA_Snout_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : IN std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : IN std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Busy/Done conditions
Done_Condition_1 : IN std_logic;
Done_Condition_2 : IN std_logic;
Done_Condition_3 : IN std_logic;
Done_Condition_4 : IN std_logic;
Done_Condition_5 : IN std_logic;
-- Channel buffer write
us_MWr_Param_Vec : IN std_logic_vector(6-1 downto 0);
ChBuf_aFull : IN std_logic;
ChBuf_WrEn : OUT std_logic;
ChBuf_WrDin : OUT std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
-- FSM indicators
State_Is_LoadParam : OUT std_logic;
State_Is_Snout : OUT std_logic;
State_Is_Body : OUT std_logic;
State_Is_Tail : OUT std_logic;
DMA_Cmd_Ack : OUT std_logic;
-- To Tx Port
ChBuf_ValidRd : IN std_logic;
BDA_nAligned : OUT std_logic;
DMA_TimeOut : OUT std_logic;
DMA_Busy : OUT std_logic;
DMA_Done : OUT std_logic;
-- DMA_Done_Rise : OUT std_logic;
-- Tags
Pkt_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
Dex_Tag : IN std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- Common ports
dma_clk : IN std_logic;
dma_reset : IN std_logic
);
end entity DMA_FSM;
architecture Behavioral of DMA_FSM is
-- DMA operation control FSM
type DMAStates is (
-- dmaST_Init: Initial state at reset.
dmaST_Init
-- dmaST_Load_Param: Load DMA parameters (PA, HA, BDA and Leng).
, dmaST_Load_Param
-- dmaST_Snout: 1st TLP might be non-integeral of MAX_SIZE.
, dmaST_Snout
-- dmaST_Stomp: after every ChBuf write, pause a clock before taking
-- next write. This state checks the availability of
-- the ChBuf (channel buffer) for write.
, dmaST_Stomp
-- dmaST_Body: TLP's in the middle, always integeral of MAX_SIZE.
, dmaST_Body
-- dmaST_Tail: the last TLP, similar with the 1st one, whose size
-- should be specially calculated.
, dmaST_Tail
-- -- dmaST_Before_Dex: before writing the MRd TLP (for next descriptor)
-- -- information for the next descriptor (if any),
-- -- a pause is needed to wait for the ChBuf available.
-- , dmaST_Before_Dex
-- dmaST_NextDex: writing the descriptor MRd TLP information to
-- the ChBuf.
, dmaST_NextDex
-- dmaST_Await_Dex: after MRd(descriptor) info is written in the ChBuf,
-- the state machine waits for the descriptor's
-- arrival.
, dmaST_Await_Dex
);
signal DMA_NextState : DMAStates;
signal DMA_State : DMAStates;
-- Busy/Done state bits generation
type FSM_BusyDone is (
FSM_Idle
, FSM_Busy1
, FSM_Busy2
, FSM_Busy3
, FSM_Busy4
, FSM_Busy5
, FSM_Done
);
signal BusyDone_NextState : FSM_BusyDone;
signal BusyDone_State : FSM_BusyDone;
-- Time-out state
type FSM_Time_Out is (
toutSt_Idle
, toutSt_CountUp
, toutSt_Pause
);
signal DMA_TimeOut_State : FSM_Time_Out;
-- DMA Start command from MWr channel
signal DMA_Start_r1 : std_logic;
-- DMA Start command from CplD channel
signal DMA_Start2_r1 : std_logic;
-- Registered Dex indicator
signal ThereIs_Dex_reg : std_logic;
signal ThereIs_Snout_reg : std_logic;
signal ThereIs_Body_reg : std_logic;
signal ThereIs_Tail_reg : std_logic;
-- DMA Stutus monitor
signal BDA_nAligned_i : std_logic;
signal DMA_Busy_i : std_logic;
signal DMA_Done_i : std_logic;
-- FSM state indicators
signal State_Is_LoadParam_i : std_logic;
signal State_Is_Snout_i : std_logic;
signal State_Is_Body_i : std_logic;
signal State_Is_Tail_i : std_logic;
signal State_Is_AwaitDex_i : std_logic;
-- Acknowledge for DMA_Start command
signal DMA_Cmd_Ack_i : std_logic;
-- channel FIFO Write control
signal ChBuf_WrDin_i : std_logic_vector(C_CHANNEL_BUF_WIDTH-1 downto 0);
signal ChBuf_WrEn_i : std_logic;
signal ChBuf_aFull_i : std_logic;
-- ---------------------------------------------------------------------------------
-- Time-out calculation : invisible to the user, so moved out of the abbPackage
-- ---------------------------------------------------------------------------------
signal cnt_DMA_TO : std_logic_vector(C_TOUT_WIDTH-1 downto 0);
signal Tout_Lo_Carry : std_logic;
signal DMA_TimeOut_i : std_logic;
-- Carry bit, only for better timing
Constant CBIT_TOUT_CARRY : integer := C_TOUT_WIDTH/2;
begin
-- As DMA Statuses
BDA_nAligned <= BDA_nAligned_i ;
DMA_Busy <= DMA_Busy_i ;
DMA_Done <= DMA_Done_i ;
-- DMA_Done_Rise <= DMA_Done_Rise_i;
DMA_TimeOut <= DMA_TimeOut_i ;
-- Abstract buffer write control
ChBuf_WrEn <= ChBuf_WrEn_i;
ChBuf_WrDin <= ChBuf_WrDin_i;
ChBuf_aFull_i <= ChBuf_aFull;
-- FSM State indicators
State_Is_LoadParam <= State_Is_LoadParam_i;
State_Is_Snout <= State_Is_Snout_i;
State_Is_Body <= State_Is_Body_i;
State_Is_Tail <= State_Is_Tail_i;
DMA_Cmd_Ack <= DMA_Cmd_Ack_i;
-- -----------------------------------------
-- Syn_Delay: DMA_Start
-- DMA_Start2
--
Syn_Delay_DMA_Starts:
process ( dma_clk)
begin
if dma_clk'event and dma_clk = '1' then
DMA_Start_r1 <= DMA_Start;
DMA_Start2_r1 <= DMA_Start2;
end if;
end process;
---- -----------------------------------------
---- -----------------------------------------
----
-- States synchronous: DMA
----
Syn_DMA_States:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_State <= dmaST_Init;
elsif dma_clk'event and dma_clk = '1' then
DMA_State <= DMA_NextState;
end if;
end process;
-- Next States: DMA
Comb_DMA_NextState:
process (
DMA_State
, DMA_Start_r1
, DMA_Start2_r1
, ChBuf_aFull_i
, No_More_Bodies
, ThereIs_Snout --_reg
-- , ThereIs_Body
, ThereIs_Tail_reg
, ThereIs_Dex_reg
)
begin
case DMA_State is
when dmaST_Init =>
if DMA_Start_r1 = '1' then
DMA_NextState <= dmaST_Load_Param;
else
DMA_NextState <= dmaST_Init;
end if;
when dmaST_Load_Param =>
if ChBuf_aFull_i = '1' then
DMA_NextState <= dmaST_Load_Param;
elsif ThereIs_Dex_reg = '1' then
DMA_NextState <= dmaST_NextDex;
elsif ThereIs_Snout = '1' then
DMA_NextState <= dmaST_Snout;
-- elsif ThereIs_Body = '1' then
-- DMA_NextState <= dmaST_Stomp;
else
DMA_NextState <= dmaST_Stomp;
end if;
when dmaST_NextDex =>
if ThereIs_Snout = '1' then
DMA_NextState <= dmaST_Snout;
elsif No_More_Bodies = '0' then
DMA_NextState <= dmaST_Body;
else
DMA_NextState <= dmaST_Await_Dex;
end if;
when dmaST_Snout =>
DMA_NextState <= dmaST_Stomp;
when dmaST_Stomp =>
if ChBuf_aFull_i = '1' then
DMA_NextState <= dmaST_Stomp;
elsif No_More_Bodies= '0' then
DMA_NextState <= dmaST_Body;
elsif ThereIs_Tail_reg= '1' then
DMA_NextState <= dmaST_Tail;
elsif ThereIs_Dex_reg= '1' then
DMA_NextState <= dmaST_Await_Dex;
else
DMA_NextState <= dmaST_Init;
end if;
when dmaST_Body =>
DMA_NextState <= dmaST_Stomp;
when dmaST_Tail =>
if ThereIs_Dex_reg = '1' then
DMA_NextState <= dmaST_Await_Dex;
else
DMA_NextState <= dmaST_Init;
end if;
when dmaST_Await_Dex =>
if DMA_Start2_r1 = '1' then
DMA_NextState <= dmaST_Load_Param;
else
DMA_NextState <= dmaST_Await_Dex;
end if;
when Others =>
DMA_NextState <= dmaST_Init;
end case; -- DMA_State
end process;
-- ----------------------------------------------------
-- States synchronous: DMA_Cmd_Ack
-- equivalent to State_Is_LoadParam
--
Syn_DMA_Cmd_Ack:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Cmd_Ack_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_NextState = dmaST_Load_Param then
DMA_Cmd_Ack_i <= '1';
else
DMA_Cmd_Ack_i <= '0';
end if;
end if;
end process;
-- ----------------------------------------------------
-- States synchronous: ThereIs_Dex_reg
--
Syn_ThereIs_Dex_reg:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Dex_reg <= '0';
ThereIs_Snout_reg <= '0';
ThereIs_Body_reg <= '0';
ThereIs_Tail_reg <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1'
or State_Is_LoadParam_i = '1'
or State_Is_AwaitDex_i ='1'
then
ThereIs_Dex_reg <= ThereIs_Dex;
ThereIs_Snout_reg <= ThereIs_Snout;
ThereIs_Body_reg <= ThereIs_Body;
ThereIs_Tail_reg <= ThereIs_Tail;
else
ThereIs_Dex_reg <= ThereIs_Dex_reg;
ThereIs_Snout_reg <= ThereIs_Snout_reg;
ThereIs_Body_reg <= ThereIs_Body_reg;
ThereIs_Tail_reg <= ThereIs_Tail_reg;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- State_Is_LoadParam
-- State_Is_Snout
-- State_Is_Body
-- State_Is_Tail
-- State_Is_AwaitDex
--
FSM_State_Is_i:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
State_Is_LoadParam_i <= '0';
State_Is_Snout_i <= '0';
State_Is_Body_i <= '0';
State_Is_Tail_i <= '0';
State_Is_AwaitDex_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_NextState= dmaST_Load_Param then
State_Is_LoadParam_i <= '1';
else
State_Is_LoadParam_i <= '0';
end if;
if DMA_NextState= dmaST_Snout then
State_Is_Snout_i <= '1';
else
State_Is_Snout_i <= '0';
end if;
if DMA_NextState= dmaST_Body then
State_Is_Body_i <= '1';
else
State_Is_Body_i <= '0';
end if;
if DMA_NextState= dmaST_Tail then
State_Is_Tail_i <= '1';
else
State_Is_Tail_i <= '0';
end if;
if DMA_NextState= dmaST_Await_Dex then
State_Is_AwaitDex_i <= '1';
else
State_Is_AwaitDex_i <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------
-- Synchronous Output: DMA_Abstract_Buffer_Write
--
-- DMA Channel (downstream and upstream) Buffers (128-bit) definition:
-- Note: Type not shows in this buffer
--
-- 127 ~ xxx : Peripheral address
-- xxy ~ 96 : reserved
-- 95 : Address increments
-- 94 : Valid
-- 93 ~ 30 : Host Address
-- 29 ~ 27 : BAR number
-- 26 ~ 19 : Tag
--
-- 18 ~ 17 : Format
-- 16 ~ 14 : TC
-- 13 : TD
-- 12 : EP
-- 11 ~ 10 : Attribute
-- 9 ~ 0 : Length
--
FSM_DMA_Abstract_Buffer_Write:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
ChBuf_WrEn_i <= '0';
ChBuf_WrDin_i <= (OTHERS =>'0');
elsif dma_clk'event and dma_clk = '1' then
case DMA_State is
when dmaST_NextDex =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_BDA_fsm;
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT); -- any value
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Dex_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= C_TLP_HAS_NO_DATA; --C_MRD_HEAD0_WORD(C_TLP_FMT_BIT_TOP);
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= BDA_is_64b_fsm;
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= C_NEXT_BD_LENGTH(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc; -- any value
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= C_RELAXED_ORDERING & C_NO_SNOOP;
when dmaST_Snout =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Loaded(C_EP_AWIDTH-1 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Loaded(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Loaded(C_DDR_IAWIDTH-1 downto 0);
else
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
end if;
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Snout_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
when dmaST_Body =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0);
else
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
end if;
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Body_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
when dmaST_Tail =>
ChBuf_WrEn_i <= '1';
ChBuf_WrDin_i <= (OTHERS=>'0'); -- must be the first argument
ChBuf_WrDin_i(C_CHBUF_HA_BIT_TOP downto C_CHBUF_HA_BIT_BOT) <= DMA_HA_Var;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_PA_BIT_TOP downto C_CHBUF_PA_BIT_BOT) <= DMA_PA_Var(C_EP_AWIDTH-1 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_BRAM_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= DMA_PA_Var(C_PRAM_AWIDTH-1+2 downto 0);
elsif DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_DDR_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_DDA_BIT_TOP downto C_CHBUF_DDA_BIT_BOT) <= DMA_PA_Var(C_DDR_IAWIDTH-1 downto 0);
else
ChBuf_WrDin_i(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT) <= C_ALL_ZEROS(C_CHBUF_MA_BIT_TOP downto C_CHBUF_MA_BIT_BOT);
end if;
ChBuf_WrDin_i(C_CHBUF_TAG_BIT_TOP downto C_CHBUF_TAG_BIT_BOT) <= Pkt_Tag;
ChBuf_WrDin_i(C_CHBUF_DMA_BAR_BIT_TOP downto C_CHBUF_DMA_BAR_BIT_BOT) <= DMA_BAR_Number;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_TOP) <= TLP_Has_Payload;
ChBuf_WrDin_i(C_CHBUF_FMT_BIT_BOT) <= TLP_Hdr_is_4DW;
if DMA_BAR_Number=CONV_STD_LOGIC_VECTOR(CINT_FIFO_SPACE_BAR, C_ENCODE_BAR_NUMBER) then
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 3) & '0';
else
ChBuf_WrDin_i(C_CHBUF_LENG_BIT_TOP downto C_CHBUF_LENG_BIT_BOT) <= DMA_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 2);
end if;
ChBuf_WrDin_i(C_CHBUF_QVALID_BIT) <= '1';
ChBuf_WrDin_i(C_CHBUF_AINC_BIT) <= DMA_Addr_Inc;
ChBuf_WrDin_i(C_CHBUF_TC_BIT_TOP downto C_CHBUF_TC_BIT_BOT) <= us_MWr_Param_Vec(2 downto 0);
ChBuf_WrDin_i(C_CHBUF_ATTR_BIT_TOP downto C_CHBUF_ATTR_BIT_BOT) <= us_MWr_Param_Vec(5 downto 4); -- C_RELAXED_ORDERING & C_NO_SNOOP;
when OTHERS =>
ChBuf_WrEn_i <= '0';
ChBuf_WrDin_i <= ChBuf_WrDin_i;
end case;
end if;
end process;
-- ----------------------------------------------
-- Synchronous Latch: BDA_nAligned_i
-- : Capture design defect
--
Latch_BDA_nAligned:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
BDA_nAligned_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
-- If the lowest 2 bits are not zero, error bit set accordingly,
-- because the logic can not deal with this situation.
-- can be removed.
if DMA_BDA_fsm(1) ='1' or DMA_BDA_fsm(0) ='1' then
BDA_nAligned_i <= '1';
else
BDA_nAligned_i <= BDA_nAligned_i;
end if;
end if;
end process;
-- States synchronous: BusyDone_States
Syn_BusyDone_States:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
BusyDone_State <= FSM_Idle;
elsif dma_clk'event and dma_clk = '1' then
BusyDone_State <= BusyDone_NextState;
end if;
end process;
-- Next States: BusyDone_State
Comb_BusyDone_State:
process (
BusyDone_State
, DMA_State
-- , Done_Condition_1
, Done_Condition_2
, Done_Condition_3
, Done_Condition_4
, Done_Condition_5
)
begin
case BusyDone_State is
when FSM_Idle =>
if DMA_State = dmaST_Load_Param then
BusyDone_NextState <= FSM_Busy1;
else
BusyDone_NextState <= FSM_Idle;
end if;
when FSM_Busy1 =>
if DMA_State = dmaST_Init --- Done_Condition_1='1'
then
BusyDone_NextState <= FSM_Busy2;
else
BusyDone_NextState <= FSM_Busy1;
end if;
when FSM_Busy2 =>
if Done_Condition_2='1'
then
BusyDone_NextState <= FSM_Busy3;
else
BusyDone_NextState <= FSM_Busy2;
end if;
when FSM_Busy3 =>
if Done_Condition_3='1'
then
BusyDone_NextState <= FSM_Busy4;
else
BusyDone_NextState <= FSM_Busy3;
end if;
when FSM_Busy4 =>
if Done_Condition_4='1'
then
BusyDone_NextState <= FSM_Busy5;
else
BusyDone_NextState <= FSM_Busy4;
end if;
when FSM_Busy5 =>
if Done_Condition_5='1'
then
BusyDone_NextState <= FSM_Done;
else
BusyDone_NextState <= FSM_Busy5;
end if;
when FSM_Done =>
if DMA_State = dmaST_Init then
BusyDone_NextState <= FSM_Idle;
else
BusyDone_NextState <= FSM_Done;
end if;
when Others =>
BusyDone_NextState <= FSM_Idle;
end case; -- BusyDone_State
end process;
-- Synchronous Output: DMA_Busy_i
FSM_Output_DMA_Busy:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Busy_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
case BusyDone_State is
when FSM_Idle =>
DMA_Busy_i <= '0';
when FSM_Busy1 =>
DMA_Busy_i <= '1';
when FSM_Busy2 =>
DMA_Busy_i <= '1';
when FSM_Busy3 =>
DMA_Busy_i <= '1';
when FSM_Busy4 =>
DMA_Busy_i <= '1';
when FSM_Busy5 =>
DMA_Busy_i <= '1';
when FSM_Done =>
DMA_Busy_i <= '0';
when Others =>
DMA_Busy_i <= '0';
end case; -- BusyDone_State
end if;
end process;
-- Synchronous Output: DMA_Done_i
FSM_Output_DMA_Done:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Done_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
case BusyDone_State is
-- when FSM_Busy1 =>
-- DMA_Done_i <= '0';
--
-- when FSM_Busy2 =>
-- DMA_Done_i <= '0';
--
-- when FSM_Busy3 =>
-- DMA_Done_i <= '0';
--
when FSM_Done =>
DMA_Done_i <= '1';
when Others =>
DMA_Done_i <= DMA_Done_i;
end case; -- BusyDone_State
end if;
end process;
-- ----------------------------------------------
-- Time out counter
-- Synchronous Output: Counter_DMA_TimeOut_i
FSM_Counter_DMA_TimeOut_i:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
DMA_TimeOut_State <= toutSt_Idle;
elsif dma_clk'event and dma_clk = '1' then
case DMA_TimeOut_State is
when toutSt_Idle =>
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
if DMA_Start='1' then
DMA_TimeOut_State <= toutSt_CountUp;
else
DMA_TimeOut_State <= toutSt_Idle;
end if;
when toutSt_CountUp =>
if DMA_Done_i='1' or DMA_Start='1' then
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
DMA_TimeOut_State <= toutSt_Idle;
elsif DMA_Stop='1' then
cnt_DMA_TO <= cnt_DMA_TO;
Tout_Lo_Carry <= Tout_Lo_Carry;
DMA_TimeOut_State <= toutSt_Pause;
elsif ChBuf_ValidRd='1' then
cnt_DMA_TO <= (Others=>'0');
Tout_Lo_Carry <= '0';
DMA_TimeOut_State <= toutSt_CountUp;
else
cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0) + '1';
if cnt_DMA_TO(CBIT_TOUT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_TOUT_CARRY-1 downto 0) then
Tout_Lo_Carry <= '1';
else
Tout_Lo_Carry <= '0';
end if;
if Tout_Lo_Carry='1' then
cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) + '1';
else
cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_CARRY);
end if;
DMA_TimeOut_State <= toutSt_CountUp;
end if;
when toutSt_Pause =>
cnt_DMA_TO <= cnt_DMA_TO;
Tout_Lo_Carry <= Tout_Lo_Carry;
if DMA_Start='1' then
DMA_TimeOut_State <= toutSt_CountUp;
elsif DMA_Done_i='1' then
DMA_TimeOut_State <= toutSt_Idle;
else
DMA_TimeOut_State <= toutSt_Pause;
end if;
when Others =>
cnt_DMA_TO <= cnt_DMA_TO;
Tout_Lo_Carry <= Tout_Lo_Carry;
DMA_TimeOut_State <= toutSt_Idle;
end case;
-- case DMA_State is
--
-- when dmaST_Init =>
-- cnt_DMA_TO <= (Others=>'0');
-- Tout_Lo_Carry <= '0';
--
-- when dmaST_Snout =>
-- cnt_DMA_TO <= (Others=>'0');
-- Tout_Lo_Carry <= '0';
--
--
-- when Others =>
-- cnt_DMA_TO(CBIT_CARRY-1 downto 0) <= cnt_DMA_TO(CBIT_CARRY-1 downto 0) + '1';
--
-- if cnt_DMA_TO(CBIT_CARRY-1 downto 0)=C_ALL_ONES(CBIT_CARRY-1 downto 0) then
-- Tout_Lo_Carry <= '1';
-- else
-- Tout_Lo_Carry <= '0';
-- end if;
--
-- if Tout_Lo_Carry='1' then
-- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) + '1';
-- else
-- cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY) <= cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_CARRY);
-- end if;
--
-- end case;
end if;
end process;
-- ----------------------------------------------
-- Time out state bit
-- Synchronous Output: DMA_TimeOut_i
FSM_DMA_TimeOut:
process ( dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_TimeOut_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
-- Capture the time-out trigger
-- if cnt_DMA_TO(CBIT_TOUT_BOT downto 0) = C_TIME_OUT_VALUE then
if cnt_DMA_TO(C_TOUT_WIDTH-1 downto CBIT_TOUT_BOT) = C_TIME_OUT_VALUE then
DMA_TimeOut_i <= '1';
else
DMA_TimeOut_i <= DMA_TimeOut_i;
end if;
end if;
end process;
end architecture Behavioral;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:45:56 05/22/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_n_cycles_delayer.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: n_cycles_delayer
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY test_n_cycles_delayer IS
END test_n_cycles_delayer;
ARCHITECTURE behavior OF test_n_cycles_delayer IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT n_cycles_delayer
GENERIC (
n : integer range 1 to 1024 := 5;
signal_width : integer range 1 to 1024 := 8
);
PORT(
nrst : IN std_logic;
clk : IN std_logic;
input : IN std_logic_vector(7 downto 0);
output : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk : std_logic := '0';
signal input : std_logic_vector(7 downto 0) := (others => '0');
--Outputs
signal output : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: n_cycles_delayer
PORT MAP (
nrst => nrst,
clk => clk,
input => input,
output => output
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process is
variable i, j : std_logic_vector (7 downto 0);
begin
-- hold reset state for 105 ns.
nrst <= '0';
wait for clk_period * 10;
nrst <= '1';
wait for clk_period * 10;
i := (others => '0');
while true loop
i := i + 1;
input <= i;
for j in 0 to 3 loop
wait for clk_period;
assert output /= input report "Should not match";
end loop;
wait for clk_period * 2;
assert output = input report "Should match";
end loop;
wait;
end process;
END;
|
-- Eric Bainville
-- Mar 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity basic_uart is
generic (
DIVISOR: natural -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
-- 2400 -> 2604
-- 9600 -> 651
-- 115200 -> 54
-- 1562500 -> 4
-- 2083333 -> 3
);
port (
clk : in std_logic; -- clock
sys_clk : in std_logic;
reset: in std_logic; -- reset
-- Client interface
bus_dq : inout std_logic_vector(15 downto 0); -- received byte
bus_addr : in std_logic_vector(15 downto 0);
bus_rw : in std_logic; -- validates byte to send if ack is '1'
bus_req : in std_logic;
ack : out std_logic; -- if '1', we can send a new byte, otherwise we won't take it
int : out std_logic; -- validates received byte (1 system clock spike)
-- Physical interface
rx : in std_logic;
tx : out std_logic
);
end basic_uart;
architecture Behavioral of basic_uart is
constant COUNTER_BITS : natural := integer(ceil(log2(real(DIVISOR))));
type fsm_state_t is (idle, active); -- common to both RX and TX FSM
type rx_state_t is
record
fsm_state: fsm_state_t; -- FSM state
counter: std_logic_vector(3 downto 0); -- tick count
bits: std_logic_vector(7 downto 0); -- received bits
nbits: std_logic_vector(3 downto 0); -- number of received bits (includes start bit)
enable: std_logic; -- signal we received a new byte
end record;
type tx_state_t is
record
fsm_state: fsm_state_t; -- FSM state
counter: std_logic_vector(3 downto 0); -- tick count
bits: std_logic_vector(8 downto 0); -- bits to emit, includes start bit
nbits: std_logic_vector(3 downto 0); -- number of bits left to send
ready: std_logic; -- signal we are accepting a new byte
end record;
signal rx_state,rx_state_next: rx_state_t;
signal tx_state,tx_state_next: tx_state_t;
signal sample: std_logic; -- 1 clk spike at 16x baud rate
signal sample_counter: std_logic_vector(COUNTER_BITS-1 downto 0); -- should fit values in 0..DIVISOR-1
begin
-- sample signal at 16x baud rate, 1 CLK spikes
sample_process: process (clk,reset) is
begin
if reset = '1' then
sample_counter <= (others => '0');
sample <= '0';
elsif rising_edge(clk) then
if sample_counter = DIVISOR-1 then
sample <= '1';
sample_counter <= (others => '0');
else
sample <= '0';
sample_counter <= sample_counter + 1;
end if;
end if;
end process;
-- RX, TX state registers update at each CLK, and RESET
reg_process: process (clk,reset) is
begin
if reset = '1' then
rx_state.fsm_state <= idle;
rx_state.bits <= (others => '0');
rx_state.nbits <= (others => '0');
rx_state.enable <= '0';
tx_state.fsm_state <= idle;
tx_state.bits <= (others => '1');
tx_state.nbits <= (others => '0');
tx_state.ready <= '1';
elsif rising_edge(clk) then
rx_state <= rx_state_next;
tx_state <= tx_state_next;
end if;
end process;
-- RX FSM
rx_process: process (rx_state,sample,rx) is
begin
case rx_state.fsm_state is
when idle =>
rx_state_next.counter <= (others => '0');
rx_state_next.bits <= (others => '0');
rx_state_next.nbits <= (others => '0');
rx_state_next.enable <= '0';
if rx = '0' then
-- start a new byte
rx_state_next.fsm_state <= active;
else
-- keep idle
rx_state_next.fsm_state <= idle;
end if;
when active =>
rx_state_next <= rx_state;
if sample = '1' then
if rx_state.counter = 8 then
-- sample next RX bit (at the middle of the counter cycle)
if rx_state.nbits = 9 then
rx_state_next.fsm_state <= idle; -- back to idle state to wait for next start bit
rx_state_next.enable <= rx; -- OK if stop bit is '1'
else
rx_state_next.bits <= rx & rx_state.bits(7 downto 1);
rx_state_next.nbits <= rx_state.nbits + 1;
end if;
end if;
rx_state_next.counter <= rx_state.counter + 1;
end if;
end case;
end process;
-- RX output
rx_output: process (rx_state) is
begin
int <= rx_state.enable;
bus_dq <= x"00" & rx_state.bits;
end process;
-- TX FSM
tx_process: process (tx_state,sample,bus_req,bus_dq) is
begin
case tx_state.fsm_state is
when idle =>
if bus_req = '1' and bus_rw = '1' and bus_addr = x"0901" then
-- start a new bit
tx_state_next.bits <= bus_dq(7 downto 0) & '0'; -- data & start
tx_state_next.nbits <= "0000" + 10; -- send 10 bits (includes '1' stop bit)
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= active;
tx_state_next.ready <= '0';
else
-- keep idle
tx_state_next.bits <= (others => '1');
tx_state_next.nbits <= (others => '0');
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
end if;
when active =>
tx_state_next <= tx_state;
if sample = '1' then
if tx_state.counter = 15 then
-- send next bit
if tx_state.nbits = 0 then
-- turn idle
tx_state_next.bits <= (others => '1');
tx_state_next.nbits <= (others => '0');
tx_state_next.counter <= (others => '0');
tx_state_next.fsm_state <= idle;
tx_state_next.ready <= '1';
else
tx_state_next.bits <= '1' & tx_state.bits(8 downto 1);
tx_state_next.nbits <= tx_state.nbits - 1;
end if;
end if;
tx_state_next.counter <= tx_state.counter + 1;
end if;
end case;
end process;
-- TX output
tx_output: process (tx_state) is
begin
--int <= tx_state.ready;
tx <= tx_state.bits(0);
end process;
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
entity split_48_bits_to_8x6 is
port( data_in: in std_logic_vector(0 to 47);
data_out_1: out std_logic_vector(0 to 5); --holds data 0 to 5
data_out_2: out std_logic_vector(0 to 5); --holds data 6 to 11
data_out_3: out std_logic_vector(0 to 5); --holds data 12 to 17
data_out_4: out std_logic_vector(0 to 5); --holds data 18 to 23
data_out_5: out std_logic_vector(0 to 5); --holds data 24 to 29
data_out_6: out std_logic_vector(0 to 5); --holds data 30 to 35
data_out_7: out std_logic_vector(0 to 5); --holds data 36 to 41
data_out_8: out std_logic_vector(0 to 5)); --holds data 42 to 47
end split_48_bits_to_8x6;
architecture behavior of split_48_bits_to_8x6 is
begin
data_out_1<=data_in(0 to 5);
data_out_2<=data_in(6 to 11);
data_out_3<=data_in(12 to 17);
data_out_4<=data_in(18 to 23);
data_out_5<=data_in(24 to 29);
data_out_6<=data_in(30 to 35);
data_out_7<=data_in(36 to 41);
data_out_8<=data_in(42 to 47);
end behavior;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
------------------------------------------------------------------------
------------------------------------------------------------------------
--
-- Entity : xlconcat
--
-- Architecture : behavior
--
-- Description : Top level VHDL description of bus concatenater
--
------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity xlconcat is
generic (
NUM_PORTS : integer := 2; -- Number of input ports to concat
IN0_WIDTH : integer := 1; -- Width of a In0 input
IN1_WIDTH : integer := 1; -- Width of a In1 input
IN2_WIDTH : integer := 1; -- Width of a In2 input
IN3_WIDTH : integer := 1; -- Width of a In3 input
IN4_WIDTH : integer := 1; -- Width of a In4 input
IN5_WIDTH : integer := 1; -- Width of a In5 input
IN6_WIDTH : integer := 1; -- Width of a In6 input
IN7_WIDTH : integer := 1; -- Width of a In7 input
IN8_WIDTH : integer := 1; -- Width of a In8 input
IN9_WIDTH : integer := 1; -- Width of a In9 input
IN10_WIDTH : integer := 1; -- Width of a In10 input
IN11_WIDTH : integer := 1; -- Width of a In10 input
IN12_WIDTH : integer := 1; -- Width of a In10 input
IN13_WIDTH : integer := 1; -- Width of a In10 input
IN14_WIDTH : integer := 1; -- Width of a In10 input
IN15_WIDTH : integer := 1; -- Width of a In15 input
IN16_WIDTH : integer := 1; -- Width of a In16 input
IN17_WIDTH : integer := 1; -- Width of a In17 input
IN18_WIDTH : integer := 1; -- Width of a In18 input
IN19_WIDTH : integer := 1; -- Width of a In19 input
IN20_WIDTH : integer := 1; -- Width of a In20 input
IN21_WIDTH : integer := 1; -- Width of a In21 input
IN22_WIDTH : integer := 1; -- Width of a In22 input
IN23_WIDTH : integer := 1; -- Width of a In23 input
IN24_WIDTH : integer := 1; -- Width of a In24 input
IN25_WIDTH : integer := 1; -- Width of a In25 input
IN26_WIDTH : integer := 1; -- Width of a In26 input
IN27_WIDTH : integer := 1; -- Width of a In27 input
IN28_WIDTH : integer := 1; -- Width of a In28 input
IN29_WIDTH : integer := 1; -- Width of a In29 input
IN30_WIDTH : integer := 1; -- Width of a In30 input
IN31_WIDTH : integer := 1; -- Width of a In31 input
dout_width : integer := 2); -- Width of output
port (
In0 : in std_logic_vector (IN0_WIDTH-1 downto 0);
In1 : in std_logic_vector (IN1_WIDTH-1 downto 0);
In2 : in std_logic_vector (IN2_WIDTH-1 downto 0);
In3 : in std_logic_vector (IN3_WIDTH-1 downto 0);
In4 : in std_logic_vector (IN4_WIDTH-1 downto 0);
In5 : in std_logic_vector (IN5_WIDTH-1 downto 0);
In6 : in std_logic_vector (IN6_WIDTH-1 downto 0);
In7 : in std_logic_vector (IN7_WIDTH-1 downto 0);
In8 : in std_logic_vector (IN8_WIDTH-1 downto 0);
In9 : in std_logic_vector (IN9_WIDTH-1 downto 0);
In10 : in std_logic_vector (IN10_WIDTH-1 downto 0);
In11 : in std_logic_vector (IN11_WIDTH-1 downto 0);
In12 : in std_logic_vector (IN12_WIDTH-1 downto 0);
In13 : in std_logic_vector (IN13_WIDTH-1 downto 0);
In14 : in std_logic_vector (IN14_WIDTH-1 downto 0);
In15 : in std_logic_vector (IN15_WIDTH-1 downto 0);
In16 : in std_logic_vector (IN16_WIDTH-1 downto 0);
In17 : in std_logic_vector (IN17_WIDTH-1 downto 0);
In18 : in std_logic_vector (IN18_WIDTH-1 downto 0);
In19 : in std_logic_vector (IN19_WIDTH-1 downto 0);
In20 : in std_logic_vector (IN20_WIDTH-1 downto 0);
In21 : in std_logic_vector (IN21_WIDTH-1 downto 0);
In22 : in std_logic_vector (IN22_WIDTH-1 downto 0);
In23 : in std_logic_vector (IN23_WIDTH-1 downto 0);
In24 : in std_logic_vector (IN24_WIDTH-1 downto 0);
In25 : in std_logic_vector (IN25_WIDTH-1 downto 0);
In26 : in std_logic_vector (IN26_WIDTH-1 downto 0);
In27 : in std_logic_vector (IN27_WIDTH-1 downto 0);
In28 : in std_logic_vector (IN28_WIDTH-1 downto 0);
In29 : in std_logic_vector (IN29_WIDTH-1 downto 0);
In30 : in std_logic_vector (IN30_WIDTH-1 downto 0);
In31 : in std_logic_vector (IN31_WIDTH-1 downto 0);
dout : out std_logic_vector (dout_width-1 downto 0)
);
end xlconcat;
architecture behavioral of xlconcat is
begin
NUM_1_INST : if NUM_PORTS = 1 generate
begin
dout <= In0;
end generate NUM_1_INST;
NUM_2_INST : if NUM_PORTS = 2 generate
begin
dout <= In1 & In0;
end generate NUM_2_INST;
NUM_3_INST : if NUM_PORTS = 3 generate
begin
dout <= In2 & In1 & In0;
end generate NUM_3_INST;
NUM_4_INST : if NUM_PORTS = 4 generate
begin
dout <= In3 & In2 & In1 & In0;
end generate NUM_4_INST;
NUM_5_INST : if NUM_PORTS = 5 generate
begin
dout <= In4 & In3 & In2 & In1 & In0;
end generate NUM_5_INST;
NUM_6_INST : if NUM_PORTS = 6 generate
begin
dout <= In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_6_INST;
NUM_7_INST : if NUM_PORTS = 7 generate
begin
dout <= In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_7_INST;
NUM_8_INST : if NUM_PORTS = 8 generate
begin
dout <= In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_8_INST;
NUM_9_INST : if NUM_PORTS = 9 generate
begin
dout <= In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_9_INST;
NUM_10_INST : if NUM_PORTS = 10 generate
begin
dout <= In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_10_INST;
NUM_11_INST : if NUM_PORTS = 11 generate
begin
dout <= In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_11_INST;
NUM_12_INST : if NUM_PORTS = 12 generate
begin
dout <= In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_12_INST;
NUM_13_INST : if NUM_PORTS = 13 generate
begin
dout <= In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_13_INST;
NUM_14_INST : if NUM_PORTS = 14 generate
begin
dout <= In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_14_INST;
NUM_15_INST : if NUM_PORTS = 15 generate
begin
dout <= In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_15_INST;
NUM_16_INST : if NUM_PORTS = 16 generate
begin
dout <= In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_16_INST;
NUM_17_INST : if NUM_PORTS = 17 generate
begin
dout <= In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_17_INST;
NUM_18_INST : if NUM_PORTS = 18 generate
begin
dout <= In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_18_INST;
NUM_19_INST : if NUM_PORTS = 19 generate
begin
dout <= In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_19_INST;
NUM_20_INST : if NUM_PORTS = 20 generate
begin
dout <= In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_20_INST;
NUM_21_INST : if NUM_PORTS = 21 generate
begin
dout <= In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_21_INST;
NUM_22_INST : if NUM_PORTS = 22 generate
begin
dout <= In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_22_INST;
NUM_23_INST : if NUM_PORTS = 23 generate
begin
dout <= In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_23_INST;
NUM_24_INST : if NUM_PORTS = 24 generate
begin
dout <= In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_24_INST;
NUM_25_INST : if NUM_PORTS = 25 generate
begin
dout <= In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_25_INST;
NUM_26_INST : if NUM_PORTS = 26 generate
begin
dout <= In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_26_INST;
NUM_27_INST : if NUM_PORTS = 27 generate
begin
dout <= In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_27_INST;
NUM_28_INST : if NUM_PORTS = 28 generate
begin
dout <= In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_28_INST;
NUM_29_INST : if NUM_PORTS = 29 generate
begin
dout <= In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_29_INST;
NUM_30_INST : if NUM_PORTS = 30 generate
begin
dout <= In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_30_INST;
NUM_31_INST : if NUM_PORTS = 31 generate
begin
dout <= In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_31_INST;
NUM_32_INST : if NUM_PORTS = 32 generate
begin
dout <= In31 & In30 & In29 & In28 & In27 & In26 & In25 & In24 & In23 & In22 & In21 & In20 & In19 & In18 & In17 & In16 & In15 & In14 & In13 & In12 & In11 & In10 & In9 & In8 & In7 & In6 & In5 & In4 & In3 & In2 & In1 & In0;
end generate NUM_32_INST;
end behavioral;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000000000000000";
link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
--link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N);
parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
faulty => LBDR_Fault_N,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
faulty => LBDR_Fault_E,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
faulty => LBDR_Fault_W,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
faulty => LBDR_Fault_S,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
faulty => LBDR_Fault_L,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000000000000000";
link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
--link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N);
parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
faulty => LBDR_Fault_N,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
faulty => LBDR_Fault_E,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
faulty => LBDR_Fault_W,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
faulty => LBDR_Fault_S,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
faulty => LBDR_Fault_L,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := 0;
Rxy_rst : integer := 10;
Cx_rst : integer := 10;
healthy_counter_threshold : integer := 8;
faulty_counter_threshold: integer := 2;
counter_depth: integer := 4;
NoC_size: integer := 4
);
port (
reset, clk: in std_logic;
RX_N, RX_E, RX_W, RX_S, RX_L : in std_logic_vector (DATA_WIDTH-1 downto 0);
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
valid_in_N, valid_in_E, valid_in_W, valid_in_S, valid_in_L : in std_logic;
valid_out_N, valid_out_E, valid_out_W, valid_out_S, valid_out_L : out std_logic;
credit_out_N, credit_out_E, credit_out_W, credit_out_S, credit_out_L: out std_logic;
TX_N, TX_E, TX_W, TX_S, TX_L: out std_logic_vector (DATA_WIDTH-1 downto 0);
Faulty_N_in, Faulty_E_in, Faulty_W_in, Faulty_S_in: in std_logic;
Faulty_N_out, Faulty_E_out, Faulty_W_out, Faulty_S_out: out std_logic;
-- should be connected to NI
link_faults: out std_logic_vector(4 downto 0);
turn_faults: out std_logic_vector(19 downto 0);
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end router_credit_based_PD_C_SHMU;
architecture behavior of router_credit_based_PD_C_SHMU is
COMPONENT FIFO_credit_based is
generic (
DATA_WIDTH: integer := 32
);
port ( reset: in std_logic;
clk: in std_logic;
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
valid_in: in std_logic;
read_en_N : in std_logic;
read_en_E : in std_logic;
read_en_W : in std_logic;
read_en_S : in std_logic;
read_en_L : in std_logic;
credit_out: out std_logic;
empty_out: out std_logic;
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0);
fault_info, health_info: out std_logic
);
end COMPONENT;
COMPONENT counter_threshold_classifier is
generic (
counter_depth: integer := 8;
healthy_counter_threshold: integer := 4;
faulty_counter_threshold: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
faulty_packet, Healthy_packet: in std_logic;
Healthy, intermittent, Faulty: out std_logic
);
end COMPONENT;
COMPONENT allocator is
port ( reset: in std_logic;
clk: in std_logic;
-- flow control
credit_in_N, credit_in_E, credit_in_W, credit_in_S, credit_in_L: in std_logic;
req_N_N, req_N_E, req_N_W, req_N_S, req_N_L: in std_logic;
req_E_N, req_E_E, req_E_W, req_E_S, req_E_L: in std_logic;
req_W_N, req_W_E, req_W_W, req_W_S, req_W_L: in std_logic;
req_S_N, req_S_E, req_S_W, req_S_S, req_S_L: in std_logic;
req_L_N, req_L_E, req_L_W, req_L_S, req_L_L: in std_logic;
empty_N, empty_E, empty_W, empty_S, empty_L: in std_logic;
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
valid_N, valid_E, valid_W, valid_S, valid_L : out std_logic;
grant_N_N, grant_N_E, grant_N_W, grant_N_S, grant_N_L: out std_logic;
grant_E_N, grant_E_E, grant_E_W, grant_E_S, grant_E_L: out std_logic;
grant_W_N, grant_W_E, grant_W_W, grant_W_S, grant_W_L: out std_logic;
grant_S_N, grant_S_E, grant_S_W, grant_S_S, grant_S_L: out std_logic;
grant_L_N, grant_L_E, grant_L_W, grant_L_S, grant_L_L: out std_logic
);
end COMPONENT;
COMPONENT parity_checker_for_LBDR is
generic(DATA_WIDTH : integer := 32);
port(
RX: in std_logic_vector(DATA_WIDTH-1 downto 0);
empty: in std_logic;
faulty: out std_logic
);
end COMPONENT;
COMPONENT LBDR_packet_drop is
generic (
cur_addr_rst: integer := 8;
Rxy_rst: integer := 8;
Cx_rst: integer := 8;
NoC_size: integer := 4
);
port ( reset: in std_logic;
clk: in std_logic;
Faulty_C_N, Faulty_C_E, Faulty_C_W, Faulty_C_S: in std_logic;
empty: in std_logic;
flit_type: in std_logic_vector(2 downto 0);
dst_addr: in std_logic_vector(NoC_size-1 downto 0);
faulty: in std_logic;
packet_drop_order: out std_logic;
grant_N, grant_E, grant_W, grant_S, grant_L: in std_logic;
Req_N, Req_E, Req_W, Req_S, Req_L:out std_logic;
Rxy_reconf_PE: in std_logic_vector(7 downto 0);
Cx_reconf_PE: in std_logic_vector(3 downto 0);
Reconfig_command : in std_logic
);
end COMPONENT;
COMPONENT XBAR is
generic (
DATA_WIDTH: integer := 32
);
port (
North_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
East_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
West_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
South_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
Local_in: in std_logic_vector(DATA_WIDTH-1 downto 0);
sel: in std_logic_vector (4 downto 0);
Data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end COMPONENT;
signal FIFO_D_out_N, FIFO_D_out_E, FIFO_D_out_W, FIFO_D_out_S, FIFO_D_out_L: std_logic_vector(DATA_WIDTH-1 downto 0);
-- Grant_XY : Grant signal generated from Arbiter for output X connected to FIFO of input Y
signal Grant_NN, Grant_NE, Grant_NW, Grant_NS, Grant_NL: std_logic;
signal Grant_EN, Grant_EE, Grant_EW, Grant_ES, Grant_EL: std_logic;
signal Grant_WN, Grant_WE, Grant_WW, Grant_WS, Grant_WL: std_logic;
signal Grant_SN, Grant_SE, Grant_SW, Grant_SS, Grant_SL: std_logic;
signal Grant_LN, Grant_LE, Grant_LW, Grant_LS, Grant_LL: std_logic;
signal Req_NN, Req_EN, Req_WN, Req_SN, Req_LN: std_logic;
signal Req_NE, Req_EE, Req_WE, Req_SE, Req_LE: std_logic;
signal Req_NW, Req_EW, Req_WW, Req_SW, Req_LW: std_logic;
signal Req_NS, Req_ES, Req_WS, Req_SS, Req_LS: std_logic;
signal Req_NL, Req_EL, Req_WL, Req_SL, Req_LL: std_logic;
signal empty_N, empty_E, empty_W, empty_S, empty_L: std_logic;
signal Xbar_sel_N, Xbar_sel_E, Xbar_sel_W, Xbar_sel_S, Xbar_sel_L: std_logic_vector(4 downto 0);
signal LBDR_Fault_N, LBDR_Fault_E, LBDR_Fault_W, LBDR_Fault_S, LBDR_Fault_L: std_logic;
signal faulty_packet_N, faulty_packet_E, faulty_packet_W, faulty_packet_S, faulty_packet_L: std_logic;
signal healthy_packet_N, healthy_packet_E, healthy_packet_W, healthy_packet_S, healthy_packet_L: std_logic;
signal packet_drop_order_N, packet_drop_order_E, packet_drop_order_W, packet_drop_order_S, packet_drop_order_L: std_logic;
signal healthy_link_N, healthy_link_E, healthy_link_W, healthy_link_S, healthy_link_L: std_logic;
signal sig_Faulty_N_out, sig_Faulty_E_out, sig_Faulty_W_out, sig_Faulty_S_out, faulty_link_L: std_logic;
signal intermittent_link_N, intermittent_link_E, intermittent_link_W, intermittent_link_S, intermittent_link_L: std_logic;
begin
turn_faults <= "00000000000000000000";
link_faults <= sig_Faulty_N_out & sig_Faulty_E_out & sig_Faulty_W_out & sig_Faulty_S_out & faulty_link_L;
--link_faults <= faulty_packet_N & faulty_packet_E & faulty_packet_W & faulty_packet_S & faulty_packet_L;
Faulty_N_out <= sig_Faulty_N_out;
Faulty_E_out <= sig_Faulty_E_out;
Faulty_W_out <= sig_Faulty_W_out;
Faulty_S_out <= sig_Faulty_S_out;
-- all the counter_threshold modules
CT_N: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_N, Healthy_packet => healthy_packet_N,
Healthy => healthy_link_N, intermittent=> intermittent_link_N, Faulty => sig_Faulty_N_out);
CT_E: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_E, Healthy_packet => healthy_packet_E,
Healthy => healthy_link_E, intermittent=> intermittent_link_E, Faulty => sig_Faulty_E_out);
CT_W: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_W, Healthy_packet => healthy_packet_W,
Healthy => healthy_link_W, intermittent=> intermittent_link_W, Faulty => sig_Faulty_W_out);
CT_S: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_S, Healthy_packet => healthy_packet_S,
Healthy => healthy_link_S, intermittent=> intermittent_link_S, Faulty => sig_Faulty_S_out);
CT_L: counter_threshold_classifier generic map(counter_depth => counter_depth, healthy_counter_threshold => healthy_counter_threshold, faulty_counter_threshold => faulty_counter_threshold)
port map(reset => reset, clk => clk, faulty_packet => faulty_packet_L, Healthy_packet => healthy_packet_L,
Healthy => healthy_link_L, intermittent=> intermittent_link_L, Faulty => faulty_link_L);
-- all the FIFOs
FIFO_N: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_N, valid_in => valid_in_N,
read_en_N => packet_drop_order_N, read_en_E =>Grant_EN, read_en_W =>Grant_WN, read_en_S =>Grant_SN, read_en_L =>Grant_LN,
credit_out => credit_out_N, empty_out => empty_N, Data_out => FIFO_D_out_N, fault_info=> faulty_packet_N, health_info=>healthy_packet_N);
FIFO_E: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_E, valid_in => valid_in_E,
read_en_N => Grant_NE, read_en_E =>packet_drop_order_E, read_en_W =>Grant_WE, read_en_S =>Grant_SE, read_en_L =>Grant_LE,
credit_out => credit_out_E, empty_out => empty_E, Data_out => FIFO_D_out_E, fault_info=> faulty_packet_E, health_info=>healthy_packet_E);
FIFO_W: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_W, valid_in => valid_in_W,
read_en_N => Grant_NW, read_en_E =>Grant_EW, read_en_W =>packet_drop_order_W, read_en_S =>Grant_SW, read_en_L =>Grant_LW,
credit_out => credit_out_W, empty_out => empty_W, Data_out => FIFO_D_out_W, fault_info=> faulty_packet_W, health_info=>healthy_packet_W);
FIFO_S: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_S, valid_in => valid_in_S,
read_en_N => Grant_NS, read_en_E =>Grant_ES, read_en_W =>Grant_WS, read_en_S =>packet_drop_order_S, read_en_L =>Grant_LS,
credit_out => credit_out_S, empty_out => empty_S, Data_out => FIFO_D_out_S, fault_info=> faulty_packet_S, health_info=>healthy_packet_S);
FIFO_L: FIFO_credit_based
generic map ( DATA_WIDTH => DATA_WIDTH)
port map ( reset => reset, clk => clk, RX => RX_L, valid_in => valid_in_L,
read_en_N => Grant_NL, read_en_E =>Grant_EL, read_en_W =>Grant_WL, read_en_S => Grant_SL, read_en_L =>packet_drop_order_L,
credit_out => credit_out_L, empty_out => empty_L, Data_out => FIFO_D_out_L, fault_info=> faulty_packet_L, health_info=>healthy_packet_L);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
parity_LBDR_N: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_N, empty_N, LBDR_Fault_N);
parity_LBDR_E: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_E, empty_E, LBDR_Fault_E);
parity_LBDR_W: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_W, empty_W, LBDR_Fault_W);
parity_LBDR_S: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_S, empty_S, LBDR_Fault_S);
parity_LBDR_L: parity_checker_for_LBDR generic map(DATA_WIDTH => DATA_WIDTH) port map(FIFO_D_out_L, empty_L, LBDR_Fault_L);
--- all the LBDRs
LBDR_N: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_N,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_N(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_N(NoC_size downto 1) ,
faulty => LBDR_Fault_N,
packet_drop_order => packet_drop_order_N,
grant_N => '0', grant_E =>Grant_EN, grant_W => Grant_WN, grant_S=>Grant_SN, grant_L =>Grant_LN,
Req_N=> Req_NN, Req_E=>Req_NE, Req_W=>Req_NW, Req_S=>Req_NS, Req_L=>Req_NL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_E: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_E,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_E(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_E(NoC_size downto 1) ,
faulty => LBDR_Fault_E,
packet_drop_order => packet_drop_order_E,
grant_N => Grant_NE, grant_E =>'0', grant_W => Grant_WE, grant_S=>Grant_SE, grant_L =>Grant_LE,
Req_N=> Req_EN, Req_E=>Req_EE, Req_W=>Req_EW, Req_S=>Req_ES, Req_L=>Req_EL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_W: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_W,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_W(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_W(NoC_size downto 1) ,
faulty => LBDR_Fault_W,
packet_drop_order => packet_drop_order_W,
grant_N => Grant_NW, grant_E =>Grant_EW, grant_W =>'0' ,grant_S=>Grant_SW, grant_L =>Grant_LW,
Req_N=> Req_WN, Req_E=>Req_WE, Req_W=>Req_WW, Req_S=>Req_WS, Req_L=>Req_WL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_S: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_S,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_S(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_S(NoC_size downto 1) ,
faulty => LBDR_Fault_S,
packet_drop_order => packet_drop_order_S,
grant_N => Grant_NS, grant_E =>Grant_ES, grant_W =>Grant_WS ,grant_S=>'0', grant_L =>Grant_LS,
Req_N=> Req_SN, Req_E=>Req_SE, Req_W=>Req_SW, Req_S=>Req_SS, Req_L=>Req_SL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
LBDR_L: LBDR_packet_drop generic map (cur_addr_rst => current_address, Cx_rst => Cx_rst, Rxy_rst => Rxy_rst, NoC_size => NoC_size)
PORT MAP (reset => reset, clk => clk, empty => empty_L,
Faulty_C_N => Faulty_N_in, Faulty_C_E => Faulty_E_in, Faulty_C_W => Faulty_W_in, Faulty_C_S => Faulty_S_in,
flit_type => FIFO_D_out_L(DATA_WIDTH-1 downto DATA_WIDTH-3), dst_addr=> FIFO_D_out_L(NoC_size downto 1) ,
faulty => LBDR_Fault_L,
packet_drop_order => packet_drop_order_L,
grant_N => Grant_NL, grant_E =>Grant_EL, grant_W => Grant_WL,grant_S=>Grant_SL, grant_L =>'0',
Req_N=> Req_LN, Req_E=>Req_LE, Req_W=>Req_LW, Req_S=>Req_LS, Req_L=>Req_LL,
Rxy_reconf_PE => Rxy_reconf_PE, Cx_reconf_PE => Cx_reconf_PE, Reconfig_command=>Reconfig_command);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- switch allocator
allocator_unit: allocator port map ( reset => reset, clk => clk,
-- flow control
credit_in_N => credit_in_N, credit_in_E => credit_in_E, credit_in_W => credit_in_W, credit_in_S => credit_in_S, credit_in_L => credit_in_L,
-- requests from the LBDRS
req_N_N => '0', req_N_E => Req_NE, req_N_W => Req_NW, req_N_S => Req_NS, req_N_L => Req_NL,
req_E_N => Req_EN, req_E_E => '0', req_E_W => Req_EW, req_E_S => Req_ES, req_E_L => Req_EL,
req_W_N => Req_WN, req_W_E => Req_WE, req_W_W => '0', req_W_S => Req_WS, req_W_L => Req_WL,
req_S_N => Req_SN, req_S_E => Req_SE, req_S_W => Req_SW, req_S_S => '0', req_S_L => Req_SL,
req_L_N => Req_LN, req_L_E => Req_LE, req_L_W => Req_LW, req_L_S => Req_LS, req_L_L => '0',
empty_N => empty_N, empty_E => empty_E, empty_w => empty_W, empty_S => empty_S, empty_L => empty_L,
valid_N => valid_out_N, valid_E => valid_out_E, valid_W => valid_out_W, valid_S => valid_out_S, valid_L => valid_out_L,
-- grant_X_Y means the grant for X output port towards Y input port
-- this means for any X in [N, E, W, S, L] then set grant_X_Y is one hot!
grant_N_N => Grant_NN, grant_N_E => Grant_NE, grant_N_W => Grant_NW, grant_N_S => Grant_NS, grant_N_L => Grant_NL,
grant_E_N => Grant_EN, grant_E_E => Grant_EE, grant_E_W => Grant_EW, grant_E_S => Grant_ES, grant_E_L => Grant_EL,
grant_W_N => Grant_WN, grant_W_E => Grant_WE, grant_W_W => Grant_WW, grant_W_S => Grant_WS, grant_W_L => Grant_WL,
grant_S_N => Grant_SN, grant_S_E => Grant_SE, grant_S_W => Grant_SW, grant_S_S => Grant_SS, grant_S_L => Grant_SL,
grant_L_N => Grant_LN, grant_L_E => Grant_LE, grant_L_W => Grant_LW, grant_L_S => Grant_LS, grant_L_L => Grant_LL
);
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbar select_signals
Xbar_sel_N <= '0' & Grant_NE & Grant_NW & Grant_NS & Grant_NL;
Xbar_sel_E <= Grant_EN & '0' & Grant_EW & Grant_ES & Grant_EL;
Xbar_sel_W <= Grant_WN & Grant_WE & '0' & Grant_WS & Grant_WL;
Xbar_sel_S <= Grant_SN & Grant_SE & Grant_SW & '0' & Grant_SL;
Xbar_sel_L <= Grant_LN & Grant_LE & Grant_LW & Grant_LS & '0';
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------------------------
-- all the Xbars
XBAR_N: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_N, Data_out=> TX_N);
XBAR_E: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_E, Data_out=> TX_E);
XBAR_W: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_W, Data_out=> TX_W);
XBAR_S: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_S, Data_out=> TX_S);
XBAR_L: XBAR generic map (DATA_WIDTH => DATA_WIDTH)
PORT MAP (North_in => FIFO_D_out_N, East_in => FIFO_D_out_E, West_in => FIFO_D_out_W, South_in => FIFO_D_out_S, Local_in => FIFO_D_out_L,
sel => Xbar_sel_L, Data_out=> TX_L);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity IO_ctl is
port(clk : in std_logic;
rst : in std_logic;
iport : in std_logic_vector(31 downto 0);
iport_data : out std_logic_vector(31 downto 0);
ipins : in std_logic_vector(7 downto 0);
ipins_data : out std_logic_vector(31 downto 0);
ipins_sel : in std_logic_vector(2 downto 0);
oport : out std_logic_vector(31 downto 0);
oport_data : in std_logic_vector(31 downto 0);
oport_en : in std_logic;
opins : out std_logic_vector(7 downto 0);
opins_data : in std_logic_vector(31 downto 0);
opins_sel : in std_logic_vector(2 downto 0);
opins_en : in std_logic
);
end IO_ctl;
architecture behavioral of IO_ctl is
signal iport_reg : std_logic_vector(31 downto 0);
signal ipins_reg : std_logic_vector(7 downto 0);
signal oport_reg : std_logic_vector(31 downto 0);
signal opins_reg : std_logic_vector(7 downto 0);
begin
iport_ctl : process (clk, rst) is
begin
if rst = '1' then
iport_reg <= (others => '0');
elsif rising_edge(clk) then
iport_reg <= iport;
end if;
end process;
iport_data <= iport_reg;
ipins_ctl : process (clk, rst) is
begin
if rst = '1' then
ipins_reg <= (others => '0');
elsif rising_edge(clk) then
ipins_reg <= ipins;
end if;
end process;
ipins_data <= "0000000000000000000000000000000" & ipins_reg(conv_integer(unsigned(ipins_sel)));
oport_ctl : process (clk, rst) is
begin
if rst = '1' then
oport_reg <= (others => '0');
elsif falling_edge(clk) then
if oport_en = '1' then
oport_reg <= oport_data;
end if;
end if;
end process;
oport <= oport_reg;
opins_ctl : process (clk, rst) is
begin
if rst = '1' then
opins_reg <= (others => '0');
elsif falling_edge(clk) then
if opins_en = '1' then
opins_reg(conv_integer(unsigned(opins_sel))) <= opins_data(0);
end if;
end if;
end process;
opins <= opins_reg;
end behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity IO_ctl is
port(clk : in std_logic;
rst : in std_logic;
iport : in std_logic_vector(31 downto 0);
iport_data : out std_logic_vector(31 downto 0);
ipins : in std_logic_vector(7 downto 0);
ipins_data : out std_logic_vector(31 downto 0);
ipins_sel : in std_logic_vector(2 downto 0);
oport : out std_logic_vector(31 downto 0);
oport_data : in std_logic_vector(31 downto 0);
oport_en : in std_logic;
opins : out std_logic_vector(7 downto 0);
opins_data : in std_logic_vector(31 downto 0);
opins_sel : in std_logic_vector(2 downto 0);
opins_en : in std_logic
);
end IO_ctl;
architecture behavioral of IO_ctl is
signal iport_reg : std_logic_vector(31 downto 0);
signal ipins_reg : std_logic_vector(7 downto 0);
signal oport_reg : std_logic_vector(31 downto 0);
signal opins_reg : std_logic_vector(7 downto 0);
begin
iport_ctl : process (clk, rst) is
begin
if rst = '1' then
iport_reg <= (others => '0');
elsif rising_edge(clk) then
iport_reg <= iport;
end if;
end process;
iport_data <= iport_reg;
ipins_ctl : process (clk, rst) is
begin
if rst = '1' then
ipins_reg <= (others => '0');
elsif rising_edge(clk) then
ipins_reg <= ipins;
end if;
end process;
ipins_data <= "0000000000000000000000000000000" & ipins_reg(conv_integer(unsigned(ipins_sel)));
oport_ctl : process (clk, rst) is
begin
if rst = '1' then
oport_reg <= (others => '0');
elsif falling_edge(clk) then
if oport_en = '1' then
oport_reg <= oport_data;
end if;
end if;
end process;
oport <= oport_reg;
opins_ctl : process (clk, rst) is
begin
if rst = '1' then
opins_reg <= (others => '0');
elsif falling_edge(clk) then
if opins_en = '1' then
opins_reg(conv_integer(unsigned(opins_sel))) <= opins_data(0);
end if;
end if;
end process;
opins <= opins_reg;
end behavioral; |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_scalars_fifo.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2012-11-04
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
library fifo_generator_v13_0_1;
use fifo_generator_v13_0_1.all;
entity xd_output_scalars_fifo is
generic (
C_FAMILY : string := "virtex6"; -- Xilinx FPGA family
C_MTBF_STAGES : integer := 4;
WIDTH : integer := 16);
port (
din : in std_logic_vector(WIDTH-1 downto 0);
din_vld : in std_logic;
din_rdy : out std_logic;
wr_clk : in std_logic;
dout : out std_logic_vector(WIDTH-1 downto 0);
dout_vld : out std_logic;
dout_rdy : in std_logic;
rd_used : out std_logic_vector(3 downto 0); -- Additional bit needed
rd_empty : out std_logic;
rd_full : out std_logic;
rd_clk : in std_logic;
rst : in std_logic);
end xd_output_scalars_fifo;
architecture rtl of xd_output_scalars_fifo is
-- FIFO constants
constant DEPTH : integer := 15;
constant FIFO_DEPTH : integer := calc_fifo_depth(DEPTH)+1;
constant ADDR_BITS : integer := log2(FIFO_DEPTH);
constant INIT_NEXT_RD_GRAY : integer := 2**ADDR_BITS-1;
constant INIT_RD_GRAY : integer := 2**ADDR_BITS-2;
constant INIT_PREV_RD_GRAY : integer := 2**ADDR_BITS-3;
constant INIT_NEXT_WR_GRAY : integer := INIT_NEXT_RD_GRAY;
constant INIT_WR_GRAY : integer := INIT_RD_GRAY;
constant INIT_WR_GRAY_AHEAD : integer := 2**ADDR_BITS-0;
signal rst_vec : std_logic_vector(0 downto 0);
signal wr_rst_vec : std_logic_vector(0 downto 0);
signal rd_rst_vec : std_logic_vector(0 downto 0);
signal wr_rst : std_logic;
signal rd_rst : std_logic;
signal rd_addr : unsigned(ADDR_BITS-1 downto 0);
signal wr_addr : unsigned(ADDR_BITS-1 downto 0);
-- Next signals are gray values:
signal wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_wr_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_gray_ahead : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal next_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
signal prev_rd_gray : std_logic_vector(ADDR_BITS-1 downto 0);
--
signal fifo_we : std_logic;
signal fifo_re : std_logic;
--
signal din_rdy_i : std_logic;
signal empty_i : std_logic;
signal rd_en : std_logic;
signal dout_vld_i : std_logic;
signal dout_trf_ok : std_logic;
type mem_type is array (2**ADDR_BITS-1 downto 0) of std_logic_vector (WIDTH-1 downto 0);
signal mem : mem_type;
attribute ram_style : string;
attribute ram_style of mem : signal is "distributed";
signal mem_dout : std_logic_vector(WIDTH-1 downto 0);
--
signal wr_gray_sync : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_bin : unsigned(ADDR_BITS-1 downto 0);
signal wr_bin : unsigned(ADDR_BITS-1 downto 0);
signal ptr_dist : unsigned(ADDR_BITS-1 downto 0);
signal rd_used_i : std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_full_i : std_logic;
signal empty : std_logic;
signal full : std_logic;
signal rstn : std_logic;
signal almost_full :std_logic;
signal wr_ack :std_logic;
signal overflow :std_logic;
signal almost_empty :std_logic;
signal valid :std_logic;
signal underflow :std_logic;
signal data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal rd_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal wr_data_count :std_logic_vector(ADDR_BITS-1 downto 0);
signal prog_full :std_logic;
signal prog_empty :std_logic;
signal sbiterr :std_logic;
signal dbiterr :std_logic;
signal wr_rst_busy :std_logic;
signal rd_rst_busy :std_logic;
signal m_axi_awid :std_logic_vector(0 downto 0);
signal m_axi_awaddr :std_logic_vector(31 downto 0);
signal m_axi_awlen :std_logic_vector(7 downto 0);
signal m_axi_awsize :std_logic_vector(2 downto 0);
signal m_axi_awburst :std_logic_vector(1 downto 0);
signal m_axi_awlock :std_logic_vector(0 downto 0);
signal m_axi_awcache :std_logic_vector(3 downto 0);
signal m_axi_awprot :std_logic_vector(2 downto 0);
signal m_axi_awqos :std_logic_vector(3 downto 0);
signal m_axi_awregion :std_logic_vector(3 downto 0);
signal m_axi_awuser :std_logic_vector(0 downto 0);
signal m_axi_awvalid :std_logic;
signal m_axi_wid :std_logic_vector(0 downto 0);
signal m_axi_wdata :std_logic_vector(63 downto 0);
signal m_axi_wstrb :std_logic_vector(7 downto 0);
signal m_axi_wlast :std_logic;
signal m_axi_wuser :std_logic_vector(0 downto 0);
signal m_axi_wvalid :std_logic;
signal m_axi_bready :std_logic;
signal s_axi_awready :std_logic;
signal s_axi_wready :std_logic;
signal s_axi_bid :std_logic_vector(0 downto 0);
signal s_axi_bresp :std_logic_vector(1 downto 0);
signal s_axi_buser :std_logic_vector(0 downto 0);
signal m_axi_arid :std_logic_vector(0 downto 0);
signal m_axi_araddr :std_logic_vector(31 downto 0);
signal m_axi_arlen :std_logic_vector(7 downto 0);
signal m_axi_arsize :std_logic_vector(2 downto 0);
signal m_axi_arburst :std_logic_vector(1 downto 0);
signal m_axi_arlock :std_logic_vector(0 downto 0);
signal m_axi_arcache :std_logic_vector(3 downto 0);
signal m_axi_arprot :std_logic_vector(2 downto 0);
signal m_axi_arqos :std_logic_vector(3 downto 0);
signal m_axi_arregion :std_logic_vector(3 downto 0);
signal m_axi_aruser :std_logic_vector(0 downto 0);
signal m_axi_arvalid :std_logic;
signal m_axi_rready :std_logic;
signal s_axi_arready :std_logic;
signal s_axi_rid :std_logic_vector(0 downto 0);
signal s_axi_rdata :std_logic_vector(63 downto 0);
signal s_axi_rresp :std_logic_vector(1 downto 0);
signal s_axi_rlast :std_logic;
signal s_axi_ruser :std_logic_vector(0 downto 0);
signal m_axis_tvalid :std_logic;
signal m_axis_tdata :std_logic_vector(7 downto 0);
signal m_axis_tstrb :std_logic_vector(0 downto 0);
signal m_axis_tlast :std_logic;
signal m_axis_tkeep :std_logic_vector(0 downto 0);
signal m_axis_tid :std_logic_vector(0 downto 0);
signal m_axis_tdest :std_logic_vector(0 downto 0);
signal m_axis_tuser :std_logic_vector(3 downto 0);
signal s_axis_tready :std_logic;
signal axi_aw_data_count :std_logic_vector(4 downto 0);
signal axi_aw_wr_data_count :std_logic_vector(4 downto 0);
signal axi_aw_rd_data_count :std_logic_vector(4 downto 0);
signal axi_aw_sbiterr :std_logic;
signal axi_aw_dbiterr :std_logic;
signal axi_aw_overflow :std_logic;
signal axi_aw_underflow :std_logic;
signal axi_aw_prog_full :std_logic;
signal axi_aw_prog_empty :std_logic;
signal axi_w_data_count :std_logic_vector(10 downto 0);
signal axi_w_wr_data_count :std_logic_vector(10 downto 0);
signal axi_w_rd_data_count :std_logic_vector(10 downto 0);
signal axi_w_sbiterr :std_logic;
signal axi_w_dbiterr :std_logic;
signal axi_w_overflow :std_logic;
signal axi_w_underflow :std_logic;
signal axi_w_prog_full :std_logic;
signal axi_w_prog_empty :std_logic;
signal axi_b_data_count :std_logic_vector(4 downto 0);
signal axi_b_wr_data_count :std_logic_vector(4 downto 0);
signal axi_b_rd_data_count :std_logic_vector(4 downto 0);
signal axi_b_sbiterr :std_logic;
signal axi_b_dbiterr :std_logic;
signal axi_b_overflow :std_logic;
signal axi_b_underflow :std_logic;
signal axi_b_prog_full :std_logic;
signal axi_b_prog_empty :std_logic;
signal axi_ar_data_count :std_logic_vector(4 downto 0);
signal axi_ar_wr_data_count :std_logic_vector(4 downto 0);
signal axi_ar_rd_data_count :std_logic_vector(4 downto 0);
signal axi_ar_sbiterr :std_logic;
signal axi_ar_dbiterr :std_logic;
signal axi_ar_overflow :std_logic;
signal axi_ar_underflow :std_logic;
signal axi_ar_prog_full :std_logic;
signal axi_ar_prog_empty :std_logic;
signal axi_r_data_count :std_logic_vector(10 downto 0);
signal axi_r_wr_data_count :std_logic_vector(10 downto 0);
signal axi_r_rd_data_count :std_logic_vector(10 downto 0);
signal axi_r_sbiterr :std_logic;
signal axi_r_dbiterr :std_logic;
signal axi_r_overflow :std_logic;
signal axi_r_underflow :std_logic;
signal axi_r_prog_full :std_logic;
signal axi_r_prog_empty :std_logic;
signal axis_data_count :std_logic_vector(10 downto 0);
signal axis_wr_data_count :std_logic_vector(10 downto 0);
signal axis_rd_data_count :std_logic_vector(10 downto 0);
signal axis_sbiterr :std_logic;
signal axis_dbiterr :std_logic;
signal axis_overflow :std_logic;
signal axis_underflow :std_logic;
signal axis_prog_full :std_logic;
signal axis_prog_empty :std_logic;
constant C_EXTRA_SYNCS : integer := 5;
begin
EXISTING : if (C_EXTRA_SYNCS = 0) generate
begin
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rst)
begin
if(rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rst)
begin
if(rst = '1') then
next_rd_gray <= bin2gray(INIT_NEXT_RD_GRAY, ADDR_BITS);
rd_gray <= bin2gray(INIT_RD_GRAY, ADDR_BITS);
prev_rd_gray <= bin2gray(INIT_PREV_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
next_wr_gray <= bin2gray(INIT_NEXT_WR_GRAY, ADDR_BITS);
wr_gray <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, rst)
begin
if(rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
-- process(wr_clk, rst)
-- begin
-- if(rst = '1') then
-- din_rdy_i <= '0';
-- elsif(wr_clk'event and wr_clk = '1') then
-- if(din_rdy_i = '1') then
-- if (wr_gray_ahead = prev_rd_gray) then
-- din_rdy_i <= not(fifo_we);
-- else
-- din_rdy_i <= '1';
-- end if;
-- else
-- if (wr_gray_ahead = rd_gray) then
-- din_rdy_i <= '0';
-- else
-- din_rdy_i <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
-- CR 741423 fix
-- If the oscalar_fifo_depth needs to be 16, din_rdy_i signal has to be validated on
-- next_wr_gray instead of wr_gray_ahead. wr_gray_ahead should be used
-- to keep the oscalar_fifo_depth equal to 15.
process(wr_clk, rst)
begin
if(rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (next_wr_gray = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (next_wr_gray = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rst)
begin
if(rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rst)
begin
if(rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
dout_trf_ok <= dout_vld_i and dout_rdy;
-----------------------------------------------------------------------
-- Memory bank modeling. Let's allow XST do it for us:
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rst)
begin
if(rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- wr_gray is synchronized with rd_clk to reduce metastability.
-- This inserts an extra rd_clk cycle latency
process(rd_clk, rst)
begin
if(rst = '1') then
wr_gray_sync <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
wr_gray_sync <= wr_gray;
end if;
end process;
wr_bin <= unsigned(gray2bin(wr_gray_sync));
process(rd_clk, rst)
begin
if(rst = '1') then
rd_bin <= to_unsigned(INIT_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
rd_bin <= rd_bin + 1;
end if;
end if;
end process;
process(rd_clk, rst)
begin
if(rst = '1') then
ptr_dist <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
ptr_dist <= ptr_dist - 1;
else
-- this is also valid at the end of count sequence:
-- wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
rd_used <= std_logic_vector(ptr_dist);
----
process(rd_clk, rst)
begin
if(rst = '1') then
rd_full_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
-- If there is a read, we exit inmediately the full state
if(dout_trf_ok = '1') then
rd_full_i <= '0';
else
-- Stay in full if next_wr_gray = rd_gray
if(next_wr_gray = rd_gray) then
rd_full_i <= '1';
else
rd_full_i <= '0';
end if;
end if;
end if;
end process;
rd_full <= rd_full_i;
rd_empty <= not(dout_vld_i);
end generate EXISTING;
NEW_INTRO : if (C_EXTRA_SYNCS = 2) generate
begin
rst_vec(0) <= rst;
wr_rst <= wr_rst_vec(0);
rd_rst <= rd_rst_vec(0);
wr_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => wr_clk,
D => rst_vec,
Q => wr_rst_vec
);
rd_rst_sync: ENTITY axis_accelerator_adapter_v2_1_6.synchronizer_ff
GENERIC MAP (
C_HAS_RST => 0,
C_WIDTH => 1
)
PORT MAP (
RST => open,
CLK => rd_clk,
D => rst_vec,
Q => rd_rst_vec
);
fifo_we <= din_vld and din_rdy_i;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_addr <= (others => '0');
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_addr <= wr_addr + 1;
end if;
end if;
end process;
fifo_re <= rd_en and not(empty_i);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_addr <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
rd_addr <= rd_addr + 1;
end if;
end if;
end process;
---------------------------------------------------------
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
next_rd_gray <= bin2gray(INIT_NEXT_RD_GRAY, ADDR_BITS);
rd_gray <= bin2gray(INIT_RD_GRAY, ADDR_BITS);
prev_rd_gray <= bin2gray(INIT_PREV_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
prev_rd_gray <= rd_gray;
rd_gray <= next_rd_gray;
next_rd_gray <= bin2gray(std_logic_vector(rd_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
next_wr_gray <= bin2gray(INIT_NEXT_WR_GRAY, ADDR_BITS);
wr_gray <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray <= next_wr_gray;
next_wr_gray <= bin2gray(std_logic_vector(wr_addr));
end if;
end if;
end process;
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
wr_gray_ahead <= bin2gray(INIT_WR_GRAY_AHEAD, ADDR_BITS);
elsif(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
wr_gray_ahead <= gray_inc(wr_gray_ahead);
end if;
end if;
end process;
-----------------------------------------------------------------
-- process(wr_clk, rst)
-- begin
-- if(rst = '1') then
-- din_rdy_i <= '0';
-- elsif(wr_clk'event and wr_clk = '1') then
-- if(din_rdy_i = '1') then
-- if (wr_gray_ahead = prev_rd_gray) then
-- din_rdy_i <= not(fifo_we);
-- else
-- din_rdy_i <= '1';
-- end if;
-- else
-- if (wr_gray_ahead = rd_gray) then
-- din_rdy_i <= '0';
-- else
-- din_rdy_i <= '1';
-- end if;
-- end if;
-- end if;
-- end process;
-- CR 741423 fix
-- If the oscalar_fifo_depth needs to be 16, din_rdy_i signal has to be validated on
-- next_wr_gray instead of wr_gray_ahead. wr_gray_ahead should be used
-- to keep the oscalar_fifo_depth equal to 15.
process(wr_clk, wr_rst)
begin
if(wr_rst = '1') then
din_rdy_i <= '0';
elsif(wr_clk'event and wr_clk = '1') then
if(din_rdy_i = '1') then
if (next_wr_gray = prev_rd_gray) then
din_rdy_i <= not(fifo_we);
else
din_rdy_i <= '1';
end if;
else
if (next_wr_gray = rd_gray) then
din_rdy_i <= '0';
else
din_rdy_i <= '1';
end if;
end if;
end if;
end process;
din_rdy <= din_rdy_i;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
empty_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
if(empty_i = '0') then
if(next_rd_gray = wr_gray) then
empty_i <= fifo_re;
else
empty_i <= '0';
end if;
else
if(rd_gray = wr_gray) then
empty_i <= '1';
else
empty_i <= '0';
end if;
end if;
end if;
end process;
rd_en <= not(dout_vld_i) or (dout_vld_i and dout_rdy);
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout_vld_i <= '0';
elsif(rd_clk'event and rd_clk = '1') then
if(rd_en = '1') then
dout_vld_i <= not(empty_i);
end if;
end if;
end process;
dout_vld <= dout_vld_i;
dout_trf_ok <= dout_vld_i and dout_rdy;
-----------------------------------------------------------------------
-- Memory bank modeling. Let's allow XST do it for us:
process(wr_clk)
begin
if(wr_clk'event and wr_clk = '1') then
if(fifo_we = '1') then
mem(to_integer(wr_addr)) <= din;
end if;
end if;
end process;
mem_dout <= mem(to_integer(rd_addr));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
dout <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if(fifo_re = '1') then
dout <= mem_dout;
end if;
end if;
end process;
-----------------------------------------------------------------------
-- wr_gray is synchronized with rd_clk to reduce metastability.
-- This inserts an extra rd_clk cycle latency
-- clkx_1: ENTITY axis_accelerator_adapter_v2_1_6.clk_x_pntrs
-- GENERIC MAP(
-- C_HAS_RST => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_MSGON_VAL => 1,
-- C_SYNCHRONIZER_STAGE => 2
-- )
-- PORT MAP(
-- WR_CLK => wr_clk,
-- RD_CLK => rd_clk,
-- WR_RST => wr_rst,
-- RD_RST => rd_rst,
-- WR_PNTR => wr_gray,
-- RD_PNTR => open,
-- WR_PNTR_RD => wr_gray_sync,
-- RD_PNTR_WR => open
-- );
-- process(rd_clk, rd_rst)
-- begin
-- if(rd_rst = '1') then
-- wr_gray_sync <= bin2gray(INIT_WR_GRAY, ADDR_BITS);
-- elsif(rd_clk'event and rd_clk = '1') then
-- wr_gray_sync <= wr_gray;
-- end if;
-- end process;
wr_bin <= unsigned(gray2bin(wr_gray_sync));
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_bin <= to_unsigned(INIT_RD_GRAY, ADDR_BITS);
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
rd_bin <= rd_bin + 1;
end if;
end if;
end process;
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
ptr_dist <= (others => '0');
elsif(rd_clk'event and rd_clk = '1') then
if (dout_trf_ok = '1') then
ptr_dist <= ptr_dist - 1;
else
-- this is also valid at the end of count sequence:
-- wr_bin < rd_bin
ptr_dist <= wr_bin - rd_bin;
end if;
end if;
end process;
rd_used <= std_logic_vector(ptr_dist(3 downto 0));
----
process(rd_clk, rd_rst)
begin
if(rd_rst = '1') then
rd_full_i <= '1';
elsif(rd_clk'event and rd_clk = '1') then
-- If there is a read, we exit inmediately the full state
if(dout_trf_ok = '1') then
rd_full_i <= '0';
else
-- Stay in full if next_wr_gray = rd_gray
if(next_wr_gray = rd_gray) then
rd_full_i <= '1';
else
rd_full_i <= '0';
end if;
end if;
end if;
end process;
rd_full <= rd_full_i;
rd_empty <= not(dout_vld_i);
end generate NEW_INTRO;
NEW_INTRO2 : if (C_EXTRA_SYNCS = 1) generate
begin
din_rdy <= not(full);
dout_vld <= not(empty);
rd_empty <= (empty);
rd_full <= (full);
-- FIF_DMG_INST : entity fifo_generator_v12_0_5.fifo_generator_v12_0_5
-- GENERIC MAP (
-- C_COMMON_CLOCK => 0,
-- C_COUNT_TYPE => 0,
-- C_DATA_COUNT_WIDTH => ADDR_BITS,
-- C_DEFAULT_VALUE => "BlankString",
-- C_DIN_WIDTH => WIDTH,
-- C_DOUT_RST_VAL => "0",
-- C_DOUT_WIDTH => WIDTH,
-- C_ENABLE_RLOCS => 0,
-- C_FAMILY => C_FAMILY,
-- C_FULL_FLAGS_RST_VAL => 0,
-- C_HAS_ALMOST_EMPTY => 0,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_BACKUP => 0,
-- C_HAS_DATA_COUNT => 0,
-- C_HAS_INT_CLK => 0,
-- C_HAS_MEMINIT_FILE => 0,
-- C_HAS_OVERFLOW => 0,
-- C_HAS_RD_DATA_COUNT => 1,
-- C_HAS_RD_RST => 0,
-- C_HAS_RST => 1,
-- C_HAS_SRST => 0,
-- C_HAS_UNDERFLOW => 0,
-- C_HAS_VALID => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_DATA_COUNT => 0,
-- C_HAS_WR_RST => 0,
-- C_IMPLEMENTATION_TYPE => 2,
-- C_INIT_WR_PNTR_VAL => 0,
-- C_MEMORY_TYPE => 2,
-- C_MIF_FILE_NAME => "BlankString",
-- C_OPTIMIZATION_MODE => 0,
-- C_OVERFLOW_LOW => 0,
-- C_PRELOAD_LATENCY => 0,
-- C_PRELOAD_REGS => 1,
-- C_PRIM_FIFO_TYPE => "512x36",
-- C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
-- C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
-- C_PROG_EMPTY_TYPE => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL => 29,
-- C_PROG_FULL_THRESH_NEGATE_VAL => 28,
-- C_PROG_FULL_TYPE => 0,
-- C_RD_DATA_COUNT_WIDTH => 4,
-- C_RD_DEPTH => FIFO_DEPTH,
-- C_RD_FREQ => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_UNDERFLOW_LOW => 0,
-- C_USE_DOUT_RST => 1,
-- C_USE_ECC => 0,
-- C_USE_EMBEDDED_REG => 0,
-- C_USE_PIPELINE_REG => 0,
-- C_POWER_SAVING_MODE => 0,
-- C_USE_FIFO16_FLAGS => 0,
-- C_USE_FWFT_DATA_COUNT => 0,
-- C_VALID_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
-- C_WR_DEPTH => FIFO_DEPTH,
-- C_WR_FREQ => 1,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_WR_RESPONSE_LATENCY => 1,
-- C_MSGON_VAL => 1,
-- C_ENABLE_RST_SYNC => 1,
-- C_ERROR_INJECTION_TYPE => 0,
-- C_SYNCHRONIZER_STAGE => 2,
-- C_INTERFACE_TYPE => 0,
-- C_AXI_TYPE => 1,
-- C_HAS_AXI_WR_CHANNEL => 1,
-- C_HAS_AXI_RD_CHANNEL => 1,
-- C_HAS_SLAVE_CE => 0,
-- C_HAS_MASTER_CE => 0,
-- C_ADD_NGC_CONSTRAINT => 0,
-- C_USE_COMMON_OVERFLOW => 0,
-- C_USE_COMMON_UNDERFLOW => 0,
-- C_USE_DEFAULT_SETTINGS => 0,
-- C_AXI_ID_WIDTH => 1,
-- C_AXI_ADDR_WIDTH => 32,
-- C_AXI_DATA_WIDTH => 64,
-- C_AXI_LEN_WIDTH => 8,
-- C_AXI_LOCK_WIDTH => 1,
-- C_HAS_AXI_ID => 0,
-- C_HAS_AXI_AWUSER => 0,
-- C_HAS_AXI_WUSER => 0,
-- C_HAS_AXI_BUSER => 0,
-- C_HAS_AXI_ARUSER => 0,
-- C_HAS_AXI_RUSER => 0,
-- C_AXI_ARUSER_WIDTH => 1,
-- C_AXI_AWUSER_WIDTH => 1,
-- C_AXI_WUSER_WIDTH => 1,
-- C_AXI_BUSER_WIDTH => 1,
-- C_AXI_RUSER_WIDTH => 1,
-- C_HAS_AXIS_TDATA => 1,
-- C_HAS_AXIS_TID => 0,
-- C_HAS_AXIS_TDEST => 0,
-- C_HAS_AXIS_TUSER => 1,
-- C_HAS_AXIS_TREADY => 1,
-- C_HAS_AXIS_TLAST => 0,
-- C_HAS_AXIS_TSTRB => 0,
-- C_HAS_AXIS_TKEEP => 0,
-- C_AXIS_TDATA_WIDTH => WIDTH,
-- C_AXIS_TID_WIDTH => 1,
-- C_AXIS_TDEST_WIDTH => 1,
-- C_AXIS_TUSER_WIDTH => 4,
-- C_AXIS_TSTRB_WIDTH => 1,
-- C_AXIS_TKEEP_WIDTH => 1,
-- C_WACH_TYPE => 0,
-- C_WDCH_TYPE => 0,
-- C_WRCH_TYPE => 0,
-- C_RACH_TYPE => 0,
-- C_RDCH_TYPE => 0,
-- C_AXIS_TYPE => 0,
-- C_IMPLEMENTATION_TYPE_WACH => 1,
-- C_IMPLEMENTATION_TYPE_WDCH => 1,
-- C_IMPLEMENTATION_TYPE_WRCH => 1,
-- C_IMPLEMENTATION_TYPE_RACH => 1,
-- C_IMPLEMENTATION_TYPE_RDCH => 1,
-- C_IMPLEMENTATION_TYPE_AXIS => 1,
-- C_APPLICATION_TYPE_WACH => 0,
-- C_APPLICATION_TYPE_WDCH => 0,
-- C_APPLICATION_TYPE_WRCH => 0,
-- C_APPLICATION_TYPE_RACH => 0,
-- C_APPLICATION_TYPE_RDCH => 0,
-- C_APPLICATION_TYPE_AXIS => 0,
-- C_PRIM_FIFO_TYPE_WACH => "512x36",
-- C_PRIM_FIFO_TYPE_WDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_WRCH => "512x36",
-- C_PRIM_FIFO_TYPE_RACH => "512x36",
-- C_PRIM_FIFO_TYPE_RDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_AXIS => "1kx18",
-- C_USE_ECC_WACH => 0,
-- C_USE_ECC_WDCH => 0,
-- C_USE_ECC_WRCH => 0,
-- C_USE_ECC_RACH => 0,
-- C_USE_ECC_RDCH => 0,
-- C_USE_ECC_AXIS => 0,
-- C_ERROR_INJECTION_TYPE_WACH => 0,
-- C_ERROR_INJECTION_TYPE_WDCH => 0,
-- C_ERROR_INJECTION_TYPE_WRCH => 0,
-- C_ERROR_INJECTION_TYPE_RACH => 0,
-- C_ERROR_INJECTION_TYPE_RDCH => 0,
-- C_ERROR_INJECTION_TYPE_AXIS => 0,
-- C_DIN_WIDTH_WACH => 32,
-- C_DIN_WIDTH_WDCH => 64,
-- C_DIN_WIDTH_WRCH => 2,
-- C_DIN_WIDTH_RACH => 32,
-- C_DIN_WIDTH_RDCH => 64,
-- C_DIN_WIDTH_AXIS => 1,
-- C_WR_DEPTH_WACH => 16,
-- C_WR_DEPTH_WDCH => 1024,
-- C_WR_DEPTH_WRCH => 16,
-- C_WR_DEPTH_RACH => 16,
-- C_WR_DEPTH_RDCH => 1024,
-- C_WR_DEPTH_AXIS => 1024,
-- C_WR_PNTR_WIDTH_WACH => 4,
-- C_WR_PNTR_WIDTH_WDCH => 10,
-- C_WR_PNTR_WIDTH_WRCH => 4,
-- C_WR_PNTR_WIDTH_RACH => 4,
-- C_WR_PNTR_WIDTH_RDCH => 10,
-- C_WR_PNTR_WIDTH_AXIS => 10,
-- C_HAS_DATA_COUNTS_WACH => 0,
-- C_HAS_DATA_COUNTS_WDCH => 0,
-- C_HAS_DATA_COUNTS_WRCH => 0,
-- C_HAS_DATA_COUNTS_RACH => 0,
-- C_HAS_DATA_COUNTS_RDCH => 0,
-- C_HAS_DATA_COUNTS_AXIS => 0,
-- C_HAS_PROG_FLAGS_WACH => 0,
-- C_HAS_PROG_FLAGS_WDCH => 0,
-- C_HAS_PROG_FLAGS_WRCH => 0,
-- C_HAS_PROG_FLAGS_RACH => 0,
-- C_HAS_PROG_FLAGS_RDCH => 0,
-- C_HAS_PROG_FLAGS_AXIS => 0,
-- C_PROG_FULL_TYPE_WACH => 0,
-- C_PROG_FULL_TYPE_WDCH => 0,
-- C_PROG_FULL_TYPE_WRCH => 0,
-- C_PROG_FULL_TYPE_RACH => 0,
-- C_PROG_FULL_TYPE_RDCH => 0,
-- C_PROG_FULL_TYPE_AXIS => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
-- C_PROG_EMPTY_TYPE_WACH => 0,
-- C_PROG_EMPTY_TYPE_WDCH => 0,
-- C_PROG_EMPTY_TYPE_WRCH => 0,
-- C_PROG_EMPTY_TYPE_RACH => 0,
-- C_PROG_EMPTY_TYPE_RDCH => 0,
-- C_PROG_EMPTY_TYPE_AXIS => 0,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
-- C_REG_SLICE_MODE_WACH => 0,
-- C_REG_SLICE_MODE_WDCH => 0,
-- C_REG_SLICE_MODE_WRCH => 0,
-- C_REG_SLICE_MODE_RACH => 0,
-- C_REG_SLICE_MODE_RDCH => 0,
-- C_REG_SLICE_MODE_AXIS => 0
-- )
-- PORT MAP (
-- backup => '0',
-- backup_marker => '0',
-- clk => '0',
-- rst => rst,
-- srst => '0',
-- wr_clk => wr_clk,
-- rd_clk => rd_clk,
-- din => din,
-- wr_en => din_vld,
-- rd_en => dout_rdy,
-- prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- int_clk => '0',
-- injectdbiterr => '0',
-- injectsbiterr => '0',
-- sleep => '0',
-- dout => dout,
-- full => full,
-- empty => empty,
-- rd_data_count => rd_used,
-- m_aclk => '0',
-- s_aclk => '0',
-- s_aresetn => '0',
-- m_aclk_en => '0',
-- s_aclk_en => '0',
-- s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awvalid => '0',
-- s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_wlast => '0',
-- s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wvalid => '0',
-- s_axi_bready => '0',
-- m_axi_awready => '0',
-- m_axi_wready => '0',
-- m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bvalid => '0',
-- s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arvalid => '0',
-- s_axi_rready => '0',
-- m_axi_arready => '0',
-- m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_rlast => '0',
-- m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rvalid => '0',
-- s_axis_tvalid => '0',
-- s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tlast => '0',
-- s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- m_axis_tready => '0',
-- axi_aw_injectsbiterr => '0',
-- axi_aw_injectdbiterr => '0',
-- axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_w_injectsbiterr => '0',
-- axi_w_injectdbiterr => '0',
-- axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_b_injectsbiterr => '0',
-- axi_b_injectdbiterr => '0',
-- axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_ar_injectsbiterr => '0',
-- axi_ar_injectdbiterr => '0',
-- axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- axi_r_injectsbiterr => '0',
-- axi_r_injectdbiterr => '0',
-- axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_injectsbiterr => '0',
-- axis_injectdbiterr => '0',
-- axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
-- );
end generate NEW_INTRO2;
NEW_INTRO3 : if (C_EXTRA_SYNCS = 5) generate
begin
rstn <= not(rst);
din_rdy <= not(full);
din_rdy_i <= not(full);
dout_vld <= not(empty);
rd_empty <= (empty);
rd_full <= (full);
-- din_rdy <= din_rdy_i;
-- dout_vld <= dout_vld_i;
-- rd_empty <= not(dout_vld_i);
-- rd_full <= not(din_rdy_i);
rd_used <= rd_used_i(3 downto 0);
FIF_DMG_INST : entity fifo_generator_v13_0_1.fifo_generator_v13_0_1
GENERIC MAP (
C_COMMON_CLOCK => 0,
C_COUNT_TYPE => 0,
C_DATA_COUNT_WIDTH => ADDR_BITS,
C_DEFAULT_VALUE => "BlankString",
C_DIN_WIDTH => WIDTH,
C_DOUT_RST_VAL => "0",
C_DOUT_WIDTH => WIDTH,
C_ENABLE_RLOCS => 0,
C_FAMILY => C_FAMILY,
C_FULL_FLAGS_RST_VAL => 0,
C_HAS_ALMOST_EMPTY => 0,
C_HAS_ALMOST_FULL => 0,
C_HAS_BACKUP => 0,
C_HAS_DATA_COUNT => 0,
C_HAS_INT_CLK => 0,
C_HAS_MEMINIT_FILE => 0,
C_HAS_OVERFLOW => 0,
C_HAS_RD_DATA_COUNT => 1,
C_HAS_RD_RST => 0,
C_HAS_RST => 1,
C_HAS_SRST => 0,
C_HAS_UNDERFLOW => 0,
C_HAS_VALID => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_DATA_COUNT => 1,
C_HAS_WR_RST => 0,
C_IMPLEMENTATION_TYPE => 2,
C_INIT_WR_PNTR_VAL => 0,
C_MEMORY_TYPE => 2,
C_MIF_FILE_NAME => "BlankString",
C_OPTIMIZATION_MODE => 0,
C_OVERFLOW_LOW => 0,
C_PRELOAD_LATENCY => 0,
C_PRELOAD_REGS => 1,
C_PRIM_FIFO_TYPE => "512x36",
C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
C_PROG_EMPTY_TYPE => 0,
C_PROG_FULL_THRESH_ASSERT_VAL => 29,
C_PROG_FULL_THRESH_NEGATE_VAL => 28,
C_PROG_FULL_TYPE => 0,
C_RD_DATA_COUNT_WIDTH => 4,
C_RD_DEPTH => FIFO_DEPTH,
C_RD_FREQ => 1,
C_RD_PNTR_WIDTH => ADDR_BITS,
C_UNDERFLOW_LOW => 0,
C_USE_DOUT_RST => 1,
C_USE_ECC => 0,
C_USE_EMBEDDED_REG => 0,
C_USE_PIPELINE_REG => 0,
C_POWER_SAVING_MODE => 0,
C_USE_FIFO16_FLAGS => 0,
C_USE_FWFT_DATA_COUNT => 1,
C_VALID_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_DATA_COUNT_WIDTH => ADDR_BITS,
C_WR_DEPTH => FIFO_DEPTH,
C_WR_FREQ => 1,
C_WR_PNTR_WIDTH => ADDR_BITS,
C_WR_RESPONSE_LATENCY => 1,
C_MSGON_VAL => 1,
C_ENABLE_RST_SYNC => 1,
C_ERROR_INJECTION_TYPE => 0,
C_SYNCHRONIZER_STAGE => 2,
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_HAS_AXI_WR_CHANNEL => 1,
C_HAS_AXI_RD_CHANNEL => 1,
C_HAS_SLAVE_CE => 0,
C_HAS_MASTER_CE => 0,
C_ADD_NGC_CONSTRAINT => 0,
C_USE_COMMON_OVERFLOW => 0,
C_USE_COMMON_UNDERFLOW => 0,
C_USE_DEFAULT_SETTINGS => 0,
C_AXI_ID_WIDTH => 1,
C_AXI_ADDR_WIDTH => 32,
C_AXI_DATA_WIDTH => 64,
C_AXI_LEN_WIDTH => 8,
C_AXI_LOCK_WIDTH => 1,
C_HAS_AXI_ID => 0,
C_HAS_AXI_AWUSER => 0,
C_HAS_AXI_WUSER => 0,
C_HAS_AXI_BUSER => 0,
C_HAS_AXI_ARUSER => 0,
C_HAS_AXI_RUSER => 0,
C_AXI_ARUSER_WIDTH => 1,
C_AXI_AWUSER_WIDTH => 1,
C_AXI_WUSER_WIDTH => 1,
C_AXI_BUSER_WIDTH => 1,
C_AXI_RUSER_WIDTH => 1,
C_HAS_AXIS_TDATA => 1,
C_HAS_AXIS_TID => 0,
C_HAS_AXIS_TDEST => 0,
C_HAS_AXIS_TUSER => 1,
C_HAS_AXIS_TREADY => 1,
C_HAS_AXIS_TLAST => 0,
C_HAS_AXIS_TSTRB => 0,
C_HAS_AXIS_TKEEP => 0,
C_AXIS_TDATA_WIDTH => 8,
C_AXIS_TID_WIDTH => 1,
C_AXIS_TDEST_WIDTH => 1,
C_AXIS_TUSER_WIDTH => 4,
C_AXIS_TSTRB_WIDTH => 1,
C_AXIS_TKEEP_WIDTH => 1,
C_WACH_TYPE => 0,
C_WDCH_TYPE => 0,
C_WRCH_TYPE => 0,
C_RACH_TYPE => 0,
C_RDCH_TYPE => 0,
C_AXIS_TYPE => 0,
C_IMPLEMENTATION_TYPE_WACH => 1,
C_IMPLEMENTATION_TYPE_WDCH => 1,
C_IMPLEMENTATION_TYPE_WRCH => 1,
C_IMPLEMENTATION_TYPE_RACH => 1,
C_IMPLEMENTATION_TYPE_RDCH => 1,
C_IMPLEMENTATION_TYPE_AXIS => 1,
C_APPLICATION_TYPE_WACH => 0,
C_APPLICATION_TYPE_WDCH => 0,
C_APPLICATION_TYPE_WRCH => 0,
C_APPLICATION_TYPE_RACH => 0,
C_APPLICATION_TYPE_RDCH => 0,
C_APPLICATION_TYPE_AXIS => 0,
C_PRIM_FIFO_TYPE_WACH => "512x36",
C_PRIM_FIFO_TYPE_WDCH => "1kx36",
C_PRIM_FIFO_TYPE_WRCH => "512x36",
C_PRIM_FIFO_TYPE_RACH => "512x36",
C_PRIM_FIFO_TYPE_RDCH => "1kx36",
C_PRIM_FIFO_TYPE_AXIS => "1kx18",
C_USE_ECC_WACH => 0,
C_USE_ECC_WDCH => 0,
C_USE_ECC_WRCH => 0,
C_USE_ECC_RACH => 0,
C_USE_ECC_RDCH => 0,
C_USE_ECC_AXIS => 0,
C_ERROR_INJECTION_TYPE_WACH => 0,
C_ERROR_INJECTION_TYPE_WDCH => 0,
C_ERROR_INJECTION_TYPE_WRCH => 0,
C_ERROR_INJECTION_TYPE_RACH => 0,
C_ERROR_INJECTION_TYPE_RDCH => 0,
C_ERROR_INJECTION_TYPE_AXIS => 0,
C_DIN_WIDTH_WACH => 32,
C_DIN_WIDTH_WDCH => 64,
C_DIN_WIDTH_WRCH => 2,
C_DIN_WIDTH_RACH => 32,
C_DIN_WIDTH_RDCH => 64,
C_DIN_WIDTH_AXIS => 1,
C_WR_DEPTH_WACH => 16,
C_WR_DEPTH_WDCH => 1024,
C_WR_DEPTH_WRCH => 16,
C_WR_DEPTH_RACH => 16,
C_WR_DEPTH_RDCH => 1024,
C_WR_DEPTH_AXIS => 1024,
C_WR_PNTR_WIDTH_WACH => 4,
C_WR_PNTR_WIDTH_WDCH => 10,
C_WR_PNTR_WIDTH_WRCH => 4,
C_WR_PNTR_WIDTH_RACH => 4,
C_WR_PNTR_WIDTH_RDCH => 10,
C_WR_PNTR_WIDTH_AXIS => 10,
C_HAS_DATA_COUNTS_WACH => 0,
C_HAS_DATA_COUNTS_WDCH => 0,
C_HAS_DATA_COUNTS_WRCH => 0,
C_HAS_DATA_COUNTS_RACH => 0,
C_HAS_DATA_COUNTS_RDCH => 0,
C_HAS_DATA_COUNTS_AXIS => 3,
C_HAS_PROG_FLAGS_WACH => 0,
C_HAS_PROG_FLAGS_WDCH => 0,
C_HAS_PROG_FLAGS_WRCH => 0,
C_HAS_PROG_FLAGS_RACH => 0,
C_HAS_PROG_FLAGS_RDCH => 0,
C_HAS_PROG_FLAGS_AXIS => 0,
C_PROG_FULL_TYPE_WACH => 0,
C_PROG_FULL_TYPE_WDCH => 0,
C_PROG_FULL_TYPE_WRCH => 0,
C_PROG_FULL_TYPE_RACH => 0,
C_PROG_FULL_TYPE_RDCH => 0,
C_PROG_FULL_TYPE_AXIS => 0,
C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
C_PROG_EMPTY_TYPE_WACH => 0,
C_PROG_EMPTY_TYPE_WDCH => 0,
C_PROG_EMPTY_TYPE_WRCH => 0,
C_PROG_EMPTY_TYPE_RACH => 0,
C_PROG_EMPTY_TYPE_RDCH => 0,
C_PROG_EMPTY_TYPE_AXIS => 0,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
C_REG_SLICE_MODE_WACH => 0,
C_REG_SLICE_MODE_WDCH => 0,
C_REG_SLICE_MODE_WRCH => 0,
C_REG_SLICE_MODE_RACH => 0,
C_REG_SLICE_MODE_RDCH => 0,
C_REG_SLICE_MODE_AXIS => 0
)
PORT MAP (
backup => '0',
backup_marker => '0',
clk => '0',
rst => rst,
srst => '0',
wr_clk => wr_clk,
wr_rst => '0',
rd_clk => rd_clk,
rd_rst => '0',
din => din,
wr_en => din_vld,
rd_en => dout_rdy,
prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
int_clk => '0',
injectdbiterr => '0',
injectsbiterr => '0',
sleep => '0',
dout => dout,
full => full,
almost_full => almost_full,
wr_ack => wr_ack,
overflow => overflow,
empty => empty,
almost_empty => almost_empty,
valid => valid,
underflow => underflow,
data_count => data_count,
rd_data_count => rd_data_count,
wr_data_count => rd_used_i,
prog_full => prog_full,
prog_empty => prog_empty,
sbiterr => sbiterr,
dbiterr => dbiterr,
wr_rst_busy => wr_rst_busy,
rd_rst_busy => rd_rst_busy,
m_aclk => '0',
s_aclk => '0',
s_aresetn => '0',
m_aclk_en => '0',
s_aclk_en => '0',
m_axi_awid => m_axi_awid,
m_axi_awaddr => m_axi_awaddr,
m_axi_awlen => m_axi_awlen,
m_axi_awsize => m_axi_awsize,
m_axi_awburst => m_axi_awburst,
m_axi_awlock => m_axi_awlock,
m_axi_awcache => m_axi_awcache,
m_axi_awprot => m_axi_awprot,
m_axi_awqos => m_axi_awqos,
m_axi_awregion => m_axi_awregion,
m_axi_awuser => m_axi_awuser,
m_axi_awvalid => m_axi_awvalid,
m_axi_awready => '0',
m_axi_wid => m_axi_wid,
m_axi_wdata => m_axi_wdata,
m_axi_wstrb => m_axi_wstrb,
m_axi_wlast => m_axi_wlast,
m_axi_wuser => m_axi_wuser,
m_axi_wvalid => m_axi_wvalid,
m_axi_wready => '0',
m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_bvalid => '0',
m_axi_bready => m_axi_bready,
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_awvalid => '0',
s_axi_awready => s_axi_awready,
s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wlast => '0',
s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wvalid => '0',
s_axi_wready => s_axi_wready,
s_axi_bid => s_axi_bid,
s_axi_bresp => s_axi_bresp,
s_axi_buser => s_axi_buser,
s_axi_bready => '0',
m_axi_arid => m_axi_arid,
m_axi_araddr => m_axi_araddr,
m_axi_arlen => m_axi_arlen,
m_axi_arsize => m_axi_arsize,
m_axi_arburst => m_axi_arburst,
m_axi_arlock => m_axi_arlock,
m_axi_arcache => m_axi_arcache,
m_axi_arprot => m_axi_arprot,
m_axi_arqos => m_axi_arqos,
m_axi_arregion => m_axi_arregion,
m_axi_aruser => m_axi_aruser,
m_axi_arvalid => m_axi_arvalid,
m_axi_arready => '0',
m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
m_axi_rlast => '0',
m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axi_rvalid => '0',
m_axi_rready => m_axi_rready,
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_arvalid => '0',
s_axi_arready => s_axi_arready,
s_axi_rid => s_axi_rid,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rlast => s_axi_rlast,
s_axi_ruser => s_axi_ruser,
s_axi_rready => '0',
m_axis_tvalid => m_axis_tvalid,
m_axis_tready => '0',
m_axis_tdata => m_axis_tdata ,
m_axis_tstrb => m_axis_tstrb ,
m_axis_tkeep => m_axis_tkeep ,
m_axis_tlast => m_axis_tlast ,
m_axis_tid => m_axis_tid ,
m_axis_tdest => m_axis_tdest ,
m_axis_tuser => m_axis_tuser ,
s_axis_tvalid => '0',
s_axis_tready => s_axis_tready,
s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tlast => '0',
s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_injectsbiterr => '0',
axi_aw_injectdbiterr => '0',
axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_aw_data_count => axi_aw_data_count,
axi_aw_wr_data_count => axi_aw_wr_data_count,
axi_aw_rd_data_count => axi_aw_rd_data_count,
axi_aw_sbiterr => axi_aw_sbiterr,
axi_aw_dbiterr => axi_aw_dbiterr,
axi_aw_overflow => axi_aw_overflow,
axi_aw_underflow => axi_aw_underflow,
axi_aw_prog_full => axi_aw_prog_full,
axi_aw_prog_empty => axi_aw_prog_empty,
axi_w_injectsbiterr => '0',
axi_w_injectdbiterr => '0',
axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_w_data_count => axi_w_data_count,
axi_w_wr_data_count => axi_w_wr_data_count,
axi_w_rd_data_count => axi_w_rd_data_count,
axi_w_sbiterr => axi_w_sbiterr,
axi_w_dbiterr => axi_w_dbiterr,
axi_w_overflow => axi_w_overflow,
axi_w_underflow => axi_w_underflow,
axi_w_prog_full => axi_w_prog_full,
axi_w_prog_empty => axi_w_prog_empty,
axi_b_injectsbiterr => '0',
axi_b_injectdbiterr => '0',
axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_b_data_count => axi_b_data_count,
axi_b_wr_data_count => axi_b_wr_data_count,
axi_b_rd_data_count => axi_b_rd_data_count,
axi_b_sbiterr => axi_b_sbiterr,
axi_b_dbiterr => axi_b_dbiterr,
axi_b_overflow => axi_b_overflow,
axi_b_underflow => axi_b_underflow,
axi_b_prog_full => axi_b_prog_full,
axi_b_prog_empty => axi_b_prog_empty,
axi_ar_injectsbiterr => '0',
axi_ar_injectdbiterr => '0',
axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
axi_ar_data_count => axi_ar_data_count,
axi_ar_wr_data_count => axi_ar_wr_data_count,
axi_ar_rd_data_count => axi_ar_rd_data_count,
axi_ar_sbiterr => axi_ar_sbiterr,
axi_ar_dbiterr => axi_ar_dbiterr,
axi_ar_overflow => axi_ar_overflow,
axi_ar_underflow => axi_ar_underflow,
axi_ar_prog_full => axi_ar_prog_full,
axi_ar_prog_empty => axi_ar_prog_empty,
axi_r_injectsbiterr => '0',
axi_r_injectdbiterr => '0',
axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axi_r_data_count => axi_r_data_count,
axi_r_wr_data_count => axi_r_wr_data_count,
axi_r_rd_data_count => axi_r_rd_data_count,
axi_r_sbiterr => axi_r_sbiterr,
axi_r_dbiterr => axi_r_dbiterr,
axi_r_overflow => axi_r_overflow,
axi_r_underflow => axi_r_underflow,
axi_r_prog_full => axi_r_prog_full,
axi_r_prog_empty => axi_r_prog_empty,
axis_injectsbiterr => '0',
axis_injectdbiterr => '0',
axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
axis_data_count => axis_data_count,
axis_wr_data_count => axis_wr_data_count,
axis_rd_data_count => axis_rd_data_count,
axis_sbiterr => axis_sbiterr,
axis_dbiterr => axis_dbiterr,
axis_overflow => axis_overflow,
axis_underflow => axis_underflow,
axis_prog_full => axis_prog_full,
axis_prog_empty => axis_prog_empty
);
-- COMP_FIFO : entity fifo_generator_v12_0_5.fifo_generator_v12_0_5
-- generic map (
-- C_COMMON_CLOCK => 0,
-- C_COUNT_TYPE => 0,
-- C_DATA_COUNT_WIDTH => 10,
-- C_DEFAULT_VALUE => "BlankString",
-- C_DIN_WIDTH => 18,
-- C_DOUT_RST_VAL => "0",
-- C_DOUT_WIDTH => 18,
-- C_ENABLE_RLOCS => 0,
-- C_FAMILY => C_FAMILY,
-- C_FULL_FLAGS_RST_VAL => 1,
-- C_HAS_ALMOST_EMPTY => 0,
-- C_HAS_ALMOST_FULL => 0,
-- C_HAS_BACKUP => 0,
-- C_HAS_DATA_COUNT => 0,
-- C_HAS_INT_CLK => 0,
-- C_HAS_MEMINIT_FILE => 0,
-- C_HAS_OVERFLOW => 0,
-- C_HAS_RD_DATA_COUNT => 0,
-- C_HAS_RD_RST => 0,
-- C_HAS_RST => 1,
-- C_HAS_SRST => 0,
-- C_HAS_UNDERFLOW => 0,
-- C_HAS_VALID => 0,
-- C_HAS_WR_ACK => 0,
-- C_HAS_WR_DATA_COUNT => 0,
-- C_HAS_WR_RST => 0,
-- C_IMPLEMENTATION_TYPE => 0,
-- C_INIT_WR_PNTR_VAL => 0,
-- C_MEMORY_TYPE => 1,
-- C_MIF_FILE_NAME => "BlankString",
-- C_OPTIMIZATION_MODE => 0,
-- C_OVERFLOW_LOW => 0,
-- C_PRELOAD_LATENCY => 1,
-- C_PRELOAD_REGS => 0,
-- C_PRIM_FIFO_TYPE => "4kx4",
-- C_PROG_EMPTY_THRESH_ASSERT_VAL => 2,
-- C_PROG_EMPTY_THRESH_NEGATE_VAL => 3,
-- C_PROG_EMPTY_TYPE => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL => 1022,
-- C_PROG_FULL_THRESH_NEGATE_VAL => 1021,
-- C_PROG_FULL_TYPE => 0,
-- C_RD_DATA_COUNT_WIDTH => 10,
-- C_RD_DEPTH => 16,
-- C_RD_FREQ => 1,
-- C_RD_PNTR_WIDTH => ADDR_BITS,
-- C_UNDERFLOW_LOW => 0,
-- C_USE_DOUT_RST => 1,
-- C_USE_ECC => 0,
-- C_USE_EMBEDDED_REG => 0,
-- C_USE_PIPELINE_REG => 0,
-- C_POWER_SAVING_MODE => 0,
-- C_USE_FIFO16_FLAGS => 0,
-- C_USE_FWFT_DATA_COUNT => 0,
-- C_VALID_LOW => 0,
-- C_WR_ACK_LOW => 0,
-- C_WR_DATA_COUNT_WIDTH => 10,
-- C_WR_DEPTH => 16,
-- C_WR_FREQ => 1,
-- C_WR_PNTR_WIDTH => ADDR_BITS,
-- C_WR_RESPONSE_LATENCY => 1,
-- C_MSGON_VAL => 1,
-- C_ENABLE_RST_SYNC => 1,
-- C_ERROR_INJECTION_TYPE => 0,
-- C_SYNCHRONIZER_STAGE => 2,
-- C_INTERFACE_TYPE => 1,
-- C_AXI_TYPE => 1,
-- C_HAS_AXI_WR_CHANNEL => 1,
-- C_HAS_AXI_RD_CHANNEL => 1,
-- C_HAS_SLAVE_CE => 0,
-- C_HAS_MASTER_CE => 0,
-- C_ADD_NGC_CONSTRAINT => 0,
-- C_USE_COMMON_OVERFLOW => 0,
-- C_USE_COMMON_UNDERFLOW => 0,
-- C_USE_DEFAULT_SETTINGS => 0,
-- C_AXI_ID_WIDTH => 1,
-- C_AXI_ADDR_WIDTH => 32,
-- C_AXI_DATA_WIDTH => 64,
-- C_AXI_LEN_WIDTH => 8,
-- C_AXI_LOCK_WIDTH => 1,
-- C_HAS_AXI_ID => 0,
-- C_HAS_AXI_AWUSER => 0,
-- C_HAS_AXI_WUSER => 0,
-- C_HAS_AXI_BUSER => 0,
-- C_HAS_AXI_ARUSER => 0,
-- C_HAS_AXI_RUSER => 0,
-- C_AXI_ARUSER_WIDTH => 1,
-- C_AXI_AWUSER_WIDTH => 1,
-- C_AXI_WUSER_WIDTH => 1,
-- C_AXI_BUSER_WIDTH => 1,
-- C_AXI_RUSER_WIDTH => 1,
-- C_HAS_AXIS_TDATA => 0,
-- C_HAS_AXIS_TID => 0,
-- C_HAS_AXIS_TDEST => 0,
-- C_HAS_AXIS_TUSER => 0,
-- C_HAS_AXIS_TREADY => 1,
-- C_HAS_AXIS_TLAST => 1,
-- C_HAS_AXIS_TSTRB => 0,
-- C_HAS_AXIS_TKEEP => 0,
-- C_AXIS_TDATA_WIDTH => 1,
-- C_AXIS_TID_WIDTH => 1,
-- C_AXIS_TDEST_WIDTH => 1,
-- C_AXIS_TUSER_WIDTH => 1,
-- C_AXIS_TSTRB_WIDTH => 1,
-- C_AXIS_TKEEP_WIDTH => 1,
-- C_WACH_TYPE => 0,
-- C_WDCH_TYPE => 0,
-- C_WRCH_TYPE => 0,
-- C_RACH_TYPE => 0,
-- C_RDCH_TYPE => 0,
-- C_AXIS_TYPE => 0,
-- C_IMPLEMENTATION_TYPE_WACH => 12,
-- C_IMPLEMENTATION_TYPE_WDCH => 11,
-- C_IMPLEMENTATION_TYPE_WRCH => 12,
-- C_IMPLEMENTATION_TYPE_RACH => 12,
-- C_IMPLEMENTATION_TYPE_RDCH => 11,
-- C_IMPLEMENTATION_TYPE_AXIS => 11,
-- C_APPLICATION_TYPE_WACH => 0,
-- C_APPLICATION_TYPE_WDCH => 0,
-- C_APPLICATION_TYPE_WRCH => 0,
-- C_APPLICATION_TYPE_RACH => 0,
-- C_APPLICATION_TYPE_RDCH => 0,
-- C_APPLICATION_TYPE_AXIS => 1,
-- C_PRIM_FIFO_TYPE_WACH => "512x36",
-- C_PRIM_FIFO_TYPE_WDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_WRCH => "512x36",
-- C_PRIM_FIFO_TYPE_RACH => "512x36",
-- C_PRIM_FIFO_TYPE_RDCH => "1kx36",
-- C_PRIM_FIFO_TYPE_AXIS => "512x36",
-- C_USE_ECC_WACH => 0,
-- C_USE_ECC_WDCH => 0,
-- C_USE_ECC_WRCH => 0,
-- C_USE_ECC_RACH => 0,
-- C_USE_ECC_RDCH => 0,
-- C_USE_ECC_AXIS => 0,
-- C_ERROR_INJECTION_TYPE_WACH => 0,
-- C_ERROR_INJECTION_TYPE_WDCH => 0,
-- C_ERROR_INJECTION_TYPE_WRCH => 0,
-- C_ERROR_INJECTION_TYPE_RACH => 0,
-- C_ERROR_INJECTION_TYPE_RDCH => 0,
-- C_ERROR_INJECTION_TYPE_AXIS => 0,
-- C_DIN_WIDTH_WACH => 32,
-- C_DIN_WIDTH_WDCH => 64,
-- C_DIN_WIDTH_WRCH => 2,
-- C_DIN_WIDTH_RACH => 32,
-- C_DIN_WIDTH_RDCH => 64,
-- C_DIN_WIDTH_AXIS => 1,
-- C_WR_DEPTH_WACH => 16,
-- C_WR_DEPTH_WDCH => 1024,
-- C_WR_DEPTH_WRCH => 16,
-- C_WR_DEPTH_RACH => 16,
-- C_WR_DEPTH_RDCH => 1024,
-- C_WR_DEPTH_AXIS => 16,
-- C_WR_PNTR_WIDTH_WACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_WDCH => 10,
-- C_WR_PNTR_WIDTH_WRCH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RACH => ADDR_BITS,
-- C_WR_PNTR_WIDTH_RDCH => 10,
-- C_WR_PNTR_WIDTH_AXIS => ADDR_BITS,
-- C_HAS_DATA_COUNTS_WACH => 0,
-- C_HAS_DATA_COUNTS_WDCH => 0,
-- C_HAS_DATA_COUNTS_WRCH => 0,
-- C_HAS_DATA_COUNTS_RACH => 0,
-- C_HAS_DATA_COUNTS_RDCH => 0,
-- C_HAS_DATA_COUNTS_AXIS => 3,
-- C_HAS_PROG_FLAGS_WACH => 0,
-- C_HAS_PROG_FLAGS_WDCH => 0,
-- C_HAS_PROG_FLAGS_WRCH => 0,
-- C_HAS_PROG_FLAGS_RACH => 0,
-- C_HAS_PROG_FLAGS_RDCH => 0,
-- C_HAS_PROG_FLAGS_AXIS => 0,
-- C_PROG_FULL_TYPE_WACH => 0,
-- C_PROG_FULL_TYPE_WDCH => 0,
-- C_PROG_FULL_TYPE_WRCH => 0,
-- C_PROG_FULL_TYPE_RACH => 0,
-- C_PROG_FULL_TYPE_RDCH => 0,
-- C_PROG_FULL_TYPE_AXIS => 0,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 15,
-- C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
-- C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 15,
-- C_PROG_EMPTY_TYPE_WACH => 0,
-- C_PROG_EMPTY_TYPE_WDCH => 0,
-- C_PROG_EMPTY_TYPE_WRCH => 0,
-- C_PROG_EMPTY_TYPE_RACH => 0,
-- C_PROG_EMPTY_TYPE_RDCH => 0,
-- C_PROG_EMPTY_TYPE_AXIS => 0,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 13,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1021,
-- C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 13,
-- C_REG_SLICE_MODE_WACH => 0,
-- C_REG_SLICE_MODE_WDCH => 0,
-- C_REG_SLICE_MODE_WRCH => 0,
-- C_REG_SLICE_MODE_RACH => 0,
-- C_REG_SLICE_MODE_RDCH => 0,
-- C_REG_SLICE_MODE_AXIS => 0
-- )
-- PORT MAP (
-- backup => '0',
-- backup_marker => '0',
-- clk => '0',
-- rst => '0',
-- srst => '0',
-- wr_clk => '0',
-- wr_rst => '0',
-- rd_clk => '0',
-- rd_rst => '0',
-- din => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 18)),
-- wr_en => '0',
-- rd_en => '0',
-- prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- int_clk => '0',
-- injectdbiterr => '0',
-- injectsbiterr => '0',
-- sleep => '0',
-- m_aclk => rd_clk,
-- s_aclk => wr_clk,
-- s_aresetn => rstn,
-- m_aclk_en => '0',
-- s_aclk_en => '0',
-- s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_awvalid => '0',
-- s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_wlast => '0',
-- s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_wvalid => '0',
-- s_axi_bready => '0',
-- m_axi_awready => '0',
-- m_axi_wready => '0',
-- m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_bvalid => '0',
-- s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
-- s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
-- s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
-- s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
-- s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axi_arvalid => '0',
-- s_axi_rready => '0',
-- m_axi_arready => '0',
-- m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
-- m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
-- m_axi_rlast => '0',
-- m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axi_rvalid => '0',
-- s_axis_tvalid => din_vld,
-- s_axis_tready => open,
-- s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- --s_axis_tdata => din,
-- s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tlast => '1',
-- s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
-- m_axis_tvalid => open,
-- m_axis_tready => m_axis_tready,
-- m_axis_tlast => m_axis_tlast,
-- axi_aw_injectsbiterr => '0',
-- axi_aw_injectdbiterr => '0',
-- axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_w_injectsbiterr => '0',
-- axi_w_injectdbiterr => '0',
-- axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_b_injectsbiterr => '0',
-- axi_b_injectdbiterr => '0',
-- axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0,ADDR_BITS)),
-- axi_ar_injectsbiterr => '0',
-- axi_ar_injectdbiterr => '0',
-- axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axi_r_injectsbiterr => '0',
-- axi_r_injectdbiterr => '0',
-- axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
-- axis_injectsbiterr => '0',
-- axis_injectdbiterr => '0',
-- axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, ADDR_BITS)),
-- axis_wr_data_count => rd_used_i,
-- axis_rd_data_count => open
-- );
end generate NEW_INTRO3;
end rtl;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_counter is
end entity tb_counter;
----------------------------------------------------------------
architecture test_behavior of tb_counter is
signal clk, reset : bit := '0';
signal count : natural;
begin
dut : entity work.counter(behavior)
port map ( clk => clk, reset => reset, count => count );
stimulus : process is
begin
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '1' after 15 ns;
for cycle_count in 1 to 5 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
reset <= '0' after 15 ns;
for cycle_count in 1 to 30 loop
wait for 20 ns;
clk <= '1', '0' after 10 ns;
end loop;
wait;
end process stimulus;
end architecture test_behavior;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- S O C B R I D G E T E S T B E N C H (soc_bridge_tb.vhd)
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.constants.all;
use work.interfaces.all;
-------------------------------------------------------------------------------
ENTITY soc_bridge_tb is
-------------------------------------------------------------------------------
begin
end soc_bridge_tb;
-------------------------------------------------------------------------------
ARCHITECTURE simulation of soc_bridge_tb is
-------------------------------------------------------------------------------
-- constants
constant CLK_PERIOD : time := 25 ns;
constant DATA_OUT_MAX : integer := 300;
constant WBS1_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"01";
constant WBS2_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"02";
constant WBS3_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"03";
constant WBS8_ADR : std_logic_vector(WB_CORE_AW-1 downto 0) := x"08"; -- alias for WBS3
-- signals
signal fpga_active_i : std_logic;
signal mcu_active_o : std_logic;
signal fifo_data_io : std_logic_vector(7 downto 0);
signal fifo_rxf_n_i : std_logic;
signal fifo_txe_n_i : std_logic;
signal fifo_rd_n_o : std_logic;
signal fifo_wr_o : std_logic;
signal clk_s : std_logic;
signal wbm_out_s : wbm_out_type;
signal wbm_in_s : wbm_in_type;
-- wishbone slaves
signal wbs1_in_s : wbs_in_type;
signal wbs1_out_s : wbs_out_type;
signal wbs1_reg1_out_s: std_logic_vector(7 downto 0);
signal wbs1_reg2_out_s: std_logic_vector(7 downto 0);
signal wbs2_in_s : wbs_in_type;
signal wbs2_out_s : wbs_out_type;
signal wbs2_reg1_out_s: std_logic_vector(7 downto 0);
signal wbs2_reg2_out_s: std_logic_vector(7 downto 0);
signal wbs3_in_s : wbs_in_type;
signal wbs3_out_s : wbs_out_type;
-- intercon signals
signal core_adr_s : std_logic_vector(WB_CORE_AW-1 downto 0);
signal reg_adr_s : std_logic_vector(WB_REG_AW-1 downto 0);
signal adr_match_1_s : std_logic;
signal adr_match_2_s : std_logic;
signal adr_match_3_s : std_logic;
signal wishbone_rst_s : std_logic;
-- data output array (stores all bytes sent back by the soc bridge)
type data_out_t is array (0 to DATA_OUT_MAX) of std_logic_vector(7 downto 0);
signal data_out_s : data_out_t;
signal data_out_cnt_s : integer range 0 to DATA_OUT_MAX;
-------------------------------------------------
procedure send_to_fifo (
-------------------------------------------------
constant data : in unsigned;
signal data_io : out std_logic_vector(7 downto 0);
signal rxf_n_i : out std_logic;
signal rd_n_o : in std_logic
) is
begin
-- assert rxf and wait until rd was asserted
rxf_n_i <= '0';
wait until rd_n_o = '0';
wait for 50 ns; -- T3: 20..50 ns
-- apply data
data_io <= std_logic_vector(data);
-- wait until dut closes transfer
wait until rd_n_o = '1';
wait for 25 ns; -- T5: 0..25 ns
rxf_n_i <= '1';
-- hiZ data lines
data_io <= (others => 'Z');
wait for 80 ns; -- T6: >80 ns
end procedure send_to_fifo;
begin -- architecture simulation
------------------------------------------------------
DATA_OUT : process(clk_s, fifo_wr_o, fifo_data_io)
------------------------------------------------------
variable data_out_cnt : integer range 0 to DATA_OUT_MAX := 0;
begin
if (falling_edge(fifo_wr_o)) then
data_out_s(data_out_cnt) <= fifo_data_io;
data_out_cnt := data_out_cnt + 1;
data_out_cnt_s <= data_out_cnt;
end if;
end process DATA_OUT;
-------------------------------------------------
STIMULI_PROC :
-------------------------------------------------
process begin
------------------------------------
-- init
------------------------------------
wishbone_rst_s <= '1';
fpga_active_i <= '0';
fifo_rxf_n_i <= '1';
fifo_txe_n_i <= '0';
fifo_data_io <= (others => '-');
wait for 100 ns;
wishbone_rst_s <= '0';
wait for CLK_PERIOD*10;
------------------------------------
-- test fpga activation
------------------------------------
assert false
report "Will now activate fpga"
severity note;
fpga_active_i <= '1';
wait for CLK_PERIOD*2;
assert (mcu_active_o = '0')
report "enable_ctrl error"
severity error;
--------------------------------------------------------
-- test reaction on status read (actually for the MCU)
--------------------------------------------------------
assert false
report "Will now test reaction on status read"
severity note;
send_to_fifo(x"c3",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o);
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- nack
data_out_s(data_out_cnt_s - 3) = x"00" and -- id
data_out_s(data_out_cnt_s - 2) = x"11" and -- error code
data_out_s(data_out_cnt_s - 1) = x"00") -- parity
report "Invalid answer to status read"
severity error;
--------------------------------------------------------
-- test detect function
--------------------------------------------------------
assert false
report "Will now send DETECT"
severity note;
send_to_fifo(x"EE",fifo_data_io,fifo_rxf_n_i, fifo_rd_n_o);
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"FF" and -- detect reply opcode
data_out_s(data_out_cnt_s - 2) = x"EF" and -- fpga identifier
data_out_s(data_out_cnt_s - 1) = x"10") -- parity
report "Wrong reply to detect frame"
severity error;
------------------------------------
-- send register wr command
------------------------------------
assert false
report "Will now send REGISTER_WR"
severity note;
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1D",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"53",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data
send_to_fifo(x"29",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"53")
report "REGISTER_WR failed!"
severity error;
--------------------------------------------------
-- send register wr command to non-existent core
--------------------------------------------------
assert false
report "Will now send REGISTER_WR to non-existent core"
severity note;
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"1F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- nack
data_out_s(data_out_cnt_s - 3) = x"1F" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"3D") -- parity
report "Read back value differs from last write"
severity error;
------------------------------------
-- send register wr command (wrong parity)
------------------------------------
assert false
report "Will now send REGISTER_WR with wrong parity"
severity note;
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"53" and -- last write
data_out_s(data_out_cnt_s - 1) = x"FB") -- parity
report "Register WR with wrong parity changed register"
severity error;
------------------------------------
-- send register rd command (wrong parity)
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity (wrong)
wait for 10 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"21" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"12") -- parity
report "Unexpected reply to register RD with wrong parity"
severity error;
------------------------------------
-- send register mwr command
------------------------------------
assert false
report "Will now send REGISTER_MWR"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"1F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"BA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"BA" and -- last write
data_out_s(data_out_cnt_s - 1) = x"12") -- parity
report "Read back value differs from last write"
severity error;
-------------------------------------------------------------
-- send register mwr command that requires partial reception
-------------------------------------------------------------
assert false
report "Will now send a long REGISTER_MWR (14 data bytes)"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"0E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"BB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data11
send_to_fifo(x"CC",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data12
send_to_fifo(x"DD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data13
send_to_fifo(x"7b",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"DD" and -- last write
data_out_s(data_out_cnt_s - 1) = x"75") -- parity
report "Read back value differs from last write"
severity error;
-------------------------------------------------------------
-- send register mwr command that failed on harware
-------------------------------------------------------------
assert false
report "Will now send a long REGISTER_MWR (11 data bytes)"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"0E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"0B",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"30",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"41" and -- last write
data_out_s(data_out_cnt_s - 1) = x"E9") -- parity
report "Read back value differs from last write"
severity error;
--------------------------------------------------------------------
-- send register mwr command that requires more partial receptions
--------------------------------------------------------------------
assert false
report "Will now send a 64 byte long REGISTER_MWR"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"0e",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"40",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0 - sequence begin 0
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data11
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data12
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data13
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data14
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data15 - sequence begin 1
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data16
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data17
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data18
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data19
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data20
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data21
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data22
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data23
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data24
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data25
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data26
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data27
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data28
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data29
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data30 - sequence begin 2
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data31
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data32
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data33
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data34
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data35
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data36
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data37
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data38
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data39
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data40
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data41
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data42
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data43
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data44
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data45 - sequence begin 3
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data46
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data47
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data48
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data49
send_to_fifo(x"36",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data50
send_to_fifo(x"37",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data51
send_to_fifo(x"38",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data52
send_to_fifo(x"39",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data53
send_to_fifo(x"41",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data54
send_to_fifo(x"42",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data55
send_to_fifo(x"43",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data56
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data57
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data58
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data59 - sequence begin 4
send_to_fifo(x"31",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data60
send_to_fifo(x"32",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data61
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data62
send_to_fifo(x"34",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data63
send_to_fifo(x"2E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"34")
report "REGISTER_MWR failed!"
severity error;
------------------------------------
-- send register rd command
------------------------------------
assert false
report "Will now send REGISTER_RD"
severity note;
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"20",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"88" and -- rdre opcode
data_out_s(data_out_cnt_s - 3) = x"20" and -- id
data_out_s(data_out_cnt_s - 2) = x"34" and -- last write
data_out_s(data_out_cnt_s - 1) = x"9C") -- parity
report "Read back value differs from last write"
severity error;
--------------------------------------------------------------------
-- send very short register mwr command
--------------------------------------------------------------------
assert false
report "Will now send a very short REGISTER_MWR"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"23",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"46",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"23")
report "REGISTER_MWR failed!"
severity error;
-------------------------------------
-- send register mwr with length 0
-------------------------------------
assert false
report "Will now send REGISTER_MWR with length 0"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"45",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"23")
report "REGISTER_MWR with length 0 changed register content"
severity error;
--------------------------------------------------------------------
-- send very short register mwr command with wrong parity
--------------------------------------------------------------------
assert false
report "Will now send a very short REGISTER_MWR with wrong parity"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"19",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"FC",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"19" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"2A") -- parity
report "Did not reply NACK after REGISTER_MWR with wrong parity"
severity error;
-- this warning will be thrown since not all request data is known while
-- already writing to registers. Parity check is performed afterwards.
assert (wbs1_reg1_out_s = x"23")
report "REGISTER_MWR with wrong parity affected register"
severity warning;
-----------------------------------------------------------
-- send register mwr to non-existent core
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MWR to non-existent core"
severity note;
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"56",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"09",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"90",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"05",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"AF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"56" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"74") -- parity
report "Did not reply NACK after trying to access non-existent core"
severity error;
------------------------------------
-- send register awr command
------------------------------------
assert false
report "Will now send REGISTER_AWR"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"C3",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert ((wbs1_reg1_out_s = x"AB") and (wbs1_reg2_out_s = x"CD"))
report "Register AWR failed"
severity error;
------------------------------------------------
-- send register awr command with wrong parity
------------------------------------------------
assert false
report "Will now send REGISTER_AWR with wrong parity"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"22" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"11") -- parity
report "Did not reply NACK after REGISTER_AWR with wrong parity"
severity error;
------------------------------------------------------
-- send register awr that failed in integration test
------------------------------------------------------
assert false
report "Will now send REGISTER_AWR with length 4"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"08",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"14",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"04",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"87",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"E6",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"00" and -- ACK opcode
data_out_s(data_out_cnt_s - 2) = x"EF" and -- id
data_out_s(data_out_cnt_s - 1) = x"EF") -- parity
report "Did not reply ACK after REGISTER_AWR with length 4"
severity error;
-------------------------------------
-- send register awr with length 0
-------------------------------------
assert false
report "Will now send REGISTER_AWR with length 0"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"49",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert ((wbs1_reg1_out_s = x"AB") and (wbs1_reg2_out_s = x"CD"))
report "Register AWR with length 0 changed register content"
severity error;
-----------------------------------------------------------
-- send register awr that exceeds register address range
-----------------------------------------------------------
assert false
report "Will now send REGISTER_AWR that exceeds register address range - test wrap-around"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"21",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"FE",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"3F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (wbs1_reg1_out_s = x"EF")
report "Register AWR wrap-around failed"
severity error;
-----------------------------------------------------------
-- send register awr to non-existent core
-----------------------------------------------------------
assert false
report "Will now send REGISTER_AWR to non-existent core"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"F0",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"F0",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"AB",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"CD",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"EF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"C1",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"22" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"00") -- parity
report "Did not reply NACK after trying to access non-existent core"
severity error;
-----------------------------------------------------------
-- load 256-register core with data using awr
-----------------------------------------------------------
assert false
report "Will now load data to 256 register core"
severity note;
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"69",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data0
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data1
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data2
send_to_fifo(x"11",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data3
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data4
send_to_fifo(x"22",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data5
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data6
send_to_fifo(x"33",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data7
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data8
send_to_fifo(x"44",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data9
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data10
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data11
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data12
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data13
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data14
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data15
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data16
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data17
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data18
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data19
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data20
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data21
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data22
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data23
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data24
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data25
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data26
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data27
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data28
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data29
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data30
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data31
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data32
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data33
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data34
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data35
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data36
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data37
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data38
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data39
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data40
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data41
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data42
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data43
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data44
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data45
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data46
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data47
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data48
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data49
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data50
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data51
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data52
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data53
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data54
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data55
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data56
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data57
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data58
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data59
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data60
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data61
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data62
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data63
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data64
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data65
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data66
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data67
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data68
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data69
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data70
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data71
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data72
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data73
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data74
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data75
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data76
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data77
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data78
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data79
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data80
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data81
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data82
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data83
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data84
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data85
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data86
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data87
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data88
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data89
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data90
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data91
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data92
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data93
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data94
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data95
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data96
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data97
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data98
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data99
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data100
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data101
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data102
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data103
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data104
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data105
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data106
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data107
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data108
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data109
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data110
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data111
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data112
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data113
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data114
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data115
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data116
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data117
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data118
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data119
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data120
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data121
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data122
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data123
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data124
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data125
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data126
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data127
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data128
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data129
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data130
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data131
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data132
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data133
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data134
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data135
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data136
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data137
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data138
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data139
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data140
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data141
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data142
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data143
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data144
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data145
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data146
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data147
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data148
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data149
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data150
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data151
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data152
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data153
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data154
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data155
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data156
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data157
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data158
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data159
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data160
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data161
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data162
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data163
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data164
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data165
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data166
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data167
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data168
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data169
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data170
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data171
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data172
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data173
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data174
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data175
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data176
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data177
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data178
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data179
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data180
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data181
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data182
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data183
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data184
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data185
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data186
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data187
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data188
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data189
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data190
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data191
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data192
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data193
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data194
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data195
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data196
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data197
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data198
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data199
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data200
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data201
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data202
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data203
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data204
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data205
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data206
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data207
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data208
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data209
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data210
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data211
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data212
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data213
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data214
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data215
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data216
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data217
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data218
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data219
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data220
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data221
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data222
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data223
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data224
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data225
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data226
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data227
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data228
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data229
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data230
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data231
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data232
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data233
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data234
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data235
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data236
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data237
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data238
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data239
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data240
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data241
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data242
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data243
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data244
send_to_fifo(x"77",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data245
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data246
send_to_fifo(x"88",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data247
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data248
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data249
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data250
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data251
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data252
send_to_fifo(x"66",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data253
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- data254
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"00" and -- ACK opcode
data_out_s(data_out_cnt_s - 2) = x"69" and -- id
data_out_s(data_out_cnt_s - 1) = x"69") -- parity
report "Did not reply ACK after 256-byte AWR"
severity error;
-----------------------------------------------------------
-- send register ard to read two bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with length 2"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"23",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"02",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"59",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 10 us;
assert( data_out_s(data_out_cnt_s - 5) = x"90" and -- ARDRE opcode
data_out_s(data_out_cnt_s - 4) = x"23" and -- id
data_out_s(data_out_cnt_s - 3) = x"EF" and -- data0
data_out_s(data_out_cnt_s - 2) = x"CD" and -- data1
data_out_s(data_out_cnt_s - 1) = x"91") -- parity
report "Reading 2 bytes using ARD failed"
severity error;
-----------------------------------------------------------
-- send register ard to non-existent core
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD to non-existent core"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"24",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"02",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"5F",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"24" and -- id
data_out_s(data_out_cnt_s - 2) = x"33" and -- error code
data_out_s(data_out_cnt_s - 1) = x"06") -- parity
report "Did not reply NACK after trying to access (ARD) non-existent core"
severity error;
-----------------------------------------------------------
-- send register ard to with wrong parity
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with wrong parity"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"25",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"FF",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"12",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"12",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"25" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"16") -- parity
report "Did not reply NACK after REGISTER_ARD with wrong parity"
severity error;
-----------------------------------------------------------
-- send register ard with length 0
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with length 0"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"35",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"01",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length
send_to_fifo(x"4D",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"90" and -- ARDRE opcode
data_out_s(data_out_cnt_s - 2) = x"35" and -- id
data_out_s(data_out_cnt_s - 1) = x"A5") -- parity
report "Unexpected answer to ARD with length 0"
severity error;
-----------------------------------------------------------
-- send register ard to read 100 bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_ARD with length 100"
severity note;
send_to_fifo(x"79",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"25",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"64",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 100
send_to_fifo(x"3b",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 50 us;
assert( data_out_s(data_out_cnt_s - 103) = x"90" and -- ARDRE opcode
data_out_s(data_out_cnt_s - 102) = x"25" and -- id
data_out_s(data_out_cnt_s - 101) = x"FF" and -- data0
data_out_s(data_out_cnt_s - 100) = x"03" and -- data1
data_out_s(data_out_cnt_s - 99) = x"11" and -- data2
data_out_s(data_out_cnt_s - 98) = x"11" and -- data3
data_out_s(data_out_cnt_s - 97) = x"22" and -- data4
data_out_s(data_out_cnt_s - 96) = x"22" and -- data5
data_out_s(data_out_cnt_s - 95) = x"33" and -- data6
data_out_s(data_out_cnt_s - 94) = x"33" and -- data7
data_out_s(data_out_cnt_s - 93) = x"44" and -- data8
data_out_s(data_out_cnt_s - 92) = x"44" and -- data9
data_out_s(data_out_cnt_s - 91) = x"55" and -- data10
data_out_s(data_out_cnt_s - 90) = x"55" and -- data11
data_out_s(data_out_cnt_s - 89) = x"66" and -- data12
data_out_s(data_out_cnt_s - 88) = x"66" and -- data13
data_out_s(data_out_cnt_s - 87) = x"77" and -- data14
data_out_s(data_out_cnt_s - 86) = x"77" and -- data15
data_out_s(data_out_cnt_s - 85) = x"88" and -- data16
data_out_s(data_out_cnt_s - 84) = x"88" and -- data17
data_out_s(data_out_cnt_s - 83) = x"99" and -- data18
data_out_s(data_out_cnt_s - 82) = x"99" and -- data19
data_out_s(data_out_cnt_s - 81) = x"55" and -- data20
data_out_s(data_out_cnt_s - 80) = x"55" and -- data21
data_out_s(data_out_cnt_s - 79) = x"66" and -- data22
data_out_s(data_out_cnt_s - 78) = x"66" and -- data23
data_out_s(data_out_cnt_s - 77) = x"77" and -- data24
data_out_s(data_out_cnt_s - 76) = x"77" and -- data25
data_out_s(data_out_cnt_s - 75) = x"88" and -- data26
data_out_s(data_out_cnt_s - 74) = x"88" and -- data27
data_out_s(data_out_cnt_s - 73) = x"99" and -- data28
data_out_s(data_out_cnt_s - 72) = x"99" and -- data29
data_out_s(data_out_cnt_s - 71) = x"55" and -- data30
data_out_s(data_out_cnt_s - 70) = x"55" and -- data31
data_out_s(data_out_cnt_s - 69) = x"66" and -- data32
data_out_s(data_out_cnt_s - 68) = x"66" and -- data33
data_out_s(data_out_cnt_s - 67) = x"77" and -- data34
data_out_s(data_out_cnt_s - 66) = x"77" and -- data35
data_out_s(data_out_cnt_s - 65) = x"88" and -- data36
data_out_s(data_out_cnt_s - 64) = x"88" and -- data37
data_out_s(data_out_cnt_s - 63) = x"99" and -- data38
data_out_s(data_out_cnt_s - 62) = x"99" and -- data39
data_out_s(data_out_cnt_s - 61) = x"55" and -- data40
data_out_s(data_out_cnt_s - 60) = x"55" and -- data41
data_out_s(data_out_cnt_s - 59) = x"66" and -- data42
data_out_s(data_out_cnt_s - 58) = x"66" and -- data43
data_out_s(data_out_cnt_s - 57) = x"77" and -- data44
data_out_s(data_out_cnt_s - 56) = x"77" and -- data45
data_out_s(data_out_cnt_s - 55) = x"88" and -- data46
data_out_s(data_out_cnt_s - 54) = x"88" and -- data47
data_out_s(data_out_cnt_s - 53) = x"99" and -- data48
data_out_s(data_out_cnt_s - 52) = x"99" and -- data49
data_out_s(data_out_cnt_s - 51) = x"55" and -- data50
data_out_s(data_out_cnt_s - 50) = x"55" and -- data51
data_out_s(data_out_cnt_s - 49) = x"66" and -- data52
data_out_s(data_out_cnt_s - 48) = x"66" and -- data53
data_out_s(data_out_cnt_s - 47) = x"77" and -- data54
data_out_s(data_out_cnt_s - 46) = x"77" and -- data55
data_out_s(data_out_cnt_s - 45) = x"88" and -- data56
data_out_s(data_out_cnt_s - 44) = x"88" and -- data57
data_out_s(data_out_cnt_s - 43) = x"99" and -- data58
data_out_s(data_out_cnt_s - 42) = x"99" and -- data59
data_out_s(data_out_cnt_s - 41) = x"55" and -- data60
data_out_s(data_out_cnt_s - 40) = x"55" and -- data61
data_out_s(data_out_cnt_s - 39) = x"66" and -- data62
data_out_s(data_out_cnt_s - 38) = x"66" and -- data63
data_out_s(data_out_cnt_s - 37) = x"77" and -- data64
data_out_s(data_out_cnt_s - 36) = x"77" and -- data65
data_out_s(data_out_cnt_s - 35) = x"88" and -- data66
data_out_s(data_out_cnt_s - 34) = x"88" and -- data67
data_out_s(data_out_cnt_s - 33) = x"99" and -- data68
data_out_s(data_out_cnt_s - 32) = x"99" and -- data69
data_out_s(data_out_cnt_s - 31) = x"55" and -- data70
data_out_s(data_out_cnt_s - 30) = x"55" and -- data71
data_out_s(data_out_cnt_s - 29) = x"66" and -- data72
data_out_s(data_out_cnt_s - 28) = x"66" and -- data73
data_out_s(data_out_cnt_s - 27) = x"77" and -- data74
data_out_s(data_out_cnt_s - 26) = x"77" and -- data75
data_out_s(data_out_cnt_s - 25) = x"88" and -- data76
data_out_s(data_out_cnt_s - 24) = x"88" and -- data77
data_out_s(data_out_cnt_s - 23) = x"99" and -- data78
data_out_s(data_out_cnt_s - 22) = x"99" and -- data79
data_out_s(data_out_cnt_s - 21) = x"55" and -- data80
data_out_s(data_out_cnt_s - 20) = x"55" and -- data81
data_out_s(data_out_cnt_s - 19) = x"66" and -- data82
data_out_s(data_out_cnt_s - 18) = x"66" and -- data83
data_out_s(data_out_cnt_s - 17) = x"77" and -- data84
data_out_s(data_out_cnt_s - 16) = x"77" and -- data85
data_out_s(data_out_cnt_s - 15) = x"88" and -- data86
data_out_s(data_out_cnt_s - 14) = x"88" and -- data87
data_out_s(data_out_cnt_s - 13) = x"99" and -- data88
data_out_s(data_out_cnt_s - 12) = x"99" and -- data89
data_out_s(data_out_cnt_s - 11) = x"55" and -- data90
data_out_s(data_out_cnt_s - 10) = x"55" and -- data91
data_out_s(data_out_cnt_s - 9) = x"66" and -- data92
data_out_s(data_out_cnt_s - 8) = x"66" and -- data93
data_out_s(data_out_cnt_s - 7) = x"77" and -- data94
data_out_s(data_out_cnt_s - 6) = x"77" and -- data95
data_out_s(data_out_cnt_s - 5) = x"88" and -- data96
data_out_s(data_out_cnt_s - 4) = x"88" and -- data97
data_out_s(data_out_cnt_s - 3) = x"99" and -- data98
data_out_s(data_out_cnt_s - 2) = x"99" and -- data99
data_out_s(data_out_cnt_s - 1) = x"49" ) -- parity
report "Reading 100 bytes using ARD failed"
severity error;
-----------------------------------------------------------
-- send register mrd to read 3 bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MRD with length 3"
severity note;
send_to_fifo(x"73",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"26",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 3
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 6) = x"93" and -- MRDRE opcode
data_out_s(data_out_cnt_s - 5) = x"26" and -- id
data_out_s(data_out_cnt_s - 4) = x"FF" and -- data0
data_out_s(data_out_cnt_s - 3) = x"FF" and -- data1
data_out_s(data_out_cnt_s - 2) = x"FF" and -- data2
data_out_s(data_out_cnt_s - 1) = x"4A") -- parity
report "Unexpected answer to MRD with length 3"
severity error;
-----------------------------------------------------------
-- send register mrd to read 30 bytes
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MRD with length 30"
severity note;
send_to_fifo(x"73",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"26",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"1E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 30
send_to_fifo(x"4B",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 20 us;
assert( data_out_s(data_out_cnt_s - 33) = x"93" and -- MRDRE opcode
data_out_s(data_out_cnt_s - 32) = x"26" and -- id
data_out_s(data_out_cnt_s - 31) = x"11" and -- data0
data_out_s(data_out_cnt_s - 30) = x"11" and -- data1
data_out_s(data_out_cnt_s - 29) = x"11" and -- data2
data_out_s(data_out_cnt_s - 28) = x"11" and -- data3
data_out_s(data_out_cnt_s - 27) = x"11" and -- data4
data_out_s(data_out_cnt_s - 26) = x"11" and -- data5
data_out_s(data_out_cnt_s - 25) = x"11" and -- data6
data_out_s(data_out_cnt_s - 24) = x"11" and -- data7
data_out_s(data_out_cnt_s - 23) = x"11" and -- data8
data_out_s(data_out_cnt_s - 22) = x"11" and -- data9
data_out_s(data_out_cnt_s - 21) = x"11" and -- data10
data_out_s(data_out_cnt_s - 20) = x"11" and -- data11
data_out_s(data_out_cnt_s - 19) = x"11" and -- data12
data_out_s(data_out_cnt_s - 18) = x"11" and -- data12
data_out_s(data_out_cnt_s - 17) = x"11" and -- data13
data_out_s(data_out_cnt_s - 16) = x"11" and -- data15
data_out_s(data_out_cnt_s - 15) = x"11" and -- data16
data_out_s(data_out_cnt_s - 14) = x"11" and -- data17
data_out_s(data_out_cnt_s - 13) = x"11" and -- data18
data_out_s(data_out_cnt_s - 12) = x"11" and -- data19
data_out_s(data_out_cnt_s - 11) = x"11" and -- data20
data_out_s(data_out_cnt_s - 10) = x"11" and -- data21
data_out_s(data_out_cnt_s - 9) = x"11" and -- data22
data_out_s(data_out_cnt_s - 8) = x"11" and -- data23
data_out_s(data_out_cnt_s - 7) = x"11" and -- data24
data_out_s(data_out_cnt_s - 6) = x"11" and -- data25
data_out_s(data_out_cnt_s - 5) = x"11" and -- data26
data_out_s(data_out_cnt_s - 4) = x"11" and -- data27
data_out_s(data_out_cnt_s - 3) = x"11" and -- data28
data_out_s(data_out_cnt_s - 2) = x"11" and -- data29
data_out_s(data_out_cnt_s - 1) = x"B5") -- parity
report "Unexpected answer to MRD with length 30"
severity error;
-----------------------------------------------------------
-- send register mrd with wrong parity
-----------------------------------------------------------
assert false
report "Will now send REGISTER_MRD with wrong parity"
severity note;
send_to_fifo(x"73",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"99",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- core address
send_to_fifo(x"03",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- register address
send_to_fifo(x"1E",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- length = 30
send_to_fifo(x"4B",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"99" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"AA") -- parity
report "Did not reply NACK after REGISTER_MRD with wrong parity"
severity error;
------------------------------------
-- enable interrupts (wrong parity)
------------------------------------
assert false
report "Will now send INT_EN (wrong parity)"
severity note;
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"27",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- wrong parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"27" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"14") -- parity
report "Did not reply NACK after INT_EN with wrong parity"
severity error;
------------------------------------
-- enable interrupts
------------------------------------
assert false
report "Will now send INT_EN"
severity note;
send_to_fifo(x"AA",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"28",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"82",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 3) = x"00" and -- NACK opcode
data_out_s(data_out_cnt_s - 2) = x"28" and -- id
data_out_s(data_out_cnt_s - 1) = x"28") -- parity
report "Did not reply ACK after INT_EN"
severity error;
------------------------------------
-- send MCU_SEL (wrong parity)
------------------------------------
assert false
report "Will now send MCU_SEL with wrong parity"
severity note;
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"29",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"00",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- wrong parity
wait for 5 us;
assert( data_out_s(data_out_cnt_s - 4) = x"11" and -- NACK opcode
data_out_s(data_out_cnt_s - 3) = x"29" and -- id
data_out_s(data_out_cnt_s - 2) = x"22" and -- error code
data_out_s(data_out_cnt_s - 1) = x"1A") -- parity
report "Did not reply NACK after MCU_SEL with wrong parity"
severity error;
assert (mcu_active_o = '0')
report "Wrong parity MCU_SEL caused switching to MCU"
severity error;
------------------------------------
-- test switching back to mcu
------------------------------------
assert false
report "Will now send MCU_SEL"
severity note;
send_to_fifo(x"55",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- opcode
send_to_fifo(x"30",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- id
send_to_fifo(x"65",fifo_data_io,fifo_rxf_n_i,fifo_rd_n_o); -- parity
wait for 5 us;
assert (mcu_active_o = '1')
report "Switching back to MCU failed!"
severity error;
if (mcu_active_o = '1') then
fpga_active_i <= '0';
end if;
-- terminate simulation the hard way
assert false report "SIMULATION FINISHED" severity failure;
end process STIMULI_PROC;
-------------------------------------------------
-- UUT instantiation
-------------------------------------------------
UUT : entity work.soc_bridge
port map (
fpga_active_i => fpga_active_i,
mcu_active_o => mcu_active_o,
fifo_data_io => fifo_data_io,
fifo_rxf_n_i => fifo_rxf_n_i,
fifo_txe_n_i => fifo_txe_n_i,
fifo_rd_n_o => fifo_rd_n_o,
fifo_wr_o => fifo_wr_o,
wbm_i => wbm_in_s,
wbm_o => wbm_out_s
);
-- two pwm16 cores as slaves
WBS1 : entity work.wbs_dual_out
port map (
wbs_in => wbs1_in_s,
wbs_out => wbs1_out_s,
reg1_out => wbs1_reg1_out_s,
reg2_out => wbs1_reg2_out_s
);
WBS2 : entity work.wbs_dual_out
port map (
wbs_in => wbs2_in_s,
wbs_out => wbs2_out_s,
reg1_out => wbs2_reg1_out_s,
reg2_out => wbs2_reg2_out_s
);
WBS3 : entity work.wbs256
port map (
wbs_in => wbs3_in_s,
wbs_out => wbs3_out_s
);
---------------
-- Intercon
---------------
-- split address
reg_adr_s <= wbm_out_s.adr(WB_REG_AW-1 downto 0);
core_adr_s <= wbm_out_s.adr(WB_AW-1 downto WB_REG_AW);
-- connect common signals
wbs1_in_s.dat <= wbm_out_s.dat;
wbs2_in_s.dat <= wbm_out_s.dat;
wbs3_in_s.dat <= wbm_out_s.dat;
wbs1_in_s.adr <= reg_adr_s;
wbs2_in_s.adr <= reg_adr_s;
wbs3_in_s.adr <= reg_adr_s;
wbs1_in_s.we <= wbm_out_s.we;
wbs2_in_s.we <= wbm_out_s.we;
wbs3_in_s.we <= wbm_out_s.we;
wbs1_in_s.cyc <= wbs1_in_s.cyc;
wbs2_in_s.cyc <= wbs2_in_s.cyc;
wbs3_in_s.cyc <= wbs3_in_s.cyc;
wbm_in_s.clk <= clk_s;
wbs1_in_s.clk <= clk_s;
wbs2_in_s.clk <= clk_s;
wbs3_in_s.clk <= clk_s;
wbs1_in_s.rst <= wishbone_rst_s;
wbs2_in_s.rst <= wishbone_rst_s;
wbs3_in_s.rst <= wishbone_rst_s;
-- slave data out mux
with core_adr_s select wbm_in_s.dat <=
wbs1_out_s.dat when WBS1_ADR,
wbs2_out_s.dat when WBS2_ADR,
wbs3_out_s.dat when WBS3_ADR,
wbs3_out_s.dat when WBS8_ADR,
(others => '-') when others;
-- address comparator
adr_match_1_s <= '1' when core_adr_s = WBS1_ADR else '0';
adr_match_2_s <= '1' when core_adr_s = WBS2_ADR else '0';
adr_match_3_s <= '1' when (core_adr_s = WBS3_ADR OR core_adr_s = WBS8_ADR) else '0';
-- ack or gate
wbm_in_s.ack <= wbs1_out_s.ack or
wbs2_out_s.ack or
wbs3_out_s.ack;
-- stb and gates
wbs1_in_s.stb <= wbm_out_s.cyc and wbm_out_s.stb and adr_match_1_s;
wbs2_in_s.stb <= wbm_out_s.cyc and wbm_out_s.stb and adr_match_2_s;
wbs3_in_s.stb <= wbm_out_s.cyc and wbm_out_s.stb and adr_match_3_s;
-------------------------------------------------
CLK_GENERATOR :
-------------------------------------------------
process begin
clk_s <= '0';
wait for CLK_PERIOD/2;
clk_s <= '1';
wait for CLK_PERIOD/2;
end process CLK_GENERATOR;
end simulation;
|
library IEEE;
use IEEE.std_logic_1164.all;
-- Contador BCD 0-9 con flag
entity bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
q: out std_logic_vector(3 downto 0);
c: out std_logic -- Flag de carry
);
end;
architecture bcd_arq of bcd is
signal rst_aux: std_logic := '0';
signal q_aux: std_logic_vector(3 downto 0) := "0000";
begin
-- Salida
q <= q_aux;
-- Flag de carry
c <= q_aux(0) and q_aux(3);
-- Si pasa el 9, reset
rst_aux <= rst or (q_aux(1) and q_aux(3));
Contador: entity work.contador4b
port map(
clk => clk,
rst => rst_aux,
ena => ena,
q => q_aux
);
end;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing device programming or simulation files), and
-- any associated documentation or information are expressly subject to the
-- terms and conditions of the Altera Program License Subscription Agreement,
-- Altera MegaCore Function License Agreement, or other applicable license
-- agreement, including, without limitation, that your use is for the sole
-- purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
-----------------------------------------------------------------------------
-- VHDL created from fp_rsqrt_s5
-- VHDL created on Mon Mar 11 11:49:52 2013
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use IEEE.MATH_REAL.all;
use std.TextIO.all;
use work.dspba_library_package.all;
LIBRARY altera_mf;
USE altera_mf.altera_mf_components.all;
LIBRARY lpm;
USE lpm.lpm_components.all;
entity fp_rsqrt_s5 is
port (
a : in std_logic_vector(31 downto 0);
en : in std_logic_vector(0 downto 0);
q : out std_logic_vector(31 downto 0);
clk : in std_logic;
areset : in std_logic
);
end;
architecture normal of fp_rsqrt_s5 is
attribute altera_attribute : string;
attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410";
signal VCC_q : std_logic_vector (0 downto 0);
signal cstAllOWE_uid6_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstAllZWF_uid7_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstNaNWF_uid8_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal cstAllZWE_uid9_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasM1o2M1_uid10_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cst3BiasP1o2M1_uid11_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal cstSel_uid42_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal cstSel_uid42_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_a : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 : std_logic_vector (23 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr : SIGNED (24 downto 0);
signal prodXY_uid75_pT1_uid63_invSqrtPolyEval_q : std_logic_vector (23 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_a : std_logic_vector (14 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (22 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 : std_logic_vector (37 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr : SIGNED (38 downto 0);
signal prodXY_uid78_pT2_uid69_invSqrtPolyEval_q : std_logic_vector (37 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC0_uid59_invSqrtTabGen_lutmem_ia : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_iq : std_logic_vector (29 downto 0);
signal memoryC0_uid59_invSqrtTabGen_lutmem_q : std_logic_vector (29 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC1_uid60_invSqrtTabGen_lutmem_ia : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_iq : std_logic_vector (20 downto 0);
signal memoryC1_uid60_invSqrtTabGen_lutmem_q : std_logic_vector (20 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_reset0 : std_logic;
signal memoryC2_uid61_invSqrtTabGen_lutmem_ia : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_aa : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_ab : std_logic_vector (8 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_iq : std_logic_vector (11 downto 0);
signal memoryC2_uid61_invSqrtTabGen_lutmem_q : std_logic_vector (11 downto 0);
signal reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q : std_logic_vector (2 downto 0);
signal reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q : std_logic_vector (8 downto 0);
signal reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q : std_logic_vector (11 downto 0);
signal reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q : std_logic_vector (11 downto 0);
signal reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q : std_logic_vector (20 downto 0);
signal reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q : std_logic_vector (14 downto 0);
signal reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q : std_logic_vector (22 downto 0);
signal reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q : std_logic_vector (29 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q : std_logic_vector (22 downto 0);
signal ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q : std_logic_vector (6 downto 0);
signal ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q : std_logic_vector (1 downto 0);
signal ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q : std_logic_vector (8 downto 0);
signal ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q : std_logic_vector (22 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 : std_logic;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q : std_logic_vector (7 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q : std_logic_vector (3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve : boolean;
attribute preserve of ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q : signal is true;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq : std_logic;
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q : signal is true;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 : std_logic;
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0);
attribute preserve of ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q : signal is true;
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0);
signal exp_uid16_fpInvSqrtTest_in : std_logic_vector (30 downto 0);
signal exp_uid16_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal frac_uid20_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal frac_uid20_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal signX_uid31_fpInvSqrtTest_in : std_logic_vector (31 downto 0);
signal signX_uid31_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsZero_uid17_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_a : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_b : std_logic_vector(7 downto 0);
signal expXIsMax_uid19_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_a : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_b : std_logic_vector(22 downto 0);
signal fracXIsZero_uid21_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_I_uid22_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expRExt_uid44_fpInvSqrtTest_a : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_b : std_logic_vector(8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_o : std_logic_vector (8 downto 0);
signal expRExt_uid44_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal outMuxSelEnc_uid53_fpInvSqrtTest_q : std_logic_vector(1 downto 0);
signal signR_uid56_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal signR_uid56_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b : std_logic_vector (12 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in : std_logic_vector (37 downto 0);
signal prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b : std_logic_vector (23 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_in : std_logic_vector (14 downto 0);
signal yPPolyEval_uid37_fpInvSqrtTest_b : std_logic_vector (14 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b : std_logic_vector(3 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b : std_logic_vector(0 downto 0);
signal ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0);
signal ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b : std_logic_vector(0 downto 0);
signal ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q : std_logic_vector(0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_in : std_logic_vector (0 downto 0);
signal evenOddExp_uid33_fpInvSqrtTest_b : std_logic_vector (0 downto 0);
signal expRExt_uid43_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expRExt_uid43_fpInvSqrtTest_b : std_logic_vector (6 downto 0);
signal yAddr_uid35_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal yAddr_uid35_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvSignX_uid47_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvExpXIsZero_uid49_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal InvFracXIsZero_uid23_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal join_uid41_fpInvSqrtTest_q : std_logic_vector (1 downto 0);
signal excRZero_uid48_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal excRZero_uid48_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal expR_uid45_fpInvSqrtTest_in : std_logic_vector (7 downto 0);
signal expR_uid45_fpInvSqrtTest_b : std_logic_vector (7 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal expRPostExc_uid55_fpInvSqrtTest_q : std_logic_vector (7 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_in : std_logic_vector (0 downto 0);
signal lowRangeB_uid64_invSqrtPolyEval_b : std_logic_vector (0 downto 0);
signal highBBits_uid65_invSqrtPolyEval_in : std_logic_vector (12 downto 0);
signal highBBits_uid65_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_in : std_logic_vector (1 downto 0);
signal lowRangeB_uid70_invSqrtPolyEval_b : std_logic_vector (1 downto 0);
signal highBBits_uid71_invSqrtPolyEval_in : std_logic_vector (23 downto 0);
signal highBBits_uid71_invSqrtPolyEval_b : std_logic_vector (21 downto 0);
signal yT1_uid62_invSqrtPolyEval_in : std_logic_vector (14 downto 0);
signal yT1_uid62_invSqrtPolyEval_b : std_logic_vector (11 downto 0);
signal yAddrPEvenOdd_uid36_fpInvSqrtTest_q : std_logic_vector (8 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xRegNeg_uid50_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal exc_N_uid24_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_a : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_b : std_logic_vector(21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_o : std_logic_vector (21 downto 0);
signal sumAHighB_uid66_invSqrtPolyEval_q : std_logic_vector (21 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_a : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_b : std_logic_vector(30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_o : std_logic_vector (30 downto 0);
signal sumAHighB_uid72_invSqrtPolyEval_q : std_logic_vector (30 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_a : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_b : std_logic_vector(0 downto 0);
signal xNOxRNeg_uid51_fpInvSqrtTest_q : std_logic_vector(0 downto 0);
signal s1_uid64_uid67_invSqrtPolyEval_q : std_logic_vector (22 downto 0);
signal s2_uid70_uid73_invSqrtPolyEval_q : std_logic_vector (32 downto 0);
signal excRConc_uid52_fpInvSqrtTest_q : std_logic_vector (2 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_in : std_logic_vector (29 downto 0);
signal fxpInvSqrtRes_uid39_fpInvSqrtTest_b : std_logic_vector (23 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_in : std_logic_vector (22 downto 0);
signal fxpInverseResFrac_uid46_fpInvSqrtTest_b : std_logic_vector (22 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_s : std_logic_vector (1 downto 0);
signal fracRPostExc_uid54_fpInvSqrtTest_q : std_logic_vector (22 downto 0);
signal R_uid57_fpInvSqrtTest_q : std_logic_vector (31 downto 0);
begin
--GND(CONSTANT,0)
--xIn(GPIN,3)@0
--signX_uid31_fpInvSqrtTest(BITSELECT,30)@0
signX_uid31_fpInvSqrtTest_in <= a;
signX_uid31_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_in(31 downto 31);
--cstAllZWE_uid9_fpInvSqrtTest(CONSTANT,8)
cstAllZWE_uid9_fpInvSqrtTest_q <= "00000000";
--exp_uid16_fpInvSqrtTest(BITSELECT,15)@0
exp_uid16_fpInvSqrtTest_in <= a(30 downto 0);
exp_uid16_fpInvSqrtTest_b <= exp_uid16_fpInvSqrtTest_in(30 downto 23);
--expXIsZero_uid17_fpInvSqrtTest(LOGICAL,16)@0
expXIsZero_uid17_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsZero_uid17_fpInvSqrtTest_b <= cstAllZWE_uid9_fpInvSqrtTest_q;
expXIsZero_uid17_fpInvSqrtTest_q <= "1" when expXIsZero_uid17_fpInvSqrtTest_a = expXIsZero_uid17_fpInvSqrtTest_b else "0";
--signR_uid56_fpInvSqrtTest(LOGICAL,55)@0
signR_uid56_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
signR_uid56_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
signR_uid56_fpInvSqrtTest_q <= signR_uid56_fpInvSqrtTest_a and signR_uid56_fpInvSqrtTest_b;
--ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c(DELAY,139)@0
ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c : dspba_delay
GENERIC MAP ( width => 1, depth => 11 )
PORT MAP ( xin => signR_uid56_fpInvSqrtTest_q, xout => ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q, ena => en(0), clk => clk, aclr => areset );
--VCC(CONSTANT,1)
VCC_q <= "1";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable(LOGICAL,182)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q <= not ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_a;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor(LOGICAL,183)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q <= not (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_a or ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_b);
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top(CONSTANT,179)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q <= "0111";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp(LOGICAL,180)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_mem_top_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q <= "1" when ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_a = ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_b else "0";
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg(REG,181)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena(REG,184)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_nor_q = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd(LOGICAL,185)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_sticky_ena_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_a and ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_b;
--cstAllOWE_uid6_fpInvSqrtTest(CONSTANT,5)
cstAllOWE_uid6_fpInvSqrtTest_q <= "11111111";
--expRExt_uid43_fpInvSqrtTest(BITSELECT,42)@0
expRExt_uid43_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b;
expRExt_uid43_fpInvSqrtTest_b <= expRExt_uid43_fpInvSqrtTest_in(7 downto 1);
--ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b(DELAY,116)@0
ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 7, depth => 1 )
PORT MAP ( xin => expRExt_uid43_fpInvSqrtTest_b, xout => ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--cst3BiasM1o2M1_uid10_fpInvSqrtTest(CONSTANT,9)
cst3BiasM1o2M1_uid10_fpInvSqrtTest_q <= "10111101";
--cst3BiasP1o2M1_uid11_fpInvSqrtTest(CONSTANT,10)
cst3BiasP1o2M1_uid11_fpInvSqrtTest_q <= "10111110";
--cstAllZWF_uid7_fpInvSqrtTest(CONSTANT,6)
cstAllZWF_uid7_fpInvSqrtTest_q <= "00000000000000000000000";
--frac_uid20_fpInvSqrtTest(BITSELECT,19)@0
frac_uid20_fpInvSqrtTest_in <= a(22 downto 0);
frac_uid20_fpInvSqrtTest_b <= frac_uid20_fpInvSqrtTest_in(22 downto 0);
--fracXIsZero_uid21_fpInvSqrtTest(LOGICAL,20)@0
fracXIsZero_uid21_fpInvSqrtTest_a <= frac_uid20_fpInvSqrtTest_b;
fracXIsZero_uid21_fpInvSqrtTest_b <= cstAllZWF_uid7_fpInvSqrtTest_q;
fracXIsZero_uid21_fpInvSqrtTest_q <= "1" when fracXIsZero_uid21_fpInvSqrtTest_a = fracXIsZero_uid21_fpInvSqrtTest_b else "0";
--evenOddExp_uid33_fpInvSqrtTest(BITSELECT,32)@0
evenOddExp_uid33_fpInvSqrtTest_in <= exp_uid16_fpInvSqrtTest_b(0 downto 0);
evenOddExp_uid33_fpInvSqrtTest_b <= evenOddExp_uid33_fpInvSqrtTest_in(0 downto 0);
--join_uid41_fpInvSqrtTest(BITJOIN,40)@0
join_uid41_fpInvSqrtTest_q <= fracXIsZero_uid21_fpInvSqrtTest_q & evenOddExp_uid33_fpInvSqrtTest_b;
--cstSel_uid42_fpInvSqrtTest(MUX,41)@0
cstSel_uid42_fpInvSqrtTest_s <= join_uid41_fpInvSqrtTest_q;
cstSel_uid42_fpInvSqrtTest: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
CASE cstSel_uid42_fpInvSqrtTest_s IS
WHEN "00" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "01" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasM1o2M1_uid10_fpInvSqrtTest_q;
WHEN "10" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN "11" => cstSel_uid42_fpInvSqrtTest_q <= cst3BiasP1o2M1_uid11_fpInvSqrtTest_q;
WHEN OTHERS => cstSel_uid42_fpInvSqrtTest_q <= (others => '0');
END CASE;
END IF;
END IF;
END PROCESS;
--expRExt_uid44_fpInvSqrtTest(SUB,43)@1
expRExt_uid44_fpInvSqrtTest_a <= STD_LOGIC_VECTOR("0" & cstSel_uid42_fpInvSqrtTest_q);
expRExt_uid44_fpInvSqrtTest_b <= STD_LOGIC_VECTOR("00" & ld_expRExt_uid43_fpInvSqrtTest_b_to_expRExt_uid44_fpInvSqrtTest_b_q);
expRExt_uid44_fpInvSqrtTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid44_fpInvSqrtTest_a) - UNSIGNED(expRExt_uid44_fpInvSqrtTest_b));
expRExt_uid44_fpInvSqrtTest_q <= expRExt_uid44_fpInvSqrtTest_o(8 downto 0);
--expR_uid45_fpInvSqrtTest(BITSELECT,44)@1
expR_uid45_fpInvSqrtTest_in <= expRExt_uid44_fpInvSqrtTest_q(7 downto 0);
expR_uid45_fpInvSqrtTest_b <= expR_uid45_fpInvSqrtTest_in(7 downto 0);
--InvExpXIsZero_uid49_fpInvSqrtTest(LOGICAL,48)@0
InvExpXIsZero_uid49_fpInvSqrtTest_a <= expXIsZero_uid17_fpInvSqrtTest_q;
InvExpXIsZero_uid49_fpInvSqrtTest_q <= not InvExpXIsZero_uid49_fpInvSqrtTest_a;
--xRegNeg_uid50_fpInvSqrtTest(LOGICAL,49)@0
xRegNeg_uid50_fpInvSqrtTest_a <= InvExpXIsZero_uid49_fpInvSqrtTest_q;
xRegNeg_uid50_fpInvSqrtTest_b <= signX_uid31_fpInvSqrtTest_b;
xRegNeg_uid50_fpInvSqrtTest_q <= xRegNeg_uid50_fpInvSqrtTest_a and xRegNeg_uid50_fpInvSqrtTest_b;
--InvFracXIsZero_uid23_fpInvSqrtTest(LOGICAL,22)@0
InvFracXIsZero_uid23_fpInvSqrtTest_a <= fracXIsZero_uid21_fpInvSqrtTest_q;
InvFracXIsZero_uid23_fpInvSqrtTest_q <= not InvFracXIsZero_uid23_fpInvSqrtTest_a;
--expXIsMax_uid19_fpInvSqrtTest(LOGICAL,18)@0
expXIsMax_uid19_fpInvSqrtTest_a <= exp_uid16_fpInvSqrtTest_b;
expXIsMax_uid19_fpInvSqrtTest_b <= cstAllOWE_uid6_fpInvSqrtTest_q;
expXIsMax_uid19_fpInvSqrtTest_q <= "1" when expXIsMax_uid19_fpInvSqrtTest_a = expXIsMax_uid19_fpInvSqrtTest_b else "0";
--exc_N_uid24_fpInvSqrtTest(LOGICAL,23)@0
exc_N_uid24_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_b <= InvFracXIsZero_uid23_fpInvSqrtTest_q;
exc_N_uid24_fpInvSqrtTest_q <= exc_N_uid24_fpInvSqrtTest_a and exc_N_uid24_fpInvSqrtTest_b;
--xNOxRNeg_uid51_fpInvSqrtTest(LOGICAL,50)@0
xNOxRNeg_uid51_fpInvSqrtTest_a <= exc_N_uid24_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_b <= xRegNeg_uid50_fpInvSqrtTest_q;
xNOxRNeg_uid51_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_a or xNOxRNeg_uid51_fpInvSqrtTest_b;
--exc_I_uid22_fpInvSqrtTest(LOGICAL,21)@0
exc_I_uid22_fpInvSqrtTest_a <= expXIsMax_uid19_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_b <= fracXIsZero_uid21_fpInvSqrtTest_q;
exc_I_uid22_fpInvSqrtTest_q <= exc_I_uid22_fpInvSqrtTest_a and exc_I_uid22_fpInvSqrtTest_b;
--InvSignX_uid47_fpInvSqrtTest(LOGICAL,46)@0
InvSignX_uid47_fpInvSqrtTest_a <= signX_uid31_fpInvSqrtTest_b;
InvSignX_uid47_fpInvSqrtTest_q <= not InvSignX_uid47_fpInvSqrtTest_a;
--excRZero_uid48_fpInvSqrtTest(LOGICAL,47)@0
excRZero_uid48_fpInvSqrtTest_a <= InvSignX_uid47_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_b <= exc_I_uid22_fpInvSqrtTest_q;
excRZero_uid48_fpInvSqrtTest_q <= excRZero_uid48_fpInvSqrtTest_a and excRZero_uid48_fpInvSqrtTest_b;
--excRConc_uid52_fpInvSqrtTest(BITJOIN,51)@0
excRConc_uid52_fpInvSqrtTest_q <= xNOxRNeg_uid51_fpInvSqrtTest_q & expXIsZero_uid17_fpInvSqrtTest_q & excRZero_uid48_fpInvSqrtTest_q;
--reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0(REG,83)@0
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q <= excRConc_uid52_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--outMuxSelEnc_uid53_fpInvSqrtTest(LOOKUP,52)@1
outMuxSelEnc_uid53_fpInvSqrtTest: PROCESS (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q)
BEGIN
-- Begin reserved scope level
CASE (reg_excRConc_uid52_fpInvSqrtTest_0_to_outMuxSelEnc_uid53_fpInvSqrtTest_0_q) IS
WHEN "000" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN "001" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "010" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "011" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "100" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "11";
WHEN "101" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "00";
WHEN "110" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "10";
WHEN "111" => outMuxSelEnc_uid53_fpInvSqrtTest_q <= "01";
WHEN OTHERS =>
outMuxSelEnc_uid53_fpInvSqrtTest_q <= (others => '-');
END CASE;
-- End reserved scope level
END PROCESS;
--expRPostExc_uid55_fpInvSqrtTest(MUX,54)@1
expRPostExc_uid55_fpInvSqrtTest_s <= outMuxSelEnc_uid53_fpInvSqrtTest_q;
expRPostExc_uid55_fpInvSqrtTest: PROCESS (expRPostExc_uid55_fpInvSqrtTest_s, en, cstAllZWE_uid9_fpInvSqrtTest_q, expR_uid45_fpInvSqrtTest_b, cstAllOWE_uid6_fpInvSqrtTest_q, cstAllOWE_uid6_fpInvSqrtTest_q)
BEGIN
CASE expRPostExc_uid55_fpInvSqrtTest_s IS
WHEN "00" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllZWE_uid9_fpInvSqrtTest_q;
WHEN "01" => expRPostExc_uid55_fpInvSqrtTest_q <= expR_uid45_fpInvSqrtTest_b;
WHEN "10" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN "11" => expRPostExc_uid55_fpInvSqrtTest_q <= cstAllOWE_uid6_fpInvSqrtTest_q;
WHEN OTHERS => expRPostExc_uid55_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg(DELAY,173)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg : dspba_delay
GENERIC MAP ( width => 8, depth => 1 )
PORT MAP ( xin => expRPostExc_uid55_fpInvSqrtTest_q, xout => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt(COUNTER,175)
-- every=1, low=0, high=7, step=1, init=1
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_i,3));
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg(REG,176)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux(MUX,177)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s <= en;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q, ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q)
BEGIN
CASE ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_s IS
WHEN "0" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
WHEN "1" => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdcnt_q;
WHEN OTHERS => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem(DUALMEM,174)
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_inputreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdreg_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_rdmux_q;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 8,
widthad_a => 3,
numwords_a => 8,
width_b => 8,
widthad_b => 3,
numwords_b => 8,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0,
clock1 => clk,
address_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq,
address_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_aa,
data_a => ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_ia
);
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_reset0 <= areset;
ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_iq(7 downto 0);
--cstNaNWF_uid8_fpInvSqrtTest(CONSTANT,7)
cstNaNWF_uid8_fpInvSqrtTest_q <= "00000000000000000000001";
--yAddr_uid35_fpInvSqrtTest(BITSELECT,34)@0
yAddr_uid35_fpInvSqrtTest_in <= frac_uid20_fpInvSqrtTest_b;
yAddr_uid35_fpInvSqrtTest_b <= yAddr_uid35_fpInvSqrtTest_in(22 downto 15);
--yAddrPEvenOdd_uid36_fpInvSqrtTest(BITJOIN,35)@0
yAddrPEvenOdd_uid36_fpInvSqrtTest_q <= evenOddExp_uid33_fpInvSqrtTest_b & yAddr_uid35_fpInvSqrtTest_b;
--reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0(REG,84)@0
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= "000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q <= yAddrPEvenOdd_uid36_fpInvSqrtTest_q;
END IF;
END IF;
END PROCESS;
--memoryC2_uid61_invSqrtTabGen_lutmem(DUALMEM,82)@1
memoryC2_uid61_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC2_uid61_invSqrtTabGen_lutmem_ab <= reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q;
memoryC2_uid61_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 12,
widthad_a => 9,
numwords_a => 512,
width_b => 12,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC2_uid61_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC2_uid61_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC2_uid61_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC2_uid61_invSqrtTabGen_lutmem_iq,
address_a => memoryC2_uid61_invSqrtTabGen_lutmem_aa,
data_a => memoryC2_uid61_invSqrtTabGen_lutmem_ia
);
memoryC2_uid61_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC2_uid61_invSqrtTabGen_lutmem_q <= memoryC2_uid61_invSqrtTabGen_lutmem_iq(11 downto 0);
--reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1(REG,86)@3
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q <= memoryC2_uid61_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg(DELAY,172)
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg : dspba_delay
GENERIC MAP ( width => 23, depth => 1 )
PORT MAP ( xin => frac_uid20_fpInvSqrtTest_b, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a(DELAY,109)@0
ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a : dspba_delay
GENERIC MAP ( width => 23, depth => 2 )
PORT MAP ( xin => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_inputreg_q, xout => ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q, ena => en(0), clk => clk, aclr => areset );
--yPPolyEval_uid37_fpInvSqrtTest(BITSELECT,36)@3
yPPolyEval_uid37_fpInvSqrtTest_in <= ld_frac_uid20_fpInvSqrtTest_b_to_yPPolyEval_uid37_fpInvSqrtTest_a_q(14 downto 0);
yPPolyEval_uid37_fpInvSqrtTest_b <= yPPolyEval_uid37_fpInvSqrtTest_in(14 downto 0);
--yT1_uid62_invSqrtPolyEval(BITSELECT,61)@3
yT1_uid62_invSqrtPolyEval_in <= yPPolyEval_uid37_fpInvSqrtTest_b;
yT1_uid62_invSqrtPolyEval_b <= yT1_uid62_invSqrtPolyEval_in(14 downto 3);
--reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0(REG,85)@3
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= "000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q <= yT1_uid62_invSqrtPolyEval_b;
END IF;
END IF;
END PROCESS;
--prodXY_uid75_pT1_uid63_invSqrtPolyEval(MULT,74)@4
prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_a),13)) * SIGNED(prodXY_uid75_pT1_uid63_invSqrtPolyEval_b);
prodXY_uid75_pT1_uid63_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= (others => '0');
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_a <= reg_yT1_uid62_invSqrtPolyEval_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_0_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_b <= reg_memoryC2_uid61_invSqrtTabGen_lutmem_0_to_prodXY_uid75_pT1_uid63_invSqrtPolyEval_1_q;
prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid75_pT1_uid63_invSqrtPolyEval_pr,24));
END IF;
END IF;
END PROCESS;
prodXY_uid75_pT1_uid63_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid75_pT1_uid63_invSqrtPolyEval_q <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval(BITSELECT,75)@7
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in <= prodXY_uid75_pT1_uid63_invSqrtPolyEval_q;
prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_in(23 downto 11);
--highBBits_uid65_invSqrtPolyEval(BITSELECT,64)@7
highBBits_uid65_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b;
highBBits_uid65_invSqrtPolyEval_b <= highBBits_uid65_invSqrtPolyEval_in(12 downto 1);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a(DELAY,160)@1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a : dspba_delay
GENERIC MAP ( width => 9, depth => 3 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset );
--memoryC1_uid60_invSqrtTabGen_lutmem(DUALMEM,81)@4
memoryC1_uid60_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC1_uid60_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC1_uid60_invSqrtTabGen_lutmem_0_q_to_memoryC1_uid60_invSqrtTabGen_lutmem_a_q;
memoryC1_uid60_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 21,
widthad_a => 9,
numwords_a => 512,
width_b => 21,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC1_uid60_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC1_uid60_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC1_uid60_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC1_uid60_invSqrtTabGen_lutmem_iq,
address_a => memoryC1_uid60_invSqrtTabGen_lutmem_aa,
data_a => memoryC1_uid60_invSqrtTabGen_lutmem_ia
);
memoryC1_uid60_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC1_uid60_invSqrtTabGen_lutmem_q <= memoryC1_uid60_invSqrtTabGen_lutmem_iq(20 downto 0);
--reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0(REG,88)@6
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= "000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q <= memoryC1_uid60_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid66_invSqrtPolyEval(ADD,65)@7
sumAHighB_uid66_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q(20)) & reg_memoryC1_uid60_invSqrtTabGen_lutmem_0_to_sumAHighB_uid66_invSqrtPolyEval_0_q);
sumAHighB_uid66_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid65_invSqrtPolyEval_b(11)) & highBBits_uid65_invSqrtPolyEval_b);
sumAHighB_uid66_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid66_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid66_invSqrtPolyEval_b));
sumAHighB_uid66_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_o(21 downto 0);
--lowRangeB_uid64_invSqrtPolyEval(BITSELECT,63)@7
lowRangeB_uid64_invSqrtPolyEval_in <= prodXYTruncFR_uid76_pT1_uid63_invSqrtPolyEval_b(0 downto 0);
lowRangeB_uid64_invSqrtPolyEval_b <= lowRangeB_uid64_invSqrtPolyEval_in(0 downto 0);
--s1_uid64_uid67_invSqrtPolyEval(BITJOIN,66)@7
s1_uid64_uid67_invSqrtPolyEval_q <= sumAHighB_uid66_invSqrtPolyEval_q & lowRangeB_uid64_invSqrtPolyEval_b;
--reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1(REG,90)@7
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= "00000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q <= s1_uid64_uid67_invSqrtPolyEval_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor(LOGICAL,207)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_a or ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_b);
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg(REG,205)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q <= VCC_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena(REG,208)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_nor_q = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd(LOGICAL,209)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_sticky_ena_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_b;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg(DELAY,199)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg : dspba_delay
GENERIC MAP ( width => 15, depth => 1 )
PORT MAP ( xin => yPPolyEval_uid37_fpInvSqrtTest_b, xout => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt(COUNTER,201)
-- every=1, low=0, high=1, step=1, init=1
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1);
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i + 1;
END IF;
END IF;
END PROCESS;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_i,1));
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg(REG,202)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux(MUX,203)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s <= en;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux: PROCESS (ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q, ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q)
BEGIN
CASE ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_s IS
WHEN "0" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
WHEN "1" => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdcnt_q;
WHEN OTHERS => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem(DUALMEM,200)
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_inputreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdreg_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_rdmux_q;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 15,
widthad_a => 1,
numwords_a => 2,
width_b => 15,
widthad_b => 1,
numwords_b => 2,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq,
address_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_aa,
data_a => ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_ia
);
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_reset0 <= areset;
ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_iq(14 downto 0);
--reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0(REG,89)@7
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= "000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q <= ld_yPPolyEval_uid37_fpInvSqrtTest_b_to_reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_a_replace_mem_q;
END IF;
END IF;
END PROCESS;
--prodXY_uid78_pT2_uid69_invSqrtPolyEval(MULT,77)@8
prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_a),16)) * SIGNED(prodXY_uid78_pT2_uid69_invSqrtPolyEval_b);
prodXY_uid78_pT2_uid69_invSqrtPolyEval_component: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= (others => '0');
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_a <= reg_yPPolyEval_uid37_fpInvSqrtTest_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_0_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_b <= reg_s1_uid64_uid67_invSqrtPolyEval_0_to_prodXY_uid78_pT2_uid69_invSqrtPolyEval_1_q;
prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid78_pT2_uid69_invSqrtPolyEval_pr,38));
END IF;
END IF;
END PROCESS;
prodXY_uid78_pT2_uid69_invSqrtPolyEval: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= (others => '0');
ELSIF(clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
prodXY_uid78_pT2_uid69_invSqrtPolyEval_q <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_s1;
END IF;
END IF;
END PROCESS;
--prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval(BITSELECT,78)@11
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in <= prodXY_uid78_pT2_uid69_invSqrtPolyEval_q;
prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_in(37 downto 14);
--highBBits_uid71_invSqrtPolyEval(BITSELECT,70)@11
highBBits_uid71_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b;
highBBits_uid71_invSqrtPolyEval_b <= highBBits_uid71_invSqrtPolyEval_in(23 downto 2);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor(LOGICAL,196)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a <= ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_notEnable_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q <= not (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_a or ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_b);
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top(CONSTANT,192)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q <= "0100";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp(LOGICAL,193)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_mem_top_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q <= "1" when ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_a = ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_b else "0";
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg(REG,194)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= "0";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmp_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena(REG,197)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= "0";
ELSIF rising_edge(clk) THEN
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_nor_q = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_cmpReg_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd(LOGICAL,198)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_sticky_ena_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_a and ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_b;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg(DELAY,186)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg : dspba_delay
GENERIC MAP ( width => 9, depth => 1 )
PORT MAP ( xin => reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC2_uid61_invSqrtTabGen_lutmem_0_q, xout => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset );
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt(COUNTER,188)
-- every=1, low=0, high=4, step=1, init=1
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
ELSIF (clk'EVENT AND clk = '1') THEN
IF (en = "1") THEN
IF ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i = 3 THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '1';
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq <= '0';
END IF;
IF (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i - 4;
ELSE
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i + 1;
END IF;
END IF;
END IF;
END PROCESS;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_i,3));
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg(REG,189)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= "000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
END IF;
END IF;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux(MUX,190)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s <= en;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q, ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q)
BEGIN
CASE ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_s IS
WHEN "0" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
WHEN "1" => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdcnt_q;
WHEN OTHERS => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q <= (others => '0');
END CASE;
END PROCESS;
--ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem(DUALMEM,187)
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_inputreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdreg_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_rdmux_q;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "MLAB",
operation_mode => "DUAL_PORT",
width_a => 9,
widthad_a => 3,
numwords_a => 5,
width_b => 9,
widthad_b => 3,
numwords_b => 5,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK1",
outdata_aclr_b => "CLEAR1",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "UNUSED",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_enaAnd_q(0),
clocken0 => '1',
wren_a => en(0),
clock0 => clk,
aclr1 => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0,
clock1 => clk,
address_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ab,
-- data_b => (others => '0'),
q_b => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq,
address_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_aa,
data_a => ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_ia
);
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_reset0 <= areset;
ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_iq(8 downto 0);
--memoryC0_uid59_invSqrtTabGen_lutmem(DUALMEM,80)@8
memoryC0_uid59_invSqrtTabGen_lutmem_ia <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_aa <= (others => '0');
memoryC0_uid59_invSqrtTabGen_lutmem_ab <= ld_reg_yAddrPEvenOdd_uid36_fpInvSqrtTest_0_to_memoryC0_uid59_invSqrtTabGen_lutmem_0_q_to_memoryC0_uid59_invSqrtTabGen_lutmem_a_replace_mem_q;
memoryC0_uid59_invSqrtTabGen_lutmem_dmem : altsyncram
GENERIC MAP (
ram_block_type => "M20K",
operation_mode => "DUAL_PORT",
width_a => 30,
widthad_a => 9,
numwords_a => 512,
width_b => 30,
widthad_b => 9,
numwords_b => 512,
lpm_type => "altsyncram",
width_byteena_a => 1,
indata_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
rdcontrol_reg_b => "CLOCK0",
byteena_reg_b => "CLOCK0",
outdata_reg_b => "CLOCK0",
outdata_aclr_b => "CLEAR0",
address_reg_b => "CLOCK0",
clock_enable_input_a => "NORMAL",
clock_enable_input_b => "NORMAL",
clock_enable_output_b => "NORMAL",
read_during_write_mode_mixed_ports => "DONT_CARE",
power_up_uninitialized => "FALSE",
init_file => "fp_rsqrt_s5_memoryC0_uid59_invSqrtTabGen_lutmem.hex",
init_file_layout => "PORT_B",
intended_device_family => "Stratix V"
)
PORT MAP (
clocken0 => en(0),
wren_a => '0',
aclr0 => memoryC0_uid59_invSqrtTabGen_lutmem_reset0,
clock0 => clk,
address_b => memoryC0_uid59_invSqrtTabGen_lutmem_ab,
-- data_b => (others => '0'),
q_b => memoryC0_uid59_invSqrtTabGen_lutmem_iq,
address_a => memoryC0_uid59_invSqrtTabGen_lutmem_aa,
data_a => memoryC0_uid59_invSqrtTabGen_lutmem_ia
);
memoryC0_uid59_invSqrtTabGen_lutmem_reset0 <= areset;
memoryC0_uid59_invSqrtTabGen_lutmem_q <= memoryC0_uid59_invSqrtTabGen_lutmem_iq(29 downto 0);
--reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0(REG,92)@10
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0: PROCESS (clk, areset)
BEGIN
IF (areset = '1') THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= "000000000000000000000000000000";
ELSIF rising_edge(clk) THEN
IF (en = "1") THEN
reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q <= memoryC0_uid59_invSqrtTabGen_lutmem_q;
END IF;
END IF;
END PROCESS;
--sumAHighB_uid72_invSqrtPolyEval(ADD,71)@11
sumAHighB_uid72_invSqrtPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q(29)) & reg_memoryC0_uid59_invSqrtTabGen_lutmem_0_to_sumAHighB_uid72_invSqrtPolyEval_0_q);
sumAHighB_uid72_invSqrtPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid71_invSqrtPolyEval_b(21)) & highBBits_uid71_invSqrtPolyEval_b);
sumAHighB_uid72_invSqrtPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid72_invSqrtPolyEval_a) + SIGNED(sumAHighB_uid72_invSqrtPolyEval_b));
sumAHighB_uid72_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_o(30 downto 0);
--lowRangeB_uid70_invSqrtPolyEval(BITSELECT,69)@11
lowRangeB_uid70_invSqrtPolyEval_in <= prodXYTruncFR_uid79_pT2_uid69_invSqrtPolyEval_b(1 downto 0);
lowRangeB_uid70_invSqrtPolyEval_b <= lowRangeB_uid70_invSqrtPolyEval_in(1 downto 0);
--s2_uid70_uid73_invSqrtPolyEval(BITJOIN,72)@11
s2_uid70_uid73_invSqrtPolyEval_q <= sumAHighB_uid72_invSqrtPolyEval_q & lowRangeB_uid70_invSqrtPolyEval_b;
--fxpInvSqrtRes_uid39_fpInvSqrtTest(BITSELECT,38)@11
fxpInvSqrtRes_uid39_fpInvSqrtTest_in <= s2_uid70_uid73_invSqrtPolyEval_q(29 downto 0);
fxpInvSqrtRes_uid39_fpInvSqrtTest_b <= fxpInvSqrtRes_uid39_fpInvSqrtTest_in(29 downto 6);
--fxpInverseResFrac_uid46_fpInvSqrtTest(BITSELECT,45)@11
fxpInverseResFrac_uid46_fpInvSqrtTest_in <= fxpInvSqrtRes_uid39_fpInvSqrtTest_b(22 downto 0);
fxpInverseResFrac_uid46_fpInvSqrtTest_b <= fxpInverseResFrac_uid46_fpInvSqrtTest_in(22 downto 0);
--ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b(DELAY,131)@1
ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b : dspba_delay
GENERIC MAP ( width => 2, depth => 10 )
PORT MAP ( xin => outMuxSelEnc_uid53_fpInvSqrtTest_q, xout => ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q, ena => en(0), clk => clk, aclr => areset );
--fracRPostExc_uid54_fpInvSqrtTest(MUX,53)@11
fracRPostExc_uid54_fpInvSqrtTest_s <= ld_outMuxSelEnc_uid53_fpInvSqrtTest_q_to_fracRPostExc_uid54_fpInvSqrtTest_b_q;
fracRPostExc_uid54_fpInvSqrtTest: PROCESS (fracRPostExc_uid54_fpInvSqrtTest_s, en, cstAllZWF_uid7_fpInvSqrtTest_q, fxpInverseResFrac_uid46_fpInvSqrtTest_b, cstAllZWF_uid7_fpInvSqrtTest_q, cstNaNWF_uid8_fpInvSqrtTest_q)
BEGIN
CASE fracRPostExc_uid54_fpInvSqrtTest_s IS
WHEN "00" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "01" => fracRPostExc_uid54_fpInvSqrtTest_q <= fxpInverseResFrac_uid46_fpInvSqrtTest_b;
WHEN "10" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstAllZWF_uid7_fpInvSqrtTest_q;
WHEN "11" => fracRPostExc_uid54_fpInvSqrtTest_q <= cstNaNWF_uid8_fpInvSqrtTest_q;
WHEN OTHERS => fracRPostExc_uid54_fpInvSqrtTest_q <= (others => '0');
END CASE;
END PROCESS;
--R_uid57_fpInvSqrtTest(BITJOIN,56)@11
R_uid57_fpInvSqrtTest_q <= ld_signR_uid56_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_c_q & ld_expRPostExc_uid55_fpInvSqrtTest_q_to_R_uid57_fpInvSqrtTest_b_replace_mem_q & fracRPostExc_uid54_fpInvSqrtTest_q;
--xOut(GPOUT,4)@11
q <= R_uid57_fpInvSqrtTest_q;
end normal;
|
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support@bitvis.no>.
--
-- UVVM AND ANY PART THEREOF ARE PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
-- WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS
-- OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
-- OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH UVVM OR THE USE OR OTHER DEALINGS IN UVVM.
--========================================================================================================================
------------------------------------------------------------------------------------------
-- Description : See library quick reference (under 'doc') and README-file(s)
--
-- Important : For systems not using 'ready' a dummy signal must be declared and set to '1'
-- For systems not using 'terminate' a dummy signal must be declared and set to '1' if using sbi_poll_until()
------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library uvvm_util;
context uvvm_util.uvvm_util_context;
--=================================================================================================
package sbi_bfm_pkg is
--===============================================================================================
-- Types and constants for SBI BFMs
--===============================================================================================
constant C_SCOPE : string := "SBI BFM";
type t_sbi_if is record
cs : std_logic; -- to dut
addr : unsigned; -- to dut
rena : std_logic; -- to dut
wena : std_logic; -- to dut
wdata : std_logic_vector; -- to dut
ready : std_logic; -- from dut
rdata : std_logic_vector; -- from dut
end record;
-- Configuration record to be assigned in the test harness.
type t_sbi_bfm_config is
record
max_wait_cycles : integer; -- The maximum number of clock cycles to wait for the DUT ready signal before reporting a timeout alert.
max_wait_cycles_severity : t_alert_level; -- The above timeout will have this severity
use_fixed_wait_cycles_read : boolean; -- When true, wait 'fixed_wait_cycles_read' after asserting rena, before sampling rdata
fixed_wait_cycles_read : natural; -- Number of clock cycles to wait after asserting rd signal, before sampling rdata from DUT.
clock_period : time; -- Period of the clock signal
id_for_bfm : t_msg_id; -- The message ID used as a general message ID in the SBI BFM
id_for_bfm_wait : t_msg_id; -- The message ID used for logging waits in the SBI BFM
id_for_bfm_poll : t_msg_id; -- The message ID used for logging polling in the SBI BFM
use_ready_signal : boolean; -- Whether or not to use the interface ready signal
end record;
constant C_SBI_BFM_CONFIG_DEFAULT : t_sbi_bfm_config := (
max_wait_cycles => 10,
max_wait_cycles_severity => failure,
use_fixed_wait_cycles_read => false,
fixed_wait_cycles_read => 0,
clock_period => 10 ns,
id_for_bfm => ID_BFM,
id_for_bfm_wait => ID_BFM_WAIT,
id_for_bfm_poll => ID_BFM_POLL,
use_ready_signal => true
);
--===============================================================================================
-- BFM procedures
--===============================================================================================
------------------------------------------
-- init_sbi_if_signals
------------------------------------------
-- - This function returns an SBI interface with initialized signals.
-- - All SBI input signals are initialized to 0
-- - All SBI output signals are initialized to Z
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if;
------------------------------------------
-- sbi_write
------------------------------------------
-- - This procedure writes data to the SBI DUT
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal wdata : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_write
------------------------------------------
-- - This procedure writes data 'data_value' to the SBI DUT address 'addr_value'
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_read
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- returns the read data in the output 'data_value'
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
);
------------------------------------------
-- sbi_read
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and returns
-- the read data in the output 'data_value'
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
);
------------------------------------------
-- sbi_check
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_check
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, an alert with
-- severity 'alert_level' is triggered.
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_poll_until
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, a new read
-- will be performed, and the new read data will be compared with the
-- 'data_exp'. This process will continue until one of the following
-- conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_polls'
-- c) The time spent polling is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_polls' is set to 0, it will be interpreted as no limitation on number of polls
-- - The SBI interface in this procedure is given as individual signals
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
------------------------------------------
-- sbi_poll_until
------------------------------------------
-- - This procedure reads data from the SBI DUT address 'addr_value' and
-- compares the read data to the expected data in 'data_exp'.
-- - If the read data is inconsistent with the expected data, a new read
-- will be performed, and the new read data will be compared with the
-- 'data_exp'. This process will continue until one of the following
-- conditions are met:
-- a) The read data is equal to the expected data
-- b) The number of reads equal 'max_polls'
-- c) The time spent polling is equal to the 'timeout'
-- - If 'timeout' is set to 0, it will be interpreted as no timeout
-- - If 'max_polls' is set to 0, it will be interpreted as no limitation on number of polls
-- - The SBI interface in this procedure is given as a t_sbi_if signal record
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
);
end package sbi_bfm_pkg;
--=================================================================================================
--=================================================================================================
package body sbi_bfm_pkg is
---------------------------------------------------------------------------------
-- initialize sbi to dut signals
---------------------------------------------------------------------------------
function init_sbi_if_signals(
addr_width : natural;
data_width : natural
) return t_sbi_if is
variable result : t_sbi_if(addr(addr_width - 1 downto 0),
wdata(data_width - 1 downto 0),
rdata(data_width - 1 downto 0));
begin
result.cs := '0';
result.rena := '0';
result.wena := '0';
result.addr := (result.addr'range => '0');
result.wdata := (result.wdata'range => '0');
result.ready := 'Z';
result.rdata := (result.rdata'range => 'Z');
return result;
end function;
---------------------------------------------------------------------------------
-- write
---------------------------------------------------------------------------------
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal wdata : inout std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_write";
constant proc_call : string := "sbi_write(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_value, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalise to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
variable v_normalised_data : std_logic_vector(wdata'length-1 downto 0) :=
normalize_and_check(data_value, wdata, ALLOW_NARROWER, "data_value", "sbi_core_in.wdata", msg);
variable v_clk_cycles_waited : natural := 0;
begin
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
cs <= '1';
wena <= '1';
rena <= '0';
addr <= v_normalised_addr;
wdata <= v_normalised_data;
if config.use_ready_signal then
check_value(ready = '1' or ready = '0', failure, "Verifying that ready signal is set to either '1' or '0' when in use", scope, ID_NEVER, msg_id_panel);
end if;
wait until rising_edge(clk);
while (config.use_ready_signal and ready = '0') loop
if v_clk_cycles_waited = 0 then
log(config.id_for_bfm_wait, proc_call & " waiting for response (sbi ready=0) " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
wait until rising_edge(clk);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, proc_call);
end loop;
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
cs <= '0';
wena <= '0';
log(config.id_for_bfm, proc_call & " completed. " & add_msg_delimiter(msg), scope, msg_id_panel);
end procedure;
procedure sbi_write (
constant addr_value : in unsigned;
constant data_value : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_write(addr_value, data_value, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.wdata,
scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- sbi_read
---------------------------------------------------------------------------------
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
) is
-- local_proc_* used if called from sequencer or VVC
constant local_proc_name : string := "sbi_read";
constant local_proc_call : string := local_proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalize to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
variable v_data_value : std_logic_vector(data_value'range);
variable v_clk_cycles_waited : natural := 0;
variable v_proc_call : line;
begin
if ext_proc_call = "" then
-- called directly from sequencer/VVC, show 'sbi_read...' in log
write(v_proc_call, local_proc_call);
else
-- called from other BFM procedure like sbi_check, log 'sbi_check(..) while executing sbi_read..'
write(v_proc_call, ext_proc_call & " while executing " & local_proc_name);
end if;
wait_until_given_time_before_rising_edge(clk, config.clock_period/4, config.clock_period);
cs <= '1';
wena <= '0';
rena <= '1';
addr <= v_normalised_addr;
if config.use_ready_signal then
check_value(ready = '1' or ready = '0', failure, "Verifying that ready signal is set to either '1' or '0' when in use", scope, ID_NEVER, msg_id_panel);
end if;
wait until rising_edge(clk);
if config.use_fixed_wait_cycles_read then
-- Wait for a fixed number of clk cycles
for i in 1 to config.fixed_wait_cycles_read loop
v_clk_cycles_waited := v_clk_cycles_waited + 1;
wait until rising_edge(clk);
end loop;
else
-- If configured, wait for ready = '1'
while (config.use_ready_signal and ready = '0') loop
if v_clk_cycles_waited = 0 then
log(config.id_for_bfm_wait, v_proc_call.all & " waiting for response (sbi ready=0) " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
wait until rising_edge(clk);
v_clk_cycles_waited := v_clk_cycles_waited + 1;
check_value(v_clk_cycles_waited <= config.max_wait_cycles, config.max_wait_cycles_severity,
": Timeout while waiting for sbi ready", scope, ID_NEVER, msg_id_panel, v_proc_call.all);
end loop;
end if;
v_data_value := rdata;
data_value := v_data_value;
wait_until_given_time_after_rising_edge(clk, config.clock_period/4);
cs <= '0';
rena <= '0';
if ext_proc_call = "" then -- proc_name = "sbi_read"
log(config.id_for_bfm, v_proc_call.all & "=> " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
else
-- Log will be handled by calling procedure (e.g. sbi_check)
end if;
end procedure;
procedure sbi_read (
constant addr_value : in unsigned;
variable data_value : out std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT;
constant ext_proc_call : in string := "" -- External proc_call; overwrite if called from other BFM procedure like sbi_check
) is
begin
sbi_read(addr_value, data_value, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
scope, msg_id_panel, config, ext_proc_call);
end procedure;
---------------------------------------------------------------------------------
-- sbi_check
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the POLL_UNTILed value.
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_check";
constant proc_call : string := "sbi_check(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ")";
-- Normalize to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
-- Helper variables
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);
variable v_check_ok : boolean;
variable v_clk_cycles_waited : natural := 0;
begin
sbi_read(addr_value, v_data_value, msg, clk, cs, addr, rena, wena, ready, rdata, scope, msg_id_panel, config, proc_call);
-- Compare values, but ignore any leading zero's if widths are different.
-- Use ID_NEVER so that check_value method does not log when check is OK,
-- log it here instead.
v_check_ok := check_value(v_data_value, data_exp, alert_level, msg, scope, HEX_BIN_IF_INVALID, SKIP_LEADING_0, ID_NEVER, msg_id_panel, proc_call);
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
end if;
end procedure;
procedure sbi_check (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_check(addr_value, data_exp, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
alert_level, scope, msg_id_panel, config);
end procedure;
---------------------------------------------------------------------------------
-- sbi_poll_until
---------------------------------------------------------------------------------
-- Perform a read operation, then compare the read value to the POLL_UNTILed value.
-- The checking is repeated until timeout or N occurrences (reads) without POLL_UNTILed data.
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal cs : inout std_logic;
signal addr : inout unsigned;
signal rena : inout std_logic;
signal wena : inout std_logic;
signal ready : in std_logic;
signal rdata : in std_logic_vector;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
constant proc_name : string := "sbi_poll_until";
constant proc_call : string := proc_name & "(A:" & to_string(addr_value, HEX, AS_IS, INCL_RADIX) &
", " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & ", " & to_string(max_polls) & ", " & to_string(timeout, ns) & ")";
constant start_time : time := now;
-- Normalise to the DUT addr/data widths
variable v_normalised_addr : unsigned(addr'length-1 downto 0) :=
normalize_and_check(addr_value, addr, ALLOW_WIDER_NARROWER, "addr_value", "sbi_core_in.addr", msg);
-- Helper variables
variable v_data_value : std_logic_vector(rdata'length - 1 downto 0);
variable v_check_ok : boolean;
variable v_timeout_ok : boolean;
variable v_num_of_occurrences_ok : boolean;
variable v_num_of_occurrences : integer := 0;
variable v_clk_cycles_waited : natural := 0;
variable v_config : t_sbi_bfm_config := config;
begin
-- Check for timeout = 0 and max_polls = 0. This combination can result in an infinite loop if the POLL_UNTILed data does not appear.
if max_polls = 0 and timeout = 0 ns then
alert(TB_WARNING, proc_name & " called with timeout=0 and max_polls=0. This can result in an infinite loop. " & add_msg_delimiter(msg), scope);
end if;
-- Initial status of the checks
v_check_ok := false;
v_timeout_ok := true;
v_num_of_occurrences_ok := true;
v_config.id_for_bfm := ID_BFM_POLL;
while not v_check_ok and v_timeout_ok and v_num_of_occurrences_ok and (terminate_loop = '0') loop
-- Read data on SBI register
sbi_read(v_normalised_addr, v_data_value, "As a part of " & proc_call & ". " & add_msg_delimiter(msg), clk, cs, addr, rena, wena, ready, rdata, scope, msg_id_panel, v_config,
return_string1_if_true_otherwise_string2("", proc_call, is_log_msg_enabled(ID_BFM_POLL, msg_id_panel))); -- ID_BFM_POLL will allow the logging inside sbi_read to be executed
-- Evaluate data
v_check_ok := matching_values(v_data_value, data_exp);
-- Evaluate number of occurrences, if limited by user
v_num_of_occurrences := v_num_of_occurrences + 1;
if max_polls > 0 then
v_num_of_occurrences_ok := v_num_of_occurrences < max_polls;
end if;
-- Evaluate timeout, if specified by user
if timeout = 0 ns then
v_timeout_ok := true;
else
v_timeout_ok := (now - start_time) < timeout;
end if;
end loop;
if v_check_ok then
log(config.id_for_bfm, proc_call & "=> OK, read data = " & to_string(v_data_value, HEX, SKIP_LEADING_0, INCL_RADIX) & " after " & to_string(v_num_of_occurrences) & " occurrences and " & to_string((now - start_time), ns) & ". " & add_msg_delimiter(msg), scope, msg_id_panel);
elsif not v_timeout_ok then
alert(alert_level, proc_call & "=> Failed due to timeout. Did not get POLL_UNTILed value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " before time " & to_string(timeout, ns) & ". " & add_msg_delimiter(msg), scope);
elsif terminate_loop = '1' then
log(ID_TERMINATE_CMD, proc_call & " Terminated from outside this BFM. " & add_msg_delimiter(msg), scope, msg_id_panel);
else
alert(alert_level, proc_call & "=> Failed. POLL_UNTILed value " & to_string(data_exp, HEX, AS_IS, INCL_RADIX) & " did not appear within " & to_string(max_polls) & " occurrences. " & add_msg_delimiter(msg), scope);
end if;
end procedure;
procedure sbi_poll_until (
constant addr_value : in unsigned;
constant data_exp : in std_logic_vector;
constant max_polls : in integer := 1;
constant timeout : in time := 0 ns;
constant msg : in string;
signal clk : in std_logic;
signal sbi_if : inout t_sbi_if;
signal terminate_loop : in std_logic;
constant alert_level : in t_alert_level := error;
constant scope : in string := C_SCOPE;
constant msg_id_panel : in t_msg_id_panel := shared_msg_id_panel;
constant config : in t_sbi_bfm_config := C_SBI_BFM_CONFIG_DEFAULT
) is
begin
sbi_poll_until(addr_value, data_exp, max_polls, timeout, msg, clk, sbi_if.cs, sbi_if.addr,
sbi_if.rena, sbi_if.wena, sbi_if.ready, sbi_if.rdata,
terminate_loop, alert_level, scope, msg_id_panel, config);
end procedure;
end package body sbi_bfm_pkg;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:03:50 10/08/2011
-- Design Name:
-- Module Name: C:/Users/BOB/Calculadora/Source/ArithmeticTest.vhd
-- Project Name: Calculadora
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ArithmeticModule
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ArithmeticTest IS
END ArithmeticTest;
ARCHITECTURE behavior OF ArithmeticTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ArithmeticModule
PORT(
A : IN std_logic_vector(7 downto 0);
B : IN std_logic_vector(7 downto 0);
Op : IN std_logic_vector(1 downto 0);
Res : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal A : std_logic_vector(7 downto 0) := (others => '0');
signal B : std_logic_vector(7 downto 0) := (others => '0');
signal Op : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal Res : std_logic_vector(15 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
--constant <clock>_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ArithmeticModule PORT MAP (
A => A,
B => B,
Op => Op,
Res => Res
);
-- Clock process definitions
--<clock>_process :process
--begin
--<clock> <= '0';
--wait for <clock>_period/2;
--<clock> <= '1';
--wait for <clock>_period/2;
--end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
--wait for <clock>_period*10;
-- Estimulos:
-- ----------
--Prueba de la operacion de suma
--Prueba 1 Comienza a 100ns
A <= "00000001";--1
B <= "00001000";--8
OP <= "00";--Suma
--Res deberia tener 9, osea 00001001b
wait for 100 ns;
--Prueba 2 Comienza a 200ns
A <= "00000001";--1
B <= "00000001";--1
OP <= "00";--Suma
--Res deberia tener 2, osea 00000010b
wait for 100 ns;
--Prueba 3 Comienza a 300ns
A <= "00000101";--5
B <= "00000011";--3
OP <= "00";--Suma
--Res deberia tener 8, osea 00001000b
wait for 100 ns;
--Prueba de la operacion de resta
--Prueba 1 Comienza a 400ns
A <= "00001000";--8
B <= "00000001";--1
OP <= "01";--Resta
--Res deberia tener 7, osea 00000111b
wait for 100 ns;
--Prueba 2 Comienza a 500ns
A <= "00000001";--1
B <= "00000001";--1
OP <= "01";--Resta
--Res deberia tener 0, osea 00000000b
wait for 100 ns;
--Prueba 3 Comienza a 600ns
A <= "00000101";--5
B <= "00000011";--3
OP <= "01";--Resta
--Res deberia tener 2, osea 00000010b
wait for 100 ns;
--Prueba de la operacion de multiplicacion
--Prueba 1 Comienza a 700ns
A <= "00001000";--8
B <= "00000001";--1
OP <= "10";--Multiplicacion
--Res deberia tener 8, osea 00001000b
wait for 100 ns;
--Prueba 2 Comienza a 800ns
A <= "00000011";--3
B <= "00000111";--7
OP <= "10";--Multiplicacion
--Res deberia tener 21, osea 00010101b
wait for 100 ns;
--Prueba 3 Comienza a 900ns
A <= "00000101";--5
B <= "00000011";--3
OP <= "10";--Multiplicacion
--Res deberia tener 15, osea 00001111b
wait for 100 ns;
wait;
end process;
END;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
WCjKBNXic0KXiU6pjAWXiq2LTkKJ7NE3g8L6OgRpnuv5wFja/4QAqU+5Vd1hH0Xxsc4vA0Nwy1zc
t7+LfMBHzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H5f3TRBy4525jkh1qIK2Qsh4q/GrtwJ6JVADtzts1qrfqD1bWIkorepAhRIvwZZByI2fH72x5SON
7IfG8zLpYUlD0Jk3QCBoYlUZJGWU6RDyaY2Rn7Gz5P5HI4qvPNtW766wSe1harlrLePNjoSKVhfF
4H7y4hlOm6KeJFp1y30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o8NUJuTvvtHQ//0yHzk4r3ROKImbnyCQ/+GiYKbHz9Jqc59WPVQMPJDi7618B5h2z5gPFkZLVKrt
oYIDayRN1eDG1k1+njjd5YRIb7DTMBqPHvFVEOao9N/cefP23vkwo+I5wXkEITLqVM0RI3al8o8t
AaA6Q0U98Bzdo+Tx+RKbiBIBi5x6wlOZOehaj7m9+DFw+updOQeJ5GNy8AZn7ul0lsua2cRf0k4L
gE8HziSaUr+ewcL1uRh7afU0No6kaXygNHGf/nl86AGwUs65q2nQnVCcL6IPPyXmKD4Bn/J0YFQN
o3G/KJKIPhXq/LL9z7Hr7LE3J/cIaba4C+44/w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
r/Xe2Ci6RnICLxvZgN4C/9rfMRo5L4MeaOlVrWhtom9UNPVoQwQaTPdI6GiUuDDQ3ElZSB7f6p92
n6ZoBVSL1eywG+ntCU6ZxZ1/8N1sV9CjSBxGOexweAx2kmsTC0q7hVe7rZnh/KLLizk+Ny6alv8B
v1zuaJAVY3QDTrVCM18=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BA7JOat/rOFWMLmTHh8DUAZtAhABvlT31S3WaH9xRoHVRI5E6pFuZ9+Ecgih4mhDcxdjqSGbeR/u
24jHGR1zNpOF5SfM2XuvRrQQu9K7wIyXwPdbsyw0LvXT1RLA9UeiqNrt0F8qGcaPOkn4zXH8hSn9
09AecPGhGA7p6v1GpR/up+MJJxlXdQp3HrAGMLNTw6FmURWGfU6ot/fE9/XTH828aIEuXPQv4VF8
6pJ5XDXcni32tirZKs20tbT3Ib0XzlMIzD6X0wniGigh4dlmtyYpx3VFbwNcoV0FuVHZukOeq/07
9NqJrMCoOA/h5LgKZYIh1HETLValj8txpIQaFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 72704)
`protect data_block
HvIwe2N34SZuMjy4um7DVGxuUtmbgThSrTNwoGwEiJdlisMhSbzJPsSLzQyCVPvBWB6KRKKsL4Rb
Vu3IRL7SYFIFYCA0Qq7GVWGEpvlLVdFovlxeEyEPw7vWI0vUv5p8t7ZuGAgwgUgLWZwGpb4Wj8Wh
NY0Ig3CnlqX1XIrtDI32CboRq6okmEybBULmi2P9k61yb7SBFyAc1svnv57UYSBqImh0j1AzkSL3
wa7THm0mcJ/gVH1/KUyrhO1il+aaW6NHEGqWVwo74qZ5/fcj+YIKKJDeGiqH2YcLSG5NjtOCUbnw
Qi+LxTROphc9BKH5UAmjqDhnJgjwGvr4bQeqYaQb4SjNwDzCodQMfFlmK0ro8aTvXCg9F65L6/fq
7DuZcatrpTd3yP/baXqApZ5wPBBkqViF04/WKfDRQMsbOlqNTWJncXWrzKoiXG4UCp3CPDPI1ADA
J4IoqjvRDyOwSbaOvd/DRgou6ZW3wRtzUd3XoyUc3ams6B2Os0tjPMhgSshCr76+8KfYp9hkLacy
Sux+oKs9jY9iRaHGLFTha5pUjG9spPLty8CV1wmij25vxNiEVXbEH22Zb7UWOtcj9DyaSa1hjrIE
x7q7kKY7XnPYCLZ23ZasHnZUjRcT62+6/6DN7KmHAlEaspJwIZt+DWh8A7U1vMtZHaMtbFE2O3Y7
iQjIjy6W6P22+JSJsLUBOdzAyiY8cghioSF+0RXrqzoHtPct4n98w0sEdA9Znpf9t5pA/uSvDBL2
iOyRM89wsiLc7lsX0sihfOSjqqxPSZopH+A9h9ue2/G31af2bLetZX6UsIMrqKKz3DsUWS5jxLx2
uO4K2xiZYATkiQj0HpfZu/5QV3d2HdSUaKtqpNfRz0Lw+5VcfWZFoyYfZ0TDA85K3FoSjhCOkt5X
qnxEdhrhvJwcdP4HRT3bFDNzaQT2Bq+0qvhCP+3ZOskwvkpFPCRCYfPKKjMYd5EsWA1ipnf37Blu
P+B6FwUT4zhffqISQupWw3TQLYLkxjkHEhNe+WkTmmsJZUnWdxVsov0XpzAcnl/DTDNtJ2+ovFuW
vS5MsdjEPyPduB00/YvmzhVscA84PYzTTOYmcWkmjYSzuwP+lws5WScc40P/b1OmM6iAtf4c0rZp
VvXlFVn0n3uvmJnaGn2RIeSQIa9WTqypLxpT+BZH6En9xteyR8rIYV1pxEc0ciBiL/jAV9n5T0k5
fvUkVJZTXX+rWbtUg9+l4nYvDOHz9+T6m88MPMqocLY9yLV+dFzczAowkeQ5QYwNFIzing+a+xZv
Pxkz++cUzgMzeTl06W6wTt2ZiUgg41n/2tzqrylGQeM9VqUiEG7wCrsr9xS5nQjWvd50z1JDlsbc
XZ4wTJNrOMBD0zmEaRn0Nrb5kYjGMUBglMp7HduoiDKKRZH+kTiXGYn5btDeDwJkymeDqU52kxMM
Ua5JylcFhWPU0/QZSOzOFQ618mpAVniy7VKgh8HzuiJ1eX9hUbnNDBqI5+sFcn606kPJ3RQume2H
+YAsr15Lx5QHTXxdHTywTQc96QLzVEd+ZCoDfLy4Ita230vNXTC2z7eECslwEaytH4C21b1sLtfr
5XqqtMYgorrrvtQqTi+7Gy5tqz/yOiJ8WuC3n6rCzNi5HVLxx2lBcmoj3ck11xEwHK50HJHCLs8n
JWjh7ZyFXcnG+XxjfbJv66Q7WQUu1ZmqFkRdo1tv2iY605wT4E/Ffc4gBG5uBhjLdth8vbgwz6ZA
RRtecix3HrcRtApeT9szKzg4hejQoo6LEak3BaEMuJWHW1+RpPJdNC1m3R31OxYyz8uOz6XTCT0X
37wFk8mqDzVYvkZRZMXxSSMgW+/tTBr9J8Ydd+N8d4SJIlaUT6Z4dEKdOx88H5kAlF30H8nMnggP
SDLxrazQ2jQmdjhLK/KZ4JKgWPpaiKEvwxmejO+E1te8EtF1r6TQWyBYuNPbEGkNULWhO4R7Cida
ludH6DOYw7JB1g7LfnsGd2QuUSkIq4hSkPehzDldUnXi3vT7fG95Y24Rs1Sd0MHAm2/25gr952+p
OEN0jULZPrgA6Wy6VgpHXNYAtOIJhXgWrp2Nf57JhizlPfOy1Pcro1lFHNWmcap/4qKYMju/R7K6
GlUTWoUzIjK19xBpBj057nLzgeOTsPvmAxpJnpGyFe2QZgFs1CiqD/9SPLFhgFpFvIujjVokVuQv
Y0SW30jzxOyRztwpB3VmYHYbIWtp7IDQkHEgypOUnIvYckMEO/2gfXT85ap+CcP2xaaMSS8qRK6i
KDBOyMwHUFSKKUvAG6UKRulCPv36152OGtsh1p+qEPYuHuYz2YHhQjAbJwovXPxLIU3qSHtBp8Q3
yc2GWHdqA3P12KMBh2LyuB6FLahJbJu2cTsHXvtXfHXiWrr17pWTXZdqbJPgbxv2jRsGZVxV9TyY
7lRyR8Y3BiPwHIYd+hXW2gqNAbPAXEHzEW/FLTfzU0IEh+8un0KCVxWV+PyVOjiySHksLyZvAgtH
XSphfYqOoGZedfxOcsK8itSk1ADQRdw/hHld7+km0JITcpn6XxxASzJAe4H2mMiuXzmv0AqopF8Q
dn2hMIc1vM+o30ll48q4nzjgzZeDYHU6ZVNTqfMAzTR3cKuj2Fl/TsX+MKLc5v1LF2njBu9aaEZy
X38BjLVxv2YO1/oTbEE2W99LCX/hW/VvpGmSx3TSAWbClged3p6hKVqvXJrGE6hSeAbmJkEBf5UV
9xLSafDYk7Dwr/oug1ymI4P2KbJKuAyPMOY94jd3Zbb08xCkTgPnKXNMGjsuU14Scf6ZQQldfv/X
Vd5uymnNA/wBuAfE0+w51MJz39YGeyyQqzp+ABKGtvX1gcyGH8g37lskc0GVG2Kuko4x+IDCgmOo
tdiIPZWz2nQhwO/4vZeZ2/h2k8G21seDc3LmaeBgdDtzN4AczOgKoqoZlxiqh9XbRUQbyyUVhGEF
NRRAJbRIDhE/b2bdPrvlDrU13gXfceRigKLhSBqwrzdvhVu1t5VHThFl0xUMVG6DXaShN6LFBfkd
qMELJr5yk73mHmfi48ipz6ZDKL948hxDZ5mRLxceIYnC4G6Zvi4LpBtIFUnvtTU5XR6KbYTZNK8D
pRDt1tgs/oyKpT3j+oJOb6s4chzqzeyH6GA3/tNu0pptqc3PDRfETxx4+wq1DuudmWuvmAZ0aPdB
NCAsKw/QOJZEsMuJ6HXwdee1iMOKoPzsdIeFEmNt7XhRkOfamcXv49MHg10jX/lQ67Kfni2xnQbr
4reqFp+uoHm3eA1qOVCwJqjNDHp1WaWtSiHKH/hXz8hzyxxgUDc8MWMD37Wdb3tjHa1nggaLwGLi
rSN2SmS4RLT1AdAGlDAmxM+N7fJMoeD9aSFhQn6SY5v57Om61C8nId5zRNy9nVQxwJehQRaWF8Aq
fQGUd25hYUrTkKGV38LTKfhJeJL9dsCGZNA2VRoL7OWx1ZWNkLrEEAFjBa7TV8dwE0x+1fzcErpH
xQ16Lsmia4F9S7CxGcAz2HfcKzcNN6gt0ah8bg8asyRNgbd8MgnANmIPxgkh6lyX/KrjBP78nBiK
BoQw6t0yb7V0UGt2AfFBXTggPoW4cj3iiaaBlCgQT/IgrUopBb9Dok3+aWBDZwCDQ1Q5iqjyJ9pD
KY21xP6p2sAIGQ5xZV1L8lMQoMSJUXS/K5kXJ5BvQ6Jk7CqNXhuxV/wAflZu2vkP1asiBCBF5Ye7
s0byJmevvnQTPWCBHdrGJ6pmcurXwFdBd0BUm9krKJX0e+ggOIDrS4m28IyFCL8k9qBJZ9dyclDw
6GivtqpQ4tAMlDUr9VIEb2zUoLC4hS79W/d4Cgf9SwFGS2vcOZBsheQvadMRMpZFQQMJ9wxCXEFU
H6rhaxKzg8E6iQkFYAtxSIxcu2lyfYMFk0F4c6+4vhd0c3Z6oLW4PTn5hLYEsNOeYUzWPawLVGhN
YKDfkI/sgWtWAUFNCWwBb/kbnv0VClgQkaLJ1R0tbEMZJjoLVFfe0kjclNs5uNhbM8wDvcSbMiEq
TMCnnQb8UtEc8uriFBmwvOEezo7AL6JbxMFZ0N1oKnDkST57UCGqMOCfQ/isGpo3zjTk7uDGuITV
d+GVfw/T+U0Dcy3yqdTiyg7NT2fWEHiv3Wj1KnKKsxTRTbpDGYCxP5wHzQI03sVIB398CoeG891T
hI0s6e3pDFks7YgWvv9M0a6d9So7MsQddPE1IwjB0jVYbmNLUkU5d0BQ5JKdQiR0SL0vMH4mvwty
KXQvW01pzD/nVo1TWzvs2EfoAMcU7hoIAQhSpXFED8NKcuPLR7GZ9NSqFlKOA+Hj5Au9F7uXrS3v
XbNXiGOSbQknrXKJs6jmU6iDxESydyyhvcN5SgmrdMmZx2/Mv3PFYJhH1PAvsdw7X+gHkzhugVDe
f4vgZ254r7LVyo2qUwGAGQgynV5GBWYbRWRrYn9i8bMhMeo5s5FtiNvKpebRQRB1jccpKDqmhdYv
HtT4onhN20B6ChVUOuSYbDCC4ydVkiI0xNIOkhL3NWhXVvuJBIn4o8ELOsiLTRbCRhb0PU/07MDw
+9BpGfTrKHBeXstbnQVzjCc4CttauKv59t1KcPKmkDN8sA7EVDXh454BiEJp8VWbHqonp7dqboBs
mqr50B2lpcfUzwbCmEVTdBiOyPCVKuNkVFfcMYIXGvqt09c+7UHm0yYdwF2nlS8W+3j5VtpBp7TJ
Zb0xii99XhH7QE2CpCSj1x4he0uNUIP6enQ4xpqAlUTm8dy00jBDayQIi5em4F0nc2qcFwUkVlkO
z27S/a/MgSzOFp/fio5suNN0UOJVyGfEKBlwEFkzYFwcwgarr9niXRezbvG9E0cNGHSGMBy3t1bi
yJRFlyuB03wUPi2NY6zPHn5oqFhBkA6y4jpeVjQuJW9CaJrYByef4li0tZDyRjaI2ySPOmtgcSt1
Bv3rSwR27hQ6+3cwYRmq25ZUKrY3tpWjoUYxb94H8LuMKja1O1r0MpaNJ6kUBKP3LGgr1YHHb7IO
irtEqdKhpGd/Wl4Cr5U6jZlxN6N7WDvkP6/n4VKyEAZa2RwNRP9DxlrPEQDvcc6nZ0/lXMJpBuke
XbRfW14uzqZp4ol3Ktw9QDZqTTXmtdhroocX3oCm0E/9BIBYx+V6XKjMmeP9SVvBNFMC9prncNqi
DpOVWEpTCZvVCyLiRJ0qx3Vyk5E6jc/hBPOZKfbeyY/FIgTj/4QKptvZH2Ptz6nfMcfZdh2Ucyq3
We53hmCbGSYVLvUzFD2fEiVlpV9tSFm+lBicoyXggAbTbNnWyMxdI84UpShrNB8nYi/EfKSHy6sk
QVc0iPgqy+lwyoAjFcgNfPmJViVNFhgAnhZhDY1iQuziensvnjPIO1AGRHoZPOvtpwubJeUM5jMV
6OeN9LgeJ8RFRpXnkQv1HJlkVuo4wVPuvEaph7eZYesqM3s1CX724Pmyq9MykE4zMN1ow1YUmIJk
lrC6txSyBg7OW0n7QzRlAKfimFh0SbgZCXYMG2uvsupyf6zamMXHM7O6y3zkB1ORd7pIdCll/3Lf
Oi9YeQlNJ2o4oiljEPInuwhktLGjLpH4fJ+uWo4fvfue3hCWesgTFk2NmwT6zGeHnbSSu3kGaVrG
OX8BLyeoG0CMskQCw9YbJRBOHtI/b7dag5JRUxqN4R/bfHDkpfu4E/Ik+x/aF5mGffsZmE6pVK/4
k3M3jIlnIVHLXXQyicE8UFo2c9VJoIgR1Y30U8vRzK2d0EKAHCKyut5hKp5KytPVaa9QaIvEUDxJ
8ydYsQxl7Y2AScybaztNKlyOOB94W1IXpVkFsSEOE5P2ICh2LoDF6qk6nYsOwgQi/QrodM8aA8Y6
o3EuacF+HCN0A45oiukQN61HXwJ0qxHKVJQjYs3HZSiEBh1rAcHyp8ylj3xUyEdbKmowB+r52M2U
2a0CgPGtlwyqFE9qku6kQ/JC18nhW7CZvNyUmbKQe6J4VIF1G6mjVeP64ItH217LsQu+XeQyZ2Jx
glXpXmZKcDu0CCS92Jd+3cmx7En+WV6A8x7OJP4KoGrYnKW2YGwZTVJoKoqT3RYp7t39QHBcbjDd
96iTZJ5SJfrVbvbIA2NMmXcYyL1jmYnx9oAr1iGKr4/zQ+aCH/Sowet1D9lBI6cg+RGcSlcy+LM0
1AiVzhvLbt7KOtAYZhux7dAad/2+lw3IBzG92c4FKnF0aMp+iQIn77K4NPUwSjR2HfP7tPmjKST+
d9BTe9YiGJjgOe/5N/eZV6voCC1DNPR7yUyME7QuhfXMF+VkFfwQnZLF1g2nZeREbCjdJaSCvmt+
erBvrerL0U/GiGDtZpBWzBlbKL6kA6hyfxppJ70cPoccfYQnYs8QTyFzaYZstGZGNGcomQIUQ/Ba
tA/fBEC8472TOD2bzIw2/VMiA4YHnYQYMqLTkdi5Kuxn6iyiUDYJamg67gmyOSfVwFTF3iuc5L8u
SGK0n/FoDZYtFE0Ip6owY4tt0OqoJhDWIzlgKUhHoYsuO0rhRuAwgZHmwCjyH85PVkUoALJqTWlK
mHc18K99zEuFST9hhrgUZUdHxULXvy5pTNoTvfFZ2IYvmiX+rk7n3noVKgVLDcnzCnjKLN/ShqyG
D5GR4mrCP/rxxl9Uu7dspgTrEkl5FfO423Y3f+9iiFYekUT1rEmvGMXanhKsgCQnGo5yAE+s6SmA
sSvFytmH1lNuUDwF+8L3sw83nU6sf3fISSEW32sXlE4zdgXje6kEHoKVShgy663x7S0R6M0b5CDJ
ecveH5A7XW8YBaOtZuAD5KA7n+ejiYi3kqrLBHWEVBKVty02KyZ24RxC/UkBE2q7OpRQI31iCSFq
Ht9ifWl32SSmycQBc/pyAORd81oyYEj22zvvwYS76CICzX+B0ONl0PAAZEH/ffwb5IkHX8bFW9eC
tfwXvZyyrpma9/vGrfoc74YNALRYKZETKW67G4mtfyAdPThR5xf8EKq0/xtDQvDbXMb97npFyq3T
bOpCoRtMgfvz93JiQfC0LMpzpCj/w8RpP0u7jaFjgIIy8NiN7F68kP0HtA17COI5+9C7AU4iw0H/
ELfzjUg4DViEtMlvnL/D6fFpjtMbjZnwQ82QKaWy8FrWA/Je+elbdepn29k3pJe9aKgxAVd3+wZE
kyV8qkCaYFb6GCr56bkD3N4aI4GZ0MCB1Dgvjyt63otTqctSd2uEsu6IW7EwM6SoqB0Ni6vbMcSk
8Ngxtg5HPXK3f0EHJZNxdOOEG9+J38vjXqWhCyUGmqhCQz5+uKS2IUKF3YIhyS1qn95RuvBm7PYT
ehuDzzH14/+pKSdQ0gHAH6cUikCGtKWGUFuj6See6jywBv2C4Q31apQKA7/rvC97BIi2paggmgd7
iNpgYLDTty91dv2FkMv/DP5uDjTykeqSMj0FrOqsMuvSPAXoFHKBecKsDyxK+ZCNzdOhD1Q5srEm
DOWCRK5w7tzT1RB9VXiim0/DqFl0P4Fs+lJYanN1Qd6fpObL9IQR11fGp5C6IutXVRBGGn4HNbTO
5P6NpCoByNHxfZ2ppans4Nz6KsOmdfPCQdp6UVK40Eu7gtEmn1pcVqkimAlZ/T+bcQQBIkWCdMgR
sEFrQM/uAVNbVGiSTqnzDTopXsOzZ680K7mdfR0YwLKNt9x3xVEM9vhzJmzln3mUDl58ldZfLgFv
WILmz+qw5pB/sQFy0jkQyPaQjobPOnkiVbgQkvQUD6mkJXKFsGQJ24GsJUTaYrEb4EyALETP4o5A
f3ytrUFDHlYfuRxz9yNU8QdYs6e2+87rKAUAFg146b3hL3afUat5ZbU6wa1XwP/970AyWZTf1gRS
Ct7bvTvckA42112OtIQfq7Gt+DoihOFVMWb4wyVC5DKXK+QBBnQDVUE4q0iJHl7k122Vsrjs9+id
rCUfrRY154uJf2SuBplIL4X5vECnLUREMpuqnLZ00pJT98IyCPMvJtQtus+gshp80MgdoTVxb5Sw
Rlo/C69GBnz7iRyk3wdybLCONx8PZvUjiG3DLLtfXULPKRUsCmk+ppgQjtvKtPsBUyugdUnekR0Y
gozZEiNS5mRvpDAb+AVMfLPsI00mZzf/eUDD9RFgJnnqQEesuebHJYduD0x7m24nNVoxfZpLQ9kr
Ph0WL7tuP7gWeIhMYv0sccG+XrShoZ/r5M5CJ40CmLbedxT953SGqnS0dZrtXaaeYGO/464k9waz
KGi87zDnxoRwA3E2JXVMIhnTdEBIcqSA9kmWPnuNeL/NvDouPBDqKNtb6W9I3NbuJMqHZ+EMGAQ+
T0hfH957EsVE1dxOTvsOLqnWLkNF79aAuLtUPKrdTM34STEBLjhPfkM0CxTJVRgXfI+riH4jDJPp
J0yTF9+CZ4DJ2Pj0SlbcGsTLalg3X06sRYBK8G/7aB3G9+8N7XQkiRndDvNLr8ayF9NqpCeIigjL
u+syGsEHU9GCHsLjqLfT0ZTxJHDT9XXqCgV0xX3E0oJY1IMojlgqCdOS+cWwzMzGII3zlQwfvS7n
KxbW0I4kfhcvqEQofZkb4yHBTQx6nY3QkzxPDW+dFmmW3VrMJofveXe0uQ0QE/PWyNNj/Zcud5LR
SiyQNC8gilQU5RRTxUNcZN4SVzFVa5go4lhFVMXoTHaCwezMz7EzxH5vrh1nMAbaam86h5lqliGP
19k39GTRg/iVKmEtjOeQ01La13ZQLdp8Oy4SxZd872VJowdVjKOIQzyXy5di2jkiGoTsVPMTGRnW
BSqpgWti/mhC/kTrmTwrGRDB9oBvNbfwr3HSqcRG9CO9R4Px7V0akzBF077ge2jhGKYwLETTxqXN
fzLjFvQd214Vv9FuuKjwHp01UpDRuR7gVgKutBPzj82kVbNv866v1YJACYdkqxZTp2dwBFgxhHZh
sQHRC5QiEp/SiXZEILSROy048rh906Tfm9QYFSNRKDNkid1VCGimBOPjgS++vLmkv3h7eRZtFX2M
iwi5Or4A7nCz4TjMngtQPh3Ll8l2EX9uudfpQVF8nkaGzZmPZ+LoPAolpIXtiqHvB+hrHTRJ57Ic
DruA3qYMPH3eSAG7Xr/9wLgS9Wz5FwvGu2kxV5BT8vd3fsZ94PYTLcfRNNfymMlp9zrfQkOD13wo
/E6PoM4fM2NhQ+7ztx1YAb9bJ+NDPPnC2u9ntBC5XZZ83Xc/Pyr9pVShrd7F8AmF6vIygKTGO1HH
3hM3By/7S3fEcq4BtOkGKF73R1k1L1eilN8iqVlseaxmRNF/WRxLWcM424/+PHSQfTpdRDfaDfoN
/nvCg3kmY89muYRJle1YRH+t0seGJubaC3jUJym8Z56xhIWwwxosav0TnScVgUU/RZKMcVcNkmU7
a8WbtR6bGlLcyIESGODlb5734KNejF8BbFj+qNipIW2E/+W9al04m6WaYhXxhpGMkbEnpZC8SrBi
dpBEKLXrio0WEkwvQdgLQaDJbD0ZEbeKNZJeAqGS53N7SiKImKqlj+wMq3Bgc0HbeF5Y7oN7IvUO
ArNFhnHwg5gf1Hnkqn4UN7oLeoClUSTkZ1tSibhQVzZThO+BxR/wEb7qNLCDWv/MhnbHxNEghtS7
HN7qa38eHjYl1H45RafwBRAIOyuB00ipyboFzSPVxtLXJRt/kTIa9jYw/HeNrndMhsuSgpdWHHRS
kcTOg0Z1727nyFFwO9F/hxpDcPrKK9ehU+1aXft1dUD+GHa9d2UOTJkqBLfqHOTDUuhqYuzvfCsY
A7Xo8S7bw3Y5IpnnjYrEf0MabgEQryAjfXe9NJfAjVGkBsBqU5S4xFP9tcw+hBNRZZIua8A3Yvxq
RzHfXTOotj3FuW4oKgyveA9kR1uWHYBaYBZvnAWFvkt8LjA8/oT5WxwwPE01gORgzy3nzDyO7C/3
LV5TY4zVOdbqTYJX1SvHFzNgTWpMc4jvJ1L8juiGRQRUWMxlMM6SbL7SXNW4XsuKmYR6cwlzqUiq
ARd7WUqE14jqt1JqGtmsskzS74P7Li89ss1fAUONlhSCTmgy8MIMiJDuISWKh4gx8AL0FVNZMihN
NU89dk1FgXtOSsmNPS+hpc+oMr/RLYVSZ/xLGVMgjFZLDP+/2L+G/212xJI+n+F79rBhGTlWEI/I
3AShC+Y2bmmwc8QNP63HDQyKyeYSFs+z4lBEH8rccVkFTsG61aGUwi6WZmqZHB4nnRrwwDljk/mb
35Z+9QnYMLbV7sTNxR5XHqKE7CWK2FyQOZNvNkJhXNg456ciDZaSn9h82WwEtJFiPZIvT7YIPM58
ohCPE+rjrMvykD9HxwoGfhOec1sKblJnb6RrNM9SCcJVs9rsGm0X+WYTA1wuThLsxbu4Zhdr2tBN
EaFbaC+z7JEjBjYTye2/DsW2MdT956+xLMQulLXcT/kXJt9UVgWsElxkHQ4Ws4xdmgDwx8MzVP6z
yncHGkHsAVqCTsCSbxU/9M1jsZAKFTgs0cDsT8ST2q/Axu+e56SR1KrkFW4bCXSg0rQFTQwLaXdw
h9/lmMkolwBFKVT/8tz6S5EOKca1ihMBTXjbnoezPGzs7xA07IJ0hh3GX4hm9hF5Dk4liJdNUWaW
AsGJhKbQAa35ylAFPyV7mb3dwU86urMJUa0A/6Juqn5W0z3g2Gng1Mb65SkiyO4w3+mHYvql3FcC
ETvhSdbSj9Ib2mUxwRPNEywd6jbh1zsx15t/iBP34zE2kycmzNkaPYS9sVT9LQSKvAJjIjxGZdH+
SaYGZF118GqrHYuFLIBlthjn0+01ath4HLeoGGB44TLnZr62ngRdAETBpTv76r+GltbBsq52zp4j
qqLWR/U6BDcYqGh4bucUgw8v+TlYMrdhsuTPzBxTIz6Y11OxSkZCsM9n8IuaVWaPCoWK/LjAD8hO
w7O5YWfWoz/RIQwsfajhyrOEGvKq1uyqg+dMd22jIDSvmS+udV0h8PZ/GsRevOAYJtZfNApo94Or
JKk/3OT71MMwiDi1WyM2C2IATUqp+GY6J6E7UJq98EtBnD4nccODm2suipwESPSb28Abg8ld0EGX
UKDUVDoLRBvv6LXc7iJ8wSipJSL/6iqIhfRRaLZJ8Mv2wMiatIRtou2qICTZYwYVdg3io8HPY6uc
JxRav3TOUShkRuHShCtFwUQDZchEqHG+XxVFkzo4z0xhrMNYG/tZ9lMsFG88sbytfWoQgOxZ5yol
xghh/ARhf6XOO3lNIWSucLcslRt3O6oN+TyQWQ8PwHJcFxkZEueucIUyDV6U2fua+SqSrLlakaV6
O6+/siur8wwmo0m9CGPPFZsyIkDjhtJ3oa+NOR35YwmCGs6RJF5QlJpOO3OE/FoXHzY1Tc2zwO/5
hnUrLCuUHL08AQ5HX6N7rAvVBp61T09ojh9Vw8uUPz2zbqa6CXD0LwfJyqUVnhh80IkNMKwtD3b5
D5LVOWIk3CpogLyY3NQnjb6FRuhTZBO0sH7MtFCpXBtCVZFfGkUZN9/z8hmsTdt6lp5egXcGEOWg
66hDCyuYepxuRiJ2le3SIwBOL1GHZPp+o/M7DSjjdZmgQqVfd7pdwIeolDdzuQGozJ8CNtmFtcXm
yZLpi3xZCeMpgEvOQGVk+QglNhyUEyCBnkoGMQcbVILyhsEYCjO1r/aPu+6YQRzSSIJVWb0r1urB
rOlXry0nG8vjM0Eua1BKwZ1OJU8TJehY1W/trLzJKdTboNyh8DebFIF2M/6SONEwO2y93Qc7JKmw
SvP/pZ8L3TlHJ8IeqHPpF7tX8Syf1AobFxITCFo+pmHis1oP59A5yCEEx7npx/7cMw8XHKqSN7Ru
GKg+9GMi1UxyrD/mvsdcc+l7s2yG/GJZhtbeHUeOiNwJPUwWTleYwhqRbsybI2G20u9gNqJCzN84
fEyr6bqxwBrXlYAlZrFd06RZrdbUOwPzpT57GsKs7eMWIqp0zXLeS0wHYOtTOXy0nF0CoH/vNOtC
BLNsEr+o1ZT38xBKJmv/cDKDJCGM72vIVAxwDGivnvGO/bniWPdKGZx97gYn0U9Pw79Ox731zl9g
aQBrx6dupt9kZ2sINFU80eu4UdkAdsUshP4Ddj3FoYnckwFWjbC8yweJFxyH5lxQiMaBoxCNT5ad
LdXWxs8IBdsQQFbBphF1/RhFQdO+VUONlPiJRSAKMZ4FLS2yio1h7OFZX3BVmufTYOtmjN12Ftqf
HOMQ9UZxGxrV06GgcODlMlqjF6Ge2oYcdum7TgWaLh4wWyQOydSOOUI26tL3C5NDknpXbTC1InhI
6qAXR1WDG3YIEDy+SNq9AWPzqbPBWB1aQt4gsmLIfw9eWe1UdyaKwsIrrdleJ0pHsVirrvMiGFUi
0dfwiSmnsbdL8DE5mJualI3ug6qITkGNqqe6/+cmxDzmnFYLNK8tq2eN9/Y1Rbmm5+VczgTgkeGA
LCVRJQqI3YkaXFDlKt1ZvQAmTjw2iU5Q7o35uG29lCilJfzX5rb/2g1oAG8FM56N8Ntb3a6KZW8X
8roMuJj+01vcvZ3YUFpzuZrEVGE+nAbkULquEcrkCF3+fONxAuQLGt2qh3TKRwk2qfwlcgVLao2m
81fhe9HAWgF/pAkzxtSxYzUP/2XS8Om301CgZQpFZLhzXgTqy4ZE3YnmvTLgQaDWUWbhYynF6EH/
2W0TdRA4aZATgBRuC8qtG0vtxDBgt2owVRmFTmwSVDtK764Db3quTQlMfj0yQNncZ+iM93MW2eCt
ZiK/R9TWbSKnXy5LFDLgQ9iShJ/62l4TcmagmzPhFIlSBp8BlzfDwGrRkekJTx8rMMw31q2b2lSj
VcItDahuerwTsf+4vQSwScrJ9L7ulGaustR3do5/3Z4v7JKTyvFSkOrsFP9ckJ6lmQxlPgfGaDWH
t05GM37syz2VdG1VvrRbcC3JHQYhWb9EbKsKEP99xxdl+//CPlW8jouqYFl6Oio9wFGfEN/KawZB
NrucvLUWc/PS1p+lSb8hZHIdtp5Sk3jmCgonyZoVcU72hMBo5Ia2T6zToa4WoyvW0l/usZzLqRoD
CQV4WuDjnQiAVjczj20wPNq2o4xRiLQgiN5MtSN1vuJLOjSowphaK/mAm0C0u54nEuejSGFSvQF0
FBD2TELfYi6vP9tyzB5iiz4JFk0Twmu9cv7C1iI9Zi9Gx7/n13n4eH3beQLr/anVfPoOtWtvo/IQ
1933lVQN1vovaXQVn1yBOUFtB6qh2yVBsyHCuLUryFlh+SHlweDjjqAXASGIaRpb4zILanLUuqF8
1Dx0midw/aUsKfyRYKZgHAiRXkd1h84apmZa5w8CfO3WQUv+N9/9QVyCXsFmaUvyTGQeE5Ag5F2+
kOymfKmYZHW0Ivu1I/u2uZys4eoZsQGcIm1jqFGLCakCw/CwzdVtcuqdlVzZX9JjtnR66otRgqgu
dJB7gtXaA0l99oaxYDH3gKXmV8gAG6RBgP9garB9JtxRwfljxjWV4a/s2om8ZGiHXpRM19lQWBYO
/uVCyHm6kT7ZaRAY0Hc87iIGOMbhViCNUw9KjBRWDKmN+m7CGr4OwaB0EiTl7s+XLal+xC69ZlHf
3PTrbd8dEkPwNZw1ck5EJYNlMpnAzBiNNkcHS8JpYmUZGYR9s24fPWDnOVv/cYOFX0N/+M0kTG5F
NUgo5oVfAc09NlSx3EUuNwuGDvzHZ4GM1V7F+ZaLc5lfkiyyQMU+Mgf8iQ5927gWpA+aVYgNV2Ju
OYcqueUy/bCrF2K2XyRi/Cis73j3ZS6uDPxEP7LCSlgurHAtE85OSj4Y7LA/DM3Ov9pqMJslXEX8
hnzd/8fgoh4B5upOTn2DUGNw2jw9RrIz/dj8X1+DzmTwdsSc+ZbzOO1zBo7Qgh+iP/alcP6v3uZi
ZXsJUPBfXXTldjHU0ftgW5wQduYLHEAzmwd1gc8FHkHJDuIZgP3XkjMh2owt8YiEgC15EBZstDGs
yd3mVlDuT4dUk+nd5ZWoGVSlZ8X1suxJ+JLmWE+tss0fkxaQdN+87uxsLXo+Y6FveJOwcS4ERkjw
VritymYicUjTE6bfaA5F9pfhX8/WEvduMdUp0afRRbjm5bdfoNCpA1VEQsMAzDCU7HVWFlTnvhrq
eZcQmxdP6SCkvJ0qUmQ4hDZYLLKn0Zg/TyKhvUo+PuHLY8gJLwdMO9cIuOHjxBWENhv+hfpn5aYk
uKMfM4dojiMtGYKbx5jhDgdIKF5BbvsM1zWsfb4q6xPNdPzzUz7P+GoSTeZ8JvGsAN380+D4ekcv
hjvJ1l4v1cz7JJVQgw80KS59oMIuLgvEz6hu8Jmrm/Ehy/+z6ZoboTq98Ahr+FRSHl5rjD+l+s+T
JjoXjygL7QQb4Rh56Y1y7I1HwLqOaZhv5JSwpcA1B3LMpxJ8qcoFHMJyjd7j1vW3n2qYIR1h5pkp
dZBEGza/un7B3KLVSJVgYuNmZYAy8drbcta/9DMXvqK148TVvKK61rNymsKfHqh89AhOp+131U7F
ZAfbFt0dYiUUd3/aBZQYijOneJpAn6AXxb3TGprdEM3vT6Vjh49LbCz4/qG3C5Y/UacERJ/d1Da6
9SYtec1mEWGa6rSqziOFh+WPbcC+xD7d++o9jLwIbanaiheYuH1upZDoSSZliNYS6Nb61DOlqfkv
lScz+UEQdRNSOero+gQnABTHjwNmAx9wEXZPnKnOUKE9W6ez8fPAct91JZxf904NDvg2M1pAGHDr
9cHbgqJIm7Rtz6O7GjIv3+00KsxpUZmlUfKNq58pNnbiuqZKFdcQjIv2UqjVqfYBCjop2nFpigIS
QthIhCJat8ykeSEJMBO9JokaYsl+KF9KSePP40mlIMaE7TbzoyGkLwILwCYgrguL6mMlH7B//Eay
/+KNo/J/rgxDQKcaIk2TP3RGelRr4fX2eKSt1bBeiv7C+iJ4434kojza/WvERtJJTHnGEbxGnneQ
Suuwy6WKC+Jp/7rQICc5Le7L4HSXouSsEftVwaecOllWq3aTjmMzKgOaVRcHUzZHW4BlScYQaQxP
2ksh+ZayLAHK0RjGxhcfybSroFv6xtKvnts1HY5vaEHFbP14Kzj1Wsl/sGw5V0P8b467YCxGVRoy
m70LkRmSKzX164aBxVCEzLNfMEFQaQLPhl6Cpi7/N8W4H300hF07USkRPWXs6qgEjFqTzYkq5r6f
0jTH18JyFLkMnSoA6eHpsUveCZykkEN8Uk/3fn9cvjfnI1A2tdhcv8Qle0rFtc0v9VLOxOSx1jsY
WrkEogWk2EKy8I5r0RNKCSzKIBojk107lomVTwBpyiLtQtGaY7w2gS/S69iIVItovR27ow0rBLUa
IDbSRRTn6Rg7iY1pcMb5QUK7JOd8b6MEBYKqJIrtdYwG6zzxMVgjH1Ant+/0k0Zfg98g0bDyUE9+
OJ0T5RrK9RSUg+PvZ/iJdw2CMExZ36LEVe46yKpjAA3Y8lKDx1amkGSIpaQSFqL6akwckajxSbfK
0uz3aHeemj3uErsWVAowP4fXyMWOsIkS/EUvbbIHLHqS3sKfiK8XlQYRzYRFUfY9ipnTqnjFowCT
beWZkg+03FuiktXr3A2S+lkblthwvaAWNc1qA57dnjz/g9/C+cBPJ4uqg1jLaRILBonmQashr9R1
MCVtjdiNsQ+vMRW9s1ItUqpXG3ZOBS/yzryK/a/lKs2v+wtXgW4lyKLwh+XSlVsxLiS0QTjUvcmG
ED50HuOn6g5d8IufBZM97BF4RZn7A/DSAEICNIVYdD3qJd4GUfVPKxVRUk5uDTFtS0w94+Q7R/ei
6Oe8+GjhQQTm2DNZELkuUJnF5M4POH6/x6d3US/+x7SV27laI2ES/6Cy967wnMz3KYatE3Y7Ov8S
hjds2RCvr0MZX3MtNY98lSfSRzAcJefTDUzpHIDptz8wqdqv/v+vhLOsCfxzXPZOAJ+Tpqul8L8v
Ey3Bq3kGrpPhtIq3XaSOYa26R++rGOuWFbWFLK23UW+6gu06PMmdOoyAWhdnYA7pREwOP1X8PhDD
U+EoYwhTwwpEU4okeOc/Ikra0SepMq8C0QKFUbQaOCv9ERrb1USGVEFtrUvvlsNFGbpZE50FzacN
UHW7pysUicibltfmGwzx6we8r12JdfXV0K4XpbPqk957C37sFhxVK0ULKjfHh+ZWgmAbNUkrMQjF
0Yi1d0Z0kd1pZjH5uI1ZlNdVB17PNLDx7LPnqTm5bMJLIS89KloE6yQxWTijvWoAf/5uj1nFA3rq
loxUzqOjtCf8kT0QIRHQDs9CTikOmSkj+GA/6p8TH29rRks4PMVygV9ot8AlUvwxp9fbGFqA6Tk1
2+8btOhQ2GjymEAfi1H7DRLnMwKieez/7JsFn2Git4t1459fJgA2XP7GE662Yv01DqVRdLAc4hGL
QdwA04AKLm6l60dxY0YrsoY0ESAnvN+4bRbY3oxMWzGrLIUkz76KrhfDrmFzxG4d8P5xzD5BmaPN
LQYP3365Gdh2L6j0pLxoKBwk7oNR1SMqHUzAVf2g73vBe/u4iqfFGgAvFen6R8Z3nM47KV0yj3lb
wUkRgySU9DOEkczpBZuDp6np9dknwsi5GYq9ln9DO1zyaGw8CgQ9R5Erd/UOqtD/2PU9rFGLjv2n
jy1c6HpcQXtrhQ1OrG952e+w265V9MjSGdC6Zcg68wCdg961u8CwDgVCbNy2klRMiFgSn2cQbEXj
JnHHn186n4J424sQWkAVc3ys0oigMMaI6d9+75R/3oObaWbv9xiIHO6BBEJIE1AUyFShqHPQZjwO
+xB0vAjZGA1uLNaLzECZlRPgiUh8qUg2P4wlEv4NHWdjTcYBBerbiJpB44sx7lfSxxAgIieYRWKi
DC5bM/1edUp6uHuq1duMBk7ehg7Izx5+JnMuMAtDoIoxY2zfnoNYVFUaLg3M+BWT/bbulOabqi4m
xjF+Tf9/ZpNjaOt3GrKOH6mnBe56eZ8uVEvhyYgvXp1yO6UN2GGUs5zN70Jr8HpChdxFlXrC/sM7
dNrg4LDJxfYNNijKKrRZZmVP8j8iXNKTd5bEDLEGQmHxknFVdBO+Pyc7vNjpcFpTPeJb2G/nG1gT
Lo6LpsjbVkgdA+ldPnHgyPazkoI5yHEkvO383S+cKoBiByv9MwvgSJhiBPeYzdstT1zXSmxzJLX6
bdtZs3uMarqZpsjf6gqAqOo0akN3Yir6O1x58FLyUxx5DPbEyHov+L6N9hZN/tG4WKOOvLd4ejhW
fZjhvOZRvldkZIKwjUHp70xSh3HFKHzIwf1Bb51vPgAGrhHlzq9eK1+2gAUlFgEbKBO4ny5QfEfn
tX3mVO2FvmTEy4Q5MpIm/HOtUDcfyixYnpaf8PCkws4ra7TQJb6KPyaUXvM/BU8pZ7SuO87UVJpf
oMH7tYLYYJ1H5jFxfsm5ZD6UqbjVnWj2MQi+fR60a10QqVJxGEtcQsFmlWk4vKZTATPOeRsCO2As
kBNquL8tLyX3ddH1D1N8ICptugLv3UUJ6nwV6wi50Z/S+FOP1NTKc4QYUUPy+N90TFG7fXYe3mE1
ASQAfYyEpNXy4noQXi+AVrQ3OcFFkA3CBjJhXJByL7UAHtX6KsNM53BWAvOM8zLC1hhVxZktJm2R
TADi7xb59WyI1a1sYpTsASx08WurNnaCCBxiZ7tvmX/VYk3xhInU20SC/h+iF7bJ7JLq/aXg2DeD
R0vdgHUcLRmINELkgAQWT0Q4F6whDdx2FzjEW83mF/U8mF5v01eXrILXAxAWkvO5N2afETrj26uB
jSIyBuA7F2AH+JAucMG/H5Oze9ZrqahSE/Z2lp3ZmIpv+7c5De7N9cD8x63xPKiu1RH0N6d0YXdZ
O1ffh3qPKz8XU8nFqFhI1V+KFUd6iYA4MKTDaOpN3NFnLPDt0txhV6bFaDPVmLK+TrxiZDf6I6QO
rJgw58hrioYH0bLmGsMK33js91ODLrAzxnQ1isglukpxthtxV06H3ZO9nkBC6CMhye3KONkgwStv
fA2RQWgNt5zASqzIORbq0Rnjjia1LKEwBuB/KIeooVWfaqF1OvnEcepNYwu16TvuO6VF+3SiWA10
BQPm3VLJF5RIB56stcmAbf9pL6oJmYf2PGaSg4/vMgkAlyqhgbtLNbERwqz0/ynp1DbCbfhwhZih
puYJL0tNYIvwyRZUnuSVOmZQTFZ/5lpM9H+Stu0kk21uJkYdiJ9Dchi4ahlkYgcBdQd6PXODMuY0
2MR11RWe962OqNGq3JzQTaNM6gpB4vMzEyoWAan+Nb4WlXLmr77KWcfQJKJIH3/ZS0oyg7wW8Iis
cnJJceAUgKjw3jzC0L5rnz6KOlK6+aS4W78PJJSPCUx8cy2vsMs6OP+pC3b1cIJsvK73It/tCOX6
eiqHmCPjDf/UStfTOD0oBGHNBH6oqMGaxv2CKnbb37khPUlHHktI/p53JlcNGByQOBWX4qRFn8wJ
UlJSOiJ1+dEX9P4R9PBXCcf0ZSLKOCtUk+fytMargtrbmeTnNPxzVPJYik+Uu8e34ew6rnbBfBNS
wtwNRduJUseL4WZb4h91LYRrdny14zy+0foJQWO5exdT/sBmLa9YreWHoxTzBaDOW1aiWe8kaCaj
hCBioJ6MRB1CEInSTJ/Qot0hPrS3trRoZoG0FQ3MSid0JXZ6AwR/vjRglbwWN1voXg/sDfk8vrdt
max+FlaKcKazR+YPVeJcJmyArkvOfrvuK6Ym6OSMYQN1hfJwhaQSoP1Fiidg9VxidlgjhEEi10i/
bh+/8VeouBIfxm09K6XAQeF5h+VwxUTJMSwYNKB8P8eArw0F2rOIOhhG7y3BZSm1cQ00eewE9fSj
+oxFxppyP2dIb7qNkRaKnCRyt++9Kzn0iIRf9V3ZGH1c8xq2fUyEHlE4ICDmrBPffx+We1FWubdS
sc7tLOIODv12STJ+4RXPXTXUXCCK3ou+wi3FY5eL2IPxUKkOLzHu9hPO3864dhgVauDTMtelXIpB
PqIz20iYWpYDGOuXybvQtTBlFgVXmxCsuLnzWE66y0HPmJQjkDIuUTi077ZYNI3rCO7AxZJgW67o
jR8yr7M1dBOUE0SOCm/N+lyDOFw6X59r2WO89tRQh/2IMrDyK9t6KVnHEGasElGoYPwf9VpMzS0s
V/MkjoEautvoOC2RQcO867Ni8qt3X4b7kJRjqoi3rA4Dqsp6XBaSJIAvW1u8IwCj5zfiXFp6Q1pv
toz9KLLJ5yQM6zSwlk1cXnrLRJT6GZPazFWNodeY20IetcHWpGxFNnu/4Lces0gfcmt8COB7Gj6F
ZI2hfkOteUFWkMQu8/yMsWy+/SoCueSYJAW3w8wTVMIUcjkSBa6Ega6oY2IxrEpV3oX5JDe0L8cX
7WhnCgm66Itie1zcz3F5dhgPxjh5idKOYctfNro4EaAza1fr+OEcQ8VGPyyugGEEA+Rrrj5vhf7J
twHBBottYF2RM+847TuETJ9YWf9KRrA5/VSRB/zp/TlLSNqmrCnNLQ7gc6uozV4cirFbMaChiYvJ
xvpQVlmjzAGdGZTBaaJsZyuVeWcmfnklvourPNRFflfQ+n4Y7Awx8YAQOxmhwh4MikxNNHM4egOi
7q4okmE04QzWKx9Mh+q1gO4BF3TAsBlDNiozGHivd1rnTSE4apC0VqwEEWklPfje5SjlbT05umtK
lAh305m2Kpt+ApassAy4xny+gWUbs8oEUUbjHSqNb1wBn6jIBkWJuoXQAeiyFMB3o8fQD69yxKqq
smz0Lm/nJR9v/O/6nAiBJ1/awjbW/AiCCuOo9HpzjAXX3kR61jKcaK5Msii/9DoOd0yAJTATu7CX
jLB/HJfOw/m0PDgjFC1grU9UaajemGIjP//cm95T9tPVkX3V+DhoO/62r5tHeycF/G6SlGnICU7h
sfye1pT/NClBi5iDAwxJJczy3mIe9PF5Gz4bBQ+Lh3Tu9wbQRp3YsQU2jDsKAbbRQLA7sa+O+f3i
+1r1nWJQlN5i603kEMbeIzNWoVGVJTJIJTg+dLne1hSfyA3vjASXLX+vk9fB/CT1x1LzFc1YvPOV
JRsf54F9YjWz52Dec2GPg6K3qPXUt0nTyKhUzwcnIV3dR2PMD8i5R6Pn+rcw5pi1ey39J3vEqIqE
ZXZEL6z+hyNcA13ZcyTNp583CzKjDJ//cTRxLaWwc4wLt6Ehv72NlHnOrcCxoZKuja1BP6y9g3Ro
pwGI/qZR+e44OGIjuUoM+DzqcLoarWUcPKHwqlryuhwMYPMKalLBEoiRlIuuqW8i68V75U80aLDP
B1/SJ6LSmGC9hy41XqVrdt9cNRMc/d2mWe+G5+WoEtssjHV2ijI0E536El2gIb01izaiH+Onl0GY
aEtm48GSdc0xXG8yBXwZBVDxI0+cvUHNuuwrmX+lf+LDE6VaYccEX9CDWqYSKJ0jvPuvPi6fRMhb
wmbanzi56MtXaYSQzPRBcs91cavkvekMtO8KosuRU7jCXI2XIfh+uTstvp5DOyTkQIuc4wE+R3ZW
esmQRuKx1LhIFKkpwuUE5I+5VwZ/vt8RMPEjMXAit6KhL5opK4AtlGRoU7vbmq1jDMuZ/Rxzve8f
s+VuMwfL2xd+TPd1TnuDSpz12cW4/AKkx24L/u1LCINwVuBTWNfjiR3clPw+zjHgmFTQ/ZZGVcab
HBdsVO8W8382VDe8XAUwaIaQT6gIFVJJ5dFVWcxbSA7cvRGk21Ay0Dk1t707MGU0W9ggCOL/4O6j
oyC7E6jAE88r7cjVlHVG1aufFI1PmIz3xb8DvDeGFHVa+iUE/L2pvh1BZVLzHMUkVQwHs331g5Um
zxt551ygelsm9nd3b1MuiNrlcf3Wcv8cgdldw12yB2V9K0OSPg6oCpuxuTO/RSkYJ8+fBanHB/N2
gDjotHICBQ7y0I12gvLhjYRGaU0WUNyfU8N3DWEEKGhsz5+rTUf3XYFYggTkM78knwGd55yuexg9
Ya9/39ftCBCVbyvvC8YZFx/lrnkJ/wam+pIK0ffCYQ0eh0/V5vflCX4vESC5/K3pj7yhOsxbvCgB
qHxKZd0hgQLnFlFqMBW9WtGN2XXqXA/oezkucR0oOiT+qvoShQmoXJq79AVQOn3RPZGdRw8WPhcU
r2bDjkeoJqlmOMx8NICWn7X9maYbuypjWfDe0hCUqkOhHNW2pagqPHBIpW/FuaQONekbCDuNiqS8
zzqqc/ZHmS7/IWDCoEiGH5k3V6oAs47yVfU1z0twqKPf5QonOFHS4DYb172XVBBSuVqpi3IFZG+c
s1yp4lNaaJ4xb6U+DxSeP0WdowXUVYFQfBjjfiaEwdG0uJu3xvif2IyaL7PyLPrX3VmWRFWslETe
HCDepn6ZCvXflUclJW3/SNtLoXLV2RxKaU39LrGrvahjUUeTJ0fNeZWFl3LgO0/qbauZ62m+0uIM
tceJNT4+Vj26C6Xnvf/w/xYwelYR3IzjXLUxO6kfr0G+SqDBSpSM+fMboiIDmZz0zaaGT1WlupLG
8TN6YtsPlJOrrZOIeiPEWEujTaTj8TcbMgjboJFK0iI2y4E70cToIPQEOfC5hcWSjoSdiGlgpmho
IDWIco4SY0dPHmcSbn5Csqh9wtXi4fheS8qp1R52jdc8Ujv1/N02cYfoNn0C4lDwPjXYTOlBKNzl
na/8dq4SmxPM7HqurdkCIixBWvD7CTVqC7UZ5S+xOZTyw0kWy5hpXIgrA1q3vjIUQZz8Yb93Wdsq
ZN+9FMIZ6SJIgfOJu4WpacqL/umssef7b1wsbOd16rNC71uhhSnBZOOsmQjkiYMW6d9qOq0ErUA5
0s7gylg6dsQhSfj6pbnwxYRRLvVXvphZA8N0axH2s9dCs3XYOD2DJwiZkFnTZ/MCYZIU+BGRl+RV
ZYafioo6NfZtt6DRQAkhJADNCYTR7Kt9qGswV+S/Ezbm/sNQRYsZrmQLzhTmLzbPYmb+wIzSWVxM
fSNhTXJ0e/J9ez9Fr8R2XZ4omZfeJyobFjues30FrA4OthbahJOqsW7YZL6gHHyghlZuyDGaktY0
4L9DoiwMwHESI/dlLuVXmQsYPLPM6NHK2lIo7mkWC/gYPqYE+EJyCwOj2pzDPneQE0RmkMB3h1Qj
pVTrB6KXjCjmdxV5164ro/j49nP2We7lledMHeWgYrq7R/wMlsa83qqdgWxRZ5guoiedAFIDf+k3
oGB81zVLd6dB3OThmfK+1sJy/yE2qdX33Wi+iNMEUTzXpkWzP4PQ4U4YDcgs7vyxGumym24fpCe0
okr1nw5c4axTrR/eqJ2SZj+JIK9+rMcLdUI37ukgX06nlLEGX5R8bim3/EQUstJmzQFAHLepz8j6
vP4/eak2+j6PVspS99PUrkYxuU2hM5aZp+65QnY5aFzfDWdI7a7/mM6N9Eoyip1jFd3KKva1Qt2i
ZjocBQ49Qy+UryOhC8GrBdkI9S2opp2oKcAMGiOypSgkawXKU97IUxaU7qO08KgjJmx3hsfoNA1p
x5OCJ2Cny9EyvuF2uWdIrC9w4dZP86V4oBDjMvwzt8u6L5s+m970BgYzE9Rym9K8tsl75Sk6G0B6
oetGmQSLnBE6JnzRG4DkaTmc4lmOuvvVx3sEb2nMx9+sTLLrC5cZ9ql+hxarm27fMp/VjJeFCYDn
SqTEbV0h6YoPr15oar+VO9z4nDsB0nXIhoXfBadSYfBA/XCqHGi0hdsbOKDGWNGtR+khlUmKiOwK
FPBxd3u6hthyoyByCkJAh5cB6iVpn4cP9Hm1rJ/nDX9lGBKZVvs1Cjew1FBLsmIgQYmpa03IFTTP
WRY8xrSAviwKyfIVgM9kBOWVEgk8ah94a/4G/eyGUtejq5147MsKFWGOyZPZ/WJiV9Ucx66hwfQz
paOPQZp5FeCD7UGIH7Zrkk0wL6/6BfwMxyVF4YF7Gqlz/6g2ncgyEE0cAeSKjwXWtoi8Bfsgh3KV
PIagwpn4sh6Y/EXoZZ2U0krCMGVec5i8UN8pRNlJku5yn4JX6erxjRc8YZrMl+TyzXqA0loSFu9b
uN1c+4J165NnbGecTwtbNK5pLr+qTlsOM3bCG+RvHt3mbmQa3bMnO6eRC61rnW5YpE+H2BQra4Qv
Y768CNkkvcFztt//sArurHi3++SvdiLeAA9WSDrJoNKYoLz3JOMYawMTAhAxNXI+3KmdBno6IssI
7LTyP4/EMTplZu129IAuY1Dl8XNEeDty+GB7LrPoPX9QhIP97Cpk8HoFE7ZADfcHv8iUvfK7HA2J
xtvKSefOrAo7c9JUth+F6g+ygBb9639XrsF/lJk4tqBMSlCX4H6T5A0l9VhIR6d/wsUUsLsNC0od
MtamoCP0oesgzfSDfXtUM/lF/4sN9SFHML7/ML4OyHfw4wp18cfDUIepfvNRxe5KwssPw5xxe5RL
lg6EaKTrfEpGuMVcCCPY+b4maEKdh0wOlSqFr7It2vQXFrBKWU8uqBtQ6Q/qOTnsq1NhhRX8Bkj7
zhSiTE8GQZCobHzEfoY6wvUOkuczgqU7kRrx6PdUukl3CpiBcqSeNWDin1kL2nsRcsOxj9N/XAae
EIUguJGEL3jGl57jY0EmJJWNez3UIvLi4kXEcex+sZqMXLbmrBpAbvsl/2Wf1s1+UtT0WuT1oheT
9sXlM0b0Ihfe77SfAgvmSbHZ1yfdwkqit9DvBBiM2e6M2IZ+N2n2K2hiEfjxWV6RnS0AOm9yNTsl
+IoMDwCLf67qTC1A6Xqu7ViAsl8HRfbLjNyYFwHqK8dnpOF5I09kkKqLXbRjk5gflE+Z2P+Xx5VV
La13Xgi5PBDIfRL1yvCrIhfnXTUigKODTWNnYFTo2UGM3wkgYU9wYEFos8o+tgGmtQefg8uS7Lsv
Qn6cFJH7PJqWzugEi+fLmcsJNQ2zOz8XbRmnzQsMDzRPZXQKkpwWmunXI5oCz4iggp6IKhRaMWPW
kQuxv0UQnplvi6+XL2HnwEMM7Pw6wRhYQumitVE7OdKXSMePrhfNdKhL7lX06XqUL/v937ZfSU8k
lPjWC/uMrbJ+vDIuTZnxsT4qok2rC7vgADhrsBOdcbDZWYd87Sp3+HWkk+T4SPIyNoA+08peDNpq
cpWYfTShliscCgAJxcpLXx58oBtYC65m7UqMbYmVo6qwtVbRoCeICrcZEcNesJFKxDkgZyiCe2BH
eXiQHuHwRCOpSErNupdVQ5YQAAcpXMUMznGSkM7BWmOU/HnyM2EZQKcAzKXxdv94GMhJNgIulE/Z
znkJuyoOr68/rt25C1/iswisjP0eVtyq/lyK9K0xsMEgpuDPZ2OA5fFdbk02kBgiAVkql66QPf7R
7CvCDGQfnfOnM0ec8fPynbnxW5IHTp/Z1UnlU4EVFEKTTe+xCauy4sh+uwhdCN/nMajauZmZZ13K
y+ZvihqqlNCqGC7zRGzLRoICsbNnfc6C12hULmp1bcs6NGz8gD/0heP8CtD3oVP8vaPZBDnp+imy
DDElpY+iZ8mVFW90DRZL9vDUCs2vDmpESo6XZB7GTEzmGZiEVMelb3zRC5Hwu6MjFRxzqtzazFvC
uZvzRGEryz5v+QSEdAUrurSr4YrKgyUG3CAIz36WGgCMs8z2rHaQl+nGlPygEoGtGGOqW+lY7fD+
ATz6pWQlKCj11+1JY2fhGUVOylVxlfgx6TM7Oh7uqRU35VzX6x4vnIHs/pwZsPTXylGimGmLchSv
iGwqxd+Japp4k9E3KblLkDRkbcX88iDdtdN+Ek6c0Kd5i8te5wUXHCQDYye0ErCSvtDdTNPrXe8a
NJeDMes3WNzcYqW7yfh1Bn8xjlTAVuJ2dBPnj16CVzH/Aco8Y17rfFbRt1msdZA/UHrpzuU7TpcP
G28o1r1LlfV4trmAVRxp9k/bd7k53FcruY2ojQypfPbIfGFPfnmSi3wV8boXGZA3nCdvIO+4+x8H
Fo1hv4dMyQA8bWsz0SIw5DnIpnM/mA5FladNZbKu5WvMNxD+UCQniOu5YVLjx+WLCErERNtuSvn9
zyVmtECzUyXu6bWGpmt5SNI3S2NjB++CF3axh7kOlNLlwXwoc1ZxygfllAmfQPHt+MtHK2AyALJ3
8OLuhn+/QaMaSDJsMMPfS3vqwIytEgMULPLTpe3I2AS+MGc/wdgnVpZd/ZxErNEN0HhxsAeEuKjP
hNUC5h7Aapna8l6PNdfgNjdEMMLZxh2DnGF00m7/E/hy0CQ1pOBwHJtc/xcvOkObOQoCPu4lp9fU
bqmuMGWhigufS7pqoSWx0fTlokd79e6ig9GnQ4NYN+aisRb96JdGuMNi6ItIPHZfNAlag8DtTGoE
f3dPyve2I9q7Ve8+OrMqQGIiZDssHaGKLallzSNA/r63UUQsbU3vN3xSOiWBNHouf0kW5cxrsvZY
L7lINRKlAmOTopdwwOyPLU0I65r9RQJwX1mOPYIZtzFVp2JgrshNOEG2ZWouLgOLIGv1pb6yZy6c
Gyeod03K86bguaUZkL5iJKEBB+1LWTs9DJP8Abhzt7QQXVYdgzFZwAIWlFcH6npTcKay0U9EI3k8
BjE8XjPWYd1mdn31aOHYCLyLoFED/sy3tHpr5sYzpVxY1CM3QXOPuUYjwuUeDk7FGBhy82ax3vOZ
GRE4OZYP/GK07ZZYutmihXuvzERuYXkadNFpHYtB1uq1cBflxAT/I0WEs/6HGprMxcivcghuOApj
mbJ77oqPOqGg1vwEYPR2q3xulrxd25kq1PkGSFop2noy/g60OcE1vM9UIR433N4fk6RfeASCxjXi
pMKiC3q4dyIMp4aDBs/6g4XY6SatXA79VBKXPeB4LStNbs9mIBx8TBny94GA/XIIylPQxKjT2tPt
Fs+c9/7qGAyY8gbhGR4r5ncZtfr4+z223RJHvL+kNSjTVyIqU1kDHr98aUgMdfEMF9+iQ9pAhNoF
8tbd3lhJCxndH9S8jtshaKLemjYmC4gzWhNuJN3ehlbPq4mSa54LgQRoACv4ofI/aar0fCXdI9pD
PUrg5++DBOi/yYrxnk9UXCvb/z4KV18HSzEl4DR74QQWW09Go9Q29sL08ocj9upZyajpSc33LSCC
Eyy/Oo8FEecW+XjBRjRPSADQHXDVYYFwm/fD6Py6YCzka46d2SCSbZqH8dn5SrodeCg5JV8f9i1E
Peyamd6Ukt+DpOxkc6JXvcNJTiEKhtRfH4XSLEZNB52TItNp87H3xh8BI5eHkRGe+Uk/WJiKodvB
UrU/ufS7n0d8HnU2iiTUSG3EsljTNd2gxuAWbIvt3DwJ4qQmzKCkIZjVkSQGK+zTQ92MDEg44nID
bWyCUiTABZTP2bkpjuF47GijpmbDM538QlBoSkVKaGy3jbKTF2UJC+ugtzua/xm9S5DwIOENqqWX
VUrFjXoJeNSIW3etsnfLlhqNTMNr7enzZgZluXpmbC+rv0TyDALuyCOaik0hJHnqEaZGimrvlBeL
1/YnIeS0fw+bOkd9Z4Fa1df8FjVzGvdkU/9ilRt0n7mFh6sAA02slmM0Ws11Hq4mtZ6zQabOAL9k
sy2ACLlEiSfO8c7DsrWWGGHH8iaqPzLFgzatHcXmRd9ovb2/qaC//S+uX/pslDCUgp4alR/QmNtb
UDx1gC4zQMGBKIgjHVyB71QWlLs/okUhC/emZuQdjWOtXXm73gJ5fqX8m0NIsCysghDiz2JNOxl7
Qv1CExW2gIkppdJa4BNOBGnXFO4OcCon5yTtzwZg8XrEvO2H7exLBYUpP5ZSzniIaqE1agROXCGk
ZKbmnW6aF8uVnXVxFHqrdtK1hZHieFjMGQ6l3nHNPNwgVhg0mSe+A71eDuqYdKPbMV0k1ou/zoAv
LvFLsYzR3IRWPE9A+7b3FrwsvP9Ehh2zGc1WwDtMbsvyFJ+GpOHMBIctYtGZDOozZ4qbu5X6Rxm3
CSbvlQJpMHKFleb99Me+wy9hA7HKjUVtYGcjS4z8XCH2NswQ7P+CO2vOrsx9m8FHSxnZR0hezgzi
ZWKvDRbyxUrVe4T2CSVaxoI23icuNQCrOl/YxTAkduink6YUpR3iFAikf4bMNinVA4Dh/cTJdKw8
HSBFeDhB77i+dyj+PvwASx+wNpeOxSurig+DzS5rEYXmYTsSq3REg5f7oxJz1+sj4AE1FW4pRDdo
fxb90KozDGGoL/QxGUD+Qcn03182ZCb7D73dCYU7PoVbSsTV+ZKm8yMwkxw90sK3edLpmgcP7iiR
fTRc0wmjxArWmRbFWeMu68W6hF9FTUqGNZDS7yuEAlF5izZImhX2jWJO2JfKcJBcRNvIcTHTRGwt
im248MsPBauQ26FxPWj6ImBc6QsRxHsEl50gmfHTl7PbHTfLWpH35u5zytZJFF0pYlEooLCk8fcJ
DbYeXGcs0WjC+RshqorkV4OKLt4yBn0U8++IONVyn+f1yjxiKXrz+UZZVcPDNK1InOVs5vmmfICm
vbV/ppOcg4yluURAsoZc1sgAUVGOS3wy0BJT1CNLn0+Q5A4yfF/tufocd0pJLmcFdaaZG/dcTnKz
gkFbgaPkJGkpFspyHK8e192uLq4afzKqYUxqylrXszKx0fqu1/QP8JdC+CB7inLhDl52FzQF3reW
SIQXPJZR0gghlTa5s47K6qhhfjO+1+1W2YVDDwq/uC/nUi2Yj1A1KSpuk3weKf0IKUeUbkq71M6o
bmgXv/ozl86XC7o8yW1XVghLRM838cUw0IU2nfs2F0EtjJtas1+1kS4AfVaO4/yhKSAr0MBrgQsc
uvD22K8CP158WDjzVrtXh2rquQYmp5RyEatjR5/JWNXikZDdYZCNZBQ+D76vv5fRBFIX7zmhDKbd
DSrky5ZW2jcvQlh6CpJeEzAs+u5Z5h2iJS11fXkNKEx1QwX4LsfuQwTIk2REvLTTIl1XUFvCqnOt
nH4dKBHAIMIFbZILZbxBSAPDo0Q7RIqcgzT1OWdOItsRBp8gWZDv0kYMF3VYwo4wlqUZk/Wr4TwG
BxAwRY0giL582i/xr+OSAFByRF8fjma7mOWm6WQ3OG4mKEq5XeBo0hrPFhn/ZIRFKLXYqYSWF1ct
v+lMiFOtsqEAxyihgBOIepJfoLMTheX8YQW2uzIMjhdb6ILssMsnC3C1Z+cvFn6d+2hgEaC9gyEo
VLQhergY+bhkg1PtQhLmzxVnb8FaVyHcbWSaa37eYraCCXPC34OnMCfDlRSk58KqERq8L3UoXjGT
08PY3w3bM0mS+TMtJ6VFT8jQbo0sJOHuz/pAquOMlOBrBaBW/wfQS03NpDJLlurv/kuApz7XuY0Q
zHq0iuiCCzOGODXcHcuR8XzSdCn4DiGCSF3ZmpzgHP62EH6wyXB8ib/GvFZN+oljbWs1WIaO48wI
86wVz8foxlVKRe2Z85qRTpEVbXKh3G77Z3sAGQugnecx2bsqzY6VbBRgvmjo7TPG1PsDEezs8sq/
K4XvsBl10oNv9QeFOQzCc34YqstpYNcP/2ejekgKEGe7gRJ7jgienTc9EZKYdsxBKgqOjA1ev1Gm
N9dm61c3o9uNC67rTHmJ75ai6C7U+A0XLj8cPilo9arNhPSIRdJGdLqWhJYbWUVV5HaJlVYbdjwi
xdY3Js+g5/B/glk4/ij+FiLm27Kn0lZi1gTRDironN4ZXFn7cz2knn2E3v3sGzZf6ksDiUAlcwZ5
mwCp/XA60IlouztI+1STrFYyi5RShuEEzVC9g2PBPS50KyK/W70mQylgRuBvj5txKSGtHUyUpLnP
RrLpqaURdF/1waCkpgWx53K6kYZSVbbdmy8+kaFa1+0X1OosIs38AnUZhcX6xv1yrZv1C4DcHl4O
o/OeGA1v7d1GRRCvpcZy+OB/YPXYPc4NCMcfGO7PpAetrU5/KbU3q2yPHgGvKxMqGVWUj4+pjlFe
3GLYIRq3pmVHTNGuB4bN24NBSOOJ6xczbqGeBvn7RMUb3o83qngjoKcOhjqfEyjvRpDVo4gVIoDX
YT2jh9iLrn0DLGbaIpVCCo6VWkwm3WbD4DJaZF5HELdUnHyiVP5YTXZx9C/pHtAtwC99YiW73jAG
ZdGLs/82VshbKM0vAUG02rc7w29cCTBRLMMZcEwLJKhwgo7434jREBAOYSst1NVH8CSJr1ENnnNj
Np5L1cnZT2fLOAibpcoRogwbqnMrXvIjYPKz3U3pMxtd+1c67Zot1U/ufzsj0RZEBoyrCqHi+Tme
cjaujlK4F17w38evpD4kjdp9e2OTkv/EgmBw1DlDjFet047MdAZaSX0ifVBA/8upv6XtQdG1aCg/
QQiluFzlK/QoxTQbQYHvbwwaVejWqpCCdIUomEbiuOM1tj8BNOFMsR+dnlaPB27VIs2ljIVZWHmj
aQ/Pi/+8Kmg5UHMA1DYKIvE/6LCRLNRJWVZMV71RubOYE1HbugO9ikJJ0tFeT49szBpMLgGGmWyL
RrGZegPwQUuh046VchDjDS42IZn7xNBx38F+d+fgO6DyKpa/H8Be7fyPt1evFZRkxpWG73BgzCyR
MTGcOs+XlzAhTQDW0A8SNBh8e7uYCH+vTuNykq6wFHOZTz7RM9bSn/hf0nwCCDC7SEU1qW9SVs1B
cWK9fSHphtR8J0ywty0f7B10b5RZ/2nZZJ+S/6fooU7PKm2F4Zz563rL0c46RKK8JlzPSkNMQFtj
ep4m5ZCj2TnwXgB9NtXebTXj+9Z5Hip7lVsAZMkLC30NhV7altsKpRdGClRlmsOmlGXqPsJpjGSK
oLgWYhNbpWyk53CEpmAQS71dmyVefwNQ1/q/U2ceAm3xBleDPRVcGIXCtoxRv3y42fgOSjumEmK2
FgfbAv8BvqFmkq4kSzIG7CP/FnyC7iJzdHusvFHZhx63MVIhxPe/GqpX5u7XrzIcqY4G9ocGQZEI
Jqn7JkhcocQWYvN+fxoRBDA4kXo6FKhBrfhmlAGE96/P5uF7vG+kF5w3tYBCcnkH3ZkhX28f0WTw
j07QrHVP1J/sJo21rSWKdqTCGSg1TYa27A+FRPTRnK2LaTIGjrh/QaFrK4joucUkz5aydqzhMuSN
UNROgrhjjIm59hLD7tX5rEkO7MB3CFri89Ipfc/n6rgumB4f4SSJd7Kx4KNBZmj4QsAxbeVGtJUg
tD07PMVkf1akDUrznqpVe5tolLYVsDqMItQqw6/Xb5qG4T6i/KMgoygpxGyBgBnjIDuJBqrN4ovL
Qq14GRZLVzvyd3Co9wA0qo33ATgAFh29rsUgGxU9ADLule1NDos1Zim3bI7aEbBaC8VuDlqWp6Mc
2R42Jk/x0Ec1XGUHwMvmiUx21UYUCGS6aJUa1UN+1ITOL0swLNAKhiXsReBdrcoXrp+896VCrKXj
IB7vfpI+jP0/TG82hG6nWLMcB9NAaDgTyWv2fAYbHM0RwKbombYv0CxVPlI1GLjQcKGwmeji4Vzd
t79xoT7w+FESS2lGXDMvwNEwrtvjD4sD/KK+uIOmplJhKOJzQqb3Ooiki9UY10K+T9YS5ataw4u/
FCpLVi/2xmzs2ivPdlDoVns/yXAzzTwZdG0MwuHABKGjiLUyar6i3Bg5ozig6OlcLIX5G4t1DkJu
T4AbvrbnnVhe5uo3TZRmYMqL81MkMxVF4E5em7cy1TC2tW2ucVTtDh1BdDCo3ZUZmzPXYIteAASk
QI2Cb/6ms+uNUcOObd803yGGlfOwjUovOFFIUHbra4CJ/HwNEcRCglfulMjIKfePoGv4pICbW3Ug
SvLKtgyTmA/U6wzJEGggkd+qLwjuxT44SMaCcHwqiuVbWJAB9oH2Vx2HRV7ZVG18rkD95f/OB2t8
vR8pcx/7VK/u/xKfmYYgxg9reyG4lb9AcWGzDR3nl8l7VifC7b57ty/UZW1hag1leDt5UXKzEd43
4l6ckQB2LvO7+ApczbHHxEZgvVMejn0clIFNpOg176O1gPdEVAFkPLa0CneD5ileqFSDf/pKHMMo
+LhbrL6cnd/zl/qt++C1gTwFs8mVJ0UfjOilMUK8TG0tNBoyBSb8lwR83/yebuNROVyWVFMd3uhP
TU/D9iDWs+3u5BPrP9LX+8YREOEaX3W1pQ96CdPiNF/j0edSz482FKuN/o+/y2+lk+XnTG6U0reQ
EUVhxH5YqDdLLABR7GKfcGcWm3z1b57OG+EdsqU3LwKfjbXuzlntAAv1/ShJXUIHHaaSjsluUuw6
DnjwR7q+3iLUyt3miL4zJzOcHGF+mYGEKUE60wdvDBxk2W/Z/oUtD8lV4+QaXWhtFOp43Gv6tpJX
2M7FgasbPLgEgV5Rr+LJulGomDnFVpjDi2PWNdyifROZsd9pulSdvv+K6KM/sIYouza8simPsZ4P
Fmuk27xxpRonBOTI/8+xRcv0blWnMqSutc8UcKlwZIsS8tPGIcj/I4iLMLGeoJ6Ra5NSXrrzBTsN
1H5iZKV93oLERfgFlBWHbvgfl8Ebhttm2TP/7y0qIob7hc5HqdwrB9pKUYK0vKTkng4fzUsXLss2
jtPycKu+De6ZfqrklWSLeyUbyawCj8fS0iETjBkVbMBpre2lnx/bkRU3og7Himm2r4ety3tNINRl
MAflLBSC1AQ9I5CNNO+G3wjNtsWKvzkGFt7uy4EC3ihWxCa/RnFTuYhA3N5jKKRvQOXmA06KPzCb
jjna1W20pjVXC/JQBZZBmhUDMWJH6mIDHjd1xwiYGFbjzY//8ytcGNwVP/Cpg+9bSRwnfukt8LAM
ypzgVPLy60lyu8Ajdpeu5M7iNwW8h1DJUfzYwvKmirV9/T/kF8sl7ThlL2JoMIG1hNNXjyh+MBuH
K6Yvk1OGbUAayA5n6nY057l7eWAsGgQMA07WFTzWAD3CQnwIWJ3cABbiEdgLfblC1bzTTwAjXGjh
OLMB67tZCPfvXOM9c614dQwt4Y2IPtaUAEt+rKH26MmCGjeA4NNU/2WxoKOHkdo78ZtmE0VMcNuV
ayAtkzK+ptmg+EmzTBtXvIMUnEgmUgOLy5noGw9INgwZm24Jsds4p526doOGm5+TzSVb6EXUmaZu
iAiXJ/uTWCN3r4rEO5u/Uc8cwX+YahNFIFs+GjD3bFtq85gsL98eP3Z3wdbs/kN7Lhwv+95TYsv3
NtbA1b7bo65O4/WypmEFwZlQ0qEYuGEdZad9YejHvOScyuzuPax/DqK/ebs66WQtuweaIa8QoIdE
FLQtembxLzUpdQlkQ2kKv/os/a/V07p7uZoKqxZJp2BQLdk+0irNXzk6BCEwZRCk3+T/tH38RETF
0fEF89llk+Q5mtM8jWpmezUIhPvQAWtC0d2Km+dirhkLzUsvFlmNpOk5zaOMhVSs1H6Wne6aQMJU
HJsCTN6bN7u6wDpO8oWH9LpDnCO7/XQ5wrNa4GfX7JUxwhggvtRJKoVirLCcA5Vqa9IBEUQPxsZm
0mCic9QZv/r0Aq8b9q7ukWPVQruZQkum6AZa+dW9y5FVHEI+92iFgk4vYQHmjem8fMkWPVgZX+HB
PrAJArd0ZmSwmMtfqmLOZ9Tz9KRobh1JaWOcywvEk0h+GNO9awj+88pxl9xQUVWzqoAf6t1Tf8bw
8P07bsHFujqoA6d9HmVisq3haRQosg+Cx5BjWwehYAF4dbB4324I9NcxRNvnX+AgTROmZ1ub1s3A
tw7hvyPG4pFc8rtJF4Qh6aPEMScmwgtC01bwgx6lDCmildo9harWpSN+boQ2xVqaPMXrhi/APFLE
A7T5GvjlSM6+SE51X01BXs+KnvzsboTcSce464WPi5xQPpFNcmudmr72I+w6KovTHZHSL1Wa48PM
1T1vxXJH4v2DH9AGqb62PezKMC15bFsH2BEehYAqUcT4zKDeBBKICkhFkQUMPSvkYku3FlyRzyPU
Odj1LWh4R1V6J8E+4m3/YoG78g1xiArieIvPWl9Gk9eEmxrfgvOEt4hObLS72EEh9ol2OzlMc3yl
Xbve6YsYfVR+1YoOv7DJ/3Lj+iqRhs5Xcwn/QJZ8rerMGrsfro8ShMGfaSGBUyK8kxqXEuD1VgYl
nrnpbBtgUFz/MRodQ4GQ7f7p9fpboL7g1MIIGZNZHoS12UX5+z5jbVbfr+wvsao9N2SUy7TpgClH
QAkchm/vOGElKXmzqWkg4eMCebRPi4LS060CDU9H8O53sUkzL9BtV2+CwHlIfIbvJ0V9mQ6Vmzn0
veCu88nJ43dBR7qvtWS1ho4eHda3YGVtEB9V3HP77nZddG9QLTNfBvDn8Wigi/I2/n7ixhfKQYmP
sga9mK9rVmJ1UL7M5ZSJrCSAujUak+cdNEnlkxn1NvZGoHX9QDKBZmC0KBW0un0wg/7gNMX3iIkr
nMVchWGJDAZq0faHWQ+nEIDR01NpCjdmdLKHwx1/Jvv3Py5J2h+m/uTipQbaWNXvHGIte3jZm5z6
b/r62GIGupS5Ih7K0qmSd7vuhYs2XOKLhBLcY9X6gBu31iufhF7fg8BPOG+NPSrCUxvakzfe+rZa
zhuQ6STLUZ2oIIlIllZ9LgPFdXpXTzEYWT7xpGxoAW9B5PSr/kiju6e4MyqlzFKNCzBrE5LGsU/P
YJyrCJlJ1XhC9jaTydZzKIaq0LoDP80VSVTzWS9F27m+BVcwZgs69v4SUGklK+I5ito0Y9DBURAk
P2DvcTH89JBIVRnR2u1AgPDfqHJi4y4TmGKi+jPifLU9LJ2tBr+/jecx9EwG3Mo/pMIuk/JtlZOp
K0+5Fg3Fa7midHJKRxTMCRxnOpea+P+0GjnOzUo7TrJPAmA5/KTyipFnE0xJYZ4+ZsApVgZ6NeBh
gRY1SLwKzLcR7fVkWcT1uHwNjRFKTIH5EXH8d1lfm6DH33xF6tamIVjQ78n0ZtsGWzIa+rnLt/73
w/YjYcNDGPCztt68u8GIQQVJslQiulrF6drlXS+sro+5Q8lEJt2EDw0IONEf+IQKWfiIShnKBlYs
IAsCriElngVZF+XsokMi/l65IPc1ZQj8QgjzDeN9gc1OPj21Ir9JLzEj/3ylRTjMfSLam4PM7Fn9
W1A4asWBB49O6Ku5z81m5zjvOUkPPQniATie6N6xjZI0qrrWBTWYsyJFhhehOJlsuVIiBb+V5Dqs
fpJiVIys6hxWo9qpytWFsVq2ySIhXtEZD5cmzghDS/qjcJP9Dxv2rJM6idto5K08ehx9vZoDD9J4
aSSRNJ5QYzu6gN54O0knKnVGiZ1DpITrNa64c5Jo1NnHw/keuYsb11/cPxtzAE9UUsG6JIuzN8Y7
MpuXaruegckRjlw+oK4SAT9FZaGje0KNqJNhEFCGLs8wC7urLZ/xRATFo40FpdIDBWPMlVE83bBQ
ssQjsln7uL/WOMmT4+CTbEyRDGGRAJSytF9IBrbPD7dYUaDYPwAnTgV6+875FfHJKDXLSpNNmkrc
vtyls/Y8oGrz3hLj8Moa39n5mvOOr5rEOxvGxIiEBMLolY3j+n9iu9AvnCkHUsfymtKKHuBCr3nV
LBKDTYOdfE/eKmHRgqLWyzzZx0wIT30OerQMMW0Sj59Jc3+nZXsEWvazO+bDNlncSs3uy4ws4WhW
lGOGyFRySxTRB9q38v2eU4bKyB4U6zJGVCUkZtM3LHWFLXTL+oanG8cYjWT3vldgn7ra+7exKpTO
BHTepz794+tLnaXf3W7atZ23JITVC5XWMxdGrQIP+JdW36oHesVVJivnU7XDAhmObcoGo8T3B6b7
ujEOGaXKpQYa3DA/uPVhWr5uhsCuQgEPDp5IeXLpPBZW/CCoert62G/30GlOQbhi6CEoxHXGSsUj
6FiAAQdK2fAgZszEf1J4ZkzC71LK2ue1rLyp8aj3soH2nXgyGxn3kVL7lT7NlFN/HgT8SuhWjy1e
WCybEd5j839OcreMuQFBX0KTsIewEpHsSMO1MgLiejXEQXHeRvo817hYW65ZUIqmVb2HwE9FvhES
s6DiUm2PLlIsjNQOC4vZN3NNd36hhLKwa7r0SIUlH2KRgLOXSZ6Bq3qV2p2TKkgQ9C6zgb5yXkZn
OUN9KEDj3Ce3pkf++kFOYzEs9drCmdLeJUkVfSidT86BpkIbNPZ5fThVirNE5Fmmj4eRCCwGvG3S
klvZDepLU4mLWgNUjqSDo8880OcVf50O0U4+GN7vhg5ybbAkgiHVwqcWCU/l0sGvzJcQrFNBH7a2
Q9NT13Fpw7XrhkMDR4C1nDaBPnO4mWw0OLzBwGOS3LtqnGfUDDcHj2Xvw2E5PW0hy6L73Y6w7gV9
fgIPb/m4nvu57aoQyGES4TQsJv6vLQGDGFibXvgKfJUBjO/F4Gqh0/Y5Uo52uWFcqH8pDBaJtJcg
EfA7VBBfD3BAIXeeqc4bGntpOSkMBxrqh/+gQtpDlPZXvcWeHJFrVERUUd6QX2A1oIf5m7+za3l3
n+iLQKF3WSDPh7iG7Vr6U3LxOXNFFD9N8l22IMxVuGSI4jiOvkFV88vW0j5gfXYQIe12aG1U01U1
1i5baZcPpKruRFuLCkowI4/y8hivhxplUhyE9pKnXtBZMhWVUu9s/HX6ZKD1KuBDX8dJQ6wcWuDP
9vHSwhdLgXAl6sbPjqKDyCMEni6DqWjWbJ6A8U/F+U6dzjNp1kSaDaakTjxLZLz2axqjkD+kK53h
oQy25z8e1DYOEK+L50/G8TZ9xENhrzvSiwEBocNrdKOYnmBWV5wyIHtw3me9Rqz4wjLPwi5ezCz3
9LeSVJQuz0veTPPH0OsbCHS/GD8qdXRRvS1zmgG7hyiHIM2Y0tAzRtd79LGxaReIY4BXByq873IN
BVjBBbAMrE7vQ17Vo5/Q7ZBY87BgA80NwwEwxzBcX4j2JDZj7F8JXBps4MnYd/FVnhHhKnor8EX/
uzTiL+dBhTYw7hF8Gc+NbErZQte1fO2oS8/eBpDmksOHJD4cJYZ/F3lU3eJY68v1Sczj3sgsqnFM
SN5k8P27yLkiCUcj7LrahLcHftvlIvSChNS0KKhkYR6BwLra4CqniocDCYO7Yw6LDWRX4Td/rfkE
3QCDyvka4VDyRwe5xXIWK0D4GN3WP+xbOxVHtNygqfAsOIW0p/i9KrWsd0F5kVNom1GeuACYTzbi
r7TU9LnCHyUctNW32U1kDL0bBRFV+m44xJ66gB+0BnGB1W8mXpu6T/TOpOyUbUp0bcIHu7Nev+zf
vYxQ87ucdIjl7nfpDea6xV4HYamejIhMNwGyifyoL+kukJcn/Lb0FPF5SX2MHhIhPydKfkQdzLFr
Ei0vLxSOhIODN20KBnZGsp2yeUrqgF2OTY7Tb01A/J+4KuwR4tOVWhAvXy9Fs4YbJWeByCvy06zY
wxBhuunaE9ufI73ImT2BLT9ZaAKOMQbArIEIbFbYFwD7fRO9e8Llp85ASKTDz9kF2G2nQ1JRR8Ts
5QDcbw2+30adcjGfRh4vGnAk+Cd/vfwcpC0LhvmyS7ie7mZdwD3pXMbLcT/+F1y6a/3wpVQiHNUD
8+hE/s0Mr861+7jsNgaiweYWvHf5MsTByLTRSMi4QTRrtrGBRKLRx+pB9PQvO6/lEiiSlj+/oP7t
WngUMy0MH/KqKabztcBY9vYJmGOIQzKrvIoqDqILE0sLjMLCIVK7MfosCMxE7mj36IgRJh4Xyiz2
a+Z+aTQmZqtA6CyosxwAeOwl8byFCttkDPYooabpWqM8k9QDnlf4diARV6NKs10mz9/DgzRhiypz
NK1iPYrWrCcDjDJYpoRZys4zqJOFUqbjTpq5ZylJqUTqf9Yp5Q3v0EtC61GSmzGOcMM0oERpHvI6
MSsMgbDPD8BJPWiZsFjnD2mgLOykChT0a9cncJx+I0zKN74lMMNT3KKOBpyz5Pfpmlvtsb9cyAea
gvJ0z4JgT00PCjtToSDmjG3UsieSOAKbojhHhJZqyXKiJCUk9Q2cHtDU0nzW/cBYT/rnPwHQLbnZ
jB19kUBIxyCToasq8hwvhR0b4KGcSrVjp6tzN9acoHCzDvki9Zhk8jlxc6gf3SMEuC1oivIUtbxP
AsdbucfZ1NRoQ2RX7CvN2zfBw+bTsoe95I6NO1scGxD6y0GyfftGy8sSsZNuBD1hw1JCYdM6QSAl
97vPeyaFukP/B1Q0rg+gG8QtY+pGy8cIXAbVzcsZJhIBTNRlA54lT+0kLom6YgAAMt4z2cq8FfkR
esC2t5C8FQ+eGtEHeU6Q2hKvKY6PLTy0PyrlLbQjpP7L5DWfKwf4vE2NfU69C47sFd2P013asPjw
I6tmS23fQLKtuVwWPRd8FRuwKfShpwiVhQPkwzNsW+HRaDcbSFXt4DCfTSmBVqXmJQmvGPMVG1ZI
NN0YERYr33IIERM7RyVgDAbKgt5sTRpg5oer30AXALdMr28qUZWspdp8dzcBdYwKBUMa2d7oyA7m
BKXXw1pM279CO+hMxA2/wX349IGaVER2vhTrL5uaXDFLLmOzwdbzorb6HAk/i3BcFt8zlA3sj8Y9
1NKES7qd8n22C/ol8feWXo7eyMy9AoI41Aq8h+fQSgKYWcvcE+YQfwfxH//g4CiV8rmKy3kGaqr7
u9JEFygYA77vyrsnTgTWg0RF4/bXLKNdBg6cbTWZVaLMn+klCA0DlnmXAB1Bls3jMfBPF514P4gX
d4QN82f8HSCElploJjQ6ou9ZiQfA45GkmBndoH0t6jLAvlr83xN593rk1hYbbIACOimvkIRoLzSd
LODBxN3QpXr0iCQaduDCiHRF0MHHhNxg80RemRfEkKfs+x5YhH3YAgJkGKFPAX1X9MVgPEDnAATc
NIzwJKkdTUC54PqKKHmNBq07Mm0kNXCWl5DwHCaNb5Z+hiVgtlZ/JMGfpE/e7Jy46AhsSGGG+/nd
8zatPajUl1PVORzQelhyck7vliMTL3vn6HfQ6UJAxJSrB8AiO6bAFN6DGEnEYkJok+8YL+d8N9lE
2vvpqRfmmJP1yKTqY1Gtx4O3E7NA9fI2a4LeHvKOqd65Bhj+GeGDnBP9ukNvdc69oHTirTWDvovX
YbhbytT7ewGd8HH2FJ8sW3J0Bnr/9bsrwLnGj3WWz7bgr/7GWlxO7cBB+/sq/1O6vFh8mozIG7LF
RNMCueQDwzD4V3U9ixTMg0/87+HN/N1tn8EgYClMmiFH5EYU8OKiwf6xrpAcVEuVIZLYAkBTNZnF
v40zcTQLDflqtWYrgn+9zkukpN3ljV5Ob/lNt9kN3v6CkP/2T51uRK0/3wS4U+FdqugN3sokLsBp
W2Sam36Z/5cRMXqylxVu7aTQJkWZcTomP87ah75OARRicg5wRIkBIIc2SNHsTvGr0OvAlDfwwOHW
xRnipoCykH4/xfafyugJTLskmdt3SyhoCyuuRwsQvZoQ7C6kmYsI+vQLFF+dX9lCGFKl2Ff7j/Fo
HBpJZvZETrLq8qLgkEiHEyyaAy5rdSEfIHn7slhfNB3exOJ4kLeoasAFCizvk8unfA1dRmgl9LJS
/yaN48kTYaijJdlJDDG6ekynVyQv9Cxdgdaj1UbYWMLHmZrU6eyyvVxr2/LcyWD75pQrYpuEvvJv
7a2hosbSuVqYd6Sq9lwyqRCUFdGbXbBArNdiWCik4W7RTCvNUmzVgGuJzd3nkEtd4vP60Iy/hn40
76Gq9ljY/PjJiCGUxyehzqVzlu0o+Pl6OPQdz7OzOj2s0MasbT3wWTG0VotNuDLi/n5CDHwEIzFQ
mVHRvsqMkMh64/M7SbvJqJ2Ia7yT9mHtxdXXIbDtWDUQH9raUvnzRLYBXF75YKGJ9JJYyoQUi86N
9Lj6UAv09fuMVRUd5FjJhoRfotKlrWjM242VIx4pbjRugJe9JLfICPgHHFo65wpPgPrQGP45NhiZ
/e1tinDcof4S4by6XkHKijzicCBueT5MljpwBvAhhvWPjc2OuwIc+mnIXaVQo3oS1xhz9eIztIvv
yiRp1sBRoqt8aN2IaTQxgg9HBKHDlv9nXgz08tO1IREysj+6W1WyLEoU0HtDJ2XLeqDVpLexjlhU
pG3Z9fGJeG41np3y6/jKX/II8WDMlB/59UjesgJ5O+5mxGb2owHmsBCu0eB/1d0oq5QK27XlY+6Y
uzMnuRNMDRbLyUVsu0ipnFbnmCCo5tuowZI4oxZrDGOOqa4aibxPEuaVFZcObosr6bzGfDr+PEcC
Sa+wPdXdd2+Tk8Ok2ELQB/AOvIkGTQzEXs6tgF5T/j+8UoCG85Rw2jZiWp8mEZC/SXm5eTkWTx5L
vJ0MT9mdPwLgirNLbIh8RUzGT/6OQFmN6/Y1CqGvyZukj7Pihw4F/PZnwAesw9wLNJD3faG8GHx3
NeL+DE0SOBLOTsqSq/7ilQ86zeQhJa9rwzYeGn+IfAs4GzAeC52oUdgbkJUOT9bcW/7OlADHuNiU
kxg9kgMwMvNjIUjTZedkxnzbRQfAt/PgpyeJAsC1p0C5eIAgYD/Zcs0YlKwcY2n0ZFaertziofTh
L60ERAJg3bNX+g+CZuqLaPlzNCJesQiZL0QDBrxjwC2xE6SHefq4MjlommTfLUpeOQrQ7MukUpKx
/t4LvnDhxVH3bZcl98LQrPwvyBsiHUd1EMtVIfwbul4vWqPJVqdVEsaxnL+uloDvo9vV5KZh30eG
KDQ8kep1l26Xj23NASFBxLEDbpyPoNBPdXtJhn1/1T2y+nIFAIjExkLuIzSaS8FoZa+JTk/G+Qt0
TLN94rVBDI6yiPbPK8ESijv16A8+k1jrNhcLGxflWYxmEm3CU929jrVJDj5kCMi0T1ctalzoWctP
2+wzDwTQTGn/P6Zuymn5l56J3W2ouE5gyBujJcMAe7Ot9+gRayz3nGRtqFo9lLFMNANiEOs9y4Ai
aFumtT/VH2EJBvucfi1U0wKKduXqiqbhYUKwICMTn1ywjCZ93NnXqc3a/xAIy4XpXVq/tSxYQy9L
pRRwAfs4F8T/TNJ584XRmjKZDazvspPJCIeGYxU3IOwZZ7MZ5MxDSucU6PKRFzqpvl33XzLBqbq8
1LkN9ld1zoYQQ0f5J3iIV3TK92QgyQm8uzKFRO4fRF3okK3a8y/3RQ9fQ883BWw9/ZW2dkPL3AbG
zoahZQLaJNnqIqQgDcCJRQXQpjNrhLvpFxCp7qB3cAi7kjcATZzgg85xaPGG5Swdwv9c4w27bVsf
5JDWORov2J1/aS/JByLtAqJtpG3fvaJUkGpH1lD4oht0ON2GanJ4+N+6wL4PiZ+3rgIlrYr5P97u
URq9zAEhyV8Idlj+l56eRx5f8fZqtFnQv1iukze2yX1Bl/FjHvobFMnbeng87Fyc0rkIUSnh+QMw
I6MNpyRFA3YUcBkUC2DZG8PYhvukVxTnfTXE1qWKBzqqzVaMEdx59aPEeQgaTu8mUYPRQARw7p5A
k+mca+EGjRnKYXCf+tyKdo9LeLcG8d5dr37xRpQ3jhayliRGoyO078RWRhyhepamfosAZSFmShmj
Y1nGfStK6Kk4H+Y7kvMWSHzK75oNQirHu52S7uXZhr7ByDnnd7ed3G6RASV/ZhROwYwOvFM7y+P/
Wc08ogWz1NCy0b3Z3suOy0JEfza8uOcFEmahOJckuvMnIKIJyRdMPuivNO9y7a3fSJGvGVTczOnH
u+fYhe7/3g866xVz9iztbPxscYy2FuhsQGvdu1SLSm9e/DNr7fNaJnEA5/1HFyTQQJBsEvAaBfiC
v7WQ9NHbrqcs0QbvYkD87oleEmjiSYcB64K/KhAs2QgE686B/h/OVVeo4O4wW1XCoZ9NVW/AxfHj
1gCESPYZxtq7jarqn4V8oi7nAonqHXnwNaHYrX58hpqD+x6Q+zTHroPwfThzm12yJS0VqKa/5dL4
d4y6l7+H7RkxMJDShZXE52LRcTKckZdhOtJNI2npPZvYk2I4uHgJ6RWQKIXpnfJr7Ynxp93c0YGH
skyi+x/fuKMnukQ0EdH79Y32cuSkV36t2mPV2gcKGD7o/DbfvO5iFtrK9aSiCJbmg6Kd8pDE1a7L
6dnWW0uhsi2w/f0RFDWAvS/o2J2M9/1QjLY9sCLo5lxI4Q3uSM4yDIm74B/o3qAjjdZfssNS0RPo
JbwTlpzNPUDiaHGTkHjDJpffakneBVEvYq6eCvgMwBgstUP+laMuFpTFXp1xjlEJEeGMqcXsIuS/
S1K6c65ldY3f4GdxoxtlhcyB9OPsn/7FcB7NJCGulIaBvRXiqeDmCLqV8p1dNVzu2HN7g0cCaeRP
x0pyepomIRGuFEqfEEPLlRjkLDIEi62CzPixOkJpiorzvFievcv45Y4zZoedaFBwbGlgb1GncriC
eg1OrFJhY1pqfTSU/rZRSS52z05KzlvXHx2HOU3nzsFeeLR2tSPkz+qyf4mpY4zQKEqAmb3y0ynP
XdsOI6RAao+nYNImC6kJMXScGFx8WpXeOzuufOo2vGUUq0aUXRIXpgljs+hL6IOTDeZFV3TUPui6
GXlwBV/3oAMPwgRghUt5u7iDnUsMOJ/JbJvLJrRVbTrjwOdlO3I1xzKaDGGc60n+G1+p+A43plKG
cCDySOOsEOlBsS0R1yTAsAvNMhkGOSXEhp06KTh0CDOYRVbUiLWo75QJOLIInX6eNssli9YoB5zF
ixkJ1ayYDkMZ66qHZG98ShdTJpVXUMITWTgvqzJgGN8HvVlPkfBskSSABO2+Sr6AHOa5tHZ/6wyq
dAiMS76WKn7TlYNAsKCf7vImJYjNzvyCOuPIvJ+1mqbBd8TA0TY/QK9UUV2IPMR3D4wpAKEcql1J
4+3+zI4aHaBewOPS7k19RhPPMRlMrGVdWh3J+qMp9OozN0+2jr1tMjMKM7OvK5jrDnOVpBeKM8qA
D2R+Dnz+VEG3wHOoYIRme5aqKSv+UL7qwZSkFkVcZ7dWo1YHwC2QDJyHLNbuK2O+2qhFk5lAAoSk
zIGO+/WYTgpbjDIdwwd+ZrKRnfmZ7u2MYBo5/psmXXaIh8rxAlg98v+IloeovtlY5UX22vO8rzvT
VRVDzXsQtQSoAjAed3ZHZWpoibCa/6o4kb/5dexjDG2Kq4peUmC/4JYZXBxxVny2+HcpeI3Nc4ZJ
w2NUK6g+EbVfHGsb/traBSxS/z+xgI3YLBxfms2eyCMGdrTbzfWRiefmMwdZeJ8Wm7kTSfASbseg
33lRzZptLDBMWFqvTDhuB043kl9oXTDQEmC3GAnOCl5iO3Vv0L8vBs7B6rJf9E1IxCadZlav5T5s
1aCuPLx3JqJ4xsyyP4i8vSBUV2mXTXJLG9lge6+7Nm/6Z3kgGfDygNRnCKjb9xorBmdCeIZ/TcCk
GDVedTEMXOfMNsEFcP6fOZCoA9ielwTRRgSai7fIwF5/u5M/1sfDwfJVa4fsaBEka7c7G51NzU+X
SptqCNtYX3m21USx9uxfIybFhRqtAxKtJDxzJTf3t+nxJjqtW4wSbewkD3J6FPtwgQcV716JIhCW
fIq3Xdc7+VnYFuzLP7rKFSjEZHYfXmQrQ7Vf6zX5pPlWqzR0X9IF8vRhnlPfNPHd0pSc8bue/7bC
zexDpxWANT1wfckXPzTmdLcMgopnChrLf2KdCvZ39o8+d2NuIfnNPbfJM2VlLV2KlYidN17z8f2B
sPI+MrEb/j786Smh0y8OLxfJddVAGRXMBzKm16O626zFaI+7ZUdvFsiDU6h0ANoOzUCnG8W1QZC3
73phwTRSDZiOvem5CD7tZXi3JdYaClFHKukP8qiDgGeFREye6kLzj7oImd4Qju98NvFLuWVLcuZ6
nntYxT0vgDhbCPeiXFWsiI3qnGcP0iG4Lg0serzJe1oitox86tOEwvb9QXuOMmoCy+wm0HjBoWqs
bJV8wJzjdNBZuEt8D+69cd4vojKPT56qlurgsFRZI1ckoo0I/3D/BcOhm/XISIJ1vXXqrg0VlvfM
+yTQe/0BdHgdcxoll9A0MRYq2WIpftdqzMHYL8n2ZnZqEB6Ud7544i3uxt7spKw8A2DK1mmCy7Kt
t1rJmxtUUZFm8kHi4kWCzRukc+C0j1wPMpGCr2KQOvylLRIZLts6mzC86hA1cfAMaaW+cSWvGpW4
prCzTC3ZUl3fQqZEKau0n41BxHC1Wx185LP9ehU1Ws/3YbArb9TLkQz7AcTfn3NI8o+nW/AoVhvV
LewqPYjaxWVkHCyz3Hm1oXFZ0hT4IqmXjbF7KN5kslnGgS7GdL5gi7BakM6jfIBvHtfa+pUYOZ0b
VvgA2fi5bps2PpU3GzlLvzOgZf9jaTu1YIzs534ckUfM9CNnnnH1IVWey16dceWI8eyZaWPILc46
k+YL9oqWNftSUlsv5bjevIsDv7hiwmHYpdbkCh2koCnmV7SHku/CMjlFTesyqWb/s//Ev//1bhde
iu0YGYlQHokYAK5XWQ4Bet/PfybT1AORzwpnAuPLldKV3r46KbXW3d/6Z4P9rkTl19jupkP1XXkN
qkh9VJFjY6LQYfAzHxtEQ4X9SZW5iyYb4lbWq9c1zTxthhxu433NTrlgNLaUj50Jg3P39PDhVGwH
IwK1YtQmAxM5gGbKEzoHjaJqpjU2lbyuNC+8IqEYOxt0xlB5TU9Mqbv0R125uYTL4H8q8YP2aZmB
xUkWkYjWHEsPHQRYSEnVGFzZBe+3dOPPV1bY2WKcGVNKq3IdvXPs2MNExicnSPFXLh3R3gOmXCSn
WEdOtOS6wnOyaReFVz3h6/BBl2R5lS8ewpRZc52sSfPkd9c8lox1MPptVidTcOb8vs9ET5KSraGh
OI+ZXJ55YNL166a9jh5NrFa0wzNU4Bh8LcXFDnFJzBTn1DK29u9+swiYY3yaCymJtyLsh0jWw5eS
Y3QxBNzyoW7HOJcwEuUdHBzGm2oTmh0pObI25f6ZXc7utV/5D9vJhhnEuOHt+UfNY2oB84nujtJ6
GcNiryWhh/jJEojwQruyXoOYjb3SF2cFfyfog0G4xnUdPxqYS+xLUZRxu4/KdGPrUjCM8gY36qRG
dBN1neky7nHfW03m2059VY26A05KfMjeMlGNXoZG7anXYoOX8G6FKmmfscp76N7l8sawslLZ80X3
j6sL6l1x2v2M0k3CbLsdWRpoW26GuA97ol7dw5om+12xNzXzybQLeyHDJd4OERLO8PQLmQHV1INf
DlJRSAL3gxloJvLxCpRNY8zx57rCGtbvxASoBZfkBS1MGBcNXqbfoTKyJYEgZOatLmJ/z/wLW73k
nYgF3qRrv48gJg4EpDmbGd4ubn2zFScREJEfr+Qrxc6KXP8rzAFKcMPSjzgtmr/zS0o8bEarwx5J
G0L64MODcN6tCUKxrtKOdVZvxaG67OtSzx537XhHXLHlEdd4W+DKwxkvE1Sv5ftuf/r0cIG36BkR
AqEiaTRrSsSXh10JRJ+vDRukFR52iwYSe7oM93ue2X/ZiCwGKGtJjghh1cOfV0puIS/IFh9R6fos
eaGIACX4iwcuZoVrOH5vp6jEHjA5QJU+09PNvY6LgcSF6prS+6KPndGXznte9fUVdyZPnRQ0eIKz
nnvDhBNNCC8f8rkpyUPBF9QnOQw8j4Oz3PT1APUME+MrY6dk7EEYUKEEwzFNATtRWfveG/a1/NNt
VHQ8UBwgZFJhehl4UlXB5xw883SvvITne17rHzg2rrbKkFDfRkWnZs7n8pm5mPTaC3IyxL5Q4sNW
o22V8mNMMkCKdbjo9HYbZX8kKDtyiVEKofBpG8m4UWhr3vnk2rBjajEb5MqYzVKmVmiIDyAKuSJg
uaFwq2zFXAawr7rBnnNa7KfmyDUsaTnvmId0G6ntTWBBMWWqT+Y+m/SjD00OyuTdIsE8RzkxVz1y
XnQuf5ymq2PGJOBfMhT7rKuQgYJrdH3MzjkmH8C/K/KebgcLq4q0FM4p3kPL0BNetrr7jm4l0f2K
e34WnwkcL8gcKd+GwNFTTjkZc2WCYj9Xb0G6G6GOk6OGZ8HwERPp4QOGo3jqR/+u0TSHOelPrkmc
RaMP91qNvZh2MS9LLA7YSFFnESem7Pa/D2IM5tAoP8Ogh6pl0U02dThsh9UWM/8sdSqD9aV9QMvU
BSKlKIZ1EP3I4Pf77XeNcPPywWkJA45Bigr0Dn/Y7S0HQAfwpHNfdzG5jIfHzQ9sWhems4TWD58i
cXnEl4xDjWhMGHC/ICuar3eXx/pv61d3gDYeneFXg8DOnDUqtinNs0F7fMXFyoEMNil3X3Pwf9W4
rhRU0UImyTnVfpuCcIEmgxkS/7+rReSCCk6jTfofMowdQp0qFE8iOrxe6+kevMQB6YHdnnIc82ys
A4B7KLLBlboqfHiv6GIxq5u3Yuzw6AJOTQnpdaejwVgxPLoR114eFquSzReDsFAohOg0fc6Ahyvs
7Lsxofld1G0nFgH87E6v9dfaZkyQsKmLRQATSjzGqKSp4ubELjR1PUVtrniLnmPrxhwvMVEsYR4Y
65VAXHw513S+1cVH+IPdYKinCTxr63NSVGMBYjLin38791FM35kOQRU6gEQicD9hp1vJaH5m/Q1B
zQd+kLuGk+f+9IFFfuzj4W+5/aOdoFhkiKXc2Iw/WYEt4MAxz2Nr0HJf2L5ekh0PpLfot5gyDII9
VyEPJ437LT7qQIHR7XgAVoKmrGesV7zHXqJwog1W+Dv5MzNV/hZEMeQEk7wstCm2+B8Sj5Khri8X
5TsFKH0ApJM32dJ33Q/LEaDTXR2JECxmIinNepWN1XFKgru3NGqaSspoCyv4cOFY5ROL/itnwj0a
z93S2RSyEmINxcolETgoZ7IHkVUYqtnkrWHrcx3fE/2//YBVeht2cFSCB73uhCO+eYgwOygZdkgl
6d8+xCYqCRKIgNy6lGdjskICy9ES5HgBizEFE4pvxEW4JsTF42BjMA7RHYXBWbE6vAR4Un57nI7t
7TG5/+yNyps8brqnSxF8wyU/jnwpPjrF/gRZOqdr+mCytz8O68bCJYU+06P1vO1IobcvsWuY+HQg
/bQ4omAZ1q7wJkIflKpBnPVLHTCxkcbJIdLT+CG8wTh9ZVYLiUFTNKfnbUdRwlMzDiLvYzEM5E+S
JuiTHvRUQcz0gQi/i/IFnQnmJ6fTapsX0+W5fdeoKePGmJfa55t9eiGh3c7rvLfyzSL9ojtnImfg
QjKNSuGdrzUtrOlQd1llrisBNe+2s5bZXlRL2562CntUvQIz73SoNauBtlfA0kY2b+b0z3+aY7xJ
Lcet4IGN/N0jt36wBv2BHCbX8IDqfsE22o7uyo8d0RyZbNJWizx9P5WZ+z7EjbFJelj7E2WI42Yo
gLstLtjVKTnpBOd9/cB91sLJb5t+XDrspRRXmUCE9pDCACcRevP/sNMzAtWPOwHXNp284P6VaIJX
Ga+4TuAULfCP5N8rT80gI7H78In1sOhe58WXKgaVy/WNmJRycIyQDjMTmuB6RZEsecKrCwDRVfuX
1Yx7dB1qQVn6+vMy58dTH3czuI6mxswxg8aiy1Uu2hAyXiO3IO4s0eELL/cdQZ7FX1ctoZjBMqSb
JJXiOhXC+/j3/YHWvrfKLMi7ATdlwvh0HI+1rz04ZePSngrH4qCrHaEWLp1wy96WwKwn/u6XNxXK
HIyc5JiUili1ZszP2b+EK3nqLYtKce2qvPVAWpurS2q9vhjYB9wzqAcgZdWl5QwVRQmlXL7kb+O6
Q+9rqFr1WANjILfol0jdi4FnqGlB1E8XxmzlUH8qixirlpaJdcUoD1njSxcCfsu+xJbOtZrsNpzB
h/1VuXGRZ6IdASuM1TC9WdnOGtWrE+/reYOnhXbEg+MmL5AUA5Fr9TF/ReOci5qgMd6Qxo6rPT3x
ogCC1w0j7GY0DzqksIw2yW8CKNkRoJ0oxsAyVVALVVsU+Se2tAjgLYqwGOmxz3nEYlnU2HUtSNzu
Ewo+dhj3tRB16Qa/lD1EHgXM8q4cDr0cqxP8MCGNcxQn6MpbBSpYe65K2RAG/nL1Ry6Pmjx4C+f5
Cq1Mt3Dhfm7TIQ7kJo0etsq4eKk/IUaXJkQ1BDCA3Xpfi3eXNGiq7lTePs5v/LlHznFIAoPTHM2C
1BMHoHU7Ja50I1bfK08lBowmJix47TyzYfcbgXZmwGJ/5ewrD2dzSabCTE3Kmp1ItFPaS3dP4EHQ
NZWVtKJA2jdLmiRvjHNClTIQ8NmPUCFfaN+VbaK+7thcqLsNsqID/AzxUFK5+jX+NMnCado/0CCz
dxYIPpUpGAHz5YVuq9IKkLsfdXClRb1s4ytIWhjRstqNHVk3++l29Rb+gFgI5KwrerCMM9t6/BUn
U3AXVX9581RcIgf+SuAffMD0paUWn6dqzGTX5fdUhGgHyMcs/OwUPjNWTQTT9DEkLL+RQ+XJ2ynf
FZbrB8EX482yTkWzP2YeraLc54OufJfI6MrLejvybXAlRCwvJFR32xeVvzms6xunaAJb/w7G8dcw
oUDO2rZdcnTnR6O15S1F4urN2g/rnbrVaXkGc0ko4plwYKYRfjMwpCJ4yPjwle1qNt7KXwxwL0A9
SzLIF2tJ7+TgO9O2+OzwsuLZ9krtOih/axBWU5SJm2IY04kJQ8mLlpgwj3swz5/09qyj/RzLt8br
Nu15yomdwwpNGYSt1g32OYGwFWlqyprz4PmdxyF6cQAjo1KN7itC1i0PuVnWcUx0j4KYqL6J4Cwe
gRz7Dlf06bk1DgfeMI4IeugDjfI8R8dZme+ywfVqsatUWc9P3X8K56c3b3IEEZjhjJd/mUzHkNFw
vMGNdx4CqrjUB71TvhdFc7F00B1RvDf7ZmhYstoJXN9QHNSK92OKminD1sHh07oNdYNGOuVh35c0
jTPy6Se5Gy+ojEZxU1XzRnXExmtTvtze7xKCeggahPJLfXTzOIVhw3lKvHxC+oaLBeKPk/YsZBfM
B0v3iMNTHECxTJjBXW/4aqzz3tcVfcUJ49sFq3VPXp8C0sg1x2GuRQ5RB/pPFrvByuI7PY7UlKcA
F0wYZUJHg2jnrJuvJAKfBNvSwct21NwPmvj4uRZEw1wiGBDfksVaHWkPhx/sOHCLkQXlTxLTaXfw
3rOeafk8g78mU5RLyb5a/D8I1Dx87dNO5iwC2e9IwmI1w4CljcUpVFKdR5dC57pqWJFiJ+dFI9Nu
GyqSYhNa/fRfkQJ9kRu9OxXyKGIBa4bXAI/ufnsSxnEn9vG98RP0WizMESztOHnEagQlcuhmNkcG
PRgp7sAyfb+ehaawA7ygDIwwdv5Rfd7j7sqC9dQi7ZZR6zQAVvS8LWa0wA/udWW2n6ytH4Pk2EsB
UdB2mOsVyw+K0JoyyBZOqPEyXzTroNBWNen+HlA3wE6e+/8qM123EwygEGkHoVbHIIzQKDPWubfI
u4AauGaFvq619LBu9Sg7XbSytJaNCiqG02sZkKFN3w/UWqmkRdwry+rBAeMjVzfqBDXvawFPvCbt
fUY9O3QKfJJyQfZi4QckR7/mRkwLI5HNV2Yz573Dnmv/51F6wFlJ1n1E0zsIe45a9nOA3AKQ8Rwo
gQvTI83r2Ua3aavwmNZ0hUMvoVfkAW85C+tQIRpZJbHFrPIyStwXo8pfUdjuoI26CJ1UYebH1dVk
la1iyYMRD0VOv93iiUwDapvXI+VuKTVMkjM6x+n0jh45OE5A0u6W/JzhfIPVPuRXrKeuW2LtvAuP
URsPA7QNbv0TIpB09jNVdUZMK0CRWb9Ft9xgYXVfnLPCt2D9RK0r1JToK0CF2qVbphu7eta+ctmy
IH6gHVxspmDUwiQEA2u0DiIXr6D2Sn3geNdMuvKngqR0bdFdzNYMkFYYeOWu/FBDnyKndGrdQGWf
+KgAIhh4m7R+G0sl4LogarVx8SKnu6cZtv1KjrVhMSalbMZ3BILxY1PjaMCw+NTEwcS8GYf1dAlU
NipzbjaMvWGmahQwhUq907Mz6GJfA4iBy22xIpVQDuXWPem1mcmvO+kzPmlUnw/zXLmQnbcO/9FI
7gTEBp/4a34J7e6lVX6f0I52/Ly1Tgi6J1fdzppiMy8PXmWjpIB/g+25Xvf3A3foDHnTcbMUSkwP
+2ZUNpt+HsxFLNQeyyXofVEAAG7Jz1ECpzQPAjdXNxdDnfcjpLIaMc64dONHs/R2qXcU4Ufg6GhD
VBbN+jib5y2bmNoAC5wbTglvaiyO1kTvtOAGBtoGBzPElZwHPonFztzU72SAOVR4xxND9CmrkChG
k7BSkaDBAS4C7KTtGSEniUQEzYkeVTcvjkydzplT3ID8h2YrnhCXrzbjNikQ8haAMv5m+FZS2nGN
YJt5WpelgFXW06+Eh1QouFF7VWsH6GwNsQI4xuwebzekRB7ONGDZyVu4ase9Uo5fsQo70ZanlJ79
X2hJb1sSiQ89qtkutEdIECtEwVq/inM5FSWp36zv8DY19ZvB6bChgd/bLdsLyedGxqkfOXIrGg+g
7ol+a9Ebv93ccNCwJpFqwCvymIJerY38xSg4Z2jIhFLQQPaLD7TqpbqQgF4aLUpORRtGwweYxm52
b4026ALZHThWGUmcyQg6P3ypr9oFpzDDwlBrRT+EfBNMPOEGJVRq+ss3lOhiFfqkpWWqzfdSP+Q3
0qjk14vxIw4pihkAbPMZ3UlFyHT/wya7f3k/pXinfY1KxvX4Hgn0JnXsguhB9iOL+q1t7cTIoz0P
qjtTt0UheXuuJyJF+zgmDU6aaizz6+E4qxr5Z6uijCPfZNWndXooxMJSrOjwSgVGTSK9dutT0rxf
JMQFMytA+rUZlWPeMmX0yXsGXxd24z0bXs4o5Bf7HHc/sbdPjgNL/1IAMbG/xo0KLsJy+JCDCcGj
RG1pQ/7YfNzB+pUfULUsYye2M7T1zUROIywTXtIxc/lM7pUHae1RHlFh/pembnnNmmzvvTs5phyc
2jONlJlXAHizDSnIxMD9+WLoohY9tCS6V3w4o9sm5B6rymJc6syg0KpT6JzSjUwYW+KsVCY5xZ4N
npiTfzeaKFvGbq4DLPT3VdfitLOZ9EryBFL9f1gjClpsvxVN8NSfATrEYop5q0RZ7Ir634gOcL+N
xJilCnMBaQaWl8GQXA+AKX+/CzcRnl2k8A3oo9IcoVcJcwYUMBxNF8Bq4V6vflajSfR2i6I6YYOY
1voEalyVYlfDOf5QRF9iBZxbahagDwWl5lR2wMbtgD2EhSv/uiD2jjCiVIpn6isVSgTQ15FHM7zw
y/s066DDFO1oE/CjkRlXpOs7Xs7h0aYS8XrhDZCNUiq8MM3+ghW3QbVxf1vwLZai05iPvNCpWA8x
ile0ptTAiT9bcU/s5qMPIV2HGWE8ugmOWkxX/EPe76BDyBn4fnYPBj3yldt4esHgWLiJAyEaY+5u
jSFSio3nB3j0LmO0DimwOvwFl3fvpVYzIvQMk2VQg/4lbgja0F1gPLor2svgGu76NSbKa7ycjybl
RF3Xj+hM8qSfp+MCbMQ/LHLWqpLouZvw8A+wh5/OUUWS0KLmb6A02PPoUQspgcSYjWJy3Vj0Iw8M
v7LEWWP+/1ujMXnQBkyFnL5b/KC4923jK9TPG1Om4C+mKTY0ajVVnk5lNhJxi75xF5CXmD+NdYYr
UPBBiIOW65QAkBESBFaOrMsxeVTNkpVmcOt0a2Xp5lOOpHh/5zGN/VDyJ88buyHSEgRS2VtWOc/x
HzvvGZTBl8AJ03QQc7uPsui6Kz8p+zCJLZRzK+Unzx/J6GZp2f80g1TVbgg0Pf8sGE37f+CfIBOW
SowgMkVbyykqxPkpVHmD+kK7VXlE98yg2U91FQArhzRMt+mPR3GvvwP81jKHC+6fO9CxRWiSvnVX
fcZteLh2GU8DZO/jP/edYp3woF5Yv9Sz+seXWqmJyJU/csd4g4k5/JPJq0t5POlEdKhPS9cLJcSi
NTfOOW2sf3QXAT1AYp4KIb/p4VhAjgAFABBLrb0NZc4rEY3Fj5xIfnyBbqiQv7M7jYvifcmgnnDD
X73veKfjtDc/Plyh4Vl0Pq2qXCzD6yLtpMRPS5Nso2PBX0zx54+scpvhLSSczmGL6XBxtvQO5QMW
LoEuxKUNYTNC9r+RaIEYc5AQpNKHYhXFS+ktuJLs4UfYZJhdW8R/W+E39/qaNKaBBhhgXeJEviJa
fnu6DgQNaK6ahpUftQqeqCtJrAnH9lzFOEBYakgo9fUlz+c8JmSUcVZy461zIWRNOxu5FwFmJ5EP
Tkq8DX7w7oVoLmnR1IRCr4/OTbGtKNN9qMGikj1M2mjPlQGhwW6IUGetk9XClNei6+rPM84xV2T7
gEhNw155VVsyyevKYwZzUM2ZCBHyAB4G+4ZYS2/PlDfkBIgCTQmFI7m281BelZfjjz9msoB93Nf9
OXX9E0qkm+UBO0iTRsO/cffPJWSO74P1xNa0zb8tkR683LfnEunLumDvrO2hd/ulTTbiu8fsoOjv
qoj4BUxLUV/i5qiCtCBD09HKLvqfGp5NS9R7YHk1fH1fWS0WiiU1534MCU7FOQpEVhSgteDnqvwL
b0acpqG1cDQQqJKOrMNypEJmaAQ3VzS7DgI291FVhU6YQKU8cilHgSLLQXi6JuT60UiU9dmtHBOF
QP5LaxdNpATB4O8ZMqA0PJ7lwQ1w+h4jOJmk8W/w3KG3XV3ljKbHsoNW1kmVoo5Tr8n9HZJTHs3y
OV2LvFP3xeo7d2ViaCa0lNnL3pv03FRyC09doW0tw9GU0S5ggu3A0WExFBxjq9gBuP/EX+9IE9yg
ugIk0eIey3jYdrJ79EzVQjmOlw3nnERuJ3c9cfC74KqqrkfIuvx//bgFgmgBJXAHDUPRgOJ8/rka
ABrKJ6aXIkVzNOTn+/VR5E7MXsNlTI1Ehhn0YpKieYt/qQc2pww9/qZrdRkj1YvmqL8rpy+tEkpU
IZ02KNl5ZUVHNNwQuX9isT8E5Tn0d/AjtJckrvAxJfMDj0H63ZyC6s0tFgGZBru+fvTRItJaEeuM
LggS7FWj7K2MHzRyH5Vwaf+mK8zEb0cgDVxCECn0hoN4VjF5BvehH7RpaHRsH+XkkjsH4QtQN3XO
7+/mvRe/j84HAlQckDDJ6WyBj77z+5CkPJrrw6aQy/EkSmN22mA2NTddYT5l/aTzqMvpzHT8jvfl
ygrkd8fmt8sALi0a0oUcFr5Nwu2SN1IE8EDyuX56WsavplsscKUf6UoW0AeYJTmTaiqDLJJNv9sL
KoKRIJooAGlBd0aibALXOVro+dCUBkidmQe3UAbH6xvsLZYQQfXTXUyNbspcVfWv/ll41C7Lj3mZ
gjHo1fqkLsa7JJBpGWLAZqwjf9NAEP+HTIA2FJRUhK0k9MWYWQWWo5Bbx+kkfbRUi0ixM/g5Yq7a
wtuGaOjMipDMxZ+Al8g/ObqhBaGOKtUXHosPJQnzKA8N9JzNZOBue/2YW9MC4D9GCzIN+rCk0ZL6
PxgIclv22Sbgj4XTbqN2p1dLUAMZ/LJJTuboVEn16uoGoNDHm8DjyTxArinJpGBW2QnCxLWQzQI+
2E5Q+HF5mYUF9C+k2JTusdzmyL7oas/r2gV0yq9rsghBGPZ/pNUDRiRJ27q/gCL6uwPmaf5OjRrt
c0zfd7CL8nYyIOlNccsR+WrBEkhbmOfKwkSZIXWWwfygotN+L0lpUHNZ9g66S/g/pLVARmjT5hKL
aXSXXoUx7lrf8ofsgxOr9lruVj/c7dlTBXhZCsG9pMy4EO/t2E5+9debahSOp9UnniGOhkBpUMAC
uIG1BfmfgK1zFO0djyX9tApMJk0jgGj4eVbFDpVO5ZBp2fWYfaBY/yVfXV/DCxQDRWSoMr+mf0Yk
NtAz2RhCYbn8z47tHwfFaitLKw8Cf9Ufx1gNykGKRhczezruzOTlvWqDtA0gjvV4nvDpCGkEkryw
DulWvN+oPCvvso5NCQcSWF+gcbzmPMc+EatdyO4Rmftov6jTSHpe5bn7MjNIldT3+6f2poH9lllN
ReRH5Yv6W8m1sNrA5wUqMnJi4zeckMwWdUi/lxcZE/cX4zgsnuSo+SvWfg2PYpno9bgrYQJRONtC
LmjR5CrHKWIyEkCA91/5v9KL4YQDThslFfWK5xj+xlV1s3+Ul7zPOFbesGMboLoL8ocV1mEv7Vih
vKMbF0VlYDmiy8P69695tN5k0A9oiZMFje9jWxMtMdA2mlASmeyhaWy3S7GMBk3Q/7p3ST8F1KCJ
jNHU3scrUTiCqJTcH1nJ1eJCiZnQ6UkgBNMwDiPSdxnCo/tfGSGPRMOlLh6BQb5cYB8yP7ZietgZ
uxpSV564wVymW6U2KAYDy5ULlmrKBAquyyG5Gkib/uyN9Kt2XvTBU2/zM5LJ8W+zDalWbnsAR1fa
+NK42lzY8MrQYIautO7ca/qkiQ7oce3vgpgRLGZNkHw6j9GUCIYoJxZGKkI1yp+40h955/lVzrue
U99YY0xwqgD9fFg6aDUJBfD4Y9Q33I9gNRUJYXSmGdj4RJoMlJkCTFozR5Cjm82aitivBvHbJ1VF
Fs3vjN9/ReDPtMpx8obykOKS2O30O2jmoX87679UfJ1+klrwbxiET4STuUwxvS++N0yJL+Pj5LEz
mx1T74xPxzkCVEEc/ATHLzYopQVJ1G5bRQfWkg14uk03ZhLPn8s2ZUMRuaO2jT1gID0yEMRtNnPy
4Rn1aPL90c7F8lVguQygUWQP9Ad5MYU/S36BuTZqIR+L9LMqAmLoeCrSB2T7I4psrxsVJQGBP2tM
PxeOt/LB286SsWHNNzAXD6ayB23umlc6H349r0Vo21RxlOE1kPP13AGNDfTg+t+GnYBMUUnOdW62
6SgPl0gdJ3Sk23dMOYJqtCMRHsw/PD1koeqllFktbjC4P027SDKldHupDEBr4/R20cnjkO4GF1Hg
3QScptmD21BY3BxqrERoJPjFajYCt1lOE5vfBFNIy1QoIX6C/leqVJUtNe5DMIlxXSW3/2v1VIW/
XtU3e1ayw2f4/WeCFAN48OfwZ87r9TefVEeuMbT+CmV6obET6jispruw5E9ZGx5Cp7JbGIWrwAVR
RAbvXVI3wQ9SVMchcdmyUCJJeNV4lXER7DK9N4mcD8F51lGYfe8+paTabwK1i1V4/GrVEFkyjcAC
F42MXs2LCj8Lu8gD+2+SYsAmdQ0bnEU+tRK+YWHOw07vPQh1AEIEAFkXQrbl9IdWgDWBcX0+YhIY
IGWrH/XdNDFGJ2VWGRJ/RpP2tzSAIM7bVQVoURPDRlqhyunRkQrdaOH/l+Jm3mnCzXb5dm39Y+gG
+Ca6DBzPPKaJoyueszR808bZv4y4e2KStXJJ50a0ofcQ8/Oarq/azvXXpWNmgQOUskJUbdwzkmFE
kD8PcCRsSN0VWfHdheC8AA1bvCSvPPguXz+LHSh2IeSxpZWI5EzRtv/KRdoj2e8LDYEmpoVAksQv
4a00VROBx0HkEG9Y1Pe6a5cwtEh4A1JdRFCWUsDBUICXPOFNi51IUF+YiYVdMS0aMzhBYCYpTt/w
sR78bEuahIx0pkNoH83cLbU3Ta217OxZdKzHo64zNQR0SiH6VMmCX/QqosBch+UPw0qyFqnQAJOw
Go1oulPx9PcpnmgGkkwUJ8Gk1yelY/Rkkru1QSu3Qmj96l1OsaSW4lM0KjSnvVnFPYex80647hEA
v4P7uIftoiEPasoU/fC8Z3yyp+uqsKdzXbIgf3G1XAecb/oRuYVvBh8JoNlLA6BeQgLphwZJiehb
AcTimonPVEJQYKEkJrHvLZb5K3Hq5o4ERZEuAQcNq231rSbVaGdOyBaucn2ZJvrDWXJFxdQ+bSjb
UJk/KyAqAWpjZD8AeqOCgPVcjPj7qdAoerhTh9gpcbhxpVDyIJp/usp9QOgiXrzG7Ss/7juPzjCo
f9gSvk31/1SBf47Rtm6yGYEZy9Pv+3e/M6qdIjT/EHpyJ+KqK2rqM/LlvkEhMDQhngKFFrONHFt0
xi3oMEetDF0bxeBOF6bK9u/w/NaZPkQPVw7cOPI+05q2l2gQi7Og40wnhJu88UUbOD2t/Pqowr0t
39MEh59/YdY9HWM8IetXpHpAj6Qbh13XR13YHg63XhcF/uKZzFGLLH8Iwc2VdPJalhZKQAE/N+37
7epOzeib9mj0I6jBdi00WTLI60xgMaMmRF2uhU30xBPLCBUvulOFgmDDhaMl1tF1115u4YQIOJXU
A6gXut1dy7rv0TUqfkgNmn4CJFxcKPI+nkv0ZRQTB3tT8pFwhWyoZ2jmrU7JVvAy12JBgUqno+pR
GHFUi5Qw/gfAh6yBeGqXO5BTqrqnB5KIV27sjC+mTsZpXyLMOTYG1B5EIRWAuazxK4vy6KhX1ykr
wakPuk7bMMy7SxPTHe/vwF8TMvMgQpppzzpqWexUGA+luKky0jLqZVGKtujTKkL7Hd7lmoo6iJh0
etGCsHDckyA3+RmtWJspLWA+ekfkPaB32EcWqX5CRgGtgytQ0EF/ye5ADkMIvEJeoJJLSOKAF/yr
9JpfK0kvVkiHgPwSGDqJ021Q0trImD3XLFe8/WmObWEge0v3S949r3Ci5RwsO5/mQdeAlzvXC9RT
kXhSPnkQbfOkajAepFCT0ghkWcGN9Zr6mkeRCfXdtBEH5ZT+aFt8FlXi3cJOKB1yAWtVpy2oMS32
hXiF9RG7SwsWeN+L0RmbT639aRm0sFP3TVNBS1DM2+1XsepLMCTbgDoqREE/DiQWhexJGzmz5XXY
+2pIPY5M/V+9+3Y3lx64joOzRE/hDU1L6SUCRFs9vl353mZOe+Q07+Ieo++T2s5dSxDvi01gCFW5
uK9suJaoZ67FcweJZRSnZgs/B7hwCu9y6tkVuWd+b5+Pt/IBwMGEt0AcVyvWZZTo19yjGgect2P9
1rvKLKy7zF6a/Bkdx3A49IOtHZVBYvUag9wO1hRnxzHYv6YsdeLdP93CwmR4cYZv+mPk0RE4QQyc
He7AY6v114Kb4qBMn/ayx8hHv+X3BonmB830i9D+yt4JGSolVr9xs0YppWN63vdySz47Yh3Y5mqz
dEwg3G0YYwwvgla5xvV1HVk48Kms+6EiWXUJlhCqLKUGSfVVJI29Q/La/acfBwcgx3yqLk9IV/Df
qBKl10yhQh5+SP7zHu4oZ9ba8chFj6XCI/H4McYunNUk0r5E0SLfAp+jv+v4vqO2fA1MH2ih2vch
xomC1s2yf/K4Ah69AU37/Fm2ES4TQjtIVFMnBnwRXfXPfuRYSXmS9v/P52RL7bNNz6/4Efjp9bm3
RKKmI4e9gI+ft/s+jx//Esh2qf4kAgKyvNb8pRi0rV9GG5aN0vISgTF+KwWn5HPgL3wCgkJ3PsZJ
wMF0uSnKMjcCYqhjDdbl+DHO3xw/Sm7NIxBH1XAV57WunkLHWABy2XOGvkAdvaWizlBrm3z+VW1+
PIYW/30GsojrZFUExKtY8r5PJwfgbR/5ObwXOoqev+ReuAdEa9g4bQLshuoL4nlhIUnBdOsuY0nS
k3NdbFfWIzEc2plRXwjeLn5grjQ4xAxVfDUB/yN+AyubWAKm5iT6rSm64X7oeG+kqxmaYMIAMrbn
KRl8zi2v1ypkTVk78VOgBWKXw7IXMYpX1rT/xJ87f2AdmgcaitxPQLVXrlIZb27aOs7DDwo15+Wd
VjRJPL1FpTykRqonN8AbtZ6Q7C6KBo28+JvyfcUSYNjw9q2ZApqmXEkLq4r7Y3aUCRWDz0Dlphme
oUSQeKVDHRbMXPSDfOXMrJvBOpZJgFsmytpJl+PCHAulcgsDELfMWmxseCu4+uUo22nO3l07vH+2
7rI6FDo7OKBGvQ5UCxCLYJN8OI+Yt05lLObl0LYmqp+97eq6YHcCrgG8fhYX1/vwPKY3JEhwLETK
Hk27kvwcRISPQEd5QDN6x72xnSnd8FIb1pe8IUUIgrbY60yPiKAD3O/KnKIVm0L/kX9yCjKRE776
N0sL4+7XIruwhKxiGVvFwTiIB9UZa79tXXyaBARA3QSq2GCkrZ9bZqrq00n01lcPD98SdnnmvaX8
l5O1NZbN1rjorwOOk3JcHa2XSIvQIzPdfh4WABIDhsPTJwoZ7UMAoDtcdbgFThlEhgOBocoljGM2
B1u9RmWSdF4ZYfaSN+MmTHksJbHJTNBIHTa5t5vuqDpt3Zpj/nkKYgBDXuUC2RBYPcD64Yde4LOJ
XitLNCGoUG/uHz1VDlgWyNIv3S7rqpapf6Wd7C4LBJNPFTdNC+zAPzv+bXzsyFz3JD8O2bWWbWx+
y5SpDtMlbgnMescxkprHnjKl3MIKfijnfYwnGFPckr32SqTnDbS8CLh+X4qmiEyODZ38Zq//OkVd
Xc4EY1o8iNjvQWgccVYosLxYSJSw4mitfCtp2qcN7AwB+gKhzp9qaOIIWU8pRbRKJ+cxgG1f9rTz
iP6Yg2CtHoJn7ZsqdhsnKXCdNLX2mWy5gPdm7BIQ2k1BHZ94ht+x6mxPRuV+W8DsPsGvtwpJcLN7
IDdnLVSzn2WnT8q0vW8xIpgvNVr34XDNEMnYvidVsmo3xHg5pV4ShqSI2sHYEtTVoURlz/qGNdAb
42kOnfeWgzodDk9goum/HzRm6yqWMbqgMpt0wbh83Yq/1Q53ElIwCvZG7UPZ79DQZ07ho3wXA+7D
YLDp3D+MVjp78pL1VsDeP/ZReH2/6DzjyiTX9D7vTl/ZmszBiYoBkHfKS2fdnqE1khNKDWnpczZ8
oppC+WmJzvXYCu/qIMOJ2mwar64FTLlh/wdy2+WeHcJw06rIi89x3GXZf1g34B9v+9KO3uaoGJF7
SlD0RODd5YWaXHXcmjJ/xFhN2jDZPDfcZ9DL/koXmwK56COl42D670jSTaFobp84P7vlDUyrm5nb
1V76N7zRVXK/PwwhZze1ry1rnwIAPqav8bWoaEL7Izp2dk0cz0HPOViX6nhZB4j5/5uX/smD21uC
lWqLIfJrv+0tEdZWf7kvRhEv44/nSXs9k9hnhEWmqqODec4FWqQCENMXlgmc0wkNl5UF8RAUts7I
A+ctVWTkoLRmv1ZFLTEDNYlrnLN8+BKpVxbbCjtJHiRNJW7xuNIOWyswUs05TptaQM9PqB4cfrsc
DcMhphZh6akUtFlLjVxYmBbfULoW30oucT6In1rMPOg3lgTdHT1/bNfbDN/JAVdSLQRyFwvPYf84
J42RVGL9e5cgQw1B/2cZ+dtZtAndFRPYoTmRkx6KDhBfJWZ0IMd5waMRC4hzf57GJjErbHsHgOta
3gIVc5QrXEeBGD6OVSQxoKttg1ql8g9v3HIHAa/RVsG9QBqOF5KXOuUiO4OPobaSmrNzeUbvInRN
xKdk+BgO5+t13ywLxU0APXhPG/1ubL9Js7+RACp3ywuG0VBHpn7r3tsQKxMuLUzHjPas3SQIPKzH
jcRUM7g/JgYlo0CzLJH4bAMzuciutlkMoz6Tz9hKsWLMzXoVVFH7CxzOBT9EzobVPU/uCw9PMwuL
WYQ2bRpuuf3Yzu8XK0KaWlsLYwBrCXAv/PfzRGL4nSKi/bQpywymNjPLLm3CsVxWaS/ALQhhT4TV
T47GHQnJFoqH1kkuSaDrjvlcCN/+O31CyCDq2d2SWhN4L9TYrz5G+8YHA5mWR8HRYohpbJOKV9Ww
RNZ/QuDn2UyHALn+6z0vOrbDL/wVQ6hcrRVPjm0K7va3Ua0ESBcvGRUrLlN1eXcccENy4+l7V+g+
mXsGKoHc2/jLZ7QD9wHbyEQkG5MnFe6vKloznWgvEA9CeIkZBmwjFOyyXQjp+EAGStYs1x2unyXA
iJDgCaqt9tPqYWQeMmH+Z1kaHmh/OFJornBQ07CvQhI0s7QScPVqLFdXjJ7ovqgQjaF33TNWY0OK
Z5GI9TVCczNQqs2u0QhOfTMR6awPfs4QirTE5nWjV6khRY1rlHqQnhvoJ8Dh/HLKaHCTzvn57D3G
7YKc3BhAk7Fc9oxTMK0N5VfJmKHuRDeDmBec8ZxmF4nSVzd1Vxh6AHgCeZT8dhlDefv0qjNN9rdF
fwChNmQV3pQHfab/TlLBLqvlBINin1goOqeIpuJDsx5Qy0Jf2v48mAa6GfXulnVAVoWAQTkAncm7
duqsf1uly1A34pAZj9Be3Xm17Dm00Fe9I7GkPSscrdf5eneedDJiZEK6SPsu+D0pNniBvEt0dQsW
NVNFpN1+zq+14VetEc7Frt/twcpZmx7uYpuJeX+oP5AaXW/uCEj//9AMts05Faq7SpVQbTgA64pS
2Er9/fnxNyfQNAL7Tz4CINVrLT/OvZqdCOHWsU9J/rvPcsetjT0zCjYWnnNp5KTW4oIQOicqSuLW
jE0d7dibEwYS/q/PBPf7/JuJKvY9r8T/1AlT6qaYdjHsgPNzJ2P/mZ4R20EXuFQNP3lp+0MXSFNN
tjOUjHVfUWhFCXOhAJMZGlqbUwMVTBYNumrodilu3s5sCdLpMCPu9bv1E70dEwBtaV0j4F74bI06
2kSR+noKA2bRzh+rBKUXSvJzfz7J4yDKXhXp8BLcp6G5qZSb8HnQSDzJE+kXuGg2rzUYYJKvDUq2
5cdmMatT516pCJaGAD74eFFhlWBEd9ra6O896CBBtD7AVcU27TgVWUdExSiwV6WNS2OrUnSDLRbb
j1U+GCwabj/Fee4JCeHMH1M4OTQ56BdME7vAr5wbBYGDLsc8JkP8EI2H+1zNOUwjhOTlLgviDQwB
lamLqyjk2AQptSsuVB77uSzLb0rCoHjJvmLXxlwbdkoGwtfyIMIrC2oGp6mntwe98HtGyxFSdJSQ
z4URckwaVWa2lASaG5K5NgzoGFZdpXSWzTIKIOSQcLXmlM/QINZ0hUnkwYrRN1PZ1Ubvb1gB57Py
KOpZljBGFtcpN5T9ws3ww2q0c7dEEPdL+OHZUKScOhJChrUPaebsy7nw08Yd02sQcolgD8TbUQ0t
Yu+StvFXq7bcipW/wFd0SYtaVHPwuXeBbEUqAfy85yL+2MtF0n80tEn19eGA/An8Y3g1Z9DYJ8OB
vY4IC4wL/f+YbNSA+mhWVal5RGFXjiY+TRXilzrh9HBx5FeeJu2uLcmsdIHLkDrHwiIftBxHZqUf
owb4mGfJWa3cDX8Z25uZ6633pYUUjDmxQibecZ4McPXoXeZIKXZlgvVA5Qr2eho8zA9NuDU3kfim
KpO2ZDG4E3wOsWRe4ujKv1g4KVtifDizLJVREdmx+2Wob3lZ5mKNuM/UYAiv2cpawdbVYNdN5nmg
LRkZ8H29Y7mLoXeuhnC5/t2nMN4HCCdjIs8Yi47YclH4PEWxfDDT0CYwZJMJaBw/DD2h1kL79l1/
q2dvlrq9DGxpiU72d4ZERFlCZkT7X7Vee/C/menHrIIQUhRkNiYNOLl6rmWxLfGxjbVfS1chttl5
Sq0vF0DVs8T4kOCT/dzjqkSFcUazE4HSt7IBSXdNLekMclUqyGKK5ciu7Dcq36kvqFhBIcRmGi1j
Bwabo+9nRd7TJQFSAlWGlnzcSDlI1B+pEbZJjY+7oz58tcavB2IjNr8ziW9ZksZge763hRsuZt5w
pnQfLtap1ZzZByhOUVpbrPVYELpzS8vPF1VAw53pmqkjMqYxnSkPAZ0hn0W9jTwRUC1h9B5HtlRg
3WXK4kTC26vMMf/OxtQn4R/WXeFQsWgXfJDxnZ41gwz9Ro0ZUQZrASXC15xdDBtfxsLYvVRQd39I
ud9REuk/Qs4I2on4jzAChF9UlHbkW+n9xs2KGBmG9em56e96L+LE5bwxxy/2iDWx3zJAeGpc7EZH
rFGdngW9FL0YTyp6UQC21e6Q3QHwXqWRa416WtvSp64dPojn9rFZBXfqJBZ6LplRpziBKC4ZmRPB
QROsL7ILvL2KVOYHyqXqwfH7QBJCqryTSanqIaBEkOk+JURAVXYHCOMjBDO358x+2yaQRRflJwjM
iAnKwVVyZidzQp9aDf1FDppw85Pcn6ol/R7SZm5nMkHB/LDjhWKCYI1QCvIZoZhAPMruiC895T5c
xXaK0MuEbAMDz58sjWNEglZBeVJMD8TspLvT9nwQsZnkOMXZVKi6ddN7GmQ29bHW5TKv1vZiBJXb
1X4v1eEjYEtOHjIDI5VooOgF7uVlHSG6572p+kKnC6mCqC3qhnZi3jOWTsdM22Cix0qUyfQ6VP0q
RVbcFZXS+GnwUkWuSiDJhSHcKZu8y4JxY/idXRVwKLTaSnyaZd7a/cijwzBGXFil62l4Ku6VQfe8
+0aOaDJs1WFdgHtX+7T3R7nraaxeu9rU8GHOEhoVnzSBoWepwh78sQjzZf6ZAfUzhvaHT/DOg9lK
YRaIXMAWjYYW1thb0+ngHwBjCXw63AhNwCyZvAk7lEFEhs99VmieOniwYLRvdJHh1JtTuQnIHxA0
Mwl9D2GIVsI6OmoQLX8kgiIOljCysoX2ifahmrhAyubMaivrOGxMpYbQQQjt/6hO0nR5baU8gjCc
l71uxT1FakHG+ScUu58K2T9jQwC1iNWkppAmjFjzS0260nznBUVM4fm7ME6uczz75ypS3O/9Qezp
EvLlXp+3dfZ5Ave0HW3GoGH17jQN8NxWlnf3leKBl/r88Jxw0L45g9afdiiHRMUeROXIlkUuDvA1
Fp//QJpaGN+JR9oTNchjqt2dxtnnW387X4CbI+GFjhCmw3i/8e+by1l591QDWMKeQo0agvsry1n7
zMOTmG5WxOwBUvl2oeGVwJ3d0E4Qn4lUKOabeAKU2jH0mlauZzHj8/CZQWwqyoAjoj0E8IVNVQJU
gJXexcrOOhc5CcBBkY6GUuTsbjZkKm62imUumwwgjGoBfSXr7m0iqlJmln2MBjUfOWdKNMAC36L5
1GedG49/mGCvk9sLCPoNxllmn7vXiROMctRNU1eYN4rRqBTyG4rN5akZmPoqt6bLB43PAaFu2HCs
4p6i8kCyxOzUwsL5Xvqs3AAOFeMJEWITkwihfuYQ5+CXV5A2KE6o1lFmvt3KlJ+SweVEO3tqDXAF
jmcDH/KBEbs8cjOv9DFyaglX8ZSVG6IWe1cq22/OUHaQtDfChFW6/W660zPeFea7Blooxo6w3vG7
+YGfyhWA6PvlilBLLtN0hca0t/AVT6wqLKS2M5RIzNKWJqg30FINqRuEIebpT3ZTnJ6kkM1xuNS2
a76aubo/G+VXFI9paxtkC7BH5MzkFb3kAfLSFFvX2eGLfF+hGNP2hTUHzz9f+aXhAbbeOu90peRR
AXebYflTaplzA22PZIJZWrtLIUX0i7W2XU4ehipd6QfV4AukM4S1+Q48vxXwDhh+Qrv7YC3vILhH
s22EcfeluN20TWJNgDVzlh9sz67xwFpCJINTvlLCtrm5aNwlsM1GpHnuKlLgeigOg8W1Px9g0TiE
6snO/nHRjuatqwTpkGM3MQKXLLLW+Ub7ohRKaIXOAw0bO7dsEz1sjIrrFtK2f5+KV1hpHaAtqegI
3LlbqMnonRrDwGiRGdZICJ4mda/e55dQ9qgy1pWfzyIyPQ4z/xP+JyVN99yxqRFGHS4RDgvyEOdk
y3M4f+Ac1cbAP63DqxgHk3XIPfenZs2gwYpQ0eFBDQKUrAdQgpyXucQyEKb0E1B4DBa5ypK7PqgX
96/LWU2Dq9jIF1y4/rzE2GoohDc8j2PYAIIkzfa0HZAYzHobCU+gTQNwPvz6Dlp5um4O45fNRtjh
Jdqxo64r9Ppi1fppXqTKOaC1C5SzO4IROXxvqiIPpKEKf3brYvP4pHeohrfgB2NfBaXccszn0xXs
ucwvaJKHdqfRlLkIHB7tTujdeCZkVMvfwjnXN8TIHDiSKdNpTPJ9HuGnloe6b3I4lm0x7EghvRtl
ViZOhlMMMzwX4xSIE32zV7UeUk7SVBa0rEhPmJYaynvej3rY2UGOkGpowR0KJF7oRoGbdi5igFXG
PTGwBJi1NL2ZvfVTcOeW1SyAjad4RQBPyvNID6FUzcCEQH7WSNqMJhFnt7xTjWXMLQ5eHcp73b2T
4l0QS7NqW9W+GCn16B0d9YW0wP53N/qzq0mD5QM04D4e4cScToBydpHzEr59itxiN1ph3UR9R76R
fSkUkPuWLCdPM7t/+PYh5rg3aqGe4YIu0VqkXyGQiXRoy6g19/l5fVfaMBqXrhvFrczus7ayi503
/af34+9BUEmBbD9t1wvcZdBaoRMoG6dRmXiCQu6pnKo+3u9Kn8Y2nROmFQGnmzP3PnjtVyPvC2sn
5J57szwLiKXFw5mDqLgJ8XeJi5CCLsXv6W1xS7mmrHnMC9IktSIK6CXDkmPuws+pSTcvYekhx1SJ
aTdJ4GVUWjBwSGRFRKf9fqASwOUrAy49jW4aPNeaxWysqgCrb8+Z/Nju0u4H/LYt2ICoAtJ0Qgkt
16AfFhsYP+EtS7oOj3oyEa6jMtybmk9soWlL7xmScoMulKR12ZRzAOPJn3Szz4/4EXeUGX8y/n0R
2tRcQcnjN7j5elFqC5PDWddjOhSLRg/PRkxvnPndwLIJx+BzlLQhEOk8P/qy3wdfmc40pFzE5vqq
B0NDNnZGh8sZF9hTjutkTofjgqRst1x3kkja2jGk3Y5/kqDEDLpHrDwwKZCl8GDO63EY81etDNyE
7EjZR5Yg8k5n3BtkETbkeN/6u/quz+Q6vO8dqG0hLRvytrF+pfdouB8PkYMHRUIjZWSH86AfU7/Z
whdyD0BBsvFOwrK1qwPYW//xgphseYK1+7mnCSwWWmNkOWG/XzNpjbvGikX2mWVPnbUGrjzV86Ob
xJemH9k8zE8HMbMqWpFlsUncGPUdnZnQ+ibjiySfNGqyuJywJ6Z5kID0BvH/H1u+AEp1Hs2moGPA
70Y1CmXC6F3Nb4j/Z+lK84i/B9sXPZKdMv5+rRk4E5nh8K/hfT8jYmwKFZbyPDufQ+40uC2R65EU
lBsehEuX9MMV8lfPI+4LPftUKPjRFTSob58kRQ2gpYiZAH1Pzf1ggiBub53p6kzb/T4kHvbaOUAf
LHB/TRQWw09CescAtqK1FM2KVUKPOT2qYzeeuKHchcWf6l8OeKYhlgAcy0Lv3mf/wWWLD0ctJmoX
nI37wjpkD7XLCvlEic5WAqzaFiJxUSXPN3u85Blwv22T+FBiSJlUWj+nJY31KspfM4c/Ou1Cg+WD
Dmx8rA1/+herDyxsjK83zyJVjLJwRLSDCcPa5wgNHm0rcebt83jjOb8VYBGUpolkWFVzvYkJjnMg
ZZFBtjlNLUw1jfGypZZYwa1r+HXhajWohw8TWoPqMW8i7tDeUFK8kYEsOm+epj3q7M8+khh6yNaK
sy+LtTm3oc9PjZLPPlqcZQ6OvO/4WsI3/ustjij9QUj2r5KGj99Y2ivNuqaozA5B52KLu/h7EpRf
GjcaiDUQRxWCxfIfpl/nH1vM33/rCdNfg8pnbKB/SYIUfbd3oaZZpgbChz9Q7VMoQtrRfx5WkUf3
FnvwWd+tI8bZLh1w8vKu4hkb691eUxHu4Qh2JfLWpMVkRPmvXN7z/Wftn4Du3jLisl7k0WJJ+bCV
HddFVp30aiFufMvlwnmvU05xrV3xvMMjThB/kmHhftTfOl5NbVPeJR2QQsjUYpQPj2nC82qb1E3N
KYvywZo+u/EnR1DFhK/ZmRg6aKf5hsNFaCwgs03j9I1cxnRLJttzUafj+UA5T/VgIP4ptBb1NGta
4+XZJyBodEnBAL2+2BbwgL8FHovD58I4AWnsYWT1DGEkOz3H01hvA2Jlv2pV/LByfxS8Y3j3uB9a
eBNL04rGn/aaH0D5G7VhO0y8oEEU+D4PfTcvsWa1tVSbHero9BuURY9a7oPL1c4xM+xwW83G5+pv
w+E+jH7pNZ47WfQjJ870utxugzjrh3G/wyLkpyqxrqEiN/whKXKxzl0QbJAyNdh2oAs3WbnwSJ/b
zB+06pIVkfloaQpBZ+VL0qGu3V4BteuLW4e3hsX3s5NfEeP13Hc5YUwMxIEE1Ird6rnXn63812jV
xYKNUfBZ+S/RPMBdNAdITkfmrMGD+zx4AdCmx5ONLAXnpZzgtMuLUYc2gsVjThBVSgJGkT4BNmQx
vuPOcMX7CnKgogBUNd7M9I3oKlDXBV/2Bsmb/morCyxcCxE1cidmNnpm1okAgMmLwUcw+AVps4FK
1HOzFMeSKYoiHBdhdt4aS2oxzwwUPeSyOmaz/SV4Qg95zIndvtWb0xmM+TdxGh02uAzpJTqUZTdc
5U2Otb8VKkdeu8yewADirM93HCF9ZLdwjuq/HoeVusmvDe4VORFPZf7q8Ph1k/agdzUOkWSXasky
aXsoYRoAKFELnkEVIDybIaI7BiRu1HN3+Z0Ch811yfmdtQbBdbVSvaoSOUqPspr9ZO1WCskKSyu8
uKbNNuJ8WS4V+OzlEDE5ONJ0vWpzobJAYCVYoNIfdHJOCEdJqcFXMlxJVaqnMjY+/3LGC6Binmy/
9CMSTjR6fL1Bl65zQlIlNMuPZIkcgHPvUBhdICMPteWSWGGD81RmRy0bUsUqikZYsakTO2vzBr38
jpnk4DH1sdu1tJjC4284eDAGYGwLBa3OYrNzWwNKkyUXs7BxRhzyDpG3f1smgBNojMMabe+65cQc
kl1XiR6+im+hxpxWOGYITE9QxjIuX+Bydc1LLp+Jo0LVA6L5znsgROxcrSX2b6+Wg0wRPhZFqMAZ
GCMdh66xAmcx7+J8SEqp7ZBW0I4sNNspQxiEtWPhWSvjPjJm6VeRvZL5rnL9VNTVM2mJ2lidg7vN
u1IvFVf1RByh77Ta2EFiH474IaFHUZAq6Wcm5jV/ceRn+3OBNwXLzE7ROPXz8O2ssgx8NqBdCJEY
aVdX+K9h6O5ezXi+G2cGokj046o9LjLG361ST/3nhpVYm6LjqvD+g5JfUoNMrUG/8iiCAG2DMz3S
ymiSn8bJLB/zlw0TCnMiVemTMyFTz2oaicFefOBO6tkCrRKQHOJBtZyNcCqn0RnYMvvLCOilVg7K
dWAMLNOHRLqF6UHM65iGQ6O2+j5fBNan0xn5otLWaqJ4SJZKeQMjed7eY0IvTzBe37sAo7KCZWlk
p3CJXWRyXGE6v0s+pQUOQYeLDqjXafSexDLrY2sGYwM7nYvVGF3pLn/lWmZD2hBYrQUPWWqbQs0n
D1ONh9XG4r25IAuPykgh0qEf3wJuwICDBECppBaLCfNJKrbgODLdaSrgL2W1crFxA5dVu5mwnBsR
yD21UZt3T7a1l4jGRsYhNcpXrjT/GjmpZAs9Cp95zVkzXMYJvSBOIWtPXja55ShNP7Fs1wk/hCUY
XiLdbbTuaYgSFnIfRhI5HNyh+Mus36ut+GANhyuqMxXBZNhMVBiJC37uKfdwn6kLIqs02c3T1qT6
h1lHPHsnsD6iHmpQLyYpsyXep8ZUbtMnL9AloZ1pdxJz4PSwNEzu5hBkUNsjlEaA8/iX0nWI0W14
79n/MWY7Uy/3VUb/PdWXIpXfZ1ijW6TdTFgGxgoLnpoH4ndHDcL5j/v3Rf+aMMMZhWgFF/+HCDAL
q6Y8WDMrGH6nTFYUhup2dIhphJpKzA9BX1NNbF2CQ5G4BNHiCT1nFAysIEjsPEAHtzjcZnQD/l/6
4tzktik+DI7t6vbu3Yzh9Yl3RCh9ghIR04UQWvdUgHVoaqK1rDoaftCqnX8kmn/NUiICKF+VceTW
YMFBHDys/b15315/DAPGg1XztFZz+Ex7cfmDza7ZQmetNrHn92IC2uuqXp21Jo9nD9AyjuRu7B+E
O6ycdxU5P+rY/sG2zsFyPuT/h+GAFAM09CDqhTI3z+RJUkTYHynBo6r6QBmOb51esbCjdsxxIaZ3
dSNedhMBOxHkcNMUhf9PvMEHrLnz1hRrXCMKLFu/fo3Yeonm2mT6X1m0Ki/h0N4EgoqdnComy8ek
4UiiAT7FBHiSTcQQlj/yy+0Bl33to2SeFqMYSC4/A2GczAiPTfITpy44KDHRkxAPF4Ai/cEYuvYC
0ZiPYcg3ntt9lQKuSlKRIAyE9mYTi3LcKvDqXk53+7XprL55ZiKdUgQH45VDp5sosQjpY1/2GDhD
q4Z6PrdxMOggGcJMsX72XETB09xUaUaQSoHbIN+Pb5sXwDsCGwbb/pGgRlKwIID7ZIduChHp53Rq
n1Zu034/qQRCV5Lgtsw+2D2jhkO9/B6vN3HW9Bn3rrtkglrM/zDM72WDY5mcpZ787Qeu5kAq14Nt
1EOsurxkRMznJLIDIGiEeMWUB50dQ5m+I7uznaxORrQ9KM4eynzVber/hXKINfd9088Fn3h3Vd+j
OHn+hcm21sm2/hKARZt6SDotfF4bGyInFuzHIe43rmVHNTlA2h2sN15zOQYqlexAbel6llrX3FAO
JxjYxGV70JsD/taIPJbJQAZupjgLWaPhlsXwbGfdDM2o3iz5hfc366viXjg/tiLFDh0mGEX+Ak5D
RgEzbaCAclNjvnDh90zDVtoQb8J7Kv3nlKXPOQsm/KXtDVfK5enavOy4gGV+miiq+96KOzkBoUZJ
5lIPaQUTwQ4U8kelEoSQ1zokTH0zSSR9K6FvqkzcrdMY2BuJYYJTTbcOG+ERJsfj2A4KkQOctX3q
O8oOHgNqwm0PgZMiKAqKehWwxnIA2dfdTvEPMMnZHvR7FrfPmT3CltOW9f/sj1ZbNTI4SrQ/TGlv
BpckF1sdfBqvv99AihE2jxKwtdaYs/W+2ixaIrwx98brwQStB1bCuuZMbFrJZU9qfH0aWtLuTZJY
ZZsVNjPoO6JZMOVyqlsxiUUc3wdKkdL7trgquLV89QsmsU7Lqog6mDijRMnN4akqJbPFTv4xeRCe
TKKtO2kysFGhkApu75hA9e9NOS/WGSP5Em2Qj5WCs4kAt1kkNr3KXkj+a3ZLdExLfrsAvXa7paSE
rUd6QcLX1ebgz/jtBOy7TjXfYJiImJ9PH/6LTSgyliFrH8YuPTuBqDmcAz0/uX1wQcYJk5sZjGNV
OWtxYOQs0K3EJNyQIbpud2aM5r09XbDwNtYBCeONcHsL+FG4FNtWkDE5nBJB6WBP8F/+lXRaHiSB
g8dtPcUSRPmThYkRidG+dOy8J15sWNZK3LS6jImTzFN609hI0ob8vyZSY0gbyFPmF2+RzeOMf/EE
g7Lquy18PVXeXCbSVLw84z0XMaZ/zCjA1MntiEvgmoQX/S1WIicxAD7GnjwxQB0hwGvldTHqwsRp
px5HZZN2wUfcFUgiSd3m8Qv/TZN/t7jm9tc/IKAtcfvQtLSIzevGynoiJyPsvbZX6JbwWZ0uI/jT
mTtRkkafuPmtZLAH5iXgH8QfR4OqiQeJQ8P2CkP3zKnLgmrptPyM3TTnBZJBhMrpLj4UHGZkKuyK
1/DBLMF1mKXOa3rbsRMYeejIw+mQ5soBBUFGRZLGSmTG5CHYPUGacbHnDqux0P6vyRNkOdYwpTmy
o2blWuyckamw6OXm6N/TxeJiDLHyTTqt/F20yHoOCMV2Z1JreH7fmQUaTBkVnvslpgqnd+wSu9Jc
TMjbt+82S3DWtko3O93u5ln9kmkr7gMgLAx7GNQDSS1XUKHHah65dvyNF6V8hS9tovp5bOC2lGyP
Us6TwiyWXzOMzCLu5mrQWPDOXpLaH8p5mDdOXFezj9yo+G7KNo2UHrExCQobZqvzO8lwghgDmM9S
S+9uqmYThM1AXXOLh0ysRR9yeKgMYoAyM8/1P4q2In0N6T0flz310qjoKJoCbtKHGMScdV16dJ5V
KJpy21jfeMVPV4q/mmoY1iAq5Dfah7k11NhS1vMz3Gc4eGvUKqplu0ku0PvvC5vH9A5tvVReB/wD
TEzRfPCr5GNxXq6h+sYRpu6Sn0asjfuIIdk+92JkcPJ3/Hp1KTkCZy3Q+PrneJcgqLg+Yd11DJye
LqzfGSgMyQOf1kL3sPonejK+MAB1jjsGsGDaP50qS/s6u+j1Irxwrz52q9LPoBY44Lttm4uRSN0B
QwvruBqI4yYiPIb7foVuBl52dCJRSMAZ5kG0dQhAzOJhr0YH1eG5rVun/fP/ypTfMaIzw3nPZqjl
+t6+XtLzRs6bfXjTkODVUKMe7Avg7OSnYus9mep6JwrvbzjHYZqW4aXLqHW4K93tX6xZzC+XMhqg
A4yZP2sr9PSDGihtcPR6fIXaBGT/4TLASnsxOVbIdyQUgbd5PY2mxEk4qGAFzoRQxbXhiNQSGMD1
o0yjaVVydTfbIgor/FNcDcAnx1NOZ+XIwaZxWdqALJIvSQsgSjAUUKbM+F6PzwOxG6Het6u4pL7N
KfruzQzo2cAHYc/vsuJBq/2OxFEuuC9ouKAbWYoARvLW6CZ8VDsLMfeN+1yzXXYRTw/uDYNt840z
aZJvMkFllVkafqHF+raxux1wOFemTnFhVKcH77b/z6Qh0CMz12OgftQY6ZLWYpcS2ePximDXSiIl
1zdEpp1CVdWQcks6y79xvYQbzgcK5U0bIRAvFBmwigIODIixOogXHfS6JODlG+KKFNNRw9n2jPYY
ysqZLq2HlgkhrwIwwOSFo3ghaJd75jHkcVL2raCTTOHV4TYhYqmgI6uv8jhRoY8benUyT9cA7Qxv
Bf5Fd4slQOFzJSobeWGmUCMMBLNH4/LlcpC9MrGSIjep9oGyob/IfhWmBzx3mN6omSP77rUQl+I8
Le51vhVIKi0Swua+M2ElMK9Mq3XTvYXH6RRFD+VZC9LK6Og5k6cLgYK48dxVAsPUVBa+5te2QzbS
dP6Po+fuxdBbUfscWXVLBOLOZZ2QO9niCIBA6Y1ejdFf6Uv8HLQL31UZDIT/g1eDBcJzsWo41eq/
KTCNp2CnOAyd4LKo6yKyNhZbpYvnqT0q/xu1FjSxLLkf8d44bTbhIywOZsDFaaLGwJ47G3fqpQCr
ufVUBcDThvldcE0vG0V/YeZOx59rsaU4q1bYxqfNSf/KuHFRUYWaDp7Rd+nEV3JrlLCsZmn5//42
CJDci0AkATH6QOAy4FHdPJSsZIbk93rUteN7wTXrisRsZmaloRUiF3yd4q3Br/MuXFciCUlBMsbl
qy7qI6+sDD8IBWMfwhmrHs6Lw7DaLaa/gRAP2OO1bJ626gcvPoeEx3/v3E1isvZRyb6u/t7RFM+H
pfJUocMlCMXbmIUioT+WCk5c8gWJXNaBSedmVSdR5j/2jV8Ouz5g7VuSb0B8VgVidOTD3jgNioFq
WryKpz3miQLHjDuTCHNk+WXxxiNLOwRcyazLmkxNidMI1UKWSZbA1U34bqempD2XYeYNitjRwRqZ
/0a4diWpb91zehrkYaVu5idPF8jPyZxCmqQZSWtTQdpdWJw+c/7gTFixCNL/Drbw9WOYsQCjHbs9
zkSD8z7p73kU0ZuFRfWJ799kkRr8uYREabeQ5y3IZgD5cFY/e0zf3I4w3LjM+m9zorfqZ21jMDmV
OGpLOTMTY/DxL5w7wjT7qF38ZKg8/DD7180RgDLrM6KgGi4rQkxsSaSIvm8Fnr+yjy/Boi3NF3oz
BsT7P7ig2K1qBnx+sQNNvTwo0ozbyvstKnog999WOVTj29zzNEfysgdaYRCt6C6Rv8/iDLxsm6Sh
daZNqbsUYwyklhRN0h6ERF5anNJ8XNuTXh10Tbtr6VisjiDG7NKElo1HN62nuLXRWWHogpa/fcX2
I51h+moR+hBUJs4dq/6zuwGlwdIj5VdulFNVyVZWzIZGD1dvI4mCZHLQUvQFDDV9cgIxthmbw4d8
2j0pZdDA0jT0iLd6xxsEVbu3GEkdzS2LGiLd0LX8cc33rZ7QCkCLiU2iWi0cFwFHMP38VeQYb3kb
jNtMrDgEa0EWa9Zvr1A8DQ5krYGPjGH5YbqHIIneZVk6imY8RdB14kEuugh6gF2lW7q10v3ssX83
j8KT1U4s/U1suKo9cBVnqGucfXgKa6zOwX00scRSnG+EVbWzoG6y+3MQGkeVnnbljcwQ9lfh7EUU
d1d73M0gIt1auTyu1Te0ECjQcqKbBddm2n3o+2O0TYFe07yri5EF3LReZlxMQvilq7Ensu7qI4H8
YVtBvhyD8hKghXC2OU9y9tsewlOC/O6H/7DIxMFouJcCyLwnRfAqB8+Ou1KI2tV93uUWXIKZghMH
s+ShCJCQz9qeNHHaNdmxzHU0QaM6YqlsoRa3nqqpW4TZcij/DevHMai2Bnqlx7H+qcWHABYTLN2S
XlrsohIlFftbxi50FfRC+cvTcijuyVR8Uh74sQzjgu/6LB1tdTeVUp+904XgVPCVNtGErgiRvo6d
l48EJbv1xqnXeB8Mx8k2Y+lIN6dx//I0vozTQTij/vCW/kbEdQU1oqircCGGlNSLAZhEH1hD30Q+
lk3lB4eGZwP1/3D8bW6cez7u7KH3ak2sXbXd77aTQdn+QqK02MLiR/q4SwEIrzUBeGyAspIyTCA6
1w2hJv7yxaUyIeLZnlEi0Y2SJX1o+bycd9b6tpXWDquWYNoQatQN4uhqm5rVOp30VZE2RWiK0akX
xs+IDfS9q/7ZbGt73hnUS6YSd7GeutUrqpaR43x5KRYQ/8PA+MGNzZNiMBHL3rlTa68KBDjdXFw6
V1xgyjPRHzByPBAqmMPYBoAPJKBhgBQqqIW+nPa1GZ33ocjk1VTGtPWmnTzYEzcuU66n7KaumAk+
GvqkrPefjGcRWe7myugf2oe5lvKTSpFITlTu533UEFNB5jPGbKLqWSXvvEr85hexVLQoyizFLx2E
wr/YR/WTKdLYfC8Lber/25ThOFD/oFmcgaxNgn+2P3Uy5sB7Too7JA4M0L3cvBIITPlMJOqU/Vfr
AaLgODRYJCLsFhBa2txkV4MyopptOXT1GJ53WvaZ1eG6xc5lTBudPCb6c+fNQwyZR8DPQeLn5/oL
WKU83oYA6GXT86dNsL9doXSbnlYphS2K+nd3tv0+SBgIvF7BM2uPxFMSN8lPdFZQsImJTtzPrvBg
GTaRKMr2hbgUWOvykU1JorvvZ1B3KTbymlIdWYurYija55sEwAW+B4liVAoOkWzQuiq27ycpEF1O
Sl0f4jF5RVwYPRLJ3lreqANDAb3Iqa9NvDU5BRSlfeIYMQOiuFH9qbeJNOKQcjTOJgjPDIou01Ko
qX5ooIHVk7fSadukT0d9v24Kgu4JajeJ3+053QQVMNX/q5Ex89ZJRlwo19Niogz02YxUUVokI+Oz
glW8kG4wqYm/KevKnhmAcMdhnJNCsUMvdRSDDu40asxPWTvnkJYB0VDPlg3nVjRGBP+/XO2mmEIr
keoleLrwSSf1vtJOruhJLxfY8loEI2dT28lJcowvNqsF8tKpTG6oA++VtgzxjVJEJpZqF5vf9koA
qYbNJmpJJKJgVjdapaWQiVU2PlK+2Whr4yTzBMYQeukKtzloFoeN/zkrIu6WIknuKsTUpNFY/By9
xrTzDWuyUPzQKC+U4egSCi5doNc5LVo8N+75rrWqnqGpkdnsk5SK/+8Y3tuiIy01PUcIv8wSWLzX
TJM+xCL03Un/OgFMsAxnBE7lDjSEhqE1DVX+OiNIojWF0/AZEmuC/Be2WDuEYDjhKyQaFECdNXMM
7Z+xYkvophQsJRCrqpyW7O8vzlUPohNM77oNWY0YKnBrj6W5QqMgFLXrOEjz6tfHDixc80IA+trg
XDegr/Q5lGp8NOS6MXlLmDckW/wRYgNlUYkvIunaiKw5am41u3pnjMMw0sBGQCb8w5G1uE5VBGWD
m+v2R4bXkGfbDsJOClp4BCz52yTL//QZJTOJJsbJ4L+uPlyTLfJYsuUzWv6BX7M9MU5h8YJaHrUu
cP9HDYDz97sLs2kMuDfg5PR5U8KCFNDAdUhVPB3/lF2koo5r/gQzbFWW5nBO6F4ylbQY05cQ4PlG
yQd00D/FQrsQgtbu5LjOr4T7D/8zpTUR9MqAj9x3ARMAsiCJ4WPzqtu2RrvY8AU4PyShBYPv+sYy
NYkkyputURVldHvtEjZ4kpXLqzMPVHnYzLOpbNvBfZCsKSOxZ1vw4jl+VWtWAwqP1coa7AU2UaTL
LMR07NQR3nARXdXjn93BiJtSGxlzY/wXL1TjRb7aRf6Mnoxqroh0z0pRrQuyaBbYR9K56F5+f8fm
8IOJ9XD48WmBhwRBjhNLh3go7Y8/oUlBL5+7xs4bcMTzmFr6Qt3OR9QV1TJ65oSAadm2MWWYr1K4
yQvwv3iHJtYtdBt9Kh8TSDO6Okwiz46D5C/44LkL9J6H+2AM5RhDUR+mTt/N44cDn7RQxQZBGxOX
Gh+t1O9TCDuleI88NkRoGAEAE5qdxMCb3DpC2tK9px9Lvl8QOxb+EdB1jN//ILzzvXiSrsqRNT4m
6gegfnLlbWFmALO+wqHQW8MUIQzKYAfIJEnRAjS35QU8XjWEwAcDPDYLBFPjzirUUaUmTYjTZXnm
wKcZtK3bC4pmrC/S4VNuuMkw6jSjh0UHTjSWDA5MVbFAwMf9lLAsyqM0YcpXvsP12bJ+siVVMsgd
/jRO150N0D6f2MuMxy2oTYP3hRVq9m0xUhlW0wZDkFEk8YVV1l2ARKWIN5lVMmyZ+ghk+0NaKEm3
Ghnii7l5sX9JSCFYzd3+1QSKGU2btgbB3T7kb17zQHRQPtb0IldMoDOtChTDqFF/5FItkRBkAtbB
xiJ/RQvWXiAUrV303Hc4AseQQpm2aSLz4j3z/iMBRaSeebvltp/ntEnXsWmXGqy3SiDMV7hfN6uk
SCM2m3UYOeIMySMZx5nv3hIjwKGdaMWQnsnYF1inuuQxI5jGZzOcW0OuHnq7UNW9X8MugrvLXXbf
2FpCw4+lN7G17uaNmYqr3xFJaRT0uT32xAWTUIspYVvJXHOimcjjoOUFb4/u7yuz+fJ+4XX1g0QD
tEhlHtJeci0Yaj330JLZNkXqfyuSR2pDFm+6rum+BztQJHqLCWBEnp7BLrcSuwOqD841zUFukpIO
3gc/705L7wcoRmDKF6vqud1yn5IcuzYxjcSFgdhB4ZSgkwCkPkPugS7SKCfCNiLZoNfRt1yL+yIh
+qcpuw0N/TOLgMIMtTOhkJTOEb9D3KfdIdRqga40xLq4sKuoVAHVkqy7UFimliCxOciBwP1cGhOV
kcjgwnh2urLnUY5Ih1nXCkbEhuoE3kIJiy3apuR9XxJ0fXkIWRzeiE3xCQzjWKSJzWePigwNooOS
+BWd/yDBU4qp3ucZwcBv2galNTBIl6ngcT9cAIdSxGtYS4z1yPgSSLCgqT7ajoo85kzsj1RA9zGF
sNqlsEycQ8Kh9tZAreTTQrWPM6b8HkiUVVz4VxAAYRlGa0m3Xk7uL99iGHAbQtHcDBiY8fG+e8iv
TwA7b7x8S5knXQFo/AhE8aivgnFR6oeynFFfn888ZxfWRS5MluRokZmXbFhNWybPNz6y3Jr7Sg4t
5zLHsGPKldv5dYVFRuajKTasBLGtaR6UyaiCyQQdTgg1dhvVsRqJPZJiW21PqQSwvceh/L+24H3d
3r0cFWelkFzsubk0j8sPMPyHl2ljtS4iH61TIWOPfr0UCQy7gIwI+b26DE5TlSaaIArsesuABD5T
yJ0z5DUjOjrzKlvGFqLTx8nyC5y0U0eH7Xi3/cLtCEgzQ+FDayKCz9vMrlsB/+sw1oYAopnp1v47
+D1lvSrT0iqHP2JUXlg5mpR0f0d6nP0p5GxVUX6FOFBaga742a3vo4vXGkhBIxYTrcRvV1uomJLg
Y+eD8fWvUmaamAGrxivc2rg5n+XwZZultZafU55ew2lJ4HzK1CbuDA1vYBoxqeXTQWw3jOJs/3IF
Cv+a3FsJBX46NirQquhpxvaoesflnNBVDxd1YZZeTJUzyxYB89QaMkwdgKReLwI/Q2QiNmw9OuLy
F6FTdZUs20CmhK9KJ53IxoE1ZxkCWMoHi1i9zZfJ8gL9DpkRMeTiiR0/Pr6aO/aZgrI2O9HP+b7M
5Gbny0tbxt3vCTIDgo68iaBPKYP+Ipn3IODVODtDvRyE2lCBYepb3B8rnWBAbWaPmgLYoHflt4f/
v1meer4Cnh3dTbNlHk4ze9qiOoUa6ujhBAz7oZBJGcvtWeFxhldIluT1qgHodM2VCK9HxKinlKUz
5KvqL+3ToRaEkli0RJOk3DO8tnmhtm/4hHGBUm8gF3Q4DEbTSLfofyefCox+HBocpHkGaqyBpPrE
qKR6YjHkjcHYNfxulm+mV58IWktXqzUHoUqAayODMrioekEHL1GPbJwLBUZY2ZYL8HZitI3TlBRf
eWrLhxsV3ndCSztYm95rtEEjn9EKxvwaLPmJMK8TujxIwe9qk0Y4LGdKNu2b+Rt08elbulJcK3Bj
8rGAv2cLQSCbqLRbHrx52JfwD2eKG7W0sJnf2i5K5OKJYxF6T41CM0nHDJ6oHNjXegf5pzUkkG8w
6X+Trrm17BlRRXvX909Bq6Q8y5exDME/GtvbXq6BTXTpk8QxTsuAH7/aeFbu1N0DW28tkJxMfbUJ
0e0iKMkagPlajgBRaA27JN/ecw55GdhcDS1cCZVTcx03ARMOGyYJBszTNqx4Ybmcanx7VW0km3Mn
dzhDD4AmE0C9Tba1Ig9CfbSNorfmKjQ6tnp/KROzFC/GU64KkiDrSyL1nC2meN9nvaSDJzGx8yWp
7Grysrt0uT+JzoMWfxYJY74BuijjMS7Winh6W0jAyWQNfS025E1i9CBCxMSuNRZWW6bpknCPPkEb
j4G4C1lqRvDS/vwjInComr1YEnNkOXVuEkslX65rJe6tAVSnSoo+Rw5zgFAgpo+Vcnbza9h2hwxt
lPbMrajPsTMqmsp7A2V+Y1yxXcyTMl507Cl7My22ghAuob+scSGHzYFGlrJfPMRG3HtnmRwgBlsO
32oe2QIXuAvV7QEDmj4TGW6DyRn7zIT8SEcBwF0nvrj3P8+WArmONLCdUIkEWepkU5oC4eqskGRc
SxYfSrhoSoF05UKYPbJYMdy+R9h9XFY3IMRn21UIbH9EscyeorA/yWvIWkF3sd4Acss/arputRBH
jqZW5hkqoJneG19e6r+aRWVCLWN1cNwNW8pMBt9bYGYrSJb3zcCcjLEb+5+DPl9HosBXM677y57h
Dm8AycTehvF/tV8bTT4RmRW7auO97VFz9yjV7Y1KsThbxU70Bh3Rs/r/n8yXIUHwACHxr/5SIuPc
wgxMYu/F45txM8g3173IYSffonmBOq8y2l5UnHNPxEJrMheP+DcnGb8rMDDAZJXTSnSx2ZE2fpCt
vSVZcurYQ1HlTrZ3L6PMazobWbePPqEyIrQOTcaFHVtPdHqewRIx446Uv9YRzQJLsEyVZE8AgvSh
HNWav5fKJbfgSc3T+GH+Iiq765BkMlxzDAp3g+GxuRG3q6MeodA+bchbAK0kzk9f8vZ7hHFohKOR
+sjFPC2z7pA/1zRyMkRn/Af0GQJ0142xsrxwheq0K5mgWc6IvbNKXLhxwMmzsryv8z6v3yfLVmUv
kFOYE+bOwhZqj0q/mut04Oxw0RB47VDfhrA1ClHQFZBAHxttpuQ+rZv4YdL7W318LTNWbMAdcGgu
HSOqsnXpb9S26AmK34c8KsLx6qbKEu0I6orHSpEZ/9bDIhYIT/wdFfCtU8NVlcLjydbGzJPoP587
dtu5TgSldgH+A1Tcg1hV8P980QI5QDQY0/IEX/q2tI6jmc473FOcmLDaHj/8RKyZF6TSdjjbd3PU
JAeo5sNwPkFBzJY3AyOUF+b2pOw3dVBYiGTcvVWGgM8FMfng5QrqVSRGa1QptuKVJFUuarZcYNIR
LnegKcaPA7yN0pe3oaoKjOjVmZzrd+/0hsnY/xbNC0f2b/whVJXt/HRroquDFtW+If9Y6MW6e8Yl
H7rl0i+q/+XDB+x+LGHohA9JU3vFeF/Qqoz3O60UF7KmmZWOEvO5wHy30ETW4oFumzuQ+CGP7p8e
6AFibmC6j5KMwWak06vKkpVyeCjy9GGOwNV2jUAuBOX9Wk/CES7ZYnwYa10YXEom5rSXIW5YNR3G
BTlTZK6a/L87VeRPaS8iYqeAF6+pRH2HOTMzBKNKaMDvn8HYfwuof8ONVWzWHOhpIRyflYxtoj4e
VtegzPW3EVbWzwsvgTm5MvinAFR7a6Uw6BU0yQI+IM3gs5Uul16kwvuJaTsJVW35mmV5QUHk6pSF
/7Wp+4p3goW5hIN5GRbAlHRlpHKf2SJGGDcyjuwOFQfrdJEWV+fabNK/8IZbi2jc1Xkwxo7lZg3R
4zkc9aqFpvtmlSZq1UOymRGO+8uhwlrzjJY1XocBRXLLq8+NLXw/r5Ph1yvkDjhR9OrPQPoLcVS0
8m2vx2FWYFtxU4U+fdFhdHO9EC0fUJ9rKi9sEWKLLKiovoM0/DHVl5LlagFRoXgxlG5/Qsmb6r8V
aqOeUQLbUvIUL+Cq8/SmX03LbovaaOOfxuo7JfbitEF7kuyfWQLiNZiS95XhmtBoQ5fCKktSfjAz
FDua6vsG0xcLHzfYBF+hiJmxjzZvDxbaW+cyyY08m31He9f/RCdzNdRW43XoZnSB8tdqLRYzwNzM
NdojsAx9IMJrMsCGs9Y6G0/yjF7jbiDFZeA1nZhGle798LO89nby1+UavIdef2rhRLaEXVxWeZV8
4yQF91aF/VyDpddKSvXyjkBZKtf0+e/U1gDWsFvDL9b7W6EFpF+3GxbxCZ2R9oCx4U/lLtJQf20J
UlWifGdx/X9m2ijpi9PAc4F2bMCgn+oW49nvVUdrx7MEK2UdGay0H29t4Na4zy/b+CQb2j8WuplM
a2phqKGf9jRe5kACrcxzuZTYhfETuzfRXyvIG0Dr14LamTb8uHKUzKY4pVav4xTzeFkJXT59SqJ4
1BqyNjI2a4G+/TWJfpCQoE7rROPhclU4puQDt8uBVkgXXPRDoNyww44zh/F/zvn31LtG0tDSykTe
9vv5LuhcvNwiH6yOI4FiuqP7SPUTspEnzfgk+YK8naBqO2ntmp0fJbhpvXxpes7/mTVbxfGvdyi7
MiXQnwQ6XWzEPPAoQLNW4R5jYnjD+fmNbBn/wv8tQZvhqxGpgelDNGx+XXZKNFnNT3nSKNbbljAU
Wk2GnxJbfq/dsDzBiXI4mRSlpw1BmGd1rFIdTwjhZBaE3swqtcPF5hHA7TLqW1MbDt5g0cY5iCZN
ka8Dw+MIK+yrNtWsF2NqfpXB6iPDBT264lpdXCxv+qoPL6WQICJHuxN/KOmBjqmb3SX+DbhS6k3R
WTUI4aTqaWkhcktsgMn6X7MP5H4TPtHlxSb6xfqSmicbIkIdfyvZ+12A7HB6zTc7WsraArWP9Mgu
k9MUY+wrhpoOV7SXC5EWFKX5viu/Fd4xYT3SkAIwLAk6dEFla84BrkSJo9o2kFhbdEEuwVbYWAwd
1PNCTHzPzXUPY0GjxQPd/IZEv8ItJCUCuDxCEqTEjJYCvflkjpN14jdnr99BWC/K9e9Nfibf1zw7
UtzXzSSU9GBWbBgNz9Oj5xugbtsMBN7MO4YUmINyljU6OicUwsBIVQU6mS5n7ukkUdFEcP4B49Gs
bZ859zc8axRFEl6Y2uXVfwxTDqcw/76kDSGY+SwGupp9UXLU79GRMfRnulDrYfZu4pF2lS1GuGCu
g9bcrYr0ZSJnipjid0WKOvZXh7fVOrTQiaf1uEuKeS1wDoVAUDy+AYqx8S1do7Xy5HvPHMRO9V+A
Jfd1iB26RkJHYmWpDYSX5lw6EH9Idl/54Vi1kacy3Kikn4TrSPpDKS2smAblVsr8LhvF8U6XmHf0
mCjxAcEuwWO+lhJj0gw+OTXhnm6MJfpTqPTJkIOjj6YKEugLtnkvlNqGR5ZbIGK0VrAT6RqtBPTo
j1GxtHpSWMzgdok1GusI1qFpXRbhmTUK/xOpLUldrYOyop4qdJo06O534y7qfeAYxHfBfEj0j4DU
uNzLu0dk4K+JPcvtMS9nNQXgfS6YccE4URJRkEywTRKDZbeKrT9oN9iC4dxI6XKynjWO+wZLfBrM
qG6ZIeU9obWLt1Qq3N8pih1I/Qbo/umY4Xw3aLEXO0tObI6qtNya0141JFItc/e4U1zFhhKUqbtT
HfV4m1aolnL1Rla3CitE4APiJyDcwscNXyZkpshiVR5tfrxqoFOodk9y/kHLNRcIpkDzdbXar8A4
EwhhMq1t/3RpK+7vnxh5LdYDJn5PcvphwZiHlfz6Ulaq95IcMwIn/tEniuDDDaaqU4Cq5g8nIGtq
GWYBPB1N4CsF4yBSKpJt0zAW9XRD4zFcIAv50iXiiY95URuDHSZfO7hNbf0Y1gXihLSxcdEyNaEs
7nnC31b4oZBmP/1RWaAxGYcM7fD8k2gSSlLMBZ2+I1H9IXcFj7O7BDOzjAYAGInW/2LDJLJvfrT8
qf/29gIqwcbSm05AqKKTJM75JLoHjjtl+SqaC7gHO4g8mNm7J8Wt8F3q9Ca/WfYMw+C4BlrDtwck
EWp2qSCLHsHVTAFNyDUhkqDs9rlRSGlwSosxBfYTPrUnYrl3UU9lP6FKerDWFVA/VJi8WVcWlMsm
EHRzEyLveaK/owbERYzwWIbsisnqWNvpyI0sSvbGjGmkGHTc3NKL6sBontBxI4fJ36VAWVhR75KJ
3f13s65AFP0OE9bPdiALOUoVMWsHCsWZfY2FQUQaXI8VGSJC24Je2sDc2JKJULStyjATu0DYcig0
FcD7YcNWwOEk31ICqnmcjBbV0iBwKCjE24YgA6uxHOz7yDY+4D9qJFRXaJURoD+dYjRHHCxd/X7q
dWfp3Y9S+T/SmMi54SdDJXZ/xtHwJCL+eCe/ABIpaWSUEBRqK6rWTm54KS1L7BvsfOBtETuI545O
Svp4aszyyD8r18jD668OzHK8bap5ZYpIVmtcbBPSz1Xz0fPuiGqCbn8PYQGa7MIAnaVOz+y3hP4f
f41GAnqw7JWUtYZ8Cd8bGQTBlLyk1y8YxJ7qUiEJQlVonLR/wbStYcmzimhOmpV7prSBtoVlWmWu
Ut8e8RU+fiLEzqLSpVgVfsHM7X/FgXZZP+vCIo4FKYdq1OaJfozGC0KzV0uMOnd3zTRsDRSFEkfh
l6UVXGReHMxPUrY+scXqPoIY/SDspEIvghz1SzzosO20qEridS29ZX5TPVVJ01XFn72XJysOT4ip
s2kfIt33LyuixaSHB6xgqBCghraPUUPWC1+zfges6LVzPW3sH3ccYEN/xeaOozpnL1AETaawMyVq
fQf57sXMWd7K8Ry5qqd23qLhPYn7a4CCBhHuGvdK/OB7PVcn0Tkqo1CVt/nV3pu6RDy+lGqs5byd
dmlf3/Nd9Po+FQQ0Bi48a0/lOh3ib8mqJDywRoWeNVNGELDaCHqq/Ce0ZGDHlmRHP2mHSWMnWH6f
Nk8cPwnrxXpLA1mDy0k3wKDs/AkwkFx4OpvYd8xOLFEE5IRubWg9c2yHnhf1e+FpWs+kF3In0FEy
JFhmCvrmcpU+lbRugvNnO5w+4v9VKQhG3KPvSu89OupW9eO4TDeWBTptjPRly2aR75QIOgTbC+0S
UQoAsyR6TPKj+F9YvzTVvme0A18s3+2EueZY7YjXLMthcYBXlmiWZe6zuwzMCWzhnUeV4rZPd79C
qT9R4Xt9SqDAXue9aW+ZfgvK/G8wlq9AT0KQp5hdGxxmkLp/ik/VtQTlTyRWaYPQ5pWSUmK/Vmju
6s+aEmNEKHwfmceu2hFAyT2NV+LLms2EVh/ivL37+o27fUg++OdbGqgo8dtzHS8LjQI8x9BsCyqw
s9V5dguN1DiinoOiWMP5aMFA80xEl8SPemkdd4NOqTymDyCEdCjh3b118WDJxoUgdl/phKoHoTl1
Nt14wfSK5y4gimENqR8XD/Vol+rjxqSgLpTggF25zfiKOafBNPfN5saRhze9C+mA/hdLXGmeChlG
SqXkK6Ty8owNWriTd325YgvVCwDt7f1vCg3QY22ealRxE9qvZwL2uad4SnfJAAuRNx7+FIVJEqUd
5WZPyiaifdiUQNk8/P2z2FtgcRZpBD1r6YWizFip0d+ii9Aqlazu1wun/tZBEMVEVch/1+5R/73T
EQgo0sTCBM+i+kEMrWWiOo+B6RqMs0G0enzU1rEsUpQ8GBea9TYHmcegKGUWyQRYS0/h4ylxWNw5
eHoEVZr5+Psm9q9uVvL/ZK+WXsDZX4tGJ3tfeF4C0HgLP83HvH+LTF8Uy/59n5ITVHf2yx6KWgIb
ml7z9jYInQFbFhSLOMfOUMfEl6XR5nsT0jcaNZ3ALXTD5oi4oDQ4CPCSEA/7oYKgTDBk58U1rAQ8
A7w24VTu/k9YlLkCu1giSjLcR0/BVQuum+smiZbEEfXD4B0FvKl9fCWJaqXjH77V/pX7McPnKlJx
Pp+KSvR5nbgyL6nKz/xlMAsW+9+nuqtLsJRrdSDziXrfzizsb6pA5jx7fTQoxA27X+IlfKp6iMy4
JZDjxn7jYj+fwdocp4hRH3xKedGhc+IjIZyZFuK/oCZRNThl2vRLN9IgHLaP1KtS96Vtc2SEGZ1d
rtLFzUIo8l85CsS5G/JpelsYZ/CcSVJrFoTMzamv8n+ZE5razuvdtufdqDXVkY75u9gQFpD7WO8N
U+Z3i8L9qvUwMH+hz+1TJjwSpVldCyNu5lduRq6REylN1bwJerC7B4z8lTvUFQdiXionRA/HBFsY
IPmGcGEBGwzN3TiYQsD02KfuFaHy2GEAxhAkG4OZcXwFrNfOGLdzSfvlAB00MWy/D8PdjosufV3f
KJA8iMP8d2EYmn0GdW3N2++jbxdldwJWKX/cmPNE760xV4l0w4Isc0mpsKwCh/E5uSN+gulsQQlP
nBtXAe/15HKCI15E8mPHijh423oYMwNQNFk7Qlj0L4PW+u5uH4Bc9g633QUHPXvRJnc5p/0WECLe
MUVLb+JcUtKZz5dEL3hrpQI8/LUjVbIVmm8nzLUt4wBuJ6ZUxscPwc6uIIupBBiHYlCiuV0XP0Q1
VgWPnZesZ4nWUFi640PsdvD7uoF8upNX7A9g26bvUBLzCceglpdHxGS7IHt1MeRoJfJIgn57aGgQ
TUDdOL4O8amRFK328AyynfyoLNY31DuVDK2P4nN7SseuzcGIA3LMNB8qNSR9Nc+5keGMRIm1Dljm
5uztdTvAZ8wbk7rbVsG52Cw0LyyjdBxbW8otqLurtZBQqecngWOts2it4PNzDKxZfynYDDoHxped
oAy0OGAXj0PlhGrwO+IXqtiFaHKbC7eMoFxpwi3+nl/GyhQ/sTgDdRwDyNELxFKw2JcbNKnCF3TA
HdZCTdcAuU/LTWg725IhFbUxoaXIBB+EX/9eVeo5jJ0PsaQ+8RZyAvv0JeNyzQRTHZV/fo80F11w
6TO3yP/RMe8WzCVKXhmUEMtxdMoJlO0yBImAuLJ08Lu0O7xkk/CACsHaG4hHsX+LUNdJlE+I/3wK
pWoaJyX2GqoszfCGpVeywl6EWBxcawC4iyIiP9xx0UPUbVpc6RFeSc00iCsDSBZwD/Yn86D67x5g
Ymkrm47+WOq3CNWg4cHJB12TX2Qllx0xMIJXV/uU3jTtHoLc8sU2WelSi9GPmFQFfFeKE/aRnXO9
sPL4uVjyQ9LjRgxaAmBh/AWzhhdK2AlEE8oJHHtNipVtTFRpikFSAxLDXPqj3DspsQFjMagFJ6Qa
GkiudxKAfINbqHyWMZBlwZB3Tcb5fw9WhM9lSK0Z9xLvWeOAJpWAfuFKJDNx4Nz11guy5mhkfwxb
xpObV/kRN4/UVeUEvrYAAMVa6eg+XYvN6klGx9W4AYCSUeUyY4fu+I6bjkJI+q2lupgurU2ooCOV
CeF9GTDyrc5uc76I+/yTkjpOzPcQslJZBJoAbYPrtZNPl15C04iCodkek8HDAG+vs27ceznVIH0/
84VIklzu2KbUXt+ucIkB7BJ61odvz0ae6G/mAln3F5Tp+fLBNUDghH2+Rvq8QcQcXC7pUhdtkAl8
LGhFzTrJoBFAUF/SVzSrTSIK7wlQK18PEyz++BjkD/fjdpVCU+ZB9c7/EI+8uLCOxhVJr29d/3+u
xhIouaMOOUKiQdQ/58x5Vfp1zwIUIdXAUE9mnCSBS4WIP1H527dWYPFq/LyMfEdpokzfWGjs1BqT
a1B1Nnrj3dAsHPO7uugOPXrPu4IaeZ+P4Fz5B+3cTPADYw/Q3zdGj4xbFH7g3L7AXJK5M81N/tTH
pbGdUTVmtPbzmXkgLMHOHpMbCV+zwZP0k2LULKS/94WJEcsK6UWKOiqqS0rImAroleczXq6Uqpyd
UK6JVaEmVeGj4fbXwbTcY2oo3Bg+Xa/MjqP9ne3hTEPoSQ5kfvUBC7LQIZxPgOu3nzFUIM9XdSrH
LBktB79/KficCBL4PDvQieJs2iGp3mdFKc+acwtw9IuNx8ZtWQ042/QFKw1rfml574YvneudKHIv
y+rVYx/4lT3fTvUAlwkfJBkc9vLH5qnT5bm2lHK8uMLzq1HrSXpJO3qJr6WGbE7A0udgelnUbPKt
h8IkA0OCG7FOH3Fj3ABm4pSSq58rVWE2YTuoOkh0oEG6S1ssMqFdS2c1XL4SIu5LtNGTIkO2+T4f
4VeNPJaRILB3antlKRRA8QJ/SWxSuKn7CpXmbKKZumx/2ns6gaNce1U0t8QVDOi2waGQX2HKqUPk
skkSXaN4ox7XDO/lDdeMj+75AzTtGdJGsxDeXio+ukJRbNw8Y7cDPNiMktdjwUy4H1qtSm8sKdJ2
jQx5Ani8Itt6QO/x1a8RwC73Z/jZjT5a16NqXbHfh82pMheCEcQNcweY3GDrG5u6LTuhThjo6Juw
PzGZ2GY/7JjWS1JJO424MaOICd4JGLvbDR4cZDLjABRhFignrkplgW2JawpK+B83t5LV7KbdhEkW
/S6v6JOegS+vJPpXIqjvUUm/rlFBKCPUivACQhu+LkBuW2kp9mJoOVSa+oSc3zGY+WdqHPpau2yX
jytHu0KBB9FpHnjyKFegw2Tf62h6/zcex0HMFhcZrdyPjs45ZZddZj8aqbQKfqmmlxoJqWkKNWFe
y/WXReMNROhk3GYox/1n2MMBw64GLYFbkNT/A89lKDHN/kssdHXxMNqVewFeeJxnkFPZhXHlq/dG
301HoXzoC/XQu7IWQLF1k+aNWXpXHU03H9Qoy89JBpCJTcOjoLeRnjDucCEc0HKsiGtaybX2HSKh
Z6Ygl56me/7YeKwf/F2o70vXr5NyQrvHxX8uJX3ZxI1LlEgLsllT4/0QykaCxxPSz8Ibj2uqLKmK
FakO6gM2t4ZoIcMsnSIGlZg41FKF+6GD9jxxHBNDJfz4nRQRg1kWlEZoY9Kp7Y6y2Y68lwbWrLzV
s7Zyio6oR/k5Bxoqs60Jlkj+teXvNODaJPPjOzhB+08fuACiiVH/vry7YRc5HvfrfRvyu76elHbK
hXqyh2u178tARx+gx3y8AxWBTcboAvnsn2tCJ+ECcb38+Q1KNzVUpIlFdEEIVX//Tj+i++d5rVrP
hoyN0BfvBmQa2rJHThU+JHxO1ZbiatkqdfLP45lY1m5oda5wjG8DfJFvC35XYxEKTZ2vFgqIMorG
cPViZPn2DAt7C/Uuk8214QHf2SiqOOqAJU1uTFKIlcyf2QYJ4Aj+5+fyw6es4GlFxnPrAfQ08u3R
zqzquaW9LGCox30btSJte6BIc9Kuf2yCfbVcToGPR62Cmb24LdnA0RJzTsv26NRBLuAIydhtME5A
8s0snwjnbRscAkP/r3UEQw1WL5RWVHrT5tJWMcZHpbTlmF4MqD1d/hC4sb4nauyBolXngz7ofOIk
UEWUgUnpr323flg2YNXvRRJn0rKlv0cUEQ+J3B2iiIR9RBd30Wr9AedxROMJHes4su/IV/0PrDbH
43KB5SCnyIiYmGC18JlEu7WQOQFV5Zpx+NRmbc4TsKmfwEzq67Cmm/ONs2yq5cFwcO2OLDfZlksc
9DsDvayrk5okseZqns1zWL7v1jxe73byB4CCw8MYp5KPjMiXUqUtYILUCNi2SfRG7wkmOT4YfT1x
CfNYuPw6aVU1GkkVfJwc1EV4hpp0yqdkaMs+BqqPgeOi2iT8PItc5NS2nm8gZqluH5VhiOKjLykO
AvfQ2pRCtqo6baaXmCp7J8uVVpM4jOIkoUBgAIzqXq+IbfnHys0aQMSsKRXUjwFxMs1c8orLKLPe
rpKPi4RSH0Vv8ioRsp7k9sURW0ChdxVVnMGs0Q1ATiXXeDdjUwMcSwcd2pml74Krvihf2lV9J/ar
jzSrrY2ghu8eoWz4X4obYlVcHjSvIOPWd4h7o/uDLyu36cLxtSzny9pAf7JeDSQbRV3A1EIMXiGW
k/W2gCHk0Co4jniqhFQpN44VHeBuHRCeMRp5Sd1bqWQCKPGpe4tNYLOgxCD5cJC/R+xkSv/e6l+9
VV5zbWvjkTtV42dOr2r2OqOjFIL9YOOCZ1dqSyLhrTqz0XQ5OAYctG6Zi8ZvBQBYYTsVc3S3UZgh
U+Ss89hhmHng+gUyAnkrGr6v+sTdKi7ogVmkw5Stkc2bqDsR+fmn8fEpweC8MSNuoCv32HoLLPQx
ygIn7JzGjLF/18AWf4yxNPyubYzBIkkg7+92v5epDK6j/K5Bq6uQiCw73xLUdRm4OqbbwuZUUHQT
oShhrGa2zi59JKNrj4pX4hwuY9ZVO5RGEQ3R7AMQirmJOAjKnswh+KvM6g3XlkhOiafaD02DSJBe
xdsFCQWDjfSwaJkK2NZ3COpP5HlHeT4q2ORc7Y8h8ClWZMBxjtuo0QZeV05+CDghzKWSBAhdoqxp
z8V3V6eg70ikdnEtRYCQhc2b20xd3j1CmDMd5Jk0qI7wm1V1CkY5Fic+6cel3ELmtLfViKi8VdHh
3HATHjBmsn2xAnb3P6yv9u96ust6Y01j12OFsW5saVwpy+09uUmS/iKgPvkWCvZL02AErJPVwj+I
OHmj2WTlq5ESVRU94XvP235rUOvjrlOr+gJOn/Wc/9fpA3QiNnPhuX0aEp8X7byRE0h6XWFxD+ZU
EP1AJ66a5iDTPtGb27s0rQBucQbGTxeBtP+80KHq+x17IaAWpCWWauS99kATXyvVLaVP5T7ryt25
7Wh//gDWfyCk/rQxuvRr7hQibt0mUx7npNQLTElAQHI2EkSQUYnkJLCgEmJLHbYz6f9NjO1OsDTX
vTcmRlt8HNOJvnAJu3TmzJkrqA1kD5Qt0U4r5xPuSglDwaOfIPhmJ3Ot/liCX63ZdQJ9xRFvfPij
pXjWGEOa/Ow3MC4kQ93a0aKCeWaUTvesx/KUQ4q0JwLRKTaqeiyWLTFbPHo2H4lumu+ZCwMUv6tR
Mp3hSk0KFSLN7um97m+pyaIMNd2TGNNLu2J+qngWiduh/EErJ3U82sx1KxmuvvZHYyQdZ1q2aH3a
Ie5IL10TYcjKwc01tDfb08N77ZULm1SDynpjdbu3fbHLMEatbKpgKlBqwzc540kmYLFqb//0eOKn
B245EBRpJLR7uZaxudfgJkIEP7b6+cVG1KSiLQ5JNu1L0fAt9S/PFdXS1GToRKJV2FgDmKxgmKRz
6pR5K+pKcyglu8ek6vAj7IH5KzHrHrX93un/KIeJJLEWS8xUbsFpUELGcXMIbckCpB1ZJdvwjxBI
1q4tVnn8E56tjmV1K0z1D331yjUoK1AvDvIVwg/KaPNvAW1EYQFBHx+Kj7jgO/eBBhEZ/3Trnt7I
lxyJ4vOcoRa08DYGuNp28XFw9CasjpT6gN0xbRl/tdepQLF/X8UTxRgiEMCkJdrmiM6pfm+qtaxp
YQJDY23Ynf5Cm78rGkRrE9JKC7PP/8A7ukSYqz7wQUwB1yYXBHfbhDA2uCQnRQuIgvDB3gST5+58
MBYCJKMhkETHNJMTO5tSggCdIF8No5bYqMuYA+gucmHrMU65SnN6MSBmhjPjgd82qtcdg08g2pGA
jX+ycYCZ/sO7TULi3tKqdcBF9RazbXu6PMEqwVeO4DJNyGfJoqhzn9JfiAjDUSSFzk/jwTNtiApt
jpjBrtUgTJnLadZnFIPUEzrSQ+CHO6rXJf59IhmjLZtKX18WJxezlfB8a9qx1G5W1Vo8CVwtudJ/
sTC8feAO2Aodp9V5b2Amngc8T7sbdLNUriXOo/jEetLx1uADBht/vWC8XGAZf4dBMCeLNFoA+n7G
GSgEU99/lyyrzdE2WAjQCJCs9zWK9/x74kKeAlxSURz1TqSGAYp7jcl80X+CNGYBvRbas22RHH80
CEWbGwEWAHWLovhm1BRYKuQXCeUd5nDmjDWwdiC79rzAtQ9nm4NDunVpB1P1q0vurDr2EeBRQPyq
jqYvAO9aOMHJvy7vPyKCgA5+OEIKbXitrA2kjcJ4JjIa1VmhU3ozkx3ZXQwZVdRfLEye8EEJrMY9
4jW2SsV10CHwdHhpE99yyAVcAsYnXioapXz80z4WEXNnFPyKQxJcnd3qNKVqzlb6Apmb0TNaUrBn
CBDClQOOWQsSIcxyXYQMlKuFuXqyMu46ejmNNwyKkQLhqDYpw+CmPHNZkCMUp8mbtbBa3EwFf+AA
RXYnbsKQSx877JFXv25iSTacF45QkYFbNwvEy/oxWW9kwOJX+BgGGMzvByozciFBmrrwRr0rbGIX
b7hCLgbG7tGIwCb+iNB/jPQqCwr1mkAxr6ACypEJ7VFTeERiFzoB6D55fqLXKXEa2m8fKr/1eLRX
PFJBEwrMi4PYIkDbNk0Jmzovydk1XGSFbPtZe5mVdud1GD4++IBNvHrda19Dc0FwK33vjRylYi/h
dKhm6EL2sfY90dbGjFJ0iQv/1gTyP8BinAm5vEEvffnGQs+ZB8g3zYIyjSQXRfHm8Xh6eg44vEkP
UnCSiDliiSeXk38yRO62eIa4cZhSTQ/DdppQ3zoruTPnHZX8WR3EZjtld5icFrEXOVj25owMLClY
bvtBsoV4l4GeLrvqOKdFUe2SvcLYFONDAcFCZwz4sDqBdTJdZdMnHSGF15RfSLIAVsRG7Da2Jw99
RXF/Qy52Za5CgLcfK0M+ZJGlm67A2fwdO8IiF7zaoH0UiJ/aVsghPYRwV2fnjFp+1t6aISyWSbrQ
YKu3zwbqVBT+GlKeEkB/CbQaHmwXnixG5A7oJyWVA5MKHz2EYzn4/ORzLAL1P2ETcJAhuFuBqvlZ
NKl34jQ0AK4GhOe0PDBdwU53yr+tzEbeJlLeQmzDvqmIleZex6hZ9kLb47Fm8aRA7JOVa1Lb5WV3
jrOsej78qExlzpSJUdz8AgEE9FsEuLz7qAegkHgPTbwiSLWdu4uT+eoZucAUpi0w17/vhj+GiYzb
w3qRsA+MJ9MkEYbRCH0rR3+F1jpja0FDHH1Py/arHCcX+UTL2Y/Xq+OVv0otzIyTTB5+KrurBNJB
7MVY8JzBOSLjNqzmEsjjoRApJjv7VNnMIsXTKe3tv+6tpjAAJchjFwTTCLWH5kh+7d9cbz5QT3A1
NpQBQ7vxcYf+3IsLOSqiXKbg+2o5ZOyq6FBFoR/78lfTUXvcLouAaCNpIhvudAiQz/FtptG98Xfc
HBNZFYU+HjndyAETUTB8dkgsOaMj/t9uqEUokNnKaaIrunjGuiocfwOTSZgeCNJgNgYChNSTxhyk
iF6pF01DMwvuNTGzwUgRNuRVWxZCg8vKjeyy+UlkX5poSJGTzPzJhgH0n3QQgE57+LgM8AqhDOqK
VhdmLIXecYfVnUCGhWhzpS/WiRiz7g8I2mHfjmU28hMZ5LCMMsXjndpCFk2pv171UiFgamPSwk79
L5yR330tfp8DSAtguSfNnDgp4hcFWqiOryXJykDv7y0KLI6bJnYNOF06vATpqkrxnpYhRrhXQxv2
rfoiHupBFJGz6sgcTke95+KNhZSdHmDFoJFIvUR3D0vpY8MlmHG7WkM6HDORKY6I3fxwJt8ufk+0
DLgC1S+5vwvEDrPgtEOxSkocg9G2RiYA9aVmRFJCP7CAx/OqX8XVkUh8LktvaCt1ONM8ZalXvEMJ
9UweRfgukJuUgr3viuEiCOJwe7BMZ9p9I5L5lRCwuFLqH0HesoSuHwwqe6KqGiYqZZ9u5fuVTlEh
j4iXMGM+sCzzySbt/AlKJKhxzT5vJKEuKZyq4EBoYndL0NQto9sVkQpn/NYzTNz6WcDOOoJokp7V
Ujmxo3bM9OIh7AmqK5iYXDWjmRadqK4SMLIwg/UIEJsHyXb3lQ4B4x4CXp1//g/6yU8Tu4oUnt6d
G/G1eMk3zrnLjk3Vqevh53FvhuZQ3lquETsNfBaXNzDoeRyRx+ALkZvX9g8qNSwG4BkjxM4emzZO
gMpjFsMEJPA7+K5rhGd4q3DM3Oq8pIS9rdBFX/7wBThpj554ZgK1CD0XPgYg2y/W1SGWud0sOpYp
7K/wgBm4nTGahpZwtVxj+fgIjAFxqJD5ii5Zlznlp6XH9iNJSM6QwPPq2UNWdsCE7uyPw5mC3jLy
4M+1dClNGIFzgYz+ypEANAYZH6F5TENuUia0Myf4k9ipE2dg+P56DUkLkcQTUmCetYUFwSrLEDII
v76W+GjaA/QY6D9eVwdEnjkWM532B4QcMAEC5OqAXpZKsgmXf/97/bFTfyuosZDcOPVEmAyzQfHu
bNDFMmafbfTnoF0r1cxni3upLkypbsI2hwK6HAwvKHesHY4goGwBcR+l3HPI6DgpV+s6fZiN+RDq
tG47bdi8wBep0HLXGdTxeb1AHQO2I0co4RjrzLiOaJMJyj717yzwyHA6eXipb2oHlQCrZdINmpRE
Oqrr+NxNYWX+VeinABp9as/YnfR1z0HrweXen/F6p2bbiIOZ/k1Tqfw7arUDhWAoeabijv+dIKXL
X7ViLvnxir4W9eMnurEuezKJxuJeblQngakRcP/GEzqsDZgafSZ3bvH6t69Fk9F3M7q8CA8dzTnS
P1upJYjtV/CjdFqL6XEhtrDyf04KUyIJAUw/dQfOBeAPSPl5SXl6qbCXwYISDkDLGDjozRtcDCxc
YWDykw9r0mBymsOpuEwwwERYYhkYXl/hl0Rr/qlWq40hAg/EqCqxIJk5UzE/Oi/dmM89HHQf+5ii
ifdBznYhB6udAlSxKa4MmEi2tETgMufxKhJ4ps8d0OEs5etUoZoQkgdlhejC6r/E75zRrgj56Wxs
xrnrSNtErtXp+GETOor8SvttN7F0Na0vM4IcDIyBAAmn4Ubn0Hq99zhCsBFIq6Fh94DThoAe5q82
90Ei3l4r3grvPqPlBeK3LH1Ckx+pLNouTRZtbjObmaUIBfeOV8kDpVdu9HK+WcbNPoLy6gvqTcHS
w7L+EQN37Q4N/ghuXAmv4tfFsc6JJ/ubGy4i73tfZCFuNuCL5x1BnbkuNwNQM1c6+XQvtAeGDQOU
JK6hNM64TS9at2FHAMI1CHEkioXkax3TDllYfQx4YdD0pf/9Ym5MWE94/MgBMfFEnUVUzX1Z6fZS
NruGJOc+Z+jlGIR7Um5iQsondwnJrYZdOrGJLaSpSK5BVNRd66jVV3Oa9wTa4zO4TEi8o64SzWQH
p7Z/VCMX8wP8RhRiH70EIG32yD/pquz+QA4zzKWHlGY1zBOqHAl0xb0oLUm+cfnmHnqmHDTfRfwA
J1XNhctG6wDon+oEI1SSew83ALXKUHwD/lWgp9m7ndn3TJs9X+t/oEWnP+TeyOAMNKgoXn7LmaSa
Z66uVNo0z8o3yt/3v+J6XqQDI3Fzg7ZspaAzwOJPL3O02ClqVQmINqiJm/OPKRbe/V+Tb7QEta3r
zq6BRBQysULFNMipOXr+nVz0MZpHqEoDh5ddT9BgIwicywxykHsAXwjl/Yti99Tr8u68+g00Zr3U
1xSGAsptRxf5y/TsUhZNLQNSEAkLHX0GfilhfJvQl1vQVbXNuoc741AEb/rtErpFlgioGo0vvcwd
UVVb01l2W9YB1f367H1WUevJgTp4/Blwll7D/uKXn34Ooblj2mEQSo/7i0ewZ9PE1Yh2vuq0lMPI
PFo9/i6hdHJtwm4wOI6iN1dKRQdTA8njmKO5Vnni23Dl/W89a7Tknsw8/y0i/gEpC1u7QWClJcKd
A5NJ0K+2rAsTTyi9Ki7Ql75bt6uqhCrnDhivkBTp/qW9wYKv+7uT9AOlAoh3KJplRO3+KN82N/c7
GODrg+wHog0KLxFrNXWfN33qDpu+DbVB3AkrsZsKLSOcb9vLmTQDuIWNT/xU1t8PIyhW18Cj6Ap9
pLl7vCa3ECOABSP9rJIGKKD4ZBMjiFE1ljEUy4mS92RKf6AUysCOd+pzLbDgtHaih7maFjxT/6c8
uxyTuShiYNB1fjj4y+sJaX2pzU3NAELbMmk48lvhwgkigfpoOCGD/qu+RjjXbYYNge/Xib1paHZ5
lMe5fJ8WwJS3ued46QAwTQQMXwABGJigyBVtUR8sQ/Pg3/PxR0WIwcc4IRkAQjVnS6cxvB1A5yVy
y9NAc0WAU7Ux9qUgwzdDVyndhSUGTe+BsE+ivHhMzU1pLwLfkRFQQ3x70AtjY1+4cF0fIV8qxgRg
9ufzeejm9UdpC1WDodmt2TD8gidqnk9fWnhtjVOo1w64n4v0tocpRg/qvFqG1HjhQioVgS+s+rmj
qHHCCrEPpY5sOl5pW2LE8ViAaHt12tsFDFXLvO1P1IFlMn85pqwAr8SDz5qYDU5NLv+qcdn37WeO
rjqCwuMOEYrlul7LHF2c5oKBY9F6A2wuP+1YWjWS9Xegnz+U0XiJeoEu8MGThebOfNeLHUkPrNi8
akOGS2lnIRjrzU25Xvj7Kw6DzAvke5VL+EpVnyreAbZICKN/w5m1mKEaqCEfm+BK3To5xuAVBthu
uCV3Co/29e+fw+03hMbBYd6LPS2RqFOBFYLRkv2nxOieAhd+v0qJxhjnvNPunEWCwSED4sslp/NS
kBn2JD8LS1LrjT13LLMoreO9Zvz00tcIlK2ukLELWTpchLNZD/YCB/Py53IRAwS4s8R/AOPPtTZ4
fk2VIVPIScPBZxLX5B3qGJdavZqij9VbWgrQA1PLR9Xa0I3iZRoR31E9ktp6TAZmRf/lWjY04G3d
JXN05/IGo1r3KgpvsVQ7Iy/94Kqfz3Dw7gKmWR4SzGbyLAKMwvXFm3JTu7YDEMBnjTXN37JW/UYd
+eeo+DxbkaWKd/5CnlQ+v8DGPZws4Xc2hdgcObpBH4CbTijbntc4ZsVIY8t9/h0sT/0/lrfqrehI
Q0fLjVrTPna+S4UJJ+OFhu7dUUf65ztfKqJly4pTtRrBQI4hH1pAlLI8Sz4ktVl+90Dk/vVFnKO2
Poxf5vjhTMjHSsTqFNOzIiDnSPIgNNNzl08YHIS8f9vgHwmy1q6rIE1kG5AsrplNb/aserTvwrZG
DhFW8l0El+/kPDzJaO9vLwoPG+HJ/Mpd8FKEnaesn9sWBvcAn2Uzg6H0ecdgrd2hzVxio36SDobx
oxBOUq0rY3G2uYpYN4F1EPpBm+oZvVtmcRg0GlE35szEc+QZoBQ05SEvPVag2ToQ4aWxptJYmMrp
AtB24oBvDPHymLJZCfG7iKfT8NwvWgaS5UcE29603e0gf4Ai3zRp3k3UMllq7JBFmDGNVslf7XQ9
VkoUuT2TJ8U339m6ZChf8A+1KVWlZCOfqXlveUSDpjF9hekHcO65edOxlRZobkJQK4gddDfyDeWn
ZLwSNBxmW2KlrcAJnm5889oFWFvR/hRqdZsNFwSZyoIPbYAWpr5ZPhsxIYxyM8McVfoKOXaoIUpT
fG0KGhuP/IZ3zxfYW8kSgAzgvi6gp6ObDbl7tQOyEc8wT8jeKOF3fUODjmLtPTA4GqpyEjmj37an
Nv5D2T04U1Gdc8/skysgO6OneIU25Ist3vaD7tSwVZ+lpniligI6ovvbKKsI1ZklgSRf8apZstIn
3HkWdMHPk5qyCH99DKk6X0DuqPJ7uzGrPMPa/H2vSe7MqlVm//9pxrQZPjtHKRetuUQNLfO7e0DC
QdPiL/rFeaZL9in1hf4lEU0BnwIcQyED656PAdd3FcHD67y66cD2c5AM4YpmOGUHz0Cwz+HtCjgD
8ZsgNdGrM5E3xv+HFUhvfwKb3gc35qQ9ypP0+dJuvwmbkxYtwhPBEHjPR/iMCAMhDMvQdag89Mt3
uh60fjhIBG2HQOtpVrJE8htMn7SJE5GxLrp4Xx23CL9gwM3t/50wodh62LRznaV0ZLyLRVYn0MY3
imn0VYhUOG4mnQP07wOIYGwsSuif2BUH2QT9C+RrPmlyb3+dk43YaYb3b1RH76dspz8IOMVf0d+s
CsxVVtd/Rbkwh4OEP1Kxlpw0eCLdmUwA0pBwNuiLBNjptnswx1XzyboC8dMMZsJ/CtKXoMDvF2kO
n90jLljo2vKxtkA7iRWPtZ84QIeZqboXpBJX1GsIAeHRWxUGHt06MIkN/RIbTfNdF4nKZt97Jtqo
+TuVli4c1C9BT17tPOoSix0ZcfpryQVfiSv9wjJhKPtFDX7oKxPvqWgCyxvXPqZ+bg8LkJZuIGEi
nVVHusnbVyNSwDENZThz9TqwJP0XlCgdCnYOuhFJlJZW4Vq4fpI42LxDTjyCmWJOm/+2wolKXWlE
J1xbjG86p4R86mZcn9FF+bu7+bI55hf5V2/HAoB9PEAxnObQ0XSvs44YJQVE75pK/ga7ldDLjFt8
wJWIC37ppfX3/ozrvtDDQkgjoc3CD1ikaM6Y0Yv/0Ct/2BLuK9sPNuTuwFARP5QBuEJjnIZsqsT9
JpBdnKhlBeiwSwI2IHyui+sBStCNu+/giR2k/arLBrUpcisJcSS8X8q9xbiWpJpjY8Xcc69DDVEO
lX9+RxzkYEzQbdQrP7U5hwWEXHvudnECaAI2Miq7Zr1a6oQ+HTQo+cU10hk7lRSHKRCoZ41iumzV
uo7MjJeqk3FYgMJz+lj6ATblMzI1r34MO+/LTU/jDFjkNYnW9lZ7tZy4M57i8WvpYHjM/t9FDoNy
ZSWGiaGQgsFM8Prmyswpdk2Nc2FmaHe71SyhmM/a6v78GCNMfqV7V14VYTZlJN3UAC7H4Vy5gclE
CCvG89AVB8BxCRv/omzThftpnJZh6qFsfbyysnasB9vJFDXtEydAkkJZj6RYxoyAZHtG2sBT8HcJ
iAntsYlxEKWIoLS90G3CqEse2a3+pTi8d2m0uX+wpMjJLLb4fckdixYiyzhqqCE+M1NESye7CYnp
EGyyQ9bq0LsMv4wWJtH2OH7/AsVB1knRsIDOk34Gm5l5a9L5cKdptaEwMti9pQ97dwO2TFY8Afkc
dhm+KoBMXXiD0CCJJTENo58gM1PNsaGv4Vs44O8gLy5m+GxTxrgXt3X068ozuQqW7wUMoMwiKwpm
z2eMZ8L7kNpb03mJL2yJoRVFRYjFywpRP+ElsLKTVfsbTkYdHDe8H87vVL7i14OAlfi5/oyZUcIx
TyuElN+QKarUfmnamGIxkEULvaGQ3iiX3Oov/yIQ9CITYMrOlxXzFyzYaYC9+oXllyAAfUy69LMn
Tth/Owxa2lxq3Y8wVez9bMk+hP/h8ttOdKYgBd3LFvHMgg0Po4VF/saCByN9YHApp7znD1dHtdgA
L0r6CjRkuc8tZtoYXfn3p16iGy24lo6G4OI3XSuD/bxuiExpjOycmLQHqPmz7AWCbLxcUUQBR+In
/e+lJSviUdAw7GLGY7hWGl/uS65Ih2yJYKnvdRGRxAr1g5E59v1EVU+7gz5/bQ7DWty+fDXA22H+
GFZBGcpWjV+Si5mTPmrQvWIgNrrmLDHNiIaOEd2uQbW4XBC5e1cVb+CbvW12L1DGXgJhFODNhJ4e
6/VmHau5+IlkDLT+xe9OZNuj9i/hrNq6nJVCpH/+O4fA94U+i6M35HBShvgrATULSEA/D+0WGsjb
wZXgPHeifQ9PvGd7uKCW0zebS0zEmpmeiRQCnl5VRphpk19BpHERtZc50y8dJ+0TOv2R/JLRhyiy
h270KoTC18aUT54bBbYX3k1ECBuoCZM2qOFD2IducNI3lFPJf0dUSUPfTAItattvh79kkPHj6E5V
zNQiN3us+CBLezMijrY3QdIN2vsq9wxJg30Id9K4dU4578WSD7yddep/Idv2gIDAH0XWmC1sYaKw
RqYTL1cFy+yLu9WrMQ98YHHdSwJo6kE2Ly/9OT0ird8KLxKyAak53DA8Ms9YnOp+wp1R+oB0FMvv
cOWJRy8aklVKM6VDybyTkU8KSAMswyWBz0VOirGDCuKITFzEZoP6Yq+gNkTppOYRSb9QOjclYFXM
efVU/cGZiRjJVrJuxjWOhWU74zL0Qra4shTp/CzYu1EVFEDwr26FHPEauY3RtM1fxvpMdoSLD4uZ
knY32M4YBmm5v+12IU/s+IKcwPu7FqoCFsu4a5yKW7k+Im7fYC48EFJFQ30BIALBt4PX85yG/DcT
D0dhNRmo/Gfx2g2O57F/Bz6uXqOVx9TifkhW95tubmocTpUsYWdeFE5v9su6weDNcHTpFu+54bk1
4Bh80hrpMFP0Sj7Npq1lF5PrAvyZyeeF4SNL1MeYGuNlVNGdoPdvSCZ3UPMvFiZcrXe3VeKy0jp1
v36wLSXA3l/d9iomJx9EvZOUzvrsl1xpg4vBrDS3lWQsyLXO58UFBm7AH134htAuv5viGdVkeSvP
HpFfDRzCF6o2ye47JUzBP9XTcVOA/kpB2zkKepbCOKmnAp3As8+KdoAA+4wCcGhf1WP6QaMEdcfx
UBoZZWSguVMCBTRYIKifonmYirg0e62SDL0uHCgvQvfCSbgZ2bm/txEWrMEvbALFpcV4nSJtsq1m
w1blK+PY8f3SFtOKecNljLud35cKTcL1UtDDBZq64nf7/HZGpetFPIR3nnOHyEw9y5T/r5eblcVr
sMfHD8nVa9gS1/Tyo8/BuszQ7xOPXSL465ANLIUMbe1s3A0rOZvpwIzAvo/iQ84xwHlHyyM73C2D
uTzMaxfIoesYdycJgV8hfq9g73+Mce881VfdQxQa0VM6qdnkaXsE9M5W+QS0Vc7OPv2mNQNxV+HV
EE4YBElNIsPPOLl9UmDhrnDDyFLphi9rahVKT+flQggQCRZ9pfq+Q40ScNMillag7LGrwd6YiC9b
tlb74kvKGm/7Ry3fsrHtlJPBlbKz8OipNVmr03i9Svq/JgpHwvE2vxW9SwDk/k31bqL2TfHLLI/A
uOlcU+Mj7HGc9Kmu3ud5wmNnMMtQjKdr+NTAwJTNYv2Fpuh/yZfipx4NKZ6yGyyXUZx+UUBXlRe9
9gX9b9zh+8uRcm0Rvu43jDmWxiGWlkmvbBDUh5tJFF/1zhiIkVKGCeuzYmVrhrLybhBBI5Aim8TE
Pd01EIW+TRhcbXgA8Rnrz1QCoHtlTJqj6IPsx80jy3fIDWMRZjq41NJjUwSQxQbrYM6/EB+DeTWE
WSF4s2IiQWMNEQ643PBOi4ZVcPple4ojnYkZf2EwykzpRcoziSARhUETirhy/OYFnJEFYVerm+ne
3wFyzHlhVlZud/so3aRcDHn6LDBg7uul+cbUp9Ol4wHhChImU5NMg1fNp7lT9dSOgoKdNq8ZYgk3
lX8fY7faItKD9YtQrENhoujkGBL+S+IH6dzAuCuqaRB/ioMmM0wenYB8qTCPOmRPGrx48coSva7w
TMfs+2/tkxqzS80nXYxg2X1rKwbYIcG97NYlYpFc7+D2H9A+YIPNJcSH4457q91namf54Za2lQc5
/D9XqEoukOqxAWdImu+jE/S+P16x6FTZswwPlXoWm6ulixcUm/AZ/fKMvt9LN7Bc+/g7BBq9dw0d
yHcbTTt5pxipJ2Ap61PPpMVSmSvoVrNO+fqsgTRIIC7iL4WiyCAFEkWBQJktz81OwSpaEgnHd66X
ES4dzMT18sYYRZqpmgR9yTzwQ/NYVM9vnHuj3F8SsoGdtVOILEYZX/k/taBH6AoFdyj7ndHQj7Xy
5fqAgGrx4ufuhZBExJAFj7L/H0XpfxQd5v5YvOoCVWyhlJy/SC5ypW9VEPlQq+z4ciLETbtahjja
+GZUFBmxB4dlcnhtoIyiXywSyYz/RUqIl4wcNgb5cDgdgUf+/K2h8IkMSYmveAMyaoqwOeck/XGF
0zfMm1tbwWRuRqLxHYebZusGJV2Ix+4cWo4t7GxuIm7jfmwUbh2zqJzOrNv6QwgbKwBTAc5kMowy
hQ64V+v//P8zpkiSKLCYdwT8ACpJ2pBqiNhBIRmivj1IkWHnyFIq+oShXPUq8QYVKLnXGjzRA2IU
DHq8jIOIb1hNL7iyexUlrTqBH3i38b/0Lr0uXVmZ4V/7sSTizCif8GQvRrVbDP4PqEuQjiJmE1z0
cqWdV4UCVDFIiEXqsvaqgTKRf/o8rfTtLmvB/rftgBXqndPcszZhSP/cWzU5c+/Uo8JBa491TthK
YK0bULTYePeFFSPxmbsM0PjYdfhip2DcuhQ93l9rKf7Z/RRFwoM6O/XKKwPTvtevs40oSw9em4Jz
btQx8N9L1W/bIiyVRv+xASEWjjs/xn+0XsjKZYc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
WCjKBNXic0KXiU6pjAWXiq2LTkKJ7NE3g8L6OgRpnuv5wFja/4QAqU+5Vd1hH0Xxsc4vA0Nwy1zc
t7+LfMBHzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H5f3TRBy4525jkh1qIK2Qsh4q/GrtwJ6JVADtzts1qrfqD1bWIkorepAhRIvwZZByI2fH72x5SON
7IfG8zLpYUlD0Jk3QCBoYlUZJGWU6RDyaY2Rn7Gz5P5HI4qvPNtW766wSe1harlrLePNjoSKVhfF
4H7y4hlOm6KeJFp1y30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o8NUJuTvvtHQ//0yHzk4r3ROKImbnyCQ/+GiYKbHz9Jqc59WPVQMPJDi7618B5h2z5gPFkZLVKrt
oYIDayRN1eDG1k1+njjd5YRIb7DTMBqPHvFVEOao9N/cefP23vkwo+I5wXkEITLqVM0RI3al8o8t
AaA6Q0U98Bzdo+Tx+RKbiBIBi5x6wlOZOehaj7m9+DFw+updOQeJ5GNy8AZn7ul0lsua2cRf0k4L
gE8HziSaUr+ewcL1uRh7afU0No6kaXygNHGf/nl86AGwUs65q2nQnVCcL6IPPyXmKD4Bn/J0YFQN
o3G/KJKIPhXq/LL9z7Hr7LE3J/cIaba4C+44/w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
r/Xe2Ci6RnICLxvZgN4C/9rfMRo5L4MeaOlVrWhtom9UNPVoQwQaTPdI6GiUuDDQ3ElZSB7f6p92
n6ZoBVSL1eywG+ntCU6ZxZ1/8N1sV9CjSBxGOexweAx2kmsTC0q7hVe7rZnh/KLLizk+Ny6alv8B
v1zuaJAVY3QDTrVCM18=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BA7JOat/rOFWMLmTHh8DUAZtAhABvlT31S3WaH9xRoHVRI5E6pFuZ9+Ecgih4mhDcxdjqSGbeR/u
24jHGR1zNpOF5SfM2XuvRrQQu9K7wIyXwPdbsyw0LvXT1RLA9UeiqNrt0F8qGcaPOkn4zXH8hSn9
09AecPGhGA7p6v1GpR/up+MJJxlXdQp3HrAGMLNTw6FmURWGfU6ot/fE9/XTH828aIEuXPQv4VF8
6pJ5XDXcni32tirZKs20tbT3Ib0XzlMIzD6X0wniGigh4dlmtyYpx3VFbwNcoV0FuVHZukOeq/07
9NqJrMCoOA/h5LgKZYIh1HETLValj8txpIQaFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 72704)
`protect data_block
HvIwe2N34SZuMjy4um7DVGxuUtmbgThSrTNwoGwEiJdlisMhSbzJPsSLzQyCVPvBWB6KRKKsL4Rb
Vu3IRL7SYFIFYCA0Qq7GVWGEpvlLVdFovlxeEyEPw7vWI0vUv5p8t7ZuGAgwgUgLWZwGpb4Wj8Wh
NY0Ig3CnlqX1XIrtDI32CboRq6okmEybBULmi2P9k61yb7SBFyAc1svnv57UYSBqImh0j1AzkSL3
wa7THm0mcJ/gVH1/KUyrhO1il+aaW6NHEGqWVwo74qZ5/fcj+YIKKJDeGiqH2YcLSG5NjtOCUbnw
Qi+LxTROphc9BKH5UAmjqDhnJgjwGvr4bQeqYaQb4SjNwDzCodQMfFlmK0ro8aTvXCg9F65L6/fq
7DuZcatrpTd3yP/baXqApZ5wPBBkqViF04/WKfDRQMsbOlqNTWJncXWrzKoiXG4UCp3CPDPI1ADA
J4IoqjvRDyOwSbaOvd/DRgou6ZW3wRtzUd3XoyUc3ams6B2Os0tjPMhgSshCr76+8KfYp9hkLacy
Sux+oKs9jY9iRaHGLFTha5pUjG9spPLty8CV1wmij25vxNiEVXbEH22Zb7UWOtcj9DyaSa1hjrIE
x7q7kKY7XnPYCLZ23ZasHnZUjRcT62+6/6DN7KmHAlEaspJwIZt+DWh8A7U1vMtZHaMtbFE2O3Y7
iQjIjy6W6P22+JSJsLUBOdzAyiY8cghioSF+0RXrqzoHtPct4n98w0sEdA9Znpf9t5pA/uSvDBL2
iOyRM89wsiLc7lsX0sihfOSjqqxPSZopH+A9h9ue2/G31af2bLetZX6UsIMrqKKz3DsUWS5jxLx2
uO4K2xiZYATkiQj0HpfZu/5QV3d2HdSUaKtqpNfRz0Lw+5VcfWZFoyYfZ0TDA85K3FoSjhCOkt5X
qnxEdhrhvJwcdP4HRT3bFDNzaQT2Bq+0qvhCP+3ZOskwvkpFPCRCYfPKKjMYd5EsWA1ipnf37Blu
P+B6FwUT4zhffqISQupWw3TQLYLkxjkHEhNe+WkTmmsJZUnWdxVsov0XpzAcnl/DTDNtJ2+ovFuW
vS5MsdjEPyPduB00/YvmzhVscA84PYzTTOYmcWkmjYSzuwP+lws5WScc40P/b1OmM6iAtf4c0rZp
VvXlFVn0n3uvmJnaGn2RIeSQIa9WTqypLxpT+BZH6En9xteyR8rIYV1pxEc0ciBiL/jAV9n5T0k5
fvUkVJZTXX+rWbtUg9+l4nYvDOHz9+T6m88MPMqocLY9yLV+dFzczAowkeQ5QYwNFIzing+a+xZv
Pxkz++cUzgMzeTl06W6wTt2ZiUgg41n/2tzqrylGQeM9VqUiEG7wCrsr9xS5nQjWvd50z1JDlsbc
XZ4wTJNrOMBD0zmEaRn0Nrb5kYjGMUBglMp7HduoiDKKRZH+kTiXGYn5btDeDwJkymeDqU52kxMM
Ua5JylcFhWPU0/QZSOzOFQ618mpAVniy7VKgh8HzuiJ1eX9hUbnNDBqI5+sFcn606kPJ3RQume2H
+YAsr15Lx5QHTXxdHTywTQc96QLzVEd+ZCoDfLy4Ita230vNXTC2z7eECslwEaytH4C21b1sLtfr
5XqqtMYgorrrvtQqTi+7Gy5tqz/yOiJ8WuC3n6rCzNi5HVLxx2lBcmoj3ck11xEwHK50HJHCLs8n
JWjh7ZyFXcnG+XxjfbJv66Q7WQUu1ZmqFkRdo1tv2iY605wT4E/Ffc4gBG5uBhjLdth8vbgwz6ZA
RRtecix3HrcRtApeT9szKzg4hejQoo6LEak3BaEMuJWHW1+RpPJdNC1m3R31OxYyz8uOz6XTCT0X
37wFk8mqDzVYvkZRZMXxSSMgW+/tTBr9J8Ydd+N8d4SJIlaUT6Z4dEKdOx88H5kAlF30H8nMnggP
SDLxrazQ2jQmdjhLK/KZ4JKgWPpaiKEvwxmejO+E1te8EtF1r6TQWyBYuNPbEGkNULWhO4R7Cida
ludH6DOYw7JB1g7LfnsGd2QuUSkIq4hSkPehzDldUnXi3vT7fG95Y24Rs1Sd0MHAm2/25gr952+p
OEN0jULZPrgA6Wy6VgpHXNYAtOIJhXgWrp2Nf57JhizlPfOy1Pcro1lFHNWmcap/4qKYMju/R7K6
GlUTWoUzIjK19xBpBj057nLzgeOTsPvmAxpJnpGyFe2QZgFs1CiqD/9SPLFhgFpFvIujjVokVuQv
Y0SW30jzxOyRztwpB3VmYHYbIWtp7IDQkHEgypOUnIvYckMEO/2gfXT85ap+CcP2xaaMSS8qRK6i
KDBOyMwHUFSKKUvAG6UKRulCPv36152OGtsh1p+qEPYuHuYz2YHhQjAbJwovXPxLIU3qSHtBp8Q3
yc2GWHdqA3P12KMBh2LyuB6FLahJbJu2cTsHXvtXfHXiWrr17pWTXZdqbJPgbxv2jRsGZVxV9TyY
7lRyR8Y3BiPwHIYd+hXW2gqNAbPAXEHzEW/FLTfzU0IEh+8un0KCVxWV+PyVOjiySHksLyZvAgtH
XSphfYqOoGZedfxOcsK8itSk1ADQRdw/hHld7+km0JITcpn6XxxASzJAe4H2mMiuXzmv0AqopF8Q
dn2hMIc1vM+o30ll48q4nzjgzZeDYHU6ZVNTqfMAzTR3cKuj2Fl/TsX+MKLc5v1LF2njBu9aaEZy
X38BjLVxv2YO1/oTbEE2W99LCX/hW/VvpGmSx3TSAWbClged3p6hKVqvXJrGE6hSeAbmJkEBf5UV
9xLSafDYk7Dwr/oug1ymI4P2KbJKuAyPMOY94jd3Zbb08xCkTgPnKXNMGjsuU14Scf6ZQQldfv/X
Vd5uymnNA/wBuAfE0+w51MJz39YGeyyQqzp+ABKGtvX1gcyGH8g37lskc0GVG2Kuko4x+IDCgmOo
tdiIPZWz2nQhwO/4vZeZ2/h2k8G21seDc3LmaeBgdDtzN4AczOgKoqoZlxiqh9XbRUQbyyUVhGEF
NRRAJbRIDhE/b2bdPrvlDrU13gXfceRigKLhSBqwrzdvhVu1t5VHThFl0xUMVG6DXaShN6LFBfkd
qMELJr5yk73mHmfi48ipz6ZDKL948hxDZ5mRLxceIYnC4G6Zvi4LpBtIFUnvtTU5XR6KbYTZNK8D
pRDt1tgs/oyKpT3j+oJOb6s4chzqzeyH6GA3/tNu0pptqc3PDRfETxx4+wq1DuudmWuvmAZ0aPdB
NCAsKw/QOJZEsMuJ6HXwdee1iMOKoPzsdIeFEmNt7XhRkOfamcXv49MHg10jX/lQ67Kfni2xnQbr
4reqFp+uoHm3eA1qOVCwJqjNDHp1WaWtSiHKH/hXz8hzyxxgUDc8MWMD37Wdb3tjHa1nggaLwGLi
rSN2SmS4RLT1AdAGlDAmxM+N7fJMoeD9aSFhQn6SY5v57Om61C8nId5zRNy9nVQxwJehQRaWF8Aq
fQGUd25hYUrTkKGV38LTKfhJeJL9dsCGZNA2VRoL7OWx1ZWNkLrEEAFjBa7TV8dwE0x+1fzcErpH
xQ16Lsmia4F9S7CxGcAz2HfcKzcNN6gt0ah8bg8asyRNgbd8MgnANmIPxgkh6lyX/KrjBP78nBiK
BoQw6t0yb7V0UGt2AfFBXTggPoW4cj3iiaaBlCgQT/IgrUopBb9Dok3+aWBDZwCDQ1Q5iqjyJ9pD
KY21xP6p2sAIGQ5xZV1L8lMQoMSJUXS/K5kXJ5BvQ6Jk7CqNXhuxV/wAflZu2vkP1asiBCBF5Ye7
s0byJmevvnQTPWCBHdrGJ6pmcurXwFdBd0BUm9krKJX0e+ggOIDrS4m28IyFCL8k9qBJZ9dyclDw
6GivtqpQ4tAMlDUr9VIEb2zUoLC4hS79W/d4Cgf9SwFGS2vcOZBsheQvadMRMpZFQQMJ9wxCXEFU
H6rhaxKzg8E6iQkFYAtxSIxcu2lyfYMFk0F4c6+4vhd0c3Z6oLW4PTn5hLYEsNOeYUzWPawLVGhN
YKDfkI/sgWtWAUFNCWwBb/kbnv0VClgQkaLJ1R0tbEMZJjoLVFfe0kjclNs5uNhbM8wDvcSbMiEq
TMCnnQb8UtEc8uriFBmwvOEezo7AL6JbxMFZ0N1oKnDkST57UCGqMOCfQ/isGpo3zjTk7uDGuITV
d+GVfw/T+U0Dcy3yqdTiyg7NT2fWEHiv3Wj1KnKKsxTRTbpDGYCxP5wHzQI03sVIB398CoeG891T
hI0s6e3pDFks7YgWvv9M0a6d9So7MsQddPE1IwjB0jVYbmNLUkU5d0BQ5JKdQiR0SL0vMH4mvwty
KXQvW01pzD/nVo1TWzvs2EfoAMcU7hoIAQhSpXFED8NKcuPLR7GZ9NSqFlKOA+Hj5Au9F7uXrS3v
XbNXiGOSbQknrXKJs6jmU6iDxESydyyhvcN5SgmrdMmZx2/Mv3PFYJhH1PAvsdw7X+gHkzhugVDe
f4vgZ254r7LVyo2qUwGAGQgynV5GBWYbRWRrYn9i8bMhMeo5s5FtiNvKpebRQRB1jccpKDqmhdYv
HtT4onhN20B6ChVUOuSYbDCC4ydVkiI0xNIOkhL3NWhXVvuJBIn4o8ELOsiLTRbCRhb0PU/07MDw
+9BpGfTrKHBeXstbnQVzjCc4CttauKv59t1KcPKmkDN8sA7EVDXh454BiEJp8VWbHqonp7dqboBs
mqr50B2lpcfUzwbCmEVTdBiOyPCVKuNkVFfcMYIXGvqt09c+7UHm0yYdwF2nlS8W+3j5VtpBp7TJ
Zb0xii99XhH7QE2CpCSj1x4he0uNUIP6enQ4xpqAlUTm8dy00jBDayQIi5em4F0nc2qcFwUkVlkO
z27S/a/MgSzOFp/fio5suNN0UOJVyGfEKBlwEFkzYFwcwgarr9niXRezbvG9E0cNGHSGMBy3t1bi
yJRFlyuB03wUPi2NY6zPHn5oqFhBkA6y4jpeVjQuJW9CaJrYByef4li0tZDyRjaI2ySPOmtgcSt1
Bv3rSwR27hQ6+3cwYRmq25ZUKrY3tpWjoUYxb94H8LuMKja1O1r0MpaNJ6kUBKP3LGgr1YHHb7IO
irtEqdKhpGd/Wl4Cr5U6jZlxN6N7WDvkP6/n4VKyEAZa2RwNRP9DxlrPEQDvcc6nZ0/lXMJpBuke
XbRfW14uzqZp4ol3Ktw9QDZqTTXmtdhroocX3oCm0E/9BIBYx+V6XKjMmeP9SVvBNFMC9prncNqi
DpOVWEpTCZvVCyLiRJ0qx3Vyk5E6jc/hBPOZKfbeyY/FIgTj/4QKptvZH2Ptz6nfMcfZdh2Ucyq3
We53hmCbGSYVLvUzFD2fEiVlpV9tSFm+lBicoyXggAbTbNnWyMxdI84UpShrNB8nYi/EfKSHy6sk
QVc0iPgqy+lwyoAjFcgNfPmJViVNFhgAnhZhDY1iQuziensvnjPIO1AGRHoZPOvtpwubJeUM5jMV
6OeN9LgeJ8RFRpXnkQv1HJlkVuo4wVPuvEaph7eZYesqM3s1CX724Pmyq9MykE4zMN1ow1YUmIJk
lrC6txSyBg7OW0n7QzRlAKfimFh0SbgZCXYMG2uvsupyf6zamMXHM7O6y3zkB1ORd7pIdCll/3Lf
Oi9YeQlNJ2o4oiljEPInuwhktLGjLpH4fJ+uWo4fvfue3hCWesgTFk2NmwT6zGeHnbSSu3kGaVrG
OX8BLyeoG0CMskQCw9YbJRBOHtI/b7dag5JRUxqN4R/bfHDkpfu4E/Ik+x/aF5mGffsZmE6pVK/4
k3M3jIlnIVHLXXQyicE8UFo2c9VJoIgR1Y30U8vRzK2d0EKAHCKyut5hKp5KytPVaa9QaIvEUDxJ
8ydYsQxl7Y2AScybaztNKlyOOB94W1IXpVkFsSEOE5P2ICh2LoDF6qk6nYsOwgQi/QrodM8aA8Y6
o3EuacF+HCN0A45oiukQN61HXwJ0qxHKVJQjYs3HZSiEBh1rAcHyp8ylj3xUyEdbKmowB+r52M2U
2a0CgPGtlwyqFE9qku6kQ/JC18nhW7CZvNyUmbKQe6J4VIF1G6mjVeP64ItH217LsQu+XeQyZ2Jx
glXpXmZKcDu0CCS92Jd+3cmx7En+WV6A8x7OJP4KoGrYnKW2YGwZTVJoKoqT3RYp7t39QHBcbjDd
96iTZJ5SJfrVbvbIA2NMmXcYyL1jmYnx9oAr1iGKr4/zQ+aCH/Sowet1D9lBI6cg+RGcSlcy+LM0
1AiVzhvLbt7KOtAYZhux7dAad/2+lw3IBzG92c4FKnF0aMp+iQIn77K4NPUwSjR2HfP7tPmjKST+
d9BTe9YiGJjgOe/5N/eZV6voCC1DNPR7yUyME7QuhfXMF+VkFfwQnZLF1g2nZeREbCjdJaSCvmt+
erBvrerL0U/GiGDtZpBWzBlbKL6kA6hyfxppJ70cPoccfYQnYs8QTyFzaYZstGZGNGcomQIUQ/Ba
tA/fBEC8472TOD2bzIw2/VMiA4YHnYQYMqLTkdi5Kuxn6iyiUDYJamg67gmyOSfVwFTF3iuc5L8u
SGK0n/FoDZYtFE0Ip6owY4tt0OqoJhDWIzlgKUhHoYsuO0rhRuAwgZHmwCjyH85PVkUoALJqTWlK
mHc18K99zEuFST9hhrgUZUdHxULXvy5pTNoTvfFZ2IYvmiX+rk7n3noVKgVLDcnzCnjKLN/ShqyG
D5GR4mrCP/rxxl9Uu7dspgTrEkl5FfO423Y3f+9iiFYekUT1rEmvGMXanhKsgCQnGo5yAE+s6SmA
sSvFytmH1lNuUDwF+8L3sw83nU6sf3fISSEW32sXlE4zdgXje6kEHoKVShgy663x7S0R6M0b5CDJ
ecveH5A7XW8YBaOtZuAD5KA7n+ejiYi3kqrLBHWEVBKVty02KyZ24RxC/UkBE2q7OpRQI31iCSFq
Ht9ifWl32SSmycQBc/pyAORd81oyYEj22zvvwYS76CICzX+B0ONl0PAAZEH/ffwb5IkHX8bFW9eC
tfwXvZyyrpma9/vGrfoc74YNALRYKZETKW67G4mtfyAdPThR5xf8EKq0/xtDQvDbXMb97npFyq3T
bOpCoRtMgfvz93JiQfC0LMpzpCj/w8RpP0u7jaFjgIIy8NiN7F68kP0HtA17COI5+9C7AU4iw0H/
ELfzjUg4DViEtMlvnL/D6fFpjtMbjZnwQ82QKaWy8FrWA/Je+elbdepn29k3pJe9aKgxAVd3+wZE
kyV8qkCaYFb6GCr56bkD3N4aI4GZ0MCB1Dgvjyt63otTqctSd2uEsu6IW7EwM6SoqB0Ni6vbMcSk
8Ngxtg5HPXK3f0EHJZNxdOOEG9+J38vjXqWhCyUGmqhCQz5+uKS2IUKF3YIhyS1qn95RuvBm7PYT
ehuDzzH14/+pKSdQ0gHAH6cUikCGtKWGUFuj6See6jywBv2C4Q31apQKA7/rvC97BIi2paggmgd7
iNpgYLDTty91dv2FkMv/DP5uDjTykeqSMj0FrOqsMuvSPAXoFHKBecKsDyxK+ZCNzdOhD1Q5srEm
DOWCRK5w7tzT1RB9VXiim0/DqFl0P4Fs+lJYanN1Qd6fpObL9IQR11fGp5C6IutXVRBGGn4HNbTO
5P6NpCoByNHxfZ2ppans4Nz6KsOmdfPCQdp6UVK40Eu7gtEmn1pcVqkimAlZ/T+bcQQBIkWCdMgR
sEFrQM/uAVNbVGiSTqnzDTopXsOzZ680K7mdfR0YwLKNt9x3xVEM9vhzJmzln3mUDl58ldZfLgFv
WILmz+qw5pB/sQFy0jkQyPaQjobPOnkiVbgQkvQUD6mkJXKFsGQJ24GsJUTaYrEb4EyALETP4o5A
f3ytrUFDHlYfuRxz9yNU8QdYs6e2+87rKAUAFg146b3hL3afUat5ZbU6wa1XwP/970AyWZTf1gRS
Ct7bvTvckA42112OtIQfq7Gt+DoihOFVMWb4wyVC5DKXK+QBBnQDVUE4q0iJHl7k122Vsrjs9+id
rCUfrRY154uJf2SuBplIL4X5vECnLUREMpuqnLZ00pJT98IyCPMvJtQtus+gshp80MgdoTVxb5Sw
Rlo/C69GBnz7iRyk3wdybLCONx8PZvUjiG3DLLtfXULPKRUsCmk+ppgQjtvKtPsBUyugdUnekR0Y
gozZEiNS5mRvpDAb+AVMfLPsI00mZzf/eUDD9RFgJnnqQEesuebHJYduD0x7m24nNVoxfZpLQ9kr
Ph0WL7tuP7gWeIhMYv0sccG+XrShoZ/r5M5CJ40CmLbedxT953SGqnS0dZrtXaaeYGO/464k9waz
KGi87zDnxoRwA3E2JXVMIhnTdEBIcqSA9kmWPnuNeL/NvDouPBDqKNtb6W9I3NbuJMqHZ+EMGAQ+
T0hfH957EsVE1dxOTvsOLqnWLkNF79aAuLtUPKrdTM34STEBLjhPfkM0CxTJVRgXfI+riH4jDJPp
J0yTF9+CZ4DJ2Pj0SlbcGsTLalg3X06sRYBK8G/7aB3G9+8N7XQkiRndDvNLr8ayF9NqpCeIigjL
u+syGsEHU9GCHsLjqLfT0ZTxJHDT9XXqCgV0xX3E0oJY1IMojlgqCdOS+cWwzMzGII3zlQwfvS7n
KxbW0I4kfhcvqEQofZkb4yHBTQx6nY3QkzxPDW+dFmmW3VrMJofveXe0uQ0QE/PWyNNj/Zcud5LR
SiyQNC8gilQU5RRTxUNcZN4SVzFVa5go4lhFVMXoTHaCwezMz7EzxH5vrh1nMAbaam86h5lqliGP
19k39GTRg/iVKmEtjOeQ01La13ZQLdp8Oy4SxZd872VJowdVjKOIQzyXy5di2jkiGoTsVPMTGRnW
BSqpgWti/mhC/kTrmTwrGRDB9oBvNbfwr3HSqcRG9CO9R4Px7V0akzBF077ge2jhGKYwLETTxqXN
fzLjFvQd214Vv9FuuKjwHp01UpDRuR7gVgKutBPzj82kVbNv866v1YJACYdkqxZTp2dwBFgxhHZh
sQHRC5QiEp/SiXZEILSROy048rh906Tfm9QYFSNRKDNkid1VCGimBOPjgS++vLmkv3h7eRZtFX2M
iwi5Or4A7nCz4TjMngtQPh3Ll8l2EX9uudfpQVF8nkaGzZmPZ+LoPAolpIXtiqHvB+hrHTRJ57Ic
DruA3qYMPH3eSAG7Xr/9wLgS9Wz5FwvGu2kxV5BT8vd3fsZ94PYTLcfRNNfymMlp9zrfQkOD13wo
/E6PoM4fM2NhQ+7ztx1YAb9bJ+NDPPnC2u9ntBC5XZZ83Xc/Pyr9pVShrd7F8AmF6vIygKTGO1HH
3hM3By/7S3fEcq4BtOkGKF73R1k1L1eilN8iqVlseaxmRNF/WRxLWcM424/+PHSQfTpdRDfaDfoN
/nvCg3kmY89muYRJle1YRH+t0seGJubaC3jUJym8Z56xhIWwwxosav0TnScVgUU/RZKMcVcNkmU7
a8WbtR6bGlLcyIESGODlb5734KNejF8BbFj+qNipIW2E/+W9al04m6WaYhXxhpGMkbEnpZC8SrBi
dpBEKLXrio0WEkwvQdgLQaDJbD0ZEbeKNZJeAqGS53N7SiKImKqlj+wMq3Bgc0HbeF5Y7oN7IvUO
ArNFhnHwg5gf1Hnkqn4UN7oLeoClUSTkZ1tSibhQVzZThO+BxR/wEb7qNLCDWv/MhnbHxNEghtS7
HN7qa38eHjYl1H45RafwBRAIOyuB00ipyboFzSPVxtLXJRt/kTIa9jYw/HeNrndMhsuSgpdWHHRS
kcTOg0Z1727nyFFwO9F/hxpDcPrKK9ehU+1aXft1dUD+GHa9d2UOTJkqBLfqHOTDUuhqYuzvfCsY
A7Xo8S7bw3Y5IpnnjYrEf0MabgEQryAjfXe9NJfAjVGkBsBqU5S4xFP9tcw+hBNRZZIua8A3Yvxq
RzHfXTOotj3FuW4oKgyveA9kR1uWHYBaYBZvnAWFvkt8LjA8/oT5WxwwPE01gORgzy3nzDyO7C/3
LV5TY4zVOdbqTYJX1SvHFzNgTWpMc4jvJ1L8juiGRQRUWMxlMM6SbL7SXNW4XsuKmYR6cwlzqUiq
ARd7WUqE14jqt1JqGtmsskzS74P7Li89ss1fAUONlhSCTmgy8MIMiJDuISWKh4gx8AL0FVNZMihN
NU89dk1FgXtOSsmNPS+hpc+oMr/RLYVSZ/xLGVMgjFZLDP+/2L+G/212xJI+n+F79rBhGTlWEI/I
3AShC+Y2bmmwc8QNP63HDQyKyeYSFs+z4lBEH8rccVkFTsG61aGUwi6WZmqZHB4nnRrwwDljk/mb
35Z+9QnYMLbV7sTNxR5XHqKE7CWK2FyQOZNvNkJhXNg456ciDZaSn9h82WwEtJFiPZIvT7YIPM58
ohCPE+rjrMvykD9HxwoGfhOec1sKblJnb6RrNM9SCcJVs9rsGm0X+WYTA1wuThLsxbu4Zhdr2tBN
EaFbaC+z7JEjBjYTye2/DsW2MdT956+xLMQulLXcT/kXJt9UVgWsElxkHQ4Ws4xdmgDwx8MzVP6z
yncHGkHsAVqCTsCSbxU/9M1jsZAKFTgs0cDsT8ST2q/Axu+e56SR1KrkFW4bCXSg0rQFTQwLaXdw
h9/lmMkolwBFKVT/8tz6S5EOKca1ihMBTXjbnoezPGzs7xA07IJ0hh3GX4hm9hF5Dk4liJdNUWaW
AsGJhKbQAa35ylAFPyV7mb3dwU86urMJUa0A/6Juqn5W0z3g2Gng1Mb65SkiyO4w3+mHYvql3FcC
ETvhSdbSj9Ib2mUxwRPNEywd6jbh1zsx15t/iBP34zE2kycmzNkaPYS9sVT9LQSKvAJjIjxGZdH+
SaYGZF118GqrHYuFLIBlthjn0+01ath4HLeoGGB44TLnZr62ngRdAETBpTv76r+GltbBsq52zp4j
qqLWR/U6BDcYqGh4bucUgw8v+TlYMrdhsuTPzBxTIz6Y11OxSkZCsM9n8IuaVWaPCoWK/LjAD8hO
w7O5YWfWoz/RIQwsfajhyrOEGvKq1uyqg+dMd22jIDSvmS+udV0h8PZ/GsRevOAYJtZfNApo94Or
JKk/3OT71MMwiDi1WyM2C2IATUqp+GY6J6E7UJq98EtBnD4nccODm2suipwESPSb28Abg8ld0EGX
UKDUVDoLRBvv6LXc7iJ8wSipJSL/6iqIhfRRaLZJ8Mv2wMiatIRtou2qICTZYwYVdg3io8HPY6uc
JxRav3TOUShkRuHShCtFwUQDZchEqHG+XxVFkzo4z0xhrMNYG/tZ9lMsFG88sbytfWoQgOxZ5yol
xghh/ARhf6XOO3lNIWSucLcslRt3O6oN+TyQWQ8PwHJcFxkZEueucIUyDV6U2fua+SqSrLlakaV6
O6+/siur8wwmo0m9CGPPFZsyIkDjhtJ3oa+NOR35YwmCGs6RJF5QlJpOO3OE/FoXHzY1Tc2zwO/5
hnUrLCuUHL08AQ5HX6N7rAvVBp61T09ojh9Vw8uUPz2zbqa6CXD0LwfJyqUVnhh80IkNMKwtD3b5
D5LVOWIk3CpogLyY3NQnjb6FRuhTZBO0sH7MtFCpXBtCVZFfGkUZN9/z8hmsTdt6lp5egXcGEOWg
66hDCyuYepxuRiJ2le3SIwBOL1GHZPp+o/M7DSjjdZmgQqVfd7pdwIeolDdzuQGozJ8CNtmFtcXm
yZLpi3xZCeMpgEvOQGVk+QglNhyUEyCBnkoGMQcbVILyhsEYCjO1r/aPu+6YQRzSSIJVWb0r1urB
rOlXry0nG8vjM0Eua1BKwZ1OJU8TJehY1W/trLzJKdTboNyh8DebFIF2M/6SONEwO2y93Qc7JKmw
SvP/pZ8L3TlHJ8IeqHPpF7tX8Syf1AobFxITCFo+pmHis1oP59A5yCEEx7npx/7cMw8XHKqSN7Ru
GKg+9GMi1UxyrD/mvsdcc+l7s2yG/GJZhtbeHUeOiNwJPUwWTleYwhqRbsybI2G20u9gNqJCzN84
fEyr6bqxwBrXlYAlZrFd06RZrdbUOwPzpT57GsKs7eMWIqp0zXLeS0wHYOtTOXy0nF0CoH/vNOtC
BLNsEr+o1ZT38xBKJmv/cDKDJCGM72vIVAxwDGivnvGO/bniWPdKGZx97gYn0U9Pw79Ox731zl9g
aQBrx6dupt9kZ2sINFU80eu4UdkAdsUshP4Ddj3FoYnckwFWjbC8yweJFxyH5lxQiMaBoxCNT5ad
LdXWxs8IBdsQQFbBphF1/RhFQdO+VUONlPiJRSAKMZ4FLS2yio1h7OFZX3BVmufTYOtmjN12Ftqf
HOMQ9UZxGxrV06GgcODlMlqjF6Ge2oYcdum7TgWaLh4wWyQOydSOOUI26tL3C5NDknpXbTC1InhI
6qAXR1WDG3YIEDy+SNq9AWPzqbPBWB1aQt4gsmLIfw9eWe1UdyaKwsIrrdleJ0pHsVirrvMiGFUi
0dfwiSmnsbdL8DE5mJualI3ug6qITkGNqqe6/+cmxDzmnFYLNK8tq2eN9/Y1Rbmm5+VczgTgkeGA
LCVRJQqI3YkaXFDlKt1ZvQAmTjw2iU5Q7o35uG29lCilJfzX5rb/2g1oAG8FM56N8Ntb3a6KZW8X
8roMuJj+01vcvZ3YUFpzuZrEVGE+nAbkULquEcrkCF3+fONxAuQLGt2qh3TKRwk2qfwlcgVLao2m
81fhe9HAWgF/pAkzxtSxYzUP/2XS8Om301CgZQpFZLhzXgTqy4ZE3YnmvTLgQaDWUWbhYynF6EH/
2W0TdRA4aZATgBRuC8qtG0vtxDBgt2owVRmFTmwSVDtK764Db3quTQlMfj0yQNncZ+iM93MW2eCt
ZiK/R9TWbSKnXy5LFDLgQ9iShJ/62l4TcmagmzPhFIlSBp8BlzfDwGrRkekJTx8rMMw31q2b2lSj
VcItDahuerwTsf+4vQSwScrJ9L7ulGaustR3do5/3Z4v7JKTyvFSkOrsFP9ckJ6lmQxlPgfGaDWH
t05GM37syz2VdG1VvrRbcC3JHQYhWb9EbKsKEP99xxdl+//CPlW8jouqYFl6Oio9wFGfEN/KawZB
NrucvLUWc/PS1p+lSb8hZHIdtp5Sk3jmCgonyZoVcU72hMBo5Ia2T6zToa4WoyvW0l/usZzLqRoD
CQV4WuDjnQiAVjczj20wPNq2o4xRiLQgiN5MtSN1vuJLOjSowphaK/mAm0C0u54nEuejSGFSvQF0
FBD2TELfYi6vP9tyzB5iiz4JFk0Twmu9cv7C1iI9Zi9Gx7/n13n4eH3beQLr/anVfPoOtWtvo/IQ
1933lVQN1vovaXQVn1yBOUFtB6qh2yVBsyHCuLUryFlh+SHlweDjjqAXASGIaRpb4zILanLUuqF8
1Dx0midw/aUsKfyRYKZgHAiRXkd1h84apmZa5w8CfO3WQUv+N9/9QVyCXsFmaUvyTGQeE5Ag5F2+
kOymfKmYZHW0Ivu1I/u2uZys4eoZsQGcIm1jqFGLCakCw/CwzdVtcuqdlVzZX9JjtnR66otRgqgu
dJB7gtXaA0l99oaxYDH3gKXmV8gAG6RBgP9garB9JtxRwfljxjWV4a/s2om8ZGiHXpRM19lQWBYO
/uVCyHm6kT7ZaRAY0Hc87iIGOMbhViCNUw9KjBRWDKmN+m7CGr4OwaB0EiTl7s+XLal+xC69ZlHf
3PTrbd8dEkPwNZw1ck5EJYNlMpnAzBiNNkcHS8JpYmUZGYR9s24fPWDnOVv/cYOFX0N/+M0kTG5F
NUgo5oVfAc09NlSx3EUuNwuGDvzHZ4GM1V7F+ZaLc5lfkiyyQMU+Mgf8iQ5927gWpA+aVYgNV2Ju
OYcqueUy/bCrF2K2XyRi/Cis73j3ZS6uDPxEP7LCSlgurHAtE85OSj4Y7LA/DM3Ov9pqMJslXEX8
hnzd/8fgoh4B5upOTn2DUGNw2jw9RrIz/dj8X1+DzmTwdsSc+ZbzOO1zBo7Qgh+iP/alcP6v3uZi
ZXsJUPBfXXTldjHU0ftgW5wQduYLHEAzmwd1gc8FHkHJDuIZgP3XkjMh2owt8YiEgC15EBZstDGs
yd3mVlDuT4dUk+nd5ZWoGVSlZ8X1suxJ+JLmWE+tss0fkxaQdN+87uxsLXo+Y6FveJOwcS4ERkjw
VritymYicUjTE6bfaA5F9pfhX8/WEvduMdUp0afRRbjm5bdfoNCpA1VEQsMAzDCU7HVWFlTnvhrq
eZcQmxdP6SCkvJ0qUmQ4hDZYLLKn0Zg/TyKhvUo+PuHLY8gJLwdMO9cIuOHjxBWENhv+hfpn5aYk
uKMfM4dojiMtGYKbx5jhDgdIKF5BbvsM1zWsfb4q6xPNdPzzUz7P+GoSTeZ8JvGsAN380+D4ekcv
hjvJ1l4v1cz7JJVQgw80KS59oMIuLgvEz6hu8Jmrm/Ehy/+z6ZoboTq98Ahr+FRSHl5rjD+l+s+T
JjoXjygL7QQb4Rh56Y1y7I1HwLqOaZhv5JSwpcA1B3LMpxJ8qcoFHMJyjd7j1vW3n2qYIR1h5pkp
dZBEGza/un7B3KLVSJVgYuNmZYAy8drbcta/9DMXvqK148TVvKK61rNymsKfHqh89AhOp+131U7F
ZAfbFt0dYiUUd3/aBZQYijOneJpAn6AXxb3TGprdEM3vT6Vjh49LbCz4/qG3C5Y/UacERJ/d1Da6
9SYtec1mEWGa6rSqziOFh+WPbcC+xD7d++o9jLwIbanaiheYuH1upZDoSSZliNYS6Nb61DOlqfkv
lScz+UEQdRNSOero+gQnABTHjwNmAx9wEXZPnKnOUKE9W6ez8fPAct91JZxf904NDvg2M1pAGHDr
9cHbgqJIm7Rtz6O7GjIv3+00KsxpUZmlUfKNq58pNnbiuqZKFdcQjIv2UqjVqfYBCjop2nFpigIS
QthIhCJat8ykeSEJMBO9JokaYsl+KF9KSePP40mlIMaE7TbzoyGkLwILwCYgrguL6mMlH7B//Eay
/+KNo/J/rgxDQKcaIk2TP3RGelRr4fX2eKSt1bBeiv7C+iJ4434kojza/WvERtJJTHnGEbxGnneQ
Suuwy6WKC+Jp/7rQICc5Le7L4HSXouSsEftVwaecOllWq3aTjmMzKgOaVRcHUzZHW4BlScYQaQxP
2ksh+ZayLAHK0RjGxhcfybSroFv6xtKvnts1HY5vaEHFbP14Kzj1Wsl/sGw5V0P8b467YCxGVRoy
m70LkRmSKzX164aBxVCEzLNfMEFQaQLPhl6Cpi7/N8W4H300hF07USkRPWXs6qgEjFqTzYkq5r6f
0jTH18JyFLkMnSoA6eHpsUveCZykkEN8Uk/3fn9cvjfnI1A2tdhcv8Qle0rFtc0v9VLOxOSx1jsY
WrkEogWk2EKy8I5r0RNKCSzKIBojk107lomVTwBpyiLtQtGaY7w2gS/S69iIVItovR27ow0rBLUa
IDbSRRTn6Rg7iY1pcMb5QUK7JOd8b6MEBYKqJIrtdYwG6zzxMVgjH1Ant+/0k0Zfg98g0bDyUE9+
OJ0T5RrK9RSUg+PvZ/iJdw2CMExZ36LEVe46yKpjAA3Y8lKDx1amkGSIpaQSFqL6akwckajxSbfK
0uz3aHeemj3uErsWVAowP4fXyMWOsIkS/EUvbbIHLHqS3sKfiK8XlQYRzYRFUfY9ipnTqnjFowCT
beWZkg+03FuiktXr3A2S+lkblthwvaAWNc1qA57dnjz/g9/C+cBPJ4uqg1jLaRILBonmQashr9R1
MCVtjdiNsQ+vMRW9s1ItUqpXG3ZOBS/yzryK/a/lKs2v+wtXgW4lyKLwh+XSlVsxLiS0QTjUvcmG
ED50HuOn6g5d8IufBZM97BF4RZn7A/DSAEICNIVYdD3qJd4GUfVPKxVRUk5uDTFtS0w94+Q7R/ei
6Oe8+GjhQQTm2DNZELkuUJnF5M4POH6/x6d3US/+x7SV27laI2ES/6Cy967wnMz3KYatE3Y7Ov8S
hjds2RCvr0MZX3MtNY98lSfSRzAcJefTDUzpHIDptz8wqdqv/v+vhLOsCfxzXPZOAJ+Tpqul8L8v
Ey3Bq3kGrpPhtIq3XaSOYa26R++rGOuWFbWFLK23UW+6gu06PMmdOoyAWhdnYA7pREwOP1X8PhDD
U+EoYwhTwwpEU4okeOc/Ikra0SepMq8C0QKFUbQaOCv9ERrb1USGVEFtrUvvlsNFGbpZE50FzacN
UHW7pysUicibltfmGwzx6we8r12JdfXV0K4XpbPqk957C37sFhxVK0ULKjfHh+ZWgmAbNUkrMQjF
0Yi1d0Z0kd1pZjH5uI1ZlNdVB17PNLDx7LPnqTm5bMJLIS89KloE6yQxWTijvWoAf/5uj1nFA3rq
loxUzqOjtCf8kT0QIRHQDs9CTikOmSkj+GA/6p8TH29rRks4PMVygV9ot8AlUvwxp9fbGFqA6Tk1
2+8btOhQ2GjymEAfi1H7DRLnMwKieez/7JsFn2Git4t1459fJgA2XP7GE662Yv01DqVRdLAc4hGL
QdwA04AKLm6l60dxY0YrsoY0ESAnvN+4bRbY3oxMWzGrLIUkz76KrhfDrmFzxG4d8P5xzD5BmaPN
LQYP3365Gdh2L6j0pLxoKBwk7oNR1SMqHUzAVf2g73vBe/u4iqfFGgAvFen6R8Z3nM47KV0yj3lb
wUkRgySU9DOEkczpBZuDp6np9dknwsi5GYq9ln9DO1zyaGw8CgQ9R5Erd/UOqtD/2PU9rFGLjv2n
jy1c6HpcQXtrhQ1OrG952e+w265V9MjSGdC6Zcg68wCdg961u8CwDgVCbNy2klRMiFgSn2cQbEXj
JnHHn186n4J424sQWkAVc3ys0oigMMaI6d9+75R/3oObaWbv9xiIHO6BBEJIE1AUyFShqHPQZjwO
+xB0vAjZGA1uLNaLzECZlRPgiUh8qUg2P4wlEv4NHWdjTcYBBerbiJpB44sx7lfSxxAgIieYRWKi
DC5bM/1edUp6uHuq1duMBk7ehg7Izx5+JnMuMAtDoIoxY2zfnoNYVFUaLg3M+BWT/bbulOabqi4m
xjF+Tf9/ZpNjaOt3GrKOH6mnBe56eZ8uVEvhyYgvXp1yO6UN2GGUs5zN70Jr8HpChdxFlXrC/sM7
dNrg4LDJxfYNNijKKrRZZmVP8j8iXNKTd5bEDLEGQmHxknFVdBO+Pyc7vNjpcFpTPeJb2G/nG1gT
Lo6LpsjbVkgdA+ldPnHgyPazkoI5yHEkvO383S+cKoBiByv9MwvgSJhiBPeYzdstT1zXSmxzJLX6
bdtZs3uMarqZpsjf6gqAqOo0akN3Yir6O1x58FLyUxx5DPbEyHov+L6N9hZN/tG4WKOOvLd4ejhW
fZjhvOZRvldkZIKwjUHp70xSh3HFKHzIwf1Bb51vPgAGrhHlzq9eK1+2gAUlFgEbKBO4ny5QfEfn
tX3mVO2FvmTEy4Q5MpIm/HOtUDcfyixYnpaf8PCkws4ra7TQJb6KPyaUXvM/BU8pZ7SuO87UVJpf
oMH7tYLYYJ1H5jFxfsm5ZD6UqbjVnWj2MQi+fR60a10QqVJxGEtcQsFmlWk4vKZTATPOeRsCO2As
kBNquL8tLyX3ddH1D1N8ICptugLv3UUJ6nwV6wi50Z/S+FOP1NTKc4QYUUPy+N90TFG7fXYe3mE1
ASQAfYyEpNXy4noQXi+AVrQ3OcFFkA3CBjJhXJByL7UAHtX6KsNM53BWAvOM8zLC1hhVxZktJm2R
TADi7xb59WyI1a1sYpTsASx08WurNnaCCBxiZ7tvmX/VYk3xhInU20SC/h+iF7bJ7JLq/aXg2DeD
R0vdgHUcLRmINELkgAQWT0Q4F6whDdx2FzjEW83mF/U8mF5v01eXrILXAxAWkvO5N2afETrj26uB
jSIyBuA7F2AH+JAucMG/H5Oze9ZrqahSE/Z2lp3ZmIpv+7c5De7N9cD8x63xPKiu1RH0N6d0YXdZ
O1ffh3qPKz8XU8nFqFhI1V+KFUd6iYA4MKTDaOpN3NFnLPDt0txhV6bFaDPVmLK+TrxiZDf6I6QO
rJgw58hrioYH0bLmGsMK33js91ODLrAzxnQ1isglukpxthtxV06H3ZO9nkBC6CMhye3KONkgwStv
fA2RQWgNt5zASqzIORbq0Rnjjia1LKEwBuB/KIeooVWfaqF1OvnEcepNYwu16TvuO6VF+3SiWA10
BQPm3VLJF5RIB56stcmAbf9pL6oJmYf2PGaSg4/vMgkAlyqhgbtLNbERwqz0/ynp1DbCbfhwhZih
puYJL0tNYIvwyRZUnuSVOmZQTFZ/5lpM9H+Stu0kk21uJkYdiJ9Dchi4ahlkYgcBdQd6PXODMuY0
2MR11RWe962OqNGq3JzQTaNM6gpB4vMzEyoWAan+Nb4WlXLmr77KWcfQJKJIH3/ZS0oyg7wW8Iis
cnJJceAUgKjw3jzC0L5rnz6KOlK6+aS4W78PJJSPCUx8cy2vsMs6OP+pC3b1cIJsvK73It/tCOX6
eiqHmCPjDf/UStfTOD0oBGHNBH6oqMGaxv2CKnbb37khPUlHHktI/p53JlcNGByQOBWX4qRFn8wJ
UlJSOiJ1+dEX9P4R9PBXCcf0ZSLKOCtUk+fytMargtrbmeTnNPxzVPJYik+Uu8e34ew6rnbBfBNS
wtwNRduJUseL4WZb4h91LYRrdny14zy+0foJQWO5exdT/sBmLa9YreWHoxTzBaDOW1aiWe8kaCaj
hCBioJ6MRB1CEInSTJ/Qot0hPrS3trRoZoG0FQ3MSid0JXZ6AwR/vjRglbwWN1voXg/sDfk8vrdt
max+FlaKcKazR+YPVeJcJmyArkvOfrvuK6Ym6OSMYQN1hfJwhaQSoP1Fiidg9VxidlgjhEEi10i/
bh+/8VeouBIfxm09K6XAQeF5h+VwxUTJMSwYNKB8P8eArw0F2rOIOhhG7y3BZSm1cQ00eewE9fSj
+oxFxppyP2dIb7qNkRaKnCRyt++9Kzn0iIRf9V3ZGH1c8xq2fUyEHlE4ICDmrBPffx+We1FWubdS
sc7tLOIODv12STJ+4RXPXTXUXCCK3ou+wi3FY5eL2IPxUKkOLzHu9hPO3864dhgVauDTMtelXIpB
PqIz20iYWpYDGOuXybvQtTBlFgVXmxCsuLnzWE66y0HPmJQjkDIuUTi077ZYNI3rCO7AxZJgW67o
jR8yr7M1dBOUE0SOCm/N+lyDOFw6X59r2WO89tRQh/2IMrDyK9t6KVnHEGasElGoYPwf9VpMzS0s
V/MkjoEautvoOC2RQcO867Ni8qt3X4b7kJRjqoi3rA4Dqsp6XBaSJIAvW1u8IwCj5zfiXFp6Q1pv
toz9KLLJ5yQM6zSwlk1cXnrLRJT6GZPazFWNodeY20IetcHWpGxFNnu/4Lces0gfcmt8COB7Gj6F
ZI2hfkOteUFWkMQu8/yMsWy+/SoCueSYJAW3w8wTVMIUcjkSBa6Ega6oY2IxrEpV3oX5JDe0L8cX
7WhnCgm66Itie1zcz3F5dhgPxjh5idKOYctfNro4EaAza1fr+OEcQ8VGPyyugGEEA+Rrrj5vhf7J
twHBBottYF2RM+847TuETJ9YWf9KRrA5/VSRB/zp/TlLSNqmrCnNLQ7gc6uozV4cirFbMaChiYvJ
xvpQVlmjzAGdGZTBaaJsZyuVeWcmfnklvourPNRFflfQ+n4Y7Awx8YAQOxmhwh4MikxNNHM4egOi
7q4okmE04QzWKx9Mh+q1gO4BF3TAsBlDNiozGHivd1rnTSE4apC0VqwEEWklPfje5SjlbT05umtK
lAh305m2Kpt+ApassAy4xny+gWUbs8oEUUbjHSqNb1wBn6jIBkWJuoXQAeiyFMB3o8fQD69yxKqq
smz0Lm/nJR9v/O/6nAiBJ1/awjbW/AiCCuOo9HpzjAXX3kR61jKcaK5Msii/9DoOd0yAJTATu7CX
jLB/HJfOw/m0PDgjFC1grU9UaajemGIjP//cm95T9tPVkX3V+DhoO/62r5tHeycF/G6SlGnICU7h
sfye1pT/NClBi5iDAwxJJczy3mIe9PF5Gz4bBQ+Lh3Tu9wbQRp3YsQU2jDsKAbbRQLA7sa+O+f3i
+1r1nWJQlN5i603kEMbeIzNWoVGVJTJIJTg+dLne1hSfyA3vjASXLX+vk9fB/CT1x1LzFc1YvPOV
JRsf54F9YjWz52Dec2GPg6K3qPXUt0nTyKhUzwcnIV3dR2PMD8i5R6Pn+rcw5pi1ey39J3vEqIqE
ZXZEL6z+hyNcA13ZcyTNp583CzKjDJ//cTRxLaWwc4wLt6Ehv72NlHnOrcCxoZKuja1BP6y9g3Ro
pwGI/qZR+e44OGIjuUoM+DzqcLoarWUcPKHwqlryuhwMYPMKalLBEoiRlIuuqW8i68V75U80aLDP
B1/SJ6LSmGC9hy41XqVrdt9cNRMc/d2mWe+G5+WoEtssjHV2ijI0E536El2gIb01izaiH+Onl0GY
aEtm48GSdc0xXG8yBXwZBVDxI0+cvUHNuuwrmX+lf+LDE6VaYccEX9CDWqYSKJ0jvPuvPi6fRMhb
wmbanzi56MtXaYSQzPRBcs91cavkvekMtO8KosuRU7jCXI2XIfh+uTstvp5DOyTkQIuc4wE+R3ZW
esmQRuKx1LhIFKkpwuUE5I+5VwZ/vt8RMPEjMXAit6KhL5opK4AtlGRoU7vbmq1jDMuZ/Rxzve8f
s+VuMwfL2xd+TPd1TnuDSpz12cW4/AKkx24L/u1LCINwVuBTWNfjiR3clPw+zjHgmFTQ/ZZGVcab
HBdsVO8W8382VDe8XAUwaIaQT6gIFVJJ5dFVWcxbSA7cvRGk21Ay0Dk1t707MGU0W9ggCOL/4O6j
oyC7E6jAE88r7cjVlHVG1aufFI1PmIz3xb8DvDeGFHVa+iUE/L2pvh1BZVLzHMUkVQwHs331g5Um
zxt551ygelsm9nd3b1MuiNrlcf3Wcv8cgdldw12yB2V9K0OSPg6oCpuxuTO/RSkYJ8+fBanHB/N2
gDjotHICBQ7y0I12gvLhjYRGaU0WUNyfU8N3DWEEKGhsz5+rTUf3XYFYggTkM78knwGd55yuexg9
Ya9/39ftCBCVbyvvC8YZFx/lrnkJ/wam+pIK0ffCYQ0eh0/V5vflCX4vESC5/K3pj7yhOsxbvCgB
qHxKZd0hgQLnFlFqMBW9WtGN2XXqXA/oezkucR0oOiT+qvoShQmoXJq79AVQOn3RPZGdRw8WPhcU
r2bDjkeoJqlmOMx8NICWn7X9maYbuypjWfDe0hCUqkOhHNW2pagqPHBIpW/FuaQONekbCDuNiqS8
zzqqc/ZHmS7/IWDCoEiGH5k3V6oAs47yVfU1z0twqKPf5QonOFHS4DYb172XVBBSuVqpi3IFZG+c
s1yp4lNaaJ4xb6U+DxSeP0WdowXUVYFQfBjjfiaEwdG0uJu3xvif2IyaL7PyLPrX3VmWRFWslETe
HCDepn6ZCvXflUclJW3/SNtLoXLV2RxKaU39LrGrvahjUUeTJ0fNeZWFl3LgO0/qbauZ62m+0uIM
tceJNT4+Vj26C6Xnvf/w/xYwelYR3IzjXLUxO6kfr0G+SqDBSpSM+fMboiIDmZz0zaaGT1WlupLG
8TN6YtsPlJOrrZOIeiPEWEujTaTj8TcbMgjboJFK0iI2y4E70cToIPQEOfC5hcWSjoSdiGlgpmho
IDWIco4SY0dPHmcSbn5Csqh9wtXi4fheS8qp1R52jdc8Ujv1/N02cYfoNn0C4lDwPjXYTOlBKNzl
na/8dq4SmxPM7HqurdkCIixBWvD7CTVqC7UZ5S+xOZTyw0kWy5hpXIgrA1q3vjIUQZz8Yb93Wdsq
ZN+9FMIZ6SJIgfOJu4WpacqL/umssef7b1wsbOd16rNC71uhhSnBZOOsmQjkiYMW6d9qOq0ErUA5
0s7gylg6dsQhSfj6pbnwxYRRLvVXvphZA8N0axH2s9dCs3XYOD2DJwiZkFnTZ/MCYZIU+BGRl+RV
ZYafioo6NfZtt6DRQAkhJADNCYTR7Kt9qGswV+S/Ezbm/sNQRYsZrmQLzhTmLzbPYmb+wIzSWVxM
fSNhTXJ0e/J9ez9Fr8R2XZ4omZfeJyobFjues30FrA4OthbahJOqsW7YZL6gHHyghlZuyDGaktY0
4L9DoiwMwHESI/dlLuVXmQsYPLPM6NHK2lIo7mkWC/gYPqYE+EJyCwOj2pzDPneQE0RmkMB3h1Qj
pVTrB6KXjCjmdxV5164ro/j49nP2We7lledMHeWgYrq7R/wMlsa83qqdgWxRZ5guoiedAFIDf+k3
oGB81zVLd6dB3OThmfK+1sJy/yE2qdX33Wi+iNMEUTzXpkWzP4PQ4U4YDcgs7vyxGumym24fpCe0
okr1nw5c4axTrR/eqJ2SZj+JIK9+rMcLdUI37ukgX06nlLEGX5R8bim3/EQUstJmzQFAHLepz8j6
vP4/eak2+j6PVspS99PUrkYxuU2hM5aZp+65QnY5aFzfDWdI7a7/mM6N9Eoyip1jFd3KKva1Qt2i
ZjocBQ49Qy+UryOhC8GrBdkI9S2opp2oKcAMGiOypSgkawXKU97IUxaU7qO08KgjJmx3hsfoNA1p
x5OCJ2Cny9EyvuF2uWdIrC9w4dZP86V4oBDjMvwzt8u6L5s+m970BgYzE9Rym9K8tsl75Sk6G0B6
oetGmQSLnBE6JnzRG4DkaTmc4lmOuvvVx3sEb2nMx9+sTLLrC5cZ9ql+hxarm27fMp/VjJeFCYDn
SqTEbV0h6YoPr15oar+VO9z4nDsB0nXIhoXfBadSYfBA/XCqHGi0hdsbOKDGWNGtR+khlUmKiOwK
FPBxd3u6hthyoyByCkJAh5cB6iVpn4cP9Hm1rJ/nDX9lGBKZVvs1Cjew1FBLsmIgQYmpa03IFTTP
WRY8xrSAviwKyfIVgM9kBOWVEgk8ah94a/4G/eyGUtejq5147MsKFWGOyZPZ/WJiV9Ucx66hwfQz
paOPQZp5FeCD7UGIH7Zrkk0wL6/6BfwMxyVF4YF7Gqlz/6g2ncgyEE0cAeSKjwXWtoi8Bfsgh3KV
PIagwpn4sh6Y/EXoZZ2U0krCMGVec5i8UN8pRNlJku5yn4JX6erxjRc8YZrMl+TyzXqA0loSFu9b
uN1c+4J165NnbGecTwtbNK5pLr+qTlsOM3bCG+RvHt3mbmQa3bMnO6eRC61rnW5YpE+H2BQra4Qv
Y768CNkkvcFztt//sArurHi3++SvdiLeAA9WSDrJoNKYoLz3JOMYawMTAhAxNXI+3KmdBno6IssI
7LTyP4/EMTplZu129IAuY1Dl8XNEeDty+GB7LrPoPX9QhIP97Cpk8HoFE7ZADfcHv8iUvfK7HA2J
xtvKSefOrAo7c9JUth+F6g+ygBb9639XrsF/lJk4tqBMSlCX4H6T5A0l9VhIR6d/wsUUsLsNC0od
MtamoCP0oesgzfSDfXtUM/lF/4sN9SFHML7/ML4OyHfw4wp18cfDUIepfvNRxe5KwssPw5xxe5RL
lg6EaKTrfEpGuMVcCCPY+b4maEKdh0wOlSqFr7It2vQXFrBKWU8uqBtQ6Q/qOTnsq1NhhRX8Bkj7
zhSiTE8GQZCobHzEfoY6wvUOkuczgqU7kRrx6PdUukl3CpiBcqSeNWDin1kL2nsRcsOxj9N/XAae
EIUguJGEL3jGl57jY0EmJJWNez3UIvLi4kXEcex+sZqMXLbmrBpAbvsl/2Wf1s1+UtT0WuT1oheT
9sXlM0b0Ihfe77SfAgvmSbHZ1yfdwkqit9DvBBiM2e6M2IZ+N2n2K2hiEfjxWV6RnS0AOm9yNTsl
+IoMDwCLf67qTC1A6Xqu7ViAsl8HRfbLjNyYFwHqK8dnpOF5I09kkKqLXbRjk5gflE+Z2P+Xx5VV
La13Xgi5PBDIfRL1yvCrIhfnXTUigKODTWNnYFTo2UGM3wkgYU9wYEFos8o+tgGmtQefg8uS7Lsv
Qn6cFJH7PJqWzugEi+fLmcsJNQ2zOz8XbRmnzQsMDzRPZXQKkpwWmunXI5oCz4iggp6IKhRaMWPW
kQuxv0UQnplvi6+XL2HnwEMM7Pw6wRhYQumitVE7OdKXSMePrhfNdKhL7lX06XqUL/v937ZfSU8k
lPjWC/uMrbJ+vDIuTZnxsT4qok2rC7vgADhrsBOdcbDZWYd87Sp3+HWkk+T4SPIyNoA+08peDNpq
cpWYfTShliscCgAJxcpLXx58oBtYC65m7UqMbYmVo6qwtVbRoCeICrcZEcNesJFKxDkgZyiCe2BH
eXiQHuHwRCOpSErNupdVQ5YQAAcpXMUMznGSkM7BWmOU/HnyM2EZQKcAzKXxdv94GMhJNgIulE/Z
znkJuyoOr68/rt25C1/iswisjP0eVtyq/lyK9K0xsMEgpuDPZ2OA5fFdbk02kBgiAVkql66QPf7R
7CvCDGQfnfOnM0ec8fPynbnxW5IHTp/Z1UnlU4EVFEKTTe+xCauy4sh+uwhdCN/nMajauZmZZ13K
y+ZvihqqlNCqGC7zRGzLRoICsbNnfc6C12hULmp1bcs6NGz8gD/0heP8CtD3oVP8vaPZBDnp+imy
DDElpY+iZ8mVFW90DRZL9vDUCs2vDmpESo6XZB7GTEzmGZiEVMelb3zRC5Hwu6MjFRxzqtzazFvC
uZvzRGEryz5v+QSEdAUrurSr4YrKgyUG3CAIz36WGgCMs8z2rHaQl+nGlPygEoGtGGOqW+lY7fD+
ATz6pWQlKCj11+1JY2fhGUVOylVxlfgx6TM7Oh7uqRU35VzX6x4vnIHs/pwZsPTXylGimGmLchSv
iGwqxd+Japp4k9E3KblLkDRkbcX88iDdtdN+Ek6c0Kd5i8te5wUXHCQDYye0ErCSvtDdTNPrXe8a
NJeDMes3WNzcYqW7yfh1Bn8xjlTAVuJ2dBPnj16CVzH/Aco8Y17rfFbRt1msdZA/UHrpzuU7TpcP
G28o1r1LlfV4trmAVRxp9k/bd7k53FcruY2ojQypfPbIfGFPfnmSi3wV8boXGZA3nCdvIO+4+x8H
Fo1hv4dMyQA8bWsz0SIw5DnIpnM/mA5FladNZbKu5WvMNxD+UCQniOu5YVLjx+WLCErERNtuSvn9
zyVmtECzUyXu6bWGpmt5SNI3S2NjB++CF3axh7kOlNLlwXwoc1ZxygfllAmfQPHt+MtHK2AyALJ3
8OLuhn+/QaMaSDJsMMPfS3vqwIytEgMULPLTpe3I2AS+MGc/wdgnVpZd/ZxErNEN0HhxsAeEuKjP
hNUC5h7Aapna8l6PNdfgNjdEMMLZxh2DnGF00m7/E/hy0CQ1pOBwHJtc/xcvOkObOQoCPu4lp9fU
bqmuMGWhigufS7pqoSWx0fTlokd79e6ig9GnQ4NYN+aisRb96JdGuMNi6ItIPHZfNAlag8DtTGoE
f3dPyve2I9q7Ve8+OrMqQGIiZDssHaGKLallzSNA/r63UUQsbU3vN3xSOiWBNHouf0kW5cxrsvZY
L7lINRKlAmOTopdwwOyPLU0I65r9RQJwX1mOPYIZtzFVp2JgrshNOEG2ZWouLgOLIGv1pb6yZy6c
Gyeod03K86bguaUZkL5iJKEBB+1LWTs9DJP8Abhzt7QQXVYdgzFZwAIWlFcH6npTcKay0U9EI3k8
BjE8XjPWYd1mdn31aOHYCLyLoFED/sy3tHpr5sYzpVxY1CM3QXOPuUYjwuUeDk7FGBhy82ax3vOZ
GRE4OZYP/GK07ZZYutmihXuvzERuYXkadNFpHYtB1uq1cBflxAT/I0WEs/6HGprMxcivcghuOApj
mbJ77oqPOqGg1vwEYPR2q3xulrxd25kq1PkGSFop2noy/g60OcE1vM9UIR433N4fk6RfeASCxjXi
pMKiC3q4dyIMp4aDBs/6g4XY6SatXA79VBKXPeB4LStNbs9mIBx8TBny94GA/XIIylPQxKjT2tPt
Fs+c9/7qGAyY8gbhGR4r5ncZtfr4+z223RJHvL+kNSjTVyIqU1kDHr98aUgMdfEMF9+iQ9pAhNoF
8tbd3lhJCxndH9S8jtshaKLemjYmC4gzWhNuJN3ehlbPq4mSa54LgQRoACv4ofI/aar0fCXdI9pD
PUrg5++DBOi/yYrxnk9UXCvb/z4KV18HSzEl4DR74QQWW09Go9Q29sL08ocj9upZyajpSc33LSCC
Eyy/Oo8FEecW+XjBRjRPSADQHXDVYYFwm/fD6Py6YCzka46d2SCSbZqH8dn5SrodeCg5JV8f9i1E
Peyamd6Ukt+DpOxkc6JXvcNJTiEKhtRfH4XSLEZNB52TItNp87H3xh8BI5eHkRGe+Uk/WJiKodvB
UrU/ufS7n0d8HnU2iiTUSG3EsljTNd2gxuAWbIvt3DwJ4qQmzKCkIZjVkSQGK+zTQ92MDEg44nID
bWyCUiTABZTP2bkpjuF47GijpmbDM538QlBoSkVKaGy3jbKTF2UJC+ugtzua/xm9S5DwIOENqqWX
VUrFjXoJeNSIW3etsnfLlhqNTMNr7enzZgZluXpmbC+rv0TyDALuyCOaik0hJHnqEaZGimrvlBeL
1/YnIeS0fw+bOkd9Z4Fa1df8FjVzGvdkU/9ilRt0n7mFh6sAA02slmM0Ws11Hq4mtZ6zQabOAL9k
sy2ACLlEiSfO8c7DsrWWGGHH8iaqPzLFgzatHcXmRd9ovb2/qaC//S+uX/pslDCUgp4alR/QmNtb
UDx1gC4zQMGBKIgjHVyB71QWlLs/okUhC/emZuQdjWOtXXm73gJ5fqX8m0NIsCysghDiz2JNOxl7
Qv1CExW2gIkppdJa4BNOBGnXFO4OcCon5yTtzwZg8XrEvO2H7exLBYUpP5ZSzniIaqE1agROXCGk
ZKbmnW6aF8uVnXVxFHqrdtK1hZHieFjMGQ6l3nHNPNwgVhg0mSe+A71eDuqYdKPbMV0k1ou/zoAv
LvFLsYzR3IRWPE9A+7b3FrwsvP9Ehh2zGc1WwDtMbsvyFJ+GpOHMBIctYtGZDOozZ4qbu5X6Rxm3
CSbvlQJpMHKFleb99Me+wy9hA7HKjUVtYGcjS4z8XCH2NswQ7P+CO2vOrsx9m8FHSxnZR0hezgzi
ZWKvDRbyxUrVe4T2CSVaxoI23icuNQCrOl/YxTAkduink6YUpR3iFAikf4bMNinVA4Dh/cTJdKw8
HSBFeDhB77i+dyj+PvwASx+wNpeOxSurig+DzS5rEYXmYTsSq3REg5f7oxJz1+sj4AE1FW4pRDdo
fxb90KozDGGoL/QxGUD+Qcn03182ZCb7D73dCYU7PoVbSsTV+ZKm8yMwkxw90sK3edLpmgcP7iiR
fTRc0wmjxArWmRbFWeMu68W6hF9FTUqGNZDS7yuEAlF5izZImhX2jWJO2JfKcJBcRNvIcTHTRGwt
im248MsPBauQ26FxPWj6ImBc6QsRxHsEl50gmfHTl7PbHTfLWpH35u5zytZJFF0pYlEooLCk8fcJ
DbYeXGcs0WjC+RshqorkV4OKLt4yBn0U8++IONVyn+f1yjxiKXrz+UZZVcPDNK1InOVs5vmmfICm
vbV/ppOcg4yluURAsoZc1sgAUVGOS3wy0BJT1CNLn0+Q5A4yfF/tufocd0pJLmcFdaaZG/dcTnKz
gkFbgaPkJGkpFspyHK8e192uLq4afzKqYUxqylrXszKx0fqu1/QP8JdC+CB7inLhDl52FzQF3reW
SIQXPJZR0gghlTa5s47K6qhhfjO+1+1W2YVDDwq/uC/nUi2Yj1A1KSpuk3weKf0IKUeUbkq71M6o
bmgXv/ozl86XC7o8yW1XVghLRM838cUw0IU2nfs2F0EtjJtas1+1kS4AfVaO4/yhKSAr0MBrgQsc
uvD22K8CP158WDjzVrtXh2rquQYmp5RyEatjR5/JWNXikZDdYZCNZBQ+D76vv5fRBFIX7zmhDKbd
DSrky5ZW2jcvQlh6CpJeEzAs+u5Z5h2iJS11fXkNKEx1QwX4LsfuQwTIk2REvLTTIl1XUFvCqnOt
nH4dKBHAIMIFbZILZbxBSAPDo0Q7RIqcgzT1OWdOItsRBp8gWZDv0kYMF3VYwo4wlqUZk/Wr4TwG
BxAwRY0giL582i/xr+OSAFByRF8fjma7mOWm6WQ3OG4mKEq5XeBo0hrPFhn/ZIRFKLXYqYSWF1ct
v+lMiFOtsqEAxyihgBOIepJfoLMTheX8YQW2uzIMjhdb6ILssMsnC3C1Z+cvFn6d+2hgEaC9gyEo
VLQhergY+bhkg1PtQhLmzxVnb8FaVyHcbWSaa37eYraCCXPC34OnMCfDlRSk58KqERq8L3UoXjGT
08PY3w3bM0mS+TMtJ6VFT8jQbo0sJOHuz/pAquOMlOBrBaBW/wfQS03NpDJLlurv/kuApz7XuY0Q
zHq0iuiCCzOGODXcHcuR8XzSdCn4DiGCSF3ZmpzgHP62EH6wyXB8ib/GvFZN+oljbWs1WIaO48wI
86wVz8foxlVKRe2Z85qRTpEVbXKh3G77Z3sAGQugnecx2bsqzY6VbBRgvmjo7TPG1PsDEezs8sq/
K4XvsBl10oNv9QeFOQzCc34YqstpYNcP/2ejekgKEGe7gRJ7jgienTc9EZKYdsxBKgqOjA1ev1Gm
N9dm61c3o9uNC67rTHmJ75ai6C7U+A0XLj8cPilo9arNhPSIRdJGdLqWhJYbWUVV5HaJlVYbdjwi
xdY3Js+g5/B/glk4/ij+FiLm27Kn0lZi1gTRDironN4ZXFn7cz2knn2E3v3sGzZf6ksDiUAlcwZ5
mwCp/XA60IlouztI+1STrFYyi5RShuEEzVC9g2PBPS50KyK/W70mQylgRuBvj5txKSGtHUyUpLnP
RrLpqaURdF/1waCkpgWx53K6kYZSVbbdmy8+kaFa1+0X1OosIs38AnUZhcX6xv1yrZv1C4DcHl4O
o/OeGA1v7d1GRRCvpcZy+OB/YPXYPc4NCMcfGO7PpAetrU5/KbU3q2yPHgGvKxMqGVWUj4+pjlFe
3GLYIRq3pmVHTNGuB4bN24NBSOOJ6xczbqGeBvn7RMUb3o83qngjoKcOhjqfEyjvRpDVo4gVIoDX
YT2jh9iLrn0DLGbaIpVCCo6VWkwm3WbD4DJaZF5HELdUnHyiVP5YTXZx9C/pHtAtwC99YiW73jAG
ZdGLs/82VshbKM0vAUG02rc7w29cCTBRLMMZcEwLJKhwgo7434jREBAOYSst1NVH8CSJr1ENnnNj
Np5L1cnZT2fLOAibpcoRogwbqnMrXvIjYPKz3U3pMxtd+1c67Zot1U/ufzsj0RZEBoyrCqHi+Tme
cjaujlK4F17w38evpD4kjdp9e2OTkv/EgmBw1DlDjFet047MdAZaSX0ifVBA/8upv6XtQdG1aCg/
QQiluFzlK/QoxTQbQYHvbwwaVejWqpCCdIUomEbiuOM1tj8BNOFMsR+dnlaPB27VIs2ljIVZWHmj
aQ/Pi/+8Kmg5UHMA1DYKIvE/6LCRLNRJWVZMV71RubOYE1HbugO9ikJJ0tFeT49szBpMLgGGmWyL
RrGZegPwQUuh046VchDjDS42IZn7xNBx38F+d+fgO6DyKpa/H8Be7fyPt1evFZRkxpWG73BgzCyR
MTGcOs+XlzAhTQDW0A8SNBh8e7uYCH+vTuNykq6wFHOZTz7RM9bSn/hf0nwCCDC7SEU1qW9SVs1B
cWK9fSHphtR8J0ywty0f7B10b5RZ/2nZZJ+S/6fooU7PKm2F4Zz563rL0c46RKK8JlzPSkNMQFtj
ep4m5ZCj2TnwXgB9NtXebTXj+9Z5Hip7lVsAZMkLC30NhV7altsKpRdGClRlmsOmlGXqPsJpjGSK
oLgWYhNbpWyk53CEpmAQS71dmyVefwNQ1/q/U2ceAm3xBleDPRVcGIXCtoxRv3y42fgOSjumEmK2
FgfbAv8BvqFmkq4kSzIG7CP/FnyC7iJzdHusvFHZhx63MVIhxPe/GqpX5u7XrzIcqY4G9ocGQZEI
Jqn7JkhcocQWYvN+fxoRBDA4kXo6FKhBrfhmlAGE96/P5uF7vG+kF5w3tYBCcnkH3ZkhX28f0WTw
j07QrHVP1J/sJo21rSWKdqTCGSg1TYa27A+FRPTRnK2LaTIGjrh/QaFrK4joucUkz5aydqzhMuSN
UNROgrhjjIm59hLD7tX5rEkO7MB3CFri89Ipfc/n6rgumB4f4SSJd7Kx4KNBZmj4QsAxbeVGtJUg
tD07PMVkf1akDUrznqpVe5tolLYVsDqMItQqw6/Xb5qG4T6i/KMgoygpxGyBgBnjIDuJBqrN4ovL
Qq14GRZLVzvyd3Co9wA0qo33ATgAFh29rsUgGxU9ADLule1NDos1Zim3bI7aEbBaC8VuDlqWp6Mc
2R42Jk/x0Ec1XGUHwMvmiUx21UYUCGS6aJUa1UN+1ITOL0swLNAKhiXsReBdrcoXrp+896VCrKXj
IB7vfpI+jP0/TG82hG6nWLMcB9NAaDgTyWv2fAYbHM0RwKbombYv0CxVPlI1GLjQcKGwmeji4Vzd
t79xoT7w+FESS2lGXDMvwNEwrtvjD4sD/KK+uIOmplJhKOJzQqb3Ooiki9UY10K+T9YS5ataw4u/
FCpLVi/2xmzs2ivPdlDoVns/yXAzzTwZdG0MwuHABKGjiLUyar6i3Bg5ozig6OlcLIX5G4t1DkJu
T4AbvrbnnVhe5uo3TZRmYMqL81MkMxVF4E5em7cy1TC2tW2ucVTtDh1BdDCo3ZUZmzPXYIteAASk
QI2Cb/6ms+uNUcOObd803yGGlfOwjUovOFFIUHbra4CJ/HwNEcRCglfulMjIKfePoGv4pICbW3Ug
SvLKtgyTmA/U6wzJEGggkd+qLwjuxT44SMaCcHwqiuVbWJAB9oH2Vx2HRV7ZVG18rkD95f/OB2t8
vR8pcx/7VK/u/xKfmYYgxg9reyG4lb9AcWGzDR3nl8l7VifC7b57ty/UZW1hag1leDt5UXKzEd43
4l6ckQB2LvO7+ApczbHHxEZgvVMejn0clIFNpOg176O1gPdEVAFkPLa0CneD5ileqFSDf/pKHMMo
+LhbrL6cnd/zl/qt++C1gTwFs8mVJ0UfjOilMUK8TG0tNBoyBSb8lwR83/yebuNROVyWVFMd3uhP
TU/D9iDWs+3u5BPrP9LX+8YREOEaX3W1pQ96CdPiNF/j0edSz482FKuN/o+/y2+lk+XnTG6U0reQ
EUVhxH5YqDdLLABR7GKfcGcWm3z1b57OG+EdsqU3LwKfjbXuzlntAAv1/ShJXUIHHaaSjsluUuw6
DnjwR7q+3iLUyt3miL4zJzOcHGF+mYGEKUE60wdvDBxk2W/Z/oUtD8lV4+QaXWhtFOp43Gv6tpJX
2M7FgasbPLgEgV5Rr+LJulGomDnFVpjDi2PWNdyifROZsd9pulSdvv+K6KM/sIYouza8simPsZ4P
Fmuk27xxpRonBOTI/8+xRcv0blWnMqSutc8UcKlwZIsS8tPGIcj/I4iLMLGeoJ6Ra5NSXrrzBTsN
1H5iZKV93oLERfgFlBWHbvgfl8Ebhttm2TP/7y0qIob7hc5HqdwrB9pKUYK0vKTkng4fzUsXLss2
jtPycKu+De6ZfqrklWSLeyUbyawCj8fS0iETjBkVbMBpre2lnx/bkRU3og7Himm2r4ety3tNINRl
MAflLBSC1AQ9I5CNNO+G3wjNtsWKvzkGFt7uy4EC3ihWxCa/RnFTuYhA3N5jKKRvQOXmA06KPzCb
jjna1W20pjVXC/JQBZZBmhUDMWJH6mIDHjd1xwiYGFbjzY//8ytcGNwVP/Cpg+9bSRwnfukt8LAM
ypzgVPLy60lyu8Ajdpeu5M7iNwW8h1DJUfzYwvKmirV9/T/kF8sl7ThlL2JoMIG1hNNXjyh+MBuH
K6Yvk1OGbUAayA5n6nY057l7eWAsGgQMA07WFTzWAD3CQnwIWJ3cABbiEdgLfblC1bzTTwAjXGjh
OLMB67tZCPfvXOM9c614dQwt4Y2IPtaUAEt+rKH26MmCGjeA4NNU/2WxoKOHkdo78ZtmE0VMcNuV
ayAtkzK+ptmg+EmzTBtXvIMUnEgmUgOLy5noGw9INgwZm24Jsds4p526doOGm5+TzSVb6EXUmaZu
iAiXJ/uTWCN3r4rEO5u/Uc8cwX+YahNFIFs+GjD3bFtq85gsL98eP3Z3wdbs/kN7Lhwv+95TYsv3
NtbA1b7bo65O4/WypmEFwZlQ0qEYuGEdZad9YejHvOScyuzuPax/DqK/ebs66WQtuweaIa8QoIdE
FLQtembxLzUpdQlkQ2kKv/os/a/V07p7uZoKqxZJp2BQLdk+0irNXzk6BCEwZRCk3+T/tH38RETF
0fEF89llk+Q5mtM8jWpmezUIhPvQAWtC0d2Km+dirhkLzUsvFlmNpOk5zaOMhVSs1H6Wne6aQMJU
HJsCTN6bN7u6wDpO8oWH9LpDnCO7/XQ5wrNa4GfX7JUxwhggvtRJKoVirLCcA5Vqa9IBEUQPxsZm
0mCic9QZv/r0Aq8b9q7ukWPVQruZQkum6AZa+dW9y5FVHEI+92iFgk4vYQHmjem8fMkWPVgZX+HB
PrAJArd0ZmSwmMtfqmLOZ9Tz9KRobh1JaWOcywvEk0h+GNO9awj+88pxl9xQUVWzqoAf6t1Tf8bw
8P07bsHFujqoA6d9HmVisq3haRQosg+Cx5BjWwehYAF4dbB4324I9NcxRNvnX+AgTROmZ1ub1s3A
tw7hvyPG4pFc8rtJF4Qh6aPEMScmwgtC01bwgx6lDCmildo9harWpSN+boQ2xVqaPMXrhi/APFLE
A7T5GvjlSM6+SE51X01BXs+KnvzsboTcSce464WPi5xQPpFNcmudmr72I+w6KovTHZHSL1Wa48PM
1T1vxXJH4v2DH9AGqb62PezKMC15bFsH2BEehYAqUcT4zKDeBBKICkhFkQUMPSvkYku3FlyRzyPU
Odj1LWh4R1V6J8E+4m3/YoG78g1xiArieIvPWl9Gk9eEmxrfgvOEt4hObLS72EEh9ol2OzlMc3yl
Xbve6YsYfVR+1YoOv7DJ/3Lj+iqRhs5Xcwn/QJZ8rerMGrsfro8ShMGfaSGBUyK8kxqXEuD1VgYl
nrnpbBtgUFz/MRodQ4GQ7f7p9fpboL7g1MIIGZNZHoS12UX5+z5jbVbfr+wvsao9N2SUy7TpgClH
QAkchm/vOGElKXmzqWkg4eMCebRPi4LS060CDU9H8O53sUkzL9BtV2+CwHlIfIbvJ0V9mQ6Vmzn0
veCu88nJ43dBR7qvtWS1ho4eHda3YGVtEB9V3HP77nZddG9QLTNfBvDn8Wigi/I2/n7ixhfKQYmP
sga9mK9rVmJ1UL7M5ZSJrCSAujUak+cdNEnlkxn1NvZGoHX9QDKBZmC0KBW0un0wg/7gNMX3iIkr
nMVchWGJDAZq0faHWQ+nEIDR01NpCjdmdLKHwx1/Jvv3Py5J2h+m/uTipQbaWNXvHGIte3jZm5z6
b/r62GIGupS5Ih7K0qmSd7vuhYs2XOKLhBLcY9X6gBu31iufhF7fg8BPOG+NPSrCUxvakzfe+rZa
zhuQ6STLUZ2oIIlIllZ9LgPFdXpXTzEYWT7xpGxoAW9B5PSr/kiju6e4MyqlzFKNCzBrE5LGsU/P
YJyrCJlJ1XhC9jaTydZzKIaq0LoDP80VSVTzWS9F27m+BVcwZgs69v4SUGklK+I5ito0Y9DBURAk
P2DvcTH89JBIVRnR2u1AgPDfqHJi4y4TmGKi+jPifLU9LJ2tBr+/jecx9EwG3Mo/pMIuk/JtlZOp
K0+5Fg3Fa7midHJKRxTMCRxnOpea+P+0GjnOzUo7TrJPAmA5/KTyipFnE0xJYZ4+ZsApVgZ6NeBh
gRY1SLwKzLcR7fVkWcT1uHwNjRFKTIH5EXH8d1lfm6DH33xF6tamIVjQ78n0ZtsGWzIa+rnLt/73
w/YjYcNDGPCztt68u8GIQQVJslQiulrF6drlXS+sro+5Q8lEJt2EDw0IONEf+IQKWfiIShnKBlYs
IAsCriElngVZF+XsokMi/l65IPc1ZQj8QgjzDeN9gc1OPj21Ir9JLzEj/3ylRTjMfSLam4PM7Fn9
W1A4asWBB49O6Ku5z81m5zjvOUkPPQniATie6N6xjZI0qrrWBTWYsyJFhhehOJlsuVIiBb+V5Dqs
fpJiVIys6hxWo9qpytWFsVq2ySIhXtEZD5cmzghDS/qjcJP9Dxv2rJM6idto5K08ehx9vZoDD9J4
aSSRNJ5QYzu6gN54O0knKnVGiZ1DpITrNa64c5Jo1NnHw/keuYsb11/cPxtzAE9UUsG6JIuzN8Y7
MpuXaruegckRjlw+oK4SAT9FZaGje0KNqJNhEFCGLs8wC7urLZ/xRATFo40FpdIDBWPMlVE83bBQ
ssQjsln7uL/WOMmT4+CTbEyRDGGRAJSytF9IBrbPD7dYUaDYPwAnTgV6+875FfHJKDXLSpNNmkrc
vtyls/Y8oGrz3hLj8Moa39n5mvOOr5rEOxvGxIiEBMLolY3j+n9iu9AvnCkHUsfymtKKHuBCr3nV
LBKDTYOdfE/eKmHRgqLWyzzZx0wIT30OerQMMW0Sj59Jc3+nZXsEWvazO+bDNlncSs3uy4ws4WhW
lGOGyFRySxTRB9q38v2eU4bKyB4U6zJGVCUkZtM3LHWFLXTL+oanG8cYjWT3vldgn7ra+7exKpTO
BHTepz794+tLnaXf3W7atZ23JITVC5XWMxdGrQIP+JdW36oHesVVJivnU7XDAhmObcoGo8T3B6b7
ujEOGaXKpQYa3DA/uPVhWr5uhsCuQgEPDp5IeXLpPBZW/CCoert62G/30GlOQbhi6CEoxHXGSsUj
6FiAAQdK2fAgZszEf1J4ZkzC71LK2ue1rLyp8aj3soH2nXgyGxn3kVL7lT7NlFN/HgT8SuhWjy1e
WCybEd5j839OcreMuQFBX0KTsIewEpHsSMO1MgLiejXEQXHeRvo817hYW65ZUIqmVb2HwE9FvhES
s6DiUm2PLlIsjNQOC4vZN3NNd36hhLKwa7r0SIUlH2KRgLOXSZ6Bq3qV2p2TKkgQ9C6zgb5yXkZn
OUN9KEDj3Ce3pkf++kFOYzEs9drCmdLeJUkVfSidT86BpkIbNPZ5fThVirNE5Fmmj4eRCCwGvG3S
klvZDepLU4mLWgNUjqSDo8880OcVf50O0U4+GN7vhg5ybbAkgiHVwqcWCU/l0sGvzJcQrFNBH7a2
Q9NT13Fpw7XrhkMDR4C1nDaBPnO4mWw0OLzBwGOS3LtqnGfUDDcHj2Xvw2E5PW0hy6L73Y6w7gV9
fgIPb/m4nvu57aoQyGES4TQsJv6vLQGDGFibXvgKfJUBjO/F4Gqh0/Y5Uo52uWFcqH8pDBaJtJcg
EfA7VBBfD3BAIXeeqc4bGntpOSkMBxrqh/+gQtpDlPZXvcWeHJFrVERUUd6QX2A1oIf5m7+za3l3
n+iLQKF3WSDPh7iG7Vr6U3LxOXNFFD9N8l22IMxVuGSI4jiOvkFV88vW0j5gfXYQIe12aG1U01U1
1i5baZcPpKruRFuLCkowI4/y8hivhxplUhyE9pKnXtBZMhWVUu9s/HX6ZKD1KuBDX8dJQ6wcWuDP
9vHSwhdLgXAl6sbPjqKDyCMEni6DqWjWbJ6A8U/F+U6dzjNp1kSaDaakTjxLZLz2axqjkD+kK53h
oQy25z8e1DYOEK+L50/G8TZ9xENhrzvSiwEBocNrdKOYnmBWV5wyIHtw3me9Rqz4wjLPwi5ezCz3
9LeSVJQuz0veTPPH0OsbCHS/GD8qdXRRvS1zmgG7hyiHIM2Y0tAzRtd79LGxaReIY4BXByq873IN
BVjBBbAMrE7vQ17Vo5/Q7ZBY87BgA80NwwEwxzBcX4j2JDZj7F8JXBps4MnYd/FVnhHhKnor8EX/
uzTiL+dBhTYw7hF8Gc+NbErZQte1fO2oS8/eBpDmksOHJD4cJYZ/F3lU3eJY68v1Sczj3sgsqnFM
SN5k8P27yLkiCUcj7LrahLcHftvlIvSChNS0KKhkYR6BwLra4CqniocDCYO7Yw6LDWRX4Td/rfkE
3QCDyvka4VDyRwe5xXIWK0D4GN3WP+xbOxVHtNygqfAsOIW0p/i9KrWsd0F5kVNom1GeuACYTzbi
r7TU9LnCHyUctNW32U1kDL0bBRFV+m44xJ66gB+0BnGB1W8mXpu6T/TOpOyUbUp0bcIHu7Nev+zf
vYxQ87ucdIjl7nfpDea6xV4HYamejIhMNwGyifyoL+kukJcn/Lb0FPF5SX2MHhIhPydKfkQdzLFr
Ei0vLxSOhIODN20KBnZGsp2yeUrqgF2OTY7Tb01A/J+4KuwR4tOVWhAvXy9Fs4YbJWeByCvy06zY
wxBhuunaE9ufI73ImT2BLT9ZaAKOMQbArIEIbFbYFwD7fRO9e8Llp85ASKTDz9kF2G2nQ1JRR8Ts
5QDcbw2+30adcjGfRh4vGnAk+Cd/vfwcpC0LhvmyS7ie7mZdwD3pXMbLcT/+F1y6a/3wpVQiHNUD
8+hE/s0Mr861+7jsNgaiweYWvHf5MsTByLTRSMi4QTRrtrGBRKLRx+pB9PQvO6/lEiiSlj+/oP7t
WngUMy0MH/KqKabztcBY9vYJmGOIQzKrvIoqDqILE0sLjMLCIVK7MfosCMxE7mj36IgRJh4Xyiz2
a+Z+aTQmZqtA6CyosxwAeOwl8byFCttkDPYooabpWqM8k9QDnlf4diARV6NKs10mz9/DgzRhiypz
NK1iPYrWrCcDjDJYpoRZys4zqJOFUqbjTpq5ZylJqUTqf9Yp5Q3v0EtC61GSmzGOcMM0oERpHvI6
MSsMgbDPD8BJPWiZsFjnD2mgLOykChT0a9cncJx+I0zKN74lMMNT3KKOBpyz5Pfpmlvtsb9cyAea
gvJ0z4JgT00PCjtToSDmjG3UsieSOAKbojhHhJZqyXKiJCUk9Q2cHtDU0nzW/cBYT/rnPwHQLbnZ
jB19kUBIxyCToasq8hwvhR0b4KGcSrVjp6tzN9acoHCzDvki9Zhk8jlxc6gf3SMEuC1oivIUtbxP
AsdbucfZ1NRoQ2RX7CvN2zfBw+bTsoe95I6NO1scGxD6y0GyfftGy8sSsZNuBD1hw1JCYdM6QSAl
97vPeyaFukP/B1Q0rg+gG8QtY+pGy8cIXAbVzcsZJhIBTNRlA54lT+0kLom6YgAAMt4z2cq8FfkR
esC2t5C8FQ+eGtEHeU6Q2hKvKY6PLTy0PyrlLbQjpP7L5DWfKwf4vE2NfU69C47sFd2P013asPjw
I6tmS23fQLKtuVwWPRd8FRuwKfShpwiVhQPkwzNsW+HRaDcbSFXt4DCfTSmBVqXmJQmvGPMVG1ZI
NN0YERYr33IIERM7RyVgDAbKgt5sTRpg5oer30AXALdMr28qUZWspdp8dzcBdYwKBUMa2d7oyA7m
BKXXw1pM279CO+hMxA2/wX349IGaVER2vhTrL5uaXDFLLmOzwdbzorb6HAk/i3BcFt8zlA3sj8Y9
1NKES7qd8n22C/ol8feWXo7eyMy9AoI41Aq8h+fQSgKYWcvcE+YQfwfxH//g4CiV8rmKy3kGaqr7
u9JEFygYA77vyrsnTgTWg0RF4/bXLKNdBg6cbTWZVaLMn+klCA0DlnmXAB1Bls3jMfBPF514P4gX
d4QN82f8HSCElploJjQ6ou9ZiQfA45GkmBndoH0t6jLAvlr83xN593rk1hYbbIACOimvkIRoLzSd
LODBxN3QpXr0iCQaduDCiHRF0MHHhNxg80RemRfEkKfs+x5YhH3YAgJkGKFPAX1X9MVgPEDnAATc
NIzwJKkdTUC54PqKKHmNBq07Mm0kNXCWl5DwHCaNb5Z+hiVgtlZ/JMGfpE/e7Jy46AhsSGGG+/nd
8zatPajUl1PVORzQelhyck7vliMTL3vn6HfQ6UJAxJSrB8AiO6bAFN6DGEnEYkJok+8YL+d8N9lE
2vvpqRfmmJP1yKTqY1Gtx4O3E7NA9fI2a4LeHvKOqd65Bhj+GeGDnBP9ukNvdc69oHTirTWDvovX
YbhbytT7ewGd8HH2FJ8sW3J0Bnr/9bsrwLnGj3WWz7bgr/7GWlxO7cBB+/sq/1O6vFh8mozIG7LF
RNMCueQDwzD4V3U9ixTMg0/87+HN/N1tn8EgYClMmiFH5EYU8OKiwf6xrpAcVEuVIZLYAkBTNZnF
v40zcTQLDflqtWYrgn+9zkukpN3ljV5Ob/lNt9kN3v6CkP/2T51uRK0/3wS4U+FdqugN3sokLsBp
W2Sam36Z/5cRMXqylxVu7aTQJkWZcTomP87ah75OARRicg5wRIkBIIc2SNHsTvGr0OvAlDfwwOHW
xRnipoCykH4/xfafyugJTLskmdt3SyhoCyuuRwsQvZoQ7C6kmYsI+vQLFF+dX9lCGFKl2Ff7j/Fo
HBpJZvZETrLq8qLgkEiHEyyaAy5rdSEfIHn7slhfNB3exOJ4kLeoasAFCizvk8unfA1dRmgl9LJS
/yaN48kTYaijJdlJDDG6ekynVyQv9Cxdgdaj1UbYWMLHmZrU6eyyvVxr2/LcyWD75pQrYpuEvvJv
7a2hosbSuVqYd6Sq9lwyqRCUFdGbXbBArNdiWCik4W7RTCvNUmzVgGuJzd3nkEtd4vP60Iy/hn40
76Gq9ljY/PjJiCGUxyehzqVzlu0o+Pl6OPQdz7OzOj2s0MasbT3wWTG0VotNuDLi/n5CDHwEIzFQ
mVHRvsqMkMh64/M7SbvJqJ2Ia7yT9mHtxdXXIbDtWDUQH9raUvnzRLYBXF75YKGJ9JJYyoQUi86N
9Lj6UAv09fuMVRUd5FjJhoRfotKlrWjM242VIx4pbjRugJe9JLfICPgHHFo65wpPgPrQGP45NhiZ
/e1tinDcof4S4by6XkHKijzicCBueT5MljpwBvAhhvWPjc2OuwIc+mnIXaVQo3oS1xhz9eIztIvv
yiRp1sBRoqt8aN2IaTQxgg9HBKHDlv9nXgz08tO1IREysj+6W1WyLEoU0HtDJ2XLeqDVpLexjlhU
pG3Z9fGJeG41np3y6/jKX/II8WDMlB/59UjesgJ5O+5mxGb2owHmsBCu0eB/1d0oq5QK27XlY+6Y
uzMnuRNMDRbLyUVsu0ipnFbnmCCo5tuowZI4oxZrDGOOqa4aibxPEuaVFZcObosr6bzGfDr+PEcC
Sa+wPdXdd2+Tk8Ok2ELQB/AOvIkGTQzEXs6tgF5T/j+8UoCG85Rw2jZiWp8mEZC/SXm5eTkWTx5L
vJ0MT9mdPwLgirNLbIh8RUzGT/6OQFmN6/Y1CqGvyZukj7Pihw4F/PZnwAesw9wLNJD3faG8GHx3
NeL+DE0SOBLOTsqSq/7ilQ86zeQhJa9rwzYeGn+IfAs4GzAeC52oUdgbkJUOT9bcW/7OlADHuNiU
kxg9kgMwMvNjIUjTZedkxnzbRQfAt/PgpyeJAsC1p0C5eIAgYD/Zcs0YlKwcY2n0ZFaertziofTh
L60ERAJg3bNX+g+CZuqLaPlzNCJesQiZL0QDBrxjwC2xE6SHefq4MjlommTfLUpeOQrQ7MukUpKx
/t4LvnDhxVH3bZcl98LQrPwvyBsiHUd1EMtVIfwbul4vWqPJVqdVEsaxnL+uloDvo9vV5KZh30eG
KDQ8kep1l26Xj23NASFBxLEDbpyPoNBPdXtJhn1/1T2y+nIFAIjExkLuIzSaS8FoZa+JTk/G+Qt0
TLN94rVBDI6yiPbPK8ESijv16A8+k1jrNhcLGxflWYxmEm3CU929jrVJDj5kCMi0T1ctalzoWctP
2+wzDwTQTGn/P6Zuymn5l56J3W2ouE5gyBujJcMAe7Ot9+gRayz3nGRtqFo9lLFMNANiEOs9y4Ai
aFumtT/VH2EJBvucfi1U0wKKduXqiqbhYUKwICMTn1ywjCZ93NnXqc3a/xAIy4XpXVq/tSxYQy9L
pRRwAfs4F8T/TNJ584XRmjKZDazvspPJCIeGYxU3IOwZZ7MZ5MxDSucU6PKRFzqpvl33XzLBqbq8
1LkN9ld1zoYQQ0f5J3iIV3TK92QgyQm8uzKFRO4fRF3okK3a8y/3RQ9fQ883BWw9/ZW2dkPL3AbG
zoahZQLaJNnqIqQgDcCJRQXQpjNrhLvpFxCp7qB3cAi7kjcATZzgg85xaPGG5Swdwv9c4w27bVsf
5JDWORov2J1/aS/JByLtAqJtpG3fvaJUkGpH1lD4oht0ON2GanJ4+N+6wL4PiZ+3rgIlrYr5P97u
URq9zAEhyV8Idlj+l56eRx5f8fZqtFnQv1iukze2yX1Bl/FjHvobFMnbeng87Fyc0rkIUSnh+QMw
I6MNpyRFA3YUcBkUC2DZG8PYhvukVxTnfTXE1qWKBzqqzVaMEdx59aPEeQgaTu8mUYPRQARw7p5A
k+mca+EGjRnKYXCf+tyKdo9LeLcG8d5dr37xRpQ3jhayliRGoyO078RWRhyhepamfosAZSFmShmj
Y1nGfStK6Kk4H+Y7kvMWSHzK75oNQirHu52S7uXZhr7ByDnnd7ed3G6RASV/ZhROwYwOvFM7y+P/
Wc08ogWz1NCy0b3Z3suOy0JEfza8uOcFEmahOJckuvMnIKIJyRdMPuivNO9y7a3fSJGvGVTczOnH
u+fYhe7/3g866xVz9iztbPxscYy2FuhsQGvdu1SLSm9e/DNr7fNaJnEA5/1HFyTQQJBsEvAaBfiC
v7WQ9NHbrqcs0QbvYkD87oleEmjiSYcB64K/KhAs2QgE686B/h/OVVeo4O4wW1XCoZ9NVW/AxfHj
1gCESPYZxtq7jarqn4V8oi7nAonqHXnwNaHYrX58hpqD+x6Q+zTHroPwfThzm12yJS0VqKa/5dL4
d4y6l7+H7RkxMJDShZXE52LRcTKckZdhOtJNI2npPZvYk2I4uHgJ6RWQKIXpnfJr7Ynxp93c0YGH
skyi+x/fuKMnukQ0EdH79Y32cuSkV36t2mPV2gcKGD7o/DbfvO5iFtrK9aSiCJbmg6Kd8pDE1a7L
6dnWW0uhsi2w/f0RFDWAvS/o2J2M9/1QjLY9sCLo5lxI4Q3uSM4yDIm74B/o3qAjjdZfssNS0RPo
JbwTlpzNPUDiaHGTkHjDJpffakneBVEvYq6eCvgMwBgstUP+laMuFpTFXp1xjlEJEeGMqcXsIuS/
S1K6c65ldY3f4GdxoxtlhcyB9OPsn/7FcB7NJCGulIaBvRXiqeDmCLqV8p1dNVzu2HN7g0cCaeRP
x0pyepomIRGuFEqfEEPLlRjkLDIEi62CzPixOkJpiorzvFievcv45Y4zZoedaFBwbGlgb1GncriC
eg1OrFJhY1pqfTSU/rZRSS52z05KzlvXHx2HOU3nzsFeeLR2tSPkz+qyf4mpY4zQKEqAmb3y0ynP
XdsOI6RAao+nYNImC6kJMXScGFx8WpXeOzuufOo2vGUUq0aUXRIXpgljs+hL6IOTDeZFV3TUPui6
GXlwBV/3oAMPwgRghUt5u7iDnUsMOJ/JbJvLJrRVbTrjwOdlO3I1xzKaDGGc60n+G1+p+A43plKG
cCDySOOsEOlBsS0R1yTAsAvNMhkGOSXEhp06KTh0CDOYRVbUiLWo75QJOLIInX6eNssli9YoB5zF
ixkJ1ayYDkMZ66qHZG98ShdTJpVXUMITWTgvqzJgGN8HvVlPkfBskSSABO2+Sr6AHOa5tHZ/6wyq
dAiMS76WKn7TlYNAsKCf7vImJYjNzvyCOuPIvJ+1mqbBd8TA0TY/QK9UUV2IPMR3D4wpAKEcql1J
4+3+zI4aHaBewOPS7k19RhPPMRlMrGVdWh3J+qMp9OozN0+2jr1tMjMKM7OvK5jrDnOVpBeKM8qA
D2R+Dnz+VEG3wHOoYIRme5aqKSv+UL7qwZSkFkVcZ7dWo1YHwC2QDJyHLNbuK2O+2qhFk5lAAoSk
zIGO+/WYTgpbjDIdwwd+ZrKRnfmZ7u2MYBo5/psmXXaIh8rxAlg98v+IloeovtlY5UX22vO8rzvT
VRVDzXsQtQSoAjAed3ZHZWpoibCa/6o4kb/5dexjDG2Kq4peUmC/4JYZXBxxVny2+HcpeI3Nc4ZJ
w2NUK6g+EbVfHGsb/traBSxS/z+xgI3YLBxfms2eyCMGdrTbzfWRiefmMwdZeJ8Wm7kTSfASbseg
33lRzZptLDBMWFqvTDhuB043kl9oXTDQEmC3GAnOCl5iO3Vv0L8vBs7B6rJf9E1IxCadZlav5T5s
1aCuPLx3JqJ4xsyyP4i8vSBUV2mXTXJLG9lge6+7Nm/6Z3kgGfDygNRnCKjb9xorBmdCeIZ/TcCk
GDVedTEMXOfMNsEFcP6fOZCoA9ielwTRRgSai7fIwF5/u5M/1sfDwfJVa4fsaBEka7c7G51NzU+X
SptqCNtYX3m21USx9uxfIybFhRqtAxKtJDxzJTf3t+nxJjqtW4wSbewkD3J6FPtwgQcV716JIhCW
fIq3Xdc7+VnYFuzLP7rKFSjEZHYfXmQrQ7Vf6zX5pPlWqzR0X9IF8vRhnlPfNPHd0pSc8bue/7bC
zexDpxWANT1wfckXPzTmdLcMgopnChrLf2KdCvZ39o8+d2NuIfnNPbfJM2VlLV2KlYidN17z8f2B
sPI+MrEb/j786Smh0y8OLxfJddVAGRXMBzKm16O626zFaI+7ZUdvFsiDU6h0ANoOzUCnG8W1QZC3
73phwTRSDZiOvem5CD7tZXi3JdYaClFHKukP8qiDgGeFREye6kLzj7oImd4Qju98NvFLuWVLcuZ6
nntYxT0vgDhbCPeiXFWsiI3qnGcP0iG4Lg0serzJe1oitox86tOEwvb9QXuOMmoCy+wm0HjBoWqs
bJV8wJzjdNBZuEt8D+69cd4vojKPT56qlurgsFRZI1ckoo0I/3D/BcOhm/XISIJ1vXXqrg0VlvfM
+yTQe/0BdHgdcxoll9A0MRYq2WIpftdqzMHYL8n2ZnZqEB6Ud7544i3uxt7spKw8A2DK1mmCy7Kt
t1rJmxtUUZFm8kHi4kWCzRukc+C0j1wPMpGCr2KQOvylLRIZLts6mzC86hA1cfAMaaW+cSWvGpW4
prCzTC3ZUl3fQqZEKau0n41BxHC1Wx185LP9ehU1Ws/3YbArb9TLkQz7AcTfn3NI8o+nW/AoVhvV
LewqPYjaxWVkHCyz3Hm1oXFZ0hT4IqmXjbF7KN5kslnGgS7GdL5gi7BakM6jfIBvHtfa+pUYOZ0b
VvgA2fi5bps2PpU3GzlLvzOgZf9jaTu1YIzs534ckUfM9CNnnnH1IVWey16dceWI8eyZaWPILc46
k+YL9oqWNftSUlsv5bjevIsDv7hiwmHYpdbkCh2koCnmV7SHku/CMjlFTesyqWb/s//Ev//1bhde
iu0YGYlQHokYAK5XWQ4Bet/PfybT1AORzwpnAuPLldKV3r46KbXW3d/6Z4P9rkTl19jupkP1XXkN
qkh9VJFjY6LQYfAzHxtEQ4X9SZW5iyYb4lbWq9c1zTxthhxu433NTrlgNLaUj50Jg3P39PDhVGwH
IwK1YtQmAxM5gGbKEzoHjaJqpjU2lbyuNC+8IqEYOxt0xlB5TU9Mqbv0R125uYTL4H8q8YP2aZmB
xUkWkYjWHEsPHQRYSEnVGFzZBe+3dOPPV1bY2WKcGVNKq3IdvXPs2MNExicnSPFXLh3R3gOmXCSn
WEdOtOS6wnOyaReFVz3h6/BBl2R5lS8ewpRZc52sSfPkd9c8lox1MPptVidTcOb8vs9ET5KSraGh
OI+ZXJ55YNL166a9jh5NrFa0wzNU4Bh8LcXFDnFJzBTn1DK29u9+swiYY3yaCymJtyLsh0jWw5eS
Y3QxBNzyoW7HOJcwEuUdHBzGm2oTmh0pObI25f6ZXc7utV/5D9vJhhnEuOHt+UfNY2oB84nujtJ6
GcNiryWhh/jJEojwQruyXoOYjb3SF2cFfyfog0G4xnUdPxqYS+xLUZRxu4/KdGPrUjCM8gY36qRG
dBN1neky7nHfW03m2059VY26A05KfMjeMlGNXoZG7anXYoOX8G6FKmmfscp76N7l8sawslLZ80X3
j6sL6l1x2v2M0k3CbLsdWRpoW26GuA97ol7dw5om+12xNzXzybQLeyHDJd4OERLO8PQLmQHV1INf
DlJRSAL3gxloJvLxCpRNY8zx57rCGtbvxASoBZfkBS1MGBcNXqbfoTKyJYEgZOatLmJ/z/wLW73k
nYgF3qRrv48gJg4EpDmbGd4ubn2zFScREJEfr+Qrxc6KXP8rzAFKcMPSjzgtmr/zS0o8bEarwx5J
G0L64MODcN6tCUKxrtKOdVZvxaG67OtSzx537XhHXLHlEdd4W+DKwxkvE1Sv5ftuf/r0cIG36BkR
AqEiaTRrSsSXh10JRJ+vDRukFR52iwYSe7oM93ue2X/ZiCwGKGtJjghh1cOfV0puIS/IFh9R6fos
eaGIACX4iwcuZoVrOH5vp6jEHjA5QJU+09PNvY6LgcSF6prS+6KPndGXznte9fUVdyZPnRQ0eIKz
nnvDhBNNCC8f8rkpyUPBF9QnOQw8j4Oz3PT1APUME+MrY6dk7EEYUKEEwzFNATtRWfveG/a1/NNt
VHQ8UBwgZFJhehl4UlXB5xw883SvvITne17rHzg2rrbKkFDfRkWnZs7n8pm5mPTaC3IyxL5Q4sNW
o22V8mNMMkCKdbjo9HYbZX8kKDtyiVEKofBpG8m4UWhr3vnk2rBjajEb5MqYzVKmVmiIDyAKuSJg
uaFwq2zFXAawr7rBnnNa7KfmyDUsaTnvmId0G6ntTWBBMWWqT+Y+m/SjD00OyuTdIsE8RzkxVz1y
XnQuf5ymq2PGJOBfMhT7rKuQgYJrdH3MzjkmH8C/K/KebgcLq4q0FM4p3kPL0BNetrr7jm4l0f2K
e34WnwkcL8gcKd+GwNFTTjkZc2WCYj9Xb0G6G6GOk6OGZ8HwERPp4QOGo3jqR/+u0TSHOelPrkmc
RaMP91qNvZh2MS9LLA7YSFFnESem7Pa/D2IM5tAoP8Ogh6pl0U02dThsh9UWM/8sdSqD9aV9QMvU
BSKlKIZ1EP3I4Pf77XeNcPPywWkJA45Bigr0Dn/Y7S0HQAfwpHNfdzG5jIfHzQ9sWhems4TWD58i
cXnEl4xDjWhMGHC/ICuar3eXx/pv61d3gDYeneFXg8DOnDUqtinNs0F7fMXFyoEMNil3X3Pwf9W4
rhRU0UImyTnVfpuCcIEmgxkS/7+rReSCCk6jTfofMowdQp0qFE8iOrxe6+kevMQB6YHdnnIc82ys
A4B7KLLBlboqfHiv6GIxq5u3Yuzw6AJOTQnpdaejwVgxPLoR114eFquSzReDsFAohOg0fc6Ahyvs
7Lsxofld1G0nFgH87E6v9dfaZkyQsKmLRQATSjzGqKSp4ubELjR1PUVtrniLnmPrxhwvMVEsYR4Y
65VAXHw513S+1cVH+IPdYKinCTxr63NSVGMBYjLin38791FM35kOQRU6gEQicD9hp1vJaH5m/Q1B
zQd+kLuGk+f+9IFFfuzj4W+5/aOdoFhkiKXc2Iw/WYEt4MAxz2Nr0HJf2L5ekh0PpLfot5gyDII9
VyEPJ437LT7qQIHR7XgAVoKmrGesV7zHXqJwog1W+Dv5MzNV/hZEMeQEk7wstCm2+B8Sj5Khri8X
5TsFKH0ApJM32dJ33Q/LEaDTXR2JECxmIinNepWN1XFKgru3NGqaSspoCyv4cOFY5ROL/itnwj0a
z93S2RSyEmINxcolETgoZ7IHkVUYqtnkrWHrcx3fE/2//YBVeht2cFSCB73uhCO+eYgwOygZdkgl
6d8+xCYqCRKIgNy6lGdjskICy9ES5HgBizEFE4pvxEW4JsTF42BjMA7RHYXBWbE6vAR4Un57nI7t
7TG5/+yNyps8brqnSxF8wyU/jnwpPjrF/gRZOqdr+mCytz8O68bCJYU+06P1vO1IobcvsWuY+HQg
/bQ4omAZ1q7wJkIflKpBnPVLHTCxkcbJIdLT+CG8wTh9ZVYLiUFTNKfnbUdRwlMzDiLvYzEM5E+S
JuiTHvRUQcz0gQi/i/IFnQnmJ6fTapsX0+W5fdeoKePGmJfa55t9eiGh3c7rvLfyzSL9ojtnImfg
QjKNSuGdrzUtrOlQd1llrisBNe+2s5bZXlRL2562CntUvQIz73SoNauBtlfA0kY2b+b0z3+aY7xJ
Lcet4IGN/N0jt36wBv2BHCbX8IDqfsE22o7uyo8d0RyZbNJWizx9P5WZ+z7EjbFJelj7E2WI42Yo
gLstLtjVKTnpBOd9/cB91sLJb5t+XDrspRRXmUCE9pDCACcRevP/sNMzAtWPOwHXNp284P6VaIJX
Ga+4TuAULfCP5N8rT80gI7H78In1sOhe58WXKgaVy/WNmJRycIyQDjMTmuB6RZEsecKrCwDRVfuX
1Yx7dB1qQVn6+vMy58dTH3czuI6mxswxg8aiy1Uu2hAyXiO3IO4s0eELL/cdQZ7FX1ctoZjBMqSb
JJXiOhXC+/j3/YHWvrfKLMi7ATdlwvh0HI+1rz04ZePSngrH4qCrHaEWLp1wy96WwKwn/u6XNxXK
HIyc5JiUili1ZszP2b+EK3nqLYtKce2qvPVAWpurS2q9vhjYB9wzqAcgZdWl5QwVRQmlXL7kb+O6
Q+9rqFr1WANjILfol0jdi4FnqGlB1E8XxmzlUH8qixirlpaJdcUoD1njSxcCfsu+xJbOtZrsNpzB
h/1VuXGRZ6IdASuM1TC9WdnOGtWrE+/reYOnhXbEg+MmL5AUA5Fr9TF/ReOci5qgMd6Qxo6rPT3x
ogCC1w0j7GY0DzqksIw2yW8CKNkRoJ0oxsAyVVALVVsU+Se2tAjgLYqwGOmxz3nEYlnU2HUtSNzu
Ewo+dhj3tRB16Qa/lD1EHgXM8q4cDr0cqxP8MCGNcxQn6MpbBSpYe65K2RAG/nL1Ry6Pmjx4C+f5
Cq1Mt3Dhfm7TIQ7kJo0etsq4eKk/IUaXJkQ1BDCA3Xpfi3eXNGiq7lTePs5v/LlHznFIAoPTHM2C
1BMHoHU7Ja50I1bfK08lBowmJix47TyzYfcbgXZmwGJ/5ewrD2dzSabCTE3Kmp1ItFPaS3dP4EHQ
NZWVtKJA2jdLmiRvjHNClTIQ8NmPUCFfaN+VbaK+7thcqLsNsqID/AzxUFK5+jX+NMnCado/0CCz
dxYIPpUpGAHz5YVuq9IKkLsfdXClRb1s4ytIWhjRstqNHVk3++l29Rb+gFgI5KwrerCMM9t6/BUn
U3AXVX9581RcIgf+SuAffMD0paUWn6dqzGTX5fdUhGgHyMcs/OwUPjNWTQTT9DEkLL+RQ+XJ2ynf
FZbrB8EX482yTkWzP2YeraLc54OufJfI6MrLejvybXAlRCwvJFR32xeVvzms6xunaAJb/w7G8dcw
oUDO2rZdcnTnR6O15S1F4urN2g/rnbrVaXkGc0ko4plwYKYRfjMwpCJ4yPjwle1qNt7KXwxwL0A9
SzLIF2tJ7+TgO9O2+OzwsuLZ9krtOih/axBWU5SJm2IY04kJQ8mLlpgwj3swz5/09qyj/RzLt8br
Nu15yomdwwpNGYSt1g32OYGwFWlqyprz4PmdxyF6cQAjo1KN7itC1i0PuVnWcUx0j4KYqL6J4Cwe
gRz7Dlf06bk1DgfeMI4IeugDjfI8R8dZme+ywfVqsatUWc9P3X8K56c3b3IEEZjhjJd/mUzHkNFw
vMGNdx4CqrjUB71TvhdFc7F00B1RvDf7ZmhYstoJXN9QHNSK92OKminD1sHh07oNdYNGOuVh35c0
jTPy6Se5Gy+ojEZxU1XzRnXExmtTvtze7xKCeggahPJLfXTzOIVhw3lKvHxC+oaLBeKPk/YsZBfM
B0v3iMNTHECxTJjBXW/4aqzz3tcVfcUJ49sFq3VPXp8C0sg1x2GuRQ5RB/pPFrvByuI7PY7UlKcA
F0wYZUJHg2jnrJuvJAKfBNvSwct21NwPmvj4uRZEw1wiGBDfksVaHWkPhx/sOHCLkQXlTxLTaXfw
3rOeafk8g78mU5RLyb5a/D8I1Dx87dNO5iwC2e9IwmI1w4CljcUpVFKdR5dC57pqWJFiJ+dFI9Nu
GyqSYhNa/fRfkQJ9kRu9OxXyKGIBa4bXAI/ufnsSxnEn9vG98RP0WizMESztOHnEagQlcuhmNkcG
PRgp7sAyfb+ehaawA7ygDIwwdv5Rfd7j7sqC9dQi7ZZR6zQAVvS8LWa0wA/udWW2n6ytH4Pk2EsB
UdB2mOsVyw+K0JoyyBZOqPEyXzTroNBWNen+HlA3wE6e+/8qM123EwygEGkHoVbHIIzQKDPWubfI
u4AauGaFvq619LBu9Sg7XbSytJaNCiqG02sZkKFN3w/UWqmkRdwry+rBAeMjVzfqBDXvawFPvCbt
fUY9O3QKfJJyQfZi4QckR7/mRkwLI5HNV2Yz573Dnmv/51F6wFlJ1n1E0zsIe45a9nOA3AKQ8Rwo
gQvTI83r2Ua3aavwmNZ0hUMvoVfkAW85C+tQIRpZJbHFrPIyStwXo8pfUdjuoI26CJ1UYebH1dVk
la1iyYMRD0VOv93iiUwDapvXI+VuKTVMkjM6x+n0jh45OE5A0u6W/JzhfIPVPuRXrKeuW2LtvAuP
URsPA7QNbv0TIpB09jNVdUZMK0CRWb9Ft9xgYXVfnLPCt2D9RK0r1JToK0CF2qVbphu7eta+ctmy
IH6gHVxspmDUwiQEA2u0DiIXr6D2Sn3geNdMuvKngqR0bdFdzNYMkFYYeOWu/FBDnyKndGrdQGWf
+KgAIhh4m7R+G0sl4LogarVx8SKnu6cZtv1KjrVhMSalbMZ3BILxY1PjaMCw+NTEwcS8GYf1dAlU
NipzbjaMvWGmahQwhUq907Mz6GJfA4iBy22xIpVQDuXWPem1mcmvO+kzPmlUnw/zXLmQnbcO/9FI
7gTEBp/4a34J7e6lVX6f0I52/Ly1Tgi6J1fdzppiMy8PXmWjpIB/g+25Xvf3A3foDHnTcbMUSkwP
+2ZUNpt+HsxFLNQeyyXofVEAAG7Jz1ECpzQPAjdXNxdDnfcjpLIaMc64dONHs/R2qXcU4Ufg6GhD
VBbN+jib5y2bmNoAC5wbTglvaiyO1kTvtOAGBtoGBzPElZwHPonFztzU72SAOVR4xxND9CmrkChG
k7BSkaDBAS4C7KTtGSEniUQEzYkeVTcvjkydzplT3ID8h2YrnhCXrzbjNikQ8haAMv5m+FZS2nGN
YJt5WpelgFXW06+Eh1QouFF7VWsH6GwNsQI4xuwebzekRB7ONGDZyVu4ase9Uo5fsQo70ZanlJ79
X2hJb1sSiQ89qtkutEdIECtEwVq/inM5FSWp36zv8DY19ZvB6bChgd/bLdsLyedGxqkfOXIrGg+g
7ol+a9Ebv93ccNCwJpFqwCvymIJerY38xSg4Z2jIhFLQQPaLD7TqpbqQgF4aLUpORRtGwweYxm52
b4026ALZHThWGUmcyQg6P3ypr9oFpzDDwlBrRT+EfBNMPOEGJVRq+ss3lOhiFfqkpWWqzfdSP+Q3
0qjk14vxIw4pihkAbPMZ3UlFyHT/wya7f3k/pXinfY1KxvX4Hgn0JnXsguhB9iOL+q1t7cTIoz0P
qjtTt0UheXuuJyJF+zgmDU6aaizz6+E4qxr5Z6uijCPfZNWndXooxMJSrOjwSgVGTSK9dutT0rxf
JMQFMytA+rUZlWPeMmX0yXsGXxd24z0bXs4o5Bf7HHc/sbdPjgNL/1IAMbG/xo0KLsJy+JCDCcGj
RG1pQ/7YfNzB+pUfULUsYye2M7T1zUROIywTXtIxc/lM7pUHae1RHlFh/pembnnNmmzvvTs5phyc
2jONlJlXAHizDSnIxMD9+WLoohY9tCS6V3w4o9sm5B6rymJc6syg0KpT6JzSjUwYW+KsVCY5xZ4N
npiTfzeaKFvGbq4DLPT3VdfitLOZ9EryBFL9f1gjClpsvxVN8NSfATrEYop5q0RZ7Ir634gOcL+N
xJilCnMBaQaWl8GQXA+AKX+/CzcRnl2k8A3oo9IcoVcJcwYUMBxNF8Bq4V6vflajSfR2i6I6YYOY
1voEalyVYlfDOf5QRF9iBZxbahagDwWl5lR2wMbtgD2EhSv/uiD2jjCiVIpn6isVSgTQ15FHM7zw
y/s066DDFO1oE/CjkRlXpOs7Xs7h0aYS8XrhDZCNUiq8MM3+ghW3QbVxf1vwLZai05iPvNCpWA8x
ile0ptTAiT9bcU/s5qMPIV2HGWE8ugmOWkxX/EPe76BDyBn4fnYPBj3yldt4esHgWLiJAyEaY+5u
jSFSio3nB3j0LmO0DimwOvwFl3fvpVYzIvQMk2VQg/4lbgja0F1gPLor2svgGu76NSbKa7ycjybl
RF3Xj+hM8qSfp+MCbMQ/LHLWqpLouZvw8A+wh5/OUUWS0KLmb6A02PPoUQspgcSYjWJy3Vj0Iw8M
v7LEWWP+/1ujMXnQBkyFnL5b/KC4923jK9TPG1Om4C+mKTY0ajVVnk5lNhJxi75xF5CXmD+NdYYr
UPBBiIOW65QAkBESBFaOrMsxeVTNkpVmcOt0a2Xp5lOOpHh/5zGN/VDyJ88buyHSEgRS2VtWOc/x
HzvvGZTBl8AJ03QQc7uPsui6Kz8p+zCJLZRzK+Unzx/J6GZp2f80g1TVbgg0Pf8sGE37f+CfIBOW
SowgMkVbyykqxPkpVHmD+kK7VXlE98yg2U91FQArhzRMt+mPR3GvvwP81jKHC+6fO9CxRWiSvnVX
fcZteLh2GU8DZO/jP/edYp3woF5Yv9Sz+seXWqmJyJU/csd4g4k5/JPJq0t5POlEdKhPS9cLJcSi
NTfOOW2sf3QXAT1AYp4KIb/p4VhAjgAFABBLrb0NZc4rEY3Fj5xIfnyBbqiQv7M7jYvifcmgnnDD
X73veKfjtDc/Plyh4Vl0Pq2qXCzD6yLtpMRPS5Nso2PBX0zx54+scpvhLSSczmGL6XBxtvQO5QMW
LoEuxKUNYTNC9r+RaIEYc5AQpNKHYhXFS+ktuJLs4UfYZJhdW8R/W+E39/qaNKaBBhhgXeJEviJa
fnu6DgQNaK6ahpUftQqeqCtJrAnH9lzFOEBYakgo9fUlz+c8JmSUcVZy461zIWRNOxu5FwFmJ5EP
Tkq8DX7w7oVoLmnR1IRCr4/OTbGtKNN9qMGikj1M2mjPlQGhwW6IUGetk9XClNei6+rPM84xV2T7
gEhNw155VVsyyevKYwZzUM2ZCBHyAB4G+4ZYS2/PlDfkBIgCTQmFI7m281BelZfjjz9msoB93Nf9
OXX9E0qkm+UBO0iTRsO/cffPJWSO74P1xNa0zb8tkR683LfnEunLumDvrO2hd/ulTTbiu8fsoOjv
qoj4BUxLUV/i5qiCtCBD09HKLvqfGp5NS9R7YHk1fH1fWS0WiiU1534MCU7FOQpEVhSgteDnqvwL
b0acpqG1cDQQqJKOrMNypEJmaAQ3VzS7DgI291FVhU6YQKU8cilHgSLLQXi6JuT60UiU9dmtHBOF
QP5LaxdNpATB4O8ZMqA0PJ7lwQ1w+h4jOJmk8W/w3KG3XV3ljKbHsoNW1kmVoo5Tr8n9HZJTHs3y
OV2LvFP3xeo7d2ViaCa0lNnL3pv03FRyC09doW0tw9GU0S5ggu3A0WExFBxjq9gBuP/EX+9IE9yg
ugIk0eIey3jYdrJ79EzVQjmOlw3nnERuJ3c9cfC74KqqrkfIuvx//bgFgmgBJXAHDUPRgOJ8/rka
ABrKJ6aXIkVzNOTn+/VR5E7MXsNlTI1Ehhn0YpKieYt/qQc2pww9/qZrdRkj1YvmqL8rpy+tEkpU
IZ02KNl5ZUVHNNwQuX9isT8E5Tn0d/AjtJckrvAxJfMDj0H63ZyC6s0tFgGZBru+fvTRItJaEeuM
LggS7FWj7K2MHzRyH5Vwaf+mK8zEb0cgDVxCECn0hoN4VjF5BvehH7RpaHRsH+XkkjsH4QtQN3XO
7+/mvRe/j84HAlQckDDJ6WyBj77z+5CkPJrrw6aQy/EkSmN22mA2NTddYT5l/aTzqMvpzHT8jvfl
ygrkd8fmt8sALi0a0oUcFr5Nwu2SN1IE8EDyuX56WsavplsscKUf6UoW0AeYJTmTaiqDLJJNv9sL
KoKRIJooAGlBd0aibALXOVro+dCUBkidmQe3UAbH6xvsLZYQQfXTXUyNbspcVfWv/ll41C7Lj3mZ
gjHo1fqkLsa7JJBpGWLAZqwjf9NAEP+HTIA2FJRUhK0k9MWYWQWWo5Bbx+kkfbRUi0ixM/g5Yq7a
wtuGaOjMipDMxZ+Al8g/ObqhBaGOKtUXHosPJQnzKA8N9JzNZOBue/2YW9MC4D9GCzIN+rCk0ZL6
PxgIclv22Sbgj4XTbqN2p1dLUAMZ/LJJTuboVEn16uoGoNDHm8DjyTxArinJpGBW2QnCxLWQzQI+
2E5Q+HF5mYUF9C+k2JTusdzmyL7oas/r2gV0yq9rsghBGPZ/pNUDRiRJ27q/gCL6uwPmaf5OjRrt
c0zfd7CL8nYyIOlNccsR+WrBEkhbmOfKwkSZIXWWwfygotN+L0lpUHNZ9g66S/g/pLVARmjT5hKL
aXSXXoUx7lrf8ofsgxOr9lruVj/c7dlTBXhZCsG9pMy4EO/t2E5+9debahSOp9UnniGOhkBpUMAC
uIG1BfmfgK1zFO0djyX9tApMJk0jgGj4eVbFDpVO5ZBp2fWYfaBY/yVfXV/DCxQDRWSoMr+mf0Yk
NtAz2RhCYbn8z47tHwfFaitLKw8Cf9Ufx1gNykGKRhczezruzOTlvWqDtA0gjvV4nvDpCGkEkryw
DulWvN+oPCvvso5NCQcSWF+gcbzmPMc+EatdyO4Rmftov6jTSHpe5bn7MjNIldT3+6f2poH9lllN
ReRH5Yv6W8m1sNrA5wUqMnJi4zeckMwWdUi/lxcZE/cX4zgsnuSo+SvWfg2PYpno9bgrYQJRONtC
LmjR5CrHKWIyEkCA91/5v9KL4YQDThslFfWK5xj+xlV1s3+Ul7zPOFbesGMboLoL8ocV1mEv7Vih
vKMbF0VlYDmiy8P69695tN5k0A9oiZMFje9jWxMtMdA2mlASmeyhaWy3S7GMBk3Q/7p3ST8F1KCJ
jNHU3scrUTiCqJTcH1nJ1eJCiZnQ6UkgBNMwDiPSdxnCo/tfGSGPRMOlLh6BQb5cYB8yP7ZietgZ
uxpSV564wVymW6U2KAYDy5ULlmrKBAquyyG5Gkib/uyN9Kt2XvTBU2/zM5LJ8W+zDalWbnsAR1fa
+NK42lzY8MrQYIautO7ca/qkiQ7oce3vgpgRLGZNkHw6j9GUCIYoJxZGKkI1yp+40h955/lVzrue
U99YY0xwqgD9fFg6aDUJBfD4Y9Q33I9gNRUJYXSmGdj4RJoMlJkCTFozR5Cjm82aitivBvHbJ1VF
Fs3vjN9/ReDPtMpx8obykOKS2O30O2jmoX87679UfJ1+klrwbxiET4STuUwxvS++N0yJL+Pj5LEz
mx1T74xPxzkCVEEc/ATHLzYopQVJ1G5bRQfWkg14uk03ZhLPn8s2ZUMRuaO2jT1gID0yEMRtNnPy
4Rn1aPL90c7F8lVguQygUWQP9Ad5MYU/S36BuTZqIR+L9LMqAmLoeCrSB2T7I4psrxsVJQGBP2tM
PxeOt/LB286SsWHNNzAXD6ayB23umlc6H349r0Vo21RxlOE1kPP13AGNDfTg+t+GnYBMUUnOdW62
6SgPl0gdJ3Sk23dMOYJqtCMRHsw/PD1koeqllFktbjC4P027SDKldHupDEBr4/R20cnjkO4GF1Hg
3QScptmD21BY3BxqrERoJPjFajYCt1lOE5vfBFNIy1QoIX6C/leqVJUtNe5DMIlxXSW3/2v1VIW/
XtU3e1ayw2f4/WeCFAN48OfwZ87r9TefVEeuMbT+CmV6obET6jispruw5E9ZGx5Cp7JbGIWrwAVR
RAbvXVI3wQ9SVMchcdmyUCJJeNV4lXER7DK9N4mcD8F51lGYfe8+paTabwK1i1V4/GrVEFkyjcAC
F42MXs2LCj8Lu8gD+2+SYsAmdQ0bnEU+tRK+YWHOw07vPQh1AEIEAFkXQrbl9IdWgDWBcX0+YhIY
IGWrH/XdNDFGJ2VWGRJ/RpP2tzSAIM7bVQVoURPDRlqhyunRkQrdaOH/l+Jm3mnCzXb5dm39Y+gG
+Ca6DBzPPKaJoyueszR808bZv4y4e2KStXJJ50a0ofcQ8/Oarq/azvXXpWNmgQOUskJUbdwzkmFE
kD8PcCRsSN0VWfHdheC8AA1bvCSvPPguXz+LHSh2IeSxpZWI5EzRtv/KRdoj2e8LDYEmpoVAksQv
4a00VROBx0HkEG9Y1Pe6a5cwtEh4A1JdRFCWUsDBUICXPOFNi51IUF+YiYVdMS0aMzhBYCYpTt/w
sR78bEuahIx0pkNoH83cLbU3Ta217OxZdKzHo64zNQR0SiH6VMmCX/QqosBch+UPw0qyFqnQAJOw
Go1oulPx9PcpnmgGkkwUJ8Gk1yelY/Rkkru1QSu3Qmj96l1OsaSW4lM0KjSnvVnFPYex80647hEA
v4P7uIftoiEPasoU/fC8Z3yyp+uqsKdzXbIgf3G1XAecb/oRuYVvBh8JoNlLA6BeQgLphwZJiehb
AcTimonPVEJQYKEkJrHvLZb5K3Hq5o4ERZEuAQcNq231rSbVaGdOyBaucn2ZJvrDWXJFxdQ+bSjb
UJk/KyAqAWpjZD8AeqOCgPVcjPj7qdAoerhTh9gpcbhxpVDyIJp/usp9QOgiXrzG7Ss/7juPzjCo
f9gSvk31/1SBf47Rtm6yGYEZy9Pv+3e/M6qdIjT/EHpyJ+KqK2rqM/LlvkEhMDQhngKFFrONHFt0
xi3oMEetDF0bxeBOF6bK9u/w/NaZPkQPVw7cOPI+05q2l2gQi7Og40wnhJu88UUbOD2t/Pqowr0t
39MEh59/YdY9HWM8IetXpHpAj6Qbh13XR13YHg63XhcF/uKZzFGLLH8Iwc2VdPJalhZKQAE/N+37
7epOzeib9mj0I6jBdi00WTLI60xgMaMmRF2uhU30xBPLCBUvulOFgmDDhaMl1tF1115u4YQIOJXU
A6gXut1dy7rv0TUqfkgNmn4CJFxcKPI+nkv0ZRQTB3tT8pFwhWyoZ2jmrU7JVvAy12JBgUqno+pR
GHFUi5Qw/gfAh6yBeGqXO5BTqrqnB5KIV27sjC+mTsZpXyLMOTYG1B5EIRWAuazxK4vy6KhX1ykr
wakPuk7bMMy7SxPTHe/vwF8TMvMgQpppzzpqWexUGA+luKky0jLqZVGKtujTKkL7Hd7lmoo6iJh0
etGCsHDckyA3+RmtWJspLWA+ekfkPaB32EcWqX5CRgGtgytQ0EF/ye5ADkMIvEJeoJJLSOKAF/yr
9JpfK0kvVkiHgPwSGDqJ021Q0trImD3XLFe8/WmObWEge0v3S949r3Ci5RwsO5/mQdeAlzvXC9RT
kXhSPnkQbfOkajAepFCT0ghkWcGN9Zr6mkeRCfXdtBEH5ZT+aFt8FlXi3cJOKB1yAWtVpy2oMS32
hXiF9RG7SwsWeN+L0RmbT639aRm0sFP3TVNBS1DM2+1XsepLMCTbgDoqREE/DiQWhexJGzmz5XXY
+2pIPY5M/V+9+3Y3lx64joOzRE/hDU1L6SUCRFs9vl353mZOe+Q07+Ieo++T2s5dSxDvi01gCFW5
uK9suJaoZ67FcweJZRSnZgs/B7hwCu9y6tkVuWd+b5+Pt/IBwMGEt0AcVyvWZZTo19yjGgect2P9
1rvKLKy7zF6a/Bkdx3A49IOtHZVBYvUag9wO1hRnxzHYv6YsdeLdP93CwmR4cYZv+mPk0RE4QQyc
He7AY6v114Kb4qBMn/ayx8hHv+X3BonmB830i9D+yt4JGSolVr9xs0YppWN63vdySz47Yh3Y5mqz
dEwg3G0YYwwvgla5xvV1HVk48Kms+6EiWXUJlhCqLKUGSfVVJI29Q/La/acfBwcgx3yqLk9IV/Df
qBKl10yhQh5+SP7zHu4oZ9ba8chFj6XCI/H4McYunNUk0r5E0SLfAp+jv+v4vqO2fA1MH2ih2vch
xomC1s2yf/K4Ah69AU37/Fm2ES4TQjtIVFMnBnwRXfXPfuRYSXmS9v/P52RL7bNNz6/4Efjp9bm3
RKKmI4e9gI+ft/s+jx//Esh2qf4kAgKyvNb8pRi0rV9GG5aN0vISgTF+KwWn5HPgL3wCgkJ3PsZJ
wMF0uSnKMjcCYqhjDdbl+DHO3xw/Sm7NIxBH1XAV57WunkLHWABy2XOGvkAdvaWizlBrm3z+VW1+
PIYW/30GsojrZFUExKtY8r5PJwfgbR/5ObwXOoqev+ReuAdEa9g4bQLshuoL4nlhIUnBdOsuY0nS
k3NdbFfWIzEc2plRXwjeLn5grjQ4xAxVfDUB/yN+AyubWAKm5iT6rSm64X7oeG+kqxmaYMIAMrbn
KRl8zi2v1ypkTVk78VOgBWKXw7IXMYpX1rT/xJ87f2AdmgcaitxPQLVXrlIZb27aOs7DDwo15+Wd
VjRJPL1FpTykRqonN8AbtZ6Q7C6KBo28+JvyfcUSYNjw9q2ZApqmXEkLq4r7Y3aUCRWDz0Dlphme
oUSQeKVDHRbMXPSDfOXMrJvBOpZJgFsmytpJl+PCHAulcgsDELfMWmxseCu4+uUo22nO3l07vH+2
7rI6FDo7OKBGvQ5UCxCLYJN8OI+Yt05lLObl0LYmqp+97eq6YHcCrgG8fhYX1/vwPKY3JEhwLETK
Hk27kvwcRISPQEd5QDN6x72xnSnd8FIb1pe8IUUIgrbY60yPiKAD3O/KnKIVm0L/kX9yCjKRE776
N0sL4+7XIruwhKxiGVvFwTiIB9UZa79tXXyaBARA3QSq2GCkrZ9bZqrq00n01lcPD98SdnnmvaX8
l5O1NZbN1rjorwOOk3JcHa2XSIvQIzPdfh4WABIDhsPTJwoZ7UMAoDtcdbgFThlEhgOBocoljGM2
B1u9RmWSdF4ZYfaSN+MmTHksJbHJTNBIHTa5t5vuqDpt3Zpj/nkKYgBDXuUC2RBYPcD64Yde4LOJ
XitLNCGoUG/uHz1VDlgWyNIv3S7rqpapf6Wd7C4LBJNPFTdNC+zAPzv+bXzsyFz3JD8O2bWWbWx+
y5SpDtMlbgnMescxkprHnjKl3MIKfijnfYwnGFPckr32SqTnDbS8CLh+X4qmiEyODZ38Zq//OkVd
Xc4EY1o8iNjvQWgccVYosLxYSJSw4mitfCtp2qcN7AwB+gKhzp9qaOIIWU8pRbRKJ+cxgG1f9rTz
iP6Yg2CtHoJn7ZsqdhsnKXCdNLX2mWy5gPdm7BIQ2k1BHZ94ht+x6mxPRuV+W8DsPsGvtwpJcLN7
IDdnLVSzn2WnT8q0vW8xIpgvNVr34XDNEMnYvidVsmo3xHg5pV4ShqSI2sHYEtTVoURlz/qGNdAb
42kOnfeWgzodDk9goum/HzRm6yqWMbqgMpt0wbh83Yq/1Q53ElIwCvZG7UPZ79DQZ07ho3wXA+7D
YLDp3D+MVjp78pL1VsDeP/ZReH2/6DzjyiTX9D7vTl/ZmszBiYoBkHfKS2fdnqE1khNKDWnpczZ8
oppC+WmJzvXYCu/qIMOJ2mwar64FTLlh/wdy2+WeHcJw06rIi89x3GXZf1g34B9v+9KO3uaoGJF7
SlD0RODd5YWaXHXcmjJ/xFhN2jDZPDfcZ9DL/koXmwK56COl42D670jSTaFobp84P7vlDUyrm5nb
1V76N7zRVXK/PwwhZze1ry1rnwIAPqav8bWoaEL7Izp2dk0cz0HPOViX6nhZB4j5/5uX/smD21uC
lWqLIfJrv+0tEdZWf7kvRhEv44/nSXs9k9hnhEWmqqODec4FWqQCENMXlgmc0wkNl5UF8RAUts7I
A+ctVWTkoLRmv1ZFLTEDNYlrnLN8+BKpVxbbCjtJHiRNJW7xuNIOWyswUs05TptaQM9PqB4cfrsc
DcMhphZh6akUtFlLjVxYmBbfULoW30oucT6In1rMPOg3lgTdHT1/bNfbDN/JAVdSLQRyFwvPYf84
J42RVGL9e5cgQw1B/2cZ+dtZtAndFRPYoTmRkx6KDhBfJWZ0IMd5waMRC4hzf57GJjErbHsHgOta
3gIVc5QrXEeBGD6OVSQxoKttg1ql8g9v3HIHAa/RVsG9QBqOF5KXOuUiO4OPobaSmrNzeUbvInRN
xKdk+BgO5+t13ywLxU0APXhPG/1ubL9Js7+RACp3ywuG0VBHpn7r3tsQKxMuLUzHjPas3SQIPKzH
jcRUM7g/JgYlo0CzLJH4bAMzuciutlkMoz6Tz9hKsWLMzXoVVFH7CxzOBT9EzobVPU/uCw9PMwuL
WYQ2bRpuuf3Yzu8XK0KaWlsLYwBrCXAv/PfzRGL4nSKi/bQpywymNjPLLm3CsVxWaS/ALQhhT4TV
T47GHQnJFoqH1kkuSaDrjvlcCN/+O31CyCDq2d2SWhN4L9TYrz5G+8YHA5mWR8HRYohpbJOKV9Ww
RNZ/QuDn2UyHALn+6z0vOrbDL/wVQ6hcrRVPjm0K7va3Ua0ESBcvGRUrLlN1eXcccENy4+l7V+g+
mXsGKoHc2/jLZ7QD9wHbyEQkG5MnFe6vKloznWgvEA9CeIkZBmwjFOyyXQjp+EAGStYs1x2unyXA
iJDgCaqt9tPqYWQeMmH+Z1kaHmh/OFJornBQ07CvQhI0s7QScPVqLFdXjJ7ovqgQjaF33TNWY0OK
Z5GI9TVCczNQqs2u0QhOfTMR6awPfs4QirTE5nWjV6khRY1rlHqQnhvoJ8Dh/HLKaHCTzvn57D3G
7YKc3BhAk7Fc9oxTMK0N5VfJmKHuRDeDmBec8ZxmF4nSVzd1Vxh6AHgCeZT8dhlDefv0qjNN9rdF
fwChNmQV3pQHfab/TlLBLqvlBINin1goOqeIpuJDsx5Qy0Jf2v48mAa6GfXulnVAVoWAQTkAncm7
duqsf1uly1A34pAZj9Be3Xm17Dm00Fe9I7GkPSscrdf5eneedDJiZEK6SPsu+D0pNniBvEt0dQsW
NVNFpN1+zq+14VetEc7Frt/twcpZmx7uYpuJeX+oP5AaXW/uCEj//9AMts05Faq7SpVQbTgA64pS
2Er9/fnxNyfQNAL7Tz4CINVrLT/OvZqdCOHWsU9J/rvPcsetjT0zCjYWnnNp5KTW4oIQOicqSuLW
jE0d7dibEwYS/q/PBPf7/JuJKvY9r8T/1AlT6qaYdjHsgPNzJ2P/mZ4R20EXuFQNP3lp+0MXSFNN
tjOUjHVfUWhFCXOhAJMZGlqbUwMVTBYNumrodilu3s5sCdLpMCPu9bv1E70dEwBtaV0j4F74bI06
2kSR+noKA2bRzh+rBKUXSvJzfz7J4yDKXhXp8BLcp6G5qZSb8HnQSDzJE+kXuGg2rzUYYJKvDUq2
5cdmMatT516pCJaGAD74eFFhlWBEd9ra6O896CBBtD7AVcU27TgVWUdExSiwV6WNS2OrUnSDLRbb
j1U+GCwabj/Fee4JCeHMH1M4OTQ56BdME7vAr5wbBYGDLsc8JkP8EI2H+1zNOUwjhOTlLgviDQwB
lamLqyjk2AQptSsuVB77uSzLb0rCoHjJvmLXxlwbdkoGwtfyIMIrC2oGp6mntwe98HtGyxFSdJSQ
z4URckwaVWa2lASaG5K5NgzoGFZdpXSWzTIKIOSQcLXmlM/QINZ0hUnkwYrRN1PZ1Ubvb1gB57Py
KOpZljBGFtcpN5T9ws3ww2q0c7dEEPdL+OHZUKScOhJChrUPaebsy7nw08Yd02sQcolgD8TbUQ0t
Yu+StvFXq7bcipW/wFd0SYtaVHPwuXeBbEUqAfy85yL+2MtF0n80tEn19eGA/An8Y3g1Z9DYJ8OB
vY4IC4wL/f+YbNSA+mhWVal5RGFXjiY+TRXilzrh9HBx5FeeJu2uLcmsdIHLkDrHwiIftBxHZqUf
owb4mGfJWa3cDX8Z25uZ6633pYUUjDmxQibecZ4McPXoXeZIKXZlgvVA5Qr2eho8zA9NuDU3kfim
KpO2ZDG4E3wOsWRe4ujKv1g4KVtifDizLJVREdmx+2Wob3lZ5mKNuM/UYAiv2cpawdbVYNdN5nmg
LRkZ8H29Y7mLoXeuhnC5/t2nMN4HCCdjIs8Yi47YclH4PEWxfDDT0CYwZJMJaBw/DD2h1kL79l1/
q2dvlrq9DGxpiU72d4ZERFlCZkT7X7Vee/C/menHrIIQUhRkNiYNOLl6rmWxLfGxjbVfS1chttl5
Sq0vF0DVs8T4kOCT/dzjqkSFcUazE4HSt7IBSXdNLekMclUqyGKK5ciu7Dcq36kvqFhBIcRmGi1j
Bwabo+9nRd7TJQFSAlWGlnzcSDlI1B+pEbZJjY+7oz58tcavB2IjNr8ziW9ZksZge763hRsuZt5w
pnQfLtap1ZzZByhOUVpbrPVYELpzS8vPF1VAw53pmqkjMqYxnSkPAZ0hn0W9jTwRUC1h9B5HtlRg
3WXK4kTC26vMMf/OxtQn4R/WXeFQsWgXfJDxnZ41gwz9Ro0ZUQZrASXC15xdDBtfxsLYvVRQd39I
ud9REuk/Qs4I2on4jzAChF9UlHbkW+n9xs2KGBmG9em56e96L+LE5bwxxy/2iDWx3zJAeGpc7EZH
rFGdngW9FL0YTyp6UQC21e6Q3QHwXqWRa416WtvSp64dPojn9rFZBXfqJBZ6LplRpziBKC4ZmRPB
QROsL7ILvL2KVOYHyqXqwfH7QBJCqryTSanqIaBEkOk+JURAVXYHCOMjBDO358x+2yaQRRflJwjM
iAnKwVVyZidzQp9aDf1FDppw85Pcn6ol/R7SZm5nMkHB/LDjhWKCYI1QCvIZoZhAPMruiC895T5c
xXaK0MuEbAMDz58sjWNEglZBeVJMD8TspLvT9nwQsZnkOMXZVKi6ddN7GmQ29bHW5TKv1vZiBJXb
1X4v1eEjYEtOHjIDI5VooOgF7uVlHSG6572p+kKnC6mCqC3qhnZi3jOWTsdM22Cix0qUyfQ6VP0q
RVbcFZXS+GnwUkWuSiDJhSHcKZu8y4JxY/idXRVwKLTaSnyaZd7a/cijwzBGXFil62l4Ku6VQfe8
+0aOaDJs1WFdgHtX+7T3R7nraaxeu9rU8GHOEhoVnzSBoWepwh78sQjzZf6ZAfUzhvaHT/DOg9lK
YRaIXMAWjYYW1thb0+ngHwBjCXw63AhNwCyZvAk7lEFEhs99VmieOniwYLRvdJHh1JtTuQnIHxA0
Mwl9D2GIVsI6OmoQLX8kgiIOljCysoX2ifahmrhAyubMaivrOGxMpYbQQQjt/6hO0nR5baU8gjCc
l71uxT1FakHG+ScUu58K2T9jQwC1iNWkppAmjFjzS0260nznBUVM4fm7ME6uczz75ypS3O/9Qezp
EvLlXp+3dfZ5Ave0HW3GoGH17jQN8NxWlnf3leKBl/r88Jxw0L45g9afdiiHRMUeROXIlkUuDvA1
Fp//QJpaGN+JR9oTNchjqt2dxtnnW387X4CbI+GFjhCmw3i/8e+by1l591QDWMKeQo0agvsry1n7
zMOTmG5WxOwBUvl2oeGVwJ3d0E4Qn4lUKOabeAKU2jH0mlauZzHj8/CZQWwqyoAjoj0E8IVNVQJU
gJXexcrOOhc5CcBBkY6GUuTsbjZkKm62imUumwwgjGoBfSXr7m0iqlJmln2MBjUfOWdKNMAC36L5
1GedG49/mGCvk9sLCPoNxllmn7vXiROMctRNU1eYN4rRqBTyG4rN5akZmPoqt6bLB43PAaFu2HCs
4p6i8kCyxOzUwsL5Xvqs3AAOFeMJEWITkwihfuYQ5+CXV5A2KE6o1lFmvt3KlJ+SweVEO3tqDXAF
jmcDH/KBEbs8cjOv9DFyaglX8ZSVG6IWe1cq22/OUHaQtDfChFW6/W660zPeFea7Blooxo6w3vG7
+YGfyhWA6PvlilBLLtN0hca0t/AVT6wqLKS2M5RIzNKWJqg30FINqRuEIebpT3ZTnJ6kkM1xuNS2
a76aubo/G+VXFI9paxtkC7BH5MzkFb3kAfLSFFvX2eGLfF+hGNP2hTUHzz9f+aXhAbbeOu90peRR
AXebYflTaplzA22PZIJZWrtLIUX0i7W2XU4ehipd6QfV4AukM4S1+Q48vxXwDhh+Qrv7YC3vILhH
s22EcfeluN20TWJNgDVzlh9sz67xwFpCJINTvlLCtrm5aNwlsM1GpHnuKlLgeigOg8W1Px9g0TiE
6snO/nHRjuatqwTpkGM3MQKXLLLW+Ub7ohRKaIXOAw0bO7dsEz1sjIrrFtK2f5+KV1hpHaAtqegI
3LlbqMnonRrDwGiRGdZICJ4mda/e55dQ9qgy1pWfzyIyPQ4z/xP+JyVN99yxqRFGHS4RDgvyEOdk
y3M4f+Ac1cbAP63DqxgHk3XIPfenZs2gwYpQ0eFBDQKUrAdQgpyXucQyEKb0E1B4DBa5ypK7PqgX
96/LWU2Dq9jIF1y4/rzE2GoohDc8j2PYAIIkzfa0HZAYzHobCU+gTQNwPvz6Dlp5um4O45fNRtjh
Jdqxo64r9Ppi1fppXqTKOaC1C5SzO4IROXxvqiIPpKEKf3brYvP4pHeohrfgB2NfBaXccszn0xXs
ucwvaJKHdqfRlLkIHB7tTujdeCZkVMvfwjnXN8TIHDiSKdNpTPJ9HuGnloe6b3I4lm0x7EghvRtl
ViZOhlMMMzwX4xSIE32zV7UeUk7SVBa0rEhPmJYaynvej3rY2UGOkGpowR0KJF7oRoGbdi5igFXG
PTGwBJi1NL2ZvfVTcOeW1SyAjad4RQBPyvNID6FUzcCEQH7WSNqMJhFnt7xTjWXMLQ5eHcp73b2T
4l0QS7NqW9W+GCn16B0d9YW0wP53N/qzq0mD5QM04D4e4cScToBydpHzEr59itxiN1ph3UR9R76R
fSkUkPuWLCdPM7t/+PYh5rg3aqGe4YIu0VqkXyGQiXRoy6g19/l5fVfaMBqXrhvFrczus7ayi503
/af34+9BUEmBbD9t1wvcZdBaoRMoG6dRmXiCQu6pnKo+3u9Kn8Y2nROmFQGnmzP3PnjtVyPvC2sn
5J57szwLiKXFw5mDqLgJ8XeJi5CCLsXv6W1xS7mmrHnMC9IktSIK6CXDkmPuws+pSTcvYekhx1SJ
aTdJ4GVUWjBwSGRFRKf9fqASwOUrAy49jW4aPNeaxWysqgCrb8+Z/Nju0u4H/LYt2ICoAtJ0Qgkt
16AfFhsYP+EtS7oOj3oyEa6jMtybmk9soWlL7xmScoMulKR12ZRzAOPJn3Szz4/4EXeUGX8y/n0R
2tRcQcnjN7j5elFqC5PDWddjOhSLRg/PRkxvnPndwLIJx+BzlLQhEOk8P/qy3wdfmc40pFzE5vqq
B0NDNnZGh8sZF9hTjutkTofjgqRst1x3kkja2jGk3Y5/kqDEDLpHrDwwKZCl8GDO63EY81etDNyE
7EjZR5Yg8k5n3BtkETbkeN/6u/quz+Q6vO8dqG0hLRvytrF+pfdouB8PkYMHRUIjZWSH86AfU7/Z
whdyD0BBsvFOwrK1qwPYW//xgphseYK1+7mnCSwWWmNkOWG/XzNpjbvGikX2mWVPnbUGrjzV86Ob
xJemH9k8zE8HMbMqWpFlsUncGPUdnZnQ+ibjiySfNGqyuJywJ6Z5kID0BvH/H1u+AEp1Hs2moGPA
70Y1CmXC6F3Nb4j/Z+lK84i/B9sXPZKdMv5+rRk4E5nh8K/hfT8jYmwKFZbyPDufQ+40uC2R65EU
lBsehEuX9MMV8lfPI+4LPftUKPjRFTSob58kRQ2gpYiZAH1Pzf1ggiBub53p6kzb/T4kHvbaOUAf
LHB/TRQWw09CescAtqK1FM2KVUKPOT2qYzeeuKHchcWf6l8OeKYhlgAcy0Lv3mf/wWWLD0ctJmoX
nI37wjpkD7XLCvlEic5WAqzaFiJxUSXPN3u85Blwv22T+FBiSJlUWj+nJY31KspfM4c/Ou1Cg+WD
Dmx8rA1/+herDyxsjK83zyJVjLJwRLSDCcPa5wgNHm0rcebt83jjOb8VYBGUpolkWFVzvYkJjnMg
ZZFBtjlNLUw1jfGypZZYwa1r+HXhajWohw8TWoPqMW8i7tDeUFK8kYEsOm+epj3q7M8+khh6yNaK
sy+LtTm3oc9PjZLPPlqcZQ6OvO/4WsI3/ustjij9QUj2r5KGj99Y2ivNuqaozA5B52KLu/h7EpRf
GjcaiDUQRxWCxfIfpl/nH1vM33/rCdNfg8pnbKB/SYIUfbd3oaZZpgbChz9Q7VMoQtrRfx5WkUf3
FnvwWd+tI8bZLh1w8vKu4hkb691eUxHu4Qh2JfLWpMVkRPmvXN7z/Wftn4Du3jLisl7k0WJJ+bCV
HddFVp30aiFufMvlwnmvU05xrV3xvMMjThB/kmHhftTfOl5NbVPeJR2QQsjUYpQPj2nC82qb1E3N
KYvywZo+u/EnR1DFhK/ZmRg6aKf5hsNFaCwgs03j9I1cxnRLJttzUafj+UA5T/VgIP4ptBb1NGta
4+XZJyBodEnBAL2+2BbwgL8FHovD58I4AWnsYWT1DGEkOz3H01hvA2Jlv2pV/LByfxS8Y3j3uB9a
eBNL04rGn/aaH0D5G7VhO0y8oEEU+D4PfTcvsWa1tVSbHero9BuURY9a7oPL1c4xM+xwW83G5+pv
w+E+jH7pNZ47WfQjJ870utxugzjrh3G/wyLkpyqxrqEiN/whKXKxzl0QbJAyNdh2oAs3WbnwSJ/b
zB+06pIVkfloaQpBZ+VL0qGu3V4BteuLW4e3hsX3s5NfEeP13Hc5YUwMxIEE1Ird6rnXn63812jV
xYKNUfBZ+S/RPMBdNAdITkfmrMGD+zx4AdCmx5ONLAXnpZzgtMuLUYc2gsVjThBVSgJGkT4BNmQx
vuPOcMX7CnKgogBUNd7M9I3oKlDXBV/2Bsmb/morCyxcCxE1cidmNnpm1okAgMmLwUcw+AVps4FK
1HOzFMeSKYoiHBdhdt4aS2oxzwwUPeSyOmaz/SV4Qg95zIndvtWb0xmM+TdxGh02uAzpJTqUZTdc
5U2Otb8VKkdeu8yewADirM93HCF9ZLdwjuq/HoeVusmvDe4VORFPZf7q8Ph1k/agdzUOkWSXasky
aXsoYRoAKFELnkEVIDybIaI7BiRu1HN3+Z0Ch811yfmdtQbBdbVSvaoSOUqPspr9ZO1WCskKSyu8
uKbNNuJ8WS4V+OzlEDE5ONJ0vWpzobJAYCVYoNIfdHJOCEdJqcFXMlxJVaqnMjY+/3LGC6Binmy/
9CMSTjR6fL1Bl65zQlIlNMuPZIkcgHPvUBhdICMPteWSWGGD81RmRy0bUsUqikZYsakTO2vzBr38
jpnk4DH1sdu1tJjC4284eDAGYGwLBa3OYrNzWwNKkyUXs7BxRhzyDpG3f1smgBNojMMabe+65cQc
kl1XiR6+im+hxpxWOGYITE9QxjIuX+Bydc1LLp+Jo0LVA6L5znsgROxcrSX2b6+Wg0wRPhZFqMAZ
GCMdh66xAmcx7+J8SEqp7ZBW0I4sNNspQxiEtWPhWSvjPjJm6VeRvZL5rnL9VNTVM2mJ2lidg7vN
u1IvFVf1RByh77Ta2EFiH474IaFHUZAq6Wcm5jV/ceRn+3OBNwXLzE7ROPXz8O2ssgx8NqBdCJEY
aVdX+K9h6O5ezXi+G2cGokj046o9LjLG361ST/3nhpVYm6LjqvD+g5JfUoNMrUG/8iiCAG2DMz3S
ymiSn8bJLB/zlw0TCnMiVemTMyFTz2oaicFefOBO6tkCrRKQHOJBtZyNcCqn0RnYMvvLCOilVg7K
dWAMLNOHRLqF6UHM65iGQ6O2+j5fBNan0xn5otLWaqJ4SJZKeQMjed7eY0IvTzBe37sAo7KCZWlk
p3CJXWRyXGE6v0s+pQUOQYeLDqjXafSexDLrY2sGYwM7nYvVGF3pLn/lWmZD2hBYrQUPWWqbQs0n
D1ONh9XG4r25IAuPykgh0qEf3wJuwICDBECppBaLCfNJKrbgODLdaSrgL2W1crFxA5dVu5mwnBsR
yD21UZt3T7a1l4jGRsYhNcpXrjT/GjmpZAs9Cp95zVkzXMYJvSBOIWtPXja55ShNP7Fs1wk/hCUY
XiLdbbTuaYgSFnIfRhI5HNyh+Mus36ut+GANhyuqMxXBZNhMVBiJC37uKfdwn6kLIqs02c3T1qT6
h1lHPHsnsD6iHmpQLyYpsyXep8ZUbtMnL9AloZ1pdxJz4PSwNEzu5hBkUNsjlEaA8/iX0nWI0W14
79n/MWY7Uy/3VUb/PdWXIpXfZ1ijW6TdTFgGxgoLnpoH4ndHDcL5j/v3Rf+aMMMZhWgFF/+HCDAL
q6Y8WDMrGH6nTFYUhup2dIhphJpKzA9BX1NNbF2CQ5G4BNHiCT1nFAysIEjsPEAHtzjcZnQD/l/6
4tzktik+DI7t6vbu3Yzh9Yl3RCh9ghIR04UQWvdUgHVoaqK1rDoaftCqnX8kmn/NUiICKF+VceTW
YMFBHDys/b15315/DAPGg1XztFZz+Ex7cfmDza7ZQmetNrHn92IC2uuqXp21Jo9nD9AyjuRu7B+E
O6ycdxU5P+rY/sG2zsFyPuT/h+GAFAM09CDqhTI3z+RJUkTYHynBo6r6QBmOb51esbCjdsxxIaZ3
dSNedhMBOxHkcNMUhf9PvMEHrLnz1hRrXCMKLFu/fo3Yeonm2mT6X1m0Ki/h0N4EgoqdnComy8ek
4UiiAT7FBHiSTcQQlj/yy+0Bl33to2SeFqMYSC4/A2GczAiPTfITpy44KDHRkxAPF4Ai/cEYuvYC
0ZiPYcg3ntt9lQKuSlKRIAyE9mYTi3LcKvDqXk53+7XprL55ZiKdUgQH45VDp5sosQjpY1/2GDhD
q4Z6PrdxMOggGcJMsX72XETB09xUaUaQSoHbIN+Pb5sXwDsCGwbb/pGgRlKwIID7ZIduChHp53Rq
n1Zu034/qQRCV5Lgtsw+2D2jhkO9/B6vN3HW9Bn3rrtkglrM/zDM72WDY5mcpZ787Qeu5kAq14Nt
1EOsurxkRMznJLIDIGiEeMWUB50dQ5m+I7uznaxORrQ9KM4eynzVber/hXKINfd9088Fn3h3Vd+j
OHn+hcm21sm2/hKARZt6SDotfF4bGyInFuzHIe43rmVHNTlA2h2sN15zOQYqlexAbel6llrX3FAO
JxjYxGV70JsD/taIPJbJQAZupjgLWaPhlsXwbGfdDM2o3iz5hfc366viXjg/tiLFDh0mGEX+Ak5D
RgEzbaCAclNjvnDh90zDVtoQb8J7Kv3nlKXPOQsm/KXtDVfK5enavOy4gGV+miiq+96KOzkBoUZJ
5lIPaQUTwQ4U8kelEoSQ1zokTH0zSSR9K6FvqkzcrdMY2BuJYYJTTbcOG+ERJsfj2A4KkQOctX3q
O8oOHgNqwm0PgZMiKAqKehWwxnIA2dfdTvEPMMnZHvR7FrfPmT3CltOW9f/sj1ZbNTI4SrQ/TGlv
BpckF1sdfBqvv99AihE2jxKwtdaYs/W+2ixaIrwx98brwQStB1bCuuZMbFrJZU9qfH0aWtLuTZJY
ZZsVNjPoO6JZMOVyqlsxiUUc3wdKkdL7trgquLV89QsmsU7Lqog6mDijRMnN4akqJbPFTv4xeRCe
TKKtO2kysFGhkApu75hA9e9NOS/WGSP5Em2Qj5WCs4kAt1kkNr3KXkj+a3ZLdExLfrsAvXa7paSE
rUd6QcLX1ebgz/jtBOy7TjXfYJiImJ9PH/6LTSgyliFrH8YuPTuBqDmcAz0/uX1wQcYJk5sZjGNV
OWtxYOQs0K3EJNyQIbpud2aM5r09XbDwNtYBCeONcHsL+FG4FNtWkDE5nBJB6WBP8F/+lXRaHiSB
g8dtPcUSRPmThYkRidG+dOy8J15sWNZK3LS6jImTzFN609hI0ob8vyZSY0gbyFPmF2+RzeOMf/EE
g7Lquy18PVXeXCbSVLw84z0XMaZ/zCjA1MntiEvgmoQX/S1WIicxAD7GnjwxQB0hwGvldTHqwsRp
px5HZZN2wUfcFUgiSd3m8Qv/TZN/t7jm9tc/IKAtcfvQtLSIzevGynoiJyPsvbZX6JbwWZ0uI/jT
mTtRkkafuPmtZLAH5iXgH8QfR4OqiQeJQ8P2CkP3zKnLgmrptPyM3TTnBZJBhMrpLj4UHGZkKuyK
1/DBLMF1mKXOa3rbsRMYeejIw+mQ5soBBUFGRZLGSmTG5CHYPUGacbHnDqux0P6vyRNkOdYwpTmy
o2blWuyckamw6OXm6N/TxeJiDLHyTTqt/F20yHoOCMV2Z1JreH7fmQUaTBkVnvslpgqnd+wSu9Jc
TMjbt+82S3DWtko3O93u5ln9kmkr7gMgLAx7GNQDSS1XUKHHah65dvyNF6V8hS9tovp5bOC2lGyP
Us6TwiyWXzOMzCLu5mrQWPDOXpLaH8p5mDdOXFezj9yo+G7KNo2UHrExCQobZqvzO8lwghgDmM9S
S+9uqmYThM1AXXOLh0ysRR9yeKgMYoAyM8/1P4q2In0N6T0flz310qjoKJoCbtKHGMScdV16dJ5V
KJpy21jfeMVPV4q/mmoY1iAq5Dfah7k11NhS1vMz3Gc4eGvUKqplu0ku0PvvC5vH9A5tvVReB/wD
TEzRfPCr5GNxXq6h+sYRpu6Sn0asjfuIIdk+92JkcPJ3/Hp1KTkCZy3Q+PrneJcgqLg+Yd11DJye
LqzfGSgMyQOf1kL3sPonejK+MAB1jjsGsGDaP50qS/s6u+j1Irxwrz52q9LPoBY44Lttm4uRSN0B
QwvruBqI4yYiPIb7foVuBl52dCJRSMAZ5kG0dQhAzOJhr0YH1eG5rVun/fP/ypTfMaIzw3nPZqjl
+t6+XtLzRs6bfXjTkODVUKMe7Avg7OSnYus9mep6JwrvbzjHYZqW4aXLqHW4K93tX6xZzC+XMhqg
A4yZP2sr9PSDGihtcPR6fIXaBGT/4TLASnsxOVbIdyQUgbd5PY2mxEk4qGAFzoRQxbXhiNQSGMD1
o0yjaVVydTfbIgor/FNcDcAnx1NOZ+XIwaZxWdqALJIvSQsgSjAUUKbM+F6PzwOxG6Het6u4pL7N
KfruzQzo2cAHYc/vsuJBq/2OxFEuuC9ouKAbWYoARvLW6CZ8VDsLMfeN+1yzXXYRTw/uDYNt840z
aZJvMkFllVkafqHF+raxux1wOFemTnFhVKcH77b/z6Qh0CMz12OgftQY6ZLWYpcS2ePximDXSiIl
1zdEpp1CVdWQcks6y79xvYQbzgcK5U0bIRAvFBmwigIODIixOogXHfS6JODlG+KKFNNRw9n2jPYY
ysqZLq2HlgkhrwIwwOSFo3ghaJd75jHkcVL2raCTTOHV4TYhYqmgI6uv8jhRoY8benUyT9cA7Qxv
Bf5Fd4slQOFzJSobeWGmUCMMBLNH4/LlcpC9MrGSIjep9oGyob/IfhWmBzx3mN6omSP77rUQl+I8
Le51vhVIKi0Swua+M2ElMK9Mq3XTvYXH6RRFD+VZC9LK6Og5k6cLgYK48dxVAsPUVBa+5te2QzbS
dP6Po+fuxdBbUfscWXVLBOLOZZ2QO9niCIBA6Y1ejdFf6Uv8HLQL31UZDIT/g1eDBcJzsWo41eq/
KTCNp2CnOAyd4LKo6yKyNhZbpYvnqT0q/xu1FjSxLLkf8d44bTbhIywOZsDFaaLGwJ47G3fqpQCr
ufVUBcDThvldcE0vG0V/YeZOx59rsaU4q1bYxqfNSf/KuHFRUYWaDp7Rd+nEV3JrlLCsZmn5//42
CJDci0AkATH6QOAy4FHdPJSsZIbk93rUteN7wTXrisRsZmaloRUiF3yd4q3Br/MuXFciCUlBMsbl
qy7qI6+sDD8IBWMfwhmrHs6Lw7DaLaa/gRAP2OO1bJ626gcvPoeEx3/v3E1isvZRyb6u/t7RFM+H
pfJUocMlCMXbmIUioT+WCk5c8gWJXNaBSedmVSdR5j/2jV8Ouz5g7VuSb0B8VgVidOTD3jgNioFq
WryKpz3miQLHjDuTCHNk+WXxxiNLOwRcyazLmkxNidMI1UKWSZbA1U34bqempD2XYeYNitjRwRqZ
/0a4diWpb91zehrkYaVu5idPF8jPyZxCmqQZSWtTQdpdWJw+c/7gTFixCNL/Drbw9WOYsQCjHbs9
zkSD8z7p73kU0ZuFRfWJ799kkRr8uYREabeQ5y3IZgD5cFY/e0zf3I4w3LjM+m9zorfqZ21jMDmV
OGpLOTMTY/DxL5w7wjT7qF38ZKg8/DD7180RgDLrM6KgGi4rQkxsSaSIvm8Fnr+yjy/Boi3NF3oz
BsT7P7ig2K1qBnx+sQNNvTwo0ozbyvstKnog999WOVTj29zzNEfysgdaYRCt6C6Rv8/iDLxsm6Sh
daZNqbsUYwyklhRN0h6ERF5anNJ8XNuTXh10Tbtr6VisjiDG7NKElo1HN62nuLXRWWHogpa/fcX2
I51h+moR+hBUJs4dq/6zuwGlwdIj5VdulFNVyVZWzIZGD1dvI4mCZHLQUvQFDDV9cgIxthmbw4d8
2j0pZdDA0jT0iLd6xxsEVbu3GEkdzS2LGiLd0LX8cc33rZ7QCkCLiU2iWi0cFwFHMP38VeQYb3kb
jNtMrDgEa0EWa9Zvr1A8DQ5krYGPjGH5YbqHIIneZVk6imY8RdB14kEuugh6gF2lW7q10v3ssX83
j8KT1U4s/U1suKo9cBVnqGucfXgKa6zOwX00scRSnG+EVbWzoG6y+3MQGkeVnnbljcwQ9lfh7EUU
d1d73M0gIt1auTyu1Te0ECjQcqKbBddm2n3o+2O0TYFe07yri5EF3LReZlxMQvilq7Ensu7qI4H8
YVtBvhyD8hKghXC2OU9y9tsewlOC/O6H/7DIxMFouJcCyLwnRfAqB8+Ou1KI2tV93uUWXIKZghMH
s+ShCJCQz9qeNHHaNdmxzHU0QaM6YqlsoRa3nqqpW4TZcij/DevHMai2Bnqlx7H+qcWHABYTLN2S
XlrsohIlFftbxi50FfRC+cvTcijuyVR8Uh74sQzjgu/6LB1tdTeVUp+904XgVPCVNtGErgiRvo6d
l48EJbv1xqnXeB8Mx8k2Y+lIN6dx//I0vozTQTij/vCW/kbEdQU1oqircCGGlNSLAZhEH1hD30Q+
lk3lB4eGZwP1/3D8bW6cez7u7KH3ak2sXbXd77aTQdn+QqK02MLiR/q4SwEIrzUBeGyAspIyTCA6
1w2hJv7yxaUyIeLZnlEi0Y2SJX1o+bycd9b6tpXWDquWYNoQatQN4uhqm5rVOp30VZE2RWiK0akX
xs+IDfS9q/7ZbGt73hnUS6YSd7GeutUrqpaR43x5KRYQ/8PA+MGNzZNiMBHL3rlTa68KBDjdXFw6
V1xgyjPRHzByPBAqmMPYBoAPJKBhgBQqqIW+nPa1GZ33ocjk1VTGtPWmnTzYEzcuU66n7KaumAk+
GvqkrPefjGcRWe7myugf2oe5lvKTSpFITlTu533UEFNB5jPGbKLqWSXvvEr85hexVLQoyizFLx2E
wr/YR/WTKdLYfC8Lber/25ThOFD/oFmcgaxNgn+2P3Uy5sB7Too7JA4M0L3cvBIITPlMJOqU/Vfr
AaLgODRYJCLsFhBa2txkV4MyopptOXT1GJ53WvaZ1eG6xc5lTBudPCb6c+fNQwyZR8DPQeLn5/oL
WKU83oYA6GXT86dNsL9doXSbnlYphS2K+nd3tv0+SBgIvF7BM2uPxFMSN8lPdFZQsImJTtzPrvBg
GTaRKMr2hbgUWOvykU1JorvvZ1B3KTbymlIdWYurYija55sEwAW+B4liVAoOkWzQuiq27ycpEF1O
Sl0f4jF5RVwYPRLJ3lreqANDAb3Iqa9NvDU5BRSlfeIYMQOiuFH9qbeJNOKQcjTOJgjPDIou01Ko
qX5ooIHVk7fSadukT0d9v24Kgu4JajeJ3+053QQVMNX/q5Ex89ZJRlwo19Niogz02YxUUVokI+Oz
glW8kG4wqYm/KevKnhmAcMdhnJNCsUMvdRSDDu40asxPWTvnkJYB0VDPlg3nVjRGBP+/XO2mmEIr
keoleLrwSSf1vtJOruhJLxfY8loEI2dT28lJcowvNqsF8tKpTG6oA++VtgzxjVJEJpZqF5vf9koA
qYbNJmpJJKJgVjdapaWQiVU2PlK+2Whr4yTzBMYQeukKtzloFoeN/zkrIu6WIknuKsTUpNFY/By9
xrTzDWuyUPzQKC+U4egSCi5doNc5LVo8N+75rrWqnqGpkdnsk5SK/+8Y3tuiIy01PUcIv8wSWLzX
TJM+xCL03Un/OgFMsAxnBE7lDjSEhqE1DVX+OiNIojWF0/AZEmuC/Be2WDuEYDjhKyQaFECdNXMM
7Z+xYkvophQsJRCrqpyW7O8vzlUPohNM77oNWY0YKnBrj6W5QqMgFLXrOEjz6tfHDixc80IA+trg
XDegr/Q5lGp8NOS6MXlLmDckW/wRYgNlUYkvIunaiKw5am41u3pnjMMw0sBGQCb8w5G1uE5VBGWD
m+v2R4bXkGfbDsJOClp4BCz52yTL//QZJTOJJsbJ4L+uPlyTLfJYsuUzWv6BX7M9MU5h8YJaHrUu
cP9HDYDz97sLs2kMuDfg5PR5U8KCFNDAdUhVPB3/lF2koo5r/gQzbFWW5nBO6F4ylbQY05cQ4PlG
yQd00D/FQrsQgtbu5LjOr4T7D/8zpTUR9MqAj9x3ARMAsiCJ4WPzqtu2RrvY8AU4PyShBYPv+sYy
NYkkyputURVldHvtEjZ4kpXLqzMPVHnYzLOpbNvBfZCsKSOxZ1vw4jl+VWtWAwqP1coa7AU2UaTL
LMR07NQR3nARXdXjn93BiJtSGxlzY/wXL1TjRb7aRf6Mnoxqroh0z0pRrQuyaBbYR9K56F5+f8fm
8IOJ9XD48WmBhwRBjhNLh3go7Y8/oUlBL5+7xs4bcMTzmFr6Qt3OR9QV1TJ65oSAadm2MWWYr1K4
yQvwv3iHJtYtdBt9Kh8TSDO6Okwiz46D5C/44LkL9J6H+2AM5RhDUR+mTt/N44cDn7RQxQZBGxOX
Gh+t1O9TCDuleI88NkRoGAEAE5qdxMCb3DpC2tK9px9Lvl8QOxb+EdB1jN//ILzzvXiSrsqRNT4m
6gegfnLlbWFmALO+wqHQW8MUIQzKYAfIJEnRAjS35QU8XjWEwAcDPDYLBFPjzirUUaUmTYjTZXnm
wKcZtK3bC4pmrC/S4VNuuMkw6jSjh0UHTjSWDA5MVbFAwMf9lLAsyqM0YcpXvsP12bJ+siVVMsgd
/jRO150N0D6f2MuMxy2oTYP3hRVq9m0xUhlW0wZDkFEk8YVV1l2ARKWIN5lVMmyZ+ghk+0NaKEm3
Ghnii7l5sX9JSCFYzd3+1QSKGU2btgbB3T7kb17zQHRQPtb0IldMoDOtChTDqFF/5FItkRBkAtbB
xiJ/RQvWXiAUrV303Hc4AseQQpm2aSLz4j3z/iMBRaSeebvltp/ntEnXsWmXGqy3SiDMV7hfN6uk
SCM2m3UYOeIMySMZx5nv3hIjwKGdaMWQnsnYF1inuuQxI5jGZzOcW0OuHnq7UNW9X8MugrvLXXbf
2FpCw4+lN7G17uaNmYqr3xFJaRT0uT32xAWTUIspYVvJXHOimcjjoOUFb4/u7yuz+fJ+4XX1g0QD
tEhlHtJeci0Yaj330JLZNkXqfyuSR2pDFm+6rum+BztQJHqLCWBEnp7BLrcSuwOqD841zUFukpIO
3gc/705L7wcoRmDKF6vqud1yn5IcuzYxjcSFgdhB4ZSgkwCkPkPugS7SKCfCNiLZoNfRt1yL+yIh
+qcpuw0N/TOLgMIMtTOhkJTOEb9D3KfdIdRqga40xLq4sKuoVAHVkqy7UFimliCxOciBwP1cGhOV
kcjgwnh2urLnUY5Ih1nXCkbEhuoE3kIJiy3apuR9XxJ0fXkIWRzeiE3xCQzjWKSJzWePigwNooOS
+BWd/yDBU4qp3ucZwcBv2galNTBIl6ngcT9cAIdSxGtYS4z1yPgSSLCgqT7ajoo85kzsj1RA9zGF
sNqlsEycQ8Kh9tZAreTTQrWPM6b8HkiUVVz4VxAAYRlGa0m3Xk7uL99iGHAbQtHcDBiY8fG+e8iv
TwA7b7x8S5knXQFo/AhE8aivgnFR6oeynFFfn888ZxfWRS5MluRokZmXbFhNWybPNz6y3Jr7Sg4t
5zLHsGPKldv5dYVFRuajKTasBLGtaR6UyaiCyQQdTgg1dhvVsRqJPZJiW21PqQSwvceh/L+24H3d
3r0cFWelkFzsubk0j8sPMPyHl2ljtS4iH61TIWOPfr0UCQy7gIwI+b26DE5TlSaaIArsesuABD5T
yJ0z5DUjOjrzKlvGFqLTx8nyC5y0U0eH7Xi3/cLtCEgzQ+FDayKCz9vMrlsB/+sw1oYAopnp1v47
+D1lvSrT0iqHP2JUXlg5mpR0f0d6nP0p5GxVUX6FOFBaga742a3vo4vXGkhBIxYTrcRvV1uomJLg
Y+eD8fWvUmaamAGrxivc2rg5n+XwZZultZafU55ew2lJ4HzK1CbuDA1vYBoxqeXTQWw3jOJs/3IF
Cv+a3FsJBX46NirQquhpxvaoesflnNBVDxd1YZZeTJUzyxYB89QaMkwdgKReLwI/Q2QiNmw9OuLy
F6FTdZUs20CmhK9KJ53IxoE1ZxkCWMoHi1i9zZfJ8gL9DpkRMeTiiR0/Pr6aO/aZgrI2O9HP+b7M
5Gbny0tbxt3vCTIDgo68iaBPKYP+Ipn3IODVODtDvRyE2lCBYepb3B8rnWBAbWaPmgLYoHflt4f/
v1meer4Cnh3dTbNlHk4ze9qiOoUa6ujhBAz7oZBJGcvtWeFxhldIluT1qgHodM2VCK9HxKinlKUz
5KvqL+3ToRaEkli0RJOk3DO8tnmhtm/4hHGBUm8gF3Q4DEbTSLfofyefCox+HBocpHkGaqyBpPrE
qKR6YjHkjcHYNfxulm+mV58IWktXqzUHoUqAayODMrioekEHL1GPbJwLBUZY2ZYL8HZitI3TlBRf
eWrLhxsV3ndCSztYm95rtEEjn9EKxvwaLPmJMK8TujxIwe9qk0Y4LGdKNu2b+Rt08elbulJcK3Bj
8rGAv2cLQSCbqLRbHrx52JfwD2eKG7W0sJnf2i5K5OKJYxF6T41CM0nHDJ6oHNjXegf5pzUkkG8w
6X+Trrm17BlRRXvX909Bq6Q8y5exDME/GtvbXq6BTXTpk8QxTsuAH7/aeFbu1N0DW28tkJxMfbUJ
0e0iKMkagPlajgBRaA27JN/ecw55GdhcDS1cCZVTcx03ARMOGyYJBszTNqx4Ybmcanx7VW0km3Mn
dzhDD4AmE0C9Tba1Ig9CfbSNorfmKjQ6tnp/KROzFC/GU64KkiDrSyL1nC2meN9nvaSDJzGx8yWp
7Grysrt0uT+JzoMWfxYJY74BuijjMS7Winh6W0jAyWQNfS025E1i9CBCxMSuNRZWW6bpknCPPkEb
j4G4C1lqRvDS/vwjInComr1YEnNkOXVuEkslX65rJe6tAVSnSoo+Rw5zgFAgpo+Vcnbza9h2hwxt
lPbMrajPsTMqmsp7A2V+Y1yxXcyTMl507Cl7My22ghAuob+scSGHzYFGlrJfPMRG3HtnmRwgBlsO
32oe2QIXuAvV7QEDmj4TGW6DyRn7zIT8SEcBwF0nvrj3P8+WArmONLCdUIkEWepkU5oC4eqskGRc
SxYfSrhoSoF05UKYPbJYMdy+R9h9XFY3IMRn21UIbH9EscyeorA/yWvIWkF3sd4Acss/arputRBH
jqZW5hkqoJneG19e6r+aRWVCLWN1cNwNW8pMBt9bYGYrSJb3zcCcjLEb+5+DPl9HosBXM677y57h
Dm8AycTehvF/tV8bTT4RmRW7auO97VFz9yjV7Y1KsThbxU70Bh3Rs/r/n8yXIUHwACHxr/5SIuPc
wgxMYu/F45txM8g3173IYSffonmBOq8y2l5UnHNPxEJrMheP+DcnGb8rMDDAZJXTSnSx2ZE2fpCt
vSVZcurYQ1HlTrZ3L6PMazobWbePPqEyIrQOTcaFHVtPdHqewRIx446Uv9YRzQJLsEyVZE8AgvSh
HNWav5fKJbfgSc3T+GH+Iiq765BkMlxzDAp3g+GxuRG3q6MeodA+bchbAK0kzk9f8vZ7hHFohKOR
+sjFPC2z7pA/1zRyMkRn/Af0GQJ0142xsrxwheq0K5mgWc6IvbNKXLhxwMmzsryv8z6v3yfLVmUv
kFOYE+bOwhZqj0q/mut04Oxw0RB47VDfhrA1ClHQFZBAHxttpuQ+rZv4YdL7W318LTNWbMAdcGgu
HSOqsnXpb9S26AmK34c8KsLx6qbKEu0I6orHSpEZ/9bDIhYIT/wdFfCtU8NVlcLjydbGzJPoP587
dtu5TgSldgH+A1Tcg1hV8P980QI5QDQY0/IEX/q2tI6jmc473FOcmLDaHj/8RKyZF6TSdjjbd3PU
JAeo5sNwPkFBzJY3AyOUF+b2pOw3dVBYiGTcvVWGgM8FMfng5QrqVSRGa1QptuKVJFUuarZcYNIR
LnegKcaPA7yN0pe3oaoKjOjVmZzrd+/0hsnY/xbNC0f2b/whVJXt/HRroquDFtW+If9Y6MW6e8Yl
H7rl0i+q/+XDB+x+LGHohA9JU3vFeF/Qqoz3O60UF7KmmZWOEvO5wHy30ETW4oFumzuQ+CGP7p8e
6AFibmC6j5KMwWak06vKkpVyeCjy9GGOwNV2jUAuBOX9Wk/CES7ZYnwYa10YXEom5rSXIW5YNR3G
BTlTZK6a/L87VeRPaS8iYqeAF6+pRH2HOTMzBKNKaMDvn8HYfwuof8ONVWzWHOhpIRyflYxtoj4e
VtegzPW3EVbWzwsvgTm5MvinAFR7a6Uw6BU0yQI+IM3gs5Uul16kwvuJaTsJVW35mmV5QUHk6pSF
/7Wp+4p3goW5hIN5GRbAlHRlpHKf2SJGGDcyjuwOFQfrdJEWV+fabNK/8IZbi2jc1Xkwxo7lZg3R
4zkc9aqFpvtmlSZq1UOymRGO+8uhwlrzjJY1XocBRXLLq8+NLXw/r5Ph1yvkDjhR9OrPQPoLcVS0
8m2vx2FWYFtxU4U+fdFhdHO9EC0fUJ9rKi9sEWKLLKiovoM0/DHVl5LlagFRoXgxlG5/Qsmb6r8V
aqOeUQLbUvIUL+Cq8/SmX03LbovaaOOfxuo7JfbitEF7kuyfWQLiNZiS95XhmtBoQ5fCKktSfjAz
FDua6vsG0xcLHzfYBF+hiJmxjzZvDxbaW+cyyY08m31He9f/RCdzNdRW43XoZnSB8tdqLRYzwNzM
NdojsAx9IMJrMsCGs9Y6G0/yjF7jbiDFZeA1nZhGle798LO89nby1+UavIdef2rhRLaEXVxWeZV8
4yQF91aF/VyDpddKSvXyjkBZKtf0+e/U1gDWsFvDL9b7W6EFpF+3GxbxCZ2R9oCx4U/lLtJQf20J
UlWifGdx/X9m2ijpi9PAc4F2bMCgn+oW49nvVUdrx7MEK2UdGay0H29t4Na4zy/b+CQb2j8WuplM
a2phqKGf9jRe5kACrcxzuZTYhfETuzfRXyvIG0Dr14LamTb8uHKUzKY4pVav4xTzeFkJXT59SqJ4
1BqyNjI2a4G+/TWJfpCQoE7rROPhclU4puQDt8uBVkgXXPRDoNyww44zh/F/zvn31LtG0tDSykTe
9vv5LuhcvNwiH6yOI4FiuqP7SPUTspEnzfgk+YK8naBqO2ntmp0fJbhpvXxpes7/mTVbxfGvdyi7
MiXQnwQ6XWzEPPAoQLNW4R5jYnjD+fmNbBn/wv8tQZvhqxGpgelDNGx+XXZKNFnNT3nSKNbbljAU
Wk2GnxJbfq/dsDzBiXI4mRSlpw1BmGd1rFIdTwjhZBaE3swqtcPF5hHA7TLqW1MbDt5g0cY5iCZN
ka8Dw+MIK+yrNtWsF2NqfpXB6iPDBT264lpdXCxv+qoPL6WQICJHuxN/KOmBjqmb3SX+DbhS6k3R
WTUI4aTqaWkhcktsgMn6X7MP5H4TPtHlxSb6xfqSmicbIkIdfyvZ+12A7HB6zTc7WsraArWP9Mgu
k9MUY+wrhpoOV7SXC5EWFKX5viu/Fd4xYT3SkAIwLAk6dEFla84BrkSJo9o2kFhbdEEuwVbYWAwd
1PNCTHzPzXUPY0GjxQPd/IZEv8ItJCUCuDxCEqTEjJYCvflkjpN14jdnr99BWC/K9e9Nfibf1zw7
UtzXzSSU9GBWbBgNz9Oj5xugbtsMBN7MO4YUmINyljU6OicUwsBIVQU6mS5n7ukkUdFEcP4B49Gs
bZ859zc8axRFEl6Y2uXVfwxTDqcw/76kDSGY+SwGupp9UXLU79GRMfRnulDrYfZu4pF2lS1GuGCu
g9bcrYr0ZSJnipjid0WKOvZXh7fVOrTQiaf1uEuKeS1wDoVAUDy+AYqx8S1do7Xy5HvPHMRO9V+A
Jfd1iB26RkJHYmWpDYSX5lw6EH9Idl/54Vi1kacy3Kikn4TrSPpDKS2smAblVsr8LhvF8U6XmHf0
mCjxAcEuwWO+lhJj0gw+OTXhnm6MJfpTqPTJkIOjj6YKEugLtnkvlNqGR5ZbIGK0VrAT6RqtBPTo
j1GxtHpSWMzgdok1GusI1qFpXRbhmTUK/xOpLUldrYOyop4qdJo06O534y7qfeAYxHfBfEj0j4DU
uNzLu0dk4K+JPcvtMS9nNQXgfS6YccE4URJRkEywTRKDZbeKrT9oN9iC4dxI6XKynjWO+wZLfBrM
qG6ZIeU9obWLt1Qq3N8pih1I/Qbo/umY4Xw3aLEXO0tObI6qtNya0141JFItc/e4U1zFhhKUqbtT
HfV4m1aolnL1Rla3CitE4APiJyDcwscNXyZkpshiVR5tfrxqoFOodk9y/kHLNRcIpkDzdbXar8A4
EwhhMq1t/3RpK+7vnxh5LdYDJn5PcvphwZiHlfz6Ulaq95IcMwIn/tEniuDDDaaqU4Cq5g8nIGtq
GWYBPB1N4CsF4yBSKpJt0zAW9XRD4zFcIAv50iXiiY95URuDHSZfO7hNbf0Y1gXihLSxcdEyNaEs
7nnC31b4oZBmP/1RWaAxGYcM7fD8k2gSSlLMBZ2+I1H9IXcFj7O7BDOzjAYAGInW/2LDJLJvfrT8
qf/29gIqwcbSm05AqKKTJM75JLoHjjtl+SqaC7gHO4g8mNm7J8Wt8F3q9Ca/WfYMw+C4BlrDtwck
EWp2qSCLHsHVTAFNyDUhkqDs9rlRSGlwSosxBfYTPrUnYrl3UU9lP6FKerDWFVA/VJi8WVcWlMsm
EHRzEyLveaK/owbERYzwWIbsisnqWNvpyI0sSvbGjGmkGHTc3NKL6sBontBxI4fJ36VAWVhR75KJ
3f13s65AFP0OE9bPdiALOUoVMWsHCsWZfY2FQUQaXI8VGSJC24Je2sDc2JKJULStyjATu0DYcig0
FcD7YcNWwOEk31ICqnmcjBbV0iBwKCjE24YgA6uxHOz7yDY+4D9qJFRXaJURoD+dYjRHHCxd/X7q
dWfp3Y9S+T/SmMi54SdDJXZ/xtHwJCL+eCe/ABIpaWSUEBRqK6rWTm54KS1L7BvsfOBtETuI545O
Svp4aszyyD8r18jD668OzHK8bap5ZYpIVmtcbBPSz1Xz0fPuiGqCbn8PYQGa7MIAnaVOz+y3hP4f
f41GAnqw7JWUtYZ8Cd8bGQTBlLyk1y8YxJ7qUiEJQlVonLR/wbStYcmzimhOmpV7prSBtoVlWmWu
Ut8e8RU+fiLEzqLSpVgVfsHM7X/FgXZZP+vCIo4FKYdq1OaJfozGC0KzV0uMOnd3zTRsDRSFEkfh
l6UVXGReHMxPUrY+scXqPoIY/SDspEIvghz1SzzosO20qEridS29ZX5TPVVJ01XFn72XJysOT4ip
s2kfIt33LyuixaSHB6xgqBCghraPUUPWC1+zfges6LVzPW3sH3ccYEN/xeaOozpnL1AETaawMyVq
fQf57sXMWd7K8Ry5qqd23qLhPYn7a4CCBhHuGvdK/OB7PVcn0Tkqo1CVt/nV3pu6RDy+lGqs5byd
dmlf3/Nd9Po+FQQ0Bi48a0/lOh3ib8mqJDywRoWeNVNGELDaCHqq/Ce0ZGDHlmRHP2mHSWMnWH6f
Nk8cPwnrxXpLA1mDy0k3wKDs/AkwkFx4OpvYd8xOLFEE5IRubWg9c2yHnhf1e+FpWs+kF3In0FEy
JFhmCvrmcpU+lbRugvNnO5w+4v9VKQhG3KPvSu89OupW9eO4TDeWBTptjPRly2aR75QIOgTbC+0S
UQoAsyR6TPKj+F9YvzTVvme0A18s3+2EueZY7YjXLMthcYBXlmiWZe6zuwzMCWzhnUeV4rZPd79C
qT9R4Xt9SqDAXue9aW+ZfgvK/G8wlq9AT0KQp5hdGxxmkLp/ik/VtQTlTyRWaYPQ5pWSUmK/Vmju
6s+aEmNEKHwfmceu2hFAyT2NV+LLms2EVh/ivL37+o27fUg++OdbGqgo8dtzHS8LjQI8x9BsCyqw
s9V5dguN1DiinoOiWMP5aMFA80xEl8SPemkdd4NOqTymDyCEdCjh3b118WDJxoUgdl/phKoHoTl1
Nt14wfSK5y4gimENqR8XD/Vol+rjxqSgLpTggF25zfiKOafBNPfN5saRhze9C+mA/hdLXGmeChlG
SqXkK6Ty8owNWriTd325YgvVCwDt7f1vCg3QY22ealRxE9qvZwL2uad4SnfJAAuRNx7+FIVJEqUd
5WZPyiaifdiUQNk8/P2z2FtgcRZpBD1r6YWizFip0d+ii9Aqlazu1wun/tZBEMVEVch/1+5R/73T
EQgo0sTCBM+i+kEMrWWiOo+B6RqMs0G0enzU1rEsUpQ8GBea9TYHmcegKGUWyQRYS0/h4ylxWNw5
eHoEVZr5+Psm9q9uVvL/ZK+WXsDZX4tGJ3tfeF4C0HgLP83HvH+LTF8Uy/59n5ITVHf2yx6KWgIb
ml7z9jYInQFbFhSLOMfOUMfEl6XR5nsT0jcaNZ3ALXTD5oi4oDQ4CPCSEA/7oYKgTDBk58U1rAQ8
A7w24VTu/k9YlLkCu1giSjLcR0/BVQuum+smiZbEEfXD4B0FvKl9fCWJaqXjH77V/pX7McPnKlJx
Pp+KSvR5nbgyL6nKz/xlMAsW+9+nuqtLsJRrdSDziXrfzizsb6pA5jx7fTQoxA27X+IlfKp6iMy4
JZDjxn7jYj+fwdocp4hRH3xKedGhc+IjIZyZFuK/oCZRNThl2vRLN9IgHLaP1KtS96Vtc2SEGZ1d
rtLFzUIo8l85CsS5G/JpelsYZ/CcSVJrFoTMzamv8n+ZE5razuvdtufdqDXVkY75u9gQFpD7WO8N
U+Z3i8L9qvUwMH+hz+1TJjwSpVldCyNu5lduRq6REylN1bwJerC7B4z8lTvUFQdiXionRA/HBFsY
IPmGcGEBGwzN3TiYQsD02KfuFaHy2GEAxhAkG4OZcXwFrNfOGLdzSfvlAB00MWy/D8PdjosufV3f
KJA8iMP8d2EYmn0GdW3N2++jbxdldwJWKX/cmPNE760xV4l0w4Isc0mpsKwCh/E5uSN+gulsQQlP
nBtXAe/15HKCI15E8mPHijh423oYMwNQNFk7Qlj0L4PW+u5uH4Bc9g633QUHPXvRJnc5p/0WECLe
MUVLb+JcUtKZz5dEL3hrpQI8/LUjVbIVmm8nzLUt4wBuJ6ZUxscPwc6uIIupBBiHYlCiuV0XP0Q1
VgWPnZesZ4nWUFi640PsdvD7uoF8upNX7A9g26bvUBLzCceglpdHxGS7IHt1MeRoJfJIgn57aGgQ
TUDdOL4O8amRFK328AyynfyoLNY31DuVDK2P4nN7SseuzcGIA3LMNB8qNSR9Nc+5keGMRIm1Dljm
5uztdTvAZ8wbk7rbVsG52Cw0LyyjdBxbW8otqLurtZBQqecngWOts2it4PNzDKxZfynYDDoHxped
oAy0OGAXj0PlhGrwO+IXqtiFaHKbC7eMoFxpwi3+nl/GyhQ/sTgDdRwDyNELxFKw2JcbNKnCF3TA
HdZCTdcAuU/LTWg725IhFbUxoaXIBB+EX/9eVeo5jJ0PsaQ+8RZyAvv0JeNyzQRTHZV/fo80F11w
6TO3yP/RMe8WzCVKXhmUEMtxdMoJlO0yBImAuLJ08Lu0O7xkk/CACsHaG4hHsX+LUNdJlE+I/3wK
pWoaJyX2GqoszfCGpVeywl6EWBxcawC4iyIiP9xx0UPUbVpc6RFeSc00iCsDSBZwD/Yn86D67x5g
Ymkrm47+WOq3CNWg4cHJB12TX2Qllx0xMIJXV/uU3jTtHoLc8sU2WelSi9GPmFQFfFeKE/aRnXO9
sPL4uVjyQ9LjRgxaAmBh/AWzhhdK2AlEE8oJHHtNipVtTFRpikFSAxLDXPqj3DspsQFjMagFJ6Qa
GkiudxKAfINbqHyWMZBlwZB3Tcb5fw9WhM9lSK0Z9xLvWeOAJpWAfuFKJDNx4Nz11guy5mhkfwxb
xpObV/kRN4/UVeUEvrYAAMVa6eg+XYvN6klGx9W4AYCSUeUyY4fu+I6bjkJI+q2lupgurU2ooCOV
CeF9GTDyrc5uc76I+/yTkjpOzPcQslJZBJoAbYPrtZNPl15C04iCodkek8HDAG+vs27ceznVIH0/
84VIklzu2KbUXt+ucIkB7BJ61odvz0ae6G/mAln3F5Tp+fLBNUDghH2+Rvq8QcQcXC7pUhdtkAl8
LGhFzTrJoBFAUF/SVzSrTSIK7wlQK18PEyz++BjkD/fjdpVCU+ZB9c7/EI+8uLCOxhVJr29d/3+u
xhIouaMOOUKiQdQ/58x5Vfp1zwIUIdXAUE9mnCSBS4WIP1H527dWYPFq/LyMfEdpokzfWGjs1BqT
a1B1Nnrj3dAsHPO7uugOPXrPu4IaeZ+P4Fz5B+3cTPADYw/Q3zdGj4xbFH7g3L7AXJK5M81N/tTH
pbGdUTVmtPbzmXkgLMHOHpMbCV+zwZP0k2LULKS/94WJEcsK6UWKOiqqS0rImAroleczXq6Uqpyd
UK6JVaEmVeGj4fbXwbTcY2oo3Bg+Xa/MjqP9ne3hTEPoSQ5kfvUBC7LQIZxPgOu3nzFUIM9XdSrH
LBktB79/KficCBL4PDvQieJs2iGp3mdFKc+acwtw9IuNx8ZtWQ042/QFKw1rfml574YvneudKHIv
y+rVYx/4lT3fTvUAlwkfJBkc9vLH5qnT5bm2lHK8uMLzq1HrSXpJO3qJr6WGbE7A0udgelnUbPKt
h8IkA0OCG7FOH3Fj3ABm4pSSq58rVWE2YTuoOkh0oEG6S1ssMqFdS2c1XL4SIu5LtNGTIkO2+T4f
4VeNPJaRILB3antlKRRA8QJ/SWxSuKn7CpXmbKKZumx/2ns6gaNce1U0t8QVDOi2waGQX2HKqUPk
skkSXaN4ox7XDO/lDdeMj+75AzTtGdJGsxDeXio+ukJRbNw8Y7cDPNiMktdjwUy4H1qtSm8sKdJ2
jQx5Ani8Itt6QO/x1a8RwC73Z/jZjT5a16NqXbHfh82pMheCEcQNcweY3GDrG5u6LTuhThjo6Juw
PzGZ2GY/7JjWS1JJO424MaOICd4JGLvbDR4cZDLjABRhFignrkplgW2JawpK+B83t5LV7KbdhEkW
/S6v6JOegS+vJPpXIqjvUUm/rlFBKCPUivACQhu+LkBuW2kp9mJoOVSa+oSc3zGY+WdqHPpau2yX
jytHu0KBB9FpHnjyKFegw2Tf62h6/zcex0HMFhcZrdyPjs45ZZddZj8aqbQKfqmmlxoJqWkKNWFe
y/WXReMNROhk3GYox/1n2MMBw64GLYFbkNT/A89lKDHN/kssdHXxMNqVewFeeJxnkFPZhXHlq/dG
301HoXzoC/XQu7IWQLF1k+aNWXpXHU03H9Qoy89JBpCJTcOjoLeRnjDucCEc0HKsiGtaybX2HSKh
Z6Ygl56me/7YeKwf/F2o70vXr5NyQrvHxX8uJX3ZxI1LlEgLsllT4/0QykaCxxPSz8Ibj2uqLKmK
FakO6gM2t4ZoIcMsnSIGlZg41FKF+6GD9jxxHBNDJfz4nRQRg1kWlEZoY9Kp7Y6y2Y68lwbWrLzV
s7Zyio6oR/k5Bxoqs60Jlkj+teXvNODaJPPjOzhB+08fuACiiVH/vry7YRc5HvfrfRvyu76elHbK
hXqyh2u178tARx+gx3y8AxWBTcboAvnsn2tCJ+ECcb38+Q1KNzVUpIlFdEEIVX//Tj+i++d5rVrP
hoyN0BfvBmQa2rJHThU+JHxO1ZbiatkqdfLP45lY1m5oda5wjG8DfJFvC35XYxEKTZ2vFgqIMorG
cPViZPn2DAt7C/Uuk8214QHf2SiqOOqAJU1uTFKIlcyf2QYJ4Aj+5+fyw6es4GlFxnPrAfQ08u3R
zqzquaW9LGCox30btSJte6BIc9Kuf2yCfbVcToGPR62Cmb24LdnA0RJzTsv26NRBLuAIydhtME5A
8s0snwjnbRscAkP/r3UEQw1WL5RWVHrT5tJWMcZHpbTlmF4MqD1d/hC4sb4nauyBolXngz7ofOIk
UEWUgUnpr323flg2YNXvRRJn0rKlv0cUEQ+J3B2iiIR9RBd30Wr9AedxROMJHes4su/IV/0PrDbH
43KB5SCnyIiYmGC18JlEu7WQOQFV5Zpx+NRmbc4TsKmfwEzq67Cmm/ONs2yq5cFwcO2OLDfZlksc
9DsDvayrk5okseZqns1zWL7v1jxe73byB4CCw8MYp5KPjMiXUqUtYILUCNi2SfRG7wkmOT4YfT1x
CfNYuPw6aVU1GkkVfJwc1EV4hpp0yqdkaMs+BqqPgeOi2iT8PItc5NS2nm8gZqluH5VhiOKjLykO
AvfQ2pRCtqo6baaXmCp7J8uVVpM4jOIkoUBgAIzqXq+IbfnHys0aQMSsKRXUjwFxMs1c8orLKLPe
rpKPi4RSH0Vv8ioRsp7k9sURW0ChdxVVnMGs0Q1ATiXXeDdjUwMcSwcd2pml74Krvihf2lV9J/ar
jzSrrY2ghu8eoWz4X4obYlVcHjSvIOPWd4h7o/uDLyu36cLxtSzny9pAf7JeDSQbRV3A1EIMXiGW
k/W2gCHk0Co4jniqhFQpN44VHeBuHRCeMRp5Sd1bqWQCKPGpe4tNYLOgxCD5cJC/R+xkSv/e6l+9
VV5zbWvjkTtV42dOr2r2OqOjFIL9YOOCZ1dqSyLhrTqz0XQ5OAYctG6Zi8ZvBQBYYTsVc3S3UZgh
U+Ss89hhmHng+gUyAnkrGr6v+sTdKi7ogVmkw5Stkc2bqDsR+fmn8fEpweC8MSNuoCv32HoLLPQx
ygIn7JzGjLF/18AWf4yxNPyubYzBIkkg7+92v5epDK6j/K5Bq6uQiCw73xLUdRm4OqbbwuZUUHQT
oShhrGa2zi59JKNrj4pX4hwuY9ZVO5RGEQ3R7AMQirmJOAjKnswh+KvM6g3XlkhOiafaD02DSJBe
xdsFCQWDjfSwaJkK2NZ3COpP5HlHeT4q2ORc7Y8h8ClWZMBxjtuo0QZeV05+CDghzKWSBAhdoqxp
z8V3V6eg70ikdnEtRYCQhc2b20xd3j1CmDMd5Jk0qI7wm1V1CkY5Fic+6cel3ELmtLfViKi8VdHh
3HATHjBmsn2xAnb3P6yv9u96ust6Y01j12OFsW5saVwpy+09uUmS/iKgPvkWCvZL02AErJPVwj+I
OHmj2WTlq5ESVRU94XvP235rUOvjrlOr+gJOn/Wc/9fpA3QiNnPhuX0aEp8X7byRE0h6XWFxD+ZU
EP1AJ66a5iDTPtGb27s0rQBucQbGTxeBtP+80KHq+x17IaAWpCWWauS99kATXyvVLaVP5T7ryt25
7Wh//gDWfyCk/rQxuvRr7hQibt0mUx7npNQLTElAQHI2EkSQUYnkJLCgEmJLHbYz6f9NjO1OsDTX
vTcmRlt8HNOJvnAJu3TmzJkrqA1kD5Qt0U4r5xPuSglDwaOfIPhmJ3Ot/liCX63ZdQJ9xRFvfPij
pXjWGEOa/Ow3MC4kQ93a0aKCeWaUTvesx/KUQ4q0JwLRKTaqeiyWLTFbPHo2H4lumu+ZCwMUv6tR
Mp3hSk0KFSLN7um97m+pyaIMNd2TGNNLu2J+qngWiduh/EErJ3U82sx1KxmuvvZHYyQdZ1q2aH3a
Ie5IL10TYcjKwc01tDfb08N77ZULm1SDynpjdbu3fbHLMEatbKpgKlBqwzc540kmYLFqb//0eOKn
B245EBRpJLR7uZaxudfgJkIEP7b6+cVG1KSiLQ5JNu1L0fAt9S/PFdXS1GToRKJV2FgDmKxgmKRz
6pR5K+pKcyglu8ek6vAj7IH5KzHrHrX93un/KIeJJLEWS8xUbsFpUELGcXMIbckCpB1ZJdvwjxBI
1q4tVnn8E56tjmV1K0z1D331yjUoK1AvDvIVwg/KaPNvAW1EYQFBHx+Kj7jgO/eBBhEZ/3Trnt7I
lxyJ4vOcoRa08DYGuNp28XFw9CasjpT6gN0xbRl/tdepQLF/X8UTxRgiEMCkJdrmiM6pfm+qtaxp
YQJDY23Ynf5Cm78rGkRrE9JKC7PP/8A7ukSYqz7wQUwB1yYXBHfbhDA2uCQnRQuIgvDB3gST5+58
MBYCJKMhkETHNJMTO5tSggCdIF8No5bYqMuYA+gucmHrMU65SnN6MSBmhjPjgd82qtcdg08g2pGA
jX+ycYCZ/sO7TULi3tKqdcBF9RazbXu6PMEqwVeO4DJNyGfJoqhzn9JfiAjDUSSFzk/jwTNtiApt
jpjBrtUgTJnLadZnFIPUEzrSQ+CHO6rXJf59IhmjLZtKX18WJxezlfB8a9qx1G5W1Vo8CVwtudJ/
sTC8feAO2Aodp9V5b2Amngc8T7sbdLNUriXOo/jEetLx1uADBht/vWC8XGAZf4dBMCeLNFoA+n7G
GSgEU99/lyyrzdE2WAjQCJCs9zWK9/x74kKeAlxSURz1TqSGAYp7jcl80X+CNGYBvRbas22RHH80
CEWbGwEWAHWLovhm1BRYKuQXCeUd5nDmjDWwdiC79rzAtQ9nm4NDunVpB1P1q0vurDr2EeBRQPyq
jqYvAO9aOMHJvy7vPyKCgA5+OEIKbXitrA2kjcJ4JjIa1VmhU3ozkx3ZXQwZVdRfLEye8EEJrMY9
4jW2SsV10CHwdHhpE99yyAVcAsYnXioapXz80z4WEXNnFPyKQxJcnd3qNKVqzlb6Apmb0TNaUrBn
CBDClQOOWQsSIcxyXYQMlKuFuXqyMu46ejmNNwyKkQLhqDYpw+CmPHNZkCMUp8mbtbBa3EwFf+AA
RXYnbsKQSx877JFXv25iSTacF45QkYFbNwvEy/oxWW9kwOJX+BgGGMzvByozciFBmrrwRr0rbGIX
b7hCLgbG7tGIwCb+iNB/jPQqCwr1mkAxr6ACypEJ7VFTeERiFzoB6D55fqLXKXEa2m8fKr/1eLRX
PFJBEwrMi4PYIkDbNk0Jmzovydk1XGSFbPtZe5mVdud1GD4++IBNvHrda19Dc0FwK33vjRylYi/h
dKhm6EL2sfY90dbGjFJ0iQv/1gTyP8BinAm5vEEvffnGQs+ZB8g3zYIyjSQXRfHm8Xh6eg44vEkP
UnCSiDliiSeXk38yRO62eIa4cZhSTQ/DdppQ3zoruTPnHZX8WR3EZjtld5icFrEXOVj25owMLClY
bvtBsoV4l4GeLrvqOKdFUe2SvcLYFONDAcFCZwz4sDqBdTJdZdMnHSGF15RfSLIAVsRG7Da2Jw99
RXF/Qy52Za5CgLcfK0M+ZJGlm67A2fwdO8IiF7zaoH0UiJ/aVsghPYRwV2fnjFp+1t6aISyWSbrQ
YKu3zwbqVBT+GlKeEkB/CbQaHmwXnixG5A7oJyWVA5MKHz2EYzn4/ORzLAL1P2ETcJAhuFuBqvlZ
NKl34jQ0AK4GhOe0PDBdwU53yr+tzEbeJlLeQmzDvqmIleZex6hZ9kLb47Fm8aRA7JOVa1Lb5WV3
jrOsej78qExlzpSJUdz8AgEE9FsEuLz7qAegkHgPTbwiSLWdu4uT+eoZucAUpi0w17/vhj+GiYzb
w3qRsA+MJ9MkEYbRCH0rR3+F1jpja0FDHH1Py/arHCcX+UTL2Y/Xq+OVv0otzIyTTB5+KrurBNJB
7MVY8JzBOSLjNqzmEsjjoRApJjv7VNnMIsXTKe3tv+6tpjAAJchjFwTTCLWH5kh+7d9cbz5QT3A1
NpQBQ7vxcYf+3IsLOSqiXKbg+2o5ZOyq6FBFoR/78lfTUXvcLouAaCNpIhvudAiQz/FtptG98Xfc
HBNZFYU+HjndyAETUTB8dkgsOaMj/t9uqEUokNnKaaIrunjGuiocfwOTSZgeCNJgNgYChNSTxhyk
iF6pF01DMwvuNTGzwUgRNuRVWxZCg8vKjeyy+UlkX5poSJGTzPzJhgH0n3QQgE57+LgM8AqhDOqK
VhdmLIXecYfVnUCGhWhzpS/WiRiz7g8I2mHfjmU28hMZ5LCMMsXjndpCFk2pv171UiFgamPSwk79
L5yR330tfp8DSAtguSfNnDgp4hcFWqiOryXJykDv7y0KLI6bJnYNOF06vATpqkrxnpYhRrhXQxv2
rfoiHupBFJGz6sgcTke95+KNhZSdHmDFoJFIvUR3D0vpY8MlmHG7WkM6HDORKY6I3fxwJt8ufk+0
DLgC1S+5vwvEDrPgtEOxSkocg9G2RiYA9aVmRFJCP7CAx/OqX8XVkUh8LktvaCt1ONM8ZalXvEMJ
9UweRfgukJuUgr3viuEiCOJwe7BMZ9p9I5L5lRCwuFLqH0HesoSuHwwqe6KqGiYqZZ9u5fuVTlEh
j4iXMGM+sCzzySbt/AlKJKhxzT5vJKEuKZyq4EBoYndL0NQto9sVkQpn/NYzTNz6WcDOOoJokp7V
Ujmxo3bM9OIh7AmqK5iYXDWjmRadqK4SMLIwg/UIEJsHyXb3lQ4B4x4CXp1//g/6yU8Tu4oUnt6d
G/G1eMk3zrnLjk3Vqevh53FvhuZQ3lquETsNfBaXNzDoeRyRx+ALkZvX9g8qNSwG4BkjxM4emzZO
gMpjFsMEJPA7+K5rhGd4q3DM3Oq8pIS9rdBFX/7wBThpj554ZgK1CD0XPgYg2y/W1SGWud0sOpYp
7K/wgBm4nTGahpZwtVxj+fgIjAFxqJD5ii5Zlznlp6XH9iNJSM6QwPPq2UNWdsCE7uyPw5mC3jLy
4M+1dClNGIFzgYz+ypEANAYZH6F5TENuUia0Myf4k9ipE2dg+P56DUkLkcQTUmCetYUFwSrLEDII
v76W+GjaA/QY6D9eVwdEnjkWM532B4QcMAEC5OqAXpZKsgmXf/97/bFTfyuosZDcOPVEmAyzQfHu
bNDFMmafbfTnoF0r1cxni3upLkypbsI2hwK6HAwvKHesHY4goGwBcR+l3HPI6DgpV+s6fZiN+RDq
tG47bdi8wBep0HLXGdTxeb1AHQO2I0co4RjrzLiOaJMJyj717yzwyHA6eXipb2oHlQCrZdINmpRE
Oqrr+NxNYWX+VeinABp9as/YnfR1z0HrweXen/F6p2bbiIOZ/k1Tqfw7arUDhWAoeabijv+dIKXL
X7ViLvnxir4W9eMnurEuezKJxuJeblQngakRcP/GEzqsDZgafSZ3bvH6t69Fk9F3M7q8CA8dzTnS
P1upJYjtV/CjdFqL6XEhtrDyf04KUyIJAUw/dQfOBeAPSPl5SXl6qbCXwYISDkDLGDjozRtcDCxc
YWDykw9r0mBymsOpuEwwwERYYhkYXl/hl0Rr/qlWq40hAg/EqCqxIJk5UzE/Oi/dmM89HHQf+5ii
ifdBznYhB6udAlSxKa4MmEi2tETgMufxKhJ4ps8d0OEs5etUoZoQkgdlhejC6r/E75zRrgj56Wxs
xrnrSNtErtXp+GETOor8SvttN7F0Na0vM4IcDIyBAAmn4Ubn0Hq99zhCsBFIq6Fh94DThoAe5q82
90Ei3l4r3grvPqPlBeK3LH1Ckx+pLNouTRZtbjObmaUIBfeOV8kDpVdu9HK+WcbNPoLy6gvqTcHS
w7L+EQN37Q4N/ghuXAmv4tfFsc6JJ/ubGy4i73tfZCFuNuCL5x1BnbkuNwNQM1c6+XQvtAeGDQOU
JK6hNM64TS9at2FHAMI1CHEkioXkax3TDllYfQx4YdD0pf/9Ym5MWE94/MgBMfFEnUVUzX1Z6fZS
NruGJOc+Z+jlGIR7Um5iQsondwnJrYZdOrGJLaSpSK5BVNRd66jVV3Oa9wTa4zO4TEi8o64SzWQH
p7Z/VCMX8wP8RhRiH70EIG32yD/pquz+QA4zzKWHlGY1zBOqHAl0xb0oLUm+cfnmHnqmHDTfRfwA
J1XNhctG6wDon+oEI1SSew83ALXKUHwD/lWgp9m7ndn3TJs9X+t/oEWnP+TeyOAMNKgoXn7LmaSa
Z66uVNo0z8o3yt/3v+J6XqQDI3Fzg7ZspaAzwOJPL3O02ClqVQmINqiJm/OPKRbe/V+Tb7QEta3r
zq6BRBQysULFNMipOXr+nVz0MZpHqEoDh5ddT9BgIwicywxykHsAXwjl/Yti99Tr8u68+g00Zr3U
1xSGAsptRxf5y/TsUhZNLQNSEAkLHX0GfilhfJvQl1vQVbXNuoc741AEb/rtErpFlgioGo0vvcwd
UVVb01l2W9YB1f367H1WUevJgTp4/Blwll7D/uKXn34Ooblj2mEQSo/7i0ewZ9PE1Yh2vuq0lMPI
PFo9/i6hdHJtwm4wOI6iN1dKRQdTA8njmKO5Vnni23Dl/W89a7Tknsw8/y0i/gEpC1u7QWClJcKd
A5NJ0K+2rAsTTyi9Ki7Ql75bt6uqhCrnDhivkBTp/qW9wYKv+7uT9AOlAoh3KJplRO3+KN82N/c7
GODrg+wHog0KLxFrNXWfN33qDpu+DbVB3AkrsZsKLSOcb9vLmTQDuIWNT/xU1t8PIyhW18Cj6Ap9
pLl7vCa3ECOABSP9rJIGKKD4ZBMjiFE1ljEUy4mS92RKf6AUysCOd+pzLbDgtHaih7maFjxT/6c8
uxyTuShiYNB1fjj4y+sJaX2pzU3NAELbMmk48lvhwgkigfpoOCGD/qu+RjjXbYYNge/Xib1paHZ5
lMe5fJ8WwJS3ued46QAwTQQMXwABGJigyBVtUR8sQ/Pg3/PxR0WIwcc4IRkAQjVnS6cxvB1A5yVy
y9NAc0WAU7Ux9qUgwzdDVyndhSUGTe+BsE+ivHhMzU1pLwLfkRFQQ3x70AtjY1+4cF0fIV8qxgRg
9ufzeejm9UdpC1WDodmt2TD8gidqnk9fWnhtjVOo1w64n4v0tocpRg/qvFqG1HjhQioVgS+s+rmj
qHHCCrEPpY5sOl5pW2LE8ViAaHt12tsFDFXLvO1P1IFlMn85pqwAr8SDz5qYDU5NLv+qcdn37WeO
rjqCwuMOEYrlul7LHF2c5oKBY9F6A2wuP+1YWjWS9Xegnz+U0XiJeoEu8MGThebOfNeLHUkPrNi8
akOGS2lnIRjrzU25Xvj7Kw6DzAvke5VL+EpVnyreAbZICKN/w5m1mKEaqCEfm+BK3To5xuAVBthu
uCV3Co/29e+fw+03hMbBYd6LPS2RqFOBFYLRkv2nxOieAhd+v0qJxhjnvNPunEWCwSED4sslp/NS
kBn2JD8LS1LrjT13LLMoreO9Zvz00tcIlK2ukLELWTpchLNZD/YCB/Py53IRAwS4s8R/AOPPtTZ4
fk2VIVPIScPBZxLX5B3qGJdavZqij9VbWgrQA1PLR9Xa0I3iZRoR31E9ktp6TAZmRf/lWjY04G3d
JXN05/IGo1r3KgpvsVQ7Iy/94Kqfz3Dw7gKmWR4SzGbyLAKMwvXFm3JTu7YDEMBnjTXN37JW/UYd
+eeo+DxbkaWKd/5CnlQ+v8DGPZws4Xc2hdgcObpBH4CbTijbntc4ZsVIY8t9/h0sT/0/lrfqrehI
Q0fLjVrTPna+S4UJJ+OFhu7dUUf65ztfKqJly4pTtRrBQI4hH1pAlLI8Sz4ktVl+90Dk/vVFnKO2
Poxf5vjhTMjHSsTqFNOzIiDnSPIgNNNzl08YHIS8f9vgHwmy1q6rIE1kG5AsrplNb/aserTvwrZG
DhFW8l0El+/kPDzJaO9vLwoPG+HJ/Mpd8FKEnaesn9sWBvcAn2Uzg6H0ecdgrd2hzVxio36SDobx
oxBOUq0rY3G2uYpYN4F1EPpBm+oZvVtmcRg0GlE35szEc+QZoBQ05SEvPVag2ToQ4aWxptJYmMrp
AtB24oBvDPHymLJZCfG7iKfT8NwvWgaS5UcE29603e0gf4Ai3zRp3k3UMllq7JBFmDGNVslf7XQ9
VkoUuT2TJ8U339m6ZChf8A+1KVWlZCOfqXlveUSDpjF9hekHcO65edOxlRZobkJQK4gddDfyDeWn
ZLwSNBxmW2KlrcAJnm5889oFWFvR/hRqdZsNFwSZyoIPbYAWpr5ZPhsxIYxyM8McVfoKOXaoIUpT
fG0KGhuP/IZ3zxfYW8kSgAzgvi6gp6ObDbl7tQOyEc8wT8jeKOF3fUODjmLtPTA4GqpyEjmj37an
Nv5D2T04U1Gdc8/skysgO6OneIU25Ist3vaD7tSwVZ+lpniligI6ovvbKKsI1ZklgSRf8apZstIn
3HkWdMHPk5qyCH99DKk6X0DuqPJ7uzGrPMPa/H2vSe7MqlVm//9pxrQZPjtHKRetuUQNLfO7e0DC
QdPiL/rFeaZL9in1hf4lEU0BnwIcQyED656PAdd3FcHD67y66cD2c5AM4YpmOGUHz0Cwz+HtCjgD
8ZsgNdGrM5E3xv+HFUhvfwKb3gc35qQ9ypP0+dJuvwmbkxYtwhPBEHjPR/iMCAMhDMvQdag89Mt3
uh60fjhIBG2HQOtpVrJE8htMn7SJE5GxLrp4Xx23CL9gwM3t/50wodh62LRznaV0ZLyLRVYn0MY3
imn0VYhUOG4mnQP07wOIYGwsSuif2BUH2QT9C+RrPmlyb3+dk43YaYb3b1RH76dspz8IOMVf0d+s
CsxVVtd/Rbkwh4OEP1Kxlpw0eCLdmUwA0pBwNuiLBNjptnswx1XzyboC8dMMZsJ/CtKXoMDvF2kO
n90jLljo2vKxtkA7iRWPtZ84QIeZqboXpBJX1GsIAeHRWxUGHt06MIkN/RIbTfNdF4nKZt97Jtqo
+TuVli4c1C9BT17tPOoSix0ZcfpryQVfiSv9wjJhKPtFDX7oKxPvqWgCyxvXPqZ+bg8LkJZuIGEi
nVVHusnbVyNSwDENZThz9TqwJP0XlCgdCnYOuhFJlJZW4Vq4fpI42LxDTjyCmWJOm/+2wolKXWlE
J1xbjG86p4R86mZcn9FF+bu7+bI55hf5V2/HAoB9PEAxnObQ0XSvs44YJQVE75pK/ga7ldDLjFt8
wJWIC37ppfX3/ozrvtDDQkgjoc3CD1ikaM6Y0Yv/0Ct/2BLuK9sPNuTuwFARP5QBuEJjnIZsqsT9
JpBdnKhlBeiwSwI2IHyui+sBStCNu+/giR2k/arLBrUpcisJcSS8X8q9xbiWpJpjY8Xcc69DDVEO
lX9+RxzkYEzQbdQrP7U5hwWEXHvudnECaAI2Miq7Zr1a6oQ+HTQo+cU10hk7lRSHKRCoZ41iumzV
uo7MjJeqk3FYgMJz+lj6ATblMzI1r34MO+/LTU/jDFjkNYnW9lZ7tZy4M57i8WvpYHjM/t9FDoNy
ZSWGiaGQgsFM8Prmyswpdk2Nc2FmaHe71SyhmM/a6v78GCNMfqV7V14VYTZlJN3UAC7H4Vy5gclE
CCvG89AVB8BxCRv/omzThftpnJZh6qFsfbyysnasB9vJFDXtEydAkkJZj6RYxoyAZHtG2sBT8HcJ
iAntsYlxEKWIoLS90G3CqEse2a3+pTi8d2m0uX+wpMjJLLb4fckdixYiyzhqqCE+M1NESye7CYnp
EGyyQ9bq0LsMv4wWJtH2OH7/AsVB1knRsIDOk34Gm5l5a9L5cKdptaEwMti9pQ97dwO2TFY8Afkc
dhm+KoBMXXiD0CCJJTENo58gM1PNsaGv4Vs44O8gLy5m+GxTxrgXt3X068ozuQqW7wUMoMwiKwpm
z2eMZ8L7kNpb03mJL2yJoRVFRYjFywpRP+ElsLKTVfsbTkYdHDe8H87vVL7i14OAlfi5/oyZUcIx
TyuElN+QKarUfmnamGIxkEULvaGQ3iiX3Oov/yIQ9CITYMrOlxXzFyzYaYC9+oXllyAAfUy69LMn
Tth/Owxa2lxq3Y8wVez9bMk+hP/h8ttOdKYgBd3LFvHMgg0Po4VF/saCByN9YHApp7znD1dHtdgA
L0r6CjRkuc8tZtoYXfn3p16iGy24lo6G4OI3XSuD/bxuiExpjOycmLQHqPmz7AWCbLxcUUQBR+In
/e+lJSviUdAw7GLGY7hWGl/uS65Ih2yJYKnvdRGRxAr1g5E59v1EVU+7gz5/bQ7DWty+fDXA22H+
GFZBGcpWjV+Si5mTPmrQvWIgNrrmLDHNiIaOEd2uQbW4XBC5e1cVb+CbvW12L1DGXgJhFODNhJ4e
6/VmHau5+IlkDLT+xe9OZNuj9i/hrNq6nJVCpH/+O4fA94U+i6M35HBShvgrATULSEA/D+0WGsjb
wZXgPHeifQ9PvGd7uKCW0zebS0zEmpmeiRQCnl5VRphpk19BpHERtZc50y8dJ+0TOv2R/JLRhyiy
h270KoTC18aUT54bBbYX3k1ECBuoCZM2qOFD2IducNI3lFPJf0dUSUPfTAItattvh79kkPHj6E5V
zNQiN3us+CBLezMijrY3QdIN2vsq9wxJg30Id9K4dU4578WSD7yddep/Idv2gIDAH0XWmC1sYaKw
RqYTL1cFy+yLu9WrMQ98YHHdSwJo6kE2Ly/9OT0ird8KLxKyAak53DA8Ms9YnOp+wp1R+oB0FMvv
cOWJRy8aklVKM6VDybyTkU8KSAMswyWBz0VOirGDCuKITFzEZoP6Yq+gNkTppOYRSb9QOjclYFXM
efVU/cGZiRjJVrJuxjWOhWU74zL0Qra4shTp/CzYu1EVFEDwr26FHPEauY3RtM1fxvpMdoSLD4uZ
knY32M4YBmm5v+12IU/s+IKcwPu7FqoCFsu4a5yKW7k+Im7fYC48EFJFQ30BIALBt4PX85yG/DcT
D0dhNRmo/Gfx2g2O57F/Bz6uXqOVx9TifkhW95tubmocTpUsYWdeFE5v9su6weDNcHTpFu+54bk1
4Bh80hrpMFP0Sj7Npq1lF5PrAvyZyeeF4SNL1MeYGuNlVNGdoPdvSCZ3UPMvFiZcrXe3VeKy0jp1
v36wLSXA3l/d9iomJx9EvZOUzvrsl1xpg4vBrDS3lWQsyLXO58UFBm7AH134htAuv5viGdVkeSvP
HpFfDRzCF6o2ye47JUzBP9XTcVOA/kpB2zkKepbCOKmnAp3As8+KdoAA+4wCcGhf1WP6QaMEdcfx
UBoZZWSguVMCBTRYIKifonmYirg0e62SDL0uHCgvQvfCSbgZ2bm/txEWrMEvbALFpcV4nSJtsq1m
w1blK+PY8f3SFtOKecNljLud35cKTcL1UtDDBZq64nf7/HZGpetFPIR3nnOHyEw9y5T/r5eblcVr
sMfHD8nVa9gS1/Tyo8/BuszQ7xOPXSL465ANLIUMbe1s3A0rOZvpwIzAvo/iQ84xwHlHyyM73C2D
uTzMaxfIoesYdycJgV8hfq9g73+Mce881VfdQxQa0VM6qdnkaXsE9M5W+QS0Vc7OPv2mNQNxV+HV
EE4YBElNIsPPOLl9UmDhrnDDyFLphi9rahVKT+flQggQCRZ9pfq+Q40ScNMillag7LGrwd6YiC9b
tlb74kvKGm/7Ry3fsrHtlJPBlbKz8OipNVmr03i9Svq/JgpHwvE2vxW9SwDk/k31bqL2TfHLLI/A
uOlcU+Mj7HGc9Kmu3ud5wmNnMMtQjKdr+NTAwJTNYv2Fpuh/yZfipx4NKZ6yGyyXUZx+UUBXlRe9
9gX9b9zh+8uRcm0Rvu43jDmWxiGWlkmvbBDUh5tJFF/1zhiIkVKGCeuzYmVrhrLybhBBI5Aim8TE
Pd01EIW+TRhcbXgA8Rnrz1QCoHtlTJqj6IPsx80jy3fIDWMRZjq41NJjUwSQxQbrYM6/EB+DeTWE
WSF4s2IiQWMNEQ643PBOi4ZVcPple4ojnYkZf2EwykzpRcoziSARhUETirhy/OYFnJEFYVerm+ne
3wFyzHlhVlZud/so3aRcDHn6LDBg7uul+cbUp9Ol4wHhChImU5NMg1fNp7lT9dSOgoKdNq8ZYgk3
lX8fY7faItKD9YtQrENhoujkGBL+S+IH6dzAuCuqaRB/ioMmM0wenYB8qTCPOmRPGrx48coSva7w
TMfs+2/tkxqzS80nXYxg2X1rKwbYIcG97NYlYpFc7+D2H9A+YIPNJcSH4457q91namf54Za2lQc5
/D9XqEoukOqxAWdImu+jE/S+P16x6FTZswwPlXoWm6ulixcUm/AZ/fKMvt9LN7Bc+/g7BBq9dw0d
yHcbTTt5pxipJ2Ap61PPpMVSmSvoVrNO+fqsgTRIIC7iL4WiyCAFEkWBQJktz81OwSpaEgnHd66X
ES4dzMT18sYYRZqpmgR9yTzwQ/NYVM9vnHuj3F8SsoGdtVOILEYZX/k/taBH6AoFdyj7ndHQj7Xy
5fqAgGrx4ufuhZBExJAFj7L/H0XpfxQd5v5YvOoCVWyhlJy/SC5ypW9VEPlQq+z4ciLETbtahjja
+GZUFBmxB4dlcnhtoIyiXywSyYz/RUqIl4wcNgb5cDgdgUf+/K2h8IkMSYmveAMyaoqwOeck/XGF
0zfMm1tbwWRuRqLxHYebZusGJV2Ix+4cWo4t7GxuIm7jfmwUbh2zqJzOrNv6QwgbKwBTAc5kMowy
hQ64V+v//P8zpkiSKLCYdwT8ACpJ2pBqiNhBIRmivj1IkWHnyFIq+oShXPUq8QYVKLnXGjzRA2IU
DHq8jIOIb1hNL7iyexUlrTqBH3i38b/0Lr0uXVmZ4V/7sSTizCif8GQvRrVbDP4PqEuQjiJmE1z0
cqWdV4UCVDFIiEXqsvaqgTKRf/o8rfTtLmvB/rftgBXqndPcszZhSP/cWzU5c+/Uo8JBa491TthK
YK0bULTYePeFFSPxmbsM0PjYdfhip2DcuhQ93l9rKf7Z/RRFwoM6O/XKKwPTvtevs40oSw9em4Jz
btQx8N9L1W/bIiyVRv+xASEWjjs/xn+0XsjKZYc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
WCjKBNXic0KXiU6pjAWXiq2LTkKJ7NE3g8L6OgRpnuv5wFja/4QAqU+5Vd1hH0Xxsc4vA0Nwy1zc
t7+LfMBHzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H5f3TRBy4525jkh1qIK2Qsh4q/GrtwJ6JVADtzts1qrfqD1bWIkorepAhRIvwZZByI2fH72x5SON
7IfG8zLpYUlD0Jk3QCBoYlUZJGWU6RDyaY2Rn7Gz5P5HI4qvPNtW766wSe1harlrLePNjoSKVhfF
4H7y4hlOm6KeJFp1y30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o8NUJuTvvtHQ//0yHzk4r3ROKImbnyCQ/+GiYKbHz9Jqc59WPVQMPJDi7618B5h2z5gPFkZLVKrt
oYIDayRN1eDG1k1+njjd5YRIb7DTMBqPHvFVEOao9N/cefP23vkwo+I5wXkEITLqVM0RI3al8o8t
AaA6Q0U98Bzdo+Tx+RKbiBIBi5x6wlOZOehaj7m9+DFw+updOQeJ5GNy8AZn7ul0lsua2cRf0k4L
gE8HziSaUr+ewcL1uRh7afU0No6kaXygNHGf/nl86AGwUs65q2nQnVCcL6IPPyXmKD4Bn/J0YFQN
o3G/KJKIPhXq/LL9z7Hr7LE3J/cIaba4C+44/w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
r/Xe2Ci6RnICLxvZgN4C/9rfMRo5L4MeaOlVrWhtom9UNPVoQwQaTPdI6GiUuDDQ3ElZSB7f6p92
n6ZoBVSL1eywG+ntCU6ZxZ1/8N1sV9CjSBxGOexweAx2kmsTC0q7hVe7rZnh/KLLizk+Ny6alv8B
v1zuaJAVY3QDTrVCM18=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BA7JOat/rOFWMLmTHh8DUAZtAhABvlT31S3WaH9xRoHVRI5E6pFuZ9+Ecgih4mhDcxdjqSGbeR/u
24jHGR1zNpOF5SfM2XuvRrQQu9K7wIyXwPdbsyw0LvXT1RLA9UeiqNrt0F8qGcaPOkn4zXH8hSn9
09AecPGhGA7p6v1GpR/up+MJJxlXdQp3HrAGMLNTw6FmURWGfU6ot/fE9/XTH828aIEuXPQv4VF8
6pJ5XDXcni32tirZKs20tbT3Ib0XzlMIzD6X0wniGigh4dlmtyYpx3VFbwNcoV0FuVHZukOeq/07
9NqJrMCoOA/h5LgKZYIh1HETLValj8txpIQaFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 72704)
`protect data_block
HvIwe2N34SZuMjy4um7DVGxuUtmbgThSrTNwoGwEiJdlisMhSbzJPsSLzQyCVPvBWB6KRKKsL4Rb
Vu3IRL7SYFIFYCA0Qq7GVWGEpvlLVdFovlxeEyEPw7vWI0vUv5p8t7ZuGAgwgUgLWZwGpb4Wj8Wh
NY0Ig3CnlqX1XIrtDI32CboRq6okmEybBULmi2P9k61yb7SBFyAc1svnv57UYSBqImh0j1AzkSL3
wa7THm0mcJ/gVH1/KUyrhO1il+aaW6NHEGqWVwo74qZ5/fcj+YIKKJDeGiqH2YcLSG5NjtOCUbnw
Qi+LxTROphc9BKH5UAmjqDhnJgjwGvr4bQeqYaQb4SjNwDzCodQMfFlmK0ro8aTvXCg9F65L6/fq
7DuZcatrpTd3yP/baXqApZ5wPBBkqViF04/WKfDRQMsbOlqNTWJncXWrzKoiXG4UCp3CPDPI1ADA
J4IoqjvRDyOwSbaOvd/DRgou6ZW3wRtzUd3XoyUc3ams6B2Os0tjPMhgSshCr76+8KfYp9hkLacy
Sux+oKs9jY9iRaHGLFTha5pUjG9spPLty8CV1wmij25vxNiEVXbEH22Zb7UWOtcj9DyaSa1hjrIE
x7q7kKY7XnPYCLZ23ZasHnZUjRcT62+6/6DN7KmHAlEaspJwIZt+DWh8A7U1vMtZHaMtbFE2O3Y7
iQjIjy6W6P22+JSJsLUBOdzAyiY8cghioSF+0RXrqzoHtPct4n98w0sEdA9Znpf9t5pA/uSvDBL2
iOyRM89wsiLc7lsX0sihfOSjqqxPSZopH+A9h9ue2/G31af2bLetZX6UsIMrqKKz3DsUWS5jxLx2
uO4K2xiZYATkiQj0HpfZu/5QV3d2HdSUaKtqpNfRz0Lw+5VcfWZFoyYfZ0TDA85K3FoSjhCOkt5X
qnxEdhrhvJwcdP4HRT3bFDNzaQT2Bq+0qvhCP+3ZOskwvkpFPCRCYfPKKjMYd5EsWA1ipnf37Blu
P+B6FwUT4zhffqISQupWw3TQLYLkxjkHEhNe+WkTmmsJZUnWdxVsov0XpzAcnl/DTDNtJ2+ovFuW
vS5MsdjEPyPduB00/YvmzhVscA84PYzTTOYmcWkmjYSzuwP+lws5WScc40P/b1OmM6iAtf4c0rZp
VvXlFVn0n3uvmJnaGn2RIeSQIa9WTqypLxpT+BZH6En9xteyR8rIYV1pxEc0ciBiL/jAV9n5T0k5
fvUkVJZTXX+rWbtUg9+l4nYvDOHz9+T6m88MPMqocLY9yLV+dFzczAowkeQ5QYwNFIzing+a+xZv
Pxkz++cUzgMzeTl06W6wTt2ZiUgg41n/2tzqrylGQeM9VqUiEG7wCrsr9xS5nQjWvd50z1JDlsbc
XZ4wTJNrOMBD0zmEaRn0Nrb5kYjGMUBglMp7HduoiDKKRZH+kTiXGYn5btDeDwJkymeDqU52kxMM
Ua5JylcFhWPU0/QZSOzOFQ618mpAVniy7VKgh8HzuiJ1eX9hUbnNDBqI5+sFcn606kPJ3RQume2H
+YAsr15Lx5QHTXxdHTywTQc96QLzVEd+ZCoDfLy4Ita230vNXTC2z7eECslwEaytH4C21b1sLtfr
5XqqtMYgorrrvtQqTi+7Gy5tqz/yOiJ8WuC3n6rCzNi5HVLxx2lBcmoj3ck11xEwHK50HJHCLs8n
JWjh7ZyFXcnG+XxjfbJv66Q7WQUu1ZmqFkRdo1tv2iY605wT4E/Ffc4gBG5uBhjLdth8vbgwz6ZA
RRtecix3HrcRtApeT9szKzg4hejQoo6LEak3BaEMuJWHW1+RpPJdNC1m3R31OxYyz8uOz6XTCT0X
37wFk8mqDzVYvkZRZMXxSSMgW+/tTBr9J8Ydd+N8d4SJIlaUT6Z4dEKdOx88H5kAlF30H8nMnggP
SDLxrazQ2jQmdjhLK/KZ4JKgWPpaiKEvwxmejO+E1te8EtF1r6TQWyBYuNPbEGkNULWhO4R7Cida
ludH6DOYw7JB1g7LfnsGd2QuUSkIq4hSkPehzDldUnXi3vT7fG95Y24Rs1Sd0MHAm2/25gr952+p
OEN0jULZPrgA6Wy6VgpHXNYAtOIJhXgWrp2Nf57JhizlPfOy1Pcro1lFHNWmcap/4qKYMju/R7K6
GlUTWoUzIjK19xBpBj057nLzgeOTsPvmAxpJnpGyFe2QZgFs1CiqD/9SPLFhgFpFvIujjVokVuQv
Y0SW30jzxOyRztwpB3VmYHYbIWtp7IDQkHEgypOUnIvYckMEO/2gfXT85ap+CcP2xaaMSS8qRK6i
KDBOyMwHUFSKKUvAG6UKRulCPv36152OGtsh1p+qEPYuHuYz2YHhQjAbJwovXPxLIU3qSHtBp8Q3
yc2GWHdqA3P12KMBh2LyuB6FLahJbJu2cTsHXvtXfHXiWrr17pWTXZdqbJPgbxv2jRsGZVxV9TyY
7lRyR8Y3BiPwHIYd+hXW2gqNAbPAXEHzEW/FLTfzU0IEh+8un0KCVxWV+PyVOjiySHksLyZvAgtH
XSphfYqOoGZedfxOcsK8itSk1ADQRdw/hHld7+km0JITcpn6XxxASzJAe4H2mMiuXzmv0AqopF8Q
dn2hMIc1vM+o30ll48q4nzjgzZeDYHU6ZVNTqfMAzTR3cKuj2Fl/TsX+MKLc5v1LF2njBu9aaEZy
X38BjLVxv2YO1/oTbEE2W99LCX/hW/VvpGmSx3TSAWbClged3p6hKVqvXJrGE6hSeAbmJkEBf5UV
9xLSafDYk7Dwr/oug1ymI4P2KbJKuAyPMOY94jd3Zbb08xCkTgPnKXNMGjsuU14Scf6ZQQldfv/X
Vd5uymnNA/wBuAfE0+w51MJz39YGeyyQqzp+ABKGtvX1gcyGH8g37lskc0GVG2Kuko4x+IDCgmOo
tdiIPZWz2nQhwO/4vZeZ2/h2k8G21seDc3LmaeBgdDtzN4AczOgKoqoZlxiqh9XbRUQbyyUVhGEF
NRRAJbRIDhE/b2bdPrvlDrU13gXfceRigKLhSBqwrzdvhVu1t5VHThFl0xUMVG6DXaShN6LFBfkd
qMELJr5yk73mHmfi48ipz6ZDKL948hxDZ5mRLxceIYnC4G6Zvi4LpBtIFUnvtTU5XR6KbYTZNK8D
pRDt1tgs/oyKpT3j+oJOb6s4chzqzeyH6GA3/tNu0pptqc3PDRfETxx4+wq1DuudmWuvmAZ0aPdB
NCAsKw/QOJZEsMuJ6HXwdee1iMOKoPzsdIeFEmNt7XhRkOfamcXv49MHg10jX/lQ67Kfni2xnQbr
4reqFp+uoHm3eA1qOVCwJqjNDHp1WaWtSiHKH/hXz8hzyxxgUDc8MWMD37Wdb3tjHa1nggaLwGLi
rSN2SmS4RLT1AdAGlDAmxM+N7fJMoeD9aSFhQn6SY5v57Om61C8nId5zRNy9nVQxwJehQRaWF8Aq
fQGUd25hYUrTkKGV38LTKfhJeJL9dsCGZNA2VRoL7OWx1ZWNkLrEEAFjBa7TV8dwE0x+1fzcErpH
xQ16Lsmia4F9S7CxGcAz2HfcKzcNN6gt0ah8bg8asyRNgbd8MgnANmIPxgkh6lyX/KrjBP78nBiK
BoQw6t0yb7V0UGt2AfFBXTggPoW4cj3iiaaBlCgQT/IgrUopBb9Dok3+aWBDZwCDQ1Q5iqjyJ9pD
KY21xP6p2sAIGQ5xZV1L8lMQoMSJUXS/K5kXJ5BvQ6Jk7CqNXhuxV/wAflZu2vkP1asiBCBF5Ye7
s0byJmevvnQTPWCBHdrGJ6pmcurXwFdBd0BUm9krKJX0e+ggOIDrS4m28IyFCL8k9qBJZ9dyclDw
6GivtqpQ4tAMlDUr9VIEb2zUoLC4hS79W/d4Cgf9SwFGS2vcOZBsheQvadMRMpZFQQMJ9wxCXEFU
H6rhaxKzg8E6iQkFYAtxSIxcu2lyfYMFk0F4c6+4vhd0c3Z6oLW4PTn5hLYEsNOeYUzWPawLVGhN
YKDfkI/sgWtWAUFNCWwBb/kbnv0VClgQkaLJ1R0tbEMZJjoLVFfe0kjclNs5uNhbM8wDvcSbMiEq
TMCnnQb8UtEc8uriFBmwvOEezo7AL6JbxMFZ0N1oKnDkST57UCGqMOCfQ/isGpo3zjTk7uDGuITV
d+GVfw/T+U0Dcy3yqdTiyg7NT2fWEHiv3Wj1KnKKsxTRTbpDGYCxP5wHzQI03sVIB398CoeG891T
hI0s6e3pDFks7YgWvv9M0a6d9So7MsQddPE1IwjB0jVYbmNLUkU5d0BQ5JKdQiR0SL0vMH4mvwty
KXQvW01pzD/nVo1TWzvs2EfoAMcU7hoIAQhSpXFED8NKcuPLR7GZ9NSqFlKOA+Hj5Au9F7uXrS3v
XbNXiGOSbQknrXKJs6jmU6iDxESydyyhvcN5SgmrdMmZx2/Mv3PFYJhH1PAvsdw7X+gHkzhugVDe
f4vgZ254r7LVyo2qUwGAGQgynV5GBWYbRWRrYn9i8bMhMeo5s5FtiNvKpebRQRB1jccpKDqmhdYv
HtT4onhN20B6ChVUOuSYbDCC4ydVkiI0xNIOkhL3NWhXVvuJBIn4o8ELOsiLTRbCRhb0PU/07MDw
+9BpGfTrKHBeXstbnQVzjCc4CttauKv59t1KcPKmkDN8sA7EVDXh454BiEJp8VWbHqonp7dqboBs
mqr50B2lpcfUzwbCmEVTdBiOyPCVKuNkVFfcMYIXGvqt09c+7UHm0yYdwF2nlS8W+3j5VtpBp7TJ
Zb0xii99XhH7QE2CpCSj1x4he0uNUIP6enQ4xpqAlUTm8dy00jBDayQIi5em4F0nc2qcFwUkVlkO
z27S/a/MgSzOFp/fio5suNN0UOJVyGfEKBlwEFkzYFwcwgarr9niXRezbvG9E0cNGHSGMBy3t1bi
yJRFlyuB03wUPi2NY6zPHn5oqFhBkA6y4jpeVjQuJW9CaJrYByef4li0tZDyRjaI2ySPOmtgcSt1
Bv3rSwR27hQ6+3cwYRmq25ZUKrY3tpWjoUYxb94H8LuMKja1O1r0MpaNJ6kUBKP3LGgr1YHHb7IO
irtEqdKhpGd/Wl4Cr5U6jZlxN6N7WDvkP6/n4VKyEAZa2RwNRP9DxlrPEQDvcc6nZ0/lXMJpBuke
XbRfW14uzqZp4ol3Ktw9QDZqTTXmtdhroocX3oCm0E/9BIBYx+V6XKjMmeP9SVvBNFMC9prncNqi
DpOVWEpTCZvVCyLiRJ0qx3Vyk5E6jc/hBPOZKfbeyY/FIgTj/4QKptvZH2Ptz6nfMcfZdh2Ucyq3
We53hmCbGSYVLvUzFD2fEiVlpV9tSFm+lBicoyXggAbTbNnWyMxdI84UpShrNB8nYi/EfKSHy6sk
QVc0iPgqy+lwyoAjFcgNfPmJViVNFhgAnhZhDY1iQuziensvnjPIO1AGRHoZPOvtpwubJeUM5jMV
6OeN9LgeJ8RFRpXnkQv1HJlkVuo4wVPuvEaph7eZYesqM3s1CX724Pmyq9MykE4zMN1ow1YUmIJk
lrC6txSyBg7OW0n7QzRlAKfimFh0SbgZCXYMG2uvsupyf6zamMXHM7O6y3zkB1ORd7pIdCll/3Lf
Oi9YeQlNJ2o4oiljEPInuwhktLGjLpH4fJ+uWo4fvfue3hCWesgTFk2NmwT6zGeHnbSSu3kGaVrG
OX8BLyeoG0CMskQCw9YbJRBOHtI/b7dag5JRUxqN4R/bfHDkpfu4E/Ik+x/aF5mGffsZmE6pVK/4
k3M3jIlnIVHLXXQyicE8UFo2c9VJoIgR1Y30U8vRzK2d0EKAHCKyut5hKp5KytPVaa9QaIvEUDxJ
8ydYsQxl7Y2AScybaztNKlyOOB94W1IXpVkFsSEOE5P2ICh2LoDF6qk6nYsOwgQi/QrodM8aA8Y6
o3EuacF+HCN0A45oiukQN61HXwJ0qxHKVJQjYs3HZSiEBh1rAcHyp8ylj3xUyEdbKmowB+r52M2U
2a0CgPGtlwyqFE9qku6kQ/JC18nhW7CZvNyUmbKQe6J4VIF1G6mjVeP64ItH217LsQu+XeQyZ2Jx
glXpXmZKcDu0CCS92Jd+3cmx7En+WV6A8x7OJP4KoGrYnKW2YGwZTVJoKoqT3RYp7t39QHBcbjDd
96iTZJ5SJfrVbvbIA2NMmXcYyL1jmYnx9oAr1iGKr4/zQ+aCH/Sowet1D9lBI6cg+RGcSlcy+LM0
1AiVzhvLbt7KOtAYZhux7dAad/2+lw3IBzG92c4FKnF0aMp+iQIn77K4NPUwSjR2HfP7tPmjKST+
d9BTe9YiGJjgOe/5N/eZV6voCC1DNPR7yUyME7QuhfXMF+VkFfwQnZLF1g2nZeREbCjdJaSCvmt+
erBvrerL0U/GiGDtZpBWzBlbKL6kA6hyfxppJ70cPoccfYQnYs8QTyFzaYZstGZGNGcomQIUQ/Ba
tA/fBEC8472TOD2bzIw2/VMiA4YHnYQYMqLTkdi5Kuxn6iyiUDYJamg67gmyOSfVwFTF3iuc5L8u
SGK0n/FoDZYtFE0Ip6owY4tt0OqoJhDWIzlgKUhHoYsuO0rhRuAwgZHmwCjyH85PVkUoALJqTWlK
mHc18K99zEuFST9hhrgUZUdHxULXvy5pTNoTvfFZ2IYvmiX+rk7n3noVKgVLDcnzCnjKLN/ShqyG
D5GR4mrCP/rxxl9Uu7dspgTrEkl5FfO423Y3f+9iiFYekUT1rEmvGMXanhKsgCQnGo5yAE+s6SmA
sSvFytmH1lNuUDwF+8L3sw83nU6sf3fISSEW32sXlE4zdgXje6kEHoKVShgy663x7S0R6M0b5CDJ
ecveH5A7XW8YBaOtZuAD5KA7n+ejiYi3kqrLBHWEVBKVty02KyZ24RxC/UkBE2q7OpRQI31iCSFq
Ht9ifWl32SSmycQBc/pyAORd81oyYEj22zvvwYS76CICzX+B0ONl0PAAZEH/ffwb5IkHX8bFW9eC
tfwXvZyyrpma9/vGrfoc74YNALRYKZETKW67G4mtfyAdPThR5xf8EKq0/xtDQvDbXMb97npFyq3T
bOpCoRtMgfvz93JiQfC0LMpzpCj/w8RpP0u7jaFjgIIy8NiN7F68kP0HtA17COI5+9C7AU4iw0H/
ELfzjUg4DViEtMlvnL/D6fFpjtMbjZnwQ82QKaWy8FrWA/Je+elbdepn29k3pJe9aKgxAVd3+wZE
kyV8qkCaYFb6GCr56bkD3N4aI4GZ0MCB1Dgvjyt63otTqctSd2uEsu6IW7EwM6SoqB0Ni6vbMcSk
8Ngxtg5HPXK3f0EHJZNxdOOEG9+J38vjXqWhCyUGmqhCQz5+uKS2IUKF3YIhyS1qn95RuvBm7PYT
ehuDzzH14/+pKSdQ0gHAH6cUikCGtKWGUFuj6See6jywBv2C4Q31apQKA7/rvC97BIi2paggmgd7
iNpgYLDTty91dv2FkMv/DP5uDjTykeqSMj0FrOqsMuvSPAXoFHKBecKsDyxK+ZCNzdOhD1Q5srEm
DOWCRK5w7tzT1RB9VXiim0/DqFl0P4Fs+lJYanN1Qd6fpObL9IQR11fGp5C6IutXVRBGGn4HNbTO
5P6NpCoByNHxfZ2ppans4Nz6KsOmdfPCQdp6UVK40Eu7gtEmn1pcVqkimAlZ/T+bcQQBIkWCdMgR
sEFrQM/uAVNbVGiSTqnzDTopXsOzZ680K7mdfR0YwLKNt9x3xVEM9vhzJmzln3mUDl58ldZfLgFv
WILmz+qw5pB/sQFy0jkQyPaQjobPOnkiVbgQkvQUD6mkJXKFsGQJ24GsJUTaYrEb4EyALETP4o5A
f3ytrUFDHlYfuRxz9yNU8QdYs6e2+87rKAUAFg146b3hL3afUat5ZbU6wa1XwP/970AyWZTf1gRS
Ct7bvTvckA42112OtIQfq7Gt+DoihOFVMWb4wyVC5DKXK+QBBnQDVUE4q0iJHl7k122Vsrjs9+id
rCUfrRY154uJf2SuBplIL4X5vECnLUREMpuqnLZ00pJT98IyCPMvJtQtus+gshp80MgdoTVxb5Sw
Rlo/C69GBnz7iRyk3wdybLCONx8PZvUjiG3DLLtfXULPKRUsCmk+ppgQjtvKtPsBUyugdUnekR0Y
gozZEiNS5mRvpDAb+AVMfLPsI00mZzf/eUDD9RFgJnnqQEesuebHJYduD0x7m24nNVoxfZpLQ9kr
Ph0WL7tuP7gWeIhMYv0sccG+XrShoZ/r5M5CJ40CmLbedxT953SGqnS0dZrtXaaeYGO/464k9waz
KGi87zDnxoRwA3E2JXVMIhnTdEBIcqSA9kmWPnuNeL/NvDouPBDqKNtb6W9I3NbuJMqHZ+EMGAQ+
T0hfH957EsVE1dxOTvsOLqnWLkNF79aAuLtUPKrdTM34STEBLjhPfkM0CxTJVRgXfI+riH4jDJPp
J0yTF9+CZ4DJ2Pj0SlbcGsTLalg3X06sRYBK8G/7aB3G9+8N7XQkiRndDvNLr8ayF9NqpCeIigjL
u+syGsEHU9GCHsLjqLfT0ZTxJHDT9XXqCgV0xX3E0oJY1IMojlgqCdOS+cWwzMzGII3zlQwfvS7n
KxbW0I4kfhcvqEQofZkb4yHBTQx6nY3QkzxPDW+dFmmW3VrMJofveXe0uQ0QE/PWyNNj/Zcud5LR
SiyQNC8gilQU5RRTxUNcZN4SVzFVa5go4lhFVMXoTHaCwezMz7EzxH5vrh1nMAbaam86h5lqliGP
19k39GTRg/iVKmEtjOeQ01La13ZQLdp8Oy4SxZd872VJowdVjKOIQzyXy5di2jkiGoTsVPMTGRnW
BSqpgWti/mhC/kTrmTwrGRDB9oBvNbfwr3HSqcRG9CO9R4Px7V0akzBF077ge2jhGKYwLETTxqXN
fzLjFvQd214Vv9FuuKjwHp01UpDRuR7gVgKutBPzj82kVbNv866v1YJACYdkqxZTp2dwBFgxhHZh
sQHRC5QiEp/SiXZEILSROy048rh906Tfm9QYFSNRKDNkid1VCGimBOPjgS++vLmkv3h7eRZtFX2M
iwi5Or4A7nCz4TjMngtQPh3Ll8l2EX9uudfpQVF8nkaGzZmPZ+LoPAolpIXtiqHvB+hrHTRJ57Ic
DruA3qYMPH3eSAG7Xr/9wLgS9Wz5FwvGu2kxV5BT8vd3fsZ94PYTLcfRNNfymMlp9zrfQkOD13wo
/E6PoM4fM2NhQ+7ztx1YAb9bJ+NDPPnC2u9ntBC5XZZ83Xc/Pyr9pVShrd7F8AmF6vIygKTGO1HH
3hM3By/7S3fEcq4BtOkGKF73R1k1L1eilN8iqVlseaxmRNF/WRxLWcM424/+PHSQfTpdRDfaDfoN
/nvCg3kmY89muYRJle1YRH+t0seGJubaC3jUJym8Z56xhIWwwxosav0TnScVgUU/RZKMcVcNkmU7
a8WbtR6bGlLcyIESGODlb5734KNejF8BbFj+qNipIW2E/+W9al04m6WaYhXxhpGMkbEnpZC8SrBi
dpBEKLXrio0WEkwvQdgLQaDJbD0ZEbeKNZJeAqGS53N7SiKImKqlj+wMq3Bgc0HbeF5Y7oN7IvUO
ArNFhnHwg5gf1Hnkqn4UN7oLeoClUSTkZ1tSibhQVzZThO+BxR/wEb7qNLCDWv/MhnbHxNEghtS7
HN7qa38eHjYl1H45RafwBRAIOyuB00ipyboFzSPVxtLXJRt/kTIa9jYw/HeNrndMhsuSgpdWHHRS
kcTOg0Z1727nyFFwO9F/hxpDcPrKK9ehU+1aXft1dUD+GHa9d2UOTJkqBLfqHOTDUuhqYuzvfCsY
A7Xo8S7bw3Y5IpnnjYrEf0MabgEQryAjfXe9NJfAjVGkBsBqU5S4xFP9tcw+hBNRZZIua8A3Yvxq
RzHfXTOotj3FuW4oKgyveA9kR1uWHYBaYBZvnAWFvkt8LjA8/oT5WxwwPE01gORgzy3nzDyO7C/3
LV5TY4zVOdbqTYJX1SvHFzNgTWpMc4jvJ1L8juiGRQRUWMxlMM6SbL7SXNW4XsuKmYR6cwlzqUiq
ARd7WUqE14jqt1JqGtmsskzS74P7Li89ss1fAUONlhSCTmgy8MIMiJDuISWKh4gx8AL0FVNZMihN
NU89dk1FgXtOSsmNPS+hpc+oMr/RLYVSZ/xLGVMgjFZLDP+/2L+G/212xJI+n+F79rBhGTlWEI/I
3AShC+Y2bmmwc8QNP63HDQyKyeYSFs+z4lBEH8rccVkFTsG61aGUwi6WZmqZHB4nnRrwwDljk/mb
35Z+9QnYMLbV7sTNxR5XHqKE7CWK2FyQOZNvNkJhXNg456ciDZaSn9h82WwEtJFiPZIvT7YIPM58
ohCPE+rjrMvykD9HxwoGfhOec1sKblJnb6RrNM9SCcJVs9rsGm0X+WYTA1wuThLsxbu4Zhdr2tBN
EaFbaC+z7JEjBjYTye2/DsW2MdT956+xLMQulLXcT/kXJt9UVgWsElxkHQ4Ws4xdmgDwx8MzVP6z
yncHGkHsAVqCTsCSbxU/9M1jsZAKFTgs0cDsT8ST2q/Axu+e56SR1KrkFW4bCXSg0rQFTQwLaXdw
h9/lmMkolwBFKVT/8tz6S5EOKca1ihMBTXjbnoezPGzs7xA07IJ0hh3GX4hm9hF5Dk4liJdNUWaW
AsGJhKbQAa35ylAFPyV7mb3dwU86urMJUa0A/6Juqn5W0z3g2Gng1Mb65SkiyO4w3+mHYvql3FcC
ETvhSdbSj9Ib2mUxwRPNEywd6jbh1zsx15t/iBP34zE2kycmzNkaPYS9sVT9LQSKvAJjIjxGZdH+
SaYGZF118GqrHYuFLIBlthjn0+01ath4HLeoGGB44TLnZr62ngRdAETBpTv76r+GltbBsq52zp4j
qqLWR/U6BDcYqGh4bucUgw8v+TlYMrdhsuTPzBxTIz6Y11OxSkZCsM9n8IuaVWaPCoWK/LjAD8hO
w7O5YWfWoz/RIQwsfajhyrOEGvKq1uyqg+dMd22jIDSvmS+udV0h8PZ/GsRevOAYJtZfNApo94Or
JKk/3OT71MMwiDi1WyM2C2IATUqp+GY6J6E7UJq98EtBnD4nccODm2suipwESPSb28Abg8ld0EGX
UKDUVDoLRBvv6LXc7iJ8wSipJSL/6iqIhfRRaLZJ8Mv2wMiatIRtou2qICTZYwYVdg3io8HPY6uc
JxRav3TOUShkRuHShCtFwUQDZchEqHG+XxVFkzo4z0xhrMNYG/tZ9lMsFG88sbytfWoQgOxZ5yol
xghh/ARhf6XOO3lNIWSucLcslRt3O6oN+TyQWQ8PwHJcFxkZEueucIUyDV6U2fua+SqSrLlakaV6
O6+/siur8wwmo0m9CGPPFZsyIkDjhtJ3oa+NOR35YwmCGs6RJF5QlJpOO3OE/FoXHzY1Tc2zwO/5
hnUrLCuUHL08AQ5HX6N7rAvVBp61T09ojh9Vw8uUPz2zbqa6CXD0LwfJyqUVnhh80IkNMKwtD3b5
D5LVOWIk3CpogLyY3NQnjb6FRuhTZBO0sH7MtFCpXBtCVZFfGkUZN9/z8hmsTdt6lp5egXcGEOWg
66hDCyuYepxuRiJ2le3SIwBOL1GHZPp+o/M7DSjjdZmgQqVfd7pdwIeolDdzuQGozJ8CNtmFtcXm
yZLpi3xZCeMpgEvOQGVk+QglNhyUEyCBnkoGMQcbVILyhsEYCjO1r/aPu+6YQRzSSIJVWb0r1urB
rOlXry0nG8vjM0Eua1BKwZ1OJU8TJehY1W/trLzJKdTboNyh8DebFIF2M/6SONEwO2y93Qc7JKmw
SvP/pZ8L3TlHJ8IeqHPpF7tX8Syf1AobFxITCFo+pmHis1oP59A5yCEEx7npx/7cMw8XHKqSN7Ru
GKg+9GMi1UxyrD/mvsdcc+l7s2yG/GJZhtbeHUeOiNwJPUwWTleYwhqRbsybI2G20u9gNqJCzN84
fEyr6bqxwBrXlYAlZrFd06RZrdbUOwPzpT57GsKs7eMWIqp0zXLeS0wHYOtTOXy0nF0CoH/vNOtC
BLNsEr+o1ZT38xBKJmv/cDKDJCGM72vIVAxwDGivnvGO/bniWPdKGZx97gYn0U9Pw79Ox731zl9g
aQBrx6dupt9kZ2sINFU80eu4UdkAdsUshP4Ddj3FoYnckwFWjbC8yweJFxyH5lxQiMaBoxCNT5ad
LdXWxs8IBdsQQFbBphF1/RhFQdO+VUONlPiJRSAKMZ4FLS2yio1h7OFZX3BVmufTYOtmjN12Ftqf
HOMQ9UZxGxrV06GgcODlMlqjF6Ge2oYcdum7TgWaLh4wWyQOydSOOUI26tL3C5NDknpXbTC1InhI
6qAXR1WDG3YIEDy+SNq9AWPzqbPBWB1aQt4gsmLIfw9eWe1UdyaKwsIrrdleJ0pHsVirrvMiGFUi
0dfwiSmnsbdL8DE5mJualI3ug6qITkGNqqe6/+cmxDzmnFYLNK8tq2eN9/Y1Rbmm5+VczgTgkeGA
LCVRJQqI3YkaXFDlKt1ZvQAmTjw2iU5Q7o35uG29lCilJfzX5rb/2g1oAG8FM56N8Ntb3a6KZW8X
8roMuJj+01vcvZ3YUFpzuZrEVGE+nAbkULquEcrkCF3+fONxAuQLGt2qh3TKRwk2qfwlcgVLao2m
81fhe9HAWgF/pAkzxtSxYzUP/2XS8Om301CgZQpFZLhzXgTqy4ZE3YnmvTLgQaDWUWbhYynF6EH/
2W0TdRA4aZATgBRuC8qtG0vtxDBgt2owVRmFTmwSVDtK764Db3quTQlMfj0yQNncZ+iM93MW2eCt
ZiK/R9TWbSKnXy5LFDLgQ9iShJ/62l4TcmagmzPhFIlSBp8BlzfDwGrRkekJTx8rMMw31q2b2lSj
VcItDahuerwTsf+4vQSwScrJ9L7ulGaustR3do5/3Z4v7JKTyvFSkOrsFP9ckJ6lmQxlPgfGaDWH
t05GM37syz2VdG1VvrRbcC3JHQYhWb9EbKsKEP99xxdl+//CPlW8jouqYFl6Oio9wFGfEN/KawZB
NrucvLUWc/PS1p+lSb8hZHIdtp5Sk3jmCgonyZoVcU72hMBo5Ia2T6zToa4WoyvW0l/usZzLqRoD
CQV4WuDjnQiAVjczj20wPNq2o4xRiLQgiN5MtSN1vuJLOjSowphaK/mAm0C0u54nEuejSGFSvQF0
FBD2TELfYi6vP9tyzB5iiz4JFk0Twmu9cv7C1iI9Zi9Gx7/n13n4eH3beQLr/anVfPoOtWtvo/IQ
1933lVQN1vovaXQVn1yBOUFtB6qh2yVBsyHCuLUryFlh+SHlweDjjqAXASGIaRpb4zILanLUuqF8
1Dx0midw/aUsKfyRYKZgHAiRXkd1h84apmZa5w8CfO3WQUv+N9/9QVyCXsFmaUvyTGQeE5Ag5F2+
kOymfKmYZHW0Ivu1I/u2uZys4eoZsQGcIm1jqFGLCakCw/CwzdVtcuqdlVzZX9JjtnR66otRgqgu
dJB7gtXaA0l99oaxYDH3gKXmV8gAG6RBgP9garB9JtxRwfljxjWV4a/s2om8ZGiHXpRM19lQWBYO
/uVCyHm6kT7ZaRAY0Hc87iIGOMbhViCNUw9KjBRWDKmN+m7CGr4OwaB0EiTl7s+XLal+xC69ZlHf
3PTrbd8dEkPwNZw1ck5EJYNlMpnAzBiNNkcHS8JpYmUZGYR9s24fPWDnOVv/cYOFX0N/+M0kTG5F
NUgo5oVfAc09NlSx3EUuNwuGDvzHZ4GM1V7F+ZaLc5lfkiyyQMU+Mgf8iQ5927gWpA+aVYgNV2Ju
OYcqueUy/bCrF2K2XyRi/Cis73j3ZS6uDPxEP7LCSlgurHAtE85OSj4Y7LA/DM3Ov9pqMJslXEX8
hnzd/8fgoh4B5upOTn2DUGNw2jw9RrIz/dj8X1+DzmTwdsSc+ZbzOO1zBo7Qgh+iP/alcP6v3uZi
ZXsJUPBfXXTldjHU0ftgW5wQduYLHEAzmwd1gc8FHkHJDuIZgP3XkjMh2owt8YiEgC15EBZstDGs
yd3mVlDuT4dUk+nd5ZWoGVSlZ8X1suxJ+JLmWE+tss0fkxaQdN+87uxsLXo+Y6FveJOwcS4ERkjw
VritymYicUjTE6bfaA5F9pfhX8/WEvduMdUp0afRRbjm5bdfoNCpA1VEQsMAzDCU7HVWFlTnvhrq
eZcQmxdP6SCkvJ0qUmQ4hDZYLLKn0Zg/TyKhvUo+PuHLY8gJLwdMO9cIuOHjxBWENhv+hfpn5aYk
uKMfM4dojiMtGYKbx5jhDgdIKF5BbvsM1zWsfb4q6xPNdPzzUz7P+GoSTeZ8JvGsAN380+D4ekcv
hjvJ1l4v1cz7JJVQgw80KS59oMIuLgvEz6hu8Jmrm/Ehy/+z6ZoboTq98Ahr+FRSHl5rjD+l+s+T
JjoXjygL7QQb4Rh56Y1y7I1HwLqOaZhv5JSwpcA1B3LMpxJ8qcoFHMJyjd7j1vW3n2qYIR1h5pkp
dZBEGza/un7B3KLVSJVgYuNmZYAy8drbcta/9DMXvqK148TVvKK61rNymsKfHqh89AhOp+131U7F
ZAfbFt0dYiUUd3/aBZQYijOneJpAn6AXxb3TGprdEM3vT6Vjh49LbCz4/qG3C5Y/UacERJ/d1Da6
9SYtec1mEWGa6rSqziOFh+WPbcC+xD7d++o9jLwIbanaiheYuH1upZDoSSZliNYS6Nb61DOlqfkv
lScz+UEQdRNSOero+gQnABTHjwNmAx9wEXZPnKnOUKE9W6ez8fPAct91JZxf904NDvg2M1pAGHDr
9cHbgqJIm7Rtz6O7GjIv3+00KsxpUZmlUfKNq58pNnbiuqZKFdcQjIv2UqjVqfYBCjop2nFpigIS
QthIhCJat8ykeSEJMBO9JokaYsl+KF9KSePP40mlIMaE7TbzoyGkLwILwCYgrguL6mMlH7B//Eay
/+KNo/J/rgxDQKcaIk2TP3RGelRr4fX2eKSt1bBeiv7C+iJ4434kojza/WvERtJJTHnGEbxGnneQ
Suuwy6WKC+Jp/7rQICc5Le7L4HSXouSsEftVwaecOllWq3aTjmMzKgOaVRcHUzZHW4BlScYQaQxP
2ksh+ZayLAHK0RjGxhcfybSroFv6xtKvnts1HY5vaEHFbP14Kzj1Wsl/sGw5V0P8b467YCxGVRoy
m70LkRmSKzX164aBxVCEzLNfMEFQaQLPhl6Cpi7/N8W4H300hF07USkRPWXs6qgEjFqTzYkq5r6f
0jTH18JyFLkMnSoA6eHpsUveCZykkEN8Uk/3fn9cvjfnI1A2tdhcv8Qle0rFtc0v9VLOxOSx1jsY
WrkEogWk2EKy8I5r0RNKCSzKIBojk107lomVTwBpyiLtQtGaY7w2gS/S69iIVItovR27ow0rBLUa
IDbSRRTn6Rg7iY1pcMb5QUK7JOd8b6MEBYKqJIrtdYwG6zzxMVgjH1Ant+/0k0Zfg98g0bDyUE9+
OJ0T5RrK9RSUg+PvZ/iJdw2CMExZ36LEVe46yKpjAA3Y8lKDx1amkGSIpaQSFqL6akwckajxSbfK
0uz3aHeemj3uErsWVAowP4fXyMWOsIkS/EUvbbIHLHqS3sKfiK8XlQYRzYRFUfY9ipnTqnjFowCT
beWZkg+03FuiktXr3A2S+lkblthwvaAWNc1qA57dnjz/g9/C+cBPJ4uqg1jLaRILBonmQashr9R1
MCVtjdiNsQ+vMRW9s1ItUqpXG3ZOBS/yzryK/a/lKs2v+wtXgW4lyKLwh+XSlVsxLiS0QTjUvcmG
ED50HuOn6g5d8IufBZM97BF4RZn7A/DSAEICNIVYdD3qJd4GUfVPKxVRUk5uDTFtS0w94+Q7R/ei
6Oe8+GjhQQTm2DNZELkuUJnF5M4POH6/x6d3US/+x7SV27laI2ES/6Cy967wnMz3KYatE3Y7Ov8S
hjds2RCvr0MZX3MtNY98lSfSRzAcJefTDUzpHIDptz8wqdqv/v+vhLOsCfxzXPZOAJ+Tpqul8L8v
Ey3Bq3kGrpPhtIq3XaSOYa26R++rGOuWFbWFLK23UW+6gu06PMmdOoyAWhdnYA7pREwOP1X8PhDD
U+EoYwhTwwpEU4okeOc/Ikra0SepMq8C0QKFUbQaOCv9ERrb1USGVEFtrUvvlsNFGbpZE50FzacN
UHW7pysUicibltfmGwzx6we8r12JdfXV0K4XpbPqk957C37sFhxVK0ULKjfHh+ZWgmAbNUkrMQjF
0Yi1d0Z0kd1pZjH5uI1ZlNdVB17PNLDx7LPnqTm5bMJLIS89KloE6yQxWTijvWoAf/5uj1nFA3rq
loxUzqOjtCf8kT0QIRHQDs9CTikOmSkj+GA/6p8TH29rRks4PMVygV9ot8AlUvwxp9fbGFqA6Tk1
2+8btOhQ2GjymEAfi1H7DRLnMwKieez/7JsFn2Git4t1459fJgA2XP7GE662Yv01DqVRdLAc4hGL
QdwA04AKLm6l60dxY0YrsoY0ESAnvN+4bRbY3oxMWzGrLIUkz76KrhfDrmFzxG4d8P5xzD5BmaPN
LQYP3365Gdh2L6j0pLxoKBwk7oNR1SMqHUzAVf2g73vBe/u4iqfFGgAvFen6R8Z3nM47KV0yj3lb
wUkRgySU9DOEkczpBZuDp6np9dknwsi5GYq9ln9DO1zyaGw8CgQ9R5Erd/UOqtD/2PU9rFGLjv2n
jy1c6HpcQXtrhQ1OrG952e+w265V9MjSGdC6Zcg68wCdg961u8CwDgVCbNy2klRMiFgSn2cQbEXj
JnHHn186n4J424sQWkAVc3ys0oigMMaI6d9+75R/3oObaWbv9xiIHO6BBEJIE1AUyFShqHPQZjwO
+xB0vAjZGA1uLNaLzECZlRPgiUh8qUg2P4wlEv4NHWdjTcYBBerbiJpB44sx7lfSxxAgIieYRWKi
DC5bM/1edUp6uHuq1duMBk7ehg7Izx5+JnMuMAtDoIoxY2zfnoNYVFUaLg3M+BWT/bbulOabqi4m
xjF+Tf9/ZpNjaOt3GrKOH6mnBe56eZ8uVEvhyYgvXp1yO6UN2GGUs5zN70Jr8HpChdxFlXrC/sM7
dNrg4LDJxfYNNijKKrRZZmVP8j8iXNKTd5bEDLEGQmHxknFVdBO+Pyc7vNjpcFpTPeJb2G/nG1gT
Lo6LpsjbVkgdA+ldPnHgyPazkoI5yHEkvO383S+cKoBiByv9MwvgSJhiBPeYzdstT1zXSmxzJLX6
bdtZs3uMarqZpsjf6gqAqOo0akN3Yir6O1x58FLyUxx5DPbEyHov+L6N9hZN/tG4WKOOvLd4ejhW
fZjhvOZRvldkZIKwjUHp70xSh3HFKHzIwf1Bb51vPgAGrhHlzq9eK1+2gAUlFgEbKBO4ny5QfEfn
tX3mVO2FvmTEy4Q5MpIm/HOtUDcfyixYnpaf8PCkws4ra7TQJb6KPyaUXvM/BU8pZ7SuO87UVJpf
oMH7tYLYYJ1H5jFxfsm5ZD6UqbjVnWj2MQi+fR60a10QqVJxGEtcQsFmlWk4vKZTATPOeRsCO2As
kBNquL8tLyX3ddH1D1N8ICptugLv3UUJ6nwV6wi50Z/S+FOP1NTKc4QYUUPy+N90TFG7fXYe3mE1
ASQAfYyEpNXy4noQXi+AVrQ3OcFFkA3CBjJhXJByL7UAHtX6KsNM53BWAvOM8zLC1hhVxZktJm2R
TADi7xb59WyI1a1sYpTsASx08WurNnaCCBxiZ7tvmX/VYk3xhInU20SC/h+iF7bJ7JLq/aXg2DeD
R0vdgHUcLRmINELkgAQWT0Q4F6whDdx2FzjEW83mF/U8mF5v01eXrILXAxAWkvO5N2afETrj26uB
jSIyBuA7F2AH+JAucMG/H5Oze9ZrqahSE/Z2lp3ZmIpv+7c5De7N9cD8x63xPKiu1RH0N6d0YXdZ
O1ffh3qPKz8XU8nFqFhI1V+KFUd6iYA4MKTDaOpN3NFnLPDt0txhV6bFaDPVmLK+TrxiZDf6I6QO
rJgw58hrioYH0bLmGsMK33js91ODLrAzxnQ1isglukpxthtxV06H3ZO9nkBC6CMhye3KONkgwStv
fA2RQWgNt5zASqzIORbq0Rnjjia1LKEwBuB/KIeooVWfaqF1OvnEcepNYwu16TvuO6VF+3SiWA10
BQPm3VLJF5RIB56stcmAbf9pL6oJmYf2PGaSg4/vMgkAlyqhgbtLNbERwqz0/ynp1DbCbfhwhZih
puYJL0tNYIvwyRZUnuSVOmZQTFZ/5lpM9H+Stu0kk21uJkYdiJ9Dchi4ahlkYgcBdQd6PXODMuY0
2MR11RWe962OqNGq3JzQTaNM6gpB4vMzEyoWAan+Nb4WlXLmr77KWcfQJKJIH3/ZS0oyg7wW8Iis
cnJJceAUgKjw3jzC0L5rnz6KOlK6+aS4W78PJJSPCUx8cy2vsMs6OP+pC3b1cIJsvK73It/tCOX6
eiqHmCPjDf/UStfTOD0oBGHNBH6oqMGaxv2CKnbb37khPUlHHktI/p53JlcNGByQOBWX4qRFn8wJ
UlJSOiJ1+dEX9P4R9PBXCcf0ZSLKOCtUk+fytMargtrbmeTnNPxzVPJYik+Uu8e34ew6rnbBfBNS
wtwNRduJUseL4WZb4h91LYRrdny14zy+0foJQWO5exdT/sBmLa9YreWHoxTzBaDOW1aiWe8kaCaj
hCBioJ6MRB1CEInSTJ/Qot0hPrS3trRoZoG0FQ3MSid0JXZ6AwR/vjRglbwWN1voXg/sDfk8vrdt
max+FlaKcKazR+YPVeJcJmyArkvOfrvuK6Ym6OSMYQN1hfJwhaQSoP1Fiidg9VxidlgjhEEi10i/
bh+/8VeouBIfxm09K6XAQeF5h+VwxUTJMSwYNKB8P8eArw0F2rOIOhhG7y3BZSm1cQ00eewE9fSj
+oxFxppyP2dIb7qNkRaKnCRyt++9Kzn0iIRf9V3ZGH1c8xq2fUyEHlE4ICDmrBPffx+We1FWubdS
sc7tLOIODv12STJ+4RXPXTXUXCCK3ou+wi3FY5eL2IPxUKkOLzHu9hPO3864dhgVauDTMtelXIpB
PqIz20iYWpYDGOuXybvQtTBlFgVXmxCsuLnzWE66y0HPmJQjkDIuUTi077ZYNI3rCO7AxZJgW67o
jR8yr7M1dBOUE0SOCm/N+lyDOFw6X59r2WO89tRQh/2IMrDyK9t6KVnHEGasElGoYPwf9VpMzS0s
V/MkjoEautvoOC2RQcO867Ni8qt3X4b7kJRjqoi3rA4Dqsp6XBaSJIAvW1u8IwCj5zfiXFp6Q1pv
toz9KLLJ5yQM6zSwlk1cXnrLRJT6GZPazFWNodeY20IetcHWpGxFNnu/4Lces0gfcmt8COB7Gj6F
ZI2hfkOteUFWkMQu8/yMsWy+/SoCueSYJAW3w8wTVMIUcjkSBa6Ega6oY2IxrEpV3oX5JDe0L8cX
7WhnCgm66Itie1zcz3F5dhgPxjh5idKOYctfNro4EaAza1fr+OEcQ8VGPyyugGEEA+Rrrj5vhf7J
twHBBottYF2RM+847TuETJ9YWf9KRrA5/VSRB/zp/TlLSNqmrCnNLQ7gc6uozV4cirFbMaChiYvJ
xvpQVlmjzAGdGZTBaaJsZyuVeWcmfnklvourPNRFflfQ+n4Y7Awx8YAQOxmhwh4MikxNNHM4egOi
7q4okmE04QzWKx9Mh+q1gO4BF3TAsBlDNiozGHivd1rnTSE4apC0VqwEEWklPfje5SjlbT05umtK
lAh305m2Kpt+ApassAy4xny+gWUbs8oEUUbjHSqNb1wBn6jIBkWJuoXQAeiyFMB3o8fQD69yxKqq
smz0Lm/nJR9v/O/6nAiBJ1/awjbW/AiCCuOo9HpzjAXX3kR61jKcaK5Msii/9DoOd0yAJTATu7CX
jLB/HJfOw/m0PDgjFC1grU9UaajemGIjP//cm95T9tPVkX3V+DhoO/62r5tHeycF/G6SlGnICU7h
sfye1pT/NClBi5iDAwxJJczy3mIe9PF5Gz4bBQ+Lh3Tu9wbQRp3YsQU2jDsKAbbRQLA7sa+O+f3i
+1r1nWJQlN5i603kEMbeIzNWoVGVJTJIJTg+dLne1hSfyA3vjASXLX+vk9fB/CT1x1LzFc1YvPOV
JRsf54F9YjWz52Dec2GPg6K3qPXUt0nTyKhUzwcnIV3dR2PMD8i5R6Pn+rcw5pi1ey39J3vEqIqE
ZXZEL6z+hyNcA13ZcyTNp583CzKjDJ//cTRxLaWwc4wLt6Ehv72NlHnOrcCxoZKuja1BP6y9g3Ro
pwGI/qZR+e44OGIjuUoM+DzqcLoarWUcPKHwqlryuhwMYPMKalLBEoiRlIuuqW8i68V75U80aLDP
B1/SJ6LSmGC9hy41XqVrdt9cNRMc/d2mWe+G5+WoEtssjHV2ijI0E536El2gIb01izaiH+Onl0GY
aEtm48GSdc0xXG8yBXwZBVDxI0+cvUHNuuwrmX+lf+LDE6VaYccEX9CDWqYSKJ0jvPuvPi6fRMhb
wmbanzi56MtXaYSQzPRBcs91cavkvekMtO8KosuRU7jCXI2XIfh+uTstvp5DOyTkQIuc4wE+R3ZW
esmQRuKx1LhIFKkpwuUE5I+5VwZ/vt8RMPEjMXAit6KhL5opK4AtlGRoU7vbmq1jDMuZ/Rxzve8f
s+VuMwfL2xd+TPd1TnuDSpz12cW4/AKkx24L/u1LCINwVuBTWNfjiR3clPw+zjHgmFTQ/ZZGVcab
HBdsVO8W8382VDe8XAUwaIaQT6gIFVJJ5dFVWcxbSA7cvRGk21Ay0Dk1t707MGU0W9ggCOL/4O6j
oyC7E6jAE88r7cjVlHVG1aufFI1PmIz3xb8DvDeGFHVa+iUE/L2pvh1BZVLzHMUkVQwHs331g5Um
zxt551ygelsm9nd3b1MuiNrlcf3Wcv8cgdldw12yB2V9K0OSPg6oCpuxuTO/RSkYJ8+fBanHB/N2
gDjotHICBQ7y0I12gvLhjYRGaU0WUNyfU8N3DWEEKGhsz5+rTUf3XYFYggTkM78knwGd55yuexg9
Ya9/39ftCBCVbyvvC8YZFx/lrnkJ/wam+pIK0ffCYQ0eh0/V5vflCX4vESC5/K3pj7yhOsxbvCgB
qHxKZd0hgQLnFlFqMBW9WtGN2XXqXA/oezkucR0oOiT+qvoShQmoXJq79AVQOn3RPZGdRw8WPhcU
r2bDjkeoJqlmOMx8NICWn7X9maYbuypjWfDe0hCUqkOhHNW2pagqPHBIpW/FuaQONekbCDuNiqS8
zzqqc/ZHmS7/IWDCoEiGH5k3V6oAs47yVfU1z0twqKPf5QonOFHS4DYb172XVBBSuVqpi3IFZG+c
s1yp4lNaaJ4xb6U+DxSeP0WdowXUVYFQfBjjfiaEwdG0uJu3xvif2IyaL7PyLPrX3VmWRFWslETe
HCDepn6ZCvXflUclJW3/SNtLoXLV2RxKaU39LrGrvahjUUeTJ0fNeZWFl3LgO0/qbauZ62m+0uIM
tceJNT4+Vj26C6Xnvf/w/xYwelYR3IzjXLUxO6kfr0G+SqDBSpSM+fMboiIDmZz0zaaGT1WlupLG
8TN6YtsPlJOrrZOIeiPEWEujTaTj8TcbMgjboJFK0iI2y4E70cToIPQEOfC5hcWSjoSdiGlgpmho
IDWIco4SY0dPHmcSbn5Csqh9wtXi4fheS8qp1R52jdc8Ujv1/N02cYfoNn0C4lDwPjXYTOlBKNzl
na/8dq4SmxPM7HqurdkCIixBWvD7CTVqC7UZ5S+xOZTyw0kWy5hpXIgrA1q3vjIUQZz8Yb93Wdsq
ZN+9FMIZ6SJIgfOJu4WpacqL/umssef7b1wsbOd16rNC71uhhSnBZOOsmQjkiYMW6d9qOq0ErUA5
0s7gylg6dsQhSfj6pbnwxYRRLvVXvphZA8N0axH2s9dCs3XYOD2DJwiZkFnTZ/MCYZIU+BGRl+RV
ZYafioo6NfZtt6DRQAkhJADNCYTR7Kt9qGswV+S/Ezbm/sNQRYsZrmQLzhTmLzbPYmb+wIzSWVxM
fSNhTXJ0e/J9ez9Fr8R2XZ4omZfeJyobFjues30FrA4OthbahJOqsW7YZL6gHHyghlZuyDGaktY0
4L9DoiwMwHESI/dlLuVXmQsYPLPM6NHK2lIo7mkWC/gYPqYE+EJyCwOj2pzDPneQE0RmkMB3h1Qj
pVTrB6KXjCjmdxV5164ro/j49nP2We7lledMHeWgYrq7R/wMlsa83qqdgWxRZ5guoiedAFIDf+k3
oGB81zVLd6dB3OThmfK+1sJy/yE2qdX33Wi+iNMEUTzXpkWzP4PQ4U4YDcgs7vyxGumym24fpCe0
okr1nw5c4axTrR/eqJ2SZj+JIK9+rMcLdUI37ukgX06nlLEGX5R8bim3/EQUstJmzQFAHLepz8j6
vP4/eak2+j6PVspS99PUrkYxuU2hM5aZp+65QnY5aFzfDWdI7a7/mM6N9Eoyip1jFd3KKva1Qt2i
ZjocBQ49Qy+UryOhC8GrBdkI9S2opp2oKcAMGiOypSgkawXKU97IUxaU7qO08KgjJmx3hsfoNA1p
x5OCJ2Cny9EyvuF2uWdIrC9w4dZP86V4oBDjMvwzt8u6L5s+m970BgYzE9Rym9K8tsl75Sk6G0B6
oetGmQSLnBE6JnzRG4DkaTmc4lmOuvvVx3sEb2nMx9+sTLLrC5cZ9ql+hxarm27fMp/VjJeFCYDn
SqTEbV0h6YoPr15oar+VO9z4nDsB0nXIhoXfBadSYfBA/XCqHGi0hdsbOKDGWNGtR+khlUmKiOwK
FPBxd3u6hthyoyByCkJAh5cB6iVpn4cP9Hm1rJ/nDX9lGBKZVvs1Cjew1FBLsmIgQYmpa03IFTTP
WRY8xrSAviwKyfIVgM9kBOWVEgk8ah94a/4G/eyGUtejq5147MsKFWGOyZPZ/WJiV9Ucx66hwfQz
paOPQZp5FeCD7UGIH7Zrkk0wL6/6BfwMxyVF4YF7Gqlz/6g2ncgyEE0cAeSKjwXWtoi8Bfsgh3KV
PIagwpn4sh6Y/EXoZZ2U0krCMGVec5i8UN8pRNlJku5yn4JX6erxjRc8YZrMl+TyzXqA0loSFu9b
uN1c+4J165NnbGecTwtbNK5pLr+qTlsOM3bCG+RvHt3mbmQa3bMnO6eRC61rnW5YpE+H2BQra4Qv
Y768CNkkvcFztt//sArurHi3++SvdiLeAA9WSDrJoNKYoLz3JOMYawMTAhAxNXI+3KmdBno6IssI
7LTyP4/EMTplZu129IAuY1Dl8XNEeDty+GB7LrPoPX9QhIP97Cpk8HoFE7ZADfcHv8iUvfK7HA2J
xtvKSefOrAo7c9JUth+F6g+ygBb9639XrsF/lJk4tqBMSlCX4H6T5A0l9VhIR6d/wsUUsLsNC0od
MtamoCP0oesgzfSDfXtUM/lF/4sN9SFHML7/ML4OyHfw4wp18cfDUIepfvNRxe5KwssPw5xxe5RL
lg6EaKTrfEpGuMVcCCPY+b4maEKdh0wOlSqFr7It2vQXFrBKWU8uqBtQ6Q/qOTnsq1NhhRX8Bkj7
zhSiTE8GQZCobHzEfoY6wvUOkuczgqU7kRrx6PdUukl3CpiBcqSeNWDin1kL2nsRcsOxj9N/XAae
EIUguJGEL3jGl57jY0EmJJWNez3UIvLi4kXEcex+sZqMXLbmrBpAbvsl/2Wf1s1+UtT0WuT1oheT
9sXlM0b0Ihfe77SfAgvmSbHZ1yfdwkqit9DvBBiM2e6M2IZ+N2n2K2hiEfjxWV6RnS0AOm9yNTsl
+IoMDwCLf67qTC1A6Xqu7ViAsl8HRfbLjNyYFwHqK8dnpOF5I09kkKqLXbRjk5gflE+Z2P+Xx5VV
La13Xgi5PBDIfRL1yvCrIhfnXTUigKODTWNnYFTo2UGM3wkgYU9wYEFos8o+tgGmtQefg8uS7Lsv
Qn6cFJH7PJqWzugEi+fLmcsJNQ2zOz8XbRmnzQsMDzRPZXQKkpwWmunXI5oCz4iggp6IKhRaMWPW
kQuxv0UQnplvi6+XL2HnwEMM7Pw6wRhYQumitVE7OdKXSMePrhfNdKhL7lX06XqUL/v937ZfSU8k
lPjWC/uMrbJ+vDIuTZnxsT4qok2rC7vgADhrsBOdcbDZWYd87Sp3+HWkk+T4SPIyNoA+08peDNpq
cpWYfTShliscCgAJxcpLXx58oBtYC65m7UqMbYmVo6qwtVbRoCeICrcZEcNesJFKxDkgZyiCe2BH
eXiQHuHwRCOpSErNupdVQ5YQAAcpXMUMznGSkM7BWmOU/HnyM2EZQKcAzKXxdv94GMhJNgIulE/Z
znkJuyoOr68/rt25C1/iswisjP0eVtyq/lyK9K0xsMEgpuDPZ2OA5fFdbk02kBgiAVkql66QPf7R
7CvCDGQfnfOnM0ec8fPynbnxW5IHTp/Z1UnlU4EVFEKTTe+xCauy4sh+uwhdCN/nMajauZmZZ13K
y+ZvihqqlNCqGC7zRGzLRoICsbNnfc6C12hULmp1bcs6NGz8gD/0heP8CtD3oVP8vaPZBDnp+imy
DDElpY+iZ8mVFW90DRZL9vDUCs2vDmpESo6XZB7GTEzmGZiEVMelb3zRC5Hwu6MjFRxzqtzazFvC
uZvzRGEryz5v+QSEdAUrurSr4YrKgyUG3CAIz36WGgCMs8z2rHaQl+nGlPygEoGtGGOqW+lY7fD+
ATz6pWQlKCj11+1JY2fhGUVOylVxlfgx6TM7Oh7uqRU35VzX6x4vnIHs/pwZsPTXylGimGmLchSv
iGwqxd+Japp4k9E3KblLkDRkbcX88iDdtdN+Ek6c0Kd5i8te5wUXHCQDYye0ErCSvtDdTNPrXe8a
NJeDMes3WNzcYqW7yfh1Bn8xjlTAVuJ2dBPnj16CVzH/Aco8Y17rfFbRt1msdZA/UHrpzuU7TpcP
G28o1r1LlfV4trmAVRxp9k/bd7k53FcruY2ojQypfPbIfGFPfnmSi3wV8boXGZA3nCdvIO+4+x8H
Fo1hv4dMyQA8bWsz0SIw5DnIpnM/mA5FladNZbKu5WvMNxD+UCQniOu5YVLjx+WLCErERNtuSvn9
zyVmtECzUyXu6bWGpmt5SNI3S2NjB++CF3axh7kOlNLlwXwoc1ZxygfllAmfQPHt+MtHK2AyALJ3
8OLuhn+/QaMaSDJsMMPfS3vqwIytEgMULPLTpe3I2AS+MGc/wdgnVpZd/ZxErNEN0HhxsAeEuKjP
hNUC5h7Aapna8l6PNdfgNjdEMMLZxh2DnGF00m7/E/hy0CQ1pOBwHJtc/xcvOkObOQoCPu4lp9fU
bqmuMGWhigufS7pqoSWx0fTlokd79e6ig9GnQ4NYN+aisRb96JdGuMNi6ItIPHZfNAlag8DtTGoE
f3dPyve2I9q7Ve8+OrMqQGIiZDssHaGKLallzSNA/r63UUQsbU3vN3xSOiWBNHouf0kW5cxrsvZY
L7lINRKlAmOTopdwwOyPLU0I65r9RQJwX1mOPYIZtzFVp2JgrshNOEG2ZWouLgOLIGv1pb6yZy6c
Gyeod03K86bguaUZkL5iJKEBB+1LWTs9DJP8Abhzt7QQXVYdgzFZwAIWlFcH6npTcKay0U9EI3k8
BjE8XjPWYd1mdn31aOHYCLyLoFED/sy3tHpr5sYzpVxY1CM3QXOPuUYjwuUeDk7FGBhy82ax3vOZ
GRE4OZYP/GK07ZZYutmihXuvzERuYXkadNFpHYtB1uq1cBflxAT/I0WEs/6HGprMxcivcghuOApj
mbJ77oqPOqGg1vwEYPR2q3xulrxd25kq1PkGSFop2noy/g60OcE1vM9UIR433N4fk6RfeASCxjXi
pMKiC3q4dyIMp4aDBs/6g4XY6SatXA79VBKXPeB4LStNbs9mIBx8TBny94GA/XIIylPQxKjT2tPt
Fs+c9/7qGAyY8gbhGR4r5ncZtfr4+z223RJHvL+kNSjTVyIqU1kDHr98aUgMdfEMF9+iQ9pAhNoF
8tbd3lhJCxndH9S8jtshaKLemjYmC4gzWhNuJN3ehlbPq4mSa54LgQRoACv4ofI/aar0fCXdI9pD
PUrg5++DBOi/yYrxnk9UXCvb/z4KV18HSzEl4DR74QQWW09Go9Q29sL08ocj9upZyajpSc33LSCC
Eyy/Oo8FEecW+XjBRjRPSADQHXDVYYFwm/fD6Py6YCzka46d2SCSbZqH8dn5SrodeCg5JV8f9i1E
Peyamd6Ukt+DpOxkc6JXvcNJTiEKhtRfH4XSLEZNB52TItNp87H3xh8BI5eHkRGe+Uk/WJiKodvB
UrU/ufS7n0d8HnU2iiTUSG3EsljTNd2gxuAWbIvt3DwJ4qQmzKCkIZjVkSQGK+zTQ92MDEg44nID
bWyCUiTABZTP2bkpjuF47GijpmbDM538QlBoSkVKaGy3jbKTF2UJC+ugtzua/xm9S5DwIOENqqWX
VUrFjXoJeNSIW3etsnfLlhqNTMNr7enzZgZluXpmbC+rv0TyDALuyCOaik0hJHnqEaZGimrvlBeL
1/YnIeS0fw+bOkd9Z4Fa1df8FjVzGvdkU/9ilRt0n7mFh6sAA02slmM0Ws11Hq4mtZ6zQabOAL9k
sy2ACLlEiSfO8c7DsrWWGGHH8iaqPzLFgzatHcXmRd9ovb2/qaC//S+uX/pslDCUgp4alR/QmNtb
UDx1gC4zQMGBKIgjHVyB71QWlLs/okUhC/emZuQdjWOtXXm73gJ5fqX8m0NIsCysghDiz2JNOxl7
Qv1CExW2gIkppdJa4BNOBGnXFO4OcCon5yTtzwZg8XrEvO2H7exLBYUpP5ZSzniIaqE1agROXCGk
ZKbmnW6aF8uVnXVxFHqrdtK1hZHieFjMGQ6l3nHNPNwgVhg0mSe+A71eDuqYdKPbMV0k1ou/zoAv
LvFLsYzR3IRWPE9A+7b3FrwsvP9Ehh2zGc1WwDtMbsvyFJ+GpOHMBIctYtGZDOozZ4qbu5X6Rxm3
CSbvlQJpMHKFleb99Me+wy9hA7HKjUVtYGcjS4z8XCH2NswQ7P+CO2vOrsx9m8FHSxnZR0hezgzi
ZWKvDRbyxUrVe4T2CSVaxoI23icuNQCrOl/YxTAkduink6YUpR3iFAikf4bMNinVA4Dh/cTJdKw8
HSBFeDhB77i+dyj+PvwASx+wNpeOxSurig+DzS5rEYXmYTsSq3REg5f7oxJz1+sj4AE1FW4pRDdo
fxb90KozDGGoL/QxGUD+Qcn03182ZCb7D73dCYU7PoVbSsTV+ZKm8yMwkxw90sK3edLpmgcP7iiR
fTRc0wmjxArWmRbFWeMu68W6hF9FTUqGNZDS7yuEAlF5izZImhX2jWJO2JfKcJBcRNvIcTHTRGwt
im248MsPBauQ26FxPWj6ImBc6QsRxHsEl50gmfHTl7PbHTfLWpH35u5zytZJFF0pYlEooLCk8fcJ
DbYeXGcs0WjC+RshqorkV4OKLt4yBn0U8++IONVyn+f1yjxiKXrz+UZZVcPDNK1InOVs5vmmfICm
vbV/ppOcg4yluURAsoZc1sgAUVGOS3wy0BJT1CNLn0+Q5A4yfF/tufocd0pJLmcFdaaZG/dcTnKz
gkFbgaPkJGkpFspyHK8e192uLq4afzKqYUxqylrXszKx0fqu1/QP8JdC+CB7inLhDl52FzQF3reW
SIQXPJZR0gghlTa5s47K6qhhfjO+1+1W2YVDDwq/uC/nUi2Yj1A1KSpuk3weKf0IKUeUbkq71M6o
bmgXv/ozl86XC7o8yW1XVghLRM838cUw0IU2nfs2F0EtjJtas1+1kS4AfVaO4/yhKSAr0MBrgQsc
uvD22K8CP158WDjzVrtXh2rquQYmp5RyEatjR5/JWNXikZDdYZCNZBQ+D76vv5fRBFIX7zmhDKbd
DSrky5ZW2jcvQlh6CpJeEzAs+u5Z5h2iJS11fXkNKEx1QwX4LsfuQwTIk2REvLTTIl1XUFvCqnOt
nH4dKBHAIMIFbZILZbxBSAPDo0Q7RIqcgzT1OWdOItsRBp8gWZDv0kYMF3VYwo4wlqUZk/Wr4TwG
BxAwRY0giL582i/xr+OSAFByRF8fjma7mOWm6WQ3OG4mKEq5XeBo0hrPFhn/ZIRFKLXYqYSWF1ct
v+lMiFOtsqEAxyihgBOIepJfoLMTheX8YQW2uzIMjhdb6ILssMsnC3C1Z+cvFn6d+2hgEaC9gyEo
VLQhergY+bhkg1PtQhLmzxVnb8FaVyHcbWSaa37eYraCCXPC34OnMCfDlRSk58KqERq8L3UoXjGT
08PY3w3bM0mS+TMtJ6VFT8jQbo0sJOHuz/pAquOMlOBrBaBW/wfQS03NpDJLlurv/kuApz7XuY0Q
zHq0iuiCCzOGODXcHcuR8XzSdCn4DiGCSF3ZmpzgHP62EH6wyXB8ib/GvFZN+oljbWs1WIaO48wI
86wVz8foxlVKRe2Z85qRTpEVbXKh3G77Z3sAGQugnecx2bsqzY6VbBRgvmjo7TPG1PsDEezs8sq/
K4XvsBl10oNv9QeFOQzCc34YqstpYNcP/2ejekgKEGe7gRJ7jgienTc9EZKYdsxBKgqOjA1ev1Gm
N9dm61c3o9uNC67rTHmJ75ai6C7U+A0XLj8cPilo9arNhPSIRdJGdLqWhJYbWUVV5HaJlVYbdjwi
xdY3Js+g5/B/glk4/ij+FiLm27Kn0lZi1gTRDironN4ZXFn7cz2knn2E3v3sGzZf6ksDiUAlcwZ5
mwCp/XA60IlouztI+1STrFYyi5RShuEEzVC9g2PBPS50KyK/W70mQylgRuBvj5txKSGtHUyUpLnP
RrLpqaURdF/1waCkpgWx53K6kYZSVbbdmy8+kaFa1+0X1OosIs38AnUZhcX6xv1yrZv1C4DcHl4O
o/OeGA1v7d1GRRCvpcZy+OB/YPXYPc4NCMcfGO7PpAetrU5/KbU3q2yPHgGvKxMqGVWUj4+pjlFe
3GLYIRq3pmVHTNGuB4bN24NBSOOJ6xczbqGeBvn7RMUb3o83qngjoKcOhjqfEyjvRpDVo4gVIoDX
YT2jh9iLrn0DLGbaIpVCCo6VWkwm3WbD4DJaZF5HELdUnHyiVP5YTXZx9C/pHtAtwC99YiW73jAG
ZdGLs/82VshbKM0vAUG02rc7w29cCTBRLMMZcEwLJKhwgo7434jREBAOYSst1NVH8CSJr1ENnnNj
Np5L1cnZT2fLOAibpcoRogwbqnMrXvIjYPKz3U3pMxtd+1c67Zot1U/ufzsj0RZEBoyrCqHi+Tme
cjaujlK4F17w38evpD4kjdp9e2OTkv/EgmBw1DlDjFet047MdAZaSX0ifVBA/8upv6XtQdG1aCg/
QQiluFzlK/QoxTQbQYHvbwwaVejWqpCCdIUomEbiuOM1tj8BNOFMsR+dnlaPB27VIs2ljIVZWHmj
aQ/Pi/+8Kmg5UHMA1DYKIvE/6LCRLNRJWVZMV71RubOYE1HbugO9ikJJ0tFeT49szBpMLgGGmWyL
RrGZegPwQUuh046VchDjDS42IZn7xNBx38F+d+fgO6DyKpa/H8Be7fyPt1evFZRkxpWG73BgzCyR
MTGcOs+XlzAhTQDW0A8SNBh8e7uYCH+vTuNykq6wFHOZTz7RM9bSn/hf0nwCCDC7SEU1qW9SVs1B
cWK9fSHphtR8J0ywty0f7B10b5RZ/2nZZJ+S/6fooU7PKm2F4Zz563rL0c46RKK8JlzPSkNMQFtj
ep4m5ZCj2TnwXgB9NtXebTXj+9Z5Hip7lVsAZMkLC30NhV7altsKpRdGClRlmsOmlGXqPsJpjGSK
oLgWYhNbpWyk53CEpmAQS71dmyVefwNQ1/q/U2ceAm3xBleDPRVcGIXCtoxRv3y42fgOSjumEmK2
FgfbAv8BvqFmkq4kSzIG7CP/FnyC7iJzdHusvFHZhx63MVIhxPe/GqpX5u7XrzIcqY4G9ocGQZEI
Jqn7JkhcocQWYvN+fxoRBDA4kXo6FKhBrfhmlAGE96/P5uF7vG+kF5w3tYBCcnkH3ZkhX28f0WTw
j07QrHVP1J/sJo21rSWKdqTCGSg1TYa27A+FRPTRnK2LaTIGjrh/QaFrK4joucUkz5aydqzhMuSN
UNROgrhjjIm59hLD7tX5rEkO7MB3CFri89Ipfc/n6rgumB4f4SSJd7Kx4KNBZmj4QsAxbeVGtJUg
tD07PMVkf1akDUrznqpVe5tolLYVsDqMItQqw6/Xb5qG4T6i/KMgoygpxGyBgBnjIDuJBqrN4ovL
Qq14GRZLVzvyd3Co9wA0qo33ATgAFh29rsUgGxU9ADLule1NDos1Zim3bI7aEbBaC8VuDlqWp6Mc
2R42Jk/x0Ec1XGUHwMvmiUx21UYUCGS6aJUa1UN+1ITOL0swLNAKhiXsReBdrcoXrp+896VCrKXj
IB7vfpI+jP0/TG82hG6nWLMcB9NAaDgTyWv2fAYbHM0RwKbombYv0CxVPlI1GLjQcKGwmeji4Vzd
t79xoT7w+FESS2lGXDMvwNEwrtvjD4sD/KK+uIOmplJhKOJzQqb3Ooiki9UY10K+T9YS5ataw4u/
FCpLVi/2xmzs2ivPdlDoVns/yXAzzTwZdG0MwuHABKGjiLUyar6i3Bg5ozig6OlcLIX5G4t1DkJu
T4AbvrbnnVhe5uo3TZRmYMqL81MkMxVF4E5em7cy1TC2tW2ucVTtDh1BdDCo3ZUZmzPXYIteAASk
QI2Cb/6ms+uNUcOObd803yGGlfOwjUovOFFIUHbra4CJ/HwNEcRCglfulMjIKfePoGv4pICbW3Ug
SvLKtgyTmA/U6wzJEGggkd+qLwjuxT44SMaCcHwqiuVbWJAB9oH2Vx2HRV7ZVG18rkD95f/OB2t8
vR8pcx/7VK/u/xKfmYYgxg9reyG4lb9AcWGzDR3nl8l7VifC7b57ty/UZW1hag1leDt5UXKzEd43
4l6ckQB2LvO7+ApczbHHxEZgvVMejn0clIFNpOg176O1gPdEVAFkPLa0CneD5ileqFSDf/pKHMMo
+LhbrL6cnd/zl/qt++C1gTwFs8mVJ0UfjOilMUK8TG0tNBoyBSb8lwR83/yebuNROVyWVFMd3uhP
TU/D9iDWs+3u5BPrP9LX+8YREOEaX3W1pQ96CdPiNF/j0edSz482FKuN/o+/y2+lk+XnTG6U0reQ
EUVhxH5YqDdLLABR7GKfcGcWm3z1b57OG+EdsqU3LwKfjbXuzlntAAv1/ShJXUIHHaaSjsluUuw6
DnjwR7q+3iLUyt3miL4zJzOcHGF+mYGEKUE60wdvDBxk2W/Z/oUtD8lV4+QaXWhtFOp43Gv6tpJX
2M7FgasbPLgEgV5Rr+LJulGomDnFVpjDi2PWNdyifROZsd9pulSdvv+K6KM/sIYouza8simPsZ4P
Fmuk27xxpRonBOTI/8+xRcv0blWnMqSutc8UcKlwZIsS8tPGIcj/I4iLMLGeoJ6Ra5NSXrrzBTsN
1H5iZKV93oLERfgFlBWHbvgfl8Ebhttm2TP/7y0qIob7hc5HqdwrB9pKUYK0vKTkng4fzUsXLss2
jtPycKu+De6ZfqrklWSLeyUbyawCj8fS0iETjBkVbMBpre2lnx/bkRU3og7Himm2r4ety3tNINRl
MAflLBSC1AQ9I5CNNO+G3wjNtsWKvzkGFt7uy4EC3ihWxCa/RnFTuYhA3N5jKKRvQOXmA06KPzCb
jjna1W20pjVXC/JQBZZBmhUDMWJH6mIDHjd1xwiYGFbjzY//8ytcGNwVP/Cpg+9bSRwnfukt8LAM
ypzgVPLy60lyu8Ajdpeu5M7iNwW8h1DJUfzYwvKmirV9/T/kF8sl7ThlL2JoMIG1hNNXjyh+MBuH
K6Yvk1OGbUAayA5n6nY057l7eWAsGgQMA07WFTzWAD3CQnwIWJ3cABbiEdgLfblC1bzTTwAjXGjh
OLMB67tZCPfvXOM9c614dQwt4Y2IPtaUAEt+rKH26MmCGjeA4NNU/2WxoKOHkdo78ZtmE0VMcNuV
ayAtkzK+ptmg+EmzTBtXvIMUnEgmUgOLy5noGw9INgwZm24Jsds4p526doOGm5+TzSVb6EXUmaZu
iAiXJ/uTWCN3r4rEO5u/Uc8cwX+YahNFIFs+GjD3bFtq85gsL98eP3Z3wdbs/kN7Lhwv+95TYsv3
NtbA1b7bo65O4/WypmEFwZlQ0qEYuGEdZad9YejHvOScyuzuPax/DqK/ebs66WQtuweaIa8QoIdE
FLQtembxLzUpdQlkQ2kKv/os/a/V07p7uZoKqxZJp2BQLdk+0irNXzk6BCEwZRCk3+T/tH38RETF
0fEF89llk+Q5mtM8jWpmezUIhPvQAWtC0d2Km+dirhkLzUsvFlmNpOk5zaOMhVSs1H6Wne6aQMJU
HJsCTN6bN7u6wDpO8oWH9LpDnCO7/XQ5wrNa4GfX7JUxwhggvtRJKoVirLCcA5Vqa9IBEUQPxsZm
0mCic9QZv/r0Aq8b9q7ukWPVQruZQkum6AZa+dW9y5FVHEI+92iFgk4vYQHmjem8fMkWPVgZX+HB
PrAJArd0ZmSwmMtfqmLOZ9Tz9KRobh1JaWOcywvEk0h+GNO9awj+88pxl9xQUVWzqoAf6t1Tf8bw
8P07bsHFujqoA6d9HmVisq3haRQosg+Cx5BjWwehYAF4dbB4324I9NcxRNvnX+AgTROmZ1ub1s3A
tw7hvyPG4pFc8rtJF4Qh6aPEMScmwgtC01bwgx6lDCmildo9harWpSN+boQ2xVqaPMXrhi/APFLE
A7T5GvjlSM6+SE51X01BXs+KnvzsboTcSce464WPi5xQPpFNcmudmr72I+w6KovTHZHSL1Wa48PM
1T1vxXJH4v2DH9AGqb62PezKMC15bFsH2BEehYAqUcT4zKDeBBKICkhFkQUMPSvkYku3FlyRzyPU
Odj1LWh4R1V6J8E+4m3/YoG78g1xiArieIvPWl9Gk9eEmxrfgvOEt4hObLS72EEh9ol2OzlMc3yl
Xbve6YsYfVR+1YoOv7DJ/3Lj+iqRhs5Xcwn/QJZ8rerMGrsfro8ShMGfaSGBUyK8kxqXEuD1VgYl
nrnpbBtgUFz/MRodQ4GQ7f7p9fpboL7g1MIIGZNZHoS12UX5+z5jbVbfr+wvsao9N2SUy7TpgClH
QAkchm/vOGElKXmzqWkg4eMCebRPi4LS060CDU9H8O53sUkzL9BtV2+CwHlIfIbvJ0V9mQ6Vmzn0
veCu88nJ43dBR7qvtWS1ho4eHda3YGVtEB9V3HP77nZddG9QLTNfBvDn8Wigi/I2/n7ixhfKQYmP
sga9mK9rVmJ1UL7M5ZSJrCSAujUak+cdNEnlkxn1NvZGoHX9QDKBZmC0KBW0un0wg/7gNMX3iIkr
nMVchWGJDAZq0faHWQ+nEIDR01NpCjdmdLKHwx1/Jvv3Py5J2h+m/uTipQbaWNXvHGIte3jZm5z6
b/r62GIGupS5Ih7K0qmSd7vuhYs2XOKLhBLcY9X6gBu31iufhF7fg8BPOG+NPSrCUxvakzfe+rZa
zhuQ6STLUZ2oIIlIllZ9LgPFdXpXTzEYWT7xpGxoAW9B5PSr/kiju6e4MyqlzFKNCzBrE5LGsU/P
YJyrCJlJ1XhC9jaTydZzKIaq0LoDP80VSVTzWS9F27m+BVcwZgs69v4SUGklK+I5ito0Y9DBURAk
P2DvcTH89JBIVRnR2u1AgPDfqHJi4y4TmGKi+jPifLU9LJ2tBr+/jecx9EwG3Mo/pMIuk/JtlZOp
K0+5Fg3Fa7midHJKRxTMCRxnOpea+P+0GjnOzUo7TrJPAmA5/KTyipFnE0xJYZ4+ZsApVgZ6NeBh
gRY1SLwKzLcR7fVkWcT1uHwNjRFKTIH5EXH8d1lfm6DH33xF6tamIVjQ78n0ZtsGWzIa+rnLt/73
w/YjYcNDGPCztt68u8GIQQVJslQiulrF6drlXS+sro+5Q8lEJt2EDw0IONEf+IQKWfiIShnKBlYs
IAsCriElngVZF+XsokMi/l65IPc1ZQj8QgjzDeN9gc1OPj21Ir9JLzEj/3ylRTjMfSLam4PM7Fn9
W1A4asWBB49O6Ku5z81m5zjvOUkPPQniATie6N6xjZI0qrrWBTWYsyJFhhehOJlsuVIiBb+V5Dqs
fpJiVIys6hxWo9qpytWFsVq2ySIhXtEZD5cmzghDS/qjcJP9Dxv2rJM6idto5K08ehx9vZoDD9J4
aSSRNJ5QYzu6gN54O0knKnVGiZ1DpITrNa64c5Jo1NnHw/keuYsb11/cPxtzAE9UUsG6JIuzN8Y7
MpuXaruegckRjlw+oK4SAT9FZaGje0KNqJNhEFCGLs8wC7urLZ/xRATFo40FpdIDBWPMlVE83bBQ
ssQjsln7uL/WOMmT4+CTbEyRDGGRAJSytF9IBrbPD7dYUaDYPwAnTgV6+875FfHJKDXLSpNNmkrc
vtyls/Y8oGrz3hLj8Moa39n5mvOOr5rEOxvGxIiEBMLolY3j+n9iu9AvnCkHUsfymtKKHuBCr3nV
LBKDTYOdfE/eKmHRgqLWyzzZx0wIT30OerQMMW0Sj59Jc3+nZXsEWvazO+bDNlncSs3uy4ws4WhW
lGOGyFRySxTRB9q38v2eU4bKyB4U6zJGVCUkZtM3LHWFLXTL+oanG8cYjWT3vldgn7ra+7exKpTO
BHTepz794+tLnaXf3W7atZ23JITVC5XWMxdGrQIP+JdW36oHesVVJivnU7XDAhmObcoGo8T3B6b7
ujEOGaXKpQYa3DA/uPVhWr5uhsCuQgEPDp5IeXLpPBZW/CCoert62G/30GlOQbhi6CEoxHXGSsUj
6FiAAQdK2fAgZszEf1J4ZkzC71LK2ue1rLyp8aj3soH2nXgyGxn3kVL7lT7NlFN/HgT8SuhWjy1e
WCybEd5j839OcreMuQFBX0KTsIewEpHsSMO1MgLiejXEQXHeRvo817hYW65ZUIqmVb2HwE9FvhES
s6DiUm2PLlIsjNQOC4vZN3NNd36hhLKwa7r0SIUlH2KRgLOXSZ6Bq3qV2p2TKkgQ9C6zgb5yXkZn
OUN9KEDj3Ce3pkf++kFOYzEs9drCmdLeJUkVfSidT86BpkIbNPZ5fThVirNE5Fmmj4eRCCwGvG3S
klvZDepLU4mLWgNUjqSDo8880OcVf50O0U4+GN7vhg5ybbAkgiHVwqcWCU/l0sGvzJcQrFNBH7a2
Q9NT13Fpw7XrhkMDR4C1nDaBPnO4mWw0OLzBwGOS3LtqnGfUDDcHj2Xvw2E5PW0hy6L73Y6w7gV9
fgIPb/m4nvu57aoQyGES4TQsJv6vLQGDGFibXvgKfJUBjO/F4Gqh0/Y5Uo52uWFcqH8pDBaJtJcg
EfA7VBBfD3BAIXeeqc4bGntpOSkMBxrqh/+gQtpDlPZXvcWeHJFrVERUUd6QX2A1oIf5m7+za3l3
n+iLQKF3WSDPh7iG7Vr6U3LxOXNFFD9N8l22IMxVuGSI4jiOvkFV88vW0j5gfXYQIe12aG1U01U1
1i5baZcPpKruRFuLCkowI4/y8hivhxplUhyE9pKnXtBZMhWVUu9s/HX6ZKD1KuBDX8dJQ6wcWuDP
9vHSwhdLgXAl6sbPjqKDyCMEni6DqWjWbJ6A8U/F+U6dzjNp1kSaDaakTjxLZLz2axqjkD+kK53h
oQy25z8e1DYOEK+L50/G8TZ9xENhrzvSiwEBocNrdKOYnmBWV5wyIHtw3me9Rqz4wjLPwi5ezCz3
9LeSVJQuz0veTPPH0OsbCHS/GD8qdXRRvS1zmgG7hyiHIM2Y0tAzRtd79LGxaReIY4BXByq873IN
BVjBBbAMrE7vQ17Vo5/Q7ZBY87BgA80NwwEwxzBcX4j2JDZj7F8JXBps4MnYd/FVnhHhKnor8EX/
uzTiL+dBhTYw7hF8Gc+NbErZQte1fO2oS8/eBpDmksOHJD4cJYZ/F3lU3eJY68v1Sczj3sgsqnFM
SN5k8P27yLkiCUcj7LrahLcHftvlIvSChNS0KKhkYR6BwLra4CqniocDCYO7Yw6LDWRX4Td/rfkE
3QCDyvka4VDyRwe5xXIWK0D4GN3WP+xbOxVHtNygqfAsOIW0p/i9KrWsd0F5kVNom1GeuACYTzbi
r7TU9LnCHyUctNW32U1kDL0bBRFV+m44xJ66gB+0BnGB1W8mXpu6T/TOpOyUbUp0bcIHu7Nev+zf
vYxQ87ucdIjl7nfpDea6xV4HYamejIhMNwGyifyoL+kukJcn/Lb0FPF5SX2MHhIhPydKfkQdzLFr
Ei0vLxSOhIODN20KBnZGsp2yeUrqgF2OTY7Tb01A/J+4KuwR4tOVWhAvXy9Fs4YbJWeByCvy06zY
wxBhuunaE9ufI73ImT2BLT9ZaAKOMQbArIEIbFbYFwD7fRO9e8Llp85ASKTDz9kF2G2nQ1JRR8Ts
5QDcbw2+30adcjGfRh4vGnAk+Cd/vfwcpC0LhvmyS7ie7mZdwD3pXMbLcT/+F1y6a/3wpVQiHNUD
8+hE/s0Mr861+7jsNgaiweYWvHf5MsTByLTRSMi4QTRrtrGBRKLRx+pB9PQvO6/lEiiSlj+/oP7t
WngUMy0MH/KqKabztcBY9vYJmGOIQzKrvIoqDqILE0sLjMLCIVK7MfosCMxE7mj36IgRJh4Xyiz2
a+Z+aTQmZqtA6CyosxwAeOwl8byFCttkDPYooabpWqM8k9QDnlf4diARV6NKs10mz9/DgzRhiypz
NK1iPYrWrCcDjDJYpoRZys4zqJOFUqbjTpq5ZylJqUTqf9Yp5Q3v0EtC61GSmzGOcMM0oERpHvI6
MSsMgbDPD8BJPWiZsFjnD2mgLOykChT0a9cncJx+I0zKN74lMMNT3KKOBpyz5Pfpmlvtsb9cyAea
gvJ0z4JgT00PCjtToSDmjG3UsieSOAKbojhHhJZqyXKiJCUk9Q2cHtDU0nzW/cBYT/rnPwHQLbnZ
jB19kUBIxyCToasq8hwvhR0b4KGcSrVjp6tzN9acoHCzDvki9Zhk8jlxc6gf3SMEuC1oivIUtbxP
AsdbucfZ1NRoQ2RX7CvN2zfBw+bTsoe95I6NO1scGxD6y0GyfftGy8sSsZNuBD1hw1JCYdM6QSAl
97vPeyaFukP/B1Q0rg+gG8QtY+pGy8cIXAbVzcsZJhIBTNRlA54lT+0kLom6YgAAMt4z2cq8FfkR
esC2t5C8FQ+eGtEHeU6Q2hKvKY6PLTy0PyrlLbQjpP7L5DWfKwf4vE2NfU69C47sFd2P013asPjw
I6tmS23fQLKtuVwWPRd8FRuwKfShpwiVhQPkwzNsW+HRaDcbSFXt4DCfTSmBVqXmJQmvGPMVG1ZI
NN0YERYr33IIERM7RyVgDAbKgt5sTRpg5oer30AXALdMr28qUZWspdp8dzcBdYwKBUMa2d7oyA7m
BKXXw1pM279CO+hMxA2/wX349IGaVER2vhTrL5uaXDFLLmOzwdbzorb6HAk/i3BcFt8zlA3sj8Y9
1NKES7qd8n22C/ol8feWXo7eyMy9AoI41Aq8h+fQSgKYWcvcE+YQfwfxH//g4CiV8rmKy3kGaqr7
u9JEFygYA77vyrsnTgTWg0RF4/bXLKNdBg6cbTWZVaLMn+klCA0DlnmXAB1Bls3jMfBPF514P4gX
d4QN82f8HSCElploJjQ6ou9ZiQfA45GkmBndoH0t6jLAvlr83xN593rk1hYbbIACOimvkIRoLzSd
LODBxN3QpXr0iCQaduDCiHRF0MHHhNxg80RemRfEkKfs+x5YhH3YAgJkGKFPAX1X9MVgPEDnAATc
NIzwJKkdTUC54PqKKHmNBq07Mm0kNXCWl5DwHCaNb5Z+hiVgtlZ/JMGfpE/e7Jy46AhsSGGG+/nd
8zatPajUl1PVORzQelhyck7vliMTL3vn6HfQ6UJAxJSrB8AiO6bAFN6DGEnEYkJok+8YL+d8N9lE
2vvpqRfmmJP1yKTqY1Gtx4O3E7NA9fI2a4LeHvKOqd65Bhj+GeGDnBP9ukNvdc69oHTirTWDvovX
YbhbytT7ewGd8HH2FJ8sW3J0Bnr/9bsrwLnGj3WWz7bgr/7GWlxO7cBB+/sq/1O6vFh8mozIG7LF
RNMCueQDwzD4V3U9ixTMg0/87+HN/N1tn8EgYClMmiFH5EYU8OKiwf6xrpAcVEuVIZLYAkBTNZnF
v40zcTQLDflqtWYrgn+9zkukpN3ljV5Ob/lNt9kN3v6CkP/2T51uRK0/3wS4U+FdqugN3sokLsBp
W2Sam36Z/5cRMXqylxVu7aTQJkWZcTomP87ah75OARRicg5wRIkBIIc2SNHsTvGr0OvAlDfwwOHW
xRnipoCykH4/xfafyugJTLskmdt3SyhoCyuuRwsQvZoQ7C6kmYsI+vQLFF+dX9lCGFKl2Ff7j/Fo
HBpJZvZETrLq8qLgkEiHEyyaAy5rdSEfIHn7slhfNB3exOJ4kLeoasAFCizvk8unfA1dRmgl9LJS
/yaN48kTYaijJdlJDDG6ekynVyQv9Cxdgdaj1UbYWMLHmZrU6eyyvVxr2/LcyWD75pQrYpuEvvJv
7a2hosbSuVqYd6Sq9lwyqRCUFdGbXbBArNdiWCik4W7RTCvNUmzVgGuJzd3nkEtd4vP60Iy/hn40
76Gq9ljY/PjJiCGUxyehzqVzlu0o+Pl6OPQdz7OzOj2s0MasbT3wWTG0VotNuDLi/n5CDHwEIzFQ
mVHRvsqMkMh64/M7SbvJqJ2Ia7yT9mHtxdXXIbDtWDUQH9raUvnzRLYBXF75YKGJ9JJYyoQUi86N
9Lj6UAv09fuMVRUd5FjJhoRfotKlrWjM242VIx4pbjRugJe9JLfICPgHHFo65wpPgPrQGP45NhiZ
/e1tinDcof4S4by6XkHKijzicCBueT5MljpwBvAhhvWPjc2OuwIc+mnIXaVQo3oS1xhz9eIztIvv
yiRp1sBRoqt8aN2IaTQxgg9HBKHDlv9nXgz08tO1IREysj+6W1WyLEoU0HtDJ2XLeqDVpLexjlhU
pG3Z9fGJeG41np3y6/jKX/II8WDMlB/59UjesgJ5O+5mxGb2owHmsBCu0eB/1d0oq5QK27XlY+6Y
uzMnuRNMDRbLyUVsu0ipnFbnmCCo5tuowZI4oxZrDGOOqa4aibxPEuaVFZcObosr6bzGfDr+PEcC
Sa+wPdXdd2+Tk8Ok2ELQB/AOvIkGTQzEXs6tgF5T/j+8UoCG85Rw2jZiWp8mEZC/SXm5eTkWTx5L
vJ0MT9mdPwLgirNLbIh8RUzGT/6OQFmN6/Y1CqGvyZukj7Pihw4F/PZnwAesw9wLNJD3faG8GHx3
NeL+DE0SOBLOTsqSq/7ilQ86zeQhJa9rwzYeGn+IfAs4GzAeC52oUdgbkJUOT9bcW/7OlADHuNiU
kxg9kgMwMvNjIUjTZedkxnzbRQfAt/PgpyeJAsC1p0C5eIAgYD/Zcs0YlKwcY2n0ZFaertziofTh
L60ERAJg3bNX+g+CZuqLaPlzNCJesQiZL0QDBrxjwC2xE6SHefq4MjlommTfLUpeOQrQ7MukUpKx
/t4LvnDhxVH3bZcl98LQrPwvyBsiHUd1EMtVIfwbul4vWqPJVqdVEsaxnL+uloDvo9vV5KZh30eG
KDQ8kep1l26Xj23NASFBxLEDbpyPoNBPdXtJhn1/1T2y+nIFAIjExkLuIzSaS8FoZa+JTk/G+Qt0
TLN94rVBDI6yiPbPK8ESijv16A8+k1jrNhcLGxflWYxmEm3CU929jrVJDj5kCMi0T1ctalzoWctP
2+wzDwTQTGn/P6Zuymn5l56J3W2ouE5gyBujJcMAe7Ot9+gRayz3nGRtqFo9lLFMNANiEOs9y4Ai
aFumtT/VH2EJBvucfi1U0wKKduXqiqbhYUKwICMTn1ywjCZ93NnXqc3a/xAIy4XpXVq/tSxYQy9L
pRRwAfs4F8T/TNJ584XRmjKZDazvspPJCIeGYxU3IOwZZ7MZ5MxDSucU6PKRFzqpvl33XzLBqbq8
1LkN9ld1zoYQQ0f5J3iIV3TK92QgyQm8uzKFRO4fRF3okK3a8y/3RQ9fQ883BWw9/ZW2dkPL3AbG
zoahZQLaJNnqIqQgDcCJRQXQpjNrhLvpFxCp7qB3cAi7kjcATZzgg85xaPGG5Swdwv9c4w27bVsf
5JDWORov2J1/aS/JByLtAqJtpG3fvaJUkGpH1lD4oht0ON2GanJ4+N+6wL4PiZ+3rgIlrYr5P97u
URq9zAEhyV8Idlj+l56eRx5f8fZqtFnQv1iukze2yX1Bl/FjHvobFMnbeng87Fyc0rkIUSnh+QMw
I6MNpyRFA3YUcBkUC2DZG8PYhvukVxTnfTXE1qWKBzqqzVaMEdx59aPEeQgaTu8mUYPRQARw7p5A
k+mca+EGjRnKYXCf+tyKdo9LeLcG8d5dr37xRpQ3jhayliRGoyO078RWRhyhepamfosAZSFmShmj
Y1nGfStK6Kk4H+Y7kvMWSHzK75oNQirHu52S7uXZhr7ByDnnd7ed3G6RASV/ZhROwYwOvFM7y+P/
Wc08ogWz1NCy0b3Z3suOy0JEfza8uOcFEmahOJckuvMnIKIJyRdMPuivNO9y7a3fSJGvGVTczOnH
u+fYhe7/3g866xVz9iztbPxscYy2FuhsQGvdu1SLSm9e/DNr7fNaJnEA5/1HFyTQQJBsEvAaBfiC
v7WQ9NHbrqcs0QbvYkD87oleEmjiSYcB64K/KhAs2QgE686B/h/OVVeo4O4wW1XCoZ9NVW/AxfHj
1gCESPYZxtq7jarqn4V8oi7nAonqHXnwNaHYrX58hpqD+x6Q+zTHroPwfThzm12yJS0VqKa/5dL4
d4y6l7+H7RkxMJDShZXE52LRcTKckZdhOtJNI2npPZvYk2I4uHgJ6RWQKIXpnfJr7Ynxp93c0YGH
skyi+x/fuKMnukQ0EdH79Y32cuSkV36t2mPV2gcKGD7o/DbfvO5iFtrK9aSiCJbmg6Kd8pDE1a7L
6dnWW0uhsi2w/f0RFDWAvS/o2J2M9/1QjLY9sCLo5lxI4Q3uSM4yDIm74B/o3qAjjdZfssNS0RPo
JbwTlpzNPUDiaHGTkHjDJpffakneBVEvYq6eCvgMwBgstUP+laMuFpTFXp1xjlEJEeGMqcXsIuS/
S1K6c65ldY3f4GdxoxtlhcyB9OPsn/7FcB7NJCGulIaBvRXiqeDmCLqV8p1dNVzu2HN7g0cCaeRP
x0pyepomIRGuFEqfEEPLlRjkLDIEi62CzPixOkJpiorzvFievcv45Y4zZoedaFBwbGlgb1GncriC
eg1OrFJhY1pqfTSU/rZRSS52z05KzlvXHx2HOU3nzsFeeLR2tSPkz+qyf4mpY4zQKEqAmb3y0ynP
XdsOI6RAao+nYNImC6kJMXScGFx8WpXeOzuufOo2vGUUq0aUXRIXpgljs+hL6IOTDeZFV3TUPui6
GXlwBV/3oAMPwgRghUt5u7iDnUsMOJ/JbJvLJrRVbTrjwOdlO3I1xzKaDGGc60n+G1+p+A43plKG
cCDySOOsEOlBsS0R1yTAsAvNMhkGOSXEhp06KTh0CDOYRVbUiLWo75QJOLIInX6eNssli9YoB5zF
ixkJ1ayYDkMZ66qHZG98ShdTJpVXUMITWTgvqzJgGN8HvVlPkfBskSSABO2+Sr6AHOa5tHZ/6wyq
dAiMS76WKn7TlYNAsKCf7vImJYjNzvyCOuPIvJ+1mqbBd8TA0TY/QK9UUV2IPMR3D4wpAKEcql1J
4+3+zI4aHaBewOPS7k19RhPPMRlMrGVdWh3J+qMp9OozN0+2jr1tMjMKM7OvK5jrDnOVpBeKM8qA
D2R+Dnz+VEG3wHOoYIRme5aqKSv+UL7qwZSkFkVcZ7dWo1YHwC2QDJyHLNbuK2O+2qhFk5lAAoSk
zIGO+/WYTgpbjDIdwwd+ZrKRnfmZ7u2MYBo5/psmXXaIh8rxAlg98v+IloeovtlY5UX22vO8rzvT
VRVDzXsQtQSoAjAed3ZHZWpoibCa/6o4kb/5dexjDG2Kq4peUmC/4JYZXBxxVny2+HcpeI3Nc4ZJ
w2NUK6g+EbVfHGsb/traBSxS/z+xgI3YLBxfms2eyCMGdrTbzfWRiefmMwdZeJ8Wm7kTSfASbseg
33lRzZptLDBMWFqvTDhuB043kl9oXTDQEmC3GAnOCl5iO3Vv0L8vBs7B6rJf9E1IxCadZlav5T5s
1aCuPLx3JqJ4xsyyP4i8vSBUV2mXTXJLG9lge6+7Nm/6Z3kgGfDygNRnCKjb9xorBmdCeIZ/TcCk
GDVedTEMXOfMNsEFcP6fOZCoA9ielwTRRgSai7fIwF5/u5M/1sfDwfJVa4fsaBEka7c7G51NzU+X
SptqCNtYX3m21USx9uxfIybFhRqtAxKtJDxzJTf3t+nxJjqtW4wSbewkD3J6FPtwgQcV716JIhCW
fIq3Xdc7+VnYFuzLP7rKFSjEZHYfXmQrQ7Vf6zX5pPlWqzR0X9IF8vRhnlPfNPHd0pSc8bue/7bC
zexDpxWANT1wfckXPzTmdLcMgopnChrLf2KdCvZ39o8+d2NuIfnNPbfJM2VlLV2KlYidN17z8f2B
sPI+MrEb/j786Smh0y8OLxfJddVAGRXMBzKm16O626zFaI+7ZUdvFsiDU6h0ANoOzUCnG8W1QZC3
73phwTRSDZiOvem5CD7tZXi3JdYaClFHKukP8qiDgGeFREye6kLzj7oImd4Qju98NvFLuWVLcuZ6
nntYxT0vgDhbCPeiXFWsiI3qnGcP0iG4Lg0serzJe1oitox86tOEwvb9QXuOMmoCy+wm0HjBoWqs
bJV8wJzjdNBZuEt8D+69cd4vojKPT56qlurgsFRZI1ckoo0I/3D/BcOhm/XISIJ1vXXqrg0VlvfM
+yTQe/0BdHgdcxoll9A0MRYq2WIpftdqzMHYL8n2ZnZqEB6Ud7544i3uxt7spKw8A2DK1mmCy7Kt
t1rJmxtUUZFm8kHi4kWCzRukc+C0j1wPMpGCr2KQOvylLRIZLts6mzC86hA1cfAMaaW+cSWvGpW4
prCzTC3ZUl3fQqZEKau0n41BxHC1Wx185LP9ehU1Ws/3YbArb9TLkQz7AcTfn3NI8o+nW/AoVhvV
LewqPYjaxWVkHCyz3Hm1oXFZ0hT4IqmXjbF7KN5kslnGgS7GdL5gi7BakM6jfIBvHtfa+pUYOZ0b
VvgA2fi5bps2PpU3GzlLvzOgZf9jaTu1YIzs534ckUfM9CNnnnH1IVWey16dceWI8eyZaWPILc46
k+YL9oqWNftSUlsv5bjevIsDv7hiwmHYpdbkCh2koCnmV7SHku/CMjlFTesyqWb/s//Ev//1bhde
iu0YGYlQHokYAK5XWQ4Bet/PfybT1AORzwpnAuPLldKV3r46KbXW3d/6Z4P9rkTl19jupkP1XXkN
qkh9VJFjY6LQYfAzHxtEQ4X9SZW5iyYb4lbWq9c1zTxthhxu433NTrlgNLaUj50Jg3P39PDhVGwH
IwK1YtQmAxM5gGbKEzoHjaJqpjU2lbyuNC+8IqEYOxt0xlB5TU9Mqbv0R125uYTL4H8q8YP2aZmB
xUkWkYjWHEsPHQRYSEnVGFzZBe+3dOPPV1bY2WKcGVNKq3IdvXPs2MNExicnSPFXLh3R3gOmXCSn
WEdOtOS6wnOyaReFVz3h6/BBl2R5lS8ewpRZc52sSfPkd9c8lox1MPptVidTcOb8vs9ET5KSraGh
OI+ZXJ55YNL166a9jh5NrFa0wzNU4Bh8LcXFDnFJzBTn1DK29u9+swiYY3yaCymJtyLsh0jWw5eS
Y3QxBNzyoW7HOJcwEuUdHBzGm2oTmh0pObI25f6ZXc7utV/5D9vJhhnEuOHt+UfNY2oB84nujtJ6
GcNiryWhh/jJEojwQruyXoOYjb3SF2cFfyfog0G4xnUdPxqYS+xLUZRxu4/KdGPrUjCM8gY36qRG
dBN1neky7nHfW03m2059VY26A05KfMjeMlGNXoZG7anXYoOX8G6FKmmfscp76N7l8sawslLZ80X3
j6sL6l1x2v2M0k3CbLsdWRpoW26GuA97ol7dw5om+12xNzXzybQLeyHDJd4OERLO8PQLmQHV1INf
DlJRSAL3gxloJvLxCpRNY8zx57rCGtbvxASoBZfkBS1MGBcNXqbfoTKyJYEgZOatLmJ/z/wLW73k
nYgF3qRrv48gJg4EpDmbGd4ubn2zFScREJEfr+Qrxc6KXP8rzAFKcMPSjzgtmr/zS0o8bEarwx5J
G0L64MODcN6tCUKxrtKOdVZvxaG67OtSzx537XhHXLHlEdd4W+DKwxkvE1Sv5ftuf/r0cIG36BkR
AqEiaTRrSsSXh10JRJ+vDRukFR52iwYSe7oM93ue2X/ZiCwGKGtJjghh1cOfV0puIS/IFh9R6fos
eaGIACX4iwcuZoVrOH5vp6jEHjA5QJU+09PNvY6LgcSF6prS+6KPndGXznte9fUVdyZPnRQ0eIKz
nnvDhBNNCC8f8rkpyUPBF9QnOQw8j4Oz3PT1APUME+MrY6dk7EEYUKEEwzFNATtRWfveG/a1/NNt
VHQ8UBwgZFJhehl4UlXB5xw883SvvITne17rHzg2rrbKkFDfRkWnZs7n8pm5mPTaC3IyxL5Q4sNW
o22V8mNMMkCKdbjo9HYbZX8kKDtyiVEKofBpG8m4UWhr3vnk2rBjajEb5MqYzVKmVmiIDyAKuSJg
uaFwq2zFXAawr7rBnnNa7KfmyDUsaTnvmId0G6ntTWBBMWWqT+Y+m/SjD00OyuTdIsE8RzkxVz1y
XnQuf5ymq2PGJOBfMhT7rKuQgYJrdH3MzjkmH8C/K/KebgcLq4q0FM4p3kPL0BNetrr7jm4l0f2K
e34WnwkcL8gcKd+GwNFTTjkZc2WCYj9Xb0G6G6GOk6OGZ8HwERPp4QOGo3jqR/+u0TSHOelPrkmc
RaMP91qNvZh2MS9LLA7YSFFnESem7Pa/D2IM5tAoP8Ogh6pl0U02dThsh9UWM/8sdSqD9aV9QMvU
BSKlKIZ1EP3I4Pf77XeNcPPywWkJA45Bigr0Dn/Y7S0HQAfwpHNfdzG5jIfHzQ9sWhems4TWD58i
cXnEl4xDjWhMGHC/ICuar3eXx/pv61d3gDYeneFXg8DOnDUqtinNs0F7fMXFyoEMNil3X3Pwf9W4
rhRU0UImyTnVfpuCcIEmgxkS/7+rReSCCk6jTfofMowdQp0qFE8iOrxe6+kevMQB6YHdnnIc82ys
A4B7KLLBlboqfHiv6GIxq5u3Yuzw6AJOTQnpdaejwVgxPLoR114eFquSzReDsFAohOg0fc6Ahyvs
7Lsxofld1G0nFgH87E6v9dfaZkyQsKmLRQATSjzGqKSp4ubELjR1PUVtrniLnmPrxhwvMVEsYR4Y
65VAXHw513S+1cVH+IPdYKinCTxr63NSVGMBYjLin38791FM35kOQRU6gEQicD9hp1vJaH5m/Q1B
zQd+kLuGk+f+9IFFfuzj4W+5/aOdoFhkiKXc2Iw/WYEt4MAxz2Nr0HJf2L5ekh0PpLfot5gyDII9
VyEPJ437LT7qQIHR7XgAVoKmrGesV7zHXqJwog1W+Dv5MzNV/hZEMeQEk7wstCm2+B8Sj5Khri8X
5TsFKH0ApJM32dJ33Q/LEaDTXR2JECxmIinNepWN1XFKgru3NGqaSspoCyv4cOFY5ROL/itnwj0a
z93S2RSyEmINxcolETgoZ7IHkVUYqtnkrWHrcx3fE/2//YBVeht2cFSCB73uhCO+eYgwOygZdkgl
6d8+xCYqCRKIgNy6lGdjskICy9ES5HgBizEFE4pvxEW4JsTF42BjMA7RHYXBWbE6vAR4Un57nI7t
7TG5/+yNyps8brqnSxF8wyU/jnwpPjrF/gRZOqdr+mCytz8O68bCJYU+06P1vO1IobcvsWuY+HQg
/bQ4omAZ1q7wJkIflKpBnPVLHTCxkcbJIdLT+CG8wTh9ZVYLiUFTNKfnbUdRwlMzDiLvYzEM5E+S
JuiTHvRUQcz0gQi/i/IFnQnmJ6fTapsX0+W5fdeoKePGmJfa55t9eiGh3c7rvLfyzSL9ojtnImfg
QjKNSuGdrzUtrOlQd1llrisBNe+2s5bZXlRL2562CntUvQIz73SoNauBtlfA0kY2b+b0z3+aY7xJ
Lcet4IGN/N0jt36wBv2BHCbX8IDqfsE22o7uyo8d0RyZbNJWizx9P5WZ+z7EjbFJelj7E2WI42Yo
gLstLtjVKTnpBOd9/cB91sLJb5t+XDrspRRXmUCE9pDCACcRevP/sNMzAtWPOwHXNp284P6VaIJX
Ga+4TuAULfCP5N8rT80gI7H78In1sOhe58WXKgaVy/WNmJRycIyQDjMTmuB6RZEsecKrCwDRVfuX
1Yx7dB1qQVn6+vMy58dTH3czuI6mxswxg8aiy1Uu2hAyXiO3IO4s0eELL/cdQZ7FX1ctoZjBMqSb
JJXiOhXC+/j3/YHWvrfKLMi7ATdlwvh0HI+1rz04ZePSngrH4qCrHaEWLp1wy96WwKwn/u6XNxXK
HIyc5JiUili1ZszP2b+EK3nqLYtKce2qvPVAWpurS2q9vhjYB9wzqAcgZdWl5QwVRQmlXL7kb+O6
Q+9rqFr1WANjILfol0jdi4FnqGlB1E8XxmzlUH8qixirlpaJdcUoD1njSxcCfsu+xJbOtZrsNpzB
h/1VuXGRZ6IdASuM1TC9WdnOGtWrE+/reYOnhXbEg+MmL5AUA5Fr9TF/ReOci5qgMd6Qxo6rPT3x
ogCC1w0j7GY0DzqksIw2yW8CKNkRoJ0oxsAyVVALVVsU+Se2tAjgLYqwGOmxz3nEYlnU2HUtSNzu
Ewo+dhj3tRB16Qa/lD1EHgXM8q4cDr0cqxP8MCGNcxQn6MpbBSpYe65K2RAG/nL1Ry6Pmjx4C+f5
Cq1Mt3Dhfm7TIQ7kJo0etsq4eKk/IUaXJkQ1BDCA3Xpfi3eXNGiq7lTePs5v/LlHznFIAoPTHM2C
1BMHoHU7Ja50I1bfK08lBowmJix47TyzYfcbgXZmwGJ/5ewrD2dzSabCTE3Kmp1ItFPaS3dP4EHQ
NZWVtKJA2jdLmiRvjHNClTIQ8NmPUCFfaN+VbaK+7thcqLsNsqID/AzxUFK5+jX+NMnCado/0CCz
dxYIPpUpGAHz5YVuq9IKkLsfdXClRb1s4ytIWhjRstqNHVk3++l29Rb+gFgI5KwrerCMM9t6/BUn
U3AXVX9581RcIgf+SuAffMD0paUWn6dqzGTX5fdUhGgHyMcs/OwUPjNWTQTT9DEkLL+RQ+XJ2ynf
FZbrB8EX482yTkWzP2YeraLc54OufJfI6MrLejvybXAlRCwvJFR32xeVvzms6xunaAJb/w7G8dcw
oUDO2rZdcnTnR6O15S1F4urN2g/rnbrVaXkGc0ko4plwYKYRfjMwpCJ4yPjwle1qNt7KXwxwL0A9
SzLIF2tJ7+TgO9O2+OzwsuLZ9krtOih/axBWU5SJm2IY04kJQ8mLlpgwj3swz5/09qyj/RzLt8br
Nu15yomdwwpNGYSt1g32OYGwFWlqyprz4PmdxyF6cQAjo1KN7itC1i0PuVnWcUx0j4KYqL6J4Cwe
gRz7Dlf06bk1DgfeMI4IeugDjfI8R8dZme+ywfVqsatUWc9P3X8K56c3b3IEEZjhjJd/mUzHkNFw
vMGNdx4CqrjUB71TvhdFc7F00B1RvDf7ZmhYstoJXN9QHNSK92OKminD1sHh07oNdYNGOuVh35c0
jTPy6Se5Gy+ojEZxU1XzRnXExmtTvtze7xKCeggahPJLfXTzOIVhw3lKvHxC+oaLBeKPk/YsZBfM
B0v3iMNTHECxTJjBXW/4aqzz3tcVfcUJ49sFq3VPXp8C0sg1x2GuRQ5RB/pPFrvByuI7PY7UlKcA
F0wYZUJHg2jnrJuvJAKfBNvSwct21NwPmvj4uRZEw1wiGBDfksVaHWkPhx/sOHCLkQXlTxLTaXfw
3rOeafk8g78mU5RLyb5a/D8I1Dx87dNO5iwC2e9IwmI1w4CljcUpVFKdR5dC57pqWJFiJ+dFI9Nu
GyqSYhNa/fRfkQJ9kRu9OxXyKGIBa4bXAI/ufnsSxnEn9vG98RP0WizMESztOHnEagQlcuhmNkcG
PRgp7sAyfb+ehaawA7ygDIwwdv5Rfd7j7sqC9dQi7ZZR6zQAVvS8LWa0wA/udWW2n6ytH4Pk2EsB
UdB2mOsVyw+K0JoyyBZOqPEyXzTroNBWNen+HlA3wE6e+/8qM123EwygEGkHoVbHIIzQKDPWubfI
u4AauGaFvq619LBu9Sg7XbSytJaNCiqG02sZkKFN3w/UWqmkRdwry+rBAeMjVzfqBDXvawFPvCbt
fUY9O3QKfJJyQfZi4QckR7/mRkwLI5HNV2Yz573Dnmv/51F6wFlJ1n1E0zsIe45a9nOA3AKQ8Rwo
gQvTI83r2Ua3aavwmNZ0hUMvoVfkAW85C+tQIRpZJbHFrPIyStwXo8pfUdjuoI26CJ1UYebH1dVk
la1iyYMRD0VOv93iiUwDapvXI+VuKTVMkjM6x+n0jh45OE5A0u6W/JzhfIPVPuRXrKeuW2LtvAuP
URsPA7QNbv0TIpB09jNVdUZMK0CRWb9Ft9xgYXVfnLPCt2D9RK0r1JToK0CF2qVbphu7eta+ctmy
IH6gHVxspmDUwiQEA2u0DiIXr6D2Sn3geNdMuvKngqR0bdFdzNYMkFYYeOWu/FBDnyKndGrdQGWf
+KgAIhh4m7R+G0sl4LogarVx8SKnu6cZtv1KjrVhMSalbMZ3BILxY1PjaMCw+NTEwcS8GYf1dAlU
NipzbjaMvWGmahQwhUq907Mz6GJfA4iBy22xIpVQDuXWPem1mcmvO+kzPmlUnw/zXLmQnbcO/9FI
7gTEBp/4a34J7e6lVX6f0I52/Ly1Tgi6J1fdzppiMy8PXmWjpIB/g+25Xvf3A3foDHnTcbMUSkwP
+2ZUNpt+HsxFLNQeyyXofVEAAG7Jz1ECpzQPAjdXNxdDnfcjpLIaMc64dONHs/R2qXcU4Ufg6GhD
VBbN+jib5y2bmNoAC5wbTglvaiyO1kTvtOAGBtoGBzPElZwHPonFztzU72SAOVR4xxND9CmrkChG
k7BSkaDBAS4C7KTtGSEniUQEzYkeVTcvjkydzplT3ID8h2YrnhCXrzbjNikQ8haAMv5m+FZS2nGN
YJt5WpelgFXW06+Eh1QouFF7VWsH6GwNsQI4xuwebzekRB7ONGDZyVu4ase9Uo5fsQo70ZanlJ79
X2hJb1sSiQ89qtkutEdIECtEwVq/inM5FSWp36zv8DY19ZvB6bChgd/bLdsLyedGxqkfOXIrGg+g
7ol+a9Ebv93ccNCwJpFqwCvymIJerY38xSg4Z2jIhFLQQPaLD7TqpbqQgF4aLUpORRtGwweYxm52
b4026ALZHThWGUmcyQg6P3ypr9oFpzDDwlBrRT+EfBNMPOEGJVRq+ss3lOhiFfqkpWWqzfdSP+Q3
0qjk14vxIw4pihkAbPMZ3UlFyHT/wya7f3k/pXinfY1KxvX4Hgn0JnXsguhB9iOL+q1t7cTIoz0P
qjtTt0UheXuuJyJF+zgmDU6aaizz6+E4qxr5Z6uijCPfZNWndXooxMJSrOjwSgVGTSK9dutT0rxf
JMQFMytA+rUZlWPeMmX0yXsGXxd24z0bXs4o5Bf7HHc/sbdPjgNL/1IAMbG/xo0KLsJy+JCDCcGj
RG1pQ/7YfNzB+pUfULUsYye2M7T1zUROIywTXtIxc/lM7pUHae1RHlFh/pembnnNmmzvvTs5phyc
2jONlJlXAHizDSnIxMD9+WLoohY9tCS6V3w4o9sm5B6rymJc6syg0KpT6JzSjUwYW+KsVCY5xZ4N
npiTfzeaKFvGbq4DLPT3VdfitLOZ9EryBFL9f1gjClpsvxVN8NSfATrEYop5q0RZ7Ir634gOcL+N
xJilCnMBaQaWl8GQXA+AKX+/CzcRnl2k8A3oo9IcoVcJcwYUMBxNF8Bq4V6vflajSfR2i6I6YYOY
1voEalyVYlfDOf5QRF9iBZxbahagDwWl5lR2wMbtgD2EhSv/uiD2jjCiVIpn6isVSgTQ15FHM7zw
y/s066DDFO1oE/CjkRlXpOs7Xs7h0aYS8XrhDZCNUiq8MM3+ghW3QbVxf1vwLZai05iPvNCpWA8x
ile0ptTAiT9bcU/s5qMPIV2HGWE8ugmOWkxX/EPe76BDyBn4fnYPBj3yldt4esHgWLiJAyEaY+5u
jSFSio3nB3j0LmO0DimwOvwFl3fvpVYzIvQMk2VQg/4lbgja0F1gPLor2svgGu76NSbKa7ycjybl
RF3Xj+hM8qSfp+MCbMQ/LHLWqpLouZvw8A+wh5/OUUWS0KLmb6A02PPoUQspgcSYjWJy3Vj0Iw8M
v7LEWWP+/1ujMXnQBkyFnL5b/KC4923jK9TPG1Om4C+mKTY0ajVVnk5lNhJxi75xF5CXmD+NdYYr
UPBBiIOW65QAkBESBFaOrMsxeVTNkpVmcOt0a2Xp5lOOpHh/5zGN/VDyJ88buyHSEgRS2VtWOc/x
HzvvGZTBl8AJ03QQc7uPsui6Kz8p+zCJLZRzK+Unzx/J6GZp2f80g1TVbgg0Pf8sGE37f+CfIBOW
SowgMkVbyykqxPkpVHmD+kK7VXlE98yg2U91FQArhzRMt+mPR3GvvwP81jKHC+6fO9CxRWiSvnVX
fcZteLh2GU8DZO/jP/edYp3woF5Yv9Sz+seXWqmJyJU/csd4g4k5/JPJq0t5POlEdKhPS9cLJcSi
NTfOOW2sf3QXAT1AYp4KIb/p4VhAjgAFABBLrb0NZc4rEY3Fj5xIfnyBbqiQv7M7jYvifcmgnnDD
X73veKfjtDc/Plyh4Vl0Pq2qXCzD6yLtpMRPS5Nso2PBX0zx54+scpvhLSSczmGL6XBxtvQO5QMW
LoEuxKUNYTNC9r+RaIEYc5AQpNKHYhXFS+ktuJLs4UfYZJhdW8R/W+E39/qaNKaBBhhgXeJEviJa
fnu6DgQNaK6ahpUftQqeqCtJrAnH9lzFOEBYakgo9fUlz+c8JmSUcVZy461zIWRNOxu5FwFmJ5EP
Tkq8DX7w7oVoLmnR1IRCr4/OTbGtKNN9qMGikj1M2mjPlQGhwW6IUGetk9XClNei6+rPM84xV2T7
gEhNw155VVsyyevKYwZzUM2ZCBHyAB4G+4ZYS2/PlDfkBIgCTQmFI7m281BelZfjjz9msoB93Nf9
OXX9E0qkm+UBO0iTRsO/cffPJWSO74P1xNa0zb8tkR683LfnEunLumDvrO2hd/ulTTbiu8fsoOjv
qoj4BUxLUV/i5qiCtCBD09HKLvqfGp5NS9R7YHk1fH1fWS0WiiU1534MCU7FOQpEVhSgteDnqvwL
b0acpqG1cDQQqJKOrMNypEJmaAQ3VzS7DgI291FVhU6YQKU8cilHgSLLQXi6JuT60UiU9dmtHBOF
QP5LaxdNpATB4O8ZMqA0PJ7lwQ1w+h4jOJmk8W/w3KG3XV3ljKbHsoNW1kmVoo5Tr8n9HZJTHs3y
OV2LvFP3xeo7d2ViaCa0lNnL3pv03FRyC09doW0tw9GU0S5ggu3A0WExFBxjq9gBuP/EX+9IE9yg
ugIk0eIey3jYdrJ79EzVQjmOlw3nnERuJ3c9cfC74KqqrkfIuvx//bgFgmgBJXAHDUPRgOJ8/rka
ABrKJ6aXIkVzNOTn+/VR5E7MXsNlTI1Ehhn0YpKieYt/qQc2pww9/qZrdRkj1YvmqL8rpy+tEkpU
IZ02KNl5ZUVHNNwQuX9isT8E5Tn0d/AjtJckrvAxJfMDj0H63ZyC6s0tFgGZBru+fvTRItJaEeuM
LggS7FWj7K2MHzRyH5Vwaf+mK8zEb0cgDVxCECn0hoN4VjF5BvehH7RpaHRsH+XkkjsH4QtQN3XO
7+/mvRe/j84HAlQckDDJ6WyBj77z+5CkPJrrw6aQy/EkSmN22mA2NTddYT5l/aTzqMvpzHT8jvfl
ygrkd8fmt8sALi0a0oUcFr5Nwu2SN1IE8EDyuX56WsavplsscKUf6UoW0AeYJTmTaiqDLJJNv9sL
KoKRIJooAGlBd0aibALXOVro+dCUBkidmQe3UAbH6xvsLZYQQfXTXUyNbspcVfWv/ll41C7Lj3mZ
gjHo1fqkLsa7JJBpGWLAZqwjf9NAEP+HTIA2FJRUhK0k9MWYWQWWo5Bbx+kkfbRUi0ixM/g5Yq7a
wtuGaOjMipDMxZ+Al8g/ObqhBaGOKtUXHosPJQnzKA8N9JzNZOBue/2YW9MC4D9GCzIN+rCk0ZL6
PxgIclv22Sbgj4XTbqN2p1dLUAMZ/LJJTuboVEn16uoGoNDHm8DjyTxArinJpGBW2QnCxLWQzQI+
2E5Q+HF5mYUF9C+k2JTusdzmyL7oas/r2gV0yq9rsghBGPZ/pNUDRiRJ27q/gCL6uwPmaf5OjRrt
c0zfd7CL8nYyIOlNccsR+WrBEkhbmOfKwkSZIXWWwfygotN+L0lpUHNZ9g66S/g/pLVARmjT5hKL
aXSXXoUx7lrf8ofsgxOr9lruVj/c7dlTBXhZCsG9pMy4EO/t2E5+9debahSOp9UnniGOhkBpUMAC
uIG1BfmfgK1zFO0djyX9tApMJk0jgGj4eVbFDpVO5ZBp2fWYfaBY/yVfXV/DCxQDRWSoMr+mf0Yk
NtAz2RhCYbn8z47tHwfFaitLKw8Cf9Ufx1gNykGKRhczezruzOTlvWqDtA0gjvV4nvDpCGkEkryw
DulWvN+oPCvvso5NCQcSWF+gcbzmPMc+EatdyO4Rmftov6jTSHpe5bn7MjNIldT3+6f2poH9lllN
ReRH5Yv6W8m1sNrA5wUqMnJi4zeckMwWdUi/lxcZE/cX4zgsnuSo+SvWfg2PYpno9bgrYQJRONtC
LmjR5CrHKWIyEkCA91/5v9KL4YQDThslFfWK5xj+xlV1s3+Ul7zPOFbesGMboLoL8ocV1mEv7Vih
vKMbF0VlYDmiy8P69695tN5k0A9oiZMFje9jWxMtMdA2mlASmeyhaWy3S7GMBk3Q/7p3ST8F1KCJ
jNHU3scrUTiCqJTcH1nJ1eJCiZnQ6UkgBNMwDiPSdxnCo/tfGSGPRMOlLh6BQb5cYB8yP7ZietgZ
uxpSV564wVymW6U2KAYDy5ULlmrKBAquyyG5Gkib/uyN9Kt2XvTBU2/zM5LJ8W+zDalWbnsAR1fa
+NK42lzY8MrQYIautO7ca/qkiQ7oce3vgpgRLGZNkHw6j9GUCIYoJxZGKkI1yp+40h955/lVzrue
U99YY0xwqgD9fFg6aDUJBfD4Y9Q33I9gNRUJYXSmGdj4RJoMlJkCTFozR5Cjm82aitivBvHbJ1VF
Fs3vjN9/ReDPtMpx8obykOKS2O30O2jmoX87679UfJ1+klrwbxiET4STuUwxvS++N0yJL+Pj5LEz
mx1T74xPxzkCVEEc/ATHLzYopQVJ1G5bRQfWkg14uk03ZhLPn8s2ZUMRuaO2jT1gID0yEMRtNnPy
4Rn1aPL90c7F8lVguQygUWQP9Ad5MYU/S36BuTZqIR+L9LMqAmLoeCrSB2T7I4psrxsVJQGBP2tM
PxeOt/LB286SsWHNNzAXD6ayB23umlc6H349r0Vo21RxlOE1kPP13AGNDfTg+t+GnYBMUUnOdW62
6SgPl0gdJ3Sk23dMOYJqtCMRHsw/PD1koeqllFktbjC4P027SDKldHupDEBr4/R20cnjkO4GF1Hg
3QScptmD21BY3BxqrERoJPjFajYCt1lOE5vfBFNIy1QoIX6C/leqVJUtNe5DMIlxXSW3/2v1VIW/
XtU3e1ayw2f4/WeCFAN48OfwZ87r9TefVEeuMbT+CmV6obET6jispruw5E9ZGx5Cp7JbGIWrwAVR
RAbvXVI3wQ9SVMchcdmyUCJJeNV4lXER7DK9N4mcD8F51lGYfe8+paTabwK1i1V4/GrVEFkyjcAC
F42MXs2LCj8Lu8gD+2+SYsAmdQ0bnEU+tRK+YWHOw07vPQh1AEIEAFkXQrbl9IdWgDWBcX0+YhIY
IGWrH/XdNDFGJ2VWGRJ/RpP2tzSAIM7bVQVoURPDRlqhyunRkQrdaOH/l+Jm3mnCzXb5dm39Y+gG
+Ca6DBzPPKaJoyueszR808bZv4y4e2KStXJJ50a0ofcQ8/Oarq/azvXXpWNmgQOUskJUbdwzkmFE
kD8PcCRsSN0VWfHdheC8AA1bvCSvPPguXz+LHSh2IeSxpZWI5EzRtv/KRdoj2e8LDYEmpoVAksQv
4a00VROBx0HkEG9Y1Pe6a5cwtEh4A1JdRFCWUsDBUICXPOFNi51IUF+YiYVdMS0aMzhBYCYpTt/w
sR78bEuahIx0pkNoH83cLbU3Ta217OxZdKzHo64zNQR0SiH6VMmCX/QqosBch+UPw0qyFqnQAJOw
Go1oulPx9PcpnmgGkkwUJ8Gk1yelY/Rkkru1QSu3Qmj96l1OsaSW4lM0KjSnvVnFPYex80647hEA
v4P7uIftoiEPasoU/fC8Z3yyp+uqsKdzXbIgf3G1XAecb/oRuYVvBh8JoNlLA6BeQgLphwZJiehb
AcTimonPVEJQYKEkJrHvLZb5K3Hq5o4ERZEuAQcNq231rSbVaGdOyBaucn2ZJvrDWXJFxdQ+bSjb
UJk/KyAqAWpjZD8AeqOCgPVcjPj7qdAoerhTh9gpcbhxpVDyIJp/usp9QOgiXrzG7Ss/7juPzjCo
f9gSvk31/1SBf47Rtm6yGYEZy9Pv+3e/M6qdIjT/EHpyJ+KqK2rqM/LlvkEhMDQhngKFFrONHFt0
xi3oMEetDF0bxeBOF6bK9u/w/NaZPkQPVw7cOPI+05q2l2gQi7Og40wnhJu88UUbOD2t/Pqowr0t
39MEh59/YdY9HWM8IetXpHpAj6Qbh13XR13YHg63XhcF/uKZzFGLLH8Iwc2VdPJalhZKQAE/N+37
7epOzeib9mj0I6jBdi00WTLI60xgMaMmRF2uhU30xBPLCBUvulOFgmDDhaMl1tF1115u4YQIOJXU
A6gXut1dy7rv0TUqfkgNmn4CJFxcKPI+nkv0ZRQTB3tT8pFwhWyoZ2jmrU7JVvAy12JBgUqno+pR
GHFUi5Qw/gfAh6yBeGqXO5BTqrqnB5KIV27sjC+mTsZpXyLMOTYG1B5EIRWAuazxK4vy6KhX1ykr
wakPuk7bMMy7SxPTHe/vwF8TMvMgQpppzzpqWexUGA+luKky0jLqZVGKtujTKkL7Hd7lmoo6iJh0
etGCsHDckyA3+RmtWJspLWA+ekfkPaB32EcWqX5CRgGtgytQ0EF/ye5ADkMIvEJeoJJLSOKAF/yr
9JpfK0kvVkiHgPwSGDqJ021Q0trImD3XLFe8/WmObWEge0v3S949r3Ci5RwsO5/mQdeAlzvXC9RT
kXhSPnkQbfOkajAepFCT0ghkWcGN9Zr6mkeRCfXdtBEH5ZT+aFt8FlXi3cJOKB1yAWtVpy2oMS32
hXiF9RG7SwsWeN+L0RmbT639aRm0sFP3TVNBS1DM2+1XsepLMCTbgDoqREE/DiQWhexJGzmz5XXY
+2pIPY5M/V+9+3Y3lx64joOzRE/hDU1L6SUCRFs9vl353mZOe+Q07+Ieo++T2s5dSxDvi01gCFW5
uK9suJaoZ67FcweJZRSnZgs/B7hwCu9y6tkVuWd+b5+Pt/IBwMGEt0AcVyvWZZTo19yjGgect2P9
1rvKLKy7zF6a/Bkdx3A49IOtHZVBYvUag9wO1hRnxzHYv6YsdeLdP93CwmR4cYZv+mPk0RE4QQyc
He7AY6v114Kb4qBMn/ayx8hHv+X3BonmB830i9D+yt4JGSolVr9xs0YppWN63vdySz47Yh3Y5mqz
dEwg3G0YYwwvgla5xvV1HVk48Kms+6EiWXUJlhCqLKUGSfVVJI29Q/La/acfBwcgx3yqLk9IV/Df
qBKl10yhQh5+SP7zHu4oZ9ba8chFj6XCI/H4McYunNUk0r5E0SLfAp+jv+v4vqO2fA1MH2ih2vch
xomC1s2yf/K4Ah69AU37/Fm2ES4TQjtIVFMnBnwRXfXPfuRYSXmS9v/P52RL7bNNz6/4Efjp9bm3
RKKmI4e9gI+ft/s+jx//Esh2qf4kAgKyvNb8pRi0rV9GG5aN0vISgTF+KwWn5HPgL3wCgkJ3PsZJ
wMF0uSnKMjcCYqhjDdbl+DHO3xw/Sm7NIxBH1XAV57WunkLHWABy2XOGvkAdvaWizlBrm3z+VW1+
PIYW/30GsojrZFUExKtY8r5PJwfgbR/5ObwXOoqev+ReuAdEa9g4bQLshuoL4nlhIUnBdOsuY0nS
k3NdbFfWIzEc2plRXwjeLn5grjQ4xAxVfDUB/yN+AyubWAKm5iT6rSm64X7oeG+kqxmaYMIAMrbn
KRl8zi2v1ypkTVk78VOgBWKXw7IXMYpX1rT/xJ87f2AdmgcaitxPQLVXrlIZb27aOs7DDwo15+Wd
VjRJPL1FpTykRqonN8AbtZ6Q7C6KBo28+JvyfcUSYNjw9q2ZApqmXEkLq4r7Y3aUCRWDz0Dlphme
oUSQeKVDHRbMXPSDfOXMrJvBOpZJgFsmytpJl+PCHAulcgsDELfMWmxseCu4+uUo22nO3l07vH+2
7rI6FDo7OKBGvQ5UCxCLYJN8OI+Yt05lLObl0LYmqp+97eq6YHcCrgG8fhYX1/vwPKY3JEhwLETK
Hk27kvwcRISPQEd5QDN6x72xnSnd8FIb1pe8IUUIgrbY60yPiKAD3O/KnKIVm0L/kX9yCjKRE776
N0sL4+7XIruwhKxiGVvFwTiIB9UZa79tXXyaBARA3QSq2GCkrZ9bZqrq00n01lcPD98SdnnmvaX8
l5O1NZbN1rjorwOOk3JcHa2XSIvQIzPdfh4WABIDhsPTJwoZ7UMAoDtcdbgFThlEhgOBocoljGM2
B1u9RmWSdF4ZYfaSN+MmTHksJbHJTNBIHTa5t5vuqDpt3Zpj/nkKYgBDXuUC2RBYPcD64Yde4LOJ
XitLNCGoUG/uHz1VDlgWyNIv3S7rqpapf6Wd7C4LBJNPFTdNC+zAPzv+bXzsyFz3JD8O2bWWbWx+
y5SpDtMlbgnMescxkprHnjKl3MIKfijnfYwnGFPckr32SqTnDbS8CLh+X4qmiEyODZ38Zq//OkVd
Xc4EY1o8iNjvQWgccVYosLxYSJSw4mitfCtp2qcN7AwB+gKhzp9qaOIIWU8pRbRKJ+cxgG1f9rTz
iP6Yg2CtHoJn7ZsqdhsnKXCdNLX2mWy5gPdm7BIQ2k1BHZ94ht+x6mxPRuV+W8DsPsGvtwpJcLN7
IDdnLVSzn2WnT8q0vW8xIpgvNVr34XDNEMnYvidVsmo3xHg5pV4ShqSI2sHYEtTVoURlz/qGNdAb
42kOnfeWgzodDk9goum/HzRm6yqWMbqgMpt0wbh83Yq/1Q53ElIwCvZG7UPZ79DQZ07ho3wXA+7D
YLDp3D+MVjp78pL1VsDeP/ZReH2/6DzjyiTX9D7vTl/ZmszBiYoBkHfKS2fdnqE1khNKDWnpczZ8
oppC+WmJzvXYCu/qIMOJ2mwar64FTLlh/wdy2+WeHcJw06rIi89x3GXZf1g34B9v+9KO3uaoGJF7
SlD0RODd5YWaXHXcmjJ/xFhN2jDZPDfcZ9DL/koXmwK56COl42D670jSTaFobp84P7vlDUyrm5nb
1V76N7zRVXK/PwwhZze1ry1rnwIAPqav8bWoaEL7Izp2dk0cz0HPOViX6nhZB4j5/5uX/smD21uC
lWqLIfJrv+0tEdZWf7kvRhEv44/nSXs9k9hnhEWmqqODec4FWqQCENMXlgmc0wkNl5UF8RAUts7I
A+ctVWTkoLRmv1ZFLTEDNYlrnLN8+BKpVxbbCjtJHiRNJW7xuNIOWyswUs05TptaQM9PqB4cfrsc
DcMhphZh6akUtFlLjVxYmBbfULoW30oucT6In1rMPOg3lgTdHT1/bNfbDN/JAVdSLQRyFwvPYf84
J42RVGL9e5cgQw1B/2cZ+dtZtAndFRPYoTmRkx6KDhBfJWZ0IMd5waMRC4hzf57GJjErbHsHgOta
3gIVc5QrXEeBGD6OVSQxoKttg1ql8g9v3HIHAa/RVsG9QBqOF5KXOuUiO4OPobaSmrNzeUbvInRN
xKdk+BgO5+t13ywLxU0APXhPG/1ubL9Js7+RACp3ywuG0VBHpn7r3tsQKxMuLUzHjPas3SQIPKzH
jcRUM7g/JgYlo0CzLJH4bAMzuciutlkMoz6Tz9hKsWLMzXoVVFH7CxzOBT9EzobVPU/uCw9PMwuL
WYQ2bRpuuf3Yzu8XK0KaWlsLYwBrCXAv/PfzRGL4nSKi/bQpywymNjPLLm3CsVxWaS/ALQhhT4TV
T47GHQnJFoqH1kkuSaDrjvlcCN/+O31CyCDq2d2SWhN4L9TYrz5G+8YHA5mWR8HRYohpbJOKV9Ww
RNZ/QuDn2UyHALn+6z0vOrbDL/wVQ6hcrRVPjm0K7va3Ua0ESBcvGRUrLlN1eXcccENy4+l7V+g+
mXsGKoHc2/jLZ7QD9wHbyEQkG5MnFe6vKloznWgvEA9CeIkZBmwjFOyyXQjp+EAGStYs1x2unyXA
iJDgCaqt9tPqYWQeMmH+Z1kaHmh/OFJornBQ07CvQhI0s7QScPVqLFdXjJ7ovqgQjaF33TNWY0OK
Z5GI9TVCczNQqs2u0QhOfTMR6awPfs4QirTE5nWjV6khRY1rlHqQnhvoJ8Dh/HLKaHCTzvn57D3G
7YKc3BhAk7Fc9oxTMK0N5VfJmKHuRDeDmBec8ZxmF4nSVzd1Vxh6AHgCeZT8dhlDefv0qjNN9rdF
fwChNmQV3pQHfab/TlLBLqvlBINin1goOqeIpuJDsx5Qy0Jf2v48mAa6GfXulnVAVoWAQTkAncm7
duqsf1uly1A34pAZj9Be3Xm17Dm00Fe9I7GkPSscrdf5eneedDJiZEK6SPsu+D0pNniBvEt0dQsW
NVNFpN1+zq+14VetEc7Frt/twcpZmx7uYpuJeX+oP5AaXW/uCEj//9AMts05Faq7SpVQbTgA64pS
2Er9/fnxNyfQNAL7Tz4CINVrLT/OvZqdCOHWsU9J/rvPcsetjT0zCjYWnnNp5KTW4oIQOicqSuLW
jE0d7dibEwYS/q/PBPf7/JuJKvY9r8T/1AlT6qaYdjHsgPNzJ2P/mZ4R20EXuFQNP3lp+0MXSFNN
tjOUjHVfUWhFCXOhAJMZGlqbUwMVTBYNumrodilu3s5sCdLpMCPu9bv1E70dEwBtaV0j4F74bI06
2kSR+noKA2bRzh+rBKUXSvJzfz7J4yDKXhXp8BLcp6G5qZSb8HnQSDzJE+kXuGg2rzUYYJKvDUq2
5cdmMatT516pCJaGAD74eFFhlWBEd9ra6O896CBBtD7AVcU27TgVWUdExSiwV6WNS2OrUnSDLRbb
j1U+GCwabj/Fee4JCeHMH1M4OTQ56BdME7vAr5wbBYGDLsc8JkP8EI2H+1zNOUwjhOTlLgviDQwB
lamLqyjk2AQptSsuVB77uSzLb0rCoHjJvmLXxlwbdkoGwtfyIMIrC2oGp6mntwe98HtGyxFSdJSQ
z4URckwaVWa2lASaG5K5NgzoGFZdpXSWzTIKIOSQcLXmlM/QINZ0hUnkwYrRN1PZ1Ubvb1gB57Py
KOpZljBGFtcpN5T9ws3ww2q0c7dEEPdL+OHZUKScOhJChrUPaebsy7nw08Yd02sQcolgD8TbUQ0t
Yu+StvFXq7bcipW/wFd0SYtaVHPwuXeBbEUqAfy85yL+2MtF0n80tEn19eGA/An8Y3g1Z9DYJ8OB
vY4IC4wL/f+YbNSA+mhWVal5RGFXjiY+TRXilzrh9HBx5FeeJu2uLcmsdIHLkDrHwiIftBxHZqUf
owb4mGfJWa3cDX8Z25uZ6633pYUUjDmxQibecZ4McPXoXeZIKXZlgvVA5Qr2eho8zA9NuDU3kfim
KpO2ZDG4E3wOsWRe4ujKv1g4KVtifDizLJVREdmx+2Wob3lZ5mKNuM/UYAiv2cpawdbVYNdN5nmg
LRkZ8H29Y7mLoXeuhnC5/t2nMN4HCCdjIs8Yi47YclH4PEWxfDDT0CYwZJMJaBw/DD2h1kL79l1/
q2dvlrq9DGxpiU72d4ZERFlCZkT7X7Vee/C/menHrIIQUhRkNiYNOLl6rmWxLfGxjbVfS1chttl5
Sq0vF0DVs8T4kOCT/dzjqkSFcUazE4HSt7IBSXdNLekMclUqyGKK5ciu7Dcq36kvqFhBIcRmGi1j
Bwabo+9nRd7TJQFSAlWGlnzcSDlI1B+pEbZJjY+7oz58tcavB2IjNr8ziW9ZksZge763hRsuZt5w
pnQfLtap1ZzZByhOUVpbrPVYELpzS8vPF1VAw53pmqkjMqYxnSkPAZ0hn0W9jTwRUC1h9B5HtlRg
3WXK4kTC26vMMf/OxtQn4R/WXeFQsWgXfJDxnZ41gwz9Ro0ZUQZrASXC15xdDBtfxsLYvVRQd39I
ud9REuk/Qs4I2on4jzAChF9UlHbkW+n9xs2KGBmG9em56e96L+LE5bwxxy/2iDWx3zJAeGpc7EZH
rFGdngW9FL0YTyp6UQC21e6Q3QHwXqWRa416WtvSp64dPojn9rFZBXfqJBZ6LplRpziBKC4ZmRPB
QROsL7ILvL2KVOYHyqXqwfH7QBJCqryTSanqIaBEkOk+JURAVXYHCOMjBDO358x+2yaQRRflJwjM
iAnKwVVyZidzQp9aDf1FDppw85Pcn6ol/R7SZm5nMkHB/LDjhWKCYI1QCvIZoZhAPMruiC895T5c
xXaK0MuEbAMDz58sjWNEglZBeVJMD8TspLvT9nwQsZnkOMXZVKi6ddN7GmQ29bHW5TKv1vZiBJXb
1X4v1eEjYEtOHjIDI5VooOgF7uVlHSG6572p+kKnC6mCqC3qhnZi3jOWTsdM22Cix0qUyfQ6VP0q
RVbcFZXS+GnwUkWuSiDJhSHcKZu8y4JxY/idXRVwKLTaSnyaZd7a/cijwzBGXFil62l4Ku6VQfe8
+0aOaDJs1WFdgHtX+7T3R7nraaxeu9rU8GHOEhoVnzSBoWepwh78sQjzZf6ZAfUzhvaHT/DOg9lK
YRaIXMAWjYYW1thb0+ngHwBjCXw63AhNwCyZvAk7lEFEhs99VmieOniwYLRvdJHh1JtTuQnIHxA0
Mwl9D2GIVsI6OmoQLX8kgiIOljCysoX2ifahmrhAyubMaivrOGxMpYbQQQjt/6hO0nR5baU8gjCc
l71uxT1FakHG+ScUu58K2T9jQwC1iNWkppAmjFjzS0260nznBUVM4fm7ME6uczz75ypS3O/9Qezp
EvLlXp+3dfZ5Ave0HW3GoGH17jQN8NxWlnf3leKBl/r88Jxw0L45g9afdiiHRMUeROXIlkUuDvA1
Fp//QJpaGN+JR9oTNchjqt2dxtnnW387X4CbI+GFjhCmw3i/8e+by1l591QDWMKeQo0agvsry1n7
zMOTmG5WxOwBUvl2oeGVwJ3d0E4Qn4lUKOabeAKU2jH0mlauZzHj8/CZQWwqyoAjoj0E8IVNVQJU
gJXexcrOOhc5CcBBkY6GUuTsbjZkKm62imUumwwgjGoBfSXr7m0iqlJmln2MBjUfOWdKNMAC36L5
1GedG49/mGCvk9sLCPoNxllmn7vXiROMctRNU1eYN4rRqBTyG4rN5akZmPoqt6bLB43PAaFu2HCs
4p6i8kCyxOzUwsL5Xvqs3AAOFeMJEWITkwihfuYQ5+CXV5A2KE6o1lFmvt3KlJ+SweVEO3tqDXAF
jmcDH/KBEbs8cjOv9DFyaglX8ZSVG6IWe1cq22/OUHaQtDfChFW6/W660zPeFea7Blooxo6w3vG7
+YGfyhWA6PvlilBLLtN0hca0t/AVT6wqLKS2M5RIzNKWJqg30FINqRuEIebpT3ZTnJ6kkM1xuNS2
a76aubo/G+VXFI9paxtkC7BH5MzkFb3kAfLSFFvX2eGLfF+hGNP2hTUHzz9f+aXhAbbeOu90peRR
AXebYflTaplzA22PZIJZWrtLIUX0i7W2XU4ehipd6QfV4AukM4S1+Q48vxXwDhh+Qrv7YC3vILhH
s22EcfeluN20TWJNgDVzlh9sz67xwFpCJINTvlLCtrm5aNwlsM1GpHnuKlLgeigOg8W1Px9g0TiE
6snO/nHRjuatqwTpkGM3MQKXLLLW+Ub7ohRKaIXOAw0bO7dsEz1sjIrrFtK2f5+KV1hpHaAtqegI
3LlbqMnonRrDwGiRGdZICJ4mda/e55dQ9qgy1pWfzyIyPQ4z/xP+JyVN99yxqRFGHS4RDgvyEOdk
y3M4f+Ac1cbAP63DqxgHk3XIPfenZs2gwYpQ0eFBDQKUrAdQgpyXucQyEKb0E1B4DBa5ypK7PqgX
96/LWU2Dq9jIF1y4/rzE2GoohDc8j2PYAIIkzfa0HZAYzHobCU+gTQNwPvz6Dlp5um4O45fNRtjh
Jdqxo64r9Ppi1fppXqTKOaC1C5SzO4IROXxvqiIPpKEKf3brYvP4pHeohrfgB2NfBaXccszn0xXs
ucwvaJKHdqfRlLkIHB7tTujdeCZkVMvfwjnXN8TIHDiSKdNpTPJ9HuGnloe6b3I4lm0x7EghvRtl
ViZOhlMMMzwX4xSIE32zV7UeUk7SVBa0rEhPmJYaynvej3rY2UGOkGpowR0KJF7oRoGbdi5igFXG
PTGwBJi1NL2ZvfVTcOeW1SyAjad4RQBPyvNID6FUzcCEQH7WSNqMJhFnt7xTjWXMLQ5eHcp73b2T
4l0QS7NqW9W+GCn16B0d9YW0wP53N/qzq0mD5QM04D4e4cScToBydpHzEr59itxiN1ph3UR9R76R
fSkUkPuWLCdPM7t/+PYh5rg3aqGe4YIu0VqkXyGQiXRoy6g19/l5fVfaMBqXrhvFrczus7ayi503
/af34+9BUEmBbD9t1wvcZdBaoRMoG6dRmXiCQu6pnKo+3u9Kn8Y2nROmFQGnmzP3PnjtVyPvC2sn
5J57szwLiKXFw5mDqLgJ8XeJi5CCLsXv6W1xS7mmrHnMC9IktSIK6CXDkmPuws+pSTcvYekhx1SJ
aTdJ4GVUWjBwSGRFRKf9fqASwOUrAy49jW4aPNeaxWysqgCrb8+Z/Nju0u4H/LYt2ICoAtJ0Qgkt
16AfFhsYP+EtS7oOj3oyEa6jMtybmk9soWlL7xmScoMulKR12ZRzAOPJn3Szz4/4EXeUGX8y/n0R
2tRcQcnjN7j5elFqC5PDWddjOhSLRg/PRkxvnPndwLIJx+BzlLQhEOk8P/qy3wdfmc40pFzE5vqq
B0NDNnZGh8sZF9hTjutkTofjgqRst1x3kkja2jGk3Y5/kqDEDLpHrDwwKZCl8GDO63EY81etDNyE
7EjZR5Yg8k5n3BtkETbkeN/6u/quz+Q6vO8dqG0hLRvytrF+pfdouB8PkYMHRUIjZWSH86AfU7/Z
whdyD0BBsvFOwrK1qwPYW//xgphseYK1+7mnCSwWWmNkOWG/XzNpjbvGikX2mWVPnbUGrjzV86Ob
xJemH9k8zE8HMbMqWpFlsUncGPUdnZnQ+ibjiySfNGqyuJywJ6Z5kID0BvH/H1u+AEp1Hs2moGPA
70Y1CmXC6F3Nb4j/Z+lK84i/B9sXPZKdMv5+rRk4E5nh8K/hfT8jYmwKFZbyPDufQ+40uC2R65EU
lBsehEuX9MMV8lfPI+4LPftUKPjRFTSob58kRQ2gpYiZAH1Pzf1ggiBub53p6kzb/T4kHvbaOUAf
LHB/TRQWw09CescAtqK1FM2KVUKPOT2qYzeeuKHchcWf6l8OeKYhlgAcy0Lv3mf/wWWLD0ctJmoX
nI37wjpkD7XLCvlEic5WAqzaFiJxUSXPN3u85Blwv22T+FBiSJlUWj+nJY31KspfM4c/Ou1Cg+WD
Dmx8rA1/+herDyxsjK83zyJVjLJwRLSDCcPa5wgNHm0rcebt83jjOb8VYBGUpolkWFVzvYkJjnMg
ZZFBtjlNLUw1jfGypZZYwa1r+HXhajWohw8TWoPqMW8i7tDeUFK8kYEsOm+epj3q7M8+khh6yNaK
sy+LtTm3oc9PjZLPPlqcZQ6OvO/4WsI3/ustjij9QUj2r5KGj99Y2ivNuqaozA5B52KLu/h7EpRf
GjcaiDUQRxWCxfIfpl/nH1vM33/rCdNfg8pnbKB/SYIUfbd3oaZZpgbChz9Q7VMoQtrRfx5WkUf3
FnvwWd+tI8bZLh1w8vKu4hkb691eUxHu4Qh2JfLWpMVkRPmvXN7z/Wftn4Du3jLisl7k0WJJ+bCV
HddFVp30aiFufMvlwnmvU05xrV3xvMMjThB/kmHhftTfOl5NbVPeJR2QQsjUYpQPj2nC82qb1E3N
KYvywZo+u/EnR1DFhK/ZmRg6aKf5hsNFaCwgs03j9I1cxnRLJttzUafj+UA5T/VgIP4ptBb1NGta
4+XZJyBodEnBAL2+2BbwgL8FHovD58I4AWnsYWT1DGEkOz3H01hvA2Jlv2pV/LByfxS8Y3j3uB9a
eBNL04rGn/aaH0D5G7VhO0y8oEEU+D4PfTcvsWa1tVSbHero9BuURY9a7oPL1c4xM+xwW83G5+pv
w+E+jH7pNZ47WfQjJ870utxugzjrh3G/wyLkpyqxrqEiN/whKXKxzl0QbJAyNdh2oAs3WbnwSJ/b
zB+06pIVkfloaQpBZ+VL0qGu3V4BteuLW4e3hsX3s5NfEeP13Hc5YUwMxIEE1Ird6rnXn63812jV
xYKNUfBZ+S/RPMBdNAdITkfmrMGD+zx4AdCmx5ONLAXnpZzgtMuLUYc2gsVjThBVSgJGkT4BNmQx
vuPOcMX7CnKgogBUNd7M9I3oKlDXBV/2Bsmb/morCyxcCxE1cidmNnpm1okAgMmLwUcw+AVps4FK
1HOzFMeSKYoiHBdhdt4aS2oxzwwUPeSyOmaz/SV4Qg95zIndvtWb0xmM+TdxGh02uAzpJTqUZTdc
5U2Otb8VKkdeu8yewADirM93HCF9ZLdwjuq/HoeVusmvDe4VORFPZf7q8Ph1k/agdzUOkWSXasky
aXsoYRoAKFELnkEVIDybIaI7BiRu1HN3+Z0Ch811yfmdtQbBdbVSvaoSOUqPspr9ZO1WCskKSyu8
uKbNNuJ8WS4V+OzlEDE5ONJ0vWpzobJAYCVYoNIfdHJOCEdJqcFXMlxJVaqnMjY+/3LGC6Binmy/
9CMSTjR6fL1Bl65zQlIlNMuPZIkcgHPvUBhdICMPteWSWGGD81RmRy0bUsUqikZYsakTO2vzBr38
jpnk4DH1sdu1tJjC4284eDAGYGwLBa3OYrNzWwNKkyUXs7BxRhzyDpG3f1smgBNojMMabe+65cQc
kl1XiR6+im+hxpxWOGYITE9QxjIuX+Bydc1LLp+Jo0LVA6L5znsgROxcrSX2b6+Wg0wRPhZFqMAZ
GCMdh66xAmcx7+J8SEqp7ZBW0I4sNNspQxiEtWPhWSvjPjJm6VeRvZL5rnL9VNTVM2mJ2lidg7vN
u1IvFVf1RByh77Ta2EFiH474IaFHUZAq6Wcm5jV/ceRn+3OBNwXLzE7ROPXz8O2ssgx8NqBdCJEY
aVdX+K9h6O5ezXi+G2cGokj046o9LjLG361ST/3nhpVYm6LjqvD+g5JfUoNMrUG/8iiCAG2DMz3S
ymiSn8bJLB/zlw0TCnMiVemTMyFTz2oaicFefOBO6tkCrRKQHOJBtZyNcCqn0RnYMvvLCOilVg7K
dWAMLNOHRLqF6UHM65iGQ6O2+j5fBNan0xn5otLWaqJ4SJZKeQMjed7eY0IvTzBe37sAo7KCZWlk
p3CJXWRyXGE6v0s+pQUOQYeLDqjXafSexDLrY2sGYwM7nYvVGF3pLn/lWmZD2hBYrQUPWWqbQs0n
D1ONh9XG4r25IAuPykgh0qEf3wJuwICDBECppBaLCfNJKrbgODLdaSrgL2W1crFxA5dVu5mwnBsR
yD21UZt3T7a1l4jGRsYhNcpXrjT/GjmpZAs9Cp95zVkzXMYJvSBOIWtPXja55ShNP7Fs1wk/hCUY
XiLdbbTuaYgSFnIfRhI5HNyh+Mus36ut+GANhyuqMxXBZNhMVBiJC37uKfdwn6kLIqs02c3T1qT6
h1lHPHsnsD6iHmpQLyYpsyXep8ZUbtMnL9AloZ1pdxJz4PSwNEzu5hBkUNsjlEaA8/iX0nWI0W14
79n/MWY7Uy/3VUb/PdWXIpXfZ1ijW6TdTFgGxgoLnpoH4ndHDcL5j/v3Rf+aMMMZhWgFF/+HCDAL
q6Y8WDMrGH6nTFYUhup2dIhphJpKzA9BX1NNbF2CQ5G4BNHiCT1nFAysIEjsPEAHtzjcZnQD/l/6
4tzktik+DI7t6vbu3Yzh9Yl3RCh9ghIR04UQWvdUgHVoaqK1rDoaftCqnX8kmn/NUiICKF+VceTW
YMFBHDys/b15315/DAPGg1XztFZz+Ex7cfmDza7ZQmetNrHn92IC2uuqXp21Jo9nD9AyjuRu7B+E
O6ycdxU5P+rY/sG2zsFyPuT/h+GAFAM09CDqhTI3z+RJUkTYHynBo6r6QBmOb51esbCjdsxxIaZ3
dSNedhMBOxHkcNMUhf9PvMEHrLnz1hRrXCMKLFu/fo3Yeonm2mT6X1m0Ki/h0N4EgoqdnComy8ek
4UiiAT7FBHiSTcQQlj/yy+0Bl33to2SeFqMYSC4/A2GczAiPTfITpy44KDHRkxAPF4Ai/cEYuvYC
0ZiPYcg3ntt9lQKuSlKRIAyE9mYTi3LcKvDqXk53+7XprL55ZiKdUgQH45VDp5sosQjpY1/2GDhD
q4Z6PrdxMOggGcJMsX72XETB09xUaUaQSoHbIN+Pb5sXwDsCGwbb/pGgRlKwIID7ZIduChHp53Rq
n1Zu034/qQRCV5Lgtsw+2D2jhkO9/B6vN3HW9Bn3rrtkglrM/zDM72WDY5mcpZ787Qeu5kAq14Nt
1EOsurxkRMznJLIDIGiEeMWUB50dQ5m+I7uznaxORrQ9KM4eynzVber/hXKINfd9088Fn3h3Vd+j
OHn+hcm21sm2/hKARZt6SDotfF4bGyInFuzHIe43rmVHNTlA2h2sN15zOQYqlexAbel6llrX3FAO
JxjYxGV70JsD/taIPJbJQAZupjgLWaPhlsXwbGfdDM2o3iz5hfc366viXjg/tiLFDh0mGEX+Ak5D
RgEzbaCAclNjvnDh90zDVtoQb8J7Kv3nlKXPOQsm/KXtDVfK5enavOy4gGV+miiq+96KOzkBoUZJ
5lIPaQUTwQ4U8kelEoSQ1zokTH0zSSR9K6FvqkzcrdMY2BuJYYJTTbcOG+ERJsfj2A4KkQOctX3q
O8oOHgNqwm0PgZMiKAqKehWwxnIA2dfdTvEPMMnZHvR7FrfPmT3CltOW9f/sj1ZbNTI4SrQ/TGlv
BpckF1sdfBqvv99AihE2jxKwtdaYs/W+2ixaIrwx98brwQStB1bCuuZMbFrJZU9qfH0aWtLuTZJY
ZZsVNjPoO6JZMOVyqlsxiUUc3wdKkdL7trgquLV89QsmsU7Lqog6mDijRMnN4akqJbPFTv4xeRCe
TKKtO2kysFGhkApu75hA9e9NOS/WGSP5Em2Qj5WCs4kAt1kkNr3KXkj+a3ZLdExLfrsAvXa7paSE
rUd6QcLX1ebgz/jtBOy7TjXfYJiImJ9PH/6LTSgyliFrH8YuPTuBqDmcAz0/uX1wQcYJk5sZjGNV
OWtxYOQs0K3EJNyQIbpud2aM5r09XbDwNtYBCeONcHsL+FG4FNtWkDE5nBJB6WBP8F/+lXRaHiSB
g8dtPcUSRPmThYkRidG+dOy8J15sWNZK3LS6jImTzFN609hI0ob8vyZSY0gbyFPmF2+RzeOMf/EE
g7Lquy18PVXeXCbSVLw84z0XMaZ/zCjA1MntiEvgmoQX/S1WIicxAD7GnjwxQB0hwGvldTHqwsRp
px5HZZN2wUfcFUgiSd3m8Qv/TZN/t7jm9tc/IKAtcfvQtLSIzevGynoiJyPsvbZX6JbwWZ0uI/jT
mTtRkkafuPmtZLAH5iXgH8QfR4OqiQeJQ8P2CkP3zKnLgmrptPyM3TTnBZJBhMrpLj4UHGZkKuyK
1/DBLMF1mKXOa3rbsRMYeejIw+mQ5soBBUFGRZLGSmTG5CHYPUGacbHnDqux0P6vyRNkOdYwpTmy
o2blWuyckamw6OXm6N/TxeJiDLHyTTqt/F20yHoOCMV2Z1JreH7fmQUaTBkVnvslpgqnd+wSu9Jc
TMjbt+82S3DWtko3O93u5ln9kmkr7gMgLAx7GNQDSS1XUKHHah65dvyNF6V8hS9tovp5bOC2lGyP
Us6TwiyWXzOMzCLu5mrQWPDOXpLaH8p5mDdOXFezj9yo+G7KNo2UHrExCQobZqvzO8lwghgDmM9S
S+9uqmYThM1AXXOLh0ysRR9yeKgMYoAyM8/1P4q2In0N6T0flz310qjoKJoCbtKHGMScdV16dJ5V
KJpy21jfeMVPV4q/mmoY1iAq5Dfah7k11NhS1vMz3Gc4eGvUKqplu0ku0PvvC5vH9A5tvVReB/wD
TEzRfPCr5GNxXq6h+sYRpu6Sn0asjfuIIdk+92JkcPJ3/Hp1KTkCZy3Q+PrneJcgqLg+Yd11DJye
LqzfGSgMyQOf1kL3sPonejK+MAB1jjsGsGDaP50qS/s6u+j1Irxwrz52q9LPoBY44Lttm4uRSN0B
QwvruBqI4yYiPIb7foVuBl52dCJRSMAZ5kG0dQhAzOJhr0YH1eG5rVun/fP/ypTfMaIzw3nPZqjl
+t6+XtLzRs6bfXjTkODVUKMe7Avg7OSnYus9mep6JwrvbzjHYZqW4aXLqHW4K93tX6xZzC+XMhqg
A4yZP2sr9PSDGihtcPR6fIXaBGT/4TLASnsxOVbIdyQUgbd5PY2mxEk4qGAFzoRQxbXhiNQSGMD1
o0yjaVVydTfbIgor/FNcDcAnx1NOZ+XIwaZxWdqALJIvSQsgSjAUUKbM+F6PzwOxG6Het6u4pL7N
KfruzQzo2cAHYc/vsuJBq/2OxFEuuC9ouKAbWYoARvLW6CZ8VDsLMfeN+1yzXXYRTw/uDYNt840z
aZJvMkFllVkafqHF+raxux1wOFemTnFhVKcH77b/z6Qh0CMz12OgftQY6ZLWYpcS2ePximDXSiIl
1zdEpp1CVdWQcks6y79xvYQbzgcK5U0bIRAvFBmwigIODIixOogXHfS6JODlG+KKFNNRw9n2jPYY
ysqZLq2HlgkhrwIwwOSFo3ghaJd75jHkcVL2raCTTOHV4TYhYqmgI6uv8jhRoY8benUyT9cA7Qxv
Bf5Fd4slQOFzJSobeWGmUCMMBLNH4/LlcpC9MrGSIjep9oGyob/IfhWmBzx3mN6omSP77rUQl+I8
Le51vhVIKi0Swua+M2ElMK9Mq3XTvYXH6RRFD+VZC9LK6Og5k6cLgYK48dxVAsPUVBa+5te2QzbS
dP6Po+fuxdBbUfscWXVLBOLOZZ2QO9niCIBA6Y1ejdFf6Uv8HLQL31UZDIT/g1eDBcJzsWo41eq/
KTCNp2CnOAyd4LKo6yKyNhZbpYvnqT0q/xu1FjSxLLkf8d44bTbhIywOZsDFaaLGwJ47G3fqpQCr
ufVUBcDThvldcE0vG0V/YeZOx59rsaU4q1bYxqfNSf/KuHFRUYWaDp7Rd+nEV3JrlLCsZmn5//42
CJDci0AkATH6QOAy4FHdPJSsZIbk93rUteN7wTXrisRsZmaloRUiF3yd4q3Br/MuXFciCUlBMsbl
qy7qI6+sDD8IBWMfwhmrHs6Lw7DaLaa/gRAP2OO1bJ626gcvPoeEx3/v3E1isvZRyb6u/t7RFM+H
pfJUocMlCMXbmIUioT+WCk5c8gWJXNaBSedmVSdR5j/2jV8Ouz5g7VuSb0B8VgVidOTD3jgNioFq
WryKpz3miQLHjDuTCHNk+WXxxiNLOwRcyazLmkxNidMI1UKWSZbA1U34bqempD2XYeYNitjRwRqZ
/0a4diWpb91zehrkYaVu5idPF8jPyZxCmqQZSWtTQdpdWJw+c/7gTFixCNL/Drbw9WOYsQCjHbs9
zkSD8z7p73kU0ZuFRfWJ799kkRr8uYREabeQ5y3IZgD5cFY/e0zf3I4w3LjM+m9zorfqZ21jMDmV
OGpLOTMTY/DxL5w7wjT7qF38ZKg8/DD7180RgDLrM6KgGi4rQkxsSaSIvm8Fnr+yjy/Boi3NF3oz
BsT7P7ig2K1qBnx+sQNNvTwo0ozbyvstKnog999WOVTj29zzNEfysgdaYRCt6C6Rv8/iDLxsm6Sh
daZNqbsUYwyklhRN0h6ERF5anNJ8XNuTXh10Tbtr6VisjiDG7NKElo1HN62nuLXRWWHogpa/fcX2
I51h+moR+hBUJs4dq/6zuwGlwdIj5VdulFNVyVZWzIZGD1dvI4mCZHLQUvQFDDV9cgIxthmbw4d8
2j0pZdDA0jT0iLd6xxsEVbu3GEkdzS2LGiLd0LX8cc33rZ7QCkCLiU2iWi0cFwFHMP38VeQYb3kb
jNtMrDgEa0EWa9Zvr1A8DQ5krYGPjGH5YbqHIIneZVk6imY8RdB14kEuugh6gF2lW7q10v3ssX83
j8KT1U4s/U1suKo9cBVnqGucfXgKa6zOwX00scRSnG+EVbWzoG6y+3MQGkeVnnbljcwQ9lfh7EUU
d1d73M0gIt1auTyu1Te0ECjQcqKbBddm2n3o+2O0TYFe07yri5EF3LReZlxMQvilq7Ensu7qI4H8
YVtBvhyD8hKghXC2OU9y9tsewlOC/O6H/7DIxMFouJcCyLwnRfAqB8+Ou1KI2tV93uUWXIKZghMH
s+ShCJCQz9qeNHHaNdmxzHU0QaM6YqlsoRa3nqqpW4TZcij/DevHMai2Bnqlx7H+qcWHABYTLN2S
XlrsohIlFftbxi50FfRC+cvTcijuyVR8Uh74sQzjgu/6LB1tdTeVUp+904XgVPCVNtGErgiRvo6d
l48EJbv1xqnXeB8Mx8k2Y+lIN6dx//I0vozTQTij/vCW/kbEdQU1oqircCGGlNSLAZhEH1hD30Q+
lk3lB4eGZwP1/3D8bW6cez7u7KH3ak2sXbXd77aTQdn+QqK02MLiR/q4SwEIrzUBeGyAspIyTCA6
1w2hJv7yxaUyIeLZnlEi0Y2SJX1o+bycd9b6tpXWDquWYNoQatQN4uhqm5rVOp30VZE2RWiK0akX
xs+IDfS9q/7ZbGt73hnUS6YSd7GeutUrqpaR43x5KRYQ/8PA+MGNzZNiMBHL3rlTa68KBDjdXFw6
V1xgyjPRHzByPBAqmMPYBoAPJKBhgBQqqIW+nPa1GZ33ocjk1VTGtPWmnTzYEzcuU66n7KaumAk+
GvqkrPefjGcRWe7myugf2oe5lvKTSpFITlTu533UEFNB5jPGbKLqWSXvvEr85hexVLQoyizFLx2E
wr/YR/WTKdLYfC8Lber/25ThOFD/oFmcgaxNgn+2P3Uy5sB7Too7JA4M0L3cvBIITPlMJOqU/Vfr
AaLgODRYJCLsFhBa2txkV4MyopptOXT1GJ53WvaZ1eG6xc5lTBudPCb6c+fNQwyZR8DPQeLn5/oL
WKU83oYA6GXT86dNsL9doXSbnlYphS2K+nd3tv0+SBgIvF7BM2uPxFMSN8lPdFZQsImJTtzPrvBg
GTaRKMr2hbgUWOvykU1JorvvZ1B3KTbymlIdWYurYija55sEwAW+B4liVAoOkWzQuiq27ycpEF1O
Sl0f4jF5RVwYPRLJ3lreqANDAb3Iqa9NvDU5BRSlfeIYMQOiuFH9qbeJNOKQcjTOJgjPDIou01Ko
qX5ooIHVk7fSadukT0d9v24Kgu4JajeJ3+053QQVMNX/q5Ex89ZJRlwo19Niogz02YxUUVokI+Oz
glW8kG4wqYm/KevKnhmAcMdhnJNCsUMvdRSDDu40asxPWTvnkJYB0VDPlg3nVjRGBP+/XO2mmEIr
keoleLrwSSf1vtJOruhJLxfY8loEI2dT28lJcowvNqsF8tKpTG6oA++VtgzxjVJEJpZqF5vf9koA
qYbNJmpJJKJgVjdapaWQiVU2PlK+2Whr4yTzBMYQeukKtzloFoeN/zkrIu6WIknuKsTUpNFY/By9
xrTzDWuyUPzQKC+U4egSCi5doNc5LVo8N+75rrWqnqGpkdnsk5SK/+8Y3tuiIy01PUcIv8wSWLzX
TJM+xCL03Un/OgFMsAxnBE7lDjSEhqE1DVX+OiNIojWF0/AZEmuC/Be2WDuEYDjhKyQaFECdNXMM
7Z+xYkvophQsJRCrqpyW7O8vzlUPohNM77oNWY0YKnBrj6W5QqMgFLXrOEjz6tfHDixc80IA+trg
XDegr/Q5lGp8NOS6MXlLmDckW/wRYgNlUYkvIunaiKw5am41u3pnjMMw0sBGQCb8w5G1uE5VBGWD
m+v2R4bXkGfbDsJOClp4BCz52yTL//QZJTOJJsbJ4L+uPlyTLfJYsuUzWv6BX7M9MU5h8YJaHrUu
cP9HDYDz97sLs2kMuDfg5PR5U8KCFNDAdUhVPB3/lF2koo5r/gQzbFWW5nBO6F4ylbQY05cQ4PlG
yQd00D/FQrsQgtbu5LjOr4T7D/8zpTUR9MqAj9x3ARMAsiCJ4WPzqtu2RrvY8AU4PyShBYPv+sYy
NYkkyputURVldHvtEjZ4kpXLqzMPVHnYzLOpbNvBfZCsKSOxZ1vw4jl+VWtWAwqP1coa7AU2UaTL
LMR07NQR3nARXdXjn93BiJtSGxlzY/wXL1TjRb7aRf6Mnoxqroh0z0pRrQuyaBbYR9K56F5+f8fm
8IOJ9XD48WmBhwRBjhNLh3go7Y8/oUlBL5+7xs4bcMTzmFr6Qt3OR9QV1TJ65oSAadm2MWWYr1K4
yQvwv3iHJtYtdBt9Kh8TSDO6Okwiz46D5C/44LkL9J6H+2AM5RhDUR+mTt/N44cDn7RQxQZBGxOX
Gh+t1O9TCDuleI88NkRoGAEAE5qdxMCb3DpC2tK9px9Lvl8QOxb+EdB1jN//ILzzvXiSrsqRNT4m
6gegfnLlbWFmALO+wqHQW8MUIQzKYAfIJEnRAjS35QU8XjWEwAcDPDYLBFPjzirUUaUmTYjTZXnm
wKcZtK3bC4pmrC/S4VNuuMkw6jSjh0UHTjSWDA5MVbFAwMf9lLAsyqM0YcpXvsP12bJ+siVVMsgd
/jRO150N0D6f2MuMxy2oTYP3hRVq9m0xUhlW0wZDkFEk8YVV1l2ARKWIN5lVMmyZ+ghk+0NaKEm3
Ghnii7l5sX9JSCFYzd3+1QSKGU2btgbB3T7kb17zQHRQPtb0IldMoDOtChTDqFF/5FItkRBkAtbB
xiJ/RQvWXiAUrV303Hc4AseQQpm2aSLz4j3z/iMBRaSeebvltp/ntEnXsWmXGqy3SiDMV7hfN6uk
SCM2m3UYOeIMySMZx5nv3hIjwKGdaMWQnsnYF1inuuQxI5jGZzOcW0OuHnq7UNW9X8MugrvLXXbf
2FpCw4+lN7G17uaNmYqr3xFJaRT0uT32xAWTUIspYVvJXHOimcjjoOUFb4/u7yuz+fJ+4XX1g0QD
tEhlHtJeci0Yaj330JLZNkXqfyuSR2pDFm+6rum+BztQJHqLCWBEnp7BLrcSuwOqD841zUFukpIO
3gc/705L7wcoRmDKF6vqud1yn5IcuzYxjcSFgdhB4ZSgkwCkPkPugS7SKCfCNiLZoNfRt1yL+yIh
+qcpuw0N/TOLgMIMtTOhkJTOEb9D3KfdIdRqga40xLq4sKuoVAHVkqy7UFimliCxOciBwP1cGhOV
kcjgwnh2urLnUY5Ih1nXCkbEhuoE3kIJiy3apuR9XxJ0fXkIWRzeiE3xCQzjWKSJzWePigwNooOS
+BWd/yDBU4qp3ucZwcBv2galNTBIl6ngcT9cAIdSxGtYS4z1yPgSSLCgqT7ajoo85kzsj1RA9zGF
sNqlsEycQ8Kh9tZAreTTQrWPM6b8HkiUVVz4VxAAYRlGa0m3Xk7uL99iGHAbQtHcDBiY8fG+e8iv
TwA7b7x8S5knXQFo/AhE8aivgnFR6oeynFFfn888ZxfWRS5MluRokZmXbFhNWybPNz6y3Jr7Sg4t
5zLHsGPKldv5dYVFRuajKTasBLGtaR6UyaiCyQQdTgg1dhvVsRqJPZJiW21PqQSwvceh/L+24H3d
3r0cFWelkFzsubk0j8sPMPyHl2ljtS4iH61TIWOPfr0UCQy7gIwI+b26DE5TlSaaIArsesuABD5T
yJ0z5DUjOjrzKlvGFqLTx8nyC5y0U0eH7Xi3/cLtCEgzQ+FDayKCz9vMrlsB/+sw1oYAopnp1v47
+D1lvSrT0iqHP2JUXlg5mpR0f0d6nP0p5GxVUX6FOFBaga742a3vo4vXGkhBIxYTrcRvV1uomJLg
Y+eD8fWvUmaamAGrxivc2rg5n+XwZZultZafU55ew2lJ4HzK1CbuDA1vYBoxqeXTQWw3jOJs/3IF
Cv+a3FsJBX46NirQquhpxvaoesflnNBVDxd1YZZeTJUzyxYB89QaMkwdgKReLwI/Q2QiNmw9OuLy
F6FTdZUs20CmhK9KJ53IxoE1ZxkCWMoHi1i9zZfJ8gL9DpkRMeTiiR0/Pr6aO/aZgrI2O9HP+b7M
5Gbny0tbxt3vCTIDgo68iaBPKYP+Ipn3IODVODtDvRyE2lCBYepb3B8rnWBAbWaPmgLYoHflt4f/
v1meer4Cnh3dTbNlHk4ze9qiOoUa6ujhBAz7oZBJGcvtWeFxhldIluT1qgHodM2VCK9HxKinlKUz
5KvqL+3ToRaEkli0RJOk3DO8tnmhtm/4hHGBUm8gF3Q4DEbTSLfofyefCox+HBocpHkGaqyBpPrE
qKR6YjHkjcHYNfxulm+mV58IWktXqzUHoUqAayODMrioekEHL1GPbJwLBUZY2ZYL8HZitI3TlBRf
eWrLhxsV3ndCSztYm95rtEEjn9EKxvwaLPmJMK8TujxIwe9qk0Y4LGdKNu2b+Rt08elbulJcK3Bj
8rGAv2cLQSCbqLRbHrx52JfwD2eKG7W0sJnf2i5K5OKJYxF6T41CM0nHDJ6oHNjXegf5pzUkkG8w
6X+Trrm17BlRRXvX909Bq6Q8y5exDME/GtvbXq6BTXTpk8QxTsuAH7/aeFbu1N0DW28tkJxMfbUJ
0e0iKMkagPlajgBRaA27JN/ecw55GdhcDS1cCZVTcx03ARMOGyYJBszTNqx4Ybmcanx7VW0km3Mn
dzhDD4AmE0C9Tba1Ig9CfbSNorfmKjQ6tnp/KROzFC/GU64KkiDrSyL1nC2meN9nvaSDJzGx8yWp
7Grysrt0uT+JzoMWfxYJY74BuijjMS7Winh6W0jAyWQNfS025E1i9CBCxMSuNRZWW6bpknCPPkEb
j4G4C1lqRvDS/vwjInComr1YEnNkOXVuEkslX65rJe6tAVSnSoo+Rw5zgFAgpo+Vcnbza9h2hwxt
lPbMrajPsTMqmsp7A2V+Y1yxXcyTMl507Cl7My22ghAuob+scSGHzYFGlrJfPMRG3HtnmRwgBlsO
32oe2QIXuAvV7QEDmj4TGW6DyRn7zIT8SEcBwF0nvrj3P8+WArmONLCdUIkEWepkU5oC4eqskGRc
SxYfSrhoSoF05UKYPbJYMdy+R9h9XFY3IMRn21UIbH9EscyeorA/yWvIWkF3sd4Acss/arputRBH
jqZW5hkqoJneG19e6r+aRWVCLWN1cNwNW8pMBt9bYGYrSJb3zcCcjLEb+5+DPl9HosBXM677y57h
Dm8AycTehvF/tV8bTT4RmRW7auO97VFz9yjV7Y1KsThbxU70Bh3Rs/r/n8yXIUHwACHxr/5SIuPc
wgxMYu/F45txM8g3173IYSffonmBOq8y2l5UnHNPxEJrMheP+DcnGb8rMDDAZJXTSnSx2ZE2fpCt
vSVZcurYQ1HlTrZ3L6PMazobWbePPqEyIrQOTcaFHVtPdHqewRIx446Uv9YRzQJLsEyVZE8AgvSh
HNWav5fKJbfgSc3T+GH+Iiq765BkMlxzDAp3g+GxuRG3q6MeodA+bchbAK0kzk9f8vZ7hHFohKOR
+sjFPC2z7pA/1zRyMkRn/Af0GQJ0142xsrxwheq0K5mgWc6IvbNKXLhxwMmzsryv8z6v3yfLVmUv
kFOYE+bOwhZqj0q/mut04Oxw0RB47VDfhrA1ClHQFZBAHxttpuQ+rZv4YdL7W318LTNWbMAdcGgu
HSOqsnXpb9S26AmK34c8KsLx6qbKEu0I6orHSpEZ/9bDIhYIT/wdFfCtU8NVlcLjydbGzJPoP587
dtu5TgSldgH+A1Tcg1hV8P980QI5QDQY0/IEX/q2tI6jmc473FOcmLDaHj/8RKyZF6TSdjjbd3PU
JAeo5sNwPkFBzJY3AyOUF+b2pOw3dVBYiGTcvVWGgM8FMfng5QrqVSRGa1QptuKVJFUuarZcYNIR
LnegKcaPA7yN0pe3oaoKjOjVmZzrd+/0hsnY/xbNC0f2b/whVJXt/HRroquDFtW+If9Y6MW6e8Yl
H7rl0i+q/+XDB+x+LGHohA9JU3vFeF/Qqoz3O60UF7KmmZWOEvO5wHy30ETW4oFumzuQ+CGP7p8e
6AFibmC6j5KMwWak06vKkpVyeCjy9GGOwNV2jUAuBOX9Wk/CES7ZYnwYa10YXEom5rSXIW5YNR3G
BTlTZK6a/L87VeRPaS8iYqeAF6+pRH2HOTMzBKNKaMDvn8HYfwuof8ONVWzWHOhpIRyflYxtoj4e
VtegzPW3EVbWzwsvgTm5MvinAFR7a6Uw6BU0yQI+IM3gs5Uul16kwvuJaTsJVW35mmV5QUHk6pSF
/7Wp+4p3goW5hIN5GRbAlHRlpHKf2SJGGDcyjuwOFQfrdJEWV+fabNK/8IZbi2jc1Xkwxo7lZg3R
4zkc9aqFpvtmlSZq1UOymRGO+8uhwlrzjJY1XocBRXLLq8+NLXw/r5Ph1yvkDjhR9OrPQPoLcVS0
8m2vx2FWYFtxU4U+fdFhdHO9EC0fUJ9rKi9sEWKLLKiovoM0/DHVl5LlagFRoXgxlG5/Qsmb6r8V
aqOeUQLbUvIUL+Cq8/SmX03LbovaaOOfxuo7JfbitEF7kuyfWQLiNZiS95XhmtBoQ5fCKktSfjAz
FDua6vsG0xcLHzfYBF+hiJmxjzZvDxbaW+cyyY08m31He9f/RCdzNdRW43XoZnSB8tdqLRYzwNzM
NdojsAx9IMJrMsCGs9Y6G0/yjF7jbiDFZeA1nZhGle798LO89nby1+UavIdef2rhRLaEXVxWeZV8
4yQF91aF/VyDpddKSvXyjkBZKtf0+e/U1gDWsFvDL9b7W6EFpF+3GxbxCZ2R9oCx4U/lLtJQf20J
UlWifGdx/X9m2ijpi9PAc4F2bMCgn+oW49nvVUdrx7MEK2UdGay0H29t4Na4zy/b+CQb2j8WuplM
a2phqKGf9jRe5kACrcxzuZTYhfETuzfRXyvIG0Dr14LamTb8uHKUzKY4pVav4xTzeFkJXT59SqJ4
1BqyNjI2a4G+/TWJfpCQoE7rROPhclU4puQDt8uBVkgXXPRDoNyww44zh/F/zvn31LtG0tDSykTe
9vv5LuhcvNwiH6yOI4FiuqP7SPUTspEnzfgk+YK8naBqO2ntmp0fJbhpvXxpes7/mTVbxfGvdyi7
MiXQnwQ6XWzEPPAoQLNW4R5jYnjD+fmNbBn/wv8tQZvhqxGpgelDNGx+XXZKNFnNT3nSKNbbljAU
Wk2GnxJbfq/dsDzBiXI4mRSlpw1BmGd1rFIdTwjhZBaE3swqtcPF5hHA7TLqW1MbDt5g0cY5iCZN
ka8Dw+MIK+yrNtWsF2NqfpXB6iPDBT264lpdXCxv+qoPL6WQICJHuxN/KOmBjqmb3SX+DbhS6k3R
WTUI4aTqaWkhcktsgMn6X7MP5H4TPtHlxSb6xfqSmicbIkIdfyvZ+12A7HB6zTc7WsraArWP9Mgu
k9MUY+wrhpoOV7SXC5EWFKX5viu/Fd4xYT3SkAIwLAk6dEFla84BrkSJo9o2kFhbdEEuwVbYWAwd
1PNCTHzPzXUPY0GjxQPd/IZEv8ItJCUCuDxCEqTEjJYCvflkjpN14jdnr99BWC/K9e9Nfibf1zw7
UtzXzSSU9GBWbBgNz9Oj5xugbtsMBN7MO4YUmINyljU6OicUwsBIVQU6mS5n7ukkUdFEcP4B49Gs
bZ859zc8axRFEl6Y2uXVfwxTDqcw/76kDSGY+SwGupp9UXLU79GRMfRnulDrYfZu4pF2lS1GuGCu
g9bcrYr0ZSJnipjid0WKOvZXh7fVOrTQiaf1uEuKeS1wDoVAUDy+AYqx8S1do7Xy5HvPHMRO9V+A
Jfd1iB26RkJHYmWpDYSX5lw6EH9Idl/54Vi1kacy3Kikn4TrSPpDKS2smAblVsr8LhvF8U6XmHf0
mCjxAcEuwWO+lhJj0gw+OTXhnm6MJfpTqPTJkIOjj6YKEugLtnkvlNqGR5ZbIGK0VrAT6RqtBPTo
j1GxtHpSWMzgdok1GusI1qFpXRbhmTUK/xOpLUldrYOyop4qdJo06O534y7qfeAYxHfBfEj0j4DU
uNzLu0dk4K+JPcvtMS9nNQXgfS6YccE4URJRkEywTRKDZbeKrT9oN9iC4dxI6XKynjWO+wZLfBrM
qG6ZIeU9obWLt1Qq3N8pih1I/Qbo/umY4Xw3aLEXO0tObI6qtNya0141JFItc/e4U1zFhhKUqbtT
HfV4m1aolnL1Rla3CitE4APiJyDcwscNXyZkpshiVR5tfrxqoFOodk9y/kHLNRcIpkDzdbXar8A4
EwhhMq1t/3RpK+7vnxh5LdYDJn5PcvphwZiHlfz6Ulaq95IcMwIn/tEniuDDDaaqU4Cq5g8nIGtq
GWYBPB1N4CsF4yBSKpJt0zAW9XRD4zFcIAv50iXiiY95URuDHSZfO7hNbf0Y1gXihLSxcdEyNaEs
7nnC31b4oZBmP/1RWaAxGYcM7fD8k2gSSlLMBZ2+I1H9IXcFj7O7BDOzjAYAGInW/2LDJLJvfrT8
qf/29gIqwcbSm05AqKKTJM75JLoHjjtl+SqaC7gHO4g8mNm7J8Wt8F3q9Ca/WfYMw+C4BlrDtwck
EWp2qSCLHsHVTAFNyDUhkqDs9rlRSGlwSosxBfYTPrUnYrl3UU9lP6FKerDWFVA/VJi8WVcWlMsm
EHRzEyLveaK/owbERYzwWIbsisnqWNvpyI0sSvbGjGmkGHTc3NKL6sBontBxI4fJ36VAWVhR75KJ
3f13s65AFP0OE9bPdiALOUoVMWsHCsWZfY2FQUQaXI8VGSJC24Je2sDc2JKJULStyjATu0DYcig0
FcD7YcNWwOEk31ICqnmcjBbV0iBwKCjE24YgA6uxHOz7yDY+4D9qJFRXaJURoD+dYjRHHCxd/X7q
dWfp3Y9S+T/SmMi54SdDJXZ/xtHwJCL+eCe/ABIpaWSUEBRqK6rWTm54KS1L7BvsfOBtETuI545O
Svp4aszyyD8r18jD668OzHK8bap5ZYpIVmtcbBPSz1Xz0fPuiGqCbn8PYQGa7MIAnaVOz+y3hP4f
f41GAnqw7JWUtYZ8Cd8bGQTBlLyk1y8YxJ7qUiEJQlVonLR/wbStYcmzimhOmpV7prSBtoVlWmWu
Ut8e8RU+fiLEzqLSpVgVfsHM7X/FgXZZP+vCIo4FKYdq1OaJfozGC0KzV0uMOnd3zTRsDRSFEkfh
l6UVXGReHMxPUrY+scXqPoIY/SDspEIvghz1SzzosO20qEridS29ZX5TPVVJ01XFn72XJysOT4ip
s2kfIt33LyuixaSHB6xgqBCghraPUUPWC1+zfges6LVzPW3sH3ccYEN/xeaOozpnL1AETaawMyVq
fQf57sXMWd7K8Ry5qqd23qLhPYn7a4CCBhHuGvdK/OB7PVcn0Tkqo1CVt/nV3pu6RDy+lGqs5byd
dmlf3/Nd9Po+FQQ0Bi48a0/lOh3ib8mqJDywRoWeNVNGELDaCHqq/Ce0ZGDHlmRHP2mHSWMnWH6f
Nk8cPwnrxXpLA1mDy0k3wKDs/AkwkFx4OpvYd8xOLFEE5IRubWg9c2yHnhf1e+FpWs+kF3In0FEy
JFhmCvrmcpU+lbRugvNnO5w+4v9VKQhG3KPvSu89OupW9eO4TDeWBTptjPRly2aR75QIOgTbC+0S
UQoAsyR6TPKj+F9YvzTVvme0A18s3+2EueZY7YjXLMthcYBXlmiWZe6zuwzMCWzhnUeV4rZPd79C
qT9R4Xt9SqDAXue9aW+ZfgvK/G8wlq9AT0KQp5hdGxxmkLp/ik/VtQTlTyRWaYPQ5pWSUmK/Vmju
6s+aEmNEKHwfmceu2hFAyT2NV+LLms2EVh/ivL37+o27fUg++OdbGqgo8dtzHS8LjQI8x9BsCyqw
s9V5dguN1DiinoOiWMP5aMFA80xEl8SPemkdd4NOqTymDyCEdCjh3b118WDJxoUgdl/phKoHoTl1
Nt14wfSK5y4gimENqR8XD/Vol+rjxqSgLpTggF25zfiKOafBNPfN5saRhze9C+mA/hdLXGmeChlG
SqXkK6Ty8owNWriTd325YgvVCwDt7f1vCg3QY22ealRxE9qvZwL2uad4SnfJAAuRNx7+FIVJEqUd
5WZPyiaifdiUQNk8/P2z2FtgcRZpBD1r6YWizFip0d+ii9Aqlazu1wun/tZBEMVEVch/1+5R/73T
EQgo0sTCBM+i+kEMrWWiOo+B6RqMs0G0enzU1rEsUpQ8GBea9TYHmcegKGUWyQRYS0/h4ylxWNw5
eHoEVZr5+Psm9q9uVvL/ZK+WXsDZX4tGJ3tfeF4C0HgLP83HvH+LTF8Uy/59n5ITVHf2yx6KWgIb
ml7z9jYInQFbFhSLOMfOUMfEl6XR5nsT0jcaNZ3ALXTD5oi4oDQ4CPCSEA/7oYKgTDBk58U1rAQ8
A7w24VTu/k9YlLkCu1giSjLcR0/BVQuum+smiZbEEfXD4B0FvKl9fCWJaqXjH77V/pX7McPnKlJx
Pp+KSvR5nbgyL6nKz/xlMAsW+9+nuqtLsJRrdSDziXrfzizsb6pA5jx7fTQoxA27X+IlfKp6iMy4
JZDjxn7jYj+fwdocp4hRH3xKedGhc+IjIZyZFuK/oCZRNThl2vRLN9IgHLaP1KtS96Vtc2SEGZ1d
rtLFzUIo8l85CsS5G/JpelsYZ/CcSVJrFoTMzamv8n+ZE5razuvdtufdqDXVkY75u9gQFpD7WO8N
U+Z3i8L9qvUwMH+hz+1TJjwSpVldCyNu5lduRq6REylN1bwJerC7B4z8lTvUFQdiXionRA/HBFsY
IPmGcGEBGwzN3TiYQsD02KfuFaHy2GEAxhAkG4OZcXwFrNfOGLdzSfvlAB00MWy/D8PdjosufV3f
KJA8iMP8d2EYmn0GdW3N2++jbxdldwJWKX/cmPNE760xV4l0w4Isc0mpsKwCh/E5uSN+gulsQQlP
nBtXAe/15HKCI15E8mPHijh423oYMwNQNFk7Qlj0L4PW+u5uH4Bc9g633QUHPXvRJnc5p/0WECLe
MUVLb+JcUtKZz5dEL3hrpQI8/LUjVbIVmm8nzLUt4wBuJ6ZUxscPwc6uIIupBBiHYlCiuV0XP0Q1
VgWPnZesZ4nWUFi640PsdvD7uoF8upNX7A9g26bvUBLzCceglpdHxGS7IHt1MeRoJfJIgn57aGgQ
TUDdOL4O8amRFK328AyynfyoLNY31DuVDK2P4nN7SseuzcGIA3LMNB8qNSR9Nc+5keGMRIm1Dljm
5uztdTvAZ8wbk7rbVsG52Cw0LyyjdBxbW8otqLurtZBQqecngWOts2it4PNzDKxZfynYDDoHxped
oAy0OGAXj0PlhGrwO+IXqtiFaHKbC7eMoFxpwi3+nl/GyhQ/sTgDdRwDyNELxFKw2JcbNKnCF3TA
HdZCTdcAuU/LTWg725IhFbUxoaXIBB+EX/9eVeo5jJ0PsaQ+8RZyAvv0JeNyzQRTHZV/fo80F11w
6TO3yP/RMe8WzCVKXhmUEMtxdMoJlO0yBImAuLJ08Lu0O7xkk/CACsHaG4hHsX+LUNdJlE+I/3wK
pWoaJyX2GqoszfCGpVeywl6EWBxcawC4iyIiP9xx0UPUbVpc6RFeSc00iCsDSBZwD/Yn86D67x5g
Ymkrm47+WOq3CNWg4cHJB12TX2Qllx0xMIJXV/uU3jTtHoLc8sU2WelSi9GPmFQFfFeKE/aRnXO9
sPL4uVjyQ9LjRgxaAmBh/AWzhhdK2AlEE8oJHHtNipVtTFRpikFSAxLDXPqj3DspsQFjMagFJ6Qa
GkiudxKAfINbqHyWMZBlwZB3Tcb5fw9WhM9lSK0Z9xLvWeOAJpWAfuFKJDNx4Nz11guy5mhkfwxb
xpObV/kRN4/UVeUEvrYAAMVa6eg+XYvN6klGx9W4AYCSUeUyY4fu+I6bjkJI+q2lupgurU2ooCOV
CeF9GTDyrc5uc76I+/yTkjpOzPcQslJZBJoAbYPrtZNPl15C04iCodkek8HDAG+vs27ceznVIH0/
84VIklzu2KbUXt+ucIkB7BJ61odvz0ae6G/mAln3F5Tp+fLBNUDghH2+Rvq8QcQcXC7pUhdtkAl8
LGhFzTrJoBFAUF/SVzSrTSIK7wlQK18PEyz++BjkD/fjdpVCU+ZB9c7/EI+8uLCOxhVJr29d/3+u
xhIouaMOOUKiQdQ/58x5Vfp1zwIUIdXAUE9mnCSBS4WIP1H527dWYPFq/LyMfEdpokzfWGjs1BqT
a1B1Nnrj3dAsHPO7uugOPXrPu4IaeZ+P4Fz5B+3cTPADYw/Q3zdGj4xbFH7g3L7AXJK5M81N/tTH
pbGdUTVmtPbzmXkgLMHOHpMbCV+zwZP0k2LULKS/94WJEcsK6UWKOiqqS0rImAroleczXq6Uqpyd
UK6JVaEmVeGj4fbXwbTcY2oo3Bg+Xa/MjqP9ne3hTEPoSQ5kfvUBC7LQIZxPgOu3nzFUIM9XdSrH
LBktB79/KficCBL4PDvQieJs2iGp3mdFKc+acwtw9IuNx8ZtWQ042/QFKw1rfml574YvneudKHIv
y+rVYx/4lT3fTvUAlwkfJBkc9vLH5qnT5bm2lHK8uMLzq1HrSXpJO3qJr6WGbE7A0udgelnUbPKt
h8IkA0OCG7FOH3Fj3ABm4pSSq58rVWE2YTuoOkh0oEG6S1ssMqFdS2c1XL4SIu5LtNGTIkO2+T4f
4VeNPJaRILB3antlKRRA8QJ/SWxSuKn7CpXmbKKZumx/2ns6gaNce1U0t8QVDOi2waGQX2HKqUPk
skkSXaN4ox7XDO/lDdeMj+75AzTtGdJGsxDeXio+ukJRbNw8Y7cDPNiMktdjwUy4H1qtSm8sKdJ2
jQx5Ani8Itt6QO/x1a8RwC73Z/jZjT5a16NqXbHfh82pMheCEcQNcweY3GDrG5u6LTuhThjo6Juw
PzGZ2GY/7JjWS1JJO424MaOICd4JGLvbDR4cZDLjABRhFignrkplgW2JawpK+B83t5LV7KbdhEkW
/S6v6JOegS+vJPpXIqjvUUm/rlFBKCPUivACQhu+LkBuW2kp9mJoOVSa+oSc3zGY+WdqHPpau2yX
jytHu0KBB9FpHnjyKFegw2Tf62h6/zcex0HMFhcZrdyPjs45ZZddZj8aqbQKfqmmlxoJqWkKNWFe
y/WXReMNROhk3GYox/1n2MMBw64GLYFbkNT/A89lKDHN/kssdHXxMNqVewFeeJxnkFPZhXHlq/dG
301HoXzoC/XQu7IWQLF1k+aNWXpXHU03H9Qoy89JBpCJTcOjoLeRnjDucCEc0HKsiGtaybX2HSKh
Z6Ygl56me/7YeKwf/F2o70vXr5NyQrvHxX8uJX3ZxI1LlEgLsllT4/0QykaCxxPSz8Ibj2uqLKmK
FakO6gM2t4ZoIcMsnSIGlZg41FKF+6GD9jxxHBNDJfz4nRQRg1kWlEZoY9Kp7Y6y2Y68lwbWrLzV
s7Zyio6oR/k5Bxoqs60Jlkj+teXvNODaJPPjOzhB+08fuACiiVH/vry7YRc5HvfrfRvyu76elHbK
hXqyh2u178tARx+gx3y8AxWBTcboAvnsn2tCJ+ECcb38+Q1KNzVUpIlFdEEIVX//Tj+i++d5rVrP
hoyN0BfvBmQa2rJHThU+JHxO1ZbiatkqdfLP45lY1m5oda5wjG8DfJFvC35XYxEKTZ2vFgqIMorG
cPViZPn2DAt7C/Uuk8214QHf2SiqOOqAJU1uTFKIlcyf2QYJ4Aj+5+fyw6es4GlFxnPrAfQ08u3R
zqzquaW9LGCox30btSJte6BIc9Kuf2yCfbVcToGPR62Cmb24LdnA0RJzTsv26NRBLuAIydhtME5A
8s0snwjnbRscAkP/r3UEQw1WL5RWVHrT5tJWMcZHpbTlmF4MqD1d/hC4sb4nauyBolXngz7ofOIk
UEWUgUnpr323flg2YNXvRRJn0rKlv0cUEQ+J3B2iiIR9RBd30Wr9AedxROMJHes4su/IV/0PrDbH
43KB5SCnyIiYmGC18JlEu7WQOQFV5Zpx+NRmbc4TsKmfwEzq67Cmm/ONs2yq5cFwcO2OLDfZlksc
9DsDvayrk5okseZqns1zWL7v1jxe73byB4CCw8MYp5KPjMiXUqUtYILUCNi2SfRG7wkmOT4YfT1x
CfNYuPw6aVU1GkkVfJwc1EV4hpp0yqdkaMs+BqqPgeOi2iT8PItc5NS2nm8gZqluH5VhiOKjLykO
AvfQ2pRCtqo6baaXmCp7J8uVVpM4jOIkoUBgAIzqXq+IbfnHys0aQMSsKRXUjwFxMs1c8orLKLPe
rpKPi4RSH0Vv8ioRsp7k9sURW0ChdxVVnMGs0Q1ATiXXeDdjUwMcSwcd2pml74Krvihf2lV9J/ar
jzSrrY2ghu8eoWz4X4obYlVcHjSvIOPWd4h7o/uDLyu36cLxtSzny9pAf7JeDSQbRV3A1EIMXiGW
k/W2gCHk0Co4jniqhFQpN44VHeBuHRCeMRp5Sd1bqWQCKPGpe4tNYLOgxCD5cJC/R+xkSv/e6l+9
VV5zbWvjkTtV42dOr2r2OqOjFIL9YOOCZ1dqSyLhrTqz0XQ5OAYctG6Zi8ZvBQBYYTsVc3S3UZgh
U+Ss89hhmHng+gUyAnkrGr6v+sTdKi7ogVmkw5Stkc2bqDsR+fmn8fEpweC8MSNuoCv32HoLLPQx
ygIn7JzGjLF/18AWf4yxNPyubYzBIkkg7+92v5epDK6j/K5Bq6uQiCw73xLUdRm4OqbbwuZUUHQT
oShhrGa2zi59JKNrj4pX4hwuY9ZVO5RGEQ3R7AMQirmJOAjKnswh+KvM6g3XlkhOiafaD02DSJBe
xdsFCQWDjfSwaJkK2NZ3COpP5HlHeT4q2ORc7Y8h8ClWZMBxjtuo0QZeV05+CDghzKWSBAhdoqxp
z8V3V6eg70ikdnEtRYCQhc2b20xd3j1CmDMd5Jk0qI7wm1V1CkY5Fic+6cel3ELmtLfViKi8VdHh
3HATHjBmsn2xAnb3P6yv9u96ust6Y01j12OFsW5saVwpy+09uUmS/iKgPvkWCvZL02AErJPVwj+I
OHmj2WTlq5ESVRU94XvP235rUOvjrlOr+gJOn/Wc/9fpA3QiNnPhuX0aEp8X7byRE0h6XWFxD+ZU
EP1AJ66a5iDTPtGb27s0rQBucQbGTxeBtP+80KHq+x17IaAWpCWWauS99kATXyvVLaVP5T7ryt25
7Wh//gDWfyCk/rQxuvRr7hQibt0mUx7npNQLTElAQHI2EkSQUYnkJLCgEmJLHbYz6f9NjO1OsDTX
vTcmRlt8HNOJvnAJu3TmzJkrqA1kD5Qt0U4r5xPuSglDwaOfIPhmJ3Ot/liCX63ZdQJ9xRFvfPij
pXjWGEOa/Ow3MC4kQ93a0aKCeWaUTvesx/KUQ4q0JwLRKTaqeiyWLTFbPHo2H4lumu+ZCwMUv6tR
Mp3hSk0KFSLN7um97m+pyaIMNd2TGNNLu2J+qngWiduh/EErJ3U82sx1KxmuvvZHYyQdZ1q2aH3a
Ie5IL10TYcjKwc01tDfb08N77ZULm1SDynpjdbu3fbHLMEatbKpgKlBqwzc540kmYLFqb//0eOKn
B245EBRpJLR7uZaxudfgJkIEP7b6+cVG1KSiLQ5JNu1L0fAt9S/PFdXS1GToRKJV2FgDmKxgmKRz
6pR5K+pKcyglu8ek6vAj7IH5KzHrHrX93un/KIeJJLEWS8xUbsFpUELGcXMIbckCpB1ZJdvwjxBI
1q4tVnn8E56tjmV1K0z1D331yjUoK1AvDvIVwg/KaPNvAW1EYQFBHx+Kj7jgO/eBBhEZ/3Trnt7I
lxyJ4vOcoRa08DYGuNp28XFw9CasjpT6gN0xbRl/tdepQLF/X8UTxRgiEMCkJdrmiM6pfm+qtaxp
YQJDY23Ynf5Cm78rGkRrE9JKC7PP/8A7ukSYqz7wQUwB1yYXBHfbhDA2uCQnRQuIgvDB3gST5+58
MBYCJKMhkETHNJMTO5tSggCdIF8No5bYqMuYA+gucmHrMU65SnN6MSBmhjPjgd82qtcdg08g2pGA
jX+ycYCZ/sO7TULi3tKqdcBF9RazbXu6PMEqwVeO4DJNyGfJoqhzn9JfiAjDUSSFzk/jwTNtiApt
jpjBrtUgTJnLadZnFIPUEzrSQ+CHO6rXJf59IhmjLZtKX18WJxezlfB8a9qx1G5W1Vo8CVwtudJ/
sTC8feAO2Aodp9V5b2Amngc8T7sbdLNUriXOo/jEetLx1uADBht/vWC8XGAZf4dBMCeLNFoA+n7G
GSgEU99/lyyrzdE2WAjQCJCs9zWK9/x74kKeAlxSURz1TqSGAYp7jcl80X+CNGYBvRbas22RHH80
CEWbGwEWAHWLovhm1BRYKuQXCeUd5nDmjDWwdiC79rzAtQ9nm4NDunVpB1P1q0vurDr2EeBRQPyq
jqYvAO9aOMHJvy7vPyKCgA5+OEIKbXitrA2kjcJ4JjIa1VmhU3ozkx3ZXQwZVdRfLEye8EEJrMY9
4jW2SsV10CHwdHhpE99yyAVcAsYnXioapXz80z4WEXNnFPyKQxJcnd3qNKVqzlb6Apmb0TNaUrBn
CBDClQOOWQsSIcxyXYQMlKuFuXqyMu46ejmNNwyKkQLhqDYpw+CmPHNZkCMUp8mbtbBa3EwFf+AA
RXYnbsKQSx877JFXv25iSTacF45QkYFbNwvEy/oxWW9kwOJX+BgGGMzvByozciFBmrrwRr0rbGIX
b7hCLgbG7tGIwCb+iNB/jPQqCwr1mkAxr6ACypEJ7VFTeERiFzoB6D55fqLXKXEa2m8fKr/1eLRX
PFJBEwrMi4PYIkDbNk0Jmzovydk1XGSFbPtZe5mVdud1GD4++IBNvHrda19Dc0FwK33vjRylYi/h
dKhm6EL2sfY90dbGjFJ0iQv/1gTyP8BinAm5vEEvffnGQs+ZB8g3zYIyjSQXRfHm8Xh6eg44vEkP
UnCSiDliiSeXk38yRO62eIa4cZhSTQ/DdppQ3zoruTPnHZX8WR3EZjtld5icFrEXOVj25owMLClY
bvtBsoV4l4GeLrvqOKdFUe2SvcLYFONDAcFCZwz4sDqBdTJdZdMnHSGF15RfSLIAVsRG7Da2Jw99
RXF/Qy52Za5CgLcfK0M+ZJGlm67A2fwdO8IiF7zaoH0UiJ/aVsghPYRwV2fnjFp+1t6aISyWSbrQ
YKu3zwbqVBT+GlKeEkB/CbQaHmwXnixG5A7oJyWVA5MKHz2EYzn4/ORzLAL1P2ETcJAhuFuBqvlZ
NKl34jQ0AK4GhOe0PDBdwU53yr+tzEbeJlLeQmzDvqmIleZex6hZ9kLb47Fm8aRA7JOVa1Lb5WV3
jrOsej78qExlzpSJUdz8AgEE9FsEuLz7qAegkHgPTbwiSLWdu4uT+eoZucAUpi0w17/vhj+GiYzb
w3qRsA+MJ9MkEYbRCH0rR3+F1jpja0FDHH1Py/arHCcX+UTL2Y/Xq+OVv0otzIyTTB5+KrurBNJB
7MVY8JzBOSLjNqzmEsjjoRApJjv7VNnMIsXTKe3tv+6tpjAAJchjFwTTCLWH5kh+7d9cbz5QT3A1
NpQBQ7vxcYf+3IsLOSqiXKbg+2o5ZOyq6FBFoR/78lfTUXvcLouAaCNpIhvudAiQz/FtptG98Xfc
HBNZFYU+HjndyAETUTB8dkgsOaMj/t9uqEUokNnKaaIrunjGuiocfwOTSZgeCNJgNgYChNSTxhyk
iF6pF01DMwvuNTGzwUgRNuRVWxZCg8vKjeyy+UlkX5poSJGTzPzJhgH0n3QQgE57+LgM8AqhDOqK
VhdmLIXecYfVnUCGhWhzpS/WiRiz7g8I2mHfjmU28hMZ5LCMMsXjndpCFk2pv171UiFgamPSwk79
L5yR330tfp8DSAtguSfNnDgp4hcFWqiOryXJykDv7y0KLI6bJnYNOF06vATpqkrxnpYhRrhXQxv2
rfoiHupBFJGz6sgcTke95+KNhZSdHmDFoJFIvUR3D0vpY8MlmHG7WkM6HDORKY6I3fxwJt8ufk+0
DLgC1S+5vwvEDrPgtEOxSkocg9G2RiYA9aVmRFJCP7CAx/OqX8XVkUh8LktvaCt1ONM8ZalXvEMJ
9UweRfgukJuUgr3viuEiCOJwe7BMZ9p9I5L5lRCwuFLqH0HesoSuHwwqe6KqGiYqZZ9u5fuVTlEh
j4iXMGM+sCzzySbt/AlKJKhxzT5vJKEuKZyq4EBoYndL0NQto9sVkQpn/NYzTNz6WcDOOoJokp7V
Ujmxo3bM9OIh7AmqK5iYXDWjmRadqK4SMLIwg/UIEJsHyXb3lQ4B4x4CXp1//g/6yU8Tu4oUnt6d
G/G1eMk3zrnLjk3Vqevh53FvhuZQ3lquETsNfBaXNzDoeRyRx+ALkZvX9g8qNSwG4BkjxM4emzZO
gMpjFsMEJPA7+K5rhGd4q3DM3Oq8pIS9rdBFX/7wBThpj554ZgK1CD0XPgYg2y/W1SGWud0sOpYp
7K/wgBm4nTGahpZwtVxj+fgIjAFxqJD5ii5Zlznlp6XH9iNJSM6QwPPq2UNWdsCE7uyPw5mC3jLy
4M+1dClNGIFzgYz+ypEANAYZH6F5TENuUia0Myf4k9ipE2dg+P56DUkLkcQTUmCetYUFwSrLEDII
v76W+GjaA/QY6D9eVwdEnjkWM532B4QcMAEC5OqAXpZKsgmXf/97/bFTfyuosZDcOPVEmAyzQfHu
bNDFMmafbfTnoF0r1cxni3upLkypbsI2hwK6HAwvKHesHY4goGwBcR+l3HPI6DgpV+s6fZiN+RDq
tG47bdi8wBep0HLXGdTxeb1AHQO2I0co4RjrzLiOaJMJyj717yzwyHA6eXipb2oHlQCrZdINmpRE
Oqrr+NxNYWX+VeinABp9as/YnfR1z0HrweXen/F6p2bbiIOZ/k1Tqfw7arUDhWAoeabijv+dIKXL
X7ViLvnxir4W9eMnurEuezKJxuJeblQngakRcP/GEzqsDZgafSZ3bvH6t69Fk9F3M7q8CA8dzTnS
P1upJYjtV/CjdFqL6XEhtrDyf04KUyIJAUw/dQfOBeAPSPl5SXl6qbCXwYISDkDLGDjozRtcDCxc
YWDykw9r0mBymsOpuEwwwERYYhkYXl/hl0Rr/qlWq40hAg/EqCqxIJk5UzE/Oi/dmM89HHQf+5ii
ifdBznYhB6udAlSxKa4MmEi2tETgMufxKhJ4ps8d0OEs5etUoZoQkgdlhejC6r/E75zRrgj56Wxs
xrnrSNtErtXp+GETOor8SvttN7F0Na0vM4IcDIyBAAmn4Ubn0Hq99zhCsBFIq6Fh94DThoAe5q82
90Ei3l4r3grvPqPlBeK3LH1Ckx+pLNouTRZtbjObmaUIBfeOV8kDpVdu9HK+WcbNPoLy6gvqTcHS
w7L+EQN37Q4N/ghuXAmv4tfFsc6JJ/ubGy4i73tfZCFuNuCL5x1BnbkuNwNQM1c6+XQvtAeGDQOU
JK6hNM64TS9at2FHAMI1CHEkioXkax3TDllYfQx4YdD0pf/9Ym5MWE94/MgBMfFEnUVUzX1Z6fZS
NruGJOc+Z+jlGIR7Um5iQsondwnJrYZdOrGJLaSpSK5BVNRd66jVV3Oa9wTa4zO4TEi8o64SzWQH
p7Z/VCMX8wP8RhRiH70EIG32yD/pquz+QA4zzKWHlGY1zBOqHAl0xb0oLUm+cfnmHnqmHDTfRfwA
J1XNhctG6wDon+oEI1SSew83ALXKUHwD/lWgp9m7ndn3TJs9X+t/oEWnP+TeyOAMNKgoXn7LmaSa
Z66uVNo0z8o3yt/3v+J6XqQDI3Fzg7ZspaAzwOJPL3O02ClqVQmINqiJm/OPKRbe/V+Tb7QEta3r
zq6BRBQysULFNMipOXr+nVz0MZpHqEoDh5ddT9BgIwicywxykHsAXwjl/Yti99Tr8u68+g00Zr3U
1xSGAsptRxf5y/TsUhZNLQNSEAkLHX0GfilhfJvQl1vQVbXNuoc741AEb/rtErpFlgioGo0vvcwd
UVVb01l2W9YB1f367H1WUevJgTp4/Blwll7D/uKXn34Ooblj2mEQSo/7i0ewZ9PE1Yh2vuq0lMPI
PFo9/i6hdHJtwm4wOI6iN1dKRQdTA8njmKO5Vnni23Dl/W89a7Tknsw8/y0i/gEpC1u7QWClJcKd
A5NJ0K+2rAsTTyi9Ki7Ql75bt6uqhCrnDhivkBTp/qW9wYKv+7uT9AOlAoh3KJplRO3+KN82N/c7
GODrg+wHog0KLxFrNXWfN33qDpu+DbVB3AkrsZsKLSOcb9vLmTQDuIWNT/xU1t8PIyhW18Cj6Ap9
pLl7vCa3ECOABSP9rJIGKKD4ZBMjiFE1ljEUy4mS92RKf6AUysCOd+pzLbDgtHaih7maFjxT/6c8
uxyTuShiYNB1fjj4y+sJaX2pzU3NAELbMmk48lvhwgkigfpoOCGD/qu+RjjXbYYNge/Xib1paHZ5
lMe5fJ8WwJS3ued46QAwTQQMXwABGJigyBVtUR8sQ/Pg3/PxR0WIwcc4IRkAQjVnS6cxvB1A5yVy
y9NAc0WAU7Ux9qUgwzdDVyndhSUGTe+BsE+ivHhMzU1pLwLfkRFQQ3x70AtjY1+4cF0fIV8qxgRg
9ufzeejm9UdpC1WDodmt2TD8gidqnk9fWnhtjVOo1w64n4v0tocpRg/qvFqG1HjhQioVgS+s+rmj
qHHCCrEPpY5sOl5pW2LE8ViAaHt12tsFDFXLvO1P1IFlMn85pqwAr8SDz5qYDU5NLv+qcdn37WeO
rjqCwuMOEYrlul7LHF2c5oKBY9F6A2wuP+1YWjWS9Xegnz+U0XiJeoEu8MGThebOfNeLHUkPrNi8
akOGS2lnIRjrzU25Xvj7Kw6DzAvke5VL+EpVnyreAbZICKN/w5m1mKEaqCEfm+BK3To5xuAVBthu
uCV3Co/29e+fw+03hMbBYd6LPS2RqFOBFYLRkv2nxOieAhd+v0qJxhjnvNPunEWCwSED4sslp/NS
kBn2JD8LS1LrjT13LLMoreO9Zvz00tcIlK2ukLELWTpchLNZD/YCB/Py53IRAwS4s8R/AOPPtTZ4
fk2VIVPIScPBZxLX5B3qGJdavZqij9VbWgrQA1PLR9Xa0I3iZRoR31E9ktp6TAZmRf/lWjY04G3d
JXN05/IGo1r3KgpvsVQ7Iy/94Kqfz3Dw7gKmWR4SzGbyLAKMwvXFm3JTu7YDEMBnjTXN37JW/UYd
+eeo+DxbkaWKd/5CnlQ+v8DGPZws4Xc2hdgcObpBH4CbTijbntc4ZsVIY8t9/h0sT/0/lrfqrehI
Q0fLjVrTPna+S4UJJ+OFhu7dUUf65ztfKqJly4pTtRrBQI4hH1pAlLI8Sz4ktVl+90Dk/vVFnKO2
Poxf5vjhTMjHSsTqFNOzIiDnSPIgNNNzl08YHIS8f9vgHwmy1q6rIE1kG5AsrplNb/aserTvwrZG
DhFW8l0El+/kPDzJaO9vLwoPG+HJ/Mpd8FKEnaesn9sWBvcAn2Uzg6H0ecdgrd2hzVxio36SDobx
oxBOUq0rY3G2uYpYN4F1EPpBm+oZvVtmcRg0GlE35szEc+QZoBQ05SEvPVag2ToQ4aWxptJYmMrp
AtB24oBvDPHymLJZCfG7iKfT8NwvWgaS5UcE29603e0gf4Ai3zRp3k3UMllq7JBFmDGNVslf7XQ9
VkoUuT2TJ8U339m6ZChf8A+1KVWlZCOfqXlveUSDpjF9hekHcO65edOxlRZobkJQK4gddDfyDeWn
ZLwSNBxmW2KlrcAJnm5889oFWFvR/hRqdZsNFwSZyoIPbYAWpr5ZPhsxIYxyM8McVfoKOXaoIUpT
fG0KGhuP/IZ3zxfYW8kSgAzgvi6gp6ObDbl7tQOyEc8wT8jeKOF3fUODjmLtPTA4GqpyEjmj37an
Nv5D2T04U1Gdc8/skysgO6OneIU25Ist3vaD7tSwVZ+lpniligI6ovvbKKsI1ZklgSRf8apZstIn
3HkWdMHPk5qyCH99DKk6X0DuqPJ7uzGrPMPa/H2vSe7MqlVm//9pxrQZPjtHKRetuUQNLfO7e0DC
QdPiL/rFeaZL9in1hf4lEU0BnwIcQyED656PAdd3FcHD67y66cD2c5AM4YpmOGUHz0Cwz+HtCjgD
8ZsgNdGrM5E3xv+HFUhvfwKb3gc35qQ9ypP0+dJuvwmbkxYtwhPBEHjPR/iMCAMhDMvQdag89Mt3
uh60fjhIBG2HQOtpVrJE8htMn7SJE5GxLrp4Xx23CL9gwM3t/50wodh62LRznaV0ZLyLRVYn0MY3
imn0VYhUOG4mnQP07wOIYGwsSuif2BUH2QT9C+RrPmlyb3+dk43YaYb3b1RH76dspz8IOMVf0d+s
CsxVVtd/Rbkwh4OEP1Kxlpw0eCLdmUwA0pBwNuiLBNjptnswx1XzyboC8dMMZsJ/CtKXoMDvF2kO
n90jLljo2vKxtkA7iRWPtZ84QIeZqboXpBJX1GsIAeHRWxUGHt06MIkN/RIbTfNdF4nKZt97Jtqo
+TuVli4c1C9BT17tPOoSix0ZcfpryQVfiSv9wjJhKPtFDX7oKxPvqWgCyxvXPqZ+bg8LkJZuIGEi
nVVHusnbVyNSwDENZThz9TqwJP0XlCgdCnYOuhFJlJZW4Vq4fpI42LxDTjyCmWJOm/+2wolKXWlE
J1xbjG86p4R86mZcn9FF+bu7+bI55hf5V2/HAoB9PEAxnObQ0XSvs44YJQVE75pK/ga7ldDLjFt8
wJWIC37ppfX3/ozrvtDDQkgjoc3CD1ikaM6Y0Yv/0Ct/2BLuK9sPNuTuwFARP5QBuEJjnIZsqsT9
JpBdnKhlBeiwSwI2IHyui+sBStCNu+/giR2k/arLBrUpcisJcSS8X8q9xbiWpJpjY8Xcc69DDVEO
lX9+RxzkYEzQbdQrP7U5hwWEXHvudnECaAI2Miq7Zr1a6oQ+HTQo+cU10hk7lRSHKRCoZ41iumzV
uo7MjJeqk3FYgMJz+lj6ATblMzI1r34MO+/LTU/jDFjkNYnW9lZ7tZy4M57i8WvpYHjM/t9FDoNy
ZSWGiaGQgsFM8Prmyswpdk2Nc2FmaHe71SyhmM/a6v78GCNMfqV7V14VYTZlJN3UAC7H4Vy5gclE
CCvG89AVB8BxCRv/omzThftpnJZh6qFsfbyysnasB9vJFDXtEydAkkJZj6RYxoyAZHtG2sBT8HcJ
iAntsYlxEKWIoLS90G3CqEse2a3+pTi8d2m0uX+wpMjJLLb4fckdixYiyzhqqCE+M1NESye7CYnp
EGyyQ9bq0LsMv4wWJtH2OH7/AsVB1knRsIDOk34Gm5l5a9L5cKdptaEwMti9pQ97dwO2TFY8Afkc
dhm+KoBMXXiD0CCJJTENo58gM1PNsaGv4Vs44O8gLy5m+GxTxrgXt3X068ozuQqW7wUMoMwiKwpm
z2eMZ8L7kNpb03mJL2yJoRVFRYjFywpRP+ElsLKTVfsbTkYdHDe8H87vVL7i14OAlfi5/oyZUcIx
TyuElN+QKarUfmnamGIxkEULvaGQ3iiX3Oov/yIQ9CITYMrOlxXzFyzYaYC9+oXllyAAfUy69LMn
Tth/Owxa2lxq3Y8wVez9bMk+hP/h8ttOdKYgBd3LFvHMgg0Po4VF/saCByN9YHApp7znD1dHtdgA
L0r6CjRkuc8tZtoYXfn3p16iGy24lo6G4OI3XSuD/bxuiExpjOycmLQHqPmz7AWCbLxcUUQBR+In
/e+lJSviUdAw7GLGY7hWGl/uS65Ih2yJYKnvdRGRxAr1g5E59v1EVU+7gz5/bQ7DWty+fDXA22H+
GFZBGcpWjV+Si5mTPmrQvWIgNrrmLDHNiIaOEd2uQbW4XBC5e1cVb+CbvW12L1DGXgJhFODNhJ4e
6/VmHau5+IlkDLT+xe9OZNuj9i/hrNq6nJVCpH/+O4fA94U+i6M35HBShvgrATULSEA/D+0WGsjb
wZXgPHeifQ9PvGd7uKCW0zebS0zEmpmeiRQCnl5VRphpk19BpHERtZc50y8dJ+0TOv2R/JLRhyiy
h270KoTC18aUT54bBbYX3k1ECBuoCZM2qOFD2IducNI3lFPJf0dUSUPfTAItattvh79kkPHj6E5V
zNQiN3us+CBLezMijrY3QdIN2vsq9wxJg30Id9K4dU4578WSD7yddep/Idv2gIDAH0XWmC1sYaKw
RqYTL1cFy+yLu9WrMQ98YHHdSwJo6kE2Ly/9OT0ird8KLxKyAak53DA8Ms9YnOp+wp1R+oB0FMvv
cOWJRy8aklVKM6VDybyTkU8KSAMswyWBz0VOirGDCuKITFzEZoP6Yq+gNkTppOYRSb9QOjclYFXM
efVU/cGZiRjJVrJuxjWOhWU74zL0Qra4shTp/CzYu1EVFEDwr26FHPEauY3RtM1fxvpMdoSLD4uZ
knY32M4YBmm5v+12IU/s+IKcwPu7FqoCFsu4a5yKW7k+Im7fYC48EFJFQ30BIALBt4PX85yG/DcT
D0dhNRmo/Gfx2g2O57F/Bz6uXqOVx9TifkhW95tubmocTpUsYWdeFE5v9su6weDNcHTpFu+54bk1
4Bh80hrpMFP0Sj7Npq1lF5PrAvyZyeeF4SNL1MeYGuNlVNGdoPdvSCZ3UPMvFiZcrXe3VeKy0jp1
v36wLSXA3l/d9iomJx9EvZOUzvrsl1xpg4vBrDS3lWQsyLXO58UFBm7AH134htAuv5viGdVkeSvP
HpFfDRzCF6o2ye47JUzBP9XTcVOA/kpB2zkKepbCOKmnAp3As8+KdoAA+4wCcGhf1WP6QaMEdcfx
UBoZZWSguVMCBTRYIKifonmYirg0e62SDL0uHCgvQvfCSbgZ2bm/txEWrMEvbALFpcV4nSJtsq1m
w1blK+PY8f3SFtOKecNljLud35cKTcL1UtDDBZq64nf7/HZGpetFPIR3nnOHyEw9y5T/r5eblcVr
sMfHD8nVa9gS1/Tyo8/BuszQ7xOPXSL465ANLIUMbe1s3A0rOZvpwIzAvo/iQ84xwHlHyyM73C2D
uTzMaxfIoesYdycJgV8hfq9g73+Mce881VfdQxQa0VM6qdnkaXsE9M5W+QS0Vc7OPv2mNQNxV+HV
EE4YBElNIsPPOLl9UmDhrnDDyFLphi9rahVKT+flQggQCRZ9pfq+Q40ScNMillag7LGrwd6YiC9b
tlb74kvKGm/7Ry3fsrHtlJPBlbKz8OipNVmr03i9Svq/JgpHwvE2vxW9SwDk/k31bqL2TfHLLI/A
uOlcU+Mj7HGc9Kmu3ud5wmNnMMtQjKdr+NTAwJTNYv2Fpuh/yZfipx4NKZ6yGyyXUZx+UUBXlRe9
9gX9b9zh+8uRcm0Rvu43jDmWxiGWlkmvbBDUh5tJFF/1zhiIkVKGCeuzYmVrhrLybhBBI5Aim8TE
Pd01EIW+TRhcbXgA8Rnrz1QCoHtlTJqj6IPsx80jy3fIDWMRZjq41NJjUwSQxQbrYM6/EB+DeTWE
WSF4s2IiQWMNEQ643PBOi4ZVcPple4ojnYkZf2EwykzpRcoziSARhUETirhy/OYFnJEFYVerm+ne
3wFyzHlhVlZud/so3aRcDHn6LDBg7uul+cbUp9Ol4wHhChImU5NMg1fNp7lT9dSOgoKdNq8ZYgk3
lX8fY7faItKD9YtQrENhoujkGBL+S+IH6dzAuCuqaRB/ioMmM0wenYB8qTCPOmRPGrx48coSva7w
TMfs+2/tkxqzS80nXYxg2X1rKwbYIcG97NYlYpFc7+D2H9A+YIPNJcSH4457q91namf54Za2lQc5
/D9XqEoukOqxAWdImu+jE/S+P16x6FTZswwPlXoWm6ulixcUm/AZ/fKMvt9LN7Bc+/g7BBq9dw0d
yHcbTTt5pxipJ2Ap61PPpMVSmSvoVrNO+fqsgTRIIC7iL4WiyCAFEkWBQJktz81OwSpaEgnHd66X
ES4dzMT18sYYRZqpmgR9yTzwQ/NYVM9vnHuj3F8SsoGdtVOILEYZX/k/taBH6AoFdyj7ndHQj7Xy
5fqAgGrx4ufuhZBExJAFj7L/H0XpfxQd5v5YvOoCVWyhlJy/SC5ypW9VEPlQq+z4ciLETbtahjja
+GZUFBmxB4dlcnhtoIyiXywSyYz/RUqIl4wcNgb5cDgdgUf+/K2h8IkMSYmveAMyaoqwOeck/XGF
0zfMm1tbwWRuRqLxHYebZusGJV2Ix+4cWo4t7GxuIm7jfmwUbh2zqJzOrNv6QwgbKwBTAc5kMowy
hQ64V+v//P8zpkiSKLCYdwT8ACpJ2pBqiNhBIRmivj1IkWHnyFIq+oShXPUq8QYVKLnXGjzRA2IU
DHq8jIOIb1hNL7iyexUlrTqBH3i38b/0Lr0uXVmZ4V/7sSTizCif8GQvRrVbDP4PqEuQjiJmE1z0
cqWdV4UCVDFIiEXqsvaqgTKRf/o8rfTtLmvB/rftgBXqndPcszZhSP/cWzU5c+/Uo8JBa491TthK
YK0bULTYePeFFSPxmbsM0PjYdfhip2DcuhQ93l9rKf7Z/RRFwoM6O/XKKwPTvtevs40oSw9em4Jz
btQx8N9L1W/bIiyVRv+xASEWjjs/xn+0XsjKZYc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
WCjKBNXic0KXiU6pjAWXiq2LTkKJ7NE3g8L6OgRpnuv5wFja/4QAqU+5Vd1hH0Xxsc4vA0Nwy1zc
t7+LfMBHzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H5f3TRBy4525jkh1qIK2Qsh4q/GrtwJ6JVADtzts1qrfqD1bWIkorepAhRIvwZZByI2fH72x5SON
7IfG8zLpYUlD0Jk3QCBoYlUZJGWU6RDyaY2Rn7Gz5P5HI4qvPNtW766wSe1harlrLePNjoSKVhfF
4H7y4hlOm6KeJFp1y30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o8NUJuTvvtHQ//0yHzk4r3ROKImbnyCQ/+GiYKbHz9Jqc59WPVQMPJDi7618B5h2z5gPFkZLVKrt
oYIDayRN1eDG1k1+njjd5YRIb7DTMBqPHvFVEOao9N/cefP23vkwo+I5wXkEITLqVM0RI3al8o8t
AaA6Q0U98Bzdo+Tx+RKbiBIBi5x6wlOZOehaj7m9+DFw+updOQeJ5GNy8AZn7ul0lsua2cRf0k4L
gE8HziSaUr+ewcL1uRh7afU0No6kaXygNHGf/nl86AGwUs65q2nQnVCcL6IPPyXmKD4Bn/J0YFQN
o3G/KJKIPhXq/LL9z7Hr7LE3J/cIaba4C+44/w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
r/Xe2Ci6RnICLxvZgN4C/9rfMRo5L4MeaOlVrWhtom9UNPVoQwQaTPdI6GiUuDDQ3ElZSB7f6p92
n6ZoBVSL1eywG+ntCU6ZxZ1/8N1sV9CjSBxGOexweAx2kmsTC0q7hVe7rZnh/KLLizk+Ny6alv8B
v1zuaJAVY3QDTrVCM18=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BA7JOat/rOFWMLmTHh8DUAZtAhABvlT31S3WaH9xRoHVRI5E6pFuZ9+Ecgih4mhDcxdjqSGbeR/u
24jHGR1zNpOF5SfM2XuvRrQQu9K7wIyXwPdbsyw0LvXT1RLA9UeiqNrt0F8qGcaPOkn4zXH8hSn9
09AecPGhGA7p6v1GpR/up+MJJxlXdQp3HrAGMLNTw6FmURWGfU6ot/fE9/XTH828aIEuXPQv4VF8
6pJ5XDXcni32tirZKs20tbT3Ib0XzlMIzD6X0wniGigh4dlmtyYpx3VFbwNcoV0FuVHZukOeq/07
9NqJrMCoOA/h5LgKZYIh1HETLValj8txpIQaFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 72704)
`protect data_block
HvIwe2N34SZuMjy4um7DVGxuUtmbgThSrTNwoGwEiJdlisMhSbzJPsSLzQyCVPvBWB6KRKKsL4Rb
Vu3IRL7SYFIFYCA0Qq7GVWGEpvlLVdFovlxeEyEPw7vWI0vUv5p8t7ZuGAgwgUgLWZwGpb4Wj8Wh
NY0Ig3CnlqX1XIrtDI32CboRq6okmEybBULmi2P9k61yb7SBFyAc1svnv57UYSBqImh0j1AzkSL3
wa7THm0mcJ/gVH1/KUyrhO1il+aaW6NHEGqWVwo74qZ5/fcj+YIKKJDeGiqH2YcLSG5NjtOCUbnw
Qi+LxTROphc9BKH5UAmjqDhnJgjwGvr4bQeqYaQb4SjNwDzCodQMfFlmK0ro8aTvXCg9F65L6/fq
7DuZcatrpTd3yP/baXqApZ5wPBBkqViF04/WKfDRQMsbOlqNTWJncXWrzKoiXG4UCp3CPDPI1ADA
J4IoqjvRDyOwSbaOvd/DRgou6ZW3wRtzUd3XoyUc3ams6B2Os0tjPMhgSshCr76+8KfYp9hkLacy
Sux+oKs9jY9iRaHGLFTha5pUjG9spPLty8CV1wmij25vxNiEVXbEH22Zb7UWOtcj9DyaSa1hjrIE
x7q7kKY7XnPYCLZ23ZasHnZUjRcT62+6/6DN7KmHAlEaspJwIZt+DWh8A7U1vMtZHaMtbFE2O3Y7
iQjIjy6W6P22+JSJsLUBOdzAyiY8cghioSF+0RXrqzoHtPct4n98w0sEdA9Znpf9t5pA/uSvDBL2
iOyRM89wsiLc7lsX0sihfOSjqqxPSZopH+A9h9ue2/G31af2bLetZX6UsIMrqKKz3DsUWS5jxLx2
uO4K2xiZYATkiQj0HpfZu/5QV3d2HdSUaKtqpNfRz0Lw+5VcfWZFoyYfZ0TDA85K3FoSjhCOkt5X
qnxEdhrhvJwcdP4HRT3bFDNzaQT2Bq+0qvhCP+3ZOskwvkpFPCRCYfPKKjMYd5EsWA1ipnf37Blu
P+B6FwUT4zhffqISQupWw3TQLYLkxjkHEhNe+WkTmmsJZUnWdxVsov0XpzAcnl/DTDNtJ2+ovFuW
vS5MsdjEPyPduB00/YvmzhVscA84PYzTTOYmcWkmjYSzuwP+lws5WScc40P/b1OmM6iAtf4c0rZp
VvXlFVn0n3uvmJnaGn2RIeSQIa9WTqypLxpT+BZH6En9xteyR8rIYV1pxEc0ciBiL/jAV9n5T0k5
fvUkVJZTXX+rWbtUg9+l4nYvDOHz9+T6m88MPMqocLY9yLV+dFzczAowkeQ5QYwNFIzing+a+xZv
Pxkz++cUzgMzeTl06W6wTt2ZiUgg41n/2tzqrylGQeM9VqUiEG7wCrsr9xS5nQjWvd50z1JDlsbc
XZ4wTJNrOMBD0zmEaRn0Nrb5kYjGMUBglMp7HduoiDKKRZH+kTiXGYn5btDeDwJkymeDqU52kxMM
Ua5JylcFhWPU0/QZSOzOFQ618mpAVniy7VKgh8HzuiJ1eX9hUbnNDBqI5+sFcn606kPJ3RQume2H
+YAsr15Lx5QHTXxdHTywTQc96QLzVEd+ZCoDfLy4Ita230vNXTC2z7eECslwEaytH4C21b1sLtfr
5XqqtMYgorrrvtQqTi+7Gy5tqz/yOiJ8WuC3n6rCzNi5HVLxx2lBcmoj3ck11xEwHK50HJHCLs8n
JWjh7ZyFXcnG+XxjfbJv66Q7WQUu1ZmqFkRdo1tv2iY605wT4E/Ffc4gBG5uBhjLdth8vbgwz6ZA
RRtecix3HrcRtApeT9szKzg4hejQoo6LEak3BaEMuJWHW1+RpPJdNC1m3R31OxYyz8uOz6XTCT0X
37wFk8mqDzVYvkZRZMXxSSMgW+/tTBr9J8Ydd+N8d4SJIlaUT6Z4dEKdOx88H5kAlF30H8nMnggP
SDLxrazQ2jQmdjhLK/KZ4JKgWPpaiKEvwxmejO+E1te8EtF1r6TQWyBYuNPbEGkNULWhO4R7Cida
ludH6DOYw7JB1g7LfnsGd2QuUSkIq4hSkPehzDldUnXi3vT7fG95Y24Rs1Sd0MHAm2/25gr952+p
OEN0jULZPrgA6Wy6VgpHXNYAtOIJhXgWrp2Nf57JhizlPfOy1Pcro1lFHNWmcap/4qKYMju/R7K6
GlUTWoUzIjK19xBpBj057nLzgeOTsPvmAxpJnpGyFe2QZgFs1CiqD/9SPLFhgFpFvIujjVokVuQv
Y0SW30jzxOyRztwpB3VmYHYbIWtp7IDQkHEgypOUnIvYckMEO/2gfXT85ap+CcP2xaaMSS8qRK6i
KDBOyMwHUFSKKUvAG6UKRulCPv36152OGtsh1p+qEPYuHuYz2YHhQjAbJwovXPxLIU3qSHtBp8Q3
yc2GWHdqA3P12KMBh2LyuB6FLahJbJu2cTsHXvtXfHXiWrr17pWTXZdqbJPgbxv2jRsGZVxV9TyY
7lRyR8Y3BiPwHIYd+hXW2gqNAbPAXEHzEW/FLTfzU0IEh+8un0KCVxWV+PyVOjiySHksLyZvAgtH
XSphfYqOoGZedfxOcsK8itSk1ADQRdw/hHld7+km0JITcpn6XxxASzJAe4H2mMiuXzmv0AqopF8Q
dn2hMIc1vM+o30ll48q4nzjgzZeDYHU6ZVNTqfMAzTR3cKuj2Fl/TsX+MKLc5v1LF2njBu9aaEZy
X38BjLVxv2YO1/oTbEE2W99LCX/hW/VvpGmSx3TSAWbClged3p6hKVqvXJrGE6hSeAbmJkEBf5UV
9xLSafDYk7Dwr/oug1ymI4P2KbJKuAyPMOY94jd3Zbb08xCkTgPnKXNMGjsuU14Scf6ZQQldfv/X
Vd5uymnNA/wBuAfE0+w51MJz39YGeyyQqzp+ABKGtvX1gcyGH8g37lskc0GVG2Kuko4x+IDCgmOo
tdiIPZWz2nQhwO/4vZeZ2/h2k8G21seDc3LmaeBgdDtzN4AczOgKoqoZlxiqh9XbRUQbyyUVhGEF
NRRAJbRIDhE/b2bdPrvlDrU13gXfceRigKLhSBqwrzdvhVu1t5VHThFl0xUMVG6DXaShN6LFBfkd
qMELJr5yk73mHmfi48ipz6ZDKL948hxDZ5mRLxceIYnC4G6Zvi4LpBtIFUnvtTU5XR6KbYTZNK8D
pRDt1tgs/oyKpT3j+oJOb6s4chzqzeyH6GA3/tNu0pptqc3PDRfETxx4+wq1DuudmWuvmAZ0aPdB
NCAsKw/QOJZEsMuJ6HXwdee1iMOKoPzsdIeFEmNt7XhRkOfamcXv49MHg10jX/lQ67Kfni2xnQbr
4reqFp+uoHm3eA1qOVCwJqjNDHp1WaWtSiHKH/hXz8hzyxxgUDc8MWMD37Wdb3tjHa1nggaLwGLi
rSN2SmS4RLT1AdAGlDAmxM+N7fJMoeD9aSFhQn6SY5v57Om61C8nId5zRNy9nVQxwJehQRaWF8Aq
fQGUd25hYUrTkKGV38LTKfhJeJL9dsCGZNA2VRoL7OWx1ZWNkLrEEAFjBa7TV8dwE0x+1fzcErpH
xQ16Lsmia4F9S7CxGcAz2HfcKzcNN6gt0ah8bg8asyRNgbd8MgnANmIPxgkh6lyX/KrjBP78nBiK
BoQw6t0yb7V0UGt2AfFBXTggPoW4cj3iiaaBlCgQT/IgrUopBb9Dok3+aWBDZwCDQ1Q5iqjyJ9pD
KY21xP6p2sAIGQ5xZV1L8lMQoMSJUXS/K5kXJ5BvQ6Jk7CqNXhuxV/wAflZu2vkP1asiBCBF5Ye7
s0byJmevvnQTPWCBHdrGJ6pmcurXwFdBd0BUm9krKJX0e+ggOIDrS4m28IyFCL8k9qBJZ9dyclDw
6GivtqpQ4tAMlDUr9VIEb2zUoLC4hS79W/d4Cgf9SwFGS2vcOZBsheQvadMRMpZFQQMJ9wxCXEFU
H6rhaxKzg8E6iQkFYAtxSIxcu2lyfYMFk0F4c6+4vhd0c3Z6oLW4PTn5hLYEsNOeYUzWPawLVGhN
YKDfkI/sgWtWAUFNCWwBb/kbnv0VClgQkaLJ1R0tbEMZJjoLVFfe0kjclNs5uNhbM8wDvcSbMiEq
TMCnnQb8UtEc8uriFBmwvOEezo7AL6JbxMFZ0N1oKnDkST57UCGqMOCfQ/isGpo3zjTk7uDGuITV
d+GVfw/T+U0Dcy3yqdTiyg7NT2fWEHiv3Wj1KnKKsxTRTbpDGYCxP5wHzQI03sVIB398CoeG891T
hI0s6e3pDFks7YgWvv9M0a6d9So7MsQddPE1IwjB0jVYbmNLUkU5d0BQ5JKdQiR0SL0vMH4mvwty
KXQvW01pzD/nVo1TWzvs2EfoAMcU7hoIAQhSpXFED8NKcuPLR7GZ9NSqFlKOA+Hj5Au9F7uXrS3v
XbNXiGOSbQknrXKJs6jmU6iDxESydyyhvcN5SgmrdMmZx2/Mv3PFYJhH1PAvsdw7X+gHkzhugVDe
f4vgZ254r7LVyo2qUwGAGQgynV5GBWYbRWRrYn9i8bMhMeo5s5FtiNvKpebRQRB1jccpKDqmhdYv
HtT4onhN20B6ChVUOuSYbDCC4ydVkiI0xNIOkhL3NWhXVvuJBIn4o8ELOsiLTRbCRhb0PU/07MDw
+9BpGfTrKHBeXstbnQVzjCc4CttauKv59t1KcPKmkDN8sA7EVDXh454BiEJp8VWbHqonp7dqboBs
mqr50B2lpcfUzwbCmEVTdBiOyPCVKuNkVFfcMYIXGvqt09c+7UHm0yYdwF2nlS8W+3j5VtpBp7TJ
Zb0xii99XhH7QE2CpCSj1x4he0uNUIP6enQ4xpqAlUTm8dy00jBDayQIi5em4F0nc2qcFwUkVlkO
z27S/a/MgSzOFp/fio5suNN0UOJVyGfEKBlwEFkzYFwcwgarr9niXRezbvG9E0cNGHSGMBy3t1bi
yJRFlyuB03wUPi2NY6zPHn5oqFhBkA6y4jpeVjQuJW9CaJrYByef4li0tZDyRjaI2ySPOmtgcSt1
Bv3rSwR27hQ6+3cwYRmq25ZUKrY3tpWjoUYxb94H8LuMKja1O1r0MpaNJ6kUBKP3LGgr1YHHb7IO
irtEqdKhpGd/Wl4Cr5U6jZlxN6N7WDvkP6/n4VKyEAZa2RwNRP9DxlrPEQDvcc6nZ0/lXMJpBuke
XbRfW14uzqZp4ol3Ktw9QDZqTTXmtdhroocX3oCm0E/9BIBYx+V6XKjMmeP9SVvBNFMC9prncNqi
DpOVWEpTCZvVCyLiRJ0qx3Vyk5E6jc/hBPOZKfbeyY/FIgTj/4QKptvZH2Ptz6nfMcfZdh2Ucyq3
We53hmCbGSYVLvUzFD2fEiVlpV9tSFm+lBicoyXggAbTbNnWyMxdI84UpShrNB8nYi/EfKSHy6sk
QVc0iPgqy+lwyoAjFcgNfPmJViVNFhgAnhZhDY1iQuziensvnjPIO1AGRHoZPOvtpwubJeUM5jMV
6OeN9LgeJ8RFRpXnkQv1HJlkVuo4wVPuvEaph7eZYesqM3s1CX724Pmyq9MykE4zMN1ow1YUmIJk
lrC6txSyBg7OW0n7QzRlAKfimFh0SbgZCXYMG2uvsupyf6zamMXHM7O6y3zkB1ORd7pIdCll/3Lf
Oi9YeQlNJ2o4oiljEPInuwhktLGjLpH4fJ+uWo4fvfue3hCWesgTFk2NmwT6zGeHnbSSu3kGaVrG
OX8BLyeoG0CMskQCw9YbJRBOHtI/b7dag5JRUxqN4R/bfHDkpfu4E/Ik+x/aF5mGffsZmE6pVK/4
k3M3jIlnIVHLXXQyicE8UFo2c9VJoIgR1Y30U8vRzK2d0EKAHCKyut5hKp5KytPVaa9QaIvEUDxJ
8ydYsQxl7Y2AScybaztNKlyOOB94W1IXpVkFsSEOE5P2ICh2LoDF6qk6nYsOwgQi/QrodM8aA8Y6
o3EuacF+HCN0A45oiukQN61HXwJ0qxHKVJQjYs3HZSiEBh1rAcHyp8ylj3xUyEdbKmowB+r52M2U
2a0CgPGtlwyqFE9qku6kQ/JC18nhW7CZvNyUmbKQe6J4VIF1G6mjVeP64ItH217LsQu+XeQyZ2Jx
glXpXmZKcDu0CCS92Jd+3cmx7En+WV6A8x7OJP4KoGrYnKW2YGwZTVJoKoqT3RYp7t39QHBcbjDd
96iTZJ5SJfrVbvbIA2NMmXcYyL1jmYnx9oAr1iGKr4/zQ+aCH/Sowet1D9lBI6cg+RGcSlcy+LM0
1AiVzhvLbt7KOtAYZhux7dAad/2+lw3IBzG92c4FKnF0aMp+iQIn77K4NPUwSjR2HfP7tPmjKST+
d9BTe9YiGJjgOe/5N/eZV6voCC1DNPR7yUyME7QuhfXMF+VkFfwQnZLF1g2nZeREbCjdJaSCvmt+
erBvrerL0U/GiGDtZpBWzBlbKL6kA6hyfxppJ70cPoccfYQnYs8QTyFzaYZstGZGNGcomQIUQ/Ba
tA/fBEC8472TOD2bzIw2/VMiA4YHnYQYMqLTkdi5Kuxn6iyiUDYJamg67gmyOSfVwFTF3iuc5L8u
SGK0n/FoDZYtFE0Ip6owY4tt0OqoJhDWIzlgKUhHoYsuO0rhRuAwgZHmwCjyH85PVkUoALJqTWlK
mHc18K99zEuFST9hhrgUZUdHxULXvy5pTNoTvfFZ2IYvmiX+rk7n3noVKgVLDcnzCnjKLN/ShqyG
D5GR4mrCP/rxxl9Uu7dspgTrEkl5FfO423Y3f+9iiFYekUT1rEmvGMXanhKsgCQnGo5yAE+s6SmA
sSvFytmH1lNuUDwF+8L3sw83nU6sf3fISSEW32sXlE4zdgXje6kEHoKVShgy663x7S0R6M0b5CDJ
ecveH5A7XW8YBaOtZuAD5KA7n+ejiYi3kqrLBHWEVBKVty02KyZ24RxC/UkBE2q7OpRQI31iCSFq
Ht9ifWl32SSmycQBc/pyAORd81oyYEj22zvvwYS76CICzX+B0ONl0PAAZEH/ffwb5IkHX8bFW9eC
tfwXvZyyrpma9/vGrfoc74YNALRYKZETKW67G4mtfyAdPThR5xf8EKq0/xtDQvDbXMb97npFyq3T
bOpCoRtMgfvz93JiQfC0LMpzpCj/w8RpP0u7jaFjgIIy8NiN7F68kP0HtA17COI5+9C7AU4iw0H/
ELfzjUg4DViEtMlvnL/D6fFpjtMbjZnwQ82QKaWy8FrWA/Je+elbdepn29k3pJe9aKgxAVd3+wZE
kyV8qkCaYFb6GCr56bkD3N4aI4GZ0MCB1Dgvjyt63otTqctSd2uEsu6IW7EwM6SoqB0Ni6vbMcSk
8Ngxtg5HPXK3f0EHJZNxdOOEG9+J38vjXqWhCyUGmqhCQz5+uKS2IUKF3YIhyS1qn95RuvBm7PYT
ehuDzzH14/+pKSdQ0gHAH6cUikCGtKWGUFuj6See6jywBv2C4Q31apQKA7/rvC97BIi2paggmgd7
iNpgYLDTty91dv2FkMv/DP5uDjTykeqSMj0FrOqsMuvSPAXoFHKBecKsDyxK+ZCNzdOhD1Q5srEm
DOWCRK5w7tzT1RB9VXiim0/DqFl0P4Fs+lJYanN1Qd6fpObL9IQR11fGp5C6IutXVRBGGn4HNbTO
5P6NpCoByNHxfZ2ppans4Nz6KsOmdfPCQdp6UVK40Eu7gtEmn1pcVqkimAlZ/T+bcQQBIkWCdMgR
sEFrQM/uAVNbVGiSTqnzDTopXsOzZ680K7mdfR0YwLKNt9x3xVEM9vhzJmzln3mUDl58ldZfLgFv
WILmz+qw5pB/sQFy0jkQyPaQjobPOnkiVbgQkvQUD6mkJXKFsGQJ24GsJUTaYrEb4EyALETP4o5A
f3ytrUFDHlYfuRxz9yNU8QdYs6e2+87rKAUAFg146b3hL3afUat5ZbU6wa1XwP/970AyWZTf1gRS
Ct7bvTvckA42112OtIQfq7Gt+DoihOFVMWb4wyVC5DKXK+QBBnQDVUE4q0iJHl7k122Vsrjs9+id
rCUfrRY154uJf2SuBplIL4X5vECnLUREMpuqnLZ00pJT98IyCPMvJtQtus+gshp80MgdoTVxb5Sw
Rlo/C69GBnz7iRyk3wdybLCONx8PZvUjiG3DLLtfXULPKRUsCmk+ppgQjtvKtPsBUyugdUnekR0Y
gozZEiNS5mRvpDAb+AVMfLPsI00mZzf/eUDD9RFgJnnqQEesuebHJYduD0x7m24nNVoxfZpLQ9kr
Ph0WL7tuP7gWeIhMYv0sccG+XrShoZ/r5M5CJ40CmLbedxT953SGqnS0dZrtXaaeYGO/464k9waz
KGi87zDnxoRwA3E2JXVMIhnTdEBIcqSA9kmWPnuNeL/NvDouPBDqKNtb6W9I3NbuJMqHZ+EMGAQ+
T0hfH957EsVE1dxOTvsOLqnWLkNF79aAuLtUPKrdTM34STEBLjhPfkM0CxTJVRgXfI+riH4jDJPp
J0yTF9+CZ4DJ2Pj0SlbcGsTLalg3X06sRYBK8G/7aB3G9+8N7XQkiRndDvNLr8ayF9NqpCeIigjL
u+syGsEHU9GCHsLjqLfT0ZTxJHDT9XXqCgV0xX3E0oJY1IMojlgqCdOS+cWwzMzGII3zlQwfvS7n
KxbW0I4kfhcvqEQofZkb4yHBTQx6nY3QkzxPDW+dFmmW3VrMJofveXe0uQ0QE/PWyNNj/Zcud5LR
SiyQNC8gilQU5RRTxUNcZN4SVzFVa5go4lhFVMXoTHaCwezMz7EzxH5vrh1nMAbaam86h5lqliGP
19k39GTRg/iVKmEtjOeQ01La13ZQLdp8Oy4SxZd872VJowdVjKOIQzyXy5di2jkiGoTsVPMTGRnW
BSqpgWti/mhC/kTrmTwrGRDB9oBvNbfwr3HSqcRG9CO9R4Px7V0akzBF077ge2jhGKYwLETTxqXN
fzLjFvQd214Vv9FuuKjwHp01UpDRuR7gVgKutBPzj82kVbNv866v1YJACYdkqxZTp2dwBFgxhHZh
sQHRC5QiEp/SiXZEILSROy048rh906Tfm9QYFSNRKDNkid1VCGimBOPjgS++vLmkv3h7eRZtFX2M
iwi5Or4A7nCz4TjMngtQPh3Ll8l2EX9uudfpQVF8nkaGzZmPZ+LoPAolpIXtiqHvB+hrHTRJ57Ic
DruA3qYMPH3eSAG7Xr/9wLgS9Wz5FwvGu2kxV5BT8vd3fsZ94PYTLcfRNNfymMlp9zrfQkOD13wo
/E6PoM4fM2NhQ+7ztx1YAb9bJ+NDPPnC2u9ntBC5XZZ83Xc/Pyr9pVShrd7F8AmF6vIygKTGO1HH
3hM3By/7S3fEcq4BtOkGKF73R1k1L1eilN8iqVlseaxmRNF/WRxLWcM424/+PHSQfTpdRDfaDfoN
/nvCg3kmY89muYRJle1YRH+t0seGJubaC3jUJym8Z56xhIWwwxosav0TnScVgUU/RZKMcVcNkmU7
a8WbtR6bGlLcyIESGODlb5734KNejF8BbFj+qNipIW2E/+W9al04m6WaYhXxhpGMkbEnpZC8SrBi
dpBEKLXrio0WEkwvQdgLQaDJbD0ZEbeKNZJeAqGS53N7SiKImKqlj+wMq3Bgc0HbeF5Y7oN7IvUO
ArNFhnHwg5gf1Hnkqn4UN7oLeoClUSTkZ1tSibhQVzZThO+BxR/wEb7qNLCDWv/MhnbHxNEghtS7
HN7qa38eHjYl1H45RafwBRAIOyuB00ipyboFzSPVxtLXJRt/kTIa9jYw/HeNrndMhsuSgpdWHHRS
kcTOg0Z1727nyFFwO9F/hxpDcPrKK9ehU+1aXft1dUD+GHa9d2UOTJkqBLfqHOTDUuhqYuzvfCsY
A7Xo8S7bw3Y5IpnnjYrEf0MabgEQryAjfXe9NJfAjVGkBsBqU5S4xFP9tcw+hBNRZZIua8A3Yvxq
RzHfXTOotj3FuW4oKgyveA9kR1uWHYBaYBZvnAWFvkt8LjA8/oT5WxwwPE01gORgzy3nzDyO7C/3
LV5TY4zVOdbqTYJX1SvHFzNgTWpMc4jvJ1L8juiGRQRUWMxlMM6SbL7SXNW4XsuKmYR6cwlzqUiq
ARd7WUqE14jqt1JqGtmsskzS74P7Li89ss1fAUONlhSCTmgy8MIMiJDuISWKh4gx8AL0FVNZMihN
NU89dk1FgXtOSsmNPS+hpc+oMr/RLYVSZ/xLGVMgjFZLDP+/2L+G/212xJI+n+F79rBhGTlWEI/I
3AShC+Y2bmmwc8QNP63HDQyKyeYSFs+z4lBEH8rccVkFTsG61aGUwi6WZmqZHB4nnRrwwDljk/mb
35Z+9QnYMLbV7sTNxR5XHqKE7CWK2FyQOZNvNkJhXNg456ciDZaSn9h82WwEtJFiPZIvT7YIPM58
ohCPE+rjrMvykD9HxwoGfhOec1sKblJnb6RrNM9SCcJVs9rsGm0X+WYTA1wuThLsxbu4Zhdr2tBN
EaFbaC+z7JEjBjYTye2/DsW2MdT956+xLMQulLXcT/kXJt9UVgWsElxkHQ4Ws4xdmgDwx8MzVP6z
yncHGkHsAVqCTsCSbxU/9M1jsZAKFTgs0cDsT8ST2q/Axu+e56SR1KrkFW4bCXSg0rQFTQwLaXdw
h9/lmMkolwBFKVT/8tz6S5EOKca1ihMBTXjbnoezPGzs7xA07IJ0hh3GX4hm9hF5Dk4liJdNUWaW
AsGJhKbQAa35ylAFPyV7mb3dwU86urMJUa0A/6Juqn5W0z3g2Gng1Mb65SkiyO4w3+mHYvql3FcC
ETvhSdbSj9Ib2mUxwRPNEywd6jbh1zsx15t/iBP34zE2kycmzNkaPYS9sVT9LQSKvAJjIjxGZdH+
SaYGZF118GqrHYuFLIBlthjn0+01ath4HLeoGGB44TLnZr62ngRdAETBpTv76r+GltbBsq52zp4j
qqLWR/U6BDcYqGh4bucUgw8v+TlYMrdhsuTPzBxTIz6Y11OxSkZCsM9n8IuaVWaPCoWK/LjAD8hO
w7O5YWfWoz/RIQwsfajhyrOEGvKq1uyqg+dMd22jIDSvmS+udV0h8PZ/GsRevOAYJtZfNApo94Or
JKk/3OT71MMwiDi1WyM2C2IATUqp+GY6J6E7UJq98EtBnD4nccODm2suipwESPSb28Abg8ld0EGX
UKDUVDoLRBvv6LXc7iJ8wSipJSL/6iqIhfRRaLZJ8Mv2wMiatIRtou2qICTZYwYVdg3io8HPY6uc
JxRav3TOUShkRuHShCtFwUQDZchEqHG+XxVFkzo4z0xhrMNYG/tZ9lMsFG88sbytfWoQgOxZ5yol
xghh/ARhf6XOO3lNIWSucLcslRt3O6oN+TyQWQ8PwHJcFxkZEueucIUyDV6U2fua+SqSrLlakaV6
O6+/siur8wwmo0m9CGPPFZsyIkDjhtJ3oa+NOR35YwmCGs6RJF5QlJpOO3OE/FoXHzY1Tc2zwO/5
hnUrLCuUHL08AQ5HX6N7rAvVBp61T09ojh9Vw8uUPz2zbqa6CXD0LwfJyqUVnhh80IkNMKwtD3b5
D5LVOWIk3CpogLyY3NQnjb6FRuhTZBO0sH7MtFCpXBtCVZFfGkUZN9/z8hmsTdt6lp5egXcGEOWg
66hDCyuYepxuRiJ2le3SIwBOL1GHZPp+o/M7DSjjdZmgQqVfd7pdwIeolDdzuQGozJ8CNtmFtcXm
yZLpi3xZCeMpgEvOQGVk+QglNhyUEyCBnkoGMQcbVILyhsEYCjO1r/aPu+6YQRzSSIJVWb0r1urB
rOlXry0nG8vjM0Eua1BKwZ1OJU8TJehY1W/trLzJKdTboNyh8DebFIF2M/6SONEwO2y93Qc7JKmw
SvP/pZ8L3TlHJ8IeqHPpF7tX8Syf1AobFxITCFo+pmHis1oP59A5yCEEx7npx/7cMw8XHKqSN7Ru
GKg+9GMi1UxyrD/mvsdcc+l7s2yG/GJZhtbeHUeOiNwJPUwWTleYwhqRbsybI2G20u9gNqJCzN84
fEyr6bqxwBrXlYAlZrFd06RZrdbUOwPzpT57GsKs7eMWIqp0zXLeS0wHYOtTOXy0nF0CoH/vNOtC
BLNsEr+o1ZT38xBKJmv/cDKDJCGM72vIVAxwDGivnvGO/bniWPdKGZx97gYn0U9Pw79Ox731zl9g
aQBrx6dupt9kZ2sINFU80eu4UdkAdsUshP4Ddj3FoYnckwFWjbC8yweJFxyH5lxQiMaBoxCNT5ad
LdXWxs8IBdsQQFbBphF1/RhFQdO+VUONlPiJRSAKMZ4FLS2yio1h7OFZX3BVmufTYOtmjN12Ftqf
HOMQ9UZxGxrV06GgcODlMlqjF6Ge2oYcdum7TgWaLh4wWyQOydSOOUI26tL3C5NDknpXbTC1InhI
6qAXR1WDG3YIEDy+SNq9AWPzqbPBWB1aQt4gsmLIfw9eWe1UdyaKwsIrrdleJ0pHsVirrvMiGFUi
0dfwiSmnsbdL8DE5mJualI3ug6qITkGNqqe6/+cmxDzmnFYLNK8tq2eN9/Y1Rbmm5+VczgTgkeGA
LCVRJQqI3YkaXFDlKt1ZvQAmTjw2iU5Q7o35uG29lCilJfzX5rb/2g1oAG8FM56N8Ntb3a6KZW8X
8roMuJj+01vcvZ3YUFpzuZrEVGE+nAbkULquEcrkCF3+fONxAuQLGt2qh3TKRwk2qfwlcgVLao2m
81fhe9HAWgF/pAkzxtSxYzUP/2XS8Om301CgZQpFZLhzXgTqy4ZE3YnmvTLgQaDWUWbhYynF6EH/
2W0TdRA4aZATgBRuC8qtG0vtxDBgt2owVRmFTmwSVDtK764Db3quTQlMfj0yQNncZ+iM93MW2eCt
ZiK/R9TWbSKnXy5LFDLgQ9iShJ/62l4TcmagmzPhFIlSBp8BlzfDwGrRkekJTx8rMMw31q2b2lSj
VcItDahuerwTsf+4vQSwScrJ9L7ulGaustR3do5/3Z4v7JKTyvFSkOrsFP9ckJ6lmQxlPgfGaDWH
t05GM37syz2VdG1VvrRbcC3JHQYhWb9EbKsKEP99xxdl+//CPlW8jouqYFl6Oio9wFGfEN/KawZB
NrucvLUWc/PS1p+lSb8hZHIdtp5Sk3jmCgonyZoVcU72hMBo5Ia2T6zToa4WoyvW0l/usZzLqRoD
CQV4WuDjnQiAVjczj20wPNq2o4xRiLQgiN5MtSN1vuJLOjSowphaK/mAm0C0u54nEuejSGFSvQF0
FBD2TELfYi6vP9tyzB5iiz4JFk0Twmu9cv7C1iI9Zi9Gx7/n13n4eH3beQLr/anVfPoOtWtvo/IQ
1933lVQN1vovaXQVn1yBOUFtB6qh2yVBsyHCuLUryFlh+SHlweDjjqAXASGIaRpb4zILanLUuqF8
1Dx0midw/aUsKfyRYKZgHAiRXkd1h84apmZa5w8CfO3WQUv+N9/9QVyCXsFmaUvyTGQeE5Ag5F2+
kOymfKmYZHW0Ivu1I/u2uZys4eoZsQGcIm1jqFGLCakCw/CwzdVtcuqdlVzZX9JjtnR66otRgqgu
dJB7gtXaA0l99oaxYDH3gKXmV8gAG6RBgP9garB9JtxRwfljxjWV4a/s2om8ZGiHXpRM19lQWBYO
/uVCyHm6kT7ZaRAY0Hc87iIGOMbhViCNUw9KjBRWDKmN+m7CGr4OwaB0EiTl7s+XLal+xC69ZlHf
3PTrbd8dEkPwNZw1ck5EJYNlMpnAzBiNNkcHS8JpYmUZGYR9s24fPWDnOVv/cYOFX0N/+M0kTG5F
NUgo5oVfAc09NlSx3EUuNwuGDvzHZ4GM1V7F+ZaLc5lfkiyyQMU+Mgf8iQ5927gWpA+aVYgNV2Ju
OYcqueUy/bCrF2K2XyRi/Cis73j3ZS6uDPxEP7LCSlgurHAtE85OSj4Y7LA/DM3Ov9pqMJslXEX8
hnzd/8fgoh4B5upOTn2DUGNw2jw9RrIz/dj8X1+DzmTwdsSc+ZbzOO1zBo7Qgh+iP/alcP6v3uZi
ZXsJUPBfXXTldjHU0ftgW5wQduYLHEAzmwd1gc8FHkHJDuIZgP3XkjMh2owt8YiEgC15EBZstDGs
yd3mVlDuT4dUk+nd5ZWoGVSlZ8X1suxJ+JLmWE+tss0fkxaQdN+87uxsLXo+Y6FveJOwcS4ERkjw
VritymYicUjTE6bfaA5F9pfhX8/WEvduMdUp0afRRbjm5bdfoNCpA1VEQsMAzDCU7HVWFlTnvhrq
eZcQmxdP6SCkvJ0qUmQ4hDZYLLKn0Zg/TyKhvUo+PuHLY8gJLwdMO9cIuOHjxBWENhv+hfpn5aYk
uKMfM4dojiMtGYKbx5jhDgdIKF5BbvsM1zWsfb4q6xPNdPzzUz7P+GoSTeZ8JvGsAN380+D4ekcv
hjvJ1l4v1cz7JJVQgw80KS59oMIuLgvEz6hu8Jmrm/Ehy/+z6ZoboTq98Ahr+FRSHl5rjD+l+s+T
JjoXjygL7QQb4Rh56Y1y7I1HwLqOaZhv5JSwpcA1B3LMpxJ8qcoFHMJyjd7j1vW3n2qYIR1h5pkp
dZBEGza/un7B3KLVSJVgYuNmZYAy8drbcta/9DMXvqK148TVvKK61rNymsKfHqh89AhOp+131U7F
ZAfbFt0dYiUUd3/aBZQYijOneJpAn6AXxb3TGprdEM3vT6Vjh49LbCz4/qG3C5Y/UacERJ/d1Da6
9SYtec1mEWGa6rSqziOFh+WPbcC+xD7d++o9jLwIbanaiheYuH1upZDoSSZliNYS6Nb61DOlqfkv
lScz+UEQdRNSOero+gQnABTHjwNmAx9wEXZPnKnOUKE9W6ez8fPAct91JZxf904NDvg2M1pAGHDr
9cHbgqJIm7Rtz6O7GjIv3+00KsxpUZmlUfKNq58pNnbiuqZKFdcQjIv2UqjVqfYBCjop2nFpigIS
QthIhCJat8ykeSEJMBO9JokaYsl+KF9KSePP40mlIMaE7TbzoyGkLwILwCYgrguL6mMlH7B//Eay
/+KNo/J/rgxDQKcaIk2TP3RGelRr4fX2eKSt1bBeiv7C+iJ4434kojza/WvERtJJTHnGEbxGnneQ
Suuwy6WKC+Jp/7rQICc5Le7L4HSXouSsEftVwaecOllWq3aTjmMzKgOaVRcHUzZHW4BlScYQaQxP
2ksh+ZayLAHK0RjGxhcfybSroFv6xtKvnts1HY5vaEHFbP14Kzj1Wsl/sGw5V0P8b467YCxGVRoy
m70LkRmSKzX164aBxVCEzLNfMEFQaQLPhl6Cpi7/N8W4H300hF07USkRPWXs6qgEjFqTzYkq5r6f
0jTH18JyFLkMnSoA6eHpsUveCZykkEN8Uk/3fn9cvjfnI1A2tdhcv8Qle0rFtc0v9VLOxOSx1jsY
WrkEogWk2EKy8I5r0RNKCSzKIBojk107lomVTwBpyiLtQtGaY7w2gS/S69iIVItovR27ow0rBLUa
IDbSRRTn6Rg7iY1pcMb5QUK7JOd8b6MEBYKqJIrtdYwG6zzxMVgjH1Ant+/0k0Zfg98g0bDyUE9+
OJ0T5RrK9RSUg+PvZ/iJdw2CMExZ36LEVe46yKpjAA3Y8lKDx1amkGSIpaQSFqL6akwckajxSbfK
0uz3aHeemj3uErsWVAowP4fXyMWOsIkS/EUvbbIHLHqS3sKfiK8XlQYRzYRFUfY9ipnTqnjFowCT
beWZkg+03FuiktXr3A2S+lkblthwvaAWNc1qA57dnjz/g9/C+cBPJ4uqg1jLaRILBonmQashr9R1
MCVtjdiNsQ+vMRW9s1ItUqpXG3ZOBS/yzryK/a/lKs2v+wtXgW4lyKLwh+XSlVsxLiS0QTjUvcmG
ED50HuOn6g5d8IufBZM97BF4RZn7A/DSAEICNIVYdD3qJd4GUfVPKxVRUk5uDTFtS0w94+Q7R/ei
6Oe8+GjhQQTm2DNZELkuUJnF5M4POH6/x6d3US/+x7SV27laI2ES/6Cy967wnMz3KYatE3Y7Ov8S
hjds2RCvr0MZX3MtNY98lSfSRzAcJefTDUzpHIDptz8wqdqv/v+vhLOsCfxzXPZOAJ+Tpqul8L8v
Ey3Bq3kGrpPhtIq3XaSOYa26R++rGOuWFbWFLK23UW+6gu06PMmdOoyAWhdnYA7pREwOP1X8PhDD
U+EoYwhTwwpEU4okeOc/Ikra0SepMq8C0QKFUbQaOCv9ERrb1USGVEFtrUvvlsNFGbpZE50FzacN
UHW7pysUicibltfmGwzx6we8r12JdfXV0K4XpbPqk957C37sFhxVK0ULKjfHh+ZWgmAbNUkrMQjF
0Yi1d0Z0kd1pZjH5uI1ZlNdVB17PNLDx7LPnqTm5bMJLIS89KloE6yQxWTijvWoAf/5uj1nFA3rq
loxUzqOjtCf8kT0QIRHQDs9CTikOmSkj+GA/6p8TH29rRks4PMVygV9ot8AlUvwxp9fbGFqA6Tk1
2+8btOhQ2GjymEAfi1H7DRLnMwKieez/7JsFn2Git4t1459fJgA2XP7GE662Yv01DqVRdLAc4hGL
QdwA04AKLm6l60dxY0YrsoY0ESAnvN+4bRbY3oxMWzGrLIUkz76KrhfDrmFzxG4d8P5xzD5BmaPN
LQYP3365Gdh2L6j0pLxoKBwk7oNR1SMqHUzAVf2g73vBe/u4iqfFGgAvFen6R8Z3nM47KV0yj3lb
wUkRgySU9DOEkczpBZuDp6np9dknwsi5GYq9ln9DO1zyaGw8CgQ9R5Erd/UOqtD/2PU9rFGLjv2n
jy1c6HpcQXtrhQ1OrG952e+w265V9MjSGdC6Zcg68wCdg961u8CwDgVCbNy2klRMiFgSn2cQbEXj
JnHHn186n4J424sQWkAVc3ys0oigMMaI6d9+75R/3oObaWbv9xiIHO6BBEJIE1AUyFShqHPQZjwO
+xB0vAjZGA1uLNaLzECZlRPgiUh8qUg2P4wlEv4NHWdjTcYBBerbiJpB44sx7lfSxxAgIieYRWKi
DC5bM/1edUp6uHuq1duMBk7ehg7Izx5+JnMuMAtDoIoxY2zfnoNYVFUaLg3M+BWT/bbulOabqi4m
xjF+Tf9/ZpNjaOt3GrKOH6mnBe56eZ8uVEvhyYgvXp1yO6UN2GGUs5zN70Jr8HpChdxFlXrC/sM7
dNrg4LDJxfYNNijKKrRZZmVP8j8iXNKTd5bEDLEGQmHxknFVdBO+Pyc7vNjpcFpTPeJb2G/nG1gT
Lo6LpsjbVkgdA+ldPnHgyPazkoI5yHEkvO383S+cKoBiByv9MwvgSJhiBPeYzdstT1zXSmxzJLX6
bdtZs3uMarqZpsjf6gqAqOo0akN3Yir6O1x58FLyUxx5DPbEyHov+L6N9hZN/tG4WKOOvLd4ejhW
fZjhvOZRvldkZIKwjUHp70xSh3HFKHzIwf1Bb51vPgAGrhHlzq9eK1+2gAUlFgEbKBO4ny5QfEfn
tX3mVO2FvmTEy4Q5MpIm/HOtUDcfyixYnpaf8PCkws4ra7TQJb6KPyaUXvM/BU8pZ7SuO87UVJpf
oMH7tYLYYJ1H5jFxfsm5ZD6UqbjVnWj2MQi+fR60a10QqVJxGEtcQsFmlWk4vKZTATPOeRsCO2As
kBNquL8tLyX3ddH1D1N8ICptugLv3UUJ6nwV6wi50Z/S+FOP1NTKc4QYUUPy+N90TFG7fXYe3mE1
ASQAfYyEpNXy4noQXi+AVrQ3OcFFkA3CBjJhXJByL7UAHtX6KsNM53BWAvOM8zLC1hhVxZktJm2R
TADi7xb59WyI1a1sYpTsASx08WurNnaCCBxiZ7tvmX/VYk3xhInU20SC/h+iF7bJ7JLq/aXg2DeD
R0vdgHUcLRmINELkgAQWT0Q4F6whDdx2FzjEW83mF/U8mF5v01eXrILXAxAWkvO5N2afETrj26uB
jSIyBuA7F2AH+JAucMG/H5Oze9ZrqahSE/Z2lp3ZmIpv+7c5De7N9cD8x63xPKiu1RH0N6d0YXdZ
O1ffh3qPKz8XU8nFqFhI1V+KFUd6iYA4MKTDaOpN3NFnLPDt0txhV6bFaDPVmLK+TrxiZDf6I6QO
rJgw58hrioYH0bLmGsMK33js91ODLrAzxnQ1isglukpxthtxV06H3ZO9nkBC6CMhye3KONkgwStv
fA2RQWgNt5zASqzIORbq0Rnjjia1LKEwBuB/KIeooVWfaqF1OvnEcepNYwu16TvuO6VF+3SiWA10
BQPm3VLJF5RIB56stcmAbf9pL6oJmYf2PGaSg4/vMgkAlyqhgbtLNbERwqz0/ynp1DbCbfhwhZih
puYJL0tNYIvwyRZUnuSVOmZQTFZ/5lpM9H+Stu0kk21uJkYdiJ9Dchi4ahlkYgcBdQd6PXODMuY0
2MR11RWe962OqNGq3JzQTaNM6gpB4vMzEyoWAan+Nb4WlXLmr77KWcfQJKJIH3/ZS0oyg7wW8Iis
cnJJceAUgKjw3jzC0L5rnz6KOlK6+aS4W78PJJSPCUx8cy2vsMs6OP+pC3b1cIJsvK73It/tCOX6
eiqHmCPjDf/UStfTOD0oBGHNBH6oqMGaxv2CKnbb37khPUlHHktI/p53JlcNGByQOBWX4qRFn8wJ
UlJSOiJ1+dEX9P4R9PBXCcf0ZSLKOCtUk+fytMargtrbmeTnNPxzVPJYik+Uu8e34ew6rnbBfBNS
wtwNRduJUseL4WZb4h91LYRrdny14zy+0foJQWO5exdT/sBmLa9YreWHoxTzBaDOW1aiWe8kaCaj
hCBioJ6MRB1CEInSTJ/Qot0hPrS3trRoZoG0FQ3MSid0JXZ6AwR/vjRglbwWN1voXg/sDfk8vrdt
max+FlaKcKazR+YPVeJcJmyArkvOfrvuK6Ym6OSMYQN1hfJwhaQSoP1Fiidg9VxidlgjhEEi10i/
bh+/8VeouBIfxm09K6XAQeF5h+VwxUTJMSwYNKB8P8eArw0F2rOIOhhG7y3BZSm1cQ00eewE9fSj
+oxFxppyP2dIb7qNkRaKnCRyt++9Kzn0iIRf9V3ZGH1c8xq2fUyEHlE4ICDmrBPffx+We1FWubdS
sc7tLOIODv12STJ+4RXPXTXUXCCK3ou+wi3FY5eL2IPxUKkOLzHu9hPO3864dhgVauDTMtelXIpB
PqIz20iYWpYDGOuXybvQtTBlFgVXmxCsuLnzWE66y0HPmJQjkDIuUTi077ZYNI3rCO7AxZJgW67o
jR8yr7M1dBOUE0SOCm/N+lyDOFw6X59r2WO89tRQh/2IMrDyK9t6KVnHEGasElGoYPwf9VpMzS0s
V/MkjoEautvoOC2RQcO867Ni8qt3X4b7kJRjqoi3rA4Dqsp6XBaSJIAvW1u8IwCj5zfiXFp6Q1pv
toz9KLLJ5yQM6zSwlk1cXnrLRJT6GZPazFWNodeY20IetcHWpGxFNnu/4Lces0gfcmt8COB7Gj6F
ZI2hfkOteUFWkMQu8/yMsWy+/SoCueSYJAW3w8wTVMIUcjkSBa6Ega6oY2IxrEpV3oX5JDe0L8cX
7WhnCgm66Itie1zcz3F5dhgPxjh5idKOYctfNro4EaAza1fr+OEcQ8VGPyyugGEEA+Rrrj5vhf7J
twHBBottYF2RM+847TuETJ9YWf9KRrA5/VSRB/zp/TlLSNqmrCnNLQ7gc6uozV4cirFbMaChiYvJ
xvpQVlmjzAGdGZTBaaJsZyuVeWcmfnklvourPNRFflfQ+n4Y7Awx8YAQOxmhwh4MikxNNHM4egOi
7q4okmE04QzWKx9Mh+q1gO4BF3TAsBlDNiozGHivd1rnTSE4apC0VqwEEWklPfje5SjlbT05umtK
lAh305m2Kpt+ApassAy4xny+gWUbs8oEUUbjHSqNb1wBn6jIBkWJuoXQAeiyFMB3o8fQD69yxKqq
smz0Lm/nJR9v/O/6nAiBJ1/awjbW/AiCCuOo9HpzjAXX3kR61jKcaK5Msii/9DoOd0yAJTATu7CX
jLB/HJfOw/m0PDgjFC1grU9UaajemGIjP//cm95T9tPVkX3V+DhoO/62r5tHeycF/G6SlGnICU7h
sfye1pT/NClBi5iDAwxJJczy3mIe9PF5Gz4bBQ+Lh3Tu9wbQRp3YsQU2jDsKAbbRQLA7sa+O+f3i
+1r1nWJQlN5i603kEMbeIzNWoVGVJTJIJTg+dLne1hSfyA3vjASXLX+vk9fB/CT1x1LzFc1YvPOV
JRsf54F9YjWz52Dec2GPg6K3qPXUt0nTyKhUzwcnIV3dR2PMD8i5R6Pn+rcw5pi1ey39J3vEqIqE
ZXZEL6z+hyNcA13ZcyTNp583CzKjDJ//cTRxLaWwc4wLt6Ehv72NlHnOrcCxoZKuja1BP6y9g3Ro
pwGI/qZR+e44OGIjuUoM+DzqcLoarWUcPKHwqlryuhwMYPMKalLBEoiRlIuuqW8i68V75U80aLDP
B1/SJ6LSmGC9hy41XqVrdt9cNRMc/d2mWe+G5+WoEtssjHV2ijI0E536El2gIb01izaiH+Onl0GY
aEtm48GSdc0xXG8yBXwZBVDxI0+cvUHNuuwrmX+lf+LDE6VaYccEX9CDWqYSKJ0jvPuvPi6fRMhb
wmbanzi56MtXaYSQzPRBcs91cavkvekMtO8KosuRU7jCXI2XIfh+uTstvp5DOyTkQIuc4wE+R3ZW
esmQRuKx1LhIFKkpwuUE5I+5VwZ/vt8RMPEjMXAit6KhL5opK4AtlGRoU7vbmq1jDMuZ/Rxzve8f
s+VuMwfL2xd+TPd1TnuDSpz12cW4/AKkx24L/u1LCINwVuBTWNfjiR3clPw+zjHgmFTQ/ZZGVcab
HBdsVO8W8382VDe8XAUwaIaQT6gIFVJJ5dFVWcxbSA7cvRGk21Ay0Dk1t707MGU0W9ggCOL/4O6j
oyC7E6jAE88r7cjVlHVG1aufFI1PmIz3xb8DvDeGFHVa+iUE/L2pvh1BZVLzHMUkVQwHs331g5Um
zxt551ygelsm9nd3b1MuiNrlcf3Wcv8cgdldw12yB2V9K0OSPg6oCpuxuTO/RSkYJ8+fBanHB/N2
gDjotHICBQ7y0I12gvLhjYRGaU0WUNyfU8N3DWEEKGhsz5+rTUf3XYFYggTkM78knwGd55yuexg9
Ya9/39ftCBCVbyvvC8YZFx/lrnkJ/wam+pIK0ffCYQ0eh0/V5vflCX4vESC5/K3pj7yhOsxbvCgB
qHxKZd0hgQLnFlFqMBW9WtGN2XXqXA/oezkucR0oOiT+qvoShQmoXJq79AVQOn3RPZGdRw8WPhcU
r2bDjkeoJqlmOMx8NICWn7X9maYbuypjWfDe0hCUqkOhHNW2pagqPHBIpW/FuaQONekbCDuNiqS8
zzqqc/ZHmS7/IWDCoEiGH5k3V6oAs47yVfU1z0twqKPf5QonOFHS4DYb172XVBBSuVqpi3IFZG+c
s1yp4lNaaJ4xb6U+DxSeP0WdowXUVYFQfBjjfiaEwdG0uJu3xvif2IyaL7PyLPrX3VmWRFWslETe
HCDepn6ZCvXflUclJW3/SNtLoXLV2RxKaU39LrGrvahjUUeTJ0fNeZWFl3LgO0/qbauZ62m+0uIM
tceJNT4+Vj26C6Xnvf/w/xYwelYR3IzjXLUxO6kfr0G+SqDBSpSM+fMboiIDmZz0zaaGT1WlupLG
8TN6YtsPlJOrrZOIeiPEWEujTaTj8TcbMgjboJFK0iI2y4E70cToIPQEOfC5hcWSjoSdiGlgpmho
IDWIco4SY0dPHmcSbn5Csqh9wtXi4fheS8qp1R52jdc8Ujv1/N02cYfoNn0C4lDwPjXYTOlBKNzl
na/8dq4SmxPM7HqurdkCIixBWvD7CTVqC7UZ5S+xOZTyw0kWy5hpXIgrA1q3vjIUQZz8Yb93Wdsq
ZN+9FMIZ6SJIgfOJu4WpacqL/umssef7b1wsbOd16rNC71uhhSnBZOOsmQjkiYMW6d9qOq0ErUA5
0s7gylg6dsQhSfj6pbnwxYRRLvVXvphZA8N0axH2s9dCs3XYOD2DJwiZkFnTZ/MCYZIU+BGRl+RV
ZYafioo6NfZtt6DRQAkhJADNCYTR7Kt9qGswV+S/Ezbm/sNQRYsZrmQLzhTmLzbPYmb+wIzSWVxM
fSNhTXJ0e/J9ez9Fr8R2XZ4omZfeJyobFjues30FrA4OthbahJOqsW7YZL6gHHyghlZuyDGaktY0
4L9DoiwMwHESI/dlLuVXmQsYPLPM6NHK2lIo7mkWC/gYPqYE+EJyCwOj2pzDPneQE0RmkMB3h1Qj
pVTrB6KXjCjmdxV5164ro/j49nP2We7lledMHeWgYrq7R/wMlsa83qqdgWxRZ5guoiedAFIDf+k3
oGB81zVLd6dB3OThmfK+1sJy/yE2qdX33Wi+iNMEUTzXpkWzP4PQ4U4YDcgs7vyxGumym24fpCe0
okr1nw5c4axTrR/eqJ2SZj+JIK9+rMcLdUI37ukgX06nlLEGX5R8bim3/EQUstJmzQFAHLepz8j6
vP4/eak2+j6PVspS99PUrkYxuU2hM5aZp+65QnY5aFzfDWdI7a7/mM6N9Eoyip1jFd3KKva1Qt2i
ZjocBQ49Qy+UryOhC8GrBdkI9S2opp2oKcAMGiOypSgkawXKU97IUxaU7qO08KgjJmx3hsfoNA1p
x5OCJ2Cny9EyvuF2uWdIrC9w4dZP86V4oBDjMvwzt8u6L5s+m970BgYzE9Rym9K8tsl75Sk6G0B6
oetGmQSLnBE6JnzRG4DkaTmc4lmOuvvVx3sEb2nMx9+sTLLrC5cZ9ql+hxarm27fMp/VjJeFCYDn
SqTEbV0h6YoPr15oar+VO9z4nDsB0nXIhoXfBadSYfBA/XCqHGi0hdsbOKDGWNGtR+khlUmKiOwK
FPBxd3u6hthyoyByCkJAh5cB6iVpn4cP9Hm1rJ/nDX9lGBKZVvs1Cjew1FBLsmIgQYmpa03IFTTP
WRY8xrSAviwKyfIVgM9kBOWVEgk8ah94a/4G/eyGUtejq5147MsKFWGOyZPZ/WJiV9Ucx66hwfQz
paOPQZp5FeCD7UGIH7Zrkk0wL6/6BfwMxyVF4YF7Gqlz/6g2ncgyEE0cAeSKjwXWtoi8Bfsgh3KV
PIagwpn4sh6Y/EXoZZ2U0krCMGVec5i8UN8pRNlJku5yn4JX6erxjRc8YZrMl+TyzXqA0loSFu9b
uN1c+4J165NnbGecTwtbNK5pLr+qTlsOM3bCG+RvHt3mbmQa3bMnO6eRC61rnW5YpE+H2BQra4Qv
Y768CNkkvcFztt//sArurHi3++SvdiLeAA9WSDrJoNKYoLz3JOMYawMTAhAxNXI+3KmdBno6IssI
7LTyP4/EMTplZu129IAuY1Dl8XNEeDty+GB7LrPoPX9QhIP97Cpk8HoFE7ZADfcHv8iUvfK7HA2J
xtvKSefOrAo7c9JUth+F6g+ygBb9639XrsF/lJk4tqBMSlCX4H6T5A0l9VhIR6d/wsUUsLsNC0od
MtamoCP0oesgzfSDfXtUM/lF/4sN9SFHML7/ML4OyHfw4wp18cfDUIepfvNRxe5KwssPw5xxe5RL
lg6EaKTrfEpGuMVcCCPY+b4maEKdh0wOlSqFr7It2vQXFrBKWU8uqBtQ6Q/qOTnsq1NhhRX8Bkj7
zhSiTE8GQZCobHzEfoY6wvUOkuczgqU7kRrx6PdUukl3CpiBcqSeNWDin1kL2nsRcsOxj9N/XAae
EIUguJGEL3jGl57jY0EmJJWNez3UIvLi4kXEcex+sZqMXLbmrBpAbvsl/2Wf1s1+UtT0WuT1oheT
9sXlM0b0Ihfe77SfAgvmSbHZ1yfdwkqit9DvBBiM2e6M2IZ+N2n2K2hiEfjxWV6RnS0AOm9yNTsl
+IoMDwCLf67qTC1A6Xqu7ViAsl8HRfbLjNyYFwHqK8dnpOF5I09kkKqLXbRjk5gflE+Z2P+Xx5VV
La13Xgi5PBDIfRL1yvCrIhfnXTUigKODTWNnYFTo2UGM3wkgYU9wYEFos8o+tgGmtQefg8uS7Lsv
Qn6cFJH7PJqWzugEi+fLmcsJNQ2zOz8XbRmnzQsMDzRPZXQKkpwWmunXI5oCz4iggp6IKhRaMWPW
kQuxv0UQnplvi6+XL2HnwEMM7Pw6wRhYQumitVE7OdKXSMePrhfNdKhL7lX06XqUL/v937ZfSU8k
lPjWC/uMrbJ+vDIuTZnxsT4qok2rC7vgADhrsBOdcbDZWYd87Sp3+HWkk+T4SPIyNoA+08peDNpq
cpWYfTShliscCgAJxcpLXx58oBtYC65m7UqMbYmVo6qwtVbRoCeICrcZEcNesJFKxDkgZyiCe2BH
eXiQHuHwRCOpSErNupdVQ5YQAAcpXMUMznGSkM7BWmOU/HnyM2EZQKcAzKXxdv94GMhJNgIulE/Z
znkJuyoOr68/rt25C1/iswisjP0eVtyq/lyK9K0xsMEgpuDPZ2OA5fFdbk02kBgiAVkql66QPf7R
7CvCDGQfnfOnM0ec8fPynbnxW5IHTp/Z1UnlU4EVFEKTTe+xCauy4sh+uwhdCN/nMajauZmZZ13K
y+ZvihqqlNCqGC7zRGzLRoICsbNnfc6C12hULmp1bcs6NGz8gD/0heP8CtD3oVP8vaPZBDnp+imy
DDElpY+iZ8mVFW90DRZL9vDUCs2vDmpESo6XZB7GTEzmGZiEVMelb3zRC5Hwu6MjFRxzqtzazFvC
uZvzRGEryz5v+QSEdAUrurSr4YrKgyUG3CAIz36WGgCMs8z2rHaQl+nGlPygEoGtGGOqW+lY7fD+
ATz6pWQlKCj11+1JY2fhGUVOylVxlfgx6TM7Oh7uqRU35VzX6x4vnIHs/pwZsPTXylGimGmLchSv
iGwqxd+Japp4k9E3KblLkDRkbcX88iDdtdN+Ek6c0Kd5i8te5wUXHCQDYye0ErCSvtDdTNPrXe8a
NJeDMes3WNzcYqW7yfh1Bn8xjlTAVuJ2dBPnj16CVzH/Aco8Y17rfFbRt1msdZA/UHrpzuU7TpcP
G28o1r1LlfV4trmAVRxp9k/bd7k53FcruY2ojQypfPbIfGFPfnmSi3wV8boXGZA3nCdvIO+4+x8H
Fo1hv4dMyQA8bWsz0SIw5DnIpnM/mA5FladNZbKu5WvMNxD+UCQniOu5YVLjx+WLCErERNtuSvn9
zyVmtECzUyXu6bWGpmt5SNI3S2NjB++CF3axh7kOlNLlwXwoc1ZxygfllAmfQPHt+MtHK2AyALJ3
8OLuhn+/QaMaSDJsMMPfS3vqwIytEgMULPLTpe3I2AS+MGc/wdgnVpZd/ZxErNEN0HhxsAeEuKjP
hNUC5h7Aapna8l6PNdfgNjdEMMLZxh2DnGF00m7/E/hy0CQ1pOBwHJtc/xcvOkObOQoCPu4lp9fU
bqmuMGWhigufS7pqoSWx0fTlokd79e6ig9GnQ4NYN+aisRb96JdGuMNi6ItIPHZfNAlag8DtTGoE
f3dPyve2I9q7Ve8+OrMqQGIiZDssHaGKLallzSNA/r63UUQsbU3vN3xSOiWBNHouf0kW5cxrsvZY
L7lINRKlAmOTopdwwOyPLU0I65r9RQJwX1mOPYIZtzFVp2JgrshNOEG2ZWouLgOLIGv1pb6yZy6c
Gyeod03K86bguaUZkL5iJKEBB+1LWTs9DJP8Abhzt7QQXVYdgzFZwAIWlFcH6npTcKay0U9EI3k8
BjE8XjPWYd1mdn31aOHYCLyLoFED/sy3tHpr5sYzpVxY1CM3QXOPuUYjwuUeDk7FGBhy82ax3vOZ
GRE4OZYP/GK07ZZYutmihXuvzERuYXkadNFpHYtB1uq1cBflxAT/I0WEs/6HGprMxcivcghuOApj
mbJ77oqPOqGg1vwEYPR2q3xulrxd25kq1PkGSFop2noy/g60OcE1vM9UIR433N4fk6RfeASCxjXi
pMKiC3q4dyIMp4aDBs/6g4XY6SatXA79VBKXPeB4LStNbs9mIBx8TBny94GA/XIIylPQxKjT2tPt
Fs+c9/7qGAyY8gbhGR4r5ncZtfr4+z223RJHvL+kNSjTVyIqU1kDHr98aUgMdfEMF9+iQ9pAhNoF
8tbd3lhJCxndH9S8jtshaKLemjYmC4gzWhNuJN3ehlbPq4mSa54LgQRoACv4ofI/aar0fCXdI9pD
PUrg5++DBOi/yYrxnk9UXCvb/z4KV18HSzEl4DR74QQWW09Go9Q29sL08ocj9upZyajpSc33LSCC
Eyy/Oo8FEecW+XjBRjRPSADQHXDVYYFwm/fD6Py6YCzka46d2SCSbZqH8dn5SrodeCg5JV8f9i1E
Peyamd6Ukt+DpOxkc6JXvcNJTiEKhtRfH4XSLEZNB52TItNp87H3xh8BI5eHkRGe+Uk/WJiKodvB
UrU/ufS7n0d8HnU2iiTUSG3EsljTNd2gxuAWbIvt3DwJ4qQmzKCkIZjVkSQGK+zTQ92MDEg44nID
bWyCUiTABZTP2bkpjuF47GijpmbDM538QlBoSkVKaGy3jbKTF2UJC+ugtzua/xm9S5DwIOENqqWX
VUrFjXoJeNSIW3etsnfLlhqNTMNr7enzZgZluXpmbC+rv0TyDALuyCOaik0hJHnqEaZGimrvlBeL
1/YnIeS0fw+bOkd9Z4Fa1df8FjVzGvdkU/9ilRt0n7mFh6sAA02slmM0Ws11Hq4mtZ6zQabOAL9k
sy2ACLlEiSfO8c7DsrWWGGHH8iaqPzLFgzatHcXmRd9ovb2/qaC//S+uX/pslDCUgp4alR/QmNtb
UDx1gC4zQMGBKIgjHVyB71QWlLs/okUhC/emZuQdjWOtXXm73gJ5fqX8m0NIsCysghDiz2JNOxl7
Qv1CExW2gIkppdJa4BNOBGnXFO4OcCon5yTtzwZg8XrEvO2H7exLBYUpP5ZSzniIaqE1agROXCGk
ZKbmnW6aF8uVnXVxFHqrdtK1hZHieFjMGQ6l3nHNPNwgVhg0mSe+A71eDuqYdKPbMV0k1ou/zoAv
LvFLsYzR3IRWPE9A+7b3FrwsvP9Ehh2zGc1WwDtMbsvyFJ+GpOHMBIctYtGZDOozZ4qbu5X6Rxm3
CSbvlQJpMHKFleb99Me+wy9hA7HKjUVtYGcjS4z8XCH2NswQ7P+CO2vOrsx9m8FHSxnZR0hezgzi
ZWKvDRbyxUrVe4T2CSVaxoI23icuNQCrOl/YxTAkduink6YUpR3iFAikf4bMNinVA4Dh/cTJdKw8
HSBFeDhB77i+dyj+PvwASx+wNpeOxSurig+DzS5rEYXmYTsSq3REg5f7oxJz1+sj4AE1FW4pRDdo
fxb90KozDGGoL/QxGUD+Qcn03182ZCb7D73dCYU7PoVbSsTV+ZKm8yMwkxw90sK3edLpmgcP7iiR
fTRc0wmjxArWmRbFWeMu68W6hF9FTUqGNZDS7yuEAlF5izZImhX2jWJO2JfKcJBcRNvIcTHTRGwt
im248MsPBauQ26FxPWj6ImBc6QsRxHsEl50gmfHTl7PbHTfLWpH35u5zytZJFF0pYlEooLCk8fcJ
DbYeXGcs0WjC+RshqorkV4OKLt4yBn0U8++IONVyn+f1yjxiKXrz+UZZVcPDNK1InOVs5vmmfICm
vbV/ppOcg4yluURAsoZc1sgAUVGOS3wy0BJT1CNLn0+Q5A4yfF/tufocd0pJLmcFdaaZG/dcTnKz
gkFbgaPkJGkpFspyHK8e192uLq4afzKqYUxqylrXszKx0fqu1/QP8JdC+CB7inLhDl52FzQF3reW
SIQXPJZR0gghlTa5s47K6qhhfjO+1+1W2YVDDwq/uC/nUi2Yj1A1KSpuk3weKf0IKUeUbkq71M6o
bmgXv/ozl86XC7o8yW1XVghLRM838cUw0IU2nfs2F0EtjJtas1+1kS4AfVaO4/yhKSAr0MBrgQsc
uvD22K8CP158WDjzVrtXh2rquQYmp5RyEatjR5/JWNXikZDdYZCNZBQ+D76vv5fRBFIX7zmhDKbd
DSrky5ZW2jcvQlh6CpJeEzAs+u5Z5h2iJS11fXkNKEx1QwX4LsfuQwTIk2REvLTTIl1XUFvCqnOt
nH4dKBHAIMIFbZILZbxBSAPDo0Q7RIqcgzT1OWdOItsRBp8gWZDv0kYMF3VYwo4wlqUZk/Wr4TwG
BxAwRY0giL582i/xr+OSAFByRF8fjma7mOWm6WQ3OG4mKEq5XeBo0hrPFhn/ZIRFKLXYqYSWF1ct
v+lMiFOtsqEAxyihgBOIepJfoLMTheX8YQW2uzIMjhdb6ILssMsnC3C1Z+cvFn6d+2hgEaC9gyEo
VLQhergY+bhkg1PtQhLmzxVnb8FaVyHcbWSaa37eYraCCXPC34OnMCfDlRSk58KqERq8L3UoXjGT
08PY3w3bM0mS+TMtJ6VFT8jQbo0sJOHuz/pAquOMlOBrBaBW/wfQS03NpDJLlurv/kuApz7XuY0Q
zHq0iuiCCzOGODXcHcuR8XzSdCn4DiGCSF3ZmpzgHP62EH6wyXB8ib/GvFZN+oljbWs1WIaO48wI
86wVz8foxlVKRe2Z85qRTpEVbXKh3G77Z3sAGQugnecx2bsqzY6VbBRgvmjo7TPG1PsDEezs8sq/
K4XvsBl10oNv9QeFOQzCc34YqstpYNcP/2ejekgKEGe7gRJ7jgienTc9EZKYdsxBKgqOjA1ev1Gm
N9dm61c3o9uNC67rTHmJ75ai6C7U+A0XLj8cPilo9arNhPSIRdJGdLqWhJYbWUVV5HaJlVYbdjwi
xdY3Js+g5/B/glk4/ij+FiLm27Kn0lZi1gTRDironN4ZXFn7cz2knn2E3v3sGzZf6ksDiUAlcwZ5
mwCp/XA60IlouztI+1STrFYyi5RShuEEzVC9g2PBPS50KyK/W70mQylgRuBvj5txKSGtHUyUpLnP
RrLpqaURdF/1waCkpgWx53K6kYZSVbbdmy8+kaFa1+0X1OosIs38AnUZhcX6xv1yrZv1C4DcHl4O
o/OeGA1v7d1GRRCvpcZy+OB/YPXYPc4NCMcfGO7PpAetrU5/KbU3q2yPHgGvKxMqGVWUj4+pjlFe
3GLYIRq3pmVHTNGuB4bN24NBSOOJ6xczbqGeBvn7RMUb3o83qngjoKcOhjqfEyjvRpDVo4gVIoDX
YT2jh9iLrn0DLGbaIpVCCo6VWkwm3WbD4DJaZF5HELdUnHyiVP5YTXZx9C/pHtAtwC99YiW73jAG
ZdGLs/82VshbKM0vAUG02rc7w29cCTBRLMMZcEwLJKhwgo7434jREBAOYSst1NVH8CSJr1ENnnNj
Np5L1cnZT2fLOAibpcoRogwbqnMrXvIjYPKz3U3pMxtd+1c67Zot1U/ufzsj0RZEBoyrCqHi+Tme
cjaujlK4F17w38evpD4kjdp9e2OTkv/EgmBw1DlDjFet047MdAZaSX0ifVBA/8upv6XtQdG1aCg/
QQiluFzlK/QoxTQbQYHvbwwaVejWqpCCdIUomEbiuOM1tj8BNOFMsR+dnlaPB27VIs2ljIVZWHmj
aQ/Pi/+8Kmg5UHMA1DYKIvE/6LCRLNRJWVZMV71RubOYE1HbugO9ikJJ0tFeT49szBpMLgGGmWyL
RrGZegPwQUuh046VchDjDS42IZn7xNBx38F+d+fgO6DyKpa/H8Be7fyPt1evFZRkxpWG73BgzCyR
MTGcOs+XlzAhTQDW0A8SNBh8e7uYCH+vTuNykq6wFHOZTz7RM9bSn/hf0nwCCDC7SEU1qW9SVs1B
cWK9fSHphtR8J0ywty0f7B10b5RZ/2nZZJ+S/6fooU7PKm2F4Zz563rL0c46RKK8JlzPSkNMQFtj
ep4m5ZCj2TnwXgB9NtXebTXj+9Z5Hip7lVsAZMkLC30NhV7altsKpRdGClRlmsOmlGXqPsJpjGSK
oLgWYhNbpWyk53CEpmAQS71dmyVefwNQ1/q/U2ceAm3xBleDPRVcGIXCtoxRv3y42fgOSjumEmK2
FgfbAv8BvqFmkq4kSzIG7CP/FnyC7iJzdHusvFHZhx63MVIhxPe/GqpX5u7XrzIcqY4G9ocGQZEI
Jqn7JkhcocQWYvN+fxoRBDA4kXo6FKhBrfhmlAGE96/P5uF7vG+kF5w3tYBCcnkH3ZkhX28f0WTw
j07QrHVP1J/sJo21rSWKdqTCGSg1TYa27A+FRPTRnK2LaTIGjrh/QaFrK4joucUkz5aydqzhMuSN
UNROgrhjjIm59hLD7tX5rEkO7MB3CFri89Ipfc/n6rgumB4f4SSJd7Kx4KNBZmj4QsAxbeVGtJUg
tD07PMVkf1akDUrznqpVe5tolLYVsDqMItQqw6/Xb5qG4T6i/KMgoygpxGyBgBnjIDuJBqrN4ovL
Qq14GRZLVzvyd3Co9wA0qo33ATgAFh29rsUgGxU9ADLule1NDos1Zim3bI7aEbBaC8VuDlqWp6Mc
2R42Jk/x0Ec1XGUHwMvmiUx21UYUCGS6aJUa1UN+1ITOL0swLNAKhiXsReBdrcoXrp+896VCrKXj
IB7vfpI+jP0/TG82hG6nWLMcB9NAaDgTyWv2fAYbHM0RwKbombYv0CxVPlI1GLjQcKGwmeji4Vzd
t79xoT7w+FESS2lGXDMvwNEwrtvjD4sD/KK+uIOmplJhKOJzQqb3Ooiki9UY10K+T9YS5ataw4u/
FCpLVi/2xmzs2ivPdlDoVns/yXAzzTwZdG0MwuHABKGjiLUyar6i3Bg5ozig6OlcLIX5G4t1DkJu
T4AbvrbnnVhe5uo3TZRmYMqL81MkMxVF4E5em7cy1TC2tW2ucVTtDh1BdDCo3ZUZmzPXYIteAASk
QI2Cb/6ms+uNUcOObd803yGGlfOwjUovOFFIUHbra4CJ/HwNEcRCglfulMjIKfePoGv4pICbW3Ug
SvLKtgyTmA/U6wzJEGggkd+qLwjuxT44SMaCcHwqiuVbWJAB9oH2Vx2HRV7ZVG18rkD95f/OB2t8
vR8pcx/7VK/u/xKfmYYgxg9reyG4lb9AcWGzDR3nl8l7VifC7b57ty/UZW1hag1leDt5UXKzEd43
4l6ckQB2LvO7+ApczbHHxEZgvVMejn0clIFNpOg176O1gPdEVAFkPLa0CneD5ileqFSDf/pKHMMo
+LhbrL6cnd/zl/qt++C1gTwFs8mVJ0UfjOilMUK8TG0tNBoyBSb8lwR83/yebuNROVyWVFMd3uhP
TU/D9iDWs+3u5BPrP9LX+8YREOEaX3W1pQ96CdPiNF/j0edSz482FKuN/o+/y2+lk+XnTG6U0reQ
EUVhxH5YqDdLLABR7GKfcGcWm3z1b57OG+EdsqU3LwKfjbXuzlntAAv1/ShJXUIHHaaSjsluUuw6
DnjwR7q+3iLUyt3miL4zJzOcHGF+mYGEKUE60wdvDBxk2W/Z/oUtD8lV4+QaXWhtFOp43Gv6tpJX
2M7FgasbPLgEgV5Rr+LJulGomDnFVpjDi2PWNdyifROZsd9pulSdvv+K6KM/sIYouza8simPsZ4P
Fmuk27xxpRonBOTI/8+xRcv0blWnMqSutc8UcKlwZIsS8tPGIcj/I4iLMLGeoJ6Ra5NSXrrzBTsN
1H5iZKV93oLERfgFlBWHbvgfl8Ebhttm2TP/7y0qIob7hc5HqdwrB9pKUYK0vKTkng4fzUsXLss2
jtPycKu+De6ZfqrklWSLeyUbyawCj8fS0iETjBkVbMBpre2lnx/bkRU3og7Himm2r4ety3tNINRl
MAflLBSC1AQ9I5CNNO+G3wjNtsWKvzkGFt7uy4EC3ihWxCa/RnFTuYhA3N5jKKRvQOXmA06KPzCb
jjna1W20pjVXC/JQBZZBmhUDMWJH6mIDHjd1xwiYGFbjzY//8ytcGNwVP/Cpg+9bSRwnfukt8LAM
ypzgVPLy60lyu8Ajdpeu5M7iNwW8h1DJUfzYwvKmirV9/T/kF8sl7ThlL2JoMIG1hNNXjyh+MBuH
K6Yvk1OGbUAayA5n6nY057l7eWAsGgQMA07WFTzWAD3CQnwIWJ3cABbiEdgLfblC1bzTTwAjXGjh
OLMB67tZCPfvXOM9c614dQwt4Y2IPtaUAEt+rKH26MmCGjeA4NNU/2WxoKOHkdo78ZtmE0VMcNuV
ayAtkzK+ptmg+EmzTBtXvIMUnEgmUgOLy5noGw9INgwZm24Jsds4p526doOGm5+TzSVb6EXUmaZu
iAiXJ/uTWCN3r4rEO5u/Uc8cwX+YahNFIFs+GjD3bFtq85gsL98eP3Z3wdbs/kN7Lhwv+95TYsv3
NtbA1b7bo65O4/WypmEFwZlQ0qEYuGEdZad9YejHvOScyuzuPax/DqK/ebs66WQtuweaIa8QoIdE
FLQtembxLzUpdQlkQ2kKv/os/a/V07p7uZoKqxZJp2BQLdk+0irNXzk6BCEwZRCk3+T/tH38RETF
0fEF89llk+Q5mtM8jWpmezUIhPvQAWtC0d2Km+dirhkLzUsvFlmNpOk5zaOMhVSs1H6Wne6aQMJU
HJsCTN6bN7u6wDpO8oWH9LpDnCO7/XQ5wrNa4GfX7JUxwhggvtRJKoVirLCcA5Vqa9IBEUQPxsZm
0mCic9QZv/r0Aq8b9q7ukWPVQruZQkum6AZa+dW9y5FVHEI+92iFgk4vYQHmjem8fMkWPVgZX+HB
PrAJArd0ZmSwmMtfqmLOZ9Tz9KRobh1JaWOcywvEk0h+GNO9awj+88pxl9xQUVWzqoAf6t1Tf8bw
8P07bsHFujqoA6d9HmVisq3haRQosg+Cx5BjWwehYAF4dbB4324I9NcxRNvnX+AgTROmZ1ub1s3A
tw7hvyPG4pFc8rtJF4Qh6aPEMScmwgtC01bwgx6lDCmildo9harWpSN+boQ2xVqaPMXrhi/APFLE
A7T5GvjlSM6+SE51X01BXs+KnvzsboTcSce464WPi5xQPpFNcmudmr72I+w6KovTHZHSL1Wa48PM
1T1vxXJH4v2DH9AGqb62PezKMC15bFsH2BEehYAqUcT4zKDeBBKICkhFkQUMPSvkYku3FlyRzyPU
Odj1LWh4R1V6J8E+4m3/YoG78g1xiArieIvPWl9Gk9eEmxrfgvOEt4hObLS72EEh9ol2OzlMc3yl
Xbve6YsYfVR+1YoOv7DJ/3Lj+iqRhs5Xcwn/QJZ8rerMGrsfro8ShMGfaSGBUyK8kxqXEuD1VgYl
nrnpbBtgUFz/MRodQ4GQ7f7p9fpboL7g1MIIGZNZHoS12UX5+z5jbVbfr+wvsao9N2SUy7TpgClH
QAkchm/vOGElKXmzqWkg4eMCebRPi4LS060CDU9H8O53sUkzL9BtV2+CwHlIfIbvJ0V9mQ6Vmzn0
veCu88nJ43dBR7qvtWS1ho4eHda3YGVtEB9V3HP77nZddG9QLTNfBvDn8Wigi/I2/n7ixhfKQYmP
sga9mK9rVmJ1UL7M5ZSJrCSAujUak+cdNEnlkxn1NvZGoHX9QDKBZmC0KBW0un0wg/7gNMX3iIkr
nMVchWGJDAZq0faHWQ+nEIDR01NpCjdmdLKHwx1/Jvv3Py5J2h+m/uTipQbaWNXvHGIte3jZm5z6
b/r62GIGupS5Ih7K0qmSd7vuhYs2XOKLhBLcY9X6gBu31iufhF7fg8BPOG+NPSrCUxvakzfe+rZa
zhuQ6STLUZ2oIIlIllZ9LgPFdXpXTzEYWT7xpGxoAW9B5PSr/kiju6e4MyqlzFKNCzBrE5LGsU/P
YJyrCJlJ1XhC9jaTydZzKIaq0LoDP80VSVTzWS9F27m+BVcwZgs69v4SUGklK+I5ito0Y9DBURAk
P2DvcTH89JBIVRnR2u1AgPDfqHJi4y4TmGKi+jPifLU9LJ2tBr+/jecx9EwG3Mo/pMIuk/JtlZOp
K0+5Fg3Fa7midHJKRxTMCRxnOpea+P+0GjnOzUo7TrJPAmA5/KTyipFnE0xJYZ4+ZsApVgZ6NeBh
gRY1SLwKzLcR7fVkWcT1uHwNjRFKTIH5EXH8d1lfm6DH33xF6tamIVjQ78n0ZtsGWzIa+rnLt/73
w/YjYcNDGPCztt68u8GIQQVJslQiulrF6drlXS+sro+5Q8lEJt2EDw0IONEf+IQKWfiIShnKBlYs
IAsCriElngVZF+XsokMi/l65IPc1ZQj8QgjzDeN9gc1OPj21Ir9JLzEj/3ylRTjMfSLam4PM7Fn9
W1A4asWBB49O6Ku5z81m5zjvOUkPPQniATie6N6xjZI0qrrWBTWYsyJFhhehOJlsuVIiBb+V5Dqs
fpJiVIys6hxWo9qpytWFsVq2ySIhXtEZD5cmzghDS/qjcJP9Dxv2rJM6idto5K08ehx9vZoDD9J4
aSSRNJ5QYzu6gN54O0knKnVGiZ1DpITrNa64c5Jo1NnHw/keuYsb11/cPxtzAE9UUsG6JIuzN8Y7
MpuXaruegckRjlw+oK4SAT9FZaGje0KNqJNhEFCGLs8wC7urLZ/xRATFo40FpdIDBWPMlVE83bBQ
ssQjsln7uL/WOMmT4+CTbEyRDGGRAJSytF9IBrbPD7dYUaDYPwAnTgV6+875FfHJKDXLSpNNmkrc
vtyls/Y8oGrz3hLj8Moa39n5mvOOr5rEOxvGxIiEBMLolY3j+n9iu9AvnCkHUsfymtKKHuBCr3nV
LBKDTYOdfE/eKmHRgqLWyzzZx0wIT30OerQMMW0Sj59Jc3+nZXsEWvazO+bDNlncSs3uy4ws4WhW
lGOGyFRySxTRB9q38v2eU4bKyB4U6zJGVCUkZtM3LHWFLXTL+oanG8cYjWT3vldgn7ra+7exKpTO
BHTepz794+tLnaXf3W7atZ23JITVC5XWMxdGrQIP+JdW36oHesVVJivnU7XDAhmObcoGo8T3B6b7
ujEOGaXKpQYa3DA/uPVhWr5uhsCuQgEPDp5IeXLpPBZW/CCoert62G/30GlOQbhi6CEoxHXGSsUj
6FiAAQdK2fAgZszEf1J4ZkzC71LK2ue1rLyp8aj3soH2nXgyGxn3kVL7lT7NlFN/HgT8SuhWjy1e
WCybEd5j839OcreMuQFBX0KTsIewEpHsSMO1MgLiejXEQXHeRvo817hYW65ZUIqmVb2HwE9FvhES
s6DiUm2PLlIsjNQOC4vZN3NNd36hhLKwa7r0SIUlH2KRgLOXSZ6Bq3qV2p2TKkgQ9C6zgb5yXkZn
OUN9KEDj3Ce3pkf++kFOYzEs9drCmdLeJUkVfSidT86BpkIbNPZ5fThVirNE5Fmmj4eRCCwGvG3S
klvZDepLU4mLWgNUjqSDo8880OcVf50O0U4+GN7vhg5ybbAkgiHVwqcWCU/l0sGvzJcQrFNBH7a2
Q9NT13Fpw7XrhkMDR4C1nDaBPnO4mWw0OLzBwGOS3LtqnGfUDDcHj2Xvw2E5PW0hy6L73Y6w7gV9
fgIPb/m4nvu57aoQyGES4TQsJv6vLQGDGFibXvgKfJUBjO/F4Gqh0/Y5Uo52uWFcqH8pDBaJtJcg
EfA7VBBfD3BAIXeeqc4bGntpOSkMBxrqh/+gQtpDlPZXvcWeHJFrVERUUd6QX2A1oIf5m7+za3l3
n+iLQKF3WSDPh7iG7Vr6U3LxOXNFFD9N8l22IMxVuGSI4jiOvkFV88vW0j5gfXYQIe12aG1U01U1
1i5baZcPpKruRFuLCkowI4/y8hivhxplUhyE9pKnXtBZMhWVUu9s/HX6ZKD1KuBDX8dJQ6wcWuDP
9vHSwhdLgXAl6sbPjqKDyCMEni6DqWjWbJ6A8U/F+U6dzjNp1kSaDaakTjxLZLz2axqjkD+kK53h
oQy25z8e1DYOEK+L50/G8TZ9xENhrzvSiwEBocNrdKOYnmBWV5wyIHtw3me9Rqz4wjLPwi5ezCz3
9LeSVJQuz0veTPPH0OsbCHS/GD8qdXRRvS1zmgG7hyiHIM2Y0tAzRtd79LGxaReIY4BXByq873IN
BVjBBbAMrE7vQ17Vo5/Q7ZBY87BgA80NwwEwxzBcX4j2JDZj7F8JXBps4MnYd/FVnhHhKnor8EX/
uzTiL+dBhTYw7hF8Gc+NbErZQte1fO2oS8/eBpDmksOHJD4cJYZ/F3lU3eJY68v1Sczj3sgsqnFM
SN5k8P27yLkiCUcj7LrahLcHftvlIvSChNS0KKhkYR6BwLra4CqniocDCYO7Yw6LDWRX4Td/rfkE
3QCDyvka4VDyRwe5xXIWK0D4GN3WP+xbOxVHtNygqfAsOIW0p/i9KrWsd0F5kVNom1GeuACYTzbi
r7TU9LnCHyUctNW32U1kDL0bBRFV+m44xJ66gB+0BnGB1W8mXpu6T/TOpOyUbUp0bcIHu7Nev+zf
vYxQ87ucdIjl7nfpDea6xV4HYamejIhMNwGyifyoL+kukJcn/Lb0FPF5SX2MHhIhPydKfkQdzLFr
Ei0vLxSOhIODN20KBnZGsp2yeUrqgF2OTY7Tb01A/J+4KuwR4tOVWhAvXy9Fs4YbJWeByCvy06zY
wxBhuunaE9ufI73ImT2BLT9ZaAKOMQbArIEIbFbYFwD7fRO9e8Llp85ASKTDz9kF2G2nQ1JRR8Ts
5QDcbw2+30adcjGfRh4vGnAk+Cd/vfwcpC0LhvmyS7ie7mZdwD3pXMbLcT/+F1y6a/3wpVQiHNUD
8+hE/s0Mr861+7jsNgaiweYWvHf5MsTByLTRSMi4QTRrtrGBRKLRx+pB9PQvO6/lEiiSlj+/oP7t
WngUMy0MH/KqKabztcBY9vYJmGOIQzKrvIoqDqILE0sLjMLCIVK7MfosCMxE7mj36IgRJh4Xyiz2
a+Z+aTQmZqtA6CyosxwAeOwl8byFCttkDPYooabpWqM8k9QDnlf4diARV6NKs10mz9/DgzRhiypz
NK1iPYrWrCcDjDJYpoRZys4zqJOFUqbjTpq5ZylJqUTqf9Yp5Q3v0EtC61GSmzGOcMM0oERpHvI6
MSsMgbDPD8BJPWiZsFjnD2mgLOykChT0a9cncJx+I0zKN74lMMNT3KKOBpyz5Pfpmlvtsb9cyAea
gvJ0z4JgT00PCjtToSDmjG3UsieSOAKbojhHhJZqyXKiJCUk9Q2cHtDU0nzW/cBYT/rnPwHQLbnZ
jB19kUBIxyCToasq8hwvhR0b4KGcSrVjp6tzN9acoHCzDvki9Zhk8jlxc6gf3SMEuC1oivIUtbxP
AsdbucfZ1NRoQ2RX7CvN2zfBw+bTsoe95I6NO1scGxD6y0GyfftGy8sSsZNuBD1hw1JCYdM6QSAl
97vPeyaFukP/B1Q0rg+gG8QtY+pGy8cIXAbVzcsZJhIBTNRlA54lT+0kLom6YgAAMt4z2cq8FfkR
esC2t5C8FQ+eGtEHeU6Q2hKvKY6PLTy0PyrlLbQjpP7L5DWfKwf4vE2NfU69C47sFd2P013asPjw
I6tmS23fQLKtuVwWPRd8FRuwKfShpwiVhQPkwzNsW+HRaDcbSFXt4DCfTSmBVqXmJQmvGPMVG1ZI
NN0YERYr33IIERM7RyVgDAbKgt5sTRpg5oer30AXALdMr28qUZWspdp8dzcBdYwKBUMa2d7oyA7m
BKXXw1pM279CO+hMxA2/wX349IGaVER2vhTrL5uaXDFLLmOzwdbzorb6HAk/i3BcFt8zlA3sj8Y9
1NKES7qd8n22C/ol8feWXo7eyMy9AoI41Aq8h+fQSgKYWcvcE+YQfwfxH//g4CiV8rmKy3kGaqr7
u9JEFygYA77vyrsnTgTWg0RF4/bXLKNdBg6cbTWZVaLMn+klCA0DlnmXAB1Bls3jMfBPF514P4gX
d4QN82f8HSCElploJjQ6ou9ZiQfA45GkmBndoH0t6jLAvlr83xN593rk1hYbbIACOimvkIRoLzSd
LODBxN3QpXr0iCQaduDCiHRF0MHHhNxg80RemRfEkKfs+x5YhH3YAgJkGKFPAX1X9MVgPEDnAATc
NIzwJKkdTUC54PqKKHmNBq07Mm0kNXCWl5DwHCaNb5Z+hiVgtlZ/JMGfpE/e7Jy46AhsSGGG+/nd
8zatPajUl1PVORzQelhyck7vliMTL3vn6HfQ6UJAxJSrB8AiO6bAFN6DGEnEYkJok+8YL+d8N9lE
2vvpqRfmmJP1yKTqY1Gtx4O3E7NA9fI2a4LeHvKOqd65Bhj+GeGDnBP9ukNvdc69oHTirTWDvovX
YbhbytT7ewGd8HH2FJ8sW3J0Bnr/9bsrwLnGj3WWz7bgr/7GWlxO7cBB+/sq/1O6vFh8mozIG7LF
RNMCueQDwzD4V3U9ixTMg0/87+HN/N1tn8EgYClMmiFH5EYU8OKiwf6xrpAcVEuVIZLYAkBTNZnF
v40zcTQLDflqtWYrgn+9zkukpN3ljV5Ob/lNt9kN3v6CkP/2T51uRK0/3wS4U+FdqugN3sokLsBp
W2Sam36Z/5cRMXqylxVu7aTQJkWZcTomP87ah75OARRicg5wRIkBIIc2SNHsTvGr0OvAlDfwwOHW
xRnipoCykH4/xfafyugJTLskmdt3SyhoCyuuRwsQvZoQ7C6kmYsI+vQLFF+dX9lCGFKl2Ff7j/Fo
HBpJZvZETrLq8qLgkEiHEyyaAy5rdSEfIHn7slhfNB3exOJ4kLeoasAFCizvk8unfA1dRmgl9LJS
/yaN48kTYaijJdlJDDG6ekynVyQv9Cxdgdaj1UbYWMLHmZrU6eyyvVxr2/LcyWD75pQrYpuEvvJv
7a2hosbSuVqYd6Sq9lwyqRCUFdGbXbBArNdiWCik4W7RTCvNUmzVgGuJzd3nkEtd4vP60Iy/hn40
76Gq9ljY/PjJiCGUxyehzqVzlu0o+Pl6OPQdz7OzOj2s0MasbT3wWTG0VotNuDLi/n5CDHwEIzFQ
mVHRvsqMkMh64/M7SbvJqJ2Ia7yT9mHtxdXXIbDtWDUQH9raUvnzRLYBXF75YKGJ9JJYyoQUi86N
9Lj6UAv09fuMVRUd5FjJhoRfotKlrWjM242VIx4pbjRugJe9JLfICPgHHFo65wpPgPrQGP45NhiZ
/e1tinDcof4S4by6XkHKijzicCBueT5MljpwBvAhhvWPjc2OuwIc+mnIXaVQo3oS1xhz9eIztIvv
yiRp1sBRoqt8aN2IaTQxgg9HBKHDlv9nXgz08tO1IREysj+6W1WyLEoU0HtDJ2XLeqDVpLexjlhU
pG3Z9fGJeG41np3y6/jKX/II8WDMlB/59UjesgJ5O+5mxGb2owHmsBCu0eB/1d0oq5QK27XlY+6Y
uzMnuRNMDRbLyUVsu0ipnFbnmCCo5tuowZI4oxZrDGOOqa4aibxPEuaVFZcObosr6bzGfDr+PEcC
Sa+wPdXdd2+Tk8Ok2ELQB/AOvIkGTQzEXs6tgF5T/j+8UoCG85Rw2jZiWp8mEZC/SXm5eTkWTx5L
vJ0MT9mdPwLgirNLbIh8RUzGT/6OQFmN6/Y1CqGvyZukj7Pihw4F/PZnwAesw9wLNJD3faG8GHx3
NeL+DE0SOBLOTsqSq/7ilQ86zeQhJa9rwzYeGn+IfAs4GzAeC52oUdgbkJUOT9bcW/7OlADHuNiU
kxg9kgMwMvNjIUjTZedkxnzbRQfAt/PgpyeJAsC1p0C5eIAgYD/Zcs0YlKwcY2n0ZFaertziofTh
L60ERAJg3bNX+g+CZuqLaPlzNCJesQiZL0QDBrxjwC2xE6SHefq4MjlommTfLUpeOQrQ7MukUpKx
/t4LvnDhxVH3bZcl98LQrPwvyBsiHUd1EMtVIfwbul4vWqPJVqdVEsaxnL+uloDvo9vV5KZh30eG
KDQ8kep1l26Xj23NASFBxLEDbpyPoNBPdXtJhn1/1T2y+nIFAIjExkLuIzSaS8FoZa+JTk/G+Qt0
TLN94rVBDI6yiPbPK8ESijv16A8+k1jrNhcLGxflWYxmEm3CU929jrVJDj5kCMi0T1ctalzoWctP
2+wzDwTQTGn/P6Zuymn5l56J3W2ouE5gyBujJcMAe7Ot9+gRayz3nGRtqFo9lLFMNANiEOs9y4Ai
aFumtT/VH2EJBvucfi1U0wKKduXqiqbhYUKwICMTn1ywjCZ93NnXqc3a/xAIy4XpXVq/tSxYQy9L
pRRwAfs4F8T/TNJ584XRmjKZDazvspPJCIeGYxU3IOwZZ7MZ5MxDSucU6PKRFzqpvl33XzLBqbq8
1LkN9ld1zoYQQ0f5J3iIV3TK92QgyQm8uzKFRO4fRF3okK3a8y/3RQ9fQ883BWw9/ZW2dkPL3AbG
zoahZQLaJNnqIqQgDcCJRQXQpjNrhLvpFxCp7qB3cAi7kjcATZzgg85xaPGG5Swdwv9c4w27bVsf
5JDWORov2J1/aS/JByLtAqJtpG3fvaJUkGpH1lD4oht0ON2GanJ4+N+6wL4PiZ+3rgIlrYr5P97u
URq9zAEhyV8Idlj+l56eRx5f8fZqtFnQv1iukze2yX1Bl/FjHvobFMnbeng87Fyc0rkIUSnh+QMw
I6MNpyRFA3YUcBkUC2DZG8PYhvukVxTnfTXE1qWKBzqqzVaMEdx59aPEeQgaTu8mUYPRQARw7p5A
k+mca+EGjRnKYXCf+tyKdo9LeLcG8d5dr37xRpQ3jhayliRGoyO078RWRhyhepamfosAZSFmShmj
Y1nGfStK6Kk4H+Y7kvMWSHzK75oNQirHu52S7uXZhr7ByDnnd7ed3G6RASV/ZhROwYwOvFM7y+P/
Wc08ogWz1NCy0b3Z3suOy0JEfza8uOcFEmahOJckuvMnIKIJyRdMPuivNO9y7a3fSJGvGVTczOnH
u+fYhe7/3g866xVz9iztbPxscYy2FuhsQGvdu1SLSm9e/DNr7fNaJnEA5/1HFyTQQJBsEvAaBfiC
v7WQ9NHbrqcs0QbvYkD87oleEmjiSYcB64K/KhAs2QgE686B/h/OVVeo4O4wW1XCoZ9NVW/AxfHj
1gCESPYZxtq7jarqn4V8oi7nAonqHXnwNaHYrX58hpqD+x6Q+zTHroPwfThzm12yJS0VqKa/5dL4
d4y6l7+H7RkxMJDShZXE52LRcTKckZdhOtJNI2npPZvYk2I4uHgJ6RWQKIXpnfJr7Ynxp93c0YGH
skyi+x/fuKMnukQ0EdH79Y32cuSkV36t2mPV2gcKGD7o/DbfvO5iFtrK9aSiCJbmg6Kd8pDE1a7L
6dnWW0uhsi2w/f0RFDWAvS/o2J2M9/1QjLY9sCLo5lxI4Q3uSM4yDIm74B/o3qAjjdZfssNS0RPo
JbwTlpzNPUDiaHGTkHjDJpffakneBVEvYq6eCvgMwBgstUP+laMuFpTFXp1xjlEJEeGMqcXsIuS/
S1K6c65ldY3f4GdxoxtlhcyB9OPsn/7FcB7NJCGulIaBvRXiqeDmCLqV8p1dNVzu2HN7g0cCaeRP
x0pyepomIRGuFEqfEEPLlRjkLDIEi62CzPixOkJpiorzvFievcv45Y4zZoedaFBwbGlgb1GncriC
eg1OrFJhY1pqfTSU/rZRSS52z05KzlvXHx2HOU3nzsFeeLR2tSPkz+qyf4mpY4zQKEqAmb3y0ynP
XdsOI6RAao+nYNImC6kJMXScGFx8WpXeOzuufOo2vGUUq0aUXRIXpgljs+hL6IOTDeZFV3TUPui6
GXlwBV/3oAMPwgRghUt5u7iDnUsMOJ/JbJvLJrRVbTrjwOdlO3I1xzKaDGGc60n+G1+p+A43plKG
cCDySOOsEOlBsS0R1yTAsAvNMhkGOSXEhp06KTh0CDOYRVbUiLWo75QJOLIInX6eNssli9YoB5zF
ixkJ1ayYDkMZ66qHZG98ShdTJpVXUMITWTgvqzJgGN8HvVlPkfBskSSABO2+Sr6AHOa5tHZ/6wyq
dAiMS76WKn7TlYNAsKCf7vImJYjNzvyCOuPIvJ+1mqbBd8TA0TY/QK9UUV2IPMR3D4wpAKEcql1J
4+3+zI4aHaBewOPS7k19RhPPMRlMrGVdWh3J+qMp9OozN0+2jr1tMjMKM7OvK5jrDnOVpBeKM8qA
D2R+Dnz+VEG3wHOoYIRme5aqKSv+UL7qwZSkFkVcZ7dWo1YHwC2QDJyHLNbuK2O+2qhFk5lAAoSk
zIGO+/WYTgpbjDIdwwd+ZrKRnfmZ7u2MYBo5/psmXXaIh8rxAlg98v+IloeovtlY5UX22vO8rzvT
VRVDzXsQtQSoAjAed3ZHZWpoibCa/6o4kb/5dexjDG2Kq4peUmC/4JYZXBxxVny2+HcpeI3Nc4ZJ
w2NUK6g+EbVfHGsb/traBSxS/z+xgI3YLBxfms2eyCMGdrTbzfWRiefmMwdZeJ8Wm7kTSfASbseg
33lRzZptLDBMWFqvTDhuB043kl9oXTDQEmC3GAnOCl5iO3Vv0L8vBs7B6rJf9E1IxCadZlav5T5s
1aCuPLx3JqJ4xsyyP4i8vSBUV2mXTXJLG9lge6+7Nm/6Z3kgGfDygNRnCKjb9xorBmdCeIZ/TcCk
GDVedTEMXOfMNsEFcP6fOZCoA9ielwTRRgSai7fIwF5/u5M/1sfDwfJVa4fsaBEka7c7G51NzU+X
SptqCNtYX3m21USx9uxfIybFhRqtAxKtJDxzJTf3t+nxJjqtW4wSbewkD3J6FPtwgQcV716JIhCW
fIq3Xdc7+VnYFuzLP7rKFSjEZHYfXmQrQ7Vf6zX5pPlWqzR0X9IF8vRhnlPfNPHd0pSc8bue/7bC
zexDpxWANT1wfckXPzTmdLcMgopnChrLf2KdCvZ39o8+d2NuIfnNPbfJM2VlLV2KlYidN17z8f2B
sPI+MrEb/j786Smh0y8OLxfJddVAGRXMBzKm16O626zFaI+7ZUdvFsiDU6h0ANoOzUCnG8W1QZC3
73phwTRSDZiOvem5CD7tZXi3JdYaClFHKukP8qiDgGeFREye6kLzj7oImd4Qju98NvFLuWVLcuZ6
nntYxT0vgDhbCPeiXFWsiI3qnGcP0iG4Lg0serzJe1oitox86tOEwvb9QXuOMmoCy+wm0HjBoWqs
bJV8wJzjdNBZuEt8D+69cd4vojKPT56qlurgsFRZI1ckoo0I/3D/BcOhm/XISIJ1vXXqrg0VlvfM
+yTQe/0BdHgdcxoll9A0MRYq2WIpftdqzMHYL8n2ZnZqEB6Ud7544i3uxt7spKw8A2DK1mmCy7Kt
t1rJmxtUUZFm8kHi4kWCzRukc+C0j1wPMpGCr2KQOvylLRIZLts6mzC86hA1cfAMaaW+cSWvGpW4
prCzTC3ZUl3fQqZEKau0n41BxHC1Wx185LP9ehU1Ws/3YbArb9TLkQz7AcTfn3NI8o+nW/AoVhvV
LewqPYjaxWVkHCyz3Hm1oXFZ0hT4IqmXjbF7KN5kslnGgS7GdL5gi7BakM6jfIBvHtfa+pUYOZ0b
VvgA2fi5bps2PpU3GzlLvzOgZf9jaTu1YIzs534ckUfM9CNnnnH1IVWey16dceWI8eyZaWPILc46
k+YL9oqWNftSUlsv5bjevIsDv7hiwmHYpdbkCh2koCnmV7SHku/CMjlFTesyqWb/s//Ev//1bhde
iu0YGYlQHokYAK5XWQ4Bet/PfybT1AORzwpnAuPLldKV3r46KbXW3d/6Z4P9rkTl19jupkP1XXkN
qkh9VJFjY6LQYfAzHxtEQ4X9SZW5iyYb4lbWq9c1zTxthhxu433NTrlgNLaUj50Jg3P39PDhVGwH
IwK1YtQmAxM5gGbKEzoHjaJqpjU2lbyuNC+8IqEYOxt0xlB5TU9Mqbv0R125uYTL4H8q8YP2aZmB
xUkWkYjWHEsPHQRYSEnVGFzZBe+3dOPPV1bY2WKcGVNKq3IdvXPs2MNExicnSPFXLh3R3gOmXCSn
WEdOtOS6wnOyaReFVz3h6/BBl2R5lS8ewpRZc52sSfPkd9c8lox1MPptVidTcOb8vs9ET5KSraGh
OI+ZXJ55YNL166a9jh5NrFa0wzNU4Bh8LcXFDnFJzBTn1DK29u9+swiYY3yaCymJtyLsh0jWw5eS
Y3QxBNzyoW7HOJcwEuUdHBzGm2oTmh0pObI25f6ZXc7utV/5D9vJhhnEuOHt+UfNY2oB84nujtJ6
GcNiryWhh/jJEojwQruyXoOYjb3SF2cFfyfog0G4xnUdPxqYS+xLUZRxu4/KdGPrUjCM8gY36qRG
dBN1neky7nHfW03m2059VY26A05KfMjeMlGNXoZG7anXYoOX8G6FKmmfscp76N7l8sawslLZ80X3
j6sL6l1x2v2M0k3CbLsdWRpoW26GuA97ol7dw5om+12xNzXzybQLeyHDJd4OERLO8PQLmQHV1INf
DlJRSAL3gxloJvLxCpRNY8zx57rCGtbvxASoBZfkBS1MGBcNXqbfoTKyJYEgZOatLmJ/z/wLW73k
nYgF3qRrv48gJg4EpDmbGd4ubn2zFScREJEfr+Qrxc6KXP8rzAFKcMPSjzgtmr/zS0o8bEarwx5J
G0L64MODcN6tCUKxrtKOdVZvxaG67OtSzx537XhHXLHlEdd4W+DKwxkvE1Sv5ftuf/r0cIG36BkR
AqEiaTRrSsSXh10JRJ+vDRukFR52iwYSe7oM93ue2X/ZiCwGKGtJjghh1cOfV0puIS/IFh9R6fos
eaGIACX4iwcuZoVrOH5vp6jEHjA5QJU+09PNvY6LgcSF6prS+6KPndGXznte9fUVdyZPnRQ0eIKz
nnvDhBNNCC8f8rkpyUPBF9QnOQw8j4Oz3PT1APUME+MrY6dk7EEYUKEEwzFNATtRWfveG/a1/NNt
VHQ8UBwgZFJhehl4UlXB5xw883SvvITne17rHzg2rrbKkFDfRkWnZs7n8pm5mPTaC3IyxL5Q4sNW
o22V8mNMMkCKdbjo9HYbZX8kKDtyiVEKofBpG8m4UWhr3vnk2rBjajEb5MqYzVKmVmiIDyAKuSJg
uaFwq2zFXAawr7rBnnNa7KfmyDUsaTnvmId0G6ntTWBBMWWqT+Y+m/SjD00OyuTdIsE8RzkxVz1y
XnQuf5ymq2PGJOBfMhT7rKuQgYJrdH3MzjkmH8C/K/KebgcLq4q0FM4p3kPL0BNetrr7jm4l0f2K
e34WnwkcL8gcKd+GwNFTTjkZc2WCYj9Xb0G6G6GOk6OGZ8HwERPp4QOGo3jqR/+u0TSHOelPrkmc
RaMP91qNvZh2MS9LLA7YSFFnESem7Pa/D2IM5tAoP8Ogh6pl0U02dThsh9UWM/8sdSqD9aV9QMvU
BSKlKIZ1EP3I4Pf77XeNcPPywWkJA45Bigr0Dn/Y7S0HQAfwpHNfdzG5jIfHzQ9sWhems4TWD58i
cXnEl4xDjWhMGHC/ICuar3eXx/pv61d3gDYeneFXg8DOnDUqtinNs0F7fMXFyoEMNil3X3Pwf9W4
rhRU0UImyTnVfpuCcIEmgxkS/7+rReSCCk6jTfofMowdQp0qFE8iOrxe6+kevMQB6YHdnnIc82ys
A4B7KLLBlboqfHiv6GIxq5u3Yuzw6AJOTQnpdaejwVgxPLoR114eFquSzReDsFAohOg0fc6Ahyvs
7Lsxofld1G0nFgH87E6v9dfaZkyQsKmLRQATSjzGqKSp4ubELjR1PUVtrniLnmPrxhwvMVEsYR4Y
65VAXHw513S+1cVH+IPdYKinCTxr63NSVGMBYjLin38791FM35kOQRU6gEQicD9hp1vJaH5m/Q1B
zQd+kLuGk+f+9IFFfuzj4W+5/aOdoFhkiKXc2Iw/WYEt4MAxz2Nr0HJf2L5ekh0PpLfot5gyDII9
VyEPJ437LT7qQIHR7XgAVoKmrGesV7zHXqJwog1W+Dv5MzNV/hZEMeQEk7wstCm2+B8Sj5Khri8X
5TsFKH0ApJM32dJ33Q/LEaDTXR2JECxmIinNepWN1XFKgru3NGqaSspoCyv4cOFY5ROL/itnwj0a
z93S2RSyEmINxcolETgoZ7IHkVUYqtnkrWHrcx3fE/2//YBVeht2cFSCB73uhCO+eYgwOygZdkgl
6d8+xCYqCRKIgNy6lGdjskICy9ES5HgBizEFE4pvxEW4JsTF42BjMA7RHYXBWbE6vAR4Un57nI7t
7TG5/+yNyps8brqnSxF8wyU/jnwpPjrF/gRZOqdr+mCytz8O68bCJYU+06P1vO1IobcvsWuY+HQg
/bQ4omAZ1q7wJkIflKpBnPVLHTCxkcbJIdLT+CG8wTh9ZVYLiUFTNKfnbUdRwlMzDiLvYzEM5E+S
JuiTHvRUQcz0gQi/i/IFnQnmJ6fTapsX0+W5fdeoKePGmJfa55t9eiGh3c7rvLfyzSL9ojtnImfg
QjKNSuGdrzUtrOlQd1llrisBNe+2s5bZXlRL2562CntUvQIz73SoNauBtlfA0kY2b+b0z3+aY7xJ
Lcet4IGN/N0jt36wBv2BHCbX8IDqfsE22o7uyo8d0RyZbNJWizx9P5WZ+z7EjbFJelj7E2WI42Yo
gLstLtjVKTnpBOd9/cB91sLJb5t+XDrspRRXmUCE9pDCACcRevP/sNMzAtWPOwHXNp284P6VaIJX
Ga+4TuAULfCP5N8rT80gI7H78In1sOhe58WXKgaVy/WNmJRycIyQDjMTmuB6RZEsecKrCwDRVfuX
1Yx7dB1qQVn6+vMy58dTH3czuI6mxswxg8aiy1Uu2hAyXiO3IO4s0eELL/cdQZ7FX1ctoZjBMqSb
JJXiOhXC+/j3/YHWvrfKLMi7ATdlwvh0HI+1rz04ZePSngrH4qCrHaEWLp1wy96WwKwn/u6XNxXK
HIyc5JiUili1ZszP2b+EK3nqLYtKce2qvPVAWpurS2q9vhjYB9wzqAcgZdWl5QwVRQmlXL7kb+O6
Q+9rqFr1WANjILfol0jdi4FnqGlB1E8XxmzlUH8qixirlpaJdcUoD1njSxcCfsu+xJbOtZrsNpzB
h/1VuXGRZ6IdASuM1TC9WdnOGtWrE+/reYOnhXbEg+MmL5AUA5Fr9TF/ReOci5qgMd6Qxo6rPT3x
ogCC1w0j7GY0DzqksIw2yW8CKNkRoJ0oxsAyVVALVVsU+Se2tAjgLYqwGOmxz3nEYlnU2HUtSNzu
Ewo+dhj3tRB16Qa/lD1EHgXM8q4cDr0cqxP8MCGNcxQn6MpbBSpYe65K2RAG/nL1Ry6Pmjx4C+f5
Cq1Mt3Dhfm7TIQ7kJo0etsq4eKk/IUaXJkQ1BDCA3Xpfi3eXNGiq7lTePs5v/LlHznFIAoPTHM2C
1BMHoHU7Ja50I1bfK08lBowmJix47TyzYfcbgXZmwGJ/5ewrD2dzSabCTE3Kmp1ItFPaS3dP4EHQ
NZWVtKJA2jdLmiRvjHNClTIQ8NmPUCFfaN+VbaK+7thcqLsNsqID/AzxUFK5+jX+NMnCado/0CCz
dxYIPpUpGAHz5YVuq9IKkLsfdXClRb1s4ytIWhjRstqNHVk3++l29Rb+gFgI5KwrerCMM9t6/BUn
U3AXVX9581RcIgf+SuAffMD0paUWn6dqzGTX5fdUhGgHyMcs/OwUPjNWTQTT9DEkLL+RQ+XJ2ynf
FZbrB8EX482yTkWzP2YeraLc54OufJfI6MrLejvybXAlRCwvJFR32xeVvzms6xunaAJb/w7G8dcw
oUDO2rZdcnTnR6O15S1F4urN2g/rnbrVaXkGc0ko4plwYKYRfjMwpCJ4yPjwle1qNt7KXwxwL0A9
SzLIF2tJ7+TgO9O2+OzwsuLZ9krtOih/axBWU5SJm2IY04kJQ8mLlpgwj3swz5/09qyj/RzLt8br
Nu15yomdwwpNGYSt1g32OYGwFWlqyprz4PmdxyF6cQAjo1KN7itC1i0PuVnWcUx0j4KYqL6J4Cwe
gRz7Dlf06bk1DgfeMI4IeugDjfI8R8dZme+ywfVqsatUWc9P3X8K56c3b3IEEZjhjJd/mUzHkNFw
vMGNdx4CqrjUB71TvhdFc7F00B1RvDf7ZmhYstoJXN9QHNSK92OKminD1sHh07oNdYNGOuVh35c0
jTPy6Se5Gy+ojEZxU1XzRnXExmtTvtze7xKCeggahPJLfXTzOIVhw3lKvHxC+oaLBeKPk/YsZBfM
B0v3iMNTHECxTJjBXW/4aqzz3tcVfcUJ49sFq3VPXp8C0sg1x2GuRQ5RB/pPFrvByuI7PY7UlKcA
F0wYZUJHg2jnrJuvJAKfBNvSwct21NwPmvj4uRZEw1wiGBDfksVaHWkPhx/sOHCLkQXlTxLTaXfw
3rOeafk8g78mU5RLyb5a/D8I1Dx87dNO5iwC2e9IwmI1w4CljcUpVFKdR5dC57pqWJFiJ+dFI9Nu
GyqSYhNa/fRfkQJ9kRu9OxXyKGIBa4bXAI/ufnsSxnEn9vG98RP0WizMESztOHnEagQlcuhmNkcG
PRgp7sAyfb+ehaawA7ygDIwwdv5Rfd7j7sqC9dQi7ZZR6zQAVvS8LWa0wA/udWW2n6ytH4Pk2EsB
UdB2mOsVyw+K0JoyyBZOqPEyXzTroNBWNen+HlA3wE6e+/8qM123EwygEGkHoVbHIIzQKDPWubfI
u4AauGaFvq619LBu9Sg7XbSytJaNCiqG02sZkKFN3w/UWqmkRdwry+rBAeMjVzfqBDXvawFPvCbt
fUY9O3QKfJJyQfZi4QckR7/mRkwLI5HNV2Yz573Dnmv/51F6wFlJ1n1E0zsIe45a9nOA3AKQ8Rwo
gQvTI83r2Ua3aavwmNZ0hUMvoVfkAW85C+tQIRpZJbHFrPIyStwXo8pfUdjuoI26CJ1UYebH1dVk
la1iyYMRD0VOv93iiUwDapvXI+VuKTVMkjM6x+n0jh45OE5A0u6W/JzhfIPVPuRXrKeuW2LtvAuP
URsPA7QNbv0TIpB09jNVdUZMK0CRWb9Ft9xgYXVfnLPCt2D9RK0r1JToK0CF2qVbphu7eta+ctmy
IH6gHVxspmDUwiQEA2u0DiIXr6D2Sn3geNdMuvKngqR0bdFdzNYMkFYYeOWu/FBDnyKndGrdQGWf
+KgAIhh4m7R+G0sl4LogarVx8SKnu6cZtv1KjrVhMSalbMZ3BILxY1PjaMCw+NTEwcS8GYf1dAlU
NipzbjaMvWGmahQwhUq907Mz6GJfA4iBy22xIpVQDuXWPem1mcmvO+kzPmlUnw/zXLmQnbcO/9FI
7gTEBp/4a34J7e6lVX6f0I52/Ly1Tgi6J1fdzppiMy8PXmWjpIB/g+25Xvf3A3foDHnTcbMUSkwP
+2ZUNpt+HsxFLNQeyyXofVEAAG7Jz1ECpzQPAjdXNxdDnfcjpLIaMc64dONHs/R2qXcU4Ufg6GhD
VBbN+jib5y2bmNoAC5wbTglvaiyO1kTvtOAGBtoGBzPElZwHPonFztzU72SAOVR4xxND9CmrkChG
k7BSkaDBAS4C7KTtGSEniUQEzYkeVTcvjkydzplT3ID8h2YrnhCXrzbjNikQ8haAMv5m+FZS2nGN
YJt5WpelgFXW06+Eh1QouFF7VWsH6GwNsQI4xuwebzekRB7ONGDZyVu4ase9Uo5fsQo70ZanlJ79
X2hJb1sSiQ89qtkutEdIECtEwVq/inM5FSWp36zv8DY19ZvB6bChgd/bLdsLyedGxqkfOXIrGg+g
7ol+a9Ebv93ccNCwJpFqwCvymIJerY38xSg4Z2jIhFLQQPaLD7TqpbqQgF4aLUpORRtGwweYxm52
b4026ALZHThWGUmcyQg6P3ypr9oFpzDDwlBrRT+EfBNMPOEGJVRq+ss3lOhiFfqkpWWqzfdSP+Q3
0qjk14vxIw4pihkAbPMZ3UlFyHT/wya7f3k/pXinfY1KxvX4Hgn0JnXsguhB9iOL+q1t7cTIoz0P
qjtTt0UheXuuJyJF+zgmDU6aaizz6+E4qxr5Z6uijCPfZNWndXooxMJSrOjwSgVGTSK9dutT0rxf
JMQFMytA+rUZlWPeMmX0yXsGXxd24z0bXs4o5Bf7HHc/sbdPjgNL/1IAMbG/xo0KLsJy+JCDCcGj
RG1pQ/7YfNzB+pUfULUsYye2M7T1zUROIywTXtIxc/lM7pUHae1RHlFh/pembnnNmmzvvTs5phyc
2jONlJlXAHizDSnIxMD9+WLoohY9tCS6V3w4o9sm5B6rymJc6syg0KpT6JzSjUwYW+KsVCY5xZ4N
npiTfzeaKFvGbq4DLPT3VdfitLOZ9EryBFL9f1gjClpsvxVN8NSfATrEYop5q0RZ7Ir634gOcL+N
xJilCnMBaQaWl8GQXA+AKX+/CzcRnl2k8A3oo9IcoVcJcwYUMBxNF8Bq4V6vflajSfR2i6I6YYOY
1voEalyVYlfDOf5QRF9iBZxbahagDwWl5lR2wMbtgD2EhSv/uiD2jjCiVIpn6isVSgTQ15FHM7zw
y/s066DDFO1oE/CjkRlXpOs7Xs7h0aYS8XrhDZCNUiq8MM3+ghW3QbVxf1vwLZai05iPvNCpWA8x
ile0ptTAiT9bcU/s5qMPIV2HGWE8ugmOWkxX/EPe76BDyBn4fnYPBj3yldt4esHgWLiJAyEaY+5u
jSFSio3nB3j0LmO0DimwOvwFl3fvpVYzIvQMk2VQg/4lbgja0F1gPLor2svgGu76NSbKa7ycjybl
RF3Xj+hM8qSfp+MCbMQ/LHLWqpLouZvw8A+wh5/OUUWS0KLmb6A02PPoUQspgcSYjWJy3Vj0Iw8M
v7LEWWP+/1ujMXnQBkyFnL5b/KC4923jK9TPG1Om4C+mKTY0ajVVnk5lNhJxi75xF5CXmD+NdYYr
UPBBiIOW65QAkBESBFaOrMsxeVTNkpVmcOt0a2Xp5lOOpHh/5zGN/VDyJ88buyHSEgRS2VtWOc/x
HzvvGZTBl8AJ03QQc7uPsui6Kz8p+zCJLZRzK+Unzx/J6GZp2f80g1TVbgg0Pf8sGE37f+CfIBOW
SowgMkVbyykqxPkpVHmD+kK7VXlE98yg2U91FQArhzRMt+mPR3GvvwP81jKHC+6fO9CxRWiSvnVX
fcZteLh2GU8DZO/jP/edYp3woF5Yv9Sz+seXWqmJyJU/csd4g4k5/JPJq0t5POlEdKhPS9cLJcSi
NTfOOW2sf3QXAT1AYp4KIb/p4VhAjgAFABBLrb0NZc4rEY3Fj5xIfnyBbqiQv7M7jYvifcmgnnDD
X73veKfjtDc/Plyh4Vl0Pq2qXCzD6yLtpMRPS5Nso2PBX0zx54+scpvhLSSczmGL6XBxtvQO5QMW
LoEuxKUNYTNC9r+RaIEYc5AQpNKHYhXFS+ktuJLs4UfYZJhdW8R/W+E39/qaNKaBBhhgXeJEviJa
fnu6DgQNaK6ahpUftQqeqCtJrAnH9lzFOEBYakgo9fUlz+c8JmSUcVZy461zIWRNOxu5FwFmJ5EP
Tkq8DX7w7oVoLmnR1IRCr4/OTbGtKNN9qMGikj1M2mjPlQGhwW6IUGetk9XClNei6+rPM84xV2T7
gEhNw155VVsyyevKYwZzUM2ZCBHyAB4G+4ZYS2/PlDfkBIgCTQmFI7m281BelZfjjz9msoB93Nf9
OXX9E0qkm+UBO0iTRsO/cffPJWSO74P1xNa0zb8tkR683LfnEunLumDvrO2hd/ulTTbiu8fsoOjv
qoj4BUxLUV/i5qiCtCBD09HKLvqfGp5NS9R7YHk1fH1fWS0WiiU1534MCU7FOQpEVhSgteDnqvwL
b0acpqG1cDQQqJKOrMNypEJmaAQ3VzS7DgI291FVhU6YQKU8cilHgSLLQXi6JuT60UiU9dmtHBOF
QP5LaxdNpATB4O8ZMqA0PJ7lwQ1w+h4jOJmk8W/w3KG3XV3ljKbHsoNW1kmVoo5Tr8n9HZJTHs3y
OV2LvFP3xeo7d2ViaCa0lNnL3pv03FRyC09doW0tw9GU0S5ggu3A0WExFBxjq9gBuP/EX+9IE9yg
ugIk0eIey3jYdrJ79EzVQjmOlw3nnERuJ3c9cfC74KqqrkfIuvx//bgFgmgBJXAHDUPRgOJ8/rka
ABrKJ6aXIkVzNOTn+/VR5E7MXsNlTI1Ehhn0YpKieYt/qQc2pww9/qZrdRkj1YvmqL8rpy+tEkpU
IZ02KNl5ZUVHNNwQuX9isT8E5Tn0d/AjtJckrvAxJfMDj0H63ZyC6s0tFgGZBru+fvTRItJaEeuM
LggS7FWj7K2MHzRyH5Vwaf+mK8zEb0cgDVxCECn0hoN4VjF5BvehH7RpaHRsH+XkkjsH4QtQN3XO
7+/mvRe/j84HAlQckDDJ6WyBj77z+5CkPJrrw6aQy/EkSmN22mA2NTddYT5l/aTzqMvpzHT8jvfl
ygrkd8fmt8sALi0a0oUcFr5Nwu2SN1IE8EDyuX56WsavplsscKUf6UoW0AeYJTmTaiqDLJJNv9sL
KoKRIJooAGlBd0aibALXOVro+dCUBkidmQe3UAbH6xvsLZYQQfXTXUyNbspcVfWv/ll41C7Lj3mZ
gjHo1fqkLsa7JJBpGWLAZqwjf9NAEP+HTIA2FJRUhK0k9MWYWQWWo5Bbx+kkfbRUi0ixM/g5Yq7a
wtuGaOjMipDMxZ+Al8g/ObqhBaGOKtUXHosPJQnzKA8N9JzNZOBue/2YW9MC4D9GCzIN+rCk0ZL6
PxgIclv22Sbgj4XTbqN2p1dLUAMZ/LJJTuboVEn16uoGoNDHm8DjyTxArinJpGBW2QnCxLWQzQI+
2E5Q+HF5mYUF9C+k2JTusdzmyL7oas/r2gV0yq9rsghBGPZ/pNUDRiRJ27q/gCL6uwPmaf5OjRrt
c0zfd7CL8nYyIOlNccsR+WrBEkhbmOfKwkSZIXWWwfygotN+L0lpUHNZ9g66S/g/pLVARmjT5hKL
aXSXXoUx7lrf8ofsgxOr9lruVj/c7dlTBXhZCsG9pMy4EO/t2E5+9debahSOp9UnniGOhkBpUMAC
uIG1BfmfgK1zFO0djyX9tApMJk0jgGj4eVbFDpVO5ZBp2fWYfaBY/yVfXV/DCxQDRWSoMr+mf0Yk
NtAz2RhCYbn8z47tHwfFaitLKw8Cf9Ufx1gNykGKRhczezruzOTlvWqDtA0gjvV4nvDpCGkEkryw
DulWvN+oPCvvso5NCQcSWF+gcbzmPMc+EatdyO4Rmftov6jTSHpe5bn7MjNIldT3+6f2poH9lllN
ReRH5Yv6W8m1sNrA5wUqMnJi4zeckMwWdUi/lxcZE/cX4zgsnuSo+SvWfg2PYpno9bgrYQJRONtC
LmjR5CrHKWIyEkCA91/5v9KL4YQDThslFfWK5xj+xlV1s3+Ul7zPOFbesGMboLoL8ocV1mEv7Vih
vKMbF0VlYDmiy8P69695tN5k0A9oiZMFje9jWxMtMdA2mlASmeyhaWy3S7GMBk3Q/7p3ST8F1KCJ
jNHU3scrUTiCqJTcH1nJ1eJCiZnQ6UkgBNMwDiPSdxnCo/tfGSGPRMOlLh6BQb5cYB8yP7ZietgZ
uxpSV564wVymW6U2KAYDy5ULlmrKBAquyyG5Gkib/uyN9Kt2XvTBU2/zM5LJ8W+zDalWbnsAR1fa
+NK42lzY8MrQYIautO7ca/qkiQ7oce3vgpgRLGZNkHw6j9GUCIYoJxZGKkI1yp+40h955/lVzrue
U99YY0xwqgD9fFg6aDUJBfD4Y9Q33I9gNRUJYXSmGdj4RJoMlJkCTFozR5Cjm82aitivBvHbJ1VF
Fs3vjN9/ReDPtMpx8obykOKS2O30O2jmoX87679UfJ1+klrwbxiET4STuUwxvS++N0yJL+Pj5LEz
mx1T74xPxzkCVEEc/ATHLzYopQVJ1G5bRQfWkg14uk03ZhLPn8s2ZUMRuaO2jT1gID0yEMRtNnPy
4Rn1aPL90c7F8lVguQygUWQP9Ad5MYU/S36BuTZqIR+L9LMqAmLoeCrSB2T7I4psrxsVJQGBP2tM
PxeOt/LB286SsWHNNzAXD6ayB23umlc6H349r0Vo21RxlOE1kPP13AGNDfTg+t+GnYBMUUnOdW62
6SgPl0gdJ3Sk23dMOYJqtCMRHsw/PD1koeqllFktbjC4P027SDKldHupDEBr4/R20cnjkO4GF1Hg
3QScptmD21BY3BxqrERoJPjFajYCt1lOE5vfBFNIy1QoIX6C/leqVJUtNe5DMIlxXSW3/2v1VIW/
XtU3e1ayw2f4/WeCFAN48OfwZ87r9TefVEeuMbT+CmV6obET6jispruw5E9ZGx5Cp7JbGIWrwAVR
RAbvXVI3wQ9SVMchcdmyUCJJeNV4lXER7DK9N4mcD8F51lGYfe8+paTabwK1i1V4/GrVEFkyjcAC
F42MXs2LCj8Lu8gD+2+SYsAmdQ0bnEU+tRK+YWHOw07vPQh1AEIEAFkXQrbl9IdWgDWBcX0+YhIY
IGWrH/XdNDFGJ2VWGRJ/RpP2tzSAIM7bVQVoURPDRlqhyunRkQrdaOH/l+Jm3mnCzXb5dm39Y+gG
+Ca6DBzPPKaJoyueszR808bZv4y4e2KStXJJ50a0ofcQ8/Oarq/azvXXpWNmgQOUskJUbdwzkmFE
kD8PcCRsSN0VWfHdheC8AA1bvCSvPPguXz+LHSh2IeSxpZWI5EzRtv/KRdoj2e8LDYEmpoVAksQv
4a00VROBx0HkEG9Y1Pe6a5cwtEh4A1JdRFCWUsDBUICXPOFNi51IUF+YiYVdMS0aMzhBYCYpTt/w
sR78bEuahIx0pkNoH83cLbU3Ta217OxZdKzHo64zNQR0SiH6VMmCX/QqosBch+UPw0qyFqnQAJOw
Go1oulPx9PcpnmgGkkwUJ8Gk1yelY/Rkkru1QSu3Qmj96l1OsaSW4lM0KjSnvVnFPYex80647hEA
v4P7uIftoiEPasoU/fC8Z3yyp+uqsKdzXbIgf3G1XAecb/oRuYVvBh8JoNlLA6BeQgLphwZJiehb
AcTimonPVEJQYKEkJrHvLZb5K3Hq5o4ERZEuAQcNq231rSbVaGdOyBaucn2ZJvrDWXJFxdQ+bSjb
UJk/KyAqAWpjZD8AeqOCgPVcjPj7qdAoerhTh9gpcbhxpVDyIJp/usp9QOgiXrzG7Ss/7juPzjCo
f9gSvk31/1SBf47Rtm6yGYEZy9Pv+3e/M6qdIjT/EHpyJ+KqK2rqM/LlvkEhMDQhngKFFrONHFt0
xi3oMEetDF0bxeBOF6bK9u/w/NaZPkQPVw7cOPI+05q2l2gQi7Og40wnhJu88UUbOD2t/Pqowr0t
39MEh59/YdY9HWM8IetXpHpAj6Qbh13XR13YHg63XhcF/uKZzFGLLH8Iwc2VdPJalhZKQAE/N+37
7epOzeib9mj0I6jBdi00WTLI60xgMaMmRF2uhU30xBPLCBUvulOFgmDDhaMl1tF1115u4YQIOJXU
A6gXut1dy7rv0TUqfkgNmn4CJFxcKPI+nkv0ZRQTB3tT8pFwhWyoZ2jmrU7JVvAy12JBgUqno+pR
GHFUi5Qw/gfAh6yBeGqXO5BTqrqnB5KIV27sjC+mTsZpXyLMOTYG1B5EIRWAuazxK4vy6KhX1ykr
wakPuk7bMMy7SxPTHe/vwF8TMvMgQpppzzpqWexUGA+luKky0jLqZVGKtujTKkL7Hd7lmoo6iJh0
etGCsHDckyA3+RmtWJspLWA+ekfkPaB32EcWqX5CRgGtgytQ0EF/ye5ADkMIvEJeoJJLSOKAF/yr
9JpfK0kvVkiHgPwSGDqJ021Q0trImD3XLFe8/WmObWEge0v3S949r3Ci5RwsO5/mQdeAlzvXC9RT
kXhSPnkQbfOkajAepFCT0ghkWcGN9Zr6mkeRCfXdtBEH5ZT+aFt8FlXi3cJOKB1yAWtVpy2oMS32
hXiF9RG7SwsWeN+L0RmbT639aRm0sFP3TVNBS1DM2+1XsepLMCTbgDoqREE/DiQWhexJGzmz5XXY
+2pIPY5M/V+9+3Y3lx64joOzRE/hDU1L6SUCRFs9vl353mZOe+Q07+Ieo++T2s5dSxDvi01gCFW5
uK9suJaoZ67FcweJZRSnZgs/B7hwCu9y6tkVuWd+b5+Pt/IBwMGEt0AcVyvWZZTo19yjGgect2P9
1rvKLKy7zF6a/Bkdx3A49IOtHZVBYvUag9wO1hRnxzHYv6YsdeLdP93CwmR4cYZv+mPk0RE4QQyc
He7AY6v114Kb4qBMn/ayx8hHv+X3BonmB830i9D+yt4JGSolVr9xs0YppWN63vdySz47Yh3Y5mqz
dEwg3G0YYwwvgla5xvV1HVk48Kms+6EiWXUJlhCqLKUGSfVVJI29Q/La/acfBwcgx3yqLk9IV/Df
qBKl10yhQh5+SP7zHu4oZ9ba8chFj6XCI/H4McYunNUk0r5E0SLfAp+jv+v4vqO2fA1MH2ih2vch
xomC1s2yf/K4Ah69AU37/Fm2ES4TQjtIVFMnBnwRXfXPfuRYSXmS9v/P52RL7bNNz6/4Efjp9bm3
RKKmI4e9gI+ft/s+jx//Esh2qf4kAgKyvNb8pRi0rV9GG5aN0vISgTF+KwWn5HPgL3wCgkJ3PsZJ
wMF0uSnKMjcCYqhjDdbl+DHO3xw/Sm7NIxBH1XAV57WunkLHWABy2XOGvkAdvaWizlBrm3z+VW1+
PIYW/30GsojrZFUExKtY8r5PJwfgbR/5ObwXOoqev+ReuAdEa9g4bQLshuoL4nlhIUnBdOsuY0nS
k3NdbFfWIzEc2plRXwjeLn5grjQ4xAxVfDUB/yN+AyubWAKm5iT6rSm64X7oeG+kqxmaYMIAMrbn
KRl8zi2v1ypkTVk78VOgBWKXw7IXMYpX1rT/xJ87f2AdmgcaitxPQLVXrlIZb27aOs7DDwo15+Wd
VjRJPL1FpTykRqonN8AbtZ6Q7C6KBo28+JvyfcUSYNjw9q2ZApqmXEkLq4r7Y3aUCRWDz0Dlphme
oUSQeKVDHRbMXPSDfOXMrJvBOpZJgFsmytpJl+PCHAulcgsDELfMWmxseCu4+uUo22nO3l07vH+2
7rI6FDo7OKBGvQ5UCxCLYJN8OI+Yt05lLObl0LYmqp+97eq6YHcCrgG8fhYX1/vwPKY3JEhwLETK
Hk27kvwcRISPQEd5QDN6x72xnSnd8FIb1pe8IUUIgrbY60yPiKAD3O/KnKIVm0L/kX9yCjKRE776
N0sL4+7XIruwhKxiGVvFwTiIB9UZa79tXXyaBARA3QSq2GCkrZ9bZqrq00n01lcPD98SdnnmvaX8
l5O1NZbN1rjorwOOk3JcHa2XSIvQIzPdfh4WABIDhsPTJwoZ7UMAoDtcdbgFThlEhgOBocoljGM2
B1u9RmWSdF4ZYfaSN+MmTHksJbHJTNBIHTa5t5vuqDpt3Zpj/nkKYgBDXuUC2RBYPcD64Yde4LOJ
XitLNCGoUG/uHz1VDlgWyNIv3S7rqpapf6Wd7C4LBJNPFTdNC+zAPzv+bXzsyFz3JD8O2bWWbWx+
y5SpDtMlbgnMescxkprHnjKl3MIKfijnfYwnGFPckr32SqTnDbS8CLh+X4qmiEyODZ38Zq//OkVd
Xc4EY1o8iNjvQWgccVYosLxYSJSw4mitfCtp2qcN7AwB+gKhzp9qaOIIWU8pRbRKJ+cxgG1f9rTz
iP6Yg2CtHoJn7ZsqdhsnKXCdNLX2mWy5gPdm7BIQ2k1BHZ94ht+x6mxPRuV+W8DsPsGvtwpJcLN7
IDdnLVSzn2WnT8q0vW8xIpgvNVr34XDNEMnYvidVsmo3xHg5pV4ShqSI2sHYEtTVoURlz/qGNdAb
42kOnfeWgzodDk9goum/HzRm6yqWMbqgMpt0wbh83Yq/1Q53ElIwCvZG7UPZ79DQZ07ho3wXA+7D
YLDp3D+MVjp78pL1VsDeP/ZReH2/6DzjyiTX9D7vTl/ZmszBiYoBkHfKS2fdnqE1khNKDWnpczZ8
oppC+WmJzvXYCu/qIMOJ2mwar64FTLlh/wdy2+WeHcJw06rIi89x3GXZf1g34B9v+9KO3uaoGJF7
SlD0RODd5YWaXHXcmjJ/xFhN2jDZPDfcZ9DL/koXmwK56COl42D670jSTaFobp84P7vlDUyrm5nb
1V76N7zRVXK/PwwhZze1ry1rnwIAPqav8bWoaEL7Izp2dk0cz0HPOViX6nhZB4j5/5uX/smD21uC
lWqLIfJrv+0tEdZWf7kvRhEv44/nSXs9k9hnhEWmqqODec4FWqQCENMXlgmc0wkNl5UF8RAUts7I
A+ctVWTkoLRmv1ZFLTEDNYlrnLN8+BKpVxbbCjtJHiRNJW7xuNIOWyswUs05TptaQM9PqB4cfrsc
DcMhphZh6akUtFlLjVxYmBbfULoW30oucT6In1rMPOg3lgTdHT1/bNfbDN/JAVdSLQRyFwvPYf84
J42RVGL9e5cgQw1B/2cZ+dtZtAndFRPYoTmRkx6KDhBfJWZ0IMd5waMRC4hzf57GJjErbHsHgOta
3gIVc5QrXEeBGD6OVSQxoKttg1ql8g9v3HIHAa/RVsG9QBqOF5KXOuUiO4OPobaSmrNzeUbvInRN
xKdk+BgO5+t13ywLxU0APXhPG/1ubL9Js7+RACp3ywuG0VBHpn7r3tsQKxMuLUzHjPas3SQIPKzH
jcRUM7g/JgYlo0CzLJH4bAMzuciutlkMoz6Tz9hKsWLMzXoVVFH7CxzOBT9EzobVPU/uCw9PMwuL
WYQ2bRpuuf3Yzu8XK0KaWlsLYwBrCXAv/PfzRGL4nSKi/bQpywymNjPLLm3CsVxWaS/ALQhhT4TV
T47GHQnJFoqH1kkuSaDrjvlcCN/+O31CyCDq2d2SWhN4L9TYrz5G+8YHA5mWR8HRYohpbJOKV9Ww
RNZ/QuDn2UyHALn+6z0vOrbDL/wVQ6hcrRVPjm0K7va3Ua0ESBcvGRUrLlN1eXcccENy4+l7V+g+
mXsGKoHc2/jLZ7QD9wHbyEQkG5MnFe6vKloznWgvEA9CeIkZBmwjFOyyXQjp+EAGStYs1x2unyXA
iJDgCaqt9tPqYWQeMmH+Z1kaHmh/OFJornBQ07CvQhI0s7QScPVqLFdXjJ7ovqgQjaF33TNWY0OK
Z5GI9TVCczNQqs2u0QhOfTMR6awPfs4QirTE5nWjV6khRY1rlHqQnhvoJ8Dh/HLKaHCTzvn57D3G
7YKc3BhAk7Fc9oxTMK0N5VfJmKHuRDeDmBec8ZxmF4nSVzd1Vxh6AHgCeZT8dhlDefv0qjNN9rdF
fwChNmQV3pQHfab/TlLBLqvlBINin1goOqeIpuJDsx5Qy0Jf2v48mAa6GfXulnVAVoWAQTkAncm7
duqsf1uly1A34pAZj9Be3Xm17Dm00Fe9I7GkPSscrdf5eneedDJiZEK6SPsu+D0pNniBvEt0dQsW
NVNFpN1+zq+14VetEc7Frt/twcpZmx7uYpuJeX+oP5AaXW/uCEj//9AMts05Faq7SpVQbTgA64pS
2Er9/fnxNyfQNAL7Tz4CINVrLT/OvZqdCOHWsU9J/rvPcsetjT0zCjYWnnNp5KTW4oIQOicqSuLW
jE0d7dibEwYS/q/PBPf7/JuJKvY9r8T/1AlT6qaYdjHsgPNzJ2P/mZ4R20EXuFQNP3lp+0MXSFNN
tjOUjHVfUWhFCXOhAJMZGlqbUwMVTBYNumrodilu3s5sCdLpMCPu9bv1E70dEwBtaV0j4F74bI06
2kSR+noKA2bRzh+rBKUXSvJzfz7J4yDKXhXp8BLcp6G5qZSb8HnQSDzJE+kXuGg2rzUYYJKvDUq2
5cdmMatT516pCJaGAD74eFFhlWBEd9ra6O896CBBtD7AVcU27TgVWUdExSiwV6WNS2OrUnSDLRbb
j1U+GCwabj/Fee4JCeHMH1M4OTQ56BdME7vAr5wbBYGDLsc8JkP8EI2H+1zNOUwjhOTlLgviDQwB
lamLqyjk2AQptSsuVB77uSzLb0rCoHjJvmLXxlwbdkoGwtfyIMIrC2oGp6mntwe98HtGyxFSdJSQ
z4URckwaVWa2lASaG5K5NgzoGFZdpXSWzTIKIOSQcLXmlM/QINZ0hUnkwYrRN1PZ1Ubvb1gB57Py
KOpZljBGFtcpN5T9ws3ww2q0c7dEEPdL+OHZUKScOhJChrUPaebsy7nw08Yd02sQcolgD8TbUQ0t
Yu+StvFXq7bcipW/wFd0SYtaVHPwuXeBbEUqAfy85yL+2MtF0n80tEn19eGA/An8Y3g1Z9DYJ8OB
vY4IC4wL/f+YbNSA+mhWVal5RGFXjiY+TRXilzrh9HBx5FeeJu2uLcmsdIHLkDrHwiIftBxHZqUf
owb4mGfJWa3cDX8Z25uZ6633pYUUjDmxQibecZ4McPXoXeZIKXZlgvVA5Qr2eho8zA9NuDU3kfim
KpO2ZDG4E3wOsWRe4ujKv1g4KVtifDizLJVREdmx+2Wob3lZ5mKNuM/UYAiv2cpawdbVYNdN5nmg
LRkZ8H29Y7mLoXeuhnC5/t2nMN4HCCdjIs8Yi47YclH4PEWxfDDT0CYwZJMJaBw/DD2h1kL79l1/
q2dvlrq9DGxpiU72d4ZERFlCZkT7X7Vee/C/menHrIIQUhRkNiYNOLl6rmWxLfGxjbVfS1chttl5
Sq0vF0DVs8T4kOCT/dzjqkSFcUazE4HSt7IBSXdNLekMclUqyGKK5ciu7Dcq36kvqFhBIcRmGi1j
Bwabo+9nRd7TJQFSAlWGlnzcSDlI1B+pEbZJjY+7oz58tcavB2IjNr8ziW9ZksZge763hRsuZt5w
pnQfLtap1ZzZByhOUVpbrPVYELpzS8vPF1VAw53pmqkjMqYxnSkPAZ0hn0W9jTwRUC1h9B5HtlRg
3WXK4kTC26vMMf/OxtQn4R/WXeFQsWgXfJDxnZ41gwz9Ro0ZUQZrASXC15xdDBtfxsLYvVRQd39I
ud9REuk/Qs4I2on4jzAChF9UlHbkW+n9xs2KGBmG9em56e96L+LE5bwxxy/2iDWx3zJAeGpc7EZH
rFGdngW9FL0YTyp6UQC21e6Q3QHwXqWRa416WtvSp64dPojn9rFZBXfqJBZ6LplRpziBKC4ZmRPB
QROsL7ILvL2KVOYHyqXqwfH7QBJCqryTSanqIaBEkOk+JURAVXYHCOMjBDO358x+2yaQRRflJwjM
iAnKwVVyZidzQp9aDf1FDppw85Pcn6ol/R7SZm5nMkHB/LDjhWKCYI1QCvIZoZhAPMruiC895T5c
xXaK0MuEbAMDz58sjWNEglZBeVJMD8TspLvT9nwQsZnkOMXZVKi6ddN7GmQ29bHW5TKv1vZiBJXb
1X4v1eEjYEtOHjIDI5VooOgF7uVlHSG6572p+kKnC6mCqC3qhnZi3jOWTsdM22Cix0qUyfQ6VP0q
RVbcFZXS+GnwUkWuSiDJhSHcKZu8y4JxY/idXRVwKLTaSnyaZd7a/cijwzBGXFil62l4Ku6VQfe8
+0aOaDJs1WFdgHtX+7T3R7nraaxeu9rU8GHOEhoVnzSBoWepwh78sQjzZf6ZAfUzhvaHT/DOg9lK
YRaIXMAWjYYW1thb0+ngHwBjCXw63AhNwCyZvAk7lEFEhs99VmieOniwYLRvdJHh1JtTuQnIHxA0
Mwl9D2GIVsI6OmoQLX8kgiIOljCysoX2ifahmrhAyubMaivrOGxMpYbQQQjt/6hO0nR5baU8gjCc
l71uxT1FakHG+ScUu58K2T9jQwC1iNWkppAmjFjzS0260nznBUVM4fm7ME6uczz75ypS3O/9Qezp
EvLlXp+3dfZ5Ave0HW3GoGH17jQN8NxWlnf3leKBl/r88Jxw0L45g9afdiiHRMUeROXIlkUuDvA1
Fp//QJpaGN+JR9oTNchjqt2dxtnnW387X4CbI+GFjhCmw3i/8e+by1l591QDWMKeQo0agvsry1n7
zMOTmG5WxOwBUvl2oeGVwJ3d0E4Qn4lUKOabeAKU2jH0mlauZzHj8/CZQWwqyoAjoj0E8IVNVQJU
gJXexcrOOhc5CcBBkY6GUuTsbjZkKm62imUumwwgjGoBfSXr7m0iqlJmln2MBjUfOWdKNMAC36L5
1GedG49/mGCvk9sLCPoNxllmn7vXiROMctRNU1eYN4rRqBTyG4rN5akZmPoqt6bLB43PAaFu2HCs
4p6i8kCyxOzUwsL5Xvqs3AAOFeMJEWITkwihfuYQ5+CXV5A2KE6o1lFmvt3KlJ+SweVEO3tqDXAF
jmcDH/KBEbs8cjOv9DFyaglX8ZSVG6IWe1cq22/OUHaQtDfChFW6/W660zPeFea7Blooxo6w3vG7
+YGfyhWA6PvlilBLLtN0hca0t/AVT6wqLKS2M5RIzNKWJqg30FINqRuEIebpT3ZTnJ6kkM1xuNS2
a76aubo/G+VXFI9paxtkC7BH5MzkFb3kAfLSFFvX2eGLfF+hGNP2hTUHzz9f+aXhAbbeOu90peRR
AXebYflTaplzA22PZIJZWrtLIUX0i7W2XU4ehipd6QfV4AukM4S1+Q48vxXwDhh+Qrv7YC3vILhH
s22EcfeluN20TWJNgDVzlh9sz67xwFpCJINTvlLCtrm5aNwlsM1GpHnuKlLgeigOg8W1Px9g0TiE
6snO/nHRjuatqwTpkGM3MQKXLLLW+Ub7ohRKaIXOAw0bO7dsEz1sjIrrFtK2f5+KV1hpHaAtqegI
3LlbqMnonRrDwGiRGdZICJ4mda/e55dQ9qgy1pWfzyIyPQ4z/xP+JyVN99yxqRFGHS4RDgvyEOdk
y3M4f+Ac1cbAP63DqxgHk3XIPfenZs2gwYpQ0eFBDQKUrAdQgpyXucQyEKb0E1B4DBa5ypK7PqgX
96/LWU2Dq9jIF1y4/rzE2GoohDc8j2PYAIIkzfa0HZAYzHobCU+gTQNwPvz6Dlp5um4O45fNRtjh
Jdqxo64r9Ppi1fppXqTKOaC1C5SzO4IROXxvqiIPpKEKf3brYvP4pHeohrfgB2NfBaXccszn0xXs
ucwvaJKHdqfRlLkIHB7tTujdeCZkVMvfwjnXN8TIHDiSKdNpTPJ9HuGnloe6b3I4lm0x7EghvRtl
ViZOhlMMMzwX4xSIE32zV7UeUk7SVBa0rEhPmJYaynvej3rY2UGOkGpowR0KJF7oRoGbdi5igFXG
PTGwBJi1NL2ZvfVTcOeW1SyAjad4RQBPyvNID6FUzcCEQH7WSNqMJhFnt7xTjWXMLQ5eHcp73b2T
4l0QS7NqW9W+GCn16B0d9YW0wP53N/qzq0mD5QM04D4e4cScToBydpHzEr59itxiN1ph3UR9R76R
fSkUkPuWLCdPM7t/+PYh5rg3aqGe4YIu0VqkXyGQiXRoy6g19/l5fVfaMBqXrhvFrczus7ayi503
/af34+9BUEmBbD9t1wvcZdBaoRMoG6dRmXiCQu6pnKo+3u9Kn8Y2nROmFQGnmzP3PnjtVyPvC2sn
5J57szwLiKXFw5mDqLgJ8XeJi5CCLsXv6W1xS7mmrHnMC9IktSIK6CXDkmPuws+pSTcvYekhx1SJ
aTdJ4GVUWjBwSGRFRKf9fqASwOUrAy49jW4aPNeaxWysqgCrb8+Z/Nju0u4H/LYt2ICoAtJ0Qgkt
16AfFhsYP+EtS7oOj3oyEa6jMtybmk9soWlL7xmScoMulKR12ZRzAOPJn3Szz4/4EXeUGX8y/n0R
2tRcQcnjN7j5elFqC5PDWddjOhSLRg/PRkxvnPndwLIJx+BzlLQhEOk8P/qy3wdfmc40pFzE5vqq
B0NDNnZGh8sZF9hTjutkTofjgqRst1x3kkja2jGk3Y5/kqDEDLpHrDwwKZCl8GDO63EY81etDNyE
7EjZR5Yg8k5n3BtkETbkeN/6u/quz+Q6vO8dqG0hLRvytrF+pfdouB8PkYMHRUIjZWSH86AfU7/Z
whdyD0BBsvFOwrK1qwPYW//xgphseYK1+7mnCSwWWmNkOWG/XzNpjbvGikX2mWVPnbUGrjzV86Ob
xJemH9k8zE8HMbMqWpFlsUncGPUdnZnQ+ibjiySfNGqyuJywJ6Z5kID0BvH/H1u+AEp1Hs2moGPA
70Y1CmXC6F3Nb4j/Z+lK84i/B9sXPZKdMv5+rRk4E5nh8K/hfT8jYmwKFZbyPDufQ+40uC2R65EU
lBsehEuX9MMV8lfPI+4LPftUKPjRFTSob58kRQ2gpYiZAH1Pzf1ggiBub53p6kzb/T4kHvbaOUAf
LHB/TRQWw09CescAtqK1FM2KVUKPOT2qYzeeuKHchcWf6l8OeKYhlgAcy0Lv3mf/wWWLD0ctJmoX
nI37wjpkD7XLCvlEic5WAqzaFiJxUSXPN3u85Blwv22T+FBiSJlUWj+nJY31KspfM4c/Ou1Cg+WD
Dmx8rA1/+herDyxsjK83zyJVjLJwRLSDCcPa5wgNHm0rcebt83jjOb8VYBGUpolkWFVzvYkJjnMg
ZZFBtjlNLUw1jfGypZZYwa1r+HXhajWohw8TWoPqMW8i7tDeUFK8kYEsOm+epj3q7M8+khh6yNaK
sy+LtTm3oc9PjZLPPlqcZQ6OvO/4WsI3/ustjij9QUj2r5KGj99Y2ivNuqaozA5B52KLu/h7EpRf
GjcaiDUQRxWCxfIfpl/nH1vM33/rCdNfg8pnbKB/SYIUfbd3oaZZpgbChz9Q7VMoQtrRfx5WkUf3
FnvwWd+tI8bZLh1w8vKu4hkb691eUxHu4Qh2JfLWpMVkRPmvXN7z/Wftn4Du3jLisl7k0WJJ+bCV
HddFVp30aiFufMvlwnmvU05xrV3xvMMjThB/kmHhftTfOl5NbVPeJR2QQsjUYpQPj2nC82qb1E3N
KYvywZo+u/EnR1DFhK/ZmRg6aKf5hsNFaCwgs03j9I1cxnRLJttzUafj+UA5T/VgIP4ptBb1NGta
4+XZJyBodEnBAL2+2BbwgL8FHovD58I4AWnsYWT1DGEkOz3H01hvA2Jlv2pV/LByfxS8Y3j3uB9a
eBNL04rGn/aaH0D5G7VhO0y8oEEU+D4PfTcvsWa1tVSbHero9BuURY9a7oPL1c4xM+xwW83G5+pv
w+E+jH7pNZ47WfQjJ870utxugzjrh3G/wyLkpyqxrqEiN/whKXKxzl0QbJAyNdh2oAs3WbnwSJ/b
zB+06pIVkfloaQpBZ+VL0qGu3V4BteuLW4e3hsX3s5NfEeP13Hc5YUwMxIEE1Ird6rnXn63812jV
xYKNUfBZ+S/RPMBdNAdITkfmrMGD+zx4AdCmx5ONLAXnpZzgtMuLUYc2gsVjThBVSgJGkT4BNmQx
vuPOcMX7CnKgogBUNd7M9I3oKlDXBV/2Bsmb/morCyxcCxE1cidmNnpm1okAgMmLwUcw+AVps4FK
1HOzFMeSKYoiHBdhdt4aS2oxzwwUPeSyOmaz/SV4Qg95zIndvtWb0xmM+TdxGh02uAzpJTqUZTdc
5U2Otb8VKkdeu8yewADirM93HCF9ZLdwjuq/HoeVusmvDe4VORFPZf7q8Ph1k/agdzUOkWSXasky
aXsoYRoAKFELnkEVIDybIaI7BiRu1HN3+Z0Ch811yfmdtQbBdbVSvaoSOUqPspr9ZO1WCskKSyu8
uKbNNuJ8WS4V+OzlEDE5ONJ0vWpzobJAYCVYoNIfdHJOCEdJqcFXMlxJVaqnMjY+/3LGC6Binmy/
9CMSTjR6fL1Bl65zQlIlNMuPZIkcgHPvUBhdICMPteWSWGGD81RmRy0bUsUqikZYsakTO2vzBr38
jpnk4DH1sdu1tJjC4284eDAGYGwLBa3OYrNzWwNKkyUXs7BxRhzyDpG3f1smgBNojMMabe+65cQc
kl1XiR6+im+hxpxWOGYITE9QxjIuX+Bydc1LLp+Jo0LVA6L5znsgROxcrSX2b6+Wg0wRPhZFqMAZ
GCMdh66xAmcx7+J8SEqp7ZBW0I4sNNspQxiEtWPhWSvjPjJm6VeRvZL5rnL9VNTVM2mJ2lidg7vN
u1IvFVf1RByh77Ta2EFiH474IaFHUZAq6Wcm5jV/ceRn+3OBNwXLzE7ROPXz8O2ssgx8NqBdCJEY
aVdX+K9h6O5ezXi+G2cGokj046o9LjLG361ST/3nhpVYm6LjqvD+g5JfUoNMrUG/8iiCAG2DMz3S
ymiSn8bJLB/zlw0TCnMiVemTMyFTz2oaicFefOBO6tkCrRKQHOJBtZyNcCqn0RnYMvvLCOilVg7K
dWAMLNOHRLqF6UHM65iGQ6O2+j5fBNan0xn5otLWaqJ4SJZKeQMjed7eY0IvTzBe37sAo7KCZWlk
p3CJXWRyXGE6v0s+pQUOQYeLDqjXafSexDLrY2sGYwM7nYvVGF3pLn/lWmZD2hBYrQUPWWqbQs0n
D1ONh9XG4r25IAuPykgh0qEf3wJuwICDBECppBaLCfNJKrbgODLdaSrgL2W1crFxA5dVu5mwnBsR
yD21UZt3T7a1l4jGRsYhNcpXrjT/GjmpZAs9Cp95zVkzXMYJvSBOIWtPXja55ShNP7Fs1wk/hCUY
XiLdbbTuaYgSFnIfRhI5HNyh+Mus36ut+GANhyuqMxXBZNhMVBiJC37uKfdwn6kLIqs02c3T1qT6
h1lHPHsnsD6iHmpQLyYpsyXep8ZUbtMnL9AloZ1pdxJz4PSwNEzu5hBkUNsjlEaA8/iX0nWI0W14
79n/MWY7Uy/3VUb/PdWXIpXfZ1ijW6TdTFgGxgoLnpoH4ndHDcL5j/v3Rf+aMMMZhWgFF/+HCDAL
q6Y8WDMrGH6nTFYUhup2dIhphJpKzA9BX1NNbF2CQ5G4BNHiCT1nFAysIEjsPEAHtzjcZnQD/l/6
4tzktik+DI7t6vbu3Yzh9Yl3RCh9ghIR04UQWvdUgHVoaqK1rDoaftCqnX8kmn/NUiICKF+VceTW
YMFBHDys/b15315/DAPGg1XztFZz+Ex7cfmDza7ZQmetNrHn92IC2uuqXp21Jo9nD9AyjuRu7B+E
O6ycdxU5P+rY/sG2zsFyPuT/h+GAFAM09CDqhTI3z+RJUkTYHynBo6r6QBmOb51esbCjdsxxIaZ3
dSNedhMBOxHkcNMUhf9PvMEHrLnz1hRrXCMKLFu/fo3Yeonm2mT6X1m0Ki/h0N4EgoqdnComy8ek
4UiiAT7FBHiSTcQQlj/yy+0Bl33to2SeFqMYSC4/A2GczAiPTfITpy44KDHRkxAPF4Ai/cEYuvYC
0ZiPYcg3ntt9lQKuSlKRIAyE9mYTi3LcKvDqXk53+7XprL55ZiKdUgQH45VDp5sosQjpY1/2GDhD
q4Z6PrdxMOggGcJMsX72XETB09xUaUaQSoHbIN+Pb5sXwDsCGwbb/pGgRlKwIID7ZIduChHp53Rq
n1Zu034/qQRCV5Lgtsw+2D2jhkO9/B6vN3HW9Bn3rrtkglrM/zDM72WDY5mcpZ787Qeu5kAq14Nt
1EOsurxkRMznJLIDIGiEeMWUB50dQ5m+I7uznaxORrQ9KM4eynzVber/hXKINfd9088Fn3h3Vd+j
OHn+hcm21sm2/hKARZt6SDotfF4bGyInFuzHIe43rmVHNTlA2h2sN15zOQYqlexAbel6llrX3FAO
JxjYxGV70JsD/taIPJbJQAZupjgLWaPhlsXwbGfdDM2o3iz5hfc366viXjg/tiLFDh0mGEX+Ak5D
RgEzbaCAclNjvnDh90zDVtoQb8J7Kv3nlKXPOQsm/KXtDVfK5enavOy4gGV+miiq+96KOzkBoUZJ
5lIPaQUTwQ4U8kelEoSQ1zokTH0zSSR9K6FvqkzcrdMY2BuJYYJTTbcOG+ERJsfj2A4KkQOctX3q
O8oOHgNqwm0PgZMiKAqKehWwxnIA2dfdTvEPMMnZHvR7FrfPmT3CltOW9f/sj1ZbNTI4SrQ/TGlv
BpckF1sdfBqvv99AihE2jxKwtdaYs/W+2ixaIrwx98brwQStB1bCuuZMbFrJZU9qfH0aWtLuTZJY
ZZsVNjPoO6JZMOVyqlsxiUUc3wdKkdL7trgquLV89QsmsU7Lqog6mDijRMnN4akqJbPFTv4xeRCe
TKKtO2kysFGhkApu75hA9e9NOS/WGSP5Em2Qj5WCs4kAt1kkNr3KXkj+a3ZLdExLfrsAvXa7paSE
rUd6QcLX1ebgz/jtBOy7TjXfYJiImJ9PH/6LTSgyliFrH8YuPTuBqDmcAz0/uX1wQcYJk5sZjGNV
OWtxYOQs0K3EJNyQIbpud2aM5r09XbDwNtYBCeONcHsL+FG4FNtWkDE5nBJB6WBP8F/+lXRaHiSB
g8dtPcUSRPmThYkRidG+dOy8J15sWNZK3LS6jImTzFN609hI0ob8vyZSY0gbyFPmF2+RzeOMf/EE
g7Lquy18PVXeXCbSVLw84z0XMaZ/zCjA1MntiEvgmoQX/S1WIicxAD7GnjwxQB0hwGvldTHqwsRp
px5HZZN2wUfcFUgiSd3m8Qv/TZN/t7jm9tc/IKAtcfvQtLSIzevGynoiJyPsvbZX6JbwWZ0uI/jT
mTtRkkafuPmtZLAH5iXgH8QfR4OqiQeJQ8P2CkP3zKnLgmrptPyM3TTnBZJBhMrpLj4UHGZkKuyK
1/DBLMF1mKXOa3rbsRMYeejIw+mQ5soBBUFGRZLGSmTG5CHYPUGacbHnDqux0P6vyRNkOdYwpTmy
o2blWuyckamw6OXm6N/TxeJiDLHyTTqt/F20yHoOCMV2Z1JreH7fmQUaTBkVnvslpgqnd+wSu9Jc
TMjbt+82S3DWtko3O93u5ln9kmkr7gMgLAx7GNQDSS1XUKHHah65dvyNF6V8hS9tovp5bOC2lGyP
Us6TwiyWXzOMzCLu5mrQWPDOXpLaH8p5mDdOXFezj9yo+G7KNo2UHrExCQobZqvzO8lwghgDmM9S
S+9uqmYThM1AXXOLh0ysRR9yeKgMYoAyM8/1P4q2In0N6T0flz310qjoKJoCbtKHGMScdV16dJ5V
KJpy21jfeMVPV4q/mmoY1iAq5Dfah7k11NhS1vMz3Gc4eGvUKqplu0ku0PvvC5vH9A5tvVReB/wD
TEzRfPCr5GNxXq6h+sYRpu6Sn0asjfuIIdk+92JkcPJ3/Hp1KTkCZy3Q+PrneJcgqLg+Yd11DJye
LqzfGSgMyQOf1kL3sPonejK+MAB1jjsGsGDaP50qS/s6u+j1Irxwrz52q9LPoBY44Lttm4uRSN0B
QwvruBqI4yYiPIb7foVuBl52dCJRSMAZ5kG0dQhAzOJhr0YH1eG5rVun/fP/ypTfMaIzw3nPZqjl
+t6+XtLzRs6bfXjTkODVUKMe7Avg7OSnYus9mep6JwrvbzjHYZqW4aXLqHW4K93tX6xZzC+XMhqg
A4yZP2sr9PSDGihtcPR6fIXaBGT/4TLASnsxOVbIdyQUgbd5PY2mxEk4qGAFzoRQxbXhiNQSGMD1
o0yjaVVydTfbIgor/FNcDcAnx1NOZ+XIwaZxWdqALJIvSQsgSjAUUKbM+F6PzwOxG6Het6u4pL7N
KfruzQzo2cAHYc/vsuJBq/2OxFEuuC9ouKAbWYoARvLW6CZ8VDsLMfeN+1yzXXYRTw/uDYNt840z
aZJvMkFllVkafqHF+raxux1wOFemTnFhVKcH77b/z6Qh0CMz12OgftQY6ZLWYpcS2ePximDXSiIl
1zdEpp1CVdWQcks6y79xvYQbzgcK5U0bIRAvFBmwigIODIixOogXHfS6JODlG+KKFNNRw9n2jPYY
ysqZLq2HlgkhrwIwwOSFo3ghaJd75jHkcVL2raCTTOHV4TYhYqmgI6uv8jhRoY8benUyT9cA7Qxv
Bf5Fd4slQOFzJSobeWGmUCMMBLNH4/LlcpC9MrGSIjep9oGyob/IfhWmBzx3mN6omSP77rUQl+I8
Le51vhVIKi0Swua+M2ElMK9Mq3XTvYXH6RRFD+VZC9LK6Og5k6cLgYK48dxVAsPUVBa+5te2QzbS
dP6Po+fuxdBbUfscWXVLBOLOZZ2QO9niCIBA6Y1ejdFf6Uv8HLQL31UZDIT/g1eDBcJzsWo41eq/
KTCNp2CnOAyd4LKo6yKyNhZbpYvnqT0q/xu1FjSxLLkf8d44bTbhIywOZsDFaaLGwJ47G3fqpQCr
ufVUBcDThvldcE0vG0V/YeZOx59rsaU4q1bYxqfNSf/KuHFRUYWaDp7Rd+nEV3JrlLCsZmn5//42
CJDci0AkATH6QOAy4FHdPJSsZIbk93rUteN7wTXrisRsZmaloRUiF3yd4q3Br/MuXFciCUlBMsbl
qy7qI6+sDD8IBWMfwhmrHs6Lw7DaLaa/gRAP2OO1bJ626gcvPoeEx3/v3E1isvZRyb6u/t7RFM+H
pfJUocMlCMXbmIUioT+WCk5c8gWJXNaBSedmVSdR5j/2jV8Ouz5g7VuSb0B8VgVidOTD3jgNioFq
WryKpz3miQLHjDuTCHNk+WXxxiNLOwRcyazLmkxNidMI1UKWSZbA1U34bqempD2XYeYNitjRwRqZ
/0a4diWpb91zehrkYaVu5idPF8jPyZxCmqQZSWtTQdpdWJw+c/7gTFixCNL/Drbw9WOYsQCjHbs9
zkSD8z7p73kU0ZuFRfWJ799kkRr8uYREabeQ5y3IZgD5cFY/e0zf3I4w3LjM+m9zorfqZ21jMDmV
OGpLOTMTY/DxL5w7wjT7qF38ZKg8/DD7180RgDLrM6KgGi4rQkxsSaSIvm8Fnr+yjy/Boi3NF3oz
BsT7P7ig2K1qBnx+sQNNvTwo0ozbyvstKnog999WOVTj29zzNEfysgdaYRCt6C6Rv8/iDLxsm6Sh
daZNqbsUYwyklhRN0h6ERF5anNJ8XNuTXh10Tbtr6VisjiDG7NKElo1HN62nuLXRWWHogpa/fcX2
I51h+moR+hBUJs4dq/6zuwGlwdIj5VdulFNVyVZWzIZGD1dvI4mCZHLQUvQFDDV9cgIxthmbw4d8
2j0pZdDA0jT0iLd6xxsEVbu3GEkdzS2LGiLd0LX8cc33rZ7QCkCLiU2iWi0cFwFHMP38VeQYb3kb
jNtMrDgEa0EWa9Zvr1A8DQ5krYGPjGH5YbqHIIneZVk6imY8RdB14kEuugh6gF2lW7q10v3ssX83
j8KT1U4s/U1suKo9cBVnqGucfXgKa6zOwX00scRSnG+EVbWzoG6y+3MQGkeVnnbljcwQ9lfh7EUU
d1d73M0gIt1auTyu1Te0ECjQcqKbBddm2n3o+2O0TYFe07yri5EF3LReZlxMQvilq7Ensu7qI4H8
YVtBvhyD8hKghXC2OU9y9tsewlOC/O6H/7DIxMFouJcCyLwnRfAqB8+Ou1KI2tV93uUWXIKZghMH
s+ShCJCQz9qeNHHaNdmxzHU0QaM6YqlsoRa3nqqpW4TZcij/DevHMai2Bnqlx7H+qcWHABYTLN2S
XlrsohIlFftbxi50FfRC+cvTcijuyVR8Uh74sQzjgu/6LB1tdTeVUp+904XgVPCVNtGErgiRvo6d
l48EJbv1xqnXeB8Mx8k2Y+lIN6dx//I0vozTQTij/vCW/kbEdQU1oqircCGGlNSLAZhEH1hD30Q+
lk3lB4eGZwP1/3D8bW6cez7u7KH3ak2sXbXd77aTQdn+QqK02MLiR/q4SwEIrzUBeGyAspIyTCA6
1w2hJv7yxaUyIeLZnlEi0Y2SJX1o+bycd9b6tpXWDquWYNoQatQN4uhqm5rVOp30VZE2RWiK0akX
xs+IDfS9q/7ZbGt73hnUS6YSd7GeutUrqpaR43x5KRYQ/8PA+MGNzZNiMBHL3rlTa68KBDjdXFw6
V1xgyjPRHzByPBAqmMPYBoAPJKBhgBQqqIW+nPa1GZ33ocjk1VTGtPWmnTzYEzcuU66n7KaumAk+
GvqkrPefjGcRWe7myugf2oe5lvKTSpFITlTu533UEFNB5jPGbKLqWSXvvEr85hexVLQoyizFLx2E
wr/YR/WTKdLYfC8Lber/25ThOFD/oFmcgaxNgn+2P3Uy5sB7Too7JA4M0L3cvBIITPlMJOqU/Vfr
AaLgODRYJCLsFhBa2txkV4MyopptOXT1GJ53WvaZ1eG6xc5lTBudPCb6c+fNQwyZR8DPQeLn5/oL
WKU83oYA6GXT86dNsL9doXSbnlYphS2K+nd3tv0+SBgIvF7BM2uPxFMSN8lPdFZQsImJTtzPrvBg
GTaRKMr2hbgUWOvykU1JorvvZ1B3KTbymlIdWYurYija55sEwAW+B4liVAoOkWzQuiq27ycpEF1O
Sl0f4jF5RVwYPRLJ3lreqANDAb3Iqa9NvDU5BRSlfeIYMQOiuFH9qbeJNOKQcjTOJgjPDIou01Ko
qX5ooIHVk7fSadukT0d9v24Kgu4JajeJ3+053QQVMNX/q5Ex89ZJRlwo19Niogz02YxUUVokI+Oz
glW8kG4wqYm/KevKnhmAcMdhnJNCsUMvdRSDDu40asxPWTvnkJYB0VDPlg3nVjRGBP+/XO2mmEIr
keoleLrwSSf1vtJOruhJLxfY8loEI2dT28lJcowvNqsF8tKpTG6oA++VtgzxjVJEJpZqF5vf9koA
qYbNJmpJJKJgVjdapaWQiVU2PlK+2Whr4yTzBMYQeukKtzloFoeN/zkrIu6WIknuKsTUpNFY/By9
xrTzDWuyUPzQKC+U4egSCi5doNc5LVo8N+75rrWqnqGpkdnsk5SK/+8Y3tuiIy01PUcIv8wSWLzX
TJM+xCL03Un/OgFMsAxnBE7lDjSEhqE1DVX+OiNIojWF0/AZEmuC/Be2WDuEYDjhKyQaFECdNXMM
7Z+xYkvophQsJRCrqpyW7O8vzlUPohNM77oNWY0YKnBrj6W5QqMgFLXrOEjz6tfHDixc80IA+trg
XDegr/Q5lGp8NOS6MXlLmDckW/wRYgNlUYkvIunaiKw5am41u3pnjMMw0sBGQCb8w5G1uE5VBGWD
m+v2R4bXkGfbDsJOClp4BCz52yTL//QZJTOJJsbJ4L+uPlyTLfJYsuUzWv6BX7M9MU5h8YJaHrUu
cP9HDYDz97sLs2kMuDfg5PR5U8KCFNDAdUhVPB3/lF2koo5r/gQzbFWW5nBO6F4ylbQY05cQ4PlG
yQd00D/FQrsQgtbu5LjOr4T7D/8zpTUR9MqAj9x3ARMAsiCJ4WPzqtu2RrvY8AU4PyShBYPv+sYy
NYkkyputURVldHvtEjZ4kpXLqzMPVHnYzLOpbNvBfZCsKSOxZ1vw4jl+VWtWAwqP1coa7AU2UaTL
LMR07NQR3nARXdXjn93BiJtSGxlzY/wXL1TjRb7aRf6Mnoxqroh0z0pRrQuyaBbYR9K56F5+f8fm
8IOJ9XD48WmBhwRBjhNLh3go7Y8/oUlBL5+7xs4bcMTzmFr6Qt3OR9QV1TJ65oSAadm2MWWYr1K4
yQvwv3iHJtYtdBt9Kh8TSDO6Okwiz46D5C/44LkL9J6H+2AM5RhDUR+mTt/N44cDn7RQxQZBGxOX
Gh+t1O9TCDuleI88NkRoGAEAE5qdxMCb3DpC2tK9px9Lvl8QOxb+EdB1jN//ILzzvXiSrsqRNT4m
6gegfnLlbWFmALO+wqHQW8MUIQzKYAfIJEnRAjS35QU8XjWEwAcDPDYLBFPjzirUUaUmTYjTZXnm
wKcZtK3bC4pmrC/S4VNuuMkw6jSjh0UHTjSWDA5MVbFAwMf9lLAsyqM0YcpXvsP12bJ+siVVMsgd
/jRO150N0D6f2MuMxy2oTYP3hRVq9m0xUhlW0wZDkFEk8YVV1l2ARKWIN5lVMmyZ+ghk+0NaKEm3
Ghnii7l5sX9JSCFYzd3+1QSKGU2btgbB3T7kb17zQHRQPtb0IldMoDOtChTDqFF/5FItkRBkAtbB
xiJ/RQvWXiAUrV303Hc4AseQQpm2aSLz4j3z/iMBRaSeebvltp/ntEnXsWmXGqy3SiDMV7hfN6uk
SCM2m3UYOeIMySMZx5nv3hIjwKGdaMWQnsnYF1inuuQxI5jGZzOcW0OuHnq7UNW9X8MugrvLXXbf
2FpCw4+lN7G17uaNmYqr3xFJaRT0uT32xAWTUIspYVvJXHOimcjjoOUFb4/u7yuz+fJ+4XX1g0QD
tEhlHtJeci0Yaj330JLZNkXqfyuSR2pDFm+6rum+BztQJHqLCWBEnp7BLrcSuwOqD841zUFukpIO
3gc/705L7wcoRmDKF6vqud1yn5IcuzYxjcSFgdhB4ZSgkwCkPkPugS7SKCfCNiLZoNfRt1yL+yIh
+qcpuw0N/TOLgMIMtTOhkJTOEb9D3KfdIdRqga40xLq4sKuoVAHVkqy7UFimliCxOciBwP1cGhOV
kcjgwnh2urLnUY5Ih1nXCkbEhuoE3kIJiy3apuR9XxJ0fXkIWRzeiE3xCQzjWKSJzWePigwNooOS
+BWd/yDBU4qp3ucZwcBv2galNTBIl6ngcT9cAIdSxGtYS4z1yPgSSLCgqT7ajoo85kzsj1RA9zGF
sNqlsEycQ8Kh9tZAreTTQrWPM6b8HkiUVVz4VxAAYRlGa0m3Xk7uL99iGHAbQtHcDBiY8fG+e8iv
TwA7b7x8S5knXQFo/AhE8aivgnFR6oeynFFfn888ZxfWRS5MluRokZmXbFhNWybPNz6y3Jr7Sg4t
5zLHsGPKldv5dYVFRuajKTasBLGtaR6UyaiCyQQdTgg1dhvVsRqJPZJiW21PqQSwvceh/L+24H3d
3r0cFWelkFzsubk0j8sPMPyHl2ljtS4iH61TIWOPfr0UCQy7gIwI+b26DE5TlSaaIArsesuABD5T
yJ0z5DUjOjrzKlvGFqLTx8nyC5y0U0eH7Xi3/cLtCEgzQ+FDayKCz9vMrlsB/+sw1oYAopnp1v47
+D1lvSrT0iqHP2JUXlg5mpR0f0d6nP0p5GxVUX6FOFBaga742a3vo4vXGkhBIxYTrcRvV1uomJLg
Y+eD8fWvUmaamAGrxivc2rg5n+XwZZultZafU55ew2lJ4HzK1CbuDA1vYBoxqeXTQWw3jOJs/3IF
Cv+a3FsJBX46NirQquhpxvaoesflnNBVDxd1YZZeTJUzyxYB89QaMkwdgKReLwI/Q2QiNmw9OuLy
F6FTdZUs20CmhK9KJ53IxoE1ZxkCWMoHi1i9zZfJ8gL9DpkRMeTiiR0/Pr6aO/aZgrI2O9HP+b7M
5Gbny0tbxt3vCTIDgo68iaBPKYP+Ipn3IODVODtDvRyE2lCBYepb3B8rnWBAbWaPmgLYoHflt4f/
v1meer4Cnh3dTbNlHk4ze9qiOoUa6ujhBAz7oZBJGcvtWeFxhldIluT1qgHodM2VCK9HxKinlKUz
5KvqL+3ToRaEkli0RJOk3DO8tnmhtm/4hHGBUm8gF3Q4DEbTSLfofyefCox+HBocpHkGaqyBpPrE
qKR6YjHkjcHYNfxulm+mV58IWktXqzUHoUqAayODMrioekEHL1GPbJwLBUZY2ZYL8HZitI3TlBRf
eWrLhxsV3ndCSztYm95rtEEjn9EKxvwaLPmJMK8TujxIwe9qk0Y4LGdKNu2b+Rt08elbulJcK3Bj
8rGAv2cLQSCbqLRbHrx52JfwD2eKG7W0sJnf2i5K5OKJYxF6T41CM0nHDJ6oHNjXegf5pzUkkG8w
6X+Trrm17BlRRXvX909Bq6Q8y5exDME/GtvbXq6BTXTpk8QxTsuAH7/aeFbu1N0DW28tkJxMfbUJ
0e0iKMkagPlajgBRaA27JN/ecw55GdhcDS1cCZVTcx03ARMOGyYJBszTNqx4Ybmcanx7VW0km3Mn
dzhDD4AmE0C9Tba1Ig9CfbSNorfmKjQ6tnp/KROzFC/GU64KkiDrSyL1nC2meN9nvaSDJzGx8yWp
7Grysrt0uT+JzoMWfxYJY74BuijjMS7Winh6W0jAyWQNfS025E1i9CBCxMSuNRZWW6bpknCPPkEb
j4G4C1lqRvDS/vwjInComr1YEnNkOXVuEkslX65rJe6tAVSnSoo+Rw5zgFAgpo+Vcnbza9h2hwxt
lPbMrajPsTMqmsp7A2V+Y1yxXcyTMl507Cl7My22ghAuob+scSGHzYFGlrJfPMRG3HtnmRwgBlsO
32oe2QIXuAvV7QEDmj4TGW6DyRn7zIT8SEcBwF0nvrj3P8+WArmONLCdUIkEWepkU5oC4eqskGRc
SxYfSrhoSoF05UKYPbJYMdy+R9h9XFY3IMRn21UIbH9EscyeorA/yWvIWkF3sd4Acss/arputRBH
jqZW5hkqoJneG19e6r+aRWVCLWN1cNwNW8pMBt9bYGYrSJb3zcCcjLEb+5+DPl9HosBXM677y57h
Dm8AycTehvF/tV8bTT4RmRW7auO97VFz9yjV7Y1KsThbxU70Bh3Rs/r/n8yXIUHwACHxr/5SIuPc
wgxMYu/F45txM8g3173IYSffonmBOq8y2l5UnHNPxEJrMheP+DcnGb8rMDDAZJXTSnSx2ZE2fpCt
vSVZcurYQ1HlTrZ3L6PMazobWbePPqEyIrQOTcaFHVtPdHqewRIx446Uv9YRzQJLsEyVZE8AgvSh
HNWav5fKJbfgSc3T+GH+Iiq765BkMlxzDAp3g+GxuRG3q6MeodA+bchbAK0kzk9f8vZ7hHFohKOR
+sjFPC2z7pA/1zRyMkRn/Af0GQJ0142xsrxwheq0K5mgWc6IvbNKXLhxwMmzsryv8z6v3yfLVmUv
kFOYE+bOwhZqj0q/mut04Oxw0RB47VDfhrA1ClHQFZBAHxttpuQ+rZv4YdL7W318LTNWbMAdcGgu
HSOqsnXpb9S26AmK34c8KsLx6qbKEu0I6orHSpEZ/9bDIhYIT/wdFfCtU8NVlcLjydbGzJPoP587
dtu5TgSldgH+A1Tcg1hV8P980QI5QDQY0/IEX/q2tI6jmc473FOcmLDaHj/8RKyZF6TSdjjbd3PU
JAeo5sNwPkFBzJY3AyOUF+b2pOw3dVBYiGTcvVWGgM8FMfng5QrqVSRGa1QptuKVJFUuarZcYNIR
LnegKcaPA7yN0pe3oaoKjOjVmZzrd+/0hsnY/xbNC0f2b/whVJXt/HRroquDFtW+If9Y6MW6e8Yl
H7rl0i+q/+XDB+x+LGHohA9JU3vFeF/Qqoz3O60UF7KmmZWOEvO5wHy30ETW4oFumzuQ+CGP7p8e
6AFibmC6j5KMwWak06vKkpVyeCjy9GGOwNV2jUAuBOX9Wk/CES7ZYnwYa10YXEom5rSXIW5YNR3G
BTlTZK6a/L87VeRPaS8iYqeAF6+pRH2HOTMzBKNKaMDvn8HYfwuof8ONVWzWHOhpIRyflYxtoj4e
VtegzPW3EVbWzwsvgTm5MvinAFR7a6Uw6BU0yQI+IM3gs5Uul16kwvuJaTsJVW35mmV5QUHk6pSF
/7Wp+4p3goW5hIN5GRbAlHRlpHKf2SJGGDcyjuwOFQfrdJEWV+fabNK/8IZbi2jc1Xkwxo7lZg3R
4zkc9aqFpvtmlSZq1UOymRGO+8uhwlrzjJY1XocBRXLLq8+NLXw/r5Ph1yvkDjhR9OrPQPoLcVS0
8m2vx2FWYFtxU4U+fdFhdHO9EC0fUJ9rKi9sEWKLLKiovoM0/DHVl5LlagFRoXgxlG5/Qsmb6r8V
aqOeUQLbUvIUL+Cq8/SmX03LbovaaOOfxuo7JfbitEF7kuyfWQLiNZiS95XhmtBoQ5fCKktSfjAz
FDua6vsG0xcLHzfYBF+hiJmxjzZvDxbaW+cyyY08m31He9f/RCdzNdRW43XoZnSB8tdqLRYzwNzM
NdojsAx9IMJrMsCGs9Y6G0/yjF7jbiDFZeA1nZhGle798LO89nby1+UavIdef2rhRLaEXVxWeZV8
4yQF91aF/VyDpddKSvXyjkBZKtf0+e/U1gDWsFvDL9b7W6EFpF+3GxbxCZ2R9oCx4U/lLtJQf20J
UlWifGdx/X9m2ijpi9PAc4F2bMCgn+oW49nvVUdrx7MEK2UdGay0H29t4Na4zy/b+CQb2j8WuplM
a2phqKGf9jRe5kACrcxzuZTYhfETuzfRXyvIG0Dr14LamTb8uHKUzKY4pVav4xTzeFkJXT59SqJ4
1BqyNjI2a4G+/TWJfpCQoE7rROPhclU4puQDt8uBVkgXXPRDoNyww44zh/F/zvn31LtG0tDSykTe
9vv5LuhcvNwiH6yOI4FiuqP7SPUTspEnzfgk+YK8naBqO2ntmp0fJbhpvXxpes7/mTVbxfGvdyi7
MiXQnwQ6XWzEPPAoQLNW4R5jYnjD+fmNbBn/wv8tQZvhqxGpgelDNGx+XXZKNFnNT3nSKNbbljAU
Wk2GnxJbfq/dsDzBiXI4mRSlpw1BmGd1rFIdTwjhZBaE3swqtcPF5hHA7TLqW1MbDt5g0cY5iCZN
ka8Dw+MIK+yrNtWsF2NqfpXB6iPDBT264lpdXCxv+qoPL6WQICJHuxN/KOmBjqmb3SX+DbhS6k3R
WTUI4aTqaWkhcktsgMn6X7MP5H4TPtHlxSb6xfqSmicbIkIdfyvZ+12A7HB6zTc7WsraArWP9Mgu
k9MUY+wrhpoOV7SXC5EWFKX5viu/Fd4xYT3SkAIwLAk6dEFla84BrkSJo9o2kFhbdEEuwVbYWAwd
1PNCTHzPzXUPY0GjxQPd/IZEv8ItJCUCuDxCEqTEjJYCvflkjpN14jdnr99BWC/K9e9Nfibf1zw7
UtzXzSSU9GBWbBgNz9Oj5xugbtsMBN7MO4YUmINyljU6OicUwsBIVQU6mS5n7ukkUdFEcP4B49Gs
bZ859zc8axRFEl6Y2uXVfwxTDqcw/76kDSGY+SwGupp9UXLU79GRMfRnulDrYfZu4pF2lS1GuGCu
g9bcrYr0ZSJnipjid0WKOvZXh7fVOrTQiaf1uEuKeS1wDoVAUDy+AYqx8S1do7Xy5HvPHMRO9V+A
Jfd1iB26RkJHYmWpDYSX5lw6EH9Idl/54Vi1kacy3Kikn4TrSPpDKS2smAblVsr8LhvF8U6XmHf0
mCjxAcEuwWO+lhJj0gw+OTXhnm6MJfpTqPTJkIOjj6YKEugLtnkvlNqGR5ZbIGK0VrAT6RqtBPTo
j1GxtHpSWMzgdok1GusI1qFpXRbhmTUK/xOpLUldrYOyop4qdJo06O534y7qfeAYxHfBfEj0j4DU
uNzLu0dk4K+JPcvtMS9nNQXgfS6YccE4URJRkEywTRKDZbeKrT9oN9iC4dxI6XKynjWO+wZLfBrM
qG6ZIeU9obWLt1Qq3N8pih1I/Qbo/umY4Xw3aLEXO0tObI6qtNya0141JFItc/e4U1zFhhKUqbtT
HfV4m1aolnL1Rla3CitE4APiJyDcwscNXyZkpshiVR5tfrxqoFOodk9y/kHLNRcIpkDzdbXar8A4
EwhhMq1t/3RpK+7vnxh5LdYDJn5PcvphwZiHlfz6Ulaq95IcMwIn/tEniuDDDaaqU4Cq5g8nIGtq
GWYBPB1N4CsF4yBSKpJt0zAW9XRD4zFcIAv50iXiiY95URuDHSZfO7hNbf0Y1gXihLSxcdEyNaEs
7nnC31b4oZBmP/1RWaAxGYcM7fD8k2gSSlLMBZ2+I1H9IXcFj7O7BDOzjAYAGInW/2LDJLJvfrT8
qf/29gIqwcbSm05AqKKTJM75JLoHjjtl+SqaC7gHO4g8mNm7J8Wt8F3q9Ca/WfYMw+C4BlrDtwck
EWp2qSCLHsHVTAFNyDUhkqDs9rlRSGlwSosxBfYTPrUnYrl3UU9lP6FKerDWFVA/VJi8WVcWlMsm
EHRzEyLveaK/owbERYzwWIbsisnqWNvpyI0sSvbGjGmkGHTc3NKL6sBontBxI4fJ36VAWVhR75KJ
3f13s65AFP0OE9bPdiALOUoVMWsHCsWZfY2FQUQaXI8VGSJC24Je2sDc2JKJULStyjATu0DYcig0
FcD7YcNWwOEk31ICqnmcjBbV0iBwKCjE24YgA6uxHOz7yDY+4D9qJFRXaJURoD+dYjRHHCxd/X7q
dWfp3Y9S+T/SmMi54SdDJXZ/xtHwJCL+eCe/ABIpaWSUEBRqK6rWTm54KS1L7BvsfOBtETuI545O
Svp4aszyyD8r18jD668OzHK8bap5ZYpIVmtcbBPSz1Xz0fPuiGqCbn8PYQGa7MIAnaVOz+y3hP4f
f41GAnqw7JWUtYZ8Cd8bGQTBlLyk1y8YxJ7qUiEJQlVonLR/wbStYcmzimhOmpV7prSBtoVlWmWu
Ut8e8RU+fiLEzqLSpVgVfsHM7X/FgXZZP+vCIo4FKYdq1OaJfozGC0KzV0uMOnd3zTRsDRSFEkfh
l6UVXGReHMxPUrY+scXqPoIY/SDspEIvghz1SzzosO20qEridS29ZX5TPVVJ01XFn72XJysOT4ip
s2kfIt33LyuixaSHB6xgqBCghraPUUPWC1+zfges6LVzPW3sH3ccYEN/xeaOozpnL1AETaawMyVq
fQf57sXMWd7K8Ry5qqd23qLhPYn7a4CCBhHuGvdK/OB7PVcn0Tkqo1CVt/nV3pu6RDy+lGqs5byd
dmlf3/Nd9Po+FQQ0Bi48a0/lOh3ib8mqJDywRoWeNVNGELDaCHqq/Ce0ZGDHlmRHP2mHSWMnWH6f
Nk8cPwnrxXpLA1mDy0k3wKDs/AkwkFx4OpvYd8xOLFEE5IRubWg9c2yHnhf1e+FpWs+kF3In0FEy
JFhmCvrmcpU+lbRugvNnO5w+4v9VKQhG3KPvSu89OupW9eO4TDeWBTptjPRly2aR75QIOgTbC+0S
UQoAsyR6TPKj+F9YvzTVvme0A18s3+2EueZY7YjXLMthcYBXlmiWZe6zuwzMCWzhnUeV4rZPd79C
qT9R4Xt9SqDAXue9aW+ZfgvK/G8wlq9AT0KQp5hdGxxmkLp/ik/VtQTlTyRWaYPQ5pWSUmK/Vmju
6s+aEmNEKHwfmceu2hFAyT2NV+LLms2EVh/ivL37+o27fUg++OdbGqgo8dtzHS8LjQI8x9BsCyqw
s9V5dguN1DiinoOiWMP5aMFA80xEl8SPemkdd4NOqTymDyCEdCjh3b118WDJxoUgdl/phKoHoTl1
Nt14wfSK5y4gimENqR8XD/Vol+rjxqSgLpTggF25zfiKOafBNPfN5saRhze9C+mA/hdLXGmeChlG
SqXkK6Ty8owNWriTd325YgvVCwDt7f1vCg3QY22ealRxE9qvZwL2uad4SnfJAAuRNx7+FIVJEqUd
5WZPyiaifdiUQNk8/P2z2FtgcRZpBD1r6YWizFip0d+ii9Aqlazu1wun/tZBEMVEVch/1+5R/73T
EQgo0sTCBM+i+kEMrWWiOo+B6RqMs0G0enzU1rEsUpQ8GBea9TYHmcegKGUWyQRYS0/h4ylxWNw5
eHoEVZr5+Psm9q9uVvL/ZK+WXsDZX4tGJ3tfeF4C0HgLP83HvH+LTF8Uy/59n5ITVHf2yx6KWgIb
ml7z9jYInQFbFhSLOMfOUMfEl6XR5nsT0jcaNZ3ALXTD5oi4oDQ4CPCSEA/7oYKgTDBk58U1rAQ8
A7w24VTu/k9YlLkCu1giSjLcR0/BVQuum+smiZbEEfXD4B0FvKl9fCWJaqXjH77V/pX7McPnKlJx
Pp+KSvR5nbgyL6nKz/xlMAsW+9+nuqtLsJRrdSDziXrfzizsb6pA5jx7fTQoxA27X+IlfKp6iMy4
JZDjxn7jYj+fwdocp4hRH3xKedGhc+IjIZyZFuK/oCZRNThl2vRLN9IgHLaP1KtS96Vtc2SEGZ1d
rtLFzUIo8l85CsS5G/JpelsYZ/CcSVJrFoTMzamv8n+ZE5razuvdtufdqDXVkY75u9gQFpD7WO8N
U+Z3i8L9qvUwMH+hz+1TJjwSpVldCyNu5lduRq6REylN1bwJerC7B4z8lTvUFQdiXionRA/HBFsY
IPmGcGEBGwzN3TiYQsD02KfuFaHy2GEAxhAkG4OZcXwFrNfOGLdzSfvlAB00MWy/D8PdjosufV3f
KJA8iMP8d2EYmn0GdW3N2++jbxdldwJWKX/cmPNE760xV4l0w4Isc0mpsKwCh/E5uSN+gulsQQlP
nBtXAe/15HKCI15E8mPHijh423oYMwNQNFk7Qlj0L4PW+u5uH4Bc9g633QUHPXvRJnc5p/0WECLe
MUVLb+JcUtKZz5dEL3hrpQI8/LUjVbIVmm8nzLUt4wBuJ6ZUxscPwc6uIIupBBiHYlCiuV0XP0Q1
VgWPnZesZ4nWUFi640PsdvD7uoF8upNX7A9g26bvUBLzCceglpdHxGS7IHt1MeRoJfJIgn57aGgQ
TUDdOL4O8amRFK328AyynfyoLNY31DuVDK2P4nN7SseuzcGIA3LMNB8qNSR9Nc+5keGMRIm1Dljm
5uztdTvAZ8wbk7rbVsG52Cw0LyyjdBxbW8otqLurtZBQqecngWOts2it4PNzDKxZfynYDDoHxped
oAy0OGAXj0PlhGrwO+IXqtiFaHKbC7eMoFxpwi3+nl/GyhQ/sTgDdRwDyNELxFKw2JcbNKnCF3TA
HdZCTdcAuU/LTWg725IhFbUxoaXIBB+EX/9eVeo5jJ0PsaQ+8RZyAvv0JeNyzQRTHZV/fo80F11w
6TO3yP/RMe8WzCVKXhmUEMtxdMoJlO0yBImAuLJ08Lu0O7xkk/CACsHaG4hHsX+LUNdJlE+I/3wK
pWoaJyX2GqoszfCGpVeywl6EWBxcawC4iyIiP9xx0UPUbVpc6RFeSc00iCsDSBZwD/Yn86D67x5g
Ymkrm47+WOq3CNWg4cHJB12TX2Qllx0xMIJXV/uU3jTtHoLc8sU2WelSi9GPmFQFfFeKE/aRnXO9
sPL4uVjyQ9LjRgxaAmBh/AWzhhdK2AlEE8oJHHtNipVtTFRpikFSAxLDXPqj3DspsQFjMagFJ6Qa
GkiudxKAfINbqHyWMZBlwZB3Tcb5fw9WhM9lSK0Z9xLvWeOAJpWAfuFKJDNx4Nz11guy5mhkfwxb
xpObV/kRN4/UVeUEvrYAAMVa6eg+XYvN6klGx9W4AYCSUeUyY4fu+I6bjkJI+q2lupgurU2ooCOV
CeF9GTDyrc5uc76I+/yTkjpOzPcQslJZBJoAbYPrtZNPl15C04iCodkek8HDAG+vs27ceznVIH0/
84VIklzu2KbUXt+ucIkB7BJ61odvz0ae6G/mAln3F5Tp+fLBNUDghH2+Rvq8QcQcXC7pUhdtkAl8
LGhFzTrJoBFAUF/SVzSrTSIK7wlQK18PEyz++BjkD/fjdpVCU+ZB9c7/EI+8uLCOxhVJr29d/3+u
xhIouaMOOUKiQdQ/58x5Vfp1zwIUIdXAUE9mnCSBS4WIP1H527dWYPFq/LyMfEdpokzfWGjs1BqT
a1B1Nnrj3dAsHPO7uugOPXrPu4IaeZ+P4Fz5B+3cTPADYw/Q3zdGj4xbFH7g3L7AXJK5M81N/tTH
pbGdUTVmtPbzmXkgLMHOHpMbCV+zwZP0k2LULKS/94WJEcsK6UWKOiqqS0rImAroleczXq6Uqpyd
UK6JVaEmVeGj4fbXwbTcY2oo3Bg+Xa/MjqP9ne3hTEPoSQ5kfvUBC7LQIZxPgOu3nzFUIM9XdSrH
LBktB79/KficCBL4PDvQieJs2iGp3mdFKc+acwtw9IuNx8ZtWQ042/QFKw1rfml574YvneudKHIv
y+rVYx/4lT3fTvUAlwkfJBkc9vLH5qnT5bm2lHK8uMLzq1HrSXpJO3qJr6WGbE7A0udgelnUbPKt
h8IkA0OCG7FOH3Fj3ABm4pSSq58rVWE2YTuoOkh0oEG6S1ssMqFdS2c1XL4SIu5LtNGTIkO2+T4f
4VeNPJaRILB3antlKRRA8QJ/SWxSuKn7CpXmbKKZumx/2ns6gaNce1U0t8QVDOi2waGQX2HKqUPk
skkSXaN4ox7XDO/lDdeMj+75AzTtGdJGsxDeXio+ukJRbNw8Y7cDPNiMktdjwUy4H1qtSm8sKdJ2
jQx5Ani8Itt6QO/x1a8RwC73Z/jZjT5a16NqXbHfh82pMheCEcQNcweY3GDrG5u6LTuhThjo6Juw
PzGZ2GY/7JjWS1JJO424MaOICd4JGLvbDR4cZDLjABRhFignrkplgW2JawpK+B83t5LV7KbdhEkW
/S6v6JOegS+vJPpXIqjvUUm/rlFBKCPUivACQhu+LkBuW2kp9mJoOVSa+oSc3zGY+WdqHPpau2yX
jytHu0KBB9FpHnjyKFegw2Tf62h6/zcex0HMFhcZrdyPjs45ZZddZj8aqbQKfqmmlxoJqWkKNWFe
y/WXReMNROhk3GYox/1n2MMBw64GLYFbkNT/A89lKDHN/kssdHXxMNqVewFeeJxnkFPZhXHlq/dG
301HoXzoC/XQu7IWQLF1k+aNWXpXHU03H9Qoy89JBpCJTcOjoLeRnjDucCEc0HKsiGtaybX2HSKh
Z6Ygl56me/7YeKwf/F2o70vXr5NyQrvHxX8uJX3ZxI1LlEgLsllT4/0QykaCxxPSz8Ibj2uqLKmK
FakO6gM2t4ZoIcMsnSIGlZg41FKF+6GD9jxxHBNDJfz4nRQRg1kWlEZoY9Kp7Y6y2Y68lwbWrLzV
s7Zyio6oR/k5Bxoqs60Jlkj+teXvNODaJPPjOzhB+08fuACiiVH/vry7YRc5HvfrfRvyu76elHbK
hXqyh2u178tARx+gx3y8AxWBTcboAvnsn2tCJ+ECcb38+Q1KNzVUpIlFdEEIVX//Tj+i++d5rVrP
hoyN0BfvBmQa2rJHThU+JHxO1ZbiatkqdfLP45lY1m5oda5wjG8DfJFvC35XYxEKTZ2vFgqIMorG
cPViZPn2DAt7C/Uuk8214QHf2SiqOOqAJU1uTFKIlcyf2QYJ4Aj+5+fyw6es4GlFxnPrAfQ08u3R
zqzquaW9LGCox30btSJte6BIc9Kuf2yCfbVcToGPR62Cmb24LdnA0RJzTsv26NRBLuAIydhtME5A
8s0snwjnbRscAkP/r3UEQw1WL5RWVHrT5tJWMcZHpbTlmF4MqD1d/hC4sb4nauyBolXngz7ofOIk
UEWUgUnpr323flg2YNXvRRJn0rKlv0cUEQ+J3B2iiIR9RBd30Wr9AedxROMJHes4su/IV/0PrDbH
43KB5SCnyIiYmGC18JlEu7WQOQFV5Zpx+NRmbc4TsKmfwEzq67Cmm/ONs2yq5cFwcO2OLDfZlksc
9DsDvayrk5okseZqns1zWL7v1jxe73byB4CCw8MYp5KPjMiXUqUtYILUCNi2SfRG7wkmOT4YfT1x
CfNYuPw6aVU1GkkVfJwc1EV4hpp0yqdkaMs+BqqPgeOi2iT8PItc5NS2nm8gZqluH5VhiOKjLykO
AvfQ2pRCtqo6baaXmCp7J8uVVpM4jOIkoUBgAIzqXq+IbfnHys0aQMSsKRXUjwFxMs1c8orLKLPe
rpKPi4RSH0Vv8ioRsp7k9sURW0ChdxVVnMGs0Q1ATiXXeDdjUwMcSwcd2pml74Krvihf2lV9J/ar
jzSrrY2ghu8eoWz4X4obYlVcHjSvIOPWd4h7o/uDLyu36cLxtSzny9pAf7JeDSQbRV3A1EIMXiGW
k/W2gCHk0Co4jniqhFQpN44VHeBuHRCeMRp5Sd1bqWQCKPGpe4tNYLOgxCD5cJC/R+xkSv/e6l+9
VV5zbWvjkTtV42dOr2r2OqOjFIL9YOOCZ1dqSyLhrTqz0XQ5OAYctG6Zi8ZvBQBYYTsVc3S3UZgh
U+Ss89hhmHng+gUyAnkrGr6v+sTdKi7ogVmkw5Stkc2bqDsR+fmn8fEpweC8MSNuoCv32HoLLPQx
ygIn7JzGjLF/18AWf4yxNPyubYzBIkkg7+92v5epDK6j/K5Bq6uQiCw73xLUdRm4OqbbwuZUUHQT
oShhrGa2zi59JKNrj4pX4hwuY9ZVO5RGEQ3R7AMQirmJOAjKnswh+KvM6g3XlkhOiafaD02DSJBe
xdsFCQWDjfSwaJkK2NZ3COpP5HlHeT4q2ORc7Y8h8ClWZMBxjtuo0QZeV05+CDghzKWSBAhdoqxp
z8V3V6eg70ikdnEtRYCQhc2b20xd3j1CmDMd5Jk0qI7wm1V1CkY5Fic+6cel3ELmtLfViKi8VdHh
3HATHjBmsn2xAnb3P6yv9u96ust6Y01j12OFsW5saVwpy+09uUmS/iKgPvkWCvZL02AErJPVwj+I
OHmj2WTlq5ESVRU94XvP235rUOvjrlOr+gJOn/Wc/9fpA3QiNnPhuX0aEp8X7byRE0h6XWFxD+ZU
EP1AJ66a5iDTPtGb27s0rQBucQbGTxeBtP+80KHq+x17IaAWpCWWauS99kATXyvVLaVP5T7ryt25
7Wh//gDWfyCk/rQxuvRr7hQibt0mUx7npNQLTElAQHI2EkSQUYnkJLCgEmJLHbYz6f9NjO1OsDTX
vTcmRlt8HNOJvnAJu3TmzJkrqA1kD5Qt0U4r5xPuSglDwaOfIPhmJ3Ot/liCX63ZdQJ9xRFvfPij
pXjWGEOa/Ow3MC4kQ93a0aKCeWaUTvesx/KUQ4q0JwLRKTaqeiyWLTFbPHo2H4lumu+ZCwMUv6tR
Mp3hSk0KFSLN7um97m+pyaIMNd2TGNNLu2J+qngWiduh/EErJ3U82sx1KxmuvvZHYyQdZ1q2aH3a
Ie5IL10TYcjKwc01tDfb08N77ZULm1SDynpjdbu3fbHLMEatbKpgKlBqwzc540kmYLFqb//0eOKn
B245EBRpJLR7uZaxudfgJkIEP7b6+cVG1KSiLQ5JNu1L0fAt9S/PFdXS1GToRKJV2FgDmKxgmKRz
6pR5K+pKcyglu8ek6vAj7IH5KzHrHrX93un/KIeJJLEWS8xUbsFpUELGcXMIbckCpB1ZJdvwjxBI
1q4tVnn8E56tjmV1K0z1D331yjUoK1AvDvIVwg/KaPNvAW1EYQFBHx+Kj7jgO/eBBhEZ/3Trnt7I
lxyJ4vOcoRa08DYGuNp28XFw9CasjpT6gN0xbRl/tdepQLF/X8UTxRgiEMCkJdrmiM6pfm+qtaxp
YQJDY23Ynf5Cm78rGkRrE9JKC7PP/8A7ukSYqz7wQUwB1yYXBHfbhDA2uCQnRQuIgvDB3gST5+58
MBYCJKMhkETHNJMTO5tSggCdIF8No5bYqMuYA+gucmHrMU65SnN6MSBmhjPjgd82qtcdg08g2pGA
jX+ycYCZ/sO7TULi3tKqdcBF9RazbXu6PMEqwVeO4DJNyGfJoqhzn9JfiAjDUSSFzk/jwTNtiApt
jpjBrtUgTJnLadZnFIPUEzrSQ+CHO6rXJf59IhmjLZtKX18WJxezlfB8a9qx1G5W1Vo8CVwtudJ/
sTC8feAO2Aodp9V5b2Amngc8T7sbdLNUriXOo/jEetLx1uADBht/vWC8XGAZf4dBMCeLNFoA+n7G
GSgEU99/lyyrzdE2WAjQCJCs9zWK9/x74kKeAlxSURz1TqSGAYp7jcl80X+CNGYBvRbas22RHH80
CEWbGwEWAHWLovhm1BRYKuQXCeUd5nDmjDWwdiC79rzAtQ9nm4NDunVpB1P1q0vurDr2EeBRQPyq
jqYvAO9aOMHJvy7vPyKCgA5+OEIKbXitrA2kjcJ4JjIa1VmhU3ozkx3ZXQwZVdRfLEye8EEJrMY9
4jW2SsV10CHwdHhpE99yyAVcAsYnXioapXz80z4WEXNnFPyKQxJcnd3qNKVqzlb6Apmb0TNaUrBn
CBDClQOOWQsSIcxyXYQMlKuFuXqyMu46ejmNNwyKkQLhqDYpw+CmPHNZkCMUp8mbtbBa3EwFf+AA
RXYnbsKQSx877JFXv25iSTacF45QkYFbNwvEy/oxWW9kwOJX+BgGGMzvByozciFBmrrwRr0rbGIX
b7hCLgbG7tGIwCb+iNB/jPQqCwr1mkAxr6ACypEJ7VFTeERiFzoB6D55fqLXKXEa2m8fKr/1eLRX
PFJBEwrMi4PYIkDbNk0Jmzovydk1XGSFbPtZe5mVdud1GD4++IBNvHrda19Dc0FwK33vjRylYi/h
dKhm6EL2sfY90dbGjFJ0iQv/1gTyP8BinAm5vEEvffnGQs+ZB8g3zYIyjSQXRfHm8Xh6eg44vEkP
UnCSiDliiSeXk38yRO62eIa4cZhSTQ/DdppQ3zoruTPnHZX8WR3EZjtld5icFrEXOVj25owMLClY
bvtBsoV4l4GeLrvqOKdFUe2SvcLYFONDAcFCZwz4sDqBdTJdZdMnHSGF15RfSLIAVsRG7Da2Jw99
RXF/Qy52Za5CgLcfK0M+ZJGlm67A2fwdO8IiF7zaoH0UiJ/aVsghPYRwV2fnjFp+1t6aISyWSbrQ
YKu3zwbqVBT+GlKeEkB/CbQaHmwXnixG5A7oJyWVA5MKHz2EYzn4/ORzLAL1P2ETcJAhuFuBqvlZ
NKl34jQ0AK4GhOe0PDBdwU53yr+tzEbeJlLeQmzDvqmIleZex6hZ9kLb47Fm8aRA7JOVa1Lb5WV3
jrOsej78qExlzpSJUdz8AgEE9FsEuLz7qAegkHgPTbwiSLWdu4uT+eoZucAUpi0w17/vhj+GiYzb
w3qRsA+MJ9MkEYbRCH0rR3+F1jpja0FDHH1Py/arHCcX+UTL2Y/Xq+OVv0otzIyTTB5+KrurBNJB
7MVY8JzBOSLjNqzmEsjjoRApJjv7VNnMIsXTKe3tv+6tpjAAJchjFwTTCLWH5kh+7d9cbz5QT3A1
NpQBQ7vxcYf+3IsLOSqiXKbg+2o5ZOyq6FBFoR/78lfTUXvcLouAaCNpIhvudAiQz/FtptG98Xfc
HBNZFYU+HjndyAETUTB8dkgsOaMj/t9uqEUokNnKaaIrunjGuiocfwOTSZgeCNJgNgYChNSTxhyk
iF6pF01DMwvuNTGzwUgRNuRVWxZCg8vKjeyy+UlkX5poSJGTzPzJhgH0n3QQgE57+LgM8AqhDOqK
VhdmLIXecYfVnUCGhWhzpS/WiRiz7g8I2mHfjmU28hMZ5LCMMsXjndpCFk2pv171UiFgamPSwk79
L5yR330tfp8DSAtguSfNnDgp4hcFWqiOryXJykDv7y0KLI6bJnYNOF06vATpqkrxnpYhRrhXQxv2
rfoiHupBFJGz6sgcTke95+KNhZSdHmDFoJFIvUR3D0vpY8MlmHG7WkM6HDORKY6I3fxwJt8ufk+0
DLgC1S+5vwvEDrPgtEOxSkocg9G2RiYA9aVmRFJCP7CAx/OqX8XVkUh8LktvaCt1ONM8ZalXvEMJ
9UweRfgukJuUgr3viuEiCOJwe7BMZ9p9I5L5lRCwuFLqH0HesoSuHwwqe6KqGiYqZZ9u5fuVTlEh
j4iXMGM+sCzzySbt/AlKJKhxzT5vJKEuKZyq4EBoYndL0NQto9sVkQpn/NYzTNz6WcDOOoJokp7V
Ujmxo3bM9OIh7AmqK5iYXDWjmRadqK4SMLIwg/UIEJsHyXb3lQ4B4x4CXp1//g/6yU8Tu4oUnt6d
G/G1eMk3zrnLjk3Vqevh53FvhuZQ3lquETsNfBaXNzDoeRyRx+ALkZvX9g8qNSwG4BkjxM4emzZO
gMpjFsMEJPA7+K5rhGd4q3DM3Oq8pIS9rdBFX/7wBThpj554ZgK1CD0XPgYg2y/W1SGWud0sOpYp
7K/wgBm4nTGahpZwtVxj+fgIjAFxqJD5ii5Zlznlp6XH9iNJSM6QwPPq2UNWdsCE7uyPw5mC3jLy
4M+1dClNGIFzgYz+ypEANAYZH6F5TENuUia0Myf4k9ipE2dg+P56DUkLkcQTUmCetYUFwSrLEDII
v76W+GjaA/QY6D9eVwdEnjkWM532B4QcMAEC5OqAXpZKsgmXf/97/bFTfyuosZDcOPVEmAyzQfHu
bNDFMmafbfTnoF0r1cxni3upLkypbsI2hwK6HAwvKHesHY4goGwBcR+l3HPI6DgpV+s6fZiN+RDq
tG47bdi8wBep0HLXGdTxeb1AHQO2I0co4RjrzLiOaJMJyj717yzwyHA6eXipb2oHlQCrZdINmpRE
Oqrr+NxNYWX+VeinABp9as/YnfR1z0HrweXen/F6p2bbiIOZ/k1Tqfw7arUDhWAoeabijv+dIKXL
X7ViLvnxir4W9eMnurEuezKJxuJeblQngakRcP/GEzqsDZgafSZ3bvH6t69Fk9F3M7q8CA8dzTnS
P1upJYjtV/CjdFqL6XEhtrDyf04KUyIJAUw/dQfOBeAPSPl5SXl6qbCXwYISDkDLGDjozRtcDCxc
YWDykw9r0mBymsOpuEwwwERYYhkYXl/hl0Rr/qlWq40hAg/EqCqxIJk5UzE/Oi/dmM89HHQf+5ii
ifdBznYhB6udAlSxKa4MmEi2tETgMufxKhJ4ps8d0OEs5etUoZoQkgdlhejC6r/E75zRrgj56Wxs
xrnrSNtErtXp+GETOor8SvttN7F0Na0vM4IcDIyBAAmn4Ubn0Hq99zhCsBFIq6Fh94DThoAe5q82
90Ei3l4r3grvPqPlBeK3LH1Ckx+pLNouTRZtbjObmaUIBfeOV8kDpVdu9HK+WcbNPoLy6gvqTcHS
w7L+EQN37Q4N/ghuXAmv4tfFsc6JJ/ubGy4i73tfZCFuNuCL5x1BnbkuNwNQM1c6+XQvtAeGDQOU
JK6hNM64TS9at2FHAMI1CHEkioXkax3TDllYfQx4YdD0pf/9Ym5MWE94/MgBMfFEnUVUzX1Z6fZS
NruGJOc+Z+jlGIR7Um5iQsondwnJrYZdOrGJLaSpSK5BVNRd66jVV3Oa9wTa4zO4TEi8o64SzWQH
p7Z/VCMX8wP8RhRiH70EIG32yD/pquz+QA4zzKWHlGY1zBOqHAl0xb0oLUm+cfnmHnqmHDTfRfwA
J1XNhctG6wDon+oEI1SSew83ALXKUHwD/lWgp9m7ndn3TJs9X+t/oEWnP+TeyOAMNKgoXn7LmaSa
Z66uVNo0z8o3yt/3v+J6XqQDI3Fzg7ZspaAzwOJPL3O02ClqVQmINqiJm/OPKRbe/V+Tb7QEta3r
zq6BRBQysULFNMipOXr+nVz0MZpHqEoDh5ddT9BgIwicywxykHsAXwjl/Yti99Tr8u68+g00Zr3U
1xSGAsptRxf5y/TsUhZNLQNSEAkLHX0GfilhfJvQl1vQVbXNuoc741AEb/rtErpFlgioGo0vvcwd
UVVb01l2W9YB1f367H1WUevJgTp4/Blwll7D/uKXn34Ooblj2mEQSo/7i0ewZ9PE1Yh2vuq0lMPI
PFo9/i6hdHJtwm4wOI6iN1dKRQdTA8njmKO5Vnni23Dl/W89a7Tknsw8/y0i/gEpC1u7QWClJcKd
A5NJ0K+2rAsTTyi9Ki7Ql75bt6uqhCrnDhivkBTp/qW9wYKv+7uT9AOlAoh3KJplRO3+KN82N/c7
GODrg+wHog0KLxFrNXWfN33qDpu+DbVB3AkrsZsKLSOcb9vLmTQDuIWNT/xU1t8PIyhW18Cj6Ap9
pLl7vCa3ECOABSP9rJIGKKD4ZBMjiFE1ljEUy4mS92RKf6AUysCOd+pzLbDgtHaih7maFjxT/6c8
uxyTuShiYNB1fjj4y+sJaX2pzU3NAELbMmk48lvhwgkigfpoOCGD/qu+RjjXbYYNge/Xib1paHZ5
lMe5fJ8WwJS3ued46QAwTQQMXwABGJigyBVtUR8sQ/Pg3/PxR0WIwcc4IRkAQjVnS6cxvB1A5yVy
y9NAc0WAU7Ux9qUgwzdDVyndhSUGTe+BsE+ivHhMzU1pLwLfkRFQQ3x70AtjY1+4cF0fIV8qxgRg
9ufzeejm9UdpC1WDodmt2TD8gidqnk9fWnhtjVOo1w64n4v0tocpRg/qvFqG1HjhQioVgS+s+rmj
qHHCCrEPpY5sOl5pW2LE8ViAaHt12tsFDFXLvO1P1IFlMn85pqwAr8SDz5qYDU5NLv+qcdn37WeO
rjqCwuMOEYrlul7LHF2c5oKBY9F6A2wuP+1YWjWS9Xegnz+U0XiJeoEu8MGThebOfNeLHUkPrNi8
akOGS2lnIRjrzU25Xvj7Kw6DzAvke5VL+EpVnyreAbZICKN/w5m1mKEaqCEfm+BK3To5xuAVBthu
uCV3Co/29e+fw+03hMbBYd6LPS2RqFOBFYLRkv2nxOieAhd+v0qJxhjnvNPunEWCwSED4sslp/NS
kBn2JD8LS1LrjT13LLMoreO9Zvz00tcIlK2ukLELWTpchLNZD/YCB/Py53IRAwS4s8R/AOPPtTZ4
fk2VIVPIScPBZxLX5B3qGJdavZqij9VbWgrQA1PLR9Xa0I3iZRoR31E9ktp6TAZmRf/lWjY04G3d
JXN05/IGo1r3KgpvsVQ7Iy/94Kqfz3Dw7gKmWR4SzGbyLAKMwvXFm3JTu7YDEMBnjTXN37JW/UYd
+eeo+DxbkaWKd/5CnlQ+v8DGPZws4Xc2hdgcObpBH4CbTijbntc4ZsVIY8t9/h0sT/0/lrfqrehI
Q0fLjVrTPna+S4UJJ+OFhu7dUUf65ztfKqJly4pTtRrBQI4hH1pAlLI8Sz4ktVl+90Dk/vVFnKO2
Poxf5vjhTMjHSsTqFNOzIiDnSPIgNNNzl08YHIS8f9vgHwmy1q6rIE1kG5AsrplNb/aserTvwrZG
DhFW8l0El+/kPDzJaO9vLwoPG+HJ/Mpd8FKEnaesn9sWBvcAn2Uzg6H0ecdgrd2hzVxio36SDobx
oxBOUq0rY3G2uYpYN4F1EPpBm+oZvVtmcRg0GlE35szEc+QZoBQ05SEvPVag2ToQ4aWxptJYmMrp
AtB24oBvDPHymLJZCfG7iKfT8NwvWgaS5UcE29603e0gf4Ai3zRp3k3UMllq7JBFmDGNVslf7XQ9
VkoUuT2TJ8U339m6ZChf8A+1KVWlZCOfqXlveUSDpjF9hekHcO65edOxlRZobkJQK4gddDfyDeWn
ZLwSNBxmW2KlrcAJnm5889oFWFvR/hRqdZsNFwSZyoIPbYAWpr5ZPhsxIYxyM8McVfoKOXaoIUpT
fG0KGhuP/IZ3zxfYW8kSgAzgvi6gp6ObDbl7tQOyEc8wT8jeKOF3fUODjmLtPTA4GqpyEjmj37an
Nv5D2T04U1Gdc8/skysgO6OneIU25Ist3vaD7tSwVZ+lpniligI6ovvbKKsI1ZklgSRf8apZstIn
3HkWdMHPk5qyCH99DKk6X0DuqPJ7uzGrPMPa/H2vSe7MqlVm//9pxrQZPjtHKRetuUQNLfO7e0DC
QdPiL/rFeaZL9in1hf4lEU0BnwIcQyED656PAdd3FcHD67y66cD2c5AM4YpmOGUHz0Cwz+HtCjgD
8ZsgNdGrM5E3xv+HFUhvfwKb3gc35qQ9ypP0+dJuvwmbkxYtwhPBEHjPR/iMCAMhDMvQdag89Mt3
uh60fjhIBG2HQOtpVrJE8htMn7SJE5GxLrp4Xx23CL9gwM3t/50wodh62LRznaV0ZLyLRVYn0MY3
imn0VYhUOG4mnQP07wOIYGwsSuif2BUH2QT9C+RrPmlyb3+dk43YaYb3b1RH76dspz8IOMVf0d+s
CsxVVtd/Rbkwh4OEP1Kxlpw0eCLdmUwA0pBwNuiLBNjptnswx1XzyboC8dMMZsJ/CtKXoMDvF2kO
n90jLljo2vKxtkA7iRWPtZ84QIeZqboXpBJX1GsIAeHRWxUGHt06MIkN/RIbTfNdF4nKZt97Jtqo
+TuVli4c1C9BT17tPOoSix0ZcfpryQVfiSv9wjJhKPtFDX7oKxPvqWgCyxvXPqZ+bg8LkJZuIGEi
nVVHusnbVyNSwDENZThz9TqwJP0XlCgdCnYOuhFJlJZW4Vq4fpI42LxDTjyCmWJOm/+2wolKXWlE
J1xbjG86p4R86mZcn9FF+bu7+bI55hf5V2/HAoB9PEAxnObQ0XSvs44YJQVE75pK/ga7ldDLjFt8
wJWIC37ppfX3/ozrvtDDQkgjoc3CD1ikaM6Y0Yv/0Ct/2BLuK9sPNuTuwFARP5QBuEJjnIZsqsT9
JpBdnKhlBeiwSwI2IHyui+sBStCNu+/giR2k/arLBrUpcisJcSS8X8q9xbiWpJpjY8Xcc69DDVEO
lX9+RxzkYEzQbdQrP7U5hwWEXHvudnECaAI2Miq7Zr1a6oQ+HTQo+cU10hk7lRSHKRCoZ41iumzV
uo7MjJeqk3FYgMJz+lj6ATblMzI1r34MO+/LTU/jDFjkNYnW9lZ7tZy4M57i8WvpYHjM/t9FDoNy
ZSWGiaGQgsFM8Prmyswpdk2Nc2FmaHe71SyhmM/a6v78GCNMfqV7V14VYTZlJN3UAC7H4Vy5gclE
CCvG89AVB8BxCRv/omzThftpnJZh6qFsfbyysnasB9vJFDXtEydAkkJZj6RYxoyAZHtG2sBT8HcJ
iAntsYlxEKWIoLS90G3CqEse2a3+pTi8d2m0uX+wpMjJLLb4fckdixYiyzhqqCE+M1NESye7CYnp
EGyyQ9bq0LsMv4wWJtH2OH7/AsVB1knRsIDOk34Gm5l5a9L5cKdptaEwMti9pQ97dwO2TFY8Afkc
dhm+KoBMXXiD0CCJJTENo58gM1PNsaGv4Vs44O8gLy5m+GxTxrgXt3X068ozuQqW7wUMoMwiKwpm
z2eMZ8L7kNpb03mJL2yJoRVFRYjFywpRP+ElsLKTVfsbTkYdHDe8H87vVL7i14OAlfi5/oyZUcIx
TyuElN+QKarUfmnamGIxkEULvaGQ3iiX3Oov/yIQ9CITYMrOlxXzFyzYaYC9+oXllyAAfUy69LMn
Tth/Owxa2lxq3Y8wVez9bMk+hP/h8ttOdKYgBd3LFvHMgg0Po4VF/saCByN9YHApp7znD1dHtdgA
L0r6CjRkuc8tZtoYXfn3p16iGy24lo6G4OI3XSuD/bxuiExpjOycmLQHqPmz7AWCbLxcUUQBR+In
/e+lJSviUdAw7GLGY7hWGl/uS65Ih2yJYKnvdRGRxAr1g5E59v1EVU+7gz5/bQ7DWty+fDXA22H+
GFZBGcpWjV+Si5mTPmrQvWIgNrrmLDHNiIaOEd2uQbW4XBC5e1cVb+CbvW12L1DGXgJhFODNhJ4e
6/VmHau5+IlkDLT+xe9OZNuj9i/hrNq6nJVCpH/+O4fA94U+i6M35HBShvgrATULSEA/D+0WGsjb
wZXgPHeifQ9PvGd7uKCW0zebS0zEmpmeiRQCnl5VRphpk19BpHERtZc50y8dJ+0TOv2R/JLRhyiy
h270KoTC18aUT54bBbYX3k1ECBuoCZM2qOFD2IducNI3lFPJf0dUSUPfTAItattvh79kkPHj6E5V
zNQiN3us+CBLezMijrY3QdIN2vsq9wxJg30Id9K4dU4578WSD7yddep/Idv2gIDAH0XWmC1sYaKw
RqYTL1cFy+yLu9WrMQ98YHHdSwJo6kE2Ly/9OT0ird8KLxKyAak53DA8Ms9YnOp+wp1R+oB0FMvv
cOWJRy8aklVKM6VDybyTkU8KSAMswyWBz0VOirGDCuKITFzEZoP6Yq+gNkTppOYRSb9QOjclYFXM
efVU/cGZiRjJVrJuxjWOhWU74zL0Qra4shTp/CzYu1EVFEDwr26FHPEauY3RtM1fxvpMdoSLD4uZ
knY32M4YBmm5v+12IU/s+IKcwPu7FqoCFsu4a5yKW7k+Im7fYC48EFJFQ30BIALBt4PX85yG/DcT
D0dhNRmo/Gfx2g2O57F/Bz6uXqOVx9TifkhW95tubmocTpUsYWdeFE5v9su6weDNcHTpFu+54bk1
4Bh80hrpMFP0Sj7Npq1lF5PrAvyZyeeF4SNL1MeYGuNlVNGdoPdvSCZ3UPMvFiZcrXe3VeKy0jp1
v36wLSXA3l/d9iomJx9EvZOUzvrsl1xpg4vBrDS3lWQsyLXO58UFBm7AH134htAuv5viGdVkeSvP
HpFfDRzCF6o2ye47JUzBP9XTcVOA/kpB2zkKepbCOKmnAp3As8+KdoAA+4wCcGhf1WP6QaMEdcfx
UBoZZWSguVMCBTRYIKifonmYirg0e62SDL0uHCgvQvfCSbgZ2bm/txEWrMEvbALFpcV4nSJtsq1m
w1blK+PY8f3SFtOKecNljLud35cKTcL1UtDDBZq64nf7/HZGpetFPIR3nnOHyEw9y5T/r5eblcVr
sMfHD8nVa9gS1/Tyo8/BuszQ7xOPXSL465ANLIUMbe1s3A0rOZvpwIzAvo/iQ84xwHlHyyM73C2D
uTzMaxfIoesYdycJgV8hfq9g73+Mce881VfdQxQa0VM6qdnkaXsE9M5W+QS0Vc7OPv2mNQNxV+HV
EE4YBElNIsPPOLl9UmDhrnDDyFLphi9rahVKT+flQggQCRZ9pfq+Q40ScNMillag7LGrwd6YiC9b
tlb74kvKGm/7Ry3fsrHtlJPBlbKz8OipNVmr03i9Svq/JgpHwvE2vxW9SwDk/k31bqL2TfHLLI/A
uOlcU+Mj7HGc9Kmu3ud5wmNnMMtQjKdr+NTAwJTNYv2Fpuh/yZfipx4NKZ6yGyyXUZx+UUBXlRe9
9gX9b9zh+8uRcm0Rvu43jDmWxiGWlkmvbBDUh5tJFF/1zhiIkVKGCeuzYmVrhrLybhBBI5Aim8TE
Pd01EIW+TRhcbXgA8Rnrz1QCoHtlTJqj6IPsx80jy3fIDWMRZjq41NJjUwSQxQbrYM6/EB+DeTWE
WSF4s2IiQWMNEQ643PBOi4ZVcPple4ojnYkZf2EwykzpRcoziSARhUETirhy/OYFnJEFYVerm+ne
3wFyzHlhVlZud/so3aRcDHn6LDBg7uul+cbUp9Ol4wHhChImU5NMg1fNp7lT9dSOgoKdNq8ZYgk3
lX8fY7faItKD9YtQrENhoujkGBL+S+IH6dzAuCuqaRB/ioMmM0wenYB8qTCPOmRPGrx48coSva7w
TMfs+2/tkxqzS80nXYxg2X1rKwbYIcG97NYlYpFc7+D2H9A+YIPNJcSH4457q91namf54Za2lQc5
/D9XqEoukOqxAWdImu+jE/S+P16x6FTZswwPlXoWm6ulixcUm/AZ/fKMvt9LN7Bc+/g7BBq9dw0d
yHcbTTt5pxipJ2Ap61PPpMVSmSvoVrNO+fqsgTRIIC7iL4WiyCAFEkWBQJktz81OwSpaEgnHd66X
ES4dzMT18sYYRZqpmgR9yTzwQ/NYVM9vnHuj3F8SsoGdtVOILEYZX/k/taBH6AoFdyj7ndHQj7Xy
5fqAgGrx4ufuhZBExJAFj7L/H0XpfxQd5v5YvOoCVWyhlJy/SC5ypW9VEPlQq+z4ciLETbtahjja
+GZUFBmxB4dlcnhtoIyiXywSyYz/RUqIl4wcNgb5cDgdgUf+/K2h8IkMSYmveAMyaoqwOeck/XGF
0zfMm1tbwWRuRqLxHYebZusGJV2Ix+4cWo4t7GxuIm7jfmwUbh2zqJzOrNv6QwgbKwBTAc5kMowy
hQ64V+v//P8zpkiSKLCYdwT8ACpJ2pBqiNhBIRmivj1IkWHnyFIq+oShXPUq8QYVKLnXGjzRA2IU
DHq8jIOIb1hNL7iyexUlrTqBH3i38b/0Lr0uXVmZ4V/7sSTizCif8GQvRrVbDP4PqEuQjiJmE1z0
cqWdV4UCVDFIiEXqsvaqgTKRf/o8rfTtLmvB/rftgBXqndPcszZhSP/cWzU5c+/Uo8JBa491TthK
YK0bULTYePeFFSPxmbsM0PjYdfhip2DcuhQ93l9rKf7Z/RRFwoM6O/XKKwPTvtevs40oSw9em4Jz
btQx8N9L1W/bIiyVRv+xASEWjjs/xn+0XsjKZYc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
WCjKBNXic0KXiU6pjAWXiq2LTkKJ7NE3g8L6OgRpnuv5wFja/4QAqU+5Vd1hH0Xxsc4vA0Nwy1zc
t7+LfMBHzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H5f3TRBy4525jkh1qIK2Qsh4q/GrtwJ6JVADtzts1qrfqD1bWIkorepAhRIvwZZByI2fH72x5SON
7IfG8zLpYUlD0Jk3QCBoYlUZJGWU6RDyaY2Rn7Gz5P5HI4qvPNtW766wSe1harlrLePNjoSKVhfF
4H7y4hlOm6KeJFp1y30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o8NUJuTvvtHQ//0yHzk4r3ROKImbnyCQ/+GiYKbHz9Jqc59WPVQMPJDi7618B5h2z5gPFkZLVKrt
oYIDayRN1eDG1k1+njjd5YRIb7DTMBqPHvFVEOao9N/cefP23vkwo+I5wXkEITLqVM0RI3al8o8t
AaA6Q0U98Bzdo+Tx+RKbiBIBi5x6wlOZOehaj7m9+DFw+updOQeJ5GNy8AZn7ul0lsua2cRf0k4L
gE8HziSaUr+ewcL1uRh7afU0No6kaXygNHGf/nl86AGwUs65q2nQnVCcL6IPPyXmKD4Bn/J0YFQN
o3G/KJKIPhXq/LL9z7Hr7LE3J/cIaba4C+44/w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
r/Xe2Ci6RnICLxvZgN4C/9rfMRo5L4MeaOlVrWhtom9UNPVoQwQaTPdI6GiUuDDQ3ElZSB7f6p92
n6ZoBVSL1eywG+ntCU6ZxZ1/8N1sV9CjSBxGOexweAx2kmsTC0q7hVe7rZnh/KLLizk+Ny6alv8B
v1zuaJAVY3QDTrVCM18=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BA7JOat/rOFWMLmTHh8DUAZtAhABvlT31S3WaH9xRoHVRI5E6pFuZ9+Ecgih4mhDcxdjqSGbeR/u
24jHGR1zNpOF5SfM2XuvRrQQu9K7wIyXwPdbsyw0LvXT1RLA9UeiqNrt0F8qGcaPOkn4zXH8hSn9
09AecPGhGA7p6v1GpR/up+MJJxlXdQp3HrAGMLNTw6FmURWGfU6ot/fE9/XTH828aIEuXPQv4VF8
6pJ5XDXcni32tirZKs20tbT3Ib0XzlMIzD6X0wniGigh4dlmtyYpx3VFbwNcoV0FuVHZukOeq/07
9NqJrMCoOA/h5LgKZYIh1HETLValj8txpIQaFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 72704)
`protect data_block
HvIwe2N34SZuMjy4um7DVGxuUtmbgThSrTNwoGwEiJdlisMhSbzJPsSLzQyCVPvBWB6KRKKsL4Rb
Vu3IRL7SYFIFYCA0Qq7GVWGEpvlLVdFovlxeEyEPw7vWI0vUv5p8t7ZuGAgwgUgLWZwGpb4Wj8Wh
NY0Ig3CnlqX1XIrtDI32CboRq6okmEybBULmi2P9k61yb7SBFyAc1svnv57UYSBqImh0j1AzkSL3
wa7THm0mcJ/gVH1/KUyrhO1il+aaW6NHEGqWVwo74qZ5/fcj+YIKKJDeGiqH2YcLSG5NjtOCUbnw
Qi+LxTROphc9BKH5UAmjqDhnJgjwGvr4bQeqYaQb4SjNwDzCodQMfFlmK0ro8aTvXCg9F65L6/fq
7DuZcatrpTd3yP/baXqApZ5wPBBkqViF04/WKfDRQMsbOlqNTWJncXWrzKoiXG4UCp3CPDPI1ADA
J4IoqjvRDyOwSbaOvd/DRgou6ZW3wRtzUd3XoyUc3ams6B2Os0tjPMhgSshCr76+8KfYp9hkLacy
Sux+oKs9jY9iRaHGLFTha5pUjG9spPLty8CV1wmij25vxNiEVXbEH22Zb7UWOtcj9DyaSa1hjrIE
x7q7kKY7XnPYCLZ23ZasHnZUjRcT62+6/6DN7KmHAlEaspJwIZt+DWh8A7U1vMtZHaMtbFE2O3Y7
iQjIjy6W6P22+JSJsLUBOdzAyiY8cghioSF+0RXrqzoHtPct4n98w0sEdA9Znpf9t5pA/uSvDBL2
iOyRM89wsiLc7lsX0sihfOSjqqxPSZopH+A9h9ue2/G31af2bLetZX6UsIMrqKKz3DsUWS5jxLx2
uO4K2xiZYATkiQj0HpfZu/5QV3d2HdSUaKtqpNfRz0Lw+5VcfWZFoyYfZ0TDA85K3FoSjhCOkt5X
qnxEdhrhvJwcdP4HRT3bFDNzaQT2Bq+0qvhCP+3ZOskwvkpFPCRCYfPKKjMYd5EsWA1ipnf37Blu
P+B6FwUT4zhffqISQupWw3TQLYLkxjkHEhNe+WkTmmsJZUnWdxVsov0XpzAcnl/DTDNtJ2+ovFuW
vS5MsdjEPyPduB00/YvmzhVscA84PYzTTOYmcWkmjYSzuwP+lws5WScc40P/b1OmM6iAtf4c0rZp
VvXlFVn0n3uvmJnaGn2RIeSQIa9WTqypLxpT+BZH6En9xteyR8rIYV1pxEc0ciBiL/jAV9n5T0k5
fvUkVJZTXX+rWbtUg9+l4nYvDOHz9+T6m88MPMqocLY9yLV+dFzczAowkeQ5QYwNFIzing+a+xZv
Pxkz++cUzgMzeTl06W6wTt2ZiUgg41n/2tzqrylGQeM9VqUiEG7wCrsr9xS5nQjWvd50z1JDlsbc
XZ4wTJNrOMBD0zmEaRn0Nrb5kYjGMUBglMp7HduoiDKKRZH+kTiXGYn5btDeDwJkymeDqU52kxMM
Ua5JylcFhWPU0/QZSOzOFQ618mpAVniy7VKgh8HzuiJ1eX9hUbnNDBqI5+sFcn606kPJ3RQume2H
+YAsr15Lx5QHTXxdHTywTQc96QLzVEd+ZCoDfLy4Ita230vNXTC2z7eECslwEaytH4C21b1sLtfr
5XqqtMYgorrrvtQqTi+7Gy5tqz/yOiJ8WuC3n6rCzNi5HVLxx2lBcmoj3ck11xEwHK50HJHCLs8n
JWjh7ZyFXcnG+XxjfbJv66Q7WQUu1ZmqFkRdo1tv2iY605wT4E/Ffc4gBG5uBhjLdth8vbgwz6ZA
RRtecix3HrcRtApeT9szKzg4hejQoo6LEak3BaEMuJWHW1+RpPJdNC1m3R31OxYyz8uOz6XTCT0X
37wFk8mqDzVYvkZRZMXxSSMgW+/tTBr9J8Ydd+N8d4SJIlaUT6Z4dEKdOx88H5kAlF30H8nMnggP
SDLxrazQ2jQmdjhLK/KZ4JKgWPpaiKEvwxmejO+E1te8EtF1r6TQWyBYuNPbEGkNULWhO4R7Cida
ludH6DOYw7JB1g7LfnsGd2QuUSkIq4hSkPehzDldUnXi3vT7fG95Y24Rs1Sd0MHAm2/25gr952+p
OEN0jULZPrgA6Wy6VgpHXNYAtOIJhXgWrp2Nf57JhizlPfOy1Pcro1lFHNWmcap/4qKYMju/R7K6
GlUTWoUzIjK19xBpBj057nLzgeOTsPvmAxpJnpGyFe2QZgFs1CiqD/9SPLFhgFpFvIujjVokVuQv
Y0SW30jzxOyRztwpB3VmYHYbIWtp7IDQkHEgypOUnIvYckMEO/2gfXT85ap+CcP2xaaMSS8qRK6i
KDBOyMwHUFSKKUvAG6UKRulCPv36152OGtsh1p+qEPYuHuYz2YHhQjAbJwovXPxLIU3qSHtBp8Q3
yc2GWHdqA3P12KMBh2LyuB6FLahJbJu2cTsHXvtXfHXiWrr17pWTXZdqbJPgbxv2jRsGZVxV9TyY
7lRyR8Y3BiPwHIYd+hXW2gqNAbPAXEHzEW/FLTfzU0IEh+8un0KCVxWV+PyVOjiySHksLyZvAgtH
XSphfYqOoGZedfxOcsK8itSk1ADQRdw/hHld7+km0JITcpn6XxxASzJAe4H2mMiuXzmv0AqopF8Q
dn2hMIc1vM+o30ll48q4nzjgzZeDYHU6ZVNTqfMAzTR3cKuj2Fl/TsX+MKLc5v1LF2njBu9aaEZy
X38BjLVxv2YO1/oTbEE2W99LCX/hW/VvpGmSx3TSAWbClged3p6hKVqvXJrGE6hSeAbmJkEBf5UV
9xLSafDYk7Dwr/oug1ymI4P2KbJKuAyPMOY94jd3Zbb08xCkTgPnKXNMGjsuU14Scf6ZQQldfv/X
Vd5uymnNA/wBuAfE0+w51MJz39YGeyyQqzp+ABKGtvX1gcyGH8g37lskc0GVG2Kuko4x+IDCgmOo
tdiIPZWz2nQhwO/4vZeZ2/h2k8G21seDc3LmaeBgdDtzN4AczOgKoqoZlxiqh9XbRUQbyyUVhGEF
NRRAJbRIDhE/b2bdPrvlDrU13gXfceRigKLhSBqwrzdvhVu1t5VHThFl0xUMVG6DXaShN6LFBfkd
qMELJr5yk73mHmfi48ipz6ZDKL948hxDZ5mRLxceIYnC4G6Zvi4LpBtIFUnvtTU5XR6KbYTZNK8D
pRDt1tgs/oyKpT3j+oJOb6s4chzqzeyH6GA3/tNu0pptqc3PDRfETxx4+wq1DuudmWuvmAZ0aPdB
NCAsKw/QOJZEsMuJ6HXwdee1iMOKoPzsdIeFEmNt7XhRkOfamcXv49MHg10jX/lQ67Kfni2xnQbr
4reqFp+uoHm3eA1qOVCwJqjNDHp1WaWtSiHKH/hXz8hzyxxgUDc8MWMD37Wdb3tjHa1nggaLwGLi
rSN2SmS4RLT1AdAGlDAmxM+N7fJMoeD9aSFhQn6SY5v57Om61C8nId5zRNy9nVQxwJehQRaWF8Aq
fQGUd25hYUrTkKGV38LTKfhJeJL9dsCGZNA2VRoL7OWx1ZWNkLrEEAFjBa7TV8dwE0x+1fzcErpH
xQ16Lsmia4F9S7CxGcAz2HfcKzcNN6gt0ah8bg8asyRNgbd8MgnANmIPxgkh6lyX/KrjBP78nBiK
BoQw6t0yb7V0UGt2AfFBXTggPoW4cj3iiaaBlCgQT/IgrUopBb9Dok3+aWBDZwCDQ1Q5iqjyJ9pD
KY21xP6p2sAIGQ5xZV1L8lMQoMSJUXS/K5kXJ5BvQ6Jk7CqNXhuxV/wAflZu2vkP1asiBCBF5Ye7
s0byJmevvnQTPWCBHdrGJ6pmcurXwFdBd0BUm9krKJX0e+ggOIDrS4m28IyFCL8k9qBJZ9dyclDw
6GivtqpQ4tAMlDUr9VIEb2zUoLC4hS79W/d4Cgf9SwFGS2vcOZBsheQvadMRMpZFQQMJ9wxCXEFU
H6rhaxKzg8E6iQkFYAtxSIxcu2lyfYMFk0F4c6+4vhd0c3Z6oLW4PTn5hLYEsNOeYUzWPawLVGhN
YKDfkI/sgWtWAUFNCWwBb/kbnv0VClgQkaLJ1R0tbEMZJjoLVFfe0kjclNs5uNhbM8wDvcSbMiEq
TMCnnQb8UtEc8uriFBmwvOEezo7AL6JbxMFZ0N1oKnDkST57UCGqMOCfQ/isGpo3zjTk7uDGuITV
d+GVfw/T+U0Dcy3yqdTiyg7NT2fWEHiv3Wj1KnKKsxTRTbpDGYCxP5wHzQI03sVIB398CoeG891T
hI0s6e3pDFks7YgWvv9M0a6d9So7MsQddPE1IwjB0jVYbmNLUkU5d0BQ5JKdQiR0SL0vMH4mvwty
KXQvW01pzD/nVo1TWzvs2EfoAMcU7hoIAQhSpXFED8NKcuPLR7GZ9NSqFlKOA+Hj5Au9F7uXrS3v
XbNXiGOSbQknrXKJs6jmU6iDxESydyyhvcN5SgmrdMmZx2/Mv3PFYJhH1PAvsdw7X+gHkzhugVDe
f4vgZ254r7LVyo2qUwGAGQgynV5GBWYbRWRrYn9i8bMhMeo5s5FtiNvKpebRQRB1jccpKDqmhdYv
HtT4onhN20B6ChVUOuSYbDCC4ydVkiI0xNIOkhL3NWhXVvuJBIn4o8ELOsiLTRbCRhb0PU/07MDw
+9BpGfTrKHBeXstbnQVzjCc4CttauKv59t1KcPKmkDN8sA7EVDXh454BiEJp8VWbHqonp7dqboBs
mqr50B2lpcfUzwbCmEVTdBiOyPCVKuNkVFfcMYIXGvqt09c+7UHm0yYdwF2nlS8W+3j5VtpBp7TJ
Zb0xii99XhH7QE2CpCSj1x4he0uNUIP6enQ4xpqAlUTm8dy00jBDayQIi5em4F0nc2qcFwUkVlkO
z27S/a/MgSzOFp/fio5suNN0UOJVyGfEKBlwEFkzYFwcwgarr9niXRezbvG9E0cNGHSGMBy3t1bi
yJRFlyuB03wUPi2NY6zPHn5oqFhBkA6y4jpeVjQuJW9CaJrYByef4li0tZDyRjaI2ySPOmtgcSt1
Bv3rSwR27hQ6+3cwYRmq25ZUKrY3tpWjoUYxb94H8LuMKja1O1r0MpaNJ6kUBKP3LGgr1YHHb7IO
irtEqdKhpGd/Wl4Cr5U6jZlxN6N7WDvkP6/n4VKyEAZa2RwNRP9DxlrPEQDvcc6nZ0/lXMJpBuke
XbRfW14uzqZp4ol3Ktw9QDZqTTXmtdhroocX3oCm0E/9BIBYx+V6XKjMmeP9SVvBNFMC9prncNqi
DpOVWEpTCZvVCyLiRJ0qx3Vyk5E6jc/hBPOZKfbeyY/FIgTj/4QKptvZH2Ptz6nfMcfZdh2Ucyq3
We53hmCbGSYVLvUzFD2fEiVlpV9tSFm+lBicoyXggAbTbNnWyMxdI84UpShrNB8nYi/EfKSHy6sk
QVc0iPgqy+lwyoAjFcgNfPmJViVNFhgAnhZhDY1iQuziensvnjPIO1AGRHoZPOvtpwubJeUM5jMV
6OeN9LgeJ8RFRpXnkQv1HJlkVuo4wVPuvEaph7eZYesqM3s1CX724Pmyq9MykE4zMN1ow1YUmIJk
lrC6txSyBg7OW0n7QzRlAKfimFh0SbgZCXYMG2uvsupyf6zamMXHM7O6y3zkB1ORd7pIdCll/3Lf
Oi9YeQlNJ2o4oiljEPInuwhktLGjLpH4fJ+uWo4fvfue3hCWesgTFk2NmwT6zGeHnbSSu3kGaVrG
OX8BLyeoG0CMskQCw9YbJRBOHtI/b7dag5JRUxqN4R/bfHDkpfu4E/Ik+x/aF5mGffsZmE6pVK/4
k3M3jIlnIVHLXXQyicE8UFo2c9VJoIgR1Y30U8vRzK2d0EKAHCKyut5hKp5KytPVaa9QaIvEUDxJ
8ydYsQxl7Y2AScybaztNKlyOOB94W1IXpVkFsSEOE5P2ICh2LoDF6qk6nYsOwgQi/QrodM8aA8Y6
o3EuacF+HCN0A45oiukQN61HXwJ0qxHKVJQjYs3HZSiEBh1rAcHyp8ylj3xUyEdbKmowB+r52M2U
2a0CgPGtlwyqFE9qku6kQ/JC18nhW7CZvNyUmbKQe6J4VIF1G6mjVeP64ItH217LsQu+XeQyZ2Jx
glXpXmZKcDu0CCS92Jd+3cmx7En+WV6A8x7OJP4KoGrYnKW2YGwZTVJoKoqT3RYp7t39QHBcbjDd
96iTZJ5SJfrVbvbIA2NMmXcYyL1jmYnx9oAr1iGKr4/zQ+aCH/Sowet1D9lBI6cg+RGcSlcy+LM0
1AiVzhvLbt7KOtAYZhux7dAad/2+lw3IBzG92c4FKnF0aMp+iQIn77K4NPUwSjR2HfP7tPmjKST+
d9BTe9YiGJjgOe/5N/eZV6voCC1DNPR7yUyME7QuhfXMF+VkFfwQnZLF1g2nZeREbCjdJaSCvmt+
erBvrerL0U/GiGDtZpBWzBlbKL6kA6hyfxppJ70cPoccfYQnYs8QTyFzaYZstGZGNGcomQIUQ/Ba
tA/fBEC8472TOD2bzIw2/VMiA4YHnYQYMqLTkdi5Kuxn6iyiUDYJamg67gmyOSfVwFTF3iuc5L8u
SGK0n/FoDZYtFE0Ip6owY4tt0OqoJhDWIzlgKUhHoYsuO0rhRuAwgZHmwCjyH85PVkUoALJqTWlK
mHc18K99zEuFST9hhrgUZUdHxULXvy5pTNoTvfFZ2IYvmiX+rk7n3noVKgVLDcnzCnjKLN/ShqyG
D5GR4mrCP/rxxl9Uu7dspgTrEkl5FfO423Y3f+9iiFYekUT1rEmvGMXanhKsgCQnGo5yAE+s6SmA
sSvFytmH1lNuUDwF+8L3sw83nU6sf3fISSEW32sXlE4zdgXje6kEHoKVShgy663x7S0R6M0b5CDJ
ecveH5A7XW8YBaOtZuAD5KA7n+ejiYi3kqrLBHWEVBKVty02KyZ24RxC/UkBE2q7OpRQI31iCSFq
Ht9ifWl32SSmycQBc/pyAORd81oyYEj22zvvwYS76CICzX+B0ONl0PAAZEH/ffwb5IkHX8bFW9eC
tfwXvZyyrpma9/vGrfoc74YNALRYKZETKW67G4mtfyAdPThR5xf8EKq0/xtDQvDbXMb97npFyq3T
bOpCoRtMgfvz93JiQfC0LMpzpCj/w8RpP0u7jaFjgIIy8NiN7F68kP0HtA17COI5+9C7AU4iw0H/
ELfzjUg4DViEtMlvnL/D6fFpjtMbjZnwQ82QKaWy8FrWA/Je+elbdepn29k3pJe9aKgxAVd3+wZE
kyV8qkCaYFb6GCr56bkD3N4aI4GZ0MCB1Dgvjyt63otTqctSd2uEsu6IW7EwM6SoqB0Ni6vbMcSk
8Ngxtg5HPXK3f0EHJZNxdOOEG9+J38vjXqWhCyUGmqhCQz5+uKS2IUKF3YIhyS1qn95RuvBm7PYT
ehuDzzH14/+pKSdQ0gHAH6cUikCGtKWGUFuj6See6jywBv2C4Q31apQKA7/rvC97BIi2paggmgd7
iNpgYLDTty91dv2FkMv/DP5uDjTykeqSMj0FrOqsMuvSPAXoFHKBecKsDyxK+ZCNzdOhD1Q5srEm
DOWCRK5w7tzT1RB9VXiim0/DqFl0P4Fs+lJYanN1Qd6fpObL9IQR11fGp5C6IutXVRBGGn4HNbTO
5P6NpCoByNHxfZ2ppans4Nz6KsOmdfPCQdp6UVK40Eu7gtEmn1pcVqkimAlZ/T+bcQQBIkWCdMgR
sEFrQM/uAVNbVGiSTqnzDTopXsOzZ680K7mdfR0YwLKNt9x3xVEM9vhzJmzln3mUDl58ldZfLgFv
WILmz+qw5pB/sQFy0jkQyPaQjobPOnkiVbgQkvQUD6mkJXKFsGQJ24GsJUTaYrEb4EyALETP4o5A
f3ytrUFDHlYfuRxz9yNU8QdYs6e2+87rKAUAFg146b3hL3afUat5ZbU6wa1XwP/970AyWZTf1gRS
Ct7bvTvckA42112OtIQfq7Gt+DoihOFVMWb4wyVC5DKXK+QBBnQDVUE4q0iJHl7k122Vsrjs9+id
rCUfrRY154uJf2SuBplIL4X5vECnLUREMpuqnLZ00pJT98IyCPMvJtQtus+gshp80MgdoTVxb5Sw
Rlo/C69GBnz7iRyk3wdybLCONx8PZvUjiG3DLLtfXULPKRUsCmk+ppgQjtvKtPsBUyugdUnekR0Y
gozZEiNS5mRvpDAb+AVMfLPsI00mZzf/eUDD9RFgJnnqQEesuebHJYduD0x7m24nNVoxfZpLQ9kr
Ph0WL7tuP7gWeIhMYv0sccG+XrShoZ/r5M5CJ40CmLbedxT953SGqnS0dZrtXaaeYGO/464k9waz
KGi87zDnxoRwA3E2JXVMIhnTdEBIcqSA9kmWPnuNeL/NvDouPBDqKNtb6W9I3NbuJMqHZ+EMGAQ+
T0hfH957EsVE1dxOTvsOLqnWLkNF79aAuLtUPKrdTM34STEBLjhPfkM0CxTJVRgXfI+riH4jDJPp
J0yTF9+CZ4DJ2Pj0SlbcGsTLalg3X06sRYBK8G/7aB3G9+8N7XQkiRndDvNLr8ayF9NqpCeIigjL
u+syGsEHU9GCHsLjqLfT0ZTxJHDT9XXqCgV0xX3E0oJY1IMojlgqCdOS+cWwzMzGII3zlQwfvS7n
KxbW0I4kfhcvqEQofZkb4yHBTQx6nY3QkzxPDW+dFmmW3VrMJofveXe0uQ0QE/PWyNNj/Zcud5LR
SiyQNC8gilQU5RRTxUNcZN4SVzFVa5go4lhFVMXoTHaCwezMz7EzxH5vrh1nMAbaam86h5lqliGP
19k39GTRg/iVKmEtjOeQ01La13ZQLdp8Oy4SxZd872VJowdVjKOIQzyXy5di2jkiGoTsVPMTGRnW
BSqpgWti/mhC/kTrmTwrGRDB9oBvNbfwr3HSqcRG9CO9R4Px7V0akzBF077ge2jhGKYwLETTxqXN
fzLjFvQd214Vv9FuuKjwHp01UpDRuR7gVgKutBPzj82kVbNv866v1YJACYdkqxZTp2dwBFgxhHZh
sQHRC5QiEp/SiXZEILSROy048rh906Tfm9QYFSNRKDNkid1VCGimBOPjgS++vLmkv3h7eRZtFX2M
iwi5Or4A7nCz4TjMngtQPh3Ll8l2EX9uudfpQVF8nkaGzZmPZ+LoPAolpIXtiqHvB+hrHTRJ57Ic
DruA3qYMPH3eSAG7Xr/9wLgS9Wz5FwvGu2kxV5BT8vd3fsZ94PYTLcfRNNfymMlp9zrfQkOD13wo
/E6PoM4fM2NhQ+7ztx1YAb9bJ+NDPPnC2u9ntBC5XZZ83Xc/Pyr9pVShrd7F8AmF6vIygKTGO1HH
3hM3By/7S3fEcq4BtOkGKF73R1k1L1eilN8iqVlseaxmRNF/WRxLWcM424/+PHSQfTpdRDfaDfoN
/nvCg3kmY89muYRJle1YRH+t0seGJubaC3jUJym8Z56xhIWwwxosav0TnScVgUU/RZKMcVcNkmU7
a8WbtR6bGlLcyIESGODlb5734KNejF8BbFj+qNipIW2E/+W9al04m6WaYhXxhpGMkbEnpZC8SrBi
dpBEKLXrio0WEkwvQdgLQaDJbD0ZEbeKNZJeAqGS53N7SiKImKqlj+wMq3Bgc0HbeF5Y7oN7IvUO
ArNFhnHwg5gf1Hnkqn4UN7oLeoClUSTkZ1tSibhQVzZThO+BxR/wEb7qNLCDWv/MhnbHxNEghtS7
HN7qa38eHjYl1H45RafwBRAIOyuB00ipyboFzSPVxtLXJRt/kTIa9jYw/HeNrndMhsuSgpdWHHRS
kcTOg0Z1727nyFFwO9F/hxpDcPrKK9ehU+1aXft1dUD+GHa9d2UOTJkqBLfqHOTDUuhqYuzvfCsY
A7Xo8S7bw3Y5IpnnjYrEf0MabgEQryAjfXe9NJfAjVGkBsBqU5S4xFP9tcw+hBNRZZIua8A3Yvxq
RzHfXTOotj3FuW4oKgyveA9kR1uWHYBaYBZvnAWFvkt8LjA8/oT5WxwwPE01gORgzy3nzDyO7C/3
LV5TY4zVOdbqTYJX1SvHFzNgTWpMc4jvJ1L8juiGRQRUWMxlMM6SbL7SXNW4XsuKmYR6cwlzqUiq
ARd7WUqE14jqt1JqGtmsskzS74P7Li89ss1fAUONlhSCTmgy8MIMiJDuISWKh4gx8AL0FVNZMihN
NU89dk1FgXtOSsmNPS+hpc+oMr/RLYVSZ/xLGVMgjFZLDP+/2L+G/212xJI+n+F79rBhGTlWEI/I
3AShC+Y2bmmwc8QNP63HDQyKyeYSFs+z4lBEH8rccVkFTsG61aGUwi6WZmqZHB4nnRrwwDljk/mb
35Z+9QnYMLbV7sTNxR5XHqKE7CWK2FyQOZNvNkJhXNg456ciDZaSn9h82WwEtJFiPZIvT7YIPM58
ohCPE+rjrMvykD9HxwoGfhOec1sKblJnb6RrNM9SCcJVs9rsGm0X+WYTA1wuThLsxbu4Zhdr2tBN
EaFbaC+z7JEjBjYTye2/DsW2MdT956+xLMQulLXcT/kXJt9UVgWsElxkHQ4Ws4xdmgDwx8MzVP6z
yncHGkHsAVqCTsCSbxU/9M1jsZAKFTgs0cDsT8ST2q/Axu+e56SR1KrkFW4bCXSg0rQFTQwLaXdw
h9/lmMkolwBFKVT/8tz6S5EOKca1ihMBTXjbnoezPGzs7xA07IJ0hh3GX4hm9hF5Dk4liJdNUWaW
AsGJhKbQAa35ylAFPyV7mb3dwU86urMJUa0A/6Juqn5W0z3g2Gng1Mb65SkiyO4w3+mHYvql3FcC
ETvhSdbSj9Ib2mUxwRPNEywd6jbh1zsx15t/iBP34zE2kycmzNkaPYS9sVT9LQSKvAJjIjxGZdH+
SaYGZF118GqrHYuFLIBlthjn0+01ath4HLeoGGB44TLnZr62ngRdAETBpTv76r+GltbBsq52zp4j
qqLWR/U6BDcYqGh4bucUgw8v+TlYMrdhsuTPzBxTIz6Y11OxSkZCsM9n8IuaVWaPCoWK/LjAD8hO
w7O5YWfWoz/RIQwsfajhyrOEGvKq1uyqg+dMd22jIDSvmS+udV0h8PZ/GsRevOAYJtZfNApo94Or
JKk/3OT71MMwiDi1WyM2C2IATUqp+GY6J6E7UJq98EtBnD4nccODm2suipwESPSb28Abg8ld0EGX
UKDUVDoLRBvv6LXc7iJ8wSipJSL/6iqIhfRRaLZJ8Mv2wMiatIRtou2qICTZYwYVdg3io8HPY6uc
JxRav3TOUShkRuHShCtFwUQDZchEqHG+XxVFkzo4z0xhrMNYG/tZ9lMsFG88sbytfWoQgOxZ5yol
xghh/ARhf6XOO3lNIWSucLcslRt3O6oN+TyQWQ8PwHJcFxkZEueucIUyDV6U2fua+SqSrLlakaV6
O6+/siur8wwmo0m9CGPPFZsyIkDjhtJ3oa+NOR35YwmCGs6RJF5QlJpOO3OE/FoXHzY1Tc2zwO/5
hnUrLCuUHL08AQ5HX6N7rAvVBp61T09ojh9Vw8uUPz2zbqa6CXD0LwfJyqUVnhh80IkNMKwtD3b5
D5LVOWIk3CpogLyY3NQnjb6FRuhTZBO0sH7MtFCpXBtCVZFfGkUZN9/z8hmsTdt6lp5egXcGEOWg
66hDCyuYepxuRiJ2le3SIwBOL1GHZPp+o/M7DSjjdZmgQqVfd7pdwIeolDdzuQGozJ8CNtmFtcXm
yZLpi3xZCeMpgEvOQGVk+QglNhyUEyCBnkoGMQcbVILyhsEYCjO1r/aPu+6YQRzSSIJVWb0r1urB
rOlXry0nG8vjM0Eua1BKwZ1OJU8TJehY1W/trLzJKdTboNyh8DebFIF2M/6SONEwO2y93Qc7JKmw
SvP/pZ8L3TlHJ8IeqHPpF7tX8Syf1AobFxITCFo+pmHis1oP59A5yCEEx7npx/7cMw8XHKqSN7Ru
GKg+9GMi1UxyrD/mvsdcc+l7s2yG/GJZhtbeHUeOiNwJPUwWTleYwhqRbsybI2G20u9gNqJCzN84
fEyr6bqxwBrXlYAlZrFd06RZrdbUOwPzpT57GsKs7eMWIqp0zXLeS0wHYOtTOXy0nF0CoH/vNOtC
BLNsEr+o1ZT38xBKJmv/cDKDJCGM72vIVAxwDGivnvGO/bniWPdKGZx97gYn0U9Pw79Ox731zl9g
aQBrx6dupt9kZ2sINFU80eu4UdkAdsUshP4Ddj3FoYnckwFWjbC8yweJFxyH5lxQiMaBoxCNT5ad
LdXWxs8IBdsQQFbBphF1/RhFQdO+VUONlPiJRSAKMZ4FLS2yio1h7OFZX3BVmufTYOtmjN12Ftqf
HOMQ9UZxGxrV06GgcODlMlqjF6Ge2oYcdum7TgWaLh4wWyQOydSOOUI26tL3C5NDknpXbTC1InhI
6qAXR1WDG3YIEDy+SNq9AWPzqbPBWB1aQt4gsmLIfw9eWe1UdyaKwsIrrdleJ0pHsVirrvMiGFUi
0dfwiSmnsbdL8DE5mJualI3ug6qITkGNqqe6/+cmxDzmnFYLNK8tq2eN9/Y1Rbmm5+VczgTgkeGA
LCVRJQqI3YkaXFDlKt1ZvQAmTjw2iU5Q7o35uG29lCilJfzX5rb/2g1oAG8FM56N8Ntb3a6KZW8X
8roMuJj+01vcvZ3YUFpzuZrEVGE+nAbkULquEcrkCF3+fONxAuQLGt2qh3TKRwk2qfwlcgVLao2m
81fhe9HAWgF/pAkzxtSxYzUP/2XS8Om301CgZQpFZLhzXgTqy4ZE3YnmvTLgQaDWUWbhYynF6EH/
2W0TdRA4aZATgBRuC8qtG0vtxDBgt2owVRmFTmwSVDtK764Db3quTQlMfj0yQNncZ+iM93MW2eCt
ZiK/R9TWbSKnXy5LFDLgQ9iShJ/62l4TcmagmzPhFIlSBp8BlzfDwGrRkekJTx8rMMw31q2b2lSj
VcItDahuerwTsf+4vQSwScrJ9L7ulGaustR3do5/3Z4v7JKTyvFSkOrsFP9ckJ6lmQxlPgfGaDWH
t05GM37syz2VdG1VvrRbcC3JHQYhWb9EbKsKEP99xxdl+//CPlW8jouqYFl6Oio9wFGfEN/KawZB
NrucvLUWc/PS1p+lSb8hZHIdtp5Sk3jmCgonyZoVcU72hMBo5Ia2T6zToa4WoyvW0l/usZzLqRoD
CQV4WuDjnQiAVjczj20wPNq2o4xRiLQgiN5MtSN1vuJLOjSowphaK/mAm0C0u54nEuejSGFSvQF0
FBD2TELfYi6vP9tyzB5iiz4JFk0Twmu9cv7C1iI9Zi9Gx7/n13n4eH3beQLr/anVfPoOtWtvo/IQ
1933lVQN1vovaXQVn1yBOUFtB6qh2yVBsyHCuLUryFlh+SHlweDjjqAXASGIaRpb4zILanLUuqF8
1Dx0midw/aUsKfyRYKZgHAiRXkd1h84apmZa5w8CfO3WQUv+N9/9QVyCXsFmaUvyTGQeE5Ag5F2+
kOymfKmYZHW0Ivu1I/u2uZys4eoZsQGcIm1jqFGLCakCw/CwzdVtcuqdlVzZX9JjtnR66otRgqgu
dJB7gtXaA0l99oaxYDH3gKXmV8gAG6RBgP9garB9JtxRwfljxjWV4a/s2om8ZGiHXpRM19lQWBYO
/uVCyHm6kT7ZaRAY0Hc87iIGOMbhViCNUw9KjBRWDKmN+m7CGr4OwaB0EiTl7s+XLal+xC69ZlHf
3PTrbd8dEkPwNZw1ck5EJYNlMpnAzBiNNkcHS8JpYmUZGYR9s24fPWDnOVv/cYOFX0N/+M0kTG5F
NUgo5oVfAc09NlSx3EUuNwuGDvzHZ4GM1V7F+ZaLc5lfkiyyQMU+Mgf8iQ5927gWpA+aVYgNV2Ju
OYcqueUy/bCrF2K2XyRi/Cis73j3ZS6uDPxEP7LCSlgurHAtE85OSj4Y7LA/DM3Ov9pqMJslXEX8
hnzd/8fgoh4B5upOTn2DUGNw2jw9RrIz/dj8X1+DzmTwdsSc+ZbzOO1zBo7Qgh+iP/alcP6v3uZi
ZXsJUPBfXXTldjHU0ftgW5wQduYLHEAzmwd1gc8FHkHJDuIZgP3XkjMh2owt8YiEgC15EBZstDGs
yd3mVlDuT4dUk+nd5ZWoGVSlZ8X1suxJ+JLmWE+tss0fkxaQdN+87uxsLXo+Y6FveJOwcS4ERkjw
VritymYicUjTE6bfaA5F9pfhX8/WEvduMdUp0afRRbjm5bdfoNCpA1VEQsMAzDCU7HVWFlTnvhrq
eZcQmxdP6SCkvJ0qUmQ4hDZYLLKn0Zg/TyKhvUo+PuHLY8gJLwdMO9cIuOHjxBWENhv+hfpn5aYk
uKMfM4dojiMtGYKbx5jhDgdIKF5BbvsM1zWsfb4q6xPNdPzzUz7P+GoSTeZ8JvGsAN380+D4ekcv
hjvJ1l4v1cz7JJVQgw80KS59oMIuLgvEz6hu8Jmrm/Ehy/+z6ZoboTq98Ahr+FRSHl5rjD+l+s+T
JjoXjygL7QQb4Rh56Y1y7I1HwLqOaZhv5JSwpcA1B3LMpxJ8qcoFHMJyjd7j1vW3n2qYIR1h5pkp
dZBEGza/un7B3KLVSJVgYuNmZYAy8drbcta/9DMXvqK148TVvKK61rNymsKfHqh89AhOp+131U7F
ZAfbFt0dYiUUd3/aBZQYijOneJpAn6AXxb3TGprdEM3vT6Vjh49LbCz4/qG3C5Y/UacERJ/d1Da6
9SYtec1mEWGa6rSqziOFh+WPbcC+xD7d++o9jLwIbanaiheYuH1upZDoSSZliNYS6Nb61DOlqfkv
lScz+UEQdRNSOero+gQnABTHjwNmAx9wEXZPnKnOUKE9W6ez8fPAct91JZxf904NDvg2M1pAGHDr
9cHbgqJIm7Rtz6O7GjIv3+00KsxpUZmlUfKNq58pNnbiuqZKFdcQjIv2UqjVqfYBCjop2nFpigIS
QthIhCJat8ykeSEJMBO9JokaYsl+KF9KSePP40mlIMaE7TbzoyGkLwILwCYgrguL6mMlH7B//Eay
/+KNo/J/rgxDQKcaIk2TP3RGelRr4fX2eKSt1bBeiv7C+iJ4434kojza/WvERtJJTHnGEbxGnneQ
Suuwy6WKC+Jp/7rQICc5Le7L4HSXouSsEftVwaecOllWq3aTjmMzKgOaVRcHUzZHW4BlScYQaQxP
2ksh+ZayLAHK0RjGxhcfybSroFv6xtKvnts1HY5vaEHFbP14Kzj1Wsl/sGw5V0P8b467YCxGVRoy
m70LkRmSKzX164aBxVCEzLNfMEFQaQLPhl6Cpi7/N8W4H300hF07USkRPWXs6qgEjFqTzYkq5r6f
0jTH18JyFLkMnSoA6eHpsUveCZykkEN8Uk/3fn9cvjfnI1A2tdhcv8Qle0rFtc0v9VLOxOSx1jsY
WrkEogWk2EKy8I5r0RNKCSzKIBojk107lomVTwBpyiLtQtGaY7w2gS/S69iIVItovR27ow0rBLUa
IDbSRRTn6Rg7iY1pcMb5QUK7JOd8b6MEBYKqJIrtdYwG6zzxMVgjH1Ant+/0k0Zfg98g0bDyUE9+
OJ0T5RrK9RSUg+PvZ/iJdw2CMExZ36LEVe46yKpjAA3Y8lKDx1amkGSIpaQSFqL6akwckajxSbfK
0uz3aHeemj3uErsWVAowP4fXyMWOsIkS/EUvbbIHLHqS3sKfiK8XlQYRzYRFUfY9ipnTqnjFowCT
beWZkg+03FuiktXr3A2S+lkblthwvaAWNc1qA57dnjz/g9/C+cBPJ4uqg1jLaRILBonmQashr9R1
MCVtjdiNsQ+vMRW9s1ItUqpXG3ZOBS/yzryK/a/lKs2v+wtXgW4lyKLwh+XSlVsxLiS0QTjUvcmG
ED50HuOn6g5d8IufBZM97BF4RZn7A/DSAEICNIVYdD3qJd4GUfVPKxVRUk5uDTFtS0w94+Q7R/ei
6Oe8+GjhQQTm2DNZELkuUJnF5M4POH6/x6d3US/+x7SV27laI2ES/6Cy967wnMz3KYatE3Y7Ov8S
hjds2RCvr0MZX3MtNY98lSfSRzAcJefTDUzpHIDptz8wqdqv/v+vhLOsCfxzXPZOAJ+Tpqul8L8v
Ey3Bq3kGrpPhtIq3XaSOYa26R++rGOuWFbWFLK23UW+6gu06PMmdOoyAWhdnYA7pREwOP1X8PhDD
U+EoYwhTwwpEU4okeOc/Ikra0SepMq8C0QKFUbQaOCv9ERrb1USGVEFtrUvvlsNFGbpZE50FzacN
UHW7pysUicibltfmGwzx6we8r12JdfXV0K4XpbPqk957C37sFhxVK0ULKjfHh+ZWgmAbNUkrMQjF
0Yi1d0Z0kd1pZjH5uI1ZlNdVB17PNLDx7LPnqTm5bMJLIS89KloE6yQxWTijvWoAf/5uj1nFA3rq
loxUzqOjtCf8kT0QIRHQDs9CTikOmSkj+GA/6p8TH29rRks4PMVygV9ot8AlUvwxp9fbGFqA6Tk1
2+8btOhQ2GjymEAfi1H7DRLnMwKieez/7JsFn2Git4t1459fJgA2XP7GE662Yv01DqVRdLAc4hGL
QdwA04AKLm6l60dxY0YrsoY0ESAnvN+4bRbY3oxMWzGrLIUkz76KrhfDrmFzxG4d8P5xzD5BmaPN
LQYP3365Gdh2L6j0pLxoKBwk7oNR1SMqHUzAVf2g73vBe/u4iqfFGgAvFen6R8Z3nM47KV0yj3lb
wUkRgySU9DOEkczpBZuDp6np9dknwsi5GYq9ln9DO1zyaGw8CgQ9R5Erd/UOqtD/2PU9rFGLjv2n
jy1c6HpcQXtrhQ1OrG952e+w265V9MjSGdC6Zcg68wCdg961u8CwDgVCbNy2klRMiFgSn2cQbEXj
JnHHn186n4J424sQWkAVc3ys0oigMMaI6d9+75R/3oObaWbv9xiIHO6BBEJIE1AUyFShqHPQZjwO
+xB0vAjZGA1uLNaLzECZlRPgiUh8qUg2P4wlEv4NHWdjTcYBBerbiJpB44sx7lfSxxAgIieYRWKi
DC5bM/1edUp6uHuq1duMBk7ehg7Izx5+JnMuMAtDoIoxY2zfnoNYVFUaLg3M+BWT/bbulOabqi4m
xjF+Tf9/ZpNjaOt3GrKOH6mnBe56eZ8uVEvhyYgvXp1yO6UN2GGUs5zN70Jr8HpChdxFlXrC/sM7
dNrg4LDJxfYNNijKKrRZZmVP8j8iXNKTd5bEDLEGQmHxknFVdBO+Pyc7vNjpcFpTPeJb2G/nG1gT
Lo6LpsjbVkgdA+ldPnHgyPazkoI5yHEkvO383S+cKoBiByv9MwvgSJhiBPeYzdstT1zXSmxzJLX6
bdtZs3uMarqZpsjf6gqAqOo0akN3Yir6O1x58FLyUxx5DPbEyHov+L6N9hZN/tG4WKOOvLd4ejhW
fZjhvOZRvldkZIKwjUHp70xSh3HFKHzIwf1Bb51vPgAGrhHlzq9eK1+2gAUlFgEbKBO4ny5QfEfn
tX3mVO2FvmTEy4Q5MpIm/HOtUDcfyixYnpaf8PCkws4ra7TQJb6KPyaUXvM/BU8pZ7SuO87UVJpf
oMH7tYLYYJ1H5jFxfsm5ZD6UqbjVnWj2MQi+fR60a10QqVJxGEtcQsFmlWk4vKZTATPOeRsCO2As
kBNquL8tLyX3ddH1D1N8ICptugLv3UUJ6nwV6wi50Z/S+FOP1NTKc4QYUUPy+N90TFG7fXYe3mE1
ASQAfYyEpNXy4noQXi+AVrQ3OcFFkA3CBjJhXJByL7UAHtX6KsNM53BWAvOM8zLC1hhVxZktJm2R
TADi7xb59WyI1a1sYpTsASx08WurNnaCCBxiZ7tvmX/VYk3xhInU20SC/h+iF7bJ7JLq/aXg2DeD
R0vdgHUcLRmINELkgAQWT0Q4F6whDdx2FzjEW83mF/U8mF5v01eXrILXAxAWkvO5N2afETrj26uB
jSIyBuA7F2AH+JAucMG/H5Oze9ZrqahSE/Z2lp3ZmIpv+7c5De7N9cD8x63xPKiu1RH0N6d0YXdZ
O1ffh3qPKz8XU8nFqFhI1V+KFUd6iYA4MKTDaOpN3NFnLPDt0txhV6bFaDPVmLK+TrxiZDf6I6QO
rJgw58hrioYH0bLmGsMK33js91ODLrAzxnQ1isglukpxthtxV06H3ZO9nkBC6CMhye3KONkgwStv
fA2RQWgNt5zASqzIORbq0Rnjjia1LKEwBuB/KIeooVWfaqF1OvnEcepNYwu16TvuO6VF+3SiWA10
BQPm3VLJF5RIB56stcmAbf9pL6oJmYf2PGaSg4/vMgkAlyqhgbtLNbERwqz0/ynp1DbCbfhwhZih
puYJL0tNYIvwyRZUnuSVOmZQTFZ/5lpM9H+Stu0kk21uJkYdiJ9Dchi4ahlkYgcBdQd6PXODMuY0
2MR11RWe962OqNGq3JzQTaNM6gpB4vMzEyoWAan+Nb4WlXLmr77KWcfQJKJIH3/ZS0oyg7wW8Iis
cnJJceAUgKjw3jzC0L5rnz6KOlK6+aS4W78PJJSPCUx8cy2vsMs6OP+pC3b1cIJsvK73It/tCOX6
eiqHmCPjDf/UStfTOD0oBGHNBH6oqMGaxv2CKnbb37khPUlHHktI/p53JlcNGByQOBWX4qRFn8wJ
UlJSOiJ1+dEX9P4R9PBXCcf0ZSLKOCtUk+fytMargtrbmeTnNPxzVPJYik+Uu8e34ew6rnbBfBNS
wtwNRduJUseL4WZb4h91LYRrdny14zy+0foJQWO5exdT/sBmLa9YreWHoxTzBaDOW1aiWe8kaCaj
hCBioJ6MRB1CEInSTJ/Qot0hPrS3trRoZoG0FQ3MSid0JXZ6AwR/vjRglbwWN1voXg/sDfk8vrdt
max+FlaKcKazR+YPVeJcJmyArkvOfrvuK6Ym6OSMYQN1hfJwhaQSoP1Fiidg9VxidlgjhEEi10i/
bh+/8VeouBIfxm09K6XAQeF5h+VwxUTJMSwYNKB8P8eArw0F2rOIOhhG7y3BZSm1cQ00eewE9fSj
+oxFxppyP2dIb7qNkRaKnCRyt++9Kzn0iIRf9V3ZGH1c8xq2fUyEHlE4ICDmrBPffx+We1FWubdS
sc7tLOIODv12STJ+4RXPXTXUXCCK3ou+wi3FY5eL2IPxUKkOLzHu9hPO3864dhgVauDTMtelXIpB
PqIz20iYWpYDGOuXybvQtTBlFgVXmxCsuLnzWE66y0HPmJQjkDIuUTi077ZYNI3rCO7AxZJgW67o
jR8yr7M1dBOUE0SOCm/N+lyDOFw6X59r2WO89tRQh/2IMrDyK9t6KVnHEGasElGoYPwf9VpMzS0s
V/MkjoEautvoOC2RQcO867Ni8qt3X4b7kJRjqoi3rA4Dqsp6XBaSJIAvW1u8IwCj5zfiXFp6Q1pv
toz9KLLJ5yQM6zSwlk1cXnrLRJT6GZPazFWNodeY20IetcHWpGxFNnu/4Lces0gfcmt8COB7Gj6F
ZI2hfkOteUFWkMQu8/yMsWy+/SoCueSYJAW3w8wTVMIUcjkSBa6Ega6oY2IxrEpV3oX5JDe0L8cX
7WhnCgm66Itie1zcz3F5dhgPxjh5idKOYctfNro4EaAza1fr+OEcQ8VGPyyugGEEA+Rrrj5vhf7J
twHBBottYF2RM+847TuETJ9YWf9KRrA5/VSRB/zp/TlLSNqmrCnNLQ7gc6uozV4cirFbMaChiYvJ
xvpQVlmjzAGdGZTBaaJsZyuVeWcmfnklvourPNRFflfQ+n4Y7Awx8YAQOxmhwh4MikxNNHM4egOi
7q4okmE04QzWKx9Mh+q1gO4BF3TAsBlDNiozGHivd1rnTSE4apC0VqwEEWklPfje5SjlbT05umtK
lAh305m2Kpt+ApassAy4xny+gWUbs8oEUUbjHSqNb1wBn6jIBkWJuoXQAeiyFMB3o8fQD69yxKqq
smz0Lm/nJR9v/O/6nAiBJ1/awjbW/AiCCuOo9HpzjAXX3kR61jKcaK5Msii/9DoOd0yAJTATu7CX
jLB/HJfOw/m0PDgjFC1grU9UaajemGIjP//cm95T9tPVkX3V+DhoO/62r5tHeycF/G6SlGnICU7h
sfye1pT/NClBi5iDAwxJJczy3mIe9PF5Gz4bBQ+Lh3Tu9wbQRp3YsQU2jDsKAbbRQLA7sa+O+f3i
+1r1nWJQlN5i603kEMbeIzNWoVGVJTJIJTg+dLne1hSfyA3vjASXLX+vk9fB/CT1x1LzFc1YvPOV
JRsf54F9YjWz52Dec2GPg6K3qPXUt0nTyKhUzwcnIV3dR2PMD8i5R6Pn+rcw5pi1ey39J3vEqIqE
ZXZEL6z+hyNcA13ZcyTNp583CzKjDJ//cTRxLaWwc4wLt6Ehv72NlHnOrcCxoZKuja1BP6y9g3Ro
pwGI/qZR+e44OGIjuUoM+DzqcLoarWUcPKHwqlryuhwMYPMKalLBEoiRlIuuqW8i68V75U80aLDP
B1/SJ6LSmGC9hy41XqVrdt9cNRMc/d2mWe+G5+WoEtssjHV2ijI0E536El2gIb01izaiH+Onl0GY
aEtm48GSdc0xXG8yBXwZBVDxI0+cvUHNuuwrmX+lf+LDE6VaYccEX9CDWqYSKJ0jvPuvPi6fRMhb
wmbanzi56MtXaYSQzPRBcs91cavkvekMtO8KosuRU7jCXI2XIfh+uTstvp5DOyTkQIuc4wE+R3ZW
esmQRuKx1LhIFKkpwuUE5I+5VwZ/vt8RMPEjMXAit6KhL5opK4AtlGRoU7vbmq1jDMuZ/Rxzve8f
s+VuMwfL2xd+TPd1TnuDSpz12cW4/AKkx24L/u1LCINwVuBTWNfjiR3clPw+zjHgmFTQ/ZZGVcab
HBdsVO8W8382VDe8XAUwaIaQT6gIFVJJ5dFVWcxbSA7cvRGk21Ay0Dk1t707MGU0W9ggCOL/4O6j
oyC7E6jAE88r7cjVlHVG1aufFI1PmIz3xb8DvDeGFHVa+iUE/L2pvh1BZVLzHMUkVQwHs331g5Um
zxt551ygelsm9nd3b1MuiNrlcf3Wcv8cgdldw12yB2V9K0OSPg6oCpuxuTO/RSkYJ8+fBanHB/N2
gDjotHICBQ7y0I12gvLhjYRGaU0WUNyfU8N3DWEEKGhsz5+rTUf3XYFYggTkM78knwGd55yuexg9
Ya9/39ftCBCVbyvvC8YZFx/lrnkJ/wam+pIK0ffCYQ0eh0/V5vflCX4vESC5/K3pj7yhOsxbvCgB
qHxKZd0hgQLnFlFqMBW9WtGN2XXqXA/oezkucR0oOiT+qvoShQmoXJq79AVQOn3RPZGdRw8WPhcU
r2bDjkeoJqlmOMx8NICWn7X9maYbuypjWfDe0hCUqkOhHNW2pagqPHBIpW/FuaQONekbCDuNiqS8
zzqqc/ZHmS7/IWDCoEiGH5k3V6oAs47yVfU1z0twqKPf5QonOFHS4DYb172XVBBSuVqpi3IFZG+c
s1yp4lNaaJ4xb6U+DxSeP0WdowXUVYFQfBjjfiaEwdG0uJu3xvif2IyaL7PyLPrX3VmWRFWslETe
HCDepn6ZCvXflUclJW3/SNtLoXLV2RxKaU39LrGrvahjUUeTJ0fNeZWFl3LgO0/qbauZ62m+0uIM
tceJNT4+Vj26C6Xnvf/w/xYwelYR3IzjXLUxO6kfr0G+SqDBSpSM+fMboiIDmZz0zaaGT1WlupLG
8TN6YtsPlJOrrZOIeiPEWEujTaTj8TcbMgjboJFK0iI2y4E70cToIPQEOfC5hcWSjoSdiGlgpmho
IDWIco4SY0dPHmcSbn5Csqh9wtXi4fheS8qp1R52jdc8Ujv1/N02cYfoNn0C4lDwPjXYTOlBKNzl
na/8dq4SmxPM7HqurdkCIixBWvD7CTVqC7UZ5S+xOZTyw0kWy5hpXIgrA1q3vjIUQZz8Yb93Wdsq
ZN+9FMIZ6SJIgfOJu4WpacqL/umssef7b1wsbOd16rNC71uhhSnBZOOsmQjkiYMW6d9qOq0ErUA5
0s7gylg6dsQhSfj6pbnwxYRRLvVXvphZA8N0axH2s9dCs3XYOD2DJwiZkFnTZ/MCYZIU+BGRl+RV
ZYafioo6NfZtt6DRQAkhJADNCYTR7Kt9qGswV+S/Ezbm/sNQRYsZrmQLzhTmLzbPYmb+wIzSWVxM
fSNhTXJ0e/J9ez9Fr8R2XZ4omZfeJyobFjues30FrA4OthbahJOqsW7YZL6gHHyghlZuyDGaktY0
4L9DoiwMwHESI/dlLuVXmQsYPLPM6NHK2lIo7mkWC/gYPqYE+EJyCwOj2pzDPneQE0RmkMB3h1Qj
pVTrB6KXjCjmdxV5164ro/j49nP2We7lledMHeWgYrq7R/wMlsa83qqdgWxRZ5guoiedAFIDf+k3
oGB81zVLd6dB3OThmfK+1sJy/yE2qdX33Wi+iNMEUTzXpkWzP4PQ4U4YDcgs7vyxGumym24fpCe0
okr1nw5c4axTrR/eqJ2SZj+JIK9+rMcLdUI37ukgX06nlLEGX5R8bim3/EQUstJmzQFAHLepz8j6
vP4/eak2+j6PVspS99PUrkYxuU2hM5aZp+65QnY5aFzfDWdI7a7/mM6N9Eoyip1jFd3KKva1Qt2i
ZjocBQ49Qy+UryOhC8GrBdkI9S2opp2oKcAMGiOypSgkawXKU97IUxaU7qO08KgjJmx3hsfoNA1p
x5OCJ2Cny9EyvuF2uWdIrC9w4dZP86V4oBDjMvwzt8u6L5s+m970BgYzE9Rym9K8tsl75Sk6G0B6
oetGmQSLnBE6JnzRG4DkaTmc4lmOuvvVx3sEb2nMx9+sTLLrC5cZ9ql+hxarm27fMp/VjJeFCYDn
SqTEbV0h6YoPr15oar+VO9z4nDsB0nXIhoXfBadSYfBA/XCqHGi0hdsbOKDGWNGtR+khlUmKiOwK
FPBxd3u6hthyoyByCkJAh5cB6iVpn4cP9Hm1rJ/nDX9lGBKZVvs1Cjew1FBLsmIgQYmpa03IFTTP
WRY8xrSAviwKyfIVgM9kBOWVEgk8ah94a/4G/eyGUtejq5147MsKFWGOyZPZ/WJiV9Ucx66hwfQz
paOPQZp5FeCD7UGIH7Zrkk0wL6/6BfwMxyVF4YF7Gqlz/6g2ncgyEE0cAeSKjwXWtoi8Bfsgh3KV
PIagwpn4sh6Y/EXoZZ2U0krCMGVec5i8UN8pRNlJku5yn4JX6erxjRc8YZrMl+TyzXqA0loSFu9b
uN1c+4J165NnbGecTwtbNK5pLr+qTlsOM3bCG+RvHt3mbmQa3bMnO6eRC61rnW5YpE+H2BQra4Qv
Y768CNkkvcFztt//sArurHi3++SvdiLeAA9WSDrJoNKYoLz3JOMYawMTAhAxNXI+3KmdBno6IssI
7LTyP4/EMTplZu129IAuY1Dl8XNEeDty+GB7LrPoPX9QhIP97Cpk8HoFE7ZADfcHv8iUvfK7HA2J
xtvKSefOrAo7c9JUth+F6g+ygBb9639XrsF/lJk4tqBMSlCX4H6T5A0l9VhIR6d/wsUUsLsNC0od
MtamoCP0oesgzfSDfXtUM/lF/4sN9SFHML7/ML4OyHfw4wp18cfDUIepfvNRxe5KwssPw5xxe5RL
lg6EaKTrfEpGuMVcCCPY+b4maEKdh0wOlSqFr7It2vQXFrBKWU8uqBtQ6Q/qOTnsq1NhhRX8Bkj7
zhSiTE8GQZCobHzEfoY6wvUOkuczgqU7kRrx6PdUukl3CpiBcqSeNWDin1kL2nsRcsOxj9N/XAae
EIUguJGEL3jGl57jY0EmJJWNez3UIvLi4kXEcex+sZqMXLbmrBpAbvsl/2Wf1s1+UtT0WuT1oheT
9sXlM0b0Ihfe77SfAgvmSbHZ1yfdwkqit9DvBBiM2e6M2IZ+N2n2K2hiEfjxWV6RnS0AOm9yNTsl
+IoMDwCLf67qTC1A6Xqu7ViAsl8HRfbLjNyYFwHqK8dnpOF5I09kkKqLXbRjk5gflE+Z2P+Xx5VV
La13Xgi5PBDIfRL1yvCrIhfnXTUigKODTWNnYFTo2UGM3wkgYU9wYEFos8o+tgGmtQefg8uS7Lsv
Qn6cFJH7PJqWzugEi+fLmcsJNQ2zOz8XbRmnzQsMDzRPZXQKkpwWmunXI5oCz4iggp6IKhRaMWPW
kQuxv0UQnplvi6+XL2HnwEMM7Pw6wRhYQumitVE7OdKXSMePrhfNdKhL7lX06XqUL/v937ZfSU8k
lPjWC/uMrbJ+vDIuTZnxsT4qok2rC7vgADhrsBOdcbDZWYd87Sp3+HWkk+T4SPIyNoA+08peDNpq
cpWYfTShliscCgAJxcpLXx58oBtYC65m7UqMbYmVo6qwtVbRoCeICrcZEcNesJFKxDkgZyiCe2BH
eXiQHuHwRCOpSErNupdVQ5YQAAcpXMUMznGSkM7BWmOU/HnyM2EZQKcAzKXxdv94GMhJNgIulE/Z
znkJuyoOr68/rt25C1/iswisjP0eVtyq/lyK9K0xsMEgpuDPZ2OA5fFdbk02kBgiAVkql66QPf7R
7CvCDGQfnfOnM0ec8fPynbnxW5IHTp/Z1UnlU4EVFEKTTe+xCauy4sh+uwhdCN/nMajauZmZZ13K
y+ZvihqqlNCqGC7zRGzLRoICsbNnfc6C12hULmp1bcs6NGz8gD/0heP8CtD3oVP8vaPZBDnp+imy
DDElpY+iZ8mVFW90DRZL9vDUCs2vDmpESo6XZB7GTEzmGZiEVMelb3zRC5Hwu6MjFRxzqtzazFvC
uZvzRGEryz5v+QSEdAUrurSr4YrKgyUG3CAIz36WGgCMs8z2rHaQl+nGlPygEoGtGGOqW+lY7fD+
ATz6pWQlKCj11+1JY2fhGUVOylVxlfgx6TM7Oh7uqRU35VzX6x4vnIHs/pwZsPTXylGimGmLchSv
iGwqxd+Japp4k9E3KblLkDRkbcX88iDdtdN+Ek6c0Kd5i8te5wUXHCQDYye0ErCSvtDdTNPrXe8a
NJeDMes3WNzcYqW7yfh1Bn8xjlTAVuJ2dBPnj16CVzH/Aco8Y17rfFbRt1msdZA/UHrpzuU7TpcP
G28o1r1LlfV4trmAVRxp9k/bd7k53FcruY2ojQypfPbIfGFPfnmSi3wV8boXGZA3nCdvIO+4+x8H
Fo1hv4dMyQA8bWsz0SIw5DnIpnM/mA5FladNZbKu5WvMNxD+UCQniOu5YVLjx+WLCErERNtuSvn9
zyVmtECzUyXu6bWGpmt5SNI3S2NjB++CF3axh7kOlNLlwXwoc1ZxygfllAmfQPHt+MtHK2AyALJ3
8OLuhn+/QaMaSDJsMMPfS3vqwIytEgMULPLTpe3I2AS+MGc/wdgnVpZd/ZxErNEN0HhxsAeEuKjP
hNUC5h7Aapna8l6PNdfgNjdEMMLZxh2DnGF00m7/E/hy0CQ1pOBwHJtc/xcvOkObOQoCPu4lp9fU
bqmuMGWhigufS7pqoSWx0fTlokd79e6ig9GnQ4NYN+aisRb96JdGuMNi6ItIPHZfNAlag8DtTGoE
f3dPyve2I9q7Ve8+OrMqQGIiZDssHaGKLallzSNA/r63UUQsbU3vN3xSOiWBNHouf0kW5cxrsvZY
L7lINRKlAmOTopdwwOyPLU0I65r9RQJwX1mOPYIZtzFVp2JgrshNOEG2ZWouLgOLIGv1pb6yZy6c
Gyeod03K86bguaUZkL5iJKEBB+1LWTs9DJP8Abhzt7QQXVYdgzFZwAIWlFcH6npTcKay0U9EI3k8
BjE8XjPWYd1mdn31aOHYCLyLoFED/sy3tHpr5sYzpVxY1CM3QXOPuUYjwuUeDk7FGBhy82ax3vOZ
GRE4OZYP/GK07ZZYutmihXuvzERuYXkadNFpHYtB1uq1cBflxAT/I0WEs/6HGprMxcivcghuOApj
mbJ77oqPOqGg1vwEYPR2q3xulrxd25kq1PkGSFop2noy/g60OcE1vM9UIR433N4fk6RfeASCxjXi
pMKiC3q4dyIMp4aDBs/6g4XY6SatXA79VBKXPeB4LStNbs9mIBx8TBny94GA/XIIylPQxKjT2tPt
Fs+c9/7qGAyY8gbhGR4r5ncZtfr4+z223RJHvL+kNSjTVyIqU1kDHr98aUgMdfEMF9+iQ9pAhNoF
8tbd3lhJCxndH9S8jtshaKLemjYmC4gzWhNuJN3ehlbPq4mSa54LgQRoACv4ofI/aar0fCXdI9pD
PUrg5++DBOi/yYrxnk9UXCvb/z4KV18HSzEl4DR74QQWW09Go9Q29sL08ocj9upZyajpSc33LSCC
Eyy/Oo8FEecW+XjBRjRPSADQHXDVYYFwm/fD6Py6YCzka46d2SCSbZqH8dn5SrodeCg5JV8f9i1E
Peyamd6Ukt+DpOxkc6JXvcNJTiEKhtRfH4XSLEZNB52TItNp87H3xh8BI5eHkRGe+Uk/WJiKodvB
UrU/ufS7n0d8HnU2iiTUSG3EsljTNd2gxuAWbIvt3DwJ4qQmzKCkIZjVkSQGK+zTQ92MDEg44nID
bWyCUiTABZTP2bkpjuF47GijpmbDM538QlBoSkVKaGy3jbKTF2UJC+ugtzua/xm9S5DwIOENqqWX
VUrFjXoJeNSIW3etsnfLlhqNTMNr7enzZgZluXpmbC+rv0TyDALuyCOaik0hJHnqEaZGimrvlBeL
1/YnIeS0fw+bOkd9Z4Fa1df8FjVzGvdkU/9ilRt0n7mFh6sAA02slmM0Ws11Hq4mtZ6zQabOAL9k
sy2ACLlEiSfO8c7DsrWWGGHH8iaqPzLFgzatHcXmRd9ovb2/qaC//S+uX/pslDCUgp4alR/QmNtb
UDx1gC4zQMGBKIgjHVyB71QWlLs/okUhC/emZuQdjWOtXXm73gJ5fqX8m0NIsCysghDiz2JNOxl7
Qv1CExW2gIkppdJa4BNOBGnXFO4OcCon5yTtzwZg8XrEvO2H7exLBYUpP5ZSzniIaqE1agROXCGk
ZKbmnW6aF8uVnXVxFHqrdtK1hZHieFjMGQ6l3nHNPNwgVhg0mSe+A71eDuqYdKPbMV0k1ou/zoAv
LvFLsYzR3IRWPE9A+7b3FrwsvP9Ehh2zGc1WwDtMbsvyFJ+GpOHMBIctYtGZDOozZ4qbu5X6Rxm3
CSbvlQJpMHKFleb99Me+wy9hA7HKjUVtYGcjS4z8XCH2NswQ7P+CO2vOrsx9m8FHSxnZR0hezgzi
ZWKvDRbyxUrVe4T2CSVaxoI23icuNQCrOl/YxTAkduink6YUpR3iFAikf4bMNinVA4Dh/cTJdKw8
HSBFeDhB77i+dyj+PvwASx+wNpeOxSurig+DzS5rEYXmYTsSq3REg5f7oxJz1+sj4AE1FW4pRDdo
fxb90KozDGGoL/QxGUD+Qcn03182ZCb7D73dCYU7PoVbSsTV+ZKm8yMwkxw90sK3edLpmgcP7iiR
fTRc0wmjxArWmRbFWeMu68W6hF9FTUqGNZDS7yuEAlF5izZImhX2jWJO2JfKcJBcRNvIcTHTRGwt
im248MsPBauQ26FxPWj6ImBc6QsRxHsEl50gmfHTl7PbHTfLWpH35u5zytZJFF0pYlEooLCk8fcJ
DbYeXGcs0WjC+RshqorkV4OKLt4yBn0U8++IONVyn+f1yjxiKXrz+UZZVcPDNK1InOVs5vmmfICm
vbV/ppOcg4yluURAsoZc1sgAUVGOS3wy0BJT1CNLn0+Q5A4yfF/tufocd0pJLmcFdaaZG/dcTnKz
gkFbgaPkJGkpFspyHK8e192uLq4afzKqYUxqylrXszKx0fqu1/QP8JdC+CB7inLhDl52FzQF3reW
SIQXPJZR0gghlTa5s47K6qhhfjO+1+1W2YVDDwq/uC/nUi2Yj1A1KSpuk3weKf0IKUeUbkq71M6o
bmgXv/ozl86XC7o8yW1XVghLRM838cUw0IU2nfs2F0EtjJtas1+1kS4AfVaO4/yhKSAr0MBrgQsc
uvD22K8CP158WDjzVrtXh2rquQYmp5RyEatjR5/JWNXikZDdYZCNZBQ+D76vv5fRBFIX7zmhDKbd
DSrky5ZW2jcvQlh6CpJeEzAs+u5Z5h2iJS11fXkNKEx1QwX4LsfuQwTIk2REvLTTIl1XUFvCqnOt
nH4dKBHAIMIFbZILZbxBSAPDo0Q7RIqcgzT1OWdOItsRBp8gWZDv0kYMF3VYwo4wlqUZk/Wr4TwG
BxAwRY0giL582i/xr+OSAFByRF8fjma7mOWm6WQ3OG4mKEq5XeBo0hrPFhn/ZIRFKLXYqYSWF1ct
v+lMiFOtsqEAxyihgBOIepJfoLMTheX8YQW2uzIMjhdb6ILssMsnC3C1Z+cvFn6d+2hgEaC9gyEo
VLQhergY+bhkg1PtQhLmzxVnb8FaVyHcbWSaa37eYraCCXPC34OnMCfDlRSk58KqERq8L3UoXjGT
08PY3w3bM0mS+TMtJ6VFT8jQbo0sJOHuz/pAquOMlOBrBaBW/wfQS03NpDJLlurv/kuApz7XuY0Q
zHq0iuiCCzOGODXcHcuR8XzSdCn4DiGCSF3ZmpzgHP62EH6wyXB8ib/GvFZN+oljbWs1WIaO48wI
86wVz8foxlVKRe2Z85qRTpEVbXKh3G77Z3sAGQugnecx2bsqzY6VbBRgvmjo7TPG1PsDEezs8sq/
K4XvsBl10oNv9QeFOQzCc34YqstpYNcP/2ejekgKEGe7gRJ7jgienTc9EZKYdsxBKgqOjA1ev1Gm
N9dm61c3o9uNC67rTHmJ75ai6C7U+A0XLj8cPilo9arNhPSIRdJGdLqWhJYbWUVV5HaJlVYbdjwi
xdY3Js+g5/B/glk4/ij+FiLm27Kn0lZi1gTRDironN4ZXFn7cz2knn2E3v3sGzZf6ksDiUAlcwZ5
mwCp/XA60IlouztI+1STrFYyi5RShuEEzVC9g2PBPS50KyK/W70mQylgRuBvj5txKSGtHUyUpLnP
RrLpqaURdF/1waCkpgWx53K6kYZSVbbdmy8+kaFa1+0X1OosIs38AnUZhcX6xv1yrZv1C4DcHl4O
o/OeGA1v7d1GRRCvpcZy+OB/YPXYPc4NCMcfGO7PpAetrU5/KbU3q2yPHgGvKxMqGVWUj4+pjlFe
3GLYIRq3pmVHTNGuB4bN24NBSOOJ6xczbqGeBvn7RMUb3o83qngjoKcOhjqfEyjvRpDVo4gVIoDX
YT2jh9iLrn0DLGbaIpVCCo6VWkwm3WbD4DJaZF5HELdUnHyiVP5YTXZx9C/pHtAtwC99YiW73jAG
ZdGLs/82VshbKM0vAUG02rc7w29cCTBRLMMZcEwLJKhwgo7434jREBAOYSst1NVH8CSJr1ENnnNj
Np5L1cnZT2fLOAibpcoRogwbqnMrXvIjYPKz3U3pMxtd+1c67Zot1U/ufzsj0RZEBoyrCqHi+Tme
cjaujlK4F17w38evpD4kjdp9e2OTkv/EgmBw1DlDjFet047MdAZaSX0ifVBA/8upv6XtQdG1aCg/
QQiluFzlK/QoxTQbQYHvbwwaVejWqpCCdIUomEbiuOM1tj8BNOFMsR+dnlaPB27VIs2ljIVZWHmj
aQ/Pi/+8Kmg5UHMA1DYKIvE/6LCRLNRJWVZMV71RubOYE1HbugO9ikJJ0tFeT49szBpMLgGGmWyL
RrGZegPwQUuh046VchDjDS42IZn7xNBx38F+d+fgO6DyKpa/H8Be7fyPt1evFZRkxpWG73BgzCyR
MTGcOs+XlzAhTQDW0A8SNBh8e7uYCH+vTuNykq6wFHOZTz7RM9bSn/hf0nwCCDC7SEU1qW9SVs1B
cWK9fSHphtR8J0ywty0f7B10b5RZ/2nZZJ+S/6fooU7PKm2F4Zz563rL0c46RKK8JlzPSkNMQFtj
ep4m5ZCj2TnwXgB9NtXebTXj+9Z5Hip7lVsAZMkLC30NhV7altsKpRdGClRlmsOmlGXqPsJpjGSK
oLgWYhNbpWyk53CEpmAQS71dmyVefwNQ1/q/U2ceAm3xBleDPRVcGIXCtoxRv3y42fgOSjumEmK2
FgfbAv8BvqFmkq4kSzIG7CP/FnyC7iJzdHusvFHZhx63MVIhxPe/GqpX5u7XrzIcqY4G9ocGQZEI
Jqn7JkhcocQWYvN+fxoRBDA4kXo6FKhBrfhmlAGE96/P5uF7vG+kF5w3tYBCcnkH3ZkhX28f0WTw
j07QrHVP1J/sJo21rSWKdqTCGSg1TYa27A+FRPTRnK2LaTIGjrh/QaFrK4joucUkz5aydqzhMuSN
UNROgrhjjIm59hLD7tX5rEkO7MB3CFri89Ipfc/n6rgumB4f4SSJd7Kx4KNBZmj4QsAxbeVGtJUg
tD07PMVkf1akDUrznqpVe5tolLYVsDqMItQqw6/Xb5qG4T6i/KMgoygpxGyBgBnjIDuJBqrN4ovL
Qq14GRZLVzvyd3Co9wA0qo33ATgAFh29rsUgGxU9ADLule1NDos1Zim3bI7aEbBaC8VuDlqWp6Mc
2R42Jk/x0Ec1XGUHwMvmiUx21UYUCGS6aJUa1UN+1ITOL0swLNAKhiXsReBdrcoXrp+896VCrKXj
IB7vfpI+jP0/TG82hG6nWLMcB9NAaDgTyWv2fAYbHM0RwKbombYv0CxVPlI1GLjQcKGwmeji4Vzd
t79xoT7w+FESS2lGXDMvwNEwrtvjD4sD/KK+uIOmplJhKOJzQqb3Ooiki9UY10K+T9YS5ataw4u/
FCpLVi/2xmzs2ivPdlDoVns/yXAzzTwZdG0MwuHABKGjiLUyar6i3Bg5ozig6OlcLIX5G4t1DkJu
T4AbvrbnnVhe5uo3TZRmYMqL81MkMxVF4E5em7cy1TC2tW2ucVTtDh1BdDCo3ZUZmzPXYIteAASk
QI2Cb/6ms+uNUcOObd803yGGlfOwjUovOFFIUHbra4CJ/HwNEcRCglfulMjIKfePoGv4pICbW3Ug
SvLKtgyTmA/U6wzJEGggkd+qLwjuxT44SMaCcHwqiuVbWJAB9oH2Vx2HRV7ZVG18rkD95f/OB2t8
vR8pcx/7VK/u/xKfmYYgxg9reyG4lb9AcWGzDR3nl8l7VifC7b57ty/UZW1hag1leDt5UXKzEd43
4l6ckQB2LvO7+ApczbHHxEZgvVMejn0clIFNpOg176O1gPdEVAFkPLa0CneD5ileqFSDf/pKHMMo
+LhbrL6cnd/zl/qt++C1gTwFs8mVJ0UfjOilMUK8TG0tNBoyBSb8lwR83/yebuNROVyWVFMd3uhP
TU/D9iDWs+3u5BPrP9LX+8YREOEaX3W1pQ96CdPiNF/j0edSz482FKuN/o+/y2+lk+XnTG6U0reQ
EUVhxH5YqDdLLABR7GKfcGcWm3z1b57OG+EdsqU3LwKfjbXuzlntAAv1/ShJXUIHHaaSjsluUuw6
DnjwR7q+3iLUyt3miL4zJzOcHGF+mYGEKUE60wdvDBxk2W/Z/oUtD8lV4+QaXWhtFOp43Gv6tpJX
2M7FgasbPLgEgV5Rr+LJulGomDnFVpjDi2PWNdyifROZsd9pulSdvv+K6KM/sIYouza8simPsZ4P
Fmuk27xxpRonBOTI/8+xRcv0blWnMqSutc8UcKlwZIsS8tPGIcj/I4iLMLGeoJ6Ra5NSXrrzBTsN
1H5iZKV93oLERfgFlBWHbvgfl8Ebhttm2TP/7y0qIob7hc5HqdwrB9pKUYK0vKTkng4fzUsXLss2
jtPycKu+De6ZfqrklWSLeyUbyawCj8fS0iETjBkVbMBpre2lnx/bkRU3og7Himm2r4ety3tNINRl
MAflLBSC1AQ9I5CNNO+G3wjNtsWKvzkGFt7uy4EC3ihWxCa/RnFTuYhA3N5jKKRvQOXmA06KPzCb
jjna1W20pjVXC/JQBZZBmhUDMWJH6mIDHjd1xwiYGFbjzY//8ytcGNwVP/Cpg+9bSRwnfukt8LAM
ypzgVPLy60lyu8Ajdpeu5M7iNwW8h1DJUfzYwvKmirV9/T/kF8sl7ThlL2JoMIG1hNNXjyh+MBuH
K6Yvk1OGbUAayA5n6nY057l7eWAsGgQMA07WFTzWAD3CQnwIWJ3cABbiEdgLfblC1bzTTwAjXGjh
OLMB67tZCPfvXOM9c614dQwt4Y2IPtaUAEt+rKH26MmCGjeA4NNU/2WxoKOHkdo78ZtmE0VMcNuV
ayAtkzK+ptmg+EmzTBtXvIMUnEgmUgOLy5noGw9INgwZm24Jsds4p526doOGm5+TzSVb6EXUmaZu
iAiXJ/uTWCN3r4rEO5u/Uc8cwX+YahNFIFs+GjD3bFtq85gsL98eP3Z3wdbs/kN7Lhwv+95TYsv3
NtbA1b7bo65O4/WypmEFwZlQ0qEYuGEdZad9YejHvOScyuzuPax/DqK/ebs66WQtuweaIa8QoIdE
FLQtembxLzUpdQlkQ2kKv/os/a/V07p7uZoKqxZJp2BQLdk+0irNXzk6BCEwZRCk3+T/tH38RETF
0fEF89llk+Q5mtM8jWpmezUIhPvQAWtC0d2Km+dirhkLzUsvFlmNpOk5zaOMhVSs1H6Wne6aQMJU
HJsCTN6bN7u6wDpO8oWH9LpDnCO7/XQ5wrNa4GfX7JUxwhggvtRJKoVirLCcA5Vqa9IBEUQPxsZm
0mCic9QZv/r0Aq8b9q7ukWPVQruZQkum6AZa+dW9y5FVHEI+92iFgk4vYQHmjem8fMkWPVgZX+HB
PrAJArd0ZmSwmMtfqmLOZ9Tz9KRobh1JaWOcywvEk0h+GNO9awj+88pxl9xQUVWzqoAf6t1Tf8bw
8P07bsHFujqoA6d9HmVisq3haRQosg+Cx5BjWwehYAF4dbB4324I9NcxRNvnX+AgTROmZ1ub1s3A
tw7hvyPG4pFc8rtJF4Qh6aPEMScmwgtC01bwgx6lDCmildo9harWpSN+boQ2xVqaPMXrhi/APFLE
A7T5GvjlSM6+SE51X01BXs+KnvzsboTcSce464WPi5xQPpFNcmudmr72I+w6KovTHZHSL1Wa48PM
1T1vxXJH4v2DH9AGqb62PezKMC15bFsH2BEehYAqUcT4zKDeBBKICkhFkQUMPSvkYku3FlyRzyPU
Odj1LWh4R1V6J8E+4m3/YoG78g1xiArieIvPWl9Gk9eEmxrfgvOEt4hObLS72EEh9ol2OzlMc3yl
Xbve6YsYfVR+1YoOv7DJ/3Lj+iqRhs5Xcwn/QJZ8rerMGrsfro8ShMGfaSGBUyK8kxqXEuD1VgYl
nrnpbBtgUFz/MRodQ4GQ7f7p9fpboL7g1MIIGZNZHoS12UX5+z5jbVbfr+wvsao9N2SUy7TpgClH
QAkchm/vOGElKXmzqWkg4eMCebRPi4LS060CDU9H8O53sUkzL9BtV2+CwHlIfIbvJ0V9mQ6Vmzn0
veCu88nJ43dBR7qvtWS1ho4eHda3YGVtEB9V3HP77nZddG9QLTNfBvDn8Wigi/I2/n7ixhfKQYmP
sga9mK9rVmJ1UL7M5ZSJrCSAujUak+cdNEnlkxn1NvZGoHX9QDKBZmC0KBW0un0wg/7gNMX3iIkr
nMVchWGJDAZq0faHWQ+nEIDR01NpCjdmdLKHwx1/Jvv3Py5J2h+m/uTipQbaWNXvHGIte3jZm5z6
b/r62GIGupS5Ih7K0qmSd7vuhYs2XOKLhBLcY9X6gBu31iufhF7fg8BPOG+NPSrCUxvakzfe+rZa
zhuQ6STLUZ2oIIlIllZ9LgPFdXpXTzEYWT7xpGxoAW9B5PSr/kiju6e4MyqlzFKNCzBrE5LGsU/P
YJyrCJlJ1XhC9jaTydZzKIaq0LoDP80VSVTzWS9F27m+BVcwZgs69v4SUGklK+I5ito0Y9DBURAk
P2DvcTH89JBIVRnR2u1AgPDfqHJi4y4TmGKi+jPifLU9LJ2tBr+/jecx9EwG3Mo/pMIuk/JtlZOp
K0+5Fg3Fa7midHJKRxTMCRxnOpea+P+0GjnOzUo7TrJPAmA5/KTyipFnE0xJYZ4+ZsApVgZ6NeBh
gRY1SLwKzLcR7fVkWcT1uHwNjRFKTIH5EXH8d1lfm6DH33xF6tamIVjQ78n0ZtsGWzIa+rnLt/73
w/YjYcNDGPCztt68u8GIQQVJslQiulrF6drlXS+sro+5Q8lEJt2EDw0IONEf+IQKWfiIShnKBlYs
IAsCriElngVZF+XsokMi/l65IPc1ZQj8QgjzDeN9gc1OPj21Ir9JLzEj/3ylRTjMfSLam4PM7Fn9
W1A4asWBB49O6Ku5z81m5zjvOUkPPQniATie6N6xjZI0qrrWBTWYsyJFhhehOJlsuVIiBb+V5Dqs
fpJiVIys6hxWo9qpytWFsVq2ySIhXtEZD5cmzghDS/qjcJP9Dxv2rJM6idto5K08ehx9vZoDD9J4
aSSRNJ5QYzu6gN54O0knKnVGiZ1DpITrNa64c5Jo1NnHw/keuYsb11/cPxtzAE9UUsG6JIuzN8Y7
MpuXaruegckRjlw+oK4SAT9FZaGje0KNqJNhEFCGLs8wC7urLZ/xRATFo40FpdIDBWPMlVE83bBQ
ssQjsln7uL/WOMmT4+CTbEyRDGGRAJSytF9IBrbPD7dYUaDYPwAnTgV6+875FfHJKDXLSpNNmkrc
vtyls/Y8oGrz3hLj8Moa39n5mvOOr5rEOxvGxIiEBMLolY3j+n9iu9AvnCkHUsfymtKKHuBCr3nV
LBKDTYOdfE/eKmHRgqLWyzzZx0wIT30OerQMMW0Sj59Jc3+nZXsEWvazO+bDNlncSs3uy4ws4WhW
lGOGyFRySxTRB9q38v2eU4bKyB4U6zJGVCUkZtM3LHWFLXTL+oanG8cYjWT3vldgn7ra+7exKpTO
BHTepz794+tLnaXf3W7atZ23JITVC5XWMxdGrQIP+JdW36oHesVVJivnU7XDAhmObcoGo8T3B6b7
ujEOGaXKpQYa3DA/uPVhWr5uhsCuQgEPDp5IeXLpPBZW/CCoert62G/30GlOQbhi6CEoxHXGSsUj
6FiAAQdK2fAgZszEf1J4ZkzC71LK2ue1rLyp8aj3soH2nXgyGxn3kVL7lT7NlFN/HgT8SuhWjy1e
WCybEd5j839OcreMuQFBX0KTsIewEpHsSMO1MgLiejXEQXHeRvo817hYW65ZUIqmVb2HwE9FvhES
s6DiUm2PLlIsjNQOC4vZN3NNd36hhLKwa7r0SIUlH2KRgLOXSZ6Bq3qV2p2TKkgQ9C6zgb5yXkZn
OUN9KEDj3Ce3pkf++kFOYzEs9drCmdLeJUkVfSidT86BpkIbNPZ5fThVirNE5Fmmj4eRCCwGvG3S
klvZDepLU4mLWgNUjqSDo8880OcVf50O0U4+GN7vhg5ybbAkgiHVwqcWCU/l0sGvzJcQrFNBH7a2
Q9NT13Fpw7XrhkMDR4C1nDaBPnO4mWw0OLzBwGOS3LtqnGfUDDcHj2Xvw2E5PW0hy6L73Y6w7gV9
fgIPb/m4nvu57aoQyGES4TQsJv6vLQGDGFibXvgKfJUBjO/F4Gqh0/Y5Uo52uWFcqH8pDBaJtJcg
EfA7VBBfD3BAIXeeqc4bGntpOSkMBxrqh/+gQtpDlPZXvcWeHJFrVERUUd6QX2A1oIf5m7+za3l3
n+iLQKF3WSDPh7iG7Vr6U3LxOXNFFD9N8l22IMxVuGSI4jiOvkFV88vW0j5gfXYQIe12aG1U01U1
1i5baZcPpKruRFuLCkowI4/y8hivhxplUhyE9pKnXtBZMhWVUu9s/HX6ZKD1KuBDX8dJQ6wcWuDP
9vHSwhdLgXAl6sbPjqKDyCMEni6DqWjWbJ6A8U/F+U6dzjNp1kSaDaakTjxLZLz2axqjkD+kK53h
oQy25z8e1DYOEK+L50/G8TZ9xENhrzvSiwEBocNrdKOYnmBWV5wyIHtw3me9Rqz4wjLPwi5ezCz3
9LeSVJQuz0veTPPH0OsbCHS/GD8qdXRRvS1zmgG7hyiHIM2Y0tAzRtd79LGxaReIY4BXByq873IN
BVjBBbAMrE7vQ17Vo5/Q7ZBY87BgA80NwwEwxzBcX4j2JDZj7F8JXBps4MnYd/FVnhHhKnor8EX/
uzTiL+dBhTYw7hF8Gc+NbErZQte1fO2oS8/eBpDmksOHJD4cJYZ/F3lU3eJY68v1Sczj3sgsqnFM
SN5k8P27yLkiCUcj7LrahLcHftvlIvSChNS0KKhkYR6BwLra4CqniocDCYO7Yw6LDWRX4Td/rfkE
3QCDyvka4VDyRwe5xXIWK0D4GN3WP+xbOxVHtNygqfAsOIW0p/i9KrWsd0F5kVNom1GeuACYTzbi
r7TU9LnCHyUctNW32U1kDL0bBRFV+m44xJ66gB+0BnGB1W8mXpu6T/TOpOyUbUp0bcIHu7Nev+zf
vYxQ87ucdIjl7nfpDea6xV4HYamejIhMNwGyifyoL+kukJcn/Lb0FPF5SX2MHhIhPydKfkQdzLFr
Ei0vLxSOhIODN20KBnZGsp2yeUrqgF2OTY7Tb01A/J+4KuwR4tOVWhAvXy9Fs4YbJWeByCvy06zY
wxBhuunaE9ufI73ImT2BLT9ZaAKOMQbArIEIbFbYFwD7fRO9e8Llp85ASKTDz9kF2G2nQ1JRR8Ts
5QDcbw2+30adcjGfRh4vGnAk+Cd/vfwcpC0LhvmyS7ie7mZdwD3pXMbLcT/+F1y6a/3wpVQiHNUD
8+hE/s0Mr861+7jsNgaiweYWvHf5MsTByLTRSMi4QTRrtrGBRKLRx+pB9PQvO6/lEiiSlj+/oP7t
WngUMy0MH/KqKabztcBY9vYJmGOIQzKrvIoqDqILE0sLjMLCIVK7MfosCMxE7mj36IgRJh4Xyiz2
a+Z+aTQmZqtA6CyosxwAeOwl8byFCttkDPYooabpWqM8k9QDnlf4diARV6NKs10mz9/DgzRhiypz
NK1iPYrWrCcDjDJYpoRZys4zqJOFUqbjTpq5ZylJqUTqf9Yp5Q3v0EtC61GSmzGOcMM0oERpHvI6
MSsMgbDPD8BJPWiZsFjnD2mgLOykChT0a9cncJx+I0zKN74lMMNT3KKOBpyz5Pfpmlvtsb9cyAea
gvJ0z4JgT00PCjtToSDmjG3UsieSOAKbojhHhJZqyXKiJCUk9Q2cHtDU0nzW/cBYT/rnPwHQLbnZ
jB19kUBIxyCToasq8hwvhR0b4KGcSrVjp6tzN9acoHCzDvki9Zhk8jlxc6gf3SMEuC1oivIUtbxP
AsdbucfZ1NRoQ2RX7CvN2zfBw+bTsoe95I6NO1scGxD6y0GyfftGy8sSsZNuBD1hw1JCYdM6QSAl
97vPeyaFukP/B1Q0rg+gG8QtY+pGy8cIXAbVzcsZJhIBTNRlA54lT+0kLom6YgAAMt4z2cq8FfkR
esC2t5C8FQ+eGtEHeU6Q2hKvKY6PLTy0PyrlLbQjpP7L5DWfKwf4vE2NfU69C47sFd2P013asPjw
I6tmS23fQLKtuVwWPRd8FRuwKfShpwiVhQPkwzNsW+HRaDcbSFXt4DCfTSmBVqXmJQmvGPMVG1ZI
NN0YERYr33IIERM7RyVgDAbKgt5sTRpg5oer30AXALdMr28qUZWspdp8dzcBdYwKBUMa2d7oyA7m
BKXXw1pM279CO+hMxA2/wX349IGaVER2vhTrL5uaXDFLLmOzwdbzorb6HAk/i3BcFt8zlA3sj8Y9
1NKES7qd8n22C/ol8feWXo7eyMy9AoI41Aq8h+fQSgKYWcvcE+YQfwfxH//g4CiV8rmKy3kGaqr7
u9JEFygYA77vyrsnTgTWg0RF4/bXLKNdBg6cbTWZVaLMn+klCA0DlnmXAB1Bls3jMfBPF514P4gX
d4QN82f8HSCElploJjQ6ou9ZiQfA45GkmBndoH0t6jLAvlr83xN593rk1hYbbIACOimvkIRoLzSd
LODBxN3QpXr0iCQaduDCiHRF0MHHhNxg80RemRfEkKfs+x5YhH3YAgJkGKFPAX1X9MVgPEDnAATc
NIzwJKkdTUC54PqKKHmNBq07Mm0kNXCWl5DwHCaNb5Z+hiVgtlZ/JMGfpE/e7Jy46AhsSGGG+/nd
8zatPajUl1PVORzQelhyck7vliMTL3vn6HfQ6UJAxJSrB8AiO6bAFN6DGEnEYkJok+8YL+d8N9lE
2vvpqRfmmJP1yKTqY1Gtx4O3E7NA9fI2a4LeHvKOqd65Bhj+GeGDnBP9ukNvdc69oHTirTWDvovX
YbhbytT7ewGd8HH2FJ8sW3J0Bnr/9bsrwLnGj3WWz7bgr/7GWlxO7cBB+/sq/1O6vFh8mozIG7LF
RNMCueQDwzD4V3U9ixTMg0/87+HN/N1tn8EgYClMmiFH5EYU8OKiwf6xrpAcVEuVIZLYAkBTNZnF
v40zcTQLDflqtWYrgn+9zkukpN3ljV5Ob/lNt9kN3v6CkP/2T51uRK0/3wS4U+FdqugN3sokLsBp
W2Sam36Z/5cRMXqylxVu7aTQJkWZcTomP87ah75OARRicg5wRIkBIIc2SNHsTvGr0OvAlDfwwOHW
xRnipoCykH4/xfafyugJTLskmdt3SyhoCyuuRwsQvZoQ7C6kmYsI+vQLFF+dX9lCGFKl2Ff7j/Fo
HBpJZvZETrLq8qLgkEiHEyyaAy5rdSEfIHn7slhfNB3exOJ4kLeoasAFCizvk8unfA1dRmgl9LJS
/yaN48kTYaijJdlJDDG6ekynVyQv9Cxdgdaj1UbYWMLHmZrU6eyyvVxr2/LcyWD75pQrYpuEvvJv
7a2hosbSuVqYd6Sq9lwyqRCUFdGbXbBArNdiWCik4W7RTCvNUmzVgGuJzd3nkEtd4vP60Iy/hn40
76Gq9ljY/PjJiCGUxyehzqVzlu0o+Pl6OPQdz7OzOj2s0MasbT3wWTG0VotNuDLi/n5CDHwEIzFQ
mVHRvsqMkMh64/M7SbvJqJ2Ia7yT9mHtxdXXIbDtWDUQH9raUvnzRLYBXF75YKGJ9JJYyoQUi86N
9Lj6UAv09fuMVRUd5FjJhoRfotKlrWjM242VIx4pbjRugJe9JLfICPgHHFo65wpPgPrQGP45NhiZ
/e1tinDcof4S4by6XkHKijzicCBueT5MljpwBvAhhvWPjc2OuwIc+mnIXaVQo3oS1xhz9eIztIvv
yiRp1sBRoqt8aN2IaTQxgg9HBKHDlv9nXgz08tO1IREysj+6W1WyLEoU0HtDJ2XLeqDVpLexjlhU
pG3Z9fGJeG41np3y6/jKX/II8WDMlB/59UjesgJ5O+5mxGb2owHmsBCu0eB/1d0oq5QK27XlY+6Y
uzMnuRNMDRbLyUVsu0ipnFbnmCCo5tuowZI4oxZrDGOOqa4aibxPEuaVFZcObosr6bzGfDr+PEcC
Sa+wPdXdd2+Tk8Ok2ELQB/AOvIkGTQzEXs6tgF5T/j+8UoCG85Rw2jZiWp8mEZC/SXm5eTkWTx5L
vJ0MT9mdPwLgirNLbIh8RUzGT/6OQFmN6/Y1CqGvyZukj7Pihw4F/PZnwAesw9wLNJD3faG8GHx3
NeL+DE0SOBLOTsqSq/7ilQ86zeQhJa9rwzYeGn+IfAs4GzAeC52oUdgbkJUOT9bcW/7OlADHuNiU
kxg9kgMwMvNjIUjTZedkxnzbRQfAt/PgpyeJAsC1p0C5eIAgYD/Zcs0YlKwcY2n0ZFaertziofTh
L60ERAJg3bNX+g+CZuqLaPlzNCJesQiZL0QDBrxjwC2xE6SHefq4MjlommTfLUpeOQrQ7MukUpKx
/t4LvnDhxVH3bZcl98LQrPwvyBsiHUd1EMtVIfwbul4vWqPJVqdVEsaxnL+uloDvo9vV5KZh30eG
KDQ8kep1l26Xj23NASFBxLEDbpyPoNBPdXtJhn1/1T2y+nIFAIjExkLuIzSaS8FoZa+JTk/G+Qt0
TLN94rVBDI6yiPbPK8ESijv16A8+k1jrNhcLGxflWYxmEm3CU929jrVJDj5kCMi0T1ctalzoWctP
2+wzDwTQTGn/P6Zuymn5l56J3W2ouE5gyBujJcMAe7Ot9+gRayz3nGRtqFo9lLFMNANiEOs9y4Ai
aFumtT/VH2EJBvucfi1U0wKKduXqiqbhYUKwICMTn1ywjCZ93NnXqc3a/xAIy4XpXVq/tSxYQy9L
pRRwAfs4F8T/TNJ584XRmjKZDazvspPJCIeGYxU3IOwZZ7MZ5MxDSucU6PKRFzqpvl33XzLBqbq8
1LkN9ld1zoYQQ0f5J3iIV3TK92QgyQm8uzKFRO4fRF3okK3a8y/3RQ9fQ883BWw9/ZW2dkPL3AbG
zoahZQLaJNnqIqQgDcCJRQXQpjNrhLvpFxCp7qB3cAi7kjcATZzgg85xaPGG5Swdwv9c4w27bVsf
5JDWORov2J1/aS/JByLtAqJtpG3fvaJUkGpH1lD4oht0ON2GanJ4+N+6wL4PiZ+3rgIlrYr5P97u
URq9zAEhyV8Idlj+l56eRx5f8fZqtFnQv1iukze2yX1Bl/FjHvobFMnbeng87Fyc0rkIUSnh+QMw
I6MNpyRFA3YUcBkUC2DZG8PYhvukVxTnfTXE1qWKBzqqzVaMEdx59aPEeQgaTu8mUYPRQARw7p5A
k+mca+EGjRnKYXCf+tyKdo9LeLcG8d5dr37xRpQ3jhayliRGoyO078RWRhyhepamfosAZSFmShmj
Y1nGfStK6Kk4H+Y7kvMWSHzK75oNQirHu52S7uXZhr7ByDnnd7ed3G6RASV/ZhROwYwOvFM7y+P/
Wc08ogWz1NCy0b3Z3suOy0JEfza8uOcFEmahOJckuvMnIKIJyRdMPuivNO9y7a3fSJGvGVTczOnH
u+fYhe7/3g866xVz9iztbPxscYy2FuhsQGvdu1SLSm9e/DNr7fNaJnEA5/1HFyTQQJBsEvAaBfiC
v7WQ9NHbrqcs0QbvYkD87oleEmjiSYcB64K/KhAs2QgE686B/h/OVVeo4O4wW1XCoZ9NVW/AxfHj
1gCESPYZxtq7jarqn4V8oi7nAonqHXnwNaHYrX58hpqD+x6Q+zTHroPwfThzm12yJS0VqKa/5dL4
d4y6l7+H7RkxMJDShZXE52LRcTKckZdhOtJNI2npPZvYk2I4uHgJ6RWQKIXpnfJr7Ynxp93c0YGH
skyi+x/fuKMnukQ0EdH79Y32cuSkV36t2mPV2gcKGD7o/DbfvO5iFtrK9aSiCJbmg6Kd8pDE1a7L
6dnWW0uhsi2w/f0RFDWAvS/o2J2M9/1QjLY9sCLo5lxI4Q3uSM4yDIm74B/o3qAjjdZfssNS0RPo
JbwTlpzNPUDiaHGTkHjDJpffakneBVEvYq6eCvgMwBgstUP+laMuFpTFXp1xjlEJEeGMqcXsIuS/
S1K6c65ldY3f4GdxoxtlhcyB9OPsn/7FcB7NJCGulIaBvRXiqeDmCLqV8p1dNVzu2HN7g0cCaeRP
x0pyepomIRGuFEqfEEPLlRjkLDIEi62CzPixOkJpiorzvFievcv45Y4zZoedaFBwbGlgb1GncriC
eg1OrFJhY1pqfTSU/rZRSS52z05KzlvXHx2HOU3nzsFeeLR2tSPkz+qyf4mpY4zQKEqAmb3y0ynP
XdsOI6RAao+nYNImC6kJMXScGFx8WpXeOzuufOo2vGUUq0aUXRIXpgljs+hL6IOTDeZFV3TUPui6
GXlwBV/3oAMPwgRghUt5u7iDnUsMOJ/JbJvLJrRVbTrjwOdlO3I1xzKaDGGc60n+G1+p+A43plKG
cCDySOOsEOlBsS0R1yTAsAvNMhkGOSXEhp06KTh0CDOYRVbUiLWo75QJOLIInX6eNssli9YoB5zF
ixkJ1ayYDkMZ66qHZG98ShdTJpVXUMITWTgvqzJgGN8HvVlPkfBskSSABO2+Sr6AHOa5tHZ/6wyq
dAiMS76WKn7TlYNAsKCf7vImJYjNzvyCOuPIvJ+1mqbBd8TA0TY/QK9UUV2IPMR3D4wpAKEcql1J
4+3+zI4aHaBewOPS7k19RhPPMRlMrGVdWh3J+qMp9OozN0+2jr1tMjMKM7OvK5jrDnOVpBeKM8qA
D2R+Dnz+VEG3wHOoYIRme5aqKSv+UL7qwZSkFkVcZ7dWo1YHwC2QDJyHLNbuK2O+2qhFk5lAAoSk
zIGO+/WYTgpbjDIdwwd+ZrKRnfmZ7u2MYBo5/psmXXaIh8rxAlg98v+IloeovtlY5UX22vO8rzvT
VRVDzXsQtQSoAjAed3ZHZWpoibCa/6o4kb/5dexjDG2Kq4peUmC/4JYZXBxxVny2+HcpeI3Nc4ZJ
w2NUK6g+EbVfHGsb/traBSxS/z+xgI3YLBxfms2eyCMGdrTbzfWRiefmMwdZeJ8Wm7kTSfASbseg
33lRzZptLDBMWFqvTDhuB043kl9oXTDQEmC3GAnOCl5iO3Vv0L8vBs7B6rJf9E1IxCadZlav5T5s
1aCuPLx3JqJ4xsyyP4i8vSBUV2mXTXJLG9lge6+7Nm/6Z3kgGfDygNRnCKjb9xorBmdCeIZ/TcCk
GDVedTEMXOfMNsEFcP6fOZCoA9ielwTRRgSai7fIwF5/u5M/1sfDwfJVa4fsaBEka7c7G51NzU+X
SptqCNtYX3m21USx9uxfIybFhRqtAxKtJDxzJTf3t+nxJjqtW4wSbewkD3J6FPtwgQcV716JIhCW
fIq3Xdc7+VnYFuzLP7rKFSjEZHYfXmQrQ7Vf6zX5pPlWqzR0X9IF8vRhnlPfNPHd0pSc8bue/7bC
zexDpxWANT1wfckXPzTmdLcMgopnChrLf2KdCvZ39o8+d2NuIfnNPbfJM2VlLV2KlYidN17z8f2B
sPI+MrEb/j786Smh0y8OLxfJddVAGRXMBzKm16O626zFaI+7ZUdvFsiDU6h0ANoOzUCnG8W1QZC3
73phwTRSDZiOvem5CD7tZXi3JdYaClFHKukP8qiDgGeFREye6kLzj7oImd4Qju98NvFLuWVLcuZ6
nntYxT0vgDhbCPeiXFWsiI3qnGcP0iG4Lg0serzJe1oitox86tOEwvb9QXuOMmoCy+wm0HjBoWqs
bJV8wJzjdNBZuEt8D+69cd4vojKPT56qlurgsFRZI1ckoo0I/3D/BcOhm/XISIJ1vXXqrg0VlvfM
+yTQe/0BdHgdcxoll9A0MRYq2WIpftdqzMHYL8n2ZnZqEB6Ud7544i3uxt7spKw8A2DK1mmCy7Kt
t1rJmxtUUZFm8kHi4kWCzRukc+C0j1wPMpGCr2KQOvylLRIZLts6mzC86hA1cfAMaaW+cSWvGpW4
prCzTC3ZUl3fQqZEKau0n41BxHC1Wx185LP9ehU1Ws/3YbArb9TLkQz7AcTfn3NI8o+nW/AoVhvV
LewqPYjaxWVkHCyz3Hm1oXFZ0hT4IqmXjbF7KN5kslnGgS7GdL5gi7BakM6jfIBvHtfa+pUYOZ0b
VvgA2fi5bps2PpU3GzlLvzOgZf9jaTu1YIzs534ckUfM9CNnnnH1IVWey16dceWI8eyZaWPILc46
k+YL9oqWNftSUlsv5bjevIsDv7hiwmHYpdbkCh2koCnmV7SHku/CMjlFTesyqWb/s//Ev//1bhde
iu0YGYlQHokYAK5XWQ4Bet/PfybT1AORzwpnAuPLldKV3r46KbXW3d/6Z4P9rkTl19jupkP1XXkN
qkh9VJFjY6LQYfAzHxtEQ4X9SZW5iyYb4lbWq9c1zTxthhxu433NTrlgNLaUj50Jg3P39PDhVGwH
IwK1YtQmAxM5gGbKEzoHjaJqpjU2lbyuNC+8IqEYOxt0xlB5TU9Mqbv0R125uYTL4H8q8YP2aZmB
xUkWkYjWHEsPHQRYSEnVGFzZBe+3dOPPV1bY2WKcGVNKq3IdvXPs2MNExicnSPFXLh3R3gOmXCSn
WEdOtOS6wnOyaReFVz3h6/BBl2R5lS8ewpRZc52sSfPkd9c8lox1MPptVidTcOb8vs9ET5KSraGh
OI+ZXJ55YNL166a9jh5NrFa0wzNU4Bh8LcXFDnFJzBTn1DK29u9+swiYY3yaCymJtyLsh0jWw5eS
Y3QxBNzyoW7HOJcwEuUdHBzGm2oTmh0pObI25f6ZXc7utV/5D9vJhhnEuOHt+UfNY2oB84nujtJ6
GcNiryWhh/jJEojwQruyXoOYjb3SF2cFfyfog0G4xnUdPxqYS+xLUZRxu4/KdGPrUjCM8gY36qRG
dBN1neky7nHfW03m2059VY26A05KfMjeMlGNXoZG7anXYoOX8G6FKmmfscp76N7l8sawslLZ80X3
j6sL6l1x2v2M0k3CbLsdWRpoW26GuA97ol7dw5om+12xNzXzybQLeyHDJd4OERLO8PQLmQHV1INf
DlJRSAL3gxloJvLxCpRNY8zx57rCGtbvxASoBZfkBS1MGBcNXqbfoTKyJYEgZOatLmJ/z/wLW73k
nYgF3qRrv48gJg4EpDmbGd4ubn2zFScREJEfr+Qrxc6KXP8rzAFKcMPSjzgtmr/zS0o8bEarwx5J
G0L64MODcN6tCUKxrtKOdVZvxaG67OtSzx537XhHXLHlEdd4W+DKwxkvE1Sv5ftuf/r0cIG36BkR
AqEiaTRrSsSXh10JRJ+vDRukFR52iwYSe7oM93ue2X/ZiCwGKGtJjghh1cOfV0puIS/IFh9R6fos
eaGIACX4iwcuZoVrOH5vp6jEHjA5QJU+09PNvY6LgcSF6prS+6KPndGXznte9fUVdyZPnRQ0eIKz
nnvDhBNNCC8f8rkpyUPBF9QnOQw8j4Oz3PT1APUME+MrY6dk7EEYUKEEwzFNATtRWfveG/a1/NNt
VHQ8UBwgZFJhehl4UlXB5xw883SvvITne17rHzg2rrbKkFDfRkWnZs7n8pm5mPTaC3IyxL5Q4sNW
o22V8mNMMkCKdbjo9HYbZX8kKDtyiVEKofBpG8m4UWhr3vnk2rBjajEb5MqYzVKmVmiIDyAKuSJg
uaFwq2zFXAawr7rBnnNa7KfmyDUsaTnvmId0G6ntTWBBMWWqT+Y+m/SjD00OyuTdIsE8RzkxVz1y
XnQuf5ymq2PGJOBfMhT7rKuQgYJrdH3MzjkmH8C/K/KebgcLq4q0FM4p3kPL0BNetrr7jm4l0f2K
e34WnwkcL8gcKd+GwNFTTjkZc2WCYj9Xb0G6G6GOk6OGZ8HwERPp4QOGo3jqR/+u0TSHOelPrkmc
RaMP91qNvZh2MS9LLA7YSFFnESem7Pa/D2IM5tAoP8Ogh6pl0U02dThsh9UWM/8sdSqD9aV9QMvU
BSKlKIZ1EP3I4Pf77XeNcPPywWkJA45Bigr0Dn/Y7S0HQAfwpHNfdzG5jIfHzQ9sWhems4TWD58i
cXnEl4xDjWhMGHC/ICuar3eXx/pv61d3gDYeneFXg8DOnDUqtinNs0F7fMXFyoEMNil3X3Pwf9W4
rhRU0UImyTnVfpuCcIEmgxkS/7+rReSCCk6jTfofMowdQp0qFE8iOrxe6+kevMQB6YHdnnIc82ys
A4B7KLLBlboqfHiv6GIxq5u3Yuzw6AJOTQnpdaejwVgxPLoR114eFquSzReDsFAohOg0fc6Ahyvs
7Lsxofld1G0nFgH87E6v9dfaZkyQsKmLRQATSjzGqKSp4ubELjR1PUVtrniLnmPrxhwvMVEsYR4Y
65VAXHw513S+1cVH+IPdYKinCTxr63NSVGMBYjLin38791FM35kOQRU6gEQicD9hp1vJaH5m/Q1B
zQd+kLuGk+f+9IFFfuzj4W+5/aOdoFhkiKXc2Iw/WYEt4MAxz2Nr0HJf2L5ekh0PpLfot5gyDII9
VyEPJ437LT7qQIHR7XgAVoKmrGesV7zHXqJwog1W+Dv5MzNV/hZEMeQEk7wstCm2+B8Sj5Khri8X
5TsFKH0ApJM32dJ33Q/LEaDTXR2JECxmIinNepWN1XFKgru3NGqaSspoCyv4cOFY5ROL/itnwj0a
z93S2RSyEmINxcolETgoZ7IHkVUYqtnkrWHrcx3fE/2//YBVeht2cFSCB73uhCO+eYgwOygZdkgl
6d8+xCYqCRKIgNy6lGdjskICy9ES5HgBizEFE4pvxEW4JsTF42BjMA7RHYXBWbE6vAR4Un57nI7t
7TG5/+yNyps8brqnSxF8wyU/jnwpPjrF/gRZOqdr+mCytz8O68bCJYU+06P1vO1IobcvsWuY+HQg
/bQ4omAZ1q7wJkIflKpBnPVLHTCxkcbJIdLT+CG8wTh9ZVYLiUFTNKfnbUdRwlMzDiLvYzEM5E+S
JuiTHvRUQcz0gQi/i/IFnQnmJ6fTapsX0+W5fdeoKePGmJfa55t9eiGh3c7rvLfyzSL9ojtnImfg
QjKNSuGdrzUtrOlQd1llrisBNe+2s5bZXlRL2562CntUvQIz73SoNauBtlfA0kY2b+b0z3+aY7xJ
Lcet4IGN/N0jt36wBv2BHCbX8IDqfsE22o7uyo8d0RyZbNJWizx9P5WZ+z7EjbFJelj7E2WI42Yo
gLstLtjVKTnpBOd9/cB91sLJb5t+XDrspRRXmUCE9pDCACcRevP/sNMzAtWPOwHXNp284P6VaIJX
Ga+4TuAULfCP5N8rT80gI7H78In1sOhe58WXKgaVy/WNmJRycIyQDjMTmuB6RZEsecKrCwDRVfuX
1Yx7dB1qQVn6+vMy58dTH3czuI6mxswxg8aiy1Uu2hAyXiO3IO4s0eELL/cdQZ7FX1ctoZjBMqSb
JJXiOhXC+/j3/YHWvrfKLMi7ATdlwvh0HI+1rz04ZePSngrH4qCrHaEWLp1wy96WwKwn/u6XNxXK
HIyc5JiUili1ZszP2b+EK3nqLYtKce2qvPVAWpurS2q9vhjYB9wzqAcgZdWl5QwVRQmlXL7kb+O6
Q+9rqFr1WANjILfol0jdi4FnqGlB1E8XxmzlUH8qixirlpaJdcUoD1njSxcCfsu+xJbOtZrsNpzB
h/1VuXGRZ6IdASuM1TC9WdnOGtWrE+/reYOnhXbEg+MmL5AUA5Fr9TF/ReOci5qgMd6Qxo6rPT3x
ogCC1w0j7GY0DzqksIw2yW8CKNkRoJ0oxsAyVVALVVsU+Se2tAjgLYqwGOmxz3nEYlnU2HUtSNzu
Ewo+dhj3tRB16Qa/lD1EHgXM8q4cDr0cqxP8MCGNcxQn6MpbBSpYe65K2RAG/nL1Ry6Pmjx4C+f5
Cq1Mt3Dhfm7TIQ7kJo0etsq4eKk/IUaXJkQ1BDCA3Xpfi3eXNGiq7lTePs5v/LlHznFIAoPTHM2C
1BMHoHU7Ja50I1bfK08lBowmJix47TyzYfcbgXZmwGJ/5ewrD2dzSabCTE3Kmp1ItFPaS3dP4EHQ
NZWVtKJA2jdLmiRvjHNClTIQ8NmPUCFfaN+VbaK+7thcqLsNsqID/AzxUFK5+jX+NMnCado/0CCz
dxYIPpUpGAHz5YVuq9IKkLsfdXClRb1s4ytIWhjRstqNHVk3++l29Rb+gFgI5KwrerCMM9t6/BUn
U3AXVX9581RcIgf+SuAffMD0paUWn6dqzGTX5fdUhGgHyMcs/OwUPjNWTQTT9DEkLL+RQ+XJ2ynf
FZbrB8EX482yTkWzP2YeraLc54OufJfI6MrLejvybXAlRCwvJFR32xeVvzms6xunaAJb/w7G8dcw
oUDO2rZdcnTnR6O15S1F4urN2g/rnbrVaXkGc0ko4plwYKYRfjMwpCJ4yPjwle1qNt7KXwxwL0A9
SzLIF2tJ7+TgO9O2+OzwsuLZ9krtOih/axBWU5SJm2IY04kJQ8mLlpgwj3swz5/09qyj/RzLt8br
Nu15yomdwwpNGYSt1g32OYGwFWlqyprz4PmdxyF6cQAjo1KN7itC1i0PuVnWcUx0j4KYqL6J4Cwe
gRz7Dlf06bk1DgfeMI4IeugDjfI8R8dZme+ywfVqsatUWc9P3X8K56c3b3IEEZjhjJd/mUzHkNFw
vMGNdx4CqrjUB71TvhdFc7F00B1RvDf7ZmhYstoJXN9QHNSK92OKminD1sHh07oNdYNGOuVh35c0
jTPy6Se5Gy+ojEZxU1XzRnXExmtTvtze7xKCeggahPJLfXTzOIVhw3lKvHxC+oaLBeKPk/YsZBfM
B0v3iMNTHECxTJjBXW/4aqzz3tcVfcUJ49sFq3VPXp8C0sg1x2GuRQ5RB/pPFrvByuI7PY7UlKcA
F0wYZUJHg2jnrJuvJAKfBNvSwct21NwPmvj4uRZEw1wiGBDfksVaHWkPhx/sOHCLkQXlTxLTaXfw
3rOeafk8g78mU5RLyb5a/D8I1Dx87dNO5iwC2e9IwmI1w4CljcUpVFKdR5dC57pqWJFiJ+dFI9Nu
GyqSYhNa/fRfkQJ9kRu9OxXyKGIBa4bXAI/ufnsSxnEn9vG98RP0WizMESztOHnEagQlcuhmNkcG
PRgp7sAyfb+ehaawA7ygDIwwdv5Rfd7j7sqC9dQi7ZZR6zQAVvS8LWa0wA/udWW2n6ytH4Pk2EsB
UdB2mOsVyw+K0JoyyBZOqPEyXzTroNBWNen+HlA3wE6e+/8qM123EwygEGkHoVbHIIzQKDPWubfI
u4AauGaFvq619LBu9Sg7XbSytJaNCiqG02sZkKFN3w/UWqmkRdwry+rBAeMjVzfqBDXvawFPvCbt
fUY9O3QKfJJyQfZi4QckR7/mRkwLI5HNV2Yz573Dnmv/51F6wFlJ1n1E0zsIe45a9nOA3AKQ8Rwo
gQvTI83r2Ua3aavwmNZ0hUMvoVfkAW85C+tQIRpZJbHFrPIyStwXo8pfUdjuoI26CJ1UYebH1dVk
la1iyYMRD0VOv93iiUwDapvXI+VuKTVMkjM6x+n0jh45OE5A0u6W/JzhfIPVPuRXrKeuW2LtvAuP
URsPA7QNbv0TIpB09jNVdUZMK0CRWb9Ft9xgYXVfnLPCt2D9RK0r1JToK0CF2qVbphu7eta+ctmy
IH6gHVxspmDUwiQEA2u0DiIXr6D2Sn3geNdMuvKngqR0bdFdzNYMkFYYeOWu/FBDnyKndGrdQGWf
+KgAIhh4m7R+G0sl4LogarVx8SKnu6cZtv1KjrVhMSalbMZ3BILxY1PjaMCw+NTEwcS8GYf1dAlU
NipzbjaMvWGmahQwhUq907Mz6GJfA4iBy22xIpVQDuXWPem1mcmvO+kzPmlUnw/zXLmQnbcO/9FI
7gTEBp/4a34J7e6lVX6f0I52/Ly1Tgi6J1fdzppiMy8PXmWjpIB/g+25Xvf3A3foDHnTcbMUSkwP
+2ZUNpt+HsxFLNQeyyXofVEAAG7Jz1ECpzQPAjdXNxdDnfcjpLIaMc64dONHs/R2qXcU4Ufg6GhD
VBbN+jib5y2bmNoAC5wbTglvaiyO1kTvtOAGBtoGBzPElZwHPonFztzU72SAOVR4xxND9CmrkChG
k7BSkaDBAS4C7KTtGSEniUQEzYkeVTcvjkydzplT3ID8h2YrnhCXrzbjNikQ8haAMv5m+FZS2nGN
YJt5WpelgFXW06+Eh1QouFF7VWsH6GwNsQI4xuwebzekRB7ONGDZyVu4ase9Uo5fsQo70ZanlJ79
X2hJb1sSiQ89qtkutEdIECtEwVq/inM5FSWp36zv8DY19ZvB6bChgd/bLdsLyedGxqkfOXIrGg+g
7ol+a9Ebv93ccNCwJpFqwCvymIJerY38xSg4Z2jIhFLQQPaLD7TqpbqQgF4aLUpORRtGwweYxm52
b4026ALZHThWGUmcyQg6P3ypr9oFpzDDwlBrRT+EfBNMPOEGJVRq+ss3lOhiFfqkpWWqzfdSP+Q3
0qjk14vxIw4pihkAbPMZ3UlFyHT/wya7f3k/pXinfY1KxvX4Hgn0JnXsguhB9iOL+q1t7cTIoz0P
qjtTt0UheXuuJyJF+zgmDU6aaizz6+E4qxr5Z6uijCPfZNWndXooxMJSrOjwSgVGTSK9dutT0rxf
JMQFMytA+rUZlWPeMmX0yXsGXxd24z0bXs4o5Bf7HHc/sbdPjgNL/1IAMbG/xo0KLsJy+JCDCcGj
RG1pQ/7YfNzB+pUfULUsYye2M7T1zUROIywTXtIxc/lM7pUHae1RHlFh/pembnnNmmzvvTs5phyc
2jONlJlXAHizDSnIxMD9+WLoohY9tCS6V3w4o9sm5B6rymJc6syg0KpT6JzSjUwYW+KsVCY5xZ4N
npiTfzeaKFvGbq4DLPT3VdfitLOZ9EryBFL9f1gjClpsvxVN8NSfATrEYop5q0RZ7Ir634gOcL+N
xJilCnMBaQaWl8GQXA+AKX+/CzcRnl2k8A3oo9IcoVcJcwYUMBxNF8Bq4V6vflajSfR2i6I6YYOY
1voEalyVYlfDOf5QRF9iBZxbahagDwWl5lR2wMbtgD2EhSv/uiD2jjCiVIpn6isVSgTQ15FHM7zw
y/s066DDFO1oE/CjkRlXpOs7Xs7h0aYS8XrhDZCNUiq8MM3+ghW3QbVxf1vwLZai05iPvNCpWA8x
ile0ptTAiT9bcU/s5qMPIV2HGWE8ugmOWkxX/EPe76BDyBn4fnYPBj3yldt4esHgWLiJAyEaY+5u
jSFSio3nB3j0LmO0DimwOvwFl3fvpVYzIvQMk2VQg/4lbgja0F1gPLor2svgGu76NSbKa7ycjybl
RF3Xj+hM8qSfp+MCbMQ/LHLWqpLouZvw8A+wh5/OUUWS0KLmb6A02PPoUQspgcSYjWJy3Vj0Iw8M
v7LEWWP+/1ujMXnQBkyFnL5b/KC4923jK9TPG1Om4C+mKTY0ajVVnk5lNhJxi75xF5CXmD+NdYYr
UPBBiIOW65QAkBESBFaOrMsxeVTNkpVmcOt0a2Xp5lOOpHh/5zGN/VDyJ88buyHSEgRS2VtWOc/x
HzvvGZTBl8AJ03QQc7uPsui6Kz8p+zCJLZRzK+Unzx/J6GZp2f80g1TVbgg0Pf8sGE37f+CfIBOW
SowgMkVbyykqxPkpVHmD+kK7VXlE98yg2U91FQArhzRMt+mPR3GvvwP81jKHC+6fO9CxRWiSvnVX
fcZteLh2GU8DZO/jP/edYp3woF5Yv9Sz+seXWqmJyJU/csd4g4k5/JPJq0t5POlEdKhPS9cLJcSi
NTfOOW2sf3QXAT1AYp4KIb/p4VhAjgAFABBLrb0NZc4rEY3Fj5xIfnyBbqiQv7M7jYvifcmgnnDD
X73veKfjtDc/Plyh4Vl0Pq2qXCzD6yLtpMRPS5Nso2PBX0zx54+scpvhLSSczmGL6XBxtvQO5QMW
LoEuxKUNYTNC9r+RaIEYc5AQpNKHYhXFS+ktuJLs4UfYZJhdW8R/W+E39/qaNKaBBhhgXeJEviJa
fnu6DgQNaK6ahpUftQqeqCtJrAnH9lzFOEBYakgo9fUlz+c8JmSUcVZy461zIWRNOxu5FwFmJ5EP
Tkq8DX7w7oVoLmnR1IRCr4/OTbGtKNN9qMGikj1M2mjPlQGhwW6IUGetk9XClNei6+rPM84xV2T7
gEhNw155VVsyyevKYwZzUM2ZCBHyAB4G+4ZYS2/PlDfkBIgCTQmFI7m281BelZfjjz9msoB93Nf9
OXX9E0qkm+UBO0iTRsO/cffPJWSO74P1xNa0zb8tkR683LfnEunLumDvrO2hd/ulTTbiu8fsoOjv
qoj4BUxLUV/i5qiCtCBD09HKLvqfGp5NS9R7YHk1fH1fWS0WiiU1534MCU7FOQpEVhSgteDnqvwL
b0acpqG1cDQQqJKOrMNypEJmaAQ3VzS7DgI291FVhU6YQKU8cilHgSLLQXi6JuT60UiU9dmtHBOF
QP5LaxdNpATB4O8ZMqA0PJ7lwQ1w+h4jOJmk8W/w3KG3XV3ljKbHsoNW1kmVoo5Tr8n9HZJTHs3y
OV2LvFP3xeo7d2ViaCa0lNnL3pv03FRyC09doW0tw9GU0S5ggu3A0WExFBxjq9gBuP/EX+9IE9yg
ugIk0eIey3jYdrJ79EzVQjmOlw3nnERuJ3c9cfC74KqqrkfIuvx//bgFgmgBJXAHDUPRgOJ8/rka
ABrKJ6aXIkVzNOTn+/VR5E7MXsNlTI1Ehhn0YpKieYt/qQc2pww9/qZrdRkj1YvmqL8rpy+tEkpU
IZ02KNl5ZUVHNNwQuX9isT8E5Tn0d/AjtJckrvAxJfMDj0H63ZyC6s0tFgGZBru+fvTRItJaEeuM
LggS7FWj7K2MHzRyH5Vwaf+mK8zEb0cgDVxCECn0hoN4VjF5BvehH7RpaHRsH+XkkjsH4QtQN3XO
7+/mvRe/j84HAlQckDDJ6WyBj77z+5CkPJrrw6aQy/EkSmN22mA2NTddYT5l/aTzqMvpzHT8jvfl
ygrkd8fmt8sALi0a0oUcFr5Nwu2SN1IE8EDyuX56WsavplsscKUf6UoW0AeYJTmTaiqDLJJNv9sL
KoKRIJooAGlBd0aibALXOVro+dCUBkidmQe3UAbH6xvsLZYQQfXTXUyNbspcVfWv/ll41C7Lj3mZ
gjHo1fqkLsa7JJBpGWLAZqwjf9NAEP+HTIA2FJRUhK0k9MWYWQWWo5Bbx+kkfbRUi0ixM/g5Yq7a
wtuGaOjMipDMxZ+Al8g/ObqhBaGOKtUXHosPJQnzKA8N9JzNZOBue/2YW9MC4D9GCzIN+rCk0ZL6
PxgIclv22Sbgj4XTbqN2p1dLUAMZ/LJJTuboVEn16uoGoNDHm8DjyTxArinJpGBW2QnCxLWQzQI+
2E5Q+HF5mYUF9C+k2JTusdzmyL7oas/r2gV0yq9rsghBGPZ/pNUDRiRJ27q/gCL6uwPmaf5OjRrt
c0zfd7CL8nYyIOlNccsR+WrBEkhbmOfKwkSZIXWWwfygotN+L0lpUHNZ9g66S/g/pLVARmjT5hKL
aXSXXoUx7lrf8ofsgxOr9lruVj/c7dlTBXhZCsG9pMy4EO/t2E5+9debahSOp9UnniGOhkBpUMAC
uIG1BfmfgK1zFO0djyX9tApMJk0jgGj4eVbFDpVO5ZBp2fWYfaBY/yVfXV/DCxQDRWSoMr+mf0Yk
NtAz2RhCYbn8z47tHwfFaitLKw8Cf9Ufx1gNykGKRhczezruzOTlvWqDtA0gjvV4nvDpCGkEkryw
DulWvN+oPCvvso5NCQcSWF+gcbzmPMc+EatdyO4Rmftov6jTSHpe5bn7MjNIldT3+6f2poH9lllN
ReRH5Yv6W8m1sNrA5wUqMnJi4zeckMwWdUi/lxcZE/cX4zgsnuSo+SvWfg2PYpno9bgrYQJRONtC
LmjR5CrHKWIyEkCA91/5v9KL4YQDThslFfWK5xj+xlV1s3+Ul7zPOFbesGMboLoL8ocV1mEv7Vih
vKMbF0VlYDmiy8P69695tN5k0A9oiZMFje9jWxMtMdA2mlASmeyhaWy3S7GMBk3Q/7p3ST8F1KCJ
jNHU3scrUTiCqJTcH1nJ1eJCiZnQ6UkgBNMwDiPSdxnCo/tfGSGPRMOlLh6BQb5cYB8yP7ZietgZ
uxpSV564wVymW6U2KAYDy5ULlmrKBAquyyG5Gkib/uyN9Kt2XvTBU2/zM5LJ8W+zDalWbnsAR1fa
+NK42lzY8MrQYIautO7ca/qkiQ7oce3vgpgRLGZNkHw6j9GUCIYoJxZGKkI1yp+40h955/lVzrue
U99YY0xwqgD9fFg6aDUJBfD4Y9Q33I9gNRUJYXSmGdj4RJoMlJkCTFozR5Cjm82aitivBvHbJ1VF
Fs3vjN9/ReDPtMpx8obykOKS2O30O2jmoX87679UfJ1+klrwbxiET4STuUwxvS++N0yJL+Pj5LEz
mx1T74xPxzkCVEEc/ATHLzYopQVJ1G5bRQfWkg14uk03ZhLPn8s2ZUMRuaO2jT1gID0yEMRtNnPy
4Rn1aPL90c7F8lVguQygUWQP9Ad5MYU/S36BuTZqIR+L9LMqAmLoeCrSB2T7I4psrxsVJQGBP2tM
PxeOt/LB286SsWHNNzAXD6ayB23umlc6H349r0Vo21RxlOE1kPP13AGNDfTg+t+GnYBMUUnOdW62
6SgPl0gdJ3Sk23dMOYJqtCMRHsw/PD1koeqllFktbjC4P027SDKldHupDEBr4/R20cnjkO4GF1Hg
3QScptmD21BY3BxqrERoJPjFajYCt1lOE5vfBFNIy1QoIX6C/leqVJUtNe5DMIlxXSW3/2v1VIW/
XtU3e1ayw2f4/WeCFAN48OfwZ87r9TefVEeuMbT+CmV6obET6jispruw5E9ZGx5Cp7JbGIWrwAVR
RAbvXVI3wQ9SVMchcdmyUCJJeNV4lXER7DK9N4mcD8F51lGYfe8+paTabwK1i1V4/GrVEFkyjcAC
F42MXs2LCj8Lu8gD+2+SYsAmdQ0bnEU+tRK+YWHOw07vPQh1AEIEAFkXQrbl9IdWgDWBcX0+YhIY
IGWrH/XdNDFGJ2VWGRJ/RpP2tzSAIM7bVQVoURPDRlqhyunRkQrdaOH/l+Jm3mnCzXb5dm39Y+gG
+Ca6DBzPPKaJoyueszR808bZv4y4e2KStXJJ50a0ofcQ8/Oarq/azvXXpWNmgQOUskJUbdwzkmFE
kD8PcCRsSN0VWfHdheC8AA1bvCSvPPguXz+LHSh2IeSxpZWI5EzRtv/KRdoj2e8LDYEmpoVAksQv
4a00VROBx0HkEG9Y1Pe6a5cwtEh4A1JdRFCWUsDBUICXPOFNi51IUF+YiYVdMS0aMzhBYCYpTt/w
sR78bEuahIx0pkNoH83cLbU3Ta217OxZdKzHo64zNQR0SiH6VMmCX/QqosBch+UPw0qyFqnQAJOw
Go1oulPx9PcpnmgGkkwUJ8Gk1yelY/Rkkru1QSu3Qmj96l1OsaSW4lM0KjSnvVnFPYex80647hEA
v4P7uIftoiEPasoU/fC8Z3yyp+uqsKdzXbIgf3G1XAecb/oRuYVvBh8JoNlLA6BeQgLphwZJiehb
AcTimonPVEJQYKEkJrHvLZb5K3Hq5o4ERZEuAQcNq231rSbVaGdOyBaucn2ZJvrDWXJFxdQ+bSjb
UJk/KyAqAWpjZD8AeqOCgPVcjPj7qdAoerhTh9gpcbhxpVDyIJp/usp9QOgiXrzG7Ss/7juPzjCo
f9gSvk31/1SBf47Rtm6yGYEZy9Pv+3e/M6qdIjT/EHpyJ+KqK2rqM/LlvkEhMDQhngKFFrONHFt0
xi3oMEetDF0bxeBOF6bK9u/w/NaZPkQPVw7cOPI+05q2l2gQi7Og40wnhJu88UUbOD2t/Pqowr0t
39MEh59/YdY9HWM8IetXpHpAj6Qbh13XR13YHg63XhcF/uKZzFGLLH8Iwc2VdPJalhZKQAE/N+37
7epOzeib9mj0I6jBdi00WTLI60xgMaMmRF2uhU30xBPLCBUvulOFgmDDhaMl1tF1115u4YQIOJXU
A6gXut1dy7rv0TUqfkgNmn4CJFxcKPI+nkv0ZRQTB3tT8pFwhWyoZ2jmrU7JVvAy12JBgUqno+pR
GHFUi5Qw/gfAh6yBeGqXO5BTqrqnB5KIV27sjC+mTsZpXyLMOTYG1B5EIRWAuazxK4vy6KhX1ykr
wakPuk7bMMy7SxPTHe/vwF8TMvMgQpppzzpqWexUGA+luKky0jLqZVGKtujTKkL7Hd7lmoo6iJh0
etGCsHDckyA3+RmtWJspLWA+ekfkPaB32EcWqX5CRgGtgytQ0EF/ye5ADkMIvEJeoJJLSOKAF/yr
9JpfK0kvVkiHgPwSGDqJ021Q0trImD3XLFe8/WmObWEge0v3S949r3Ci5RwsO5/mQdeAlzvXC9RT
kXhSPnkQbfOkajAepFCT0ghkWcGN9Zr6mkeRCfXdtBEH5ZT+aFt8FlXi3cJOKB1yAWtVpy2oMS32
hXiF9RG7SwsWeN+L0RmbT639aRm0sFP3TVNBS1DM2+1XsepLMCTbgDoqREE/DiQWhexJGzmz5XXY
+2pIPY5M/V+9+3Y3lx64joOzRE/hDU1L6SUCRFs9vl353mZOe+Q07+Ieo++T2s5dSxDvi01gCFW5
uK9suJaoZ67FcweJZRSnZgs/B7hwCu9y6tkVuWd+b5+Pt/IBwMGEt0AcVyvWZZTo19yjGgect2P9
1rvKLKy7zF6a/Bkdx3A49IOtHZVBYvUag9wO1hRnxzHYv6YsdeLdP93CwmR4cYZv+mPk0RE4QQyc
He7AY6v114Kb4qBMn/ayx8hHv+X3BonmB830i9D+yt4JGSolVr9xs0YppWN63vdySz47Yh3Y5mqz
dEwg3G0YYwwvgla5xvV1HVk48Kms+6EiWXUJlhCqLKUGSfVVJI29Q/La/acfBwcgx3yqLk9IV/Df
qBKl10yhQh5+SP7zHu4oZ9ba8chFj6XCI/H4McYunNUk0r5E0SLfAp+jv+v4vqO2fA1MH2ih2vch
xomC1s2yf/K4Ah69AU37/Fm2ES4TQjtIVFMnBnwRXfXPfuRYSXmS9v/P52RL7bNNz6/4Efjp9bm3
RKKmI4e9gI+ft/s+jx//Esh2qf4kAgKyvNb8pRi0rV9GG5aN0vISgTF+KwWn5HPgL3wCgkJ3PsZJ
wMF0uSnKMjcCYqhjDdbl+DHO3xw/Sm7NIxBH1XAV57WunkLHWABy2XOGvkAdvaWizlBrm3z+VW1+
PIYW/30GsojrZFUExKtY8r5PJwfgbR/5ObwXOoqev+ReuAdEa9g4bQLshuoL4nlhIUnBdOsuY0nS
k3NdbFfWIzEc2plRXwjeLn5grjQ4xAxVfDUB/yN+AyubWAKm5iT6rSm64X7oeG+kqxmaYMIAMrbn
KRl8zi2v1ypkTVk78VOgBWKXw7IXMYpX1rT/xJ87f2AdmgcaitxPQLVXrlIZb27aOs7DDwo15+Wd
VjRJPL1FpTykRqonN8AbtZ6Q7C6KBo28+JvyfcUSYNjw9q2ZApqmXEkLq4r7Y3aUCRWDz0Dlphme
oUSQeKVDHRbMXPSDfOXMrJvBOpZJgFsmytpJl+PCHAulcgsDELfMWmxseCu4+uUo22nO3l07vH+2
7rI6FDo7OKBGvQ5UCxCLYJN8OI+Yt05lLObl0LYmqp+97eq6YHcCrgG8fhYX1/vwPKY3JEhwLETK
Hk27kvwcRISPQEd5QDN6x72xnSnd8FIb1pe8IUUIgrbY60yPiKAD3O/KnKIVm0L/kX9yCjKRE776
N0sL4+7XIruwhKxiGVvFwTiIB9UZa79tXXyaBARA3QSq2GCkrZ9bZqrq00n01lcPD98SdnnmvaX8
l5O1NZbN1rjorwOOk3JcHa2XSIvQIzPdfh4WABIDhsPTJwoZ7UMAoDtcdbgFThlEhgOBocoljGM2
B1u9RmWSdF4ZYfaSN+MmTHksJbHJTNBIHTa5t5vuqDpt3Zpj/nkKYgBDXuUC2RBYPcD64Yde4LOJ
XitLNCGoUG/uHz1VDlgWyNIv3S7rqpapf6Wd7C4LBJNPFTdNC+zAPzv+bXzsyFz3JD8O2bWWbWx+
y5SpDtMlbgnMescxkprHnjKl3MIKfijnfYwnGFPckr32SqTnDbS8CLh+X4qmiEyODZ38Zq//OkVd
Xc4EY1o8iNjvQWgccVYosLxYSJSw4mitfCtp2qcN7AwB+gKhzp9qaOIIWU8pRbRKJ+cxgG1f9rTz
iP6Yg2CtHoJn7ZsqdhsnKXCdNLX2mWy5gPdm7BIQ2k1BHZ94ht+x6mxPRuV+W8DsPsGvtwpJcLN7
IDdnLVSzn2WnT8q0vW8xIpgvNVr34XDNEMnYvidVsmo3xHg5pV4ShqSI2sHYEtTVoURlz/qGNdAb
42kOnfeWgzodDk9goum/HzRm6yqWMbqgMpt0wbh83Yq/1Q53ElIwCvZG7UPZ79DQZ07ho3wXA+7D
YLDp3D+MVjp78pL1VsDeP/ZReH2/6DzjyiTX9D7vTl/ZmszBiYoBkHfKS2fdnqE1khNKDWnpczZ8
oppC+WmJzvXYCu/qIMOJ2mwar64FTLlh/wdy2+WeHcJw06rIi89x3GXZf1g34B9v+9KO3uaoGJF7
SlD0RODd5YWaXHXcmjJ/xFhN2jDZPDfcZ9DL/koXmwK56COl42D670jSTaFobp84P7vlDUyrm5nb
1V76N7zRVXK/PwwhZze1ry1rnwIAPqav8bWoaEL7Izp2dk0cz0HPOViX6nhZB4j5/5uX/smD21uC
lWqLIfJrv+0tEdZWf7kvRhEv44/nSXs9k9hnhEWmqqODec4FWqQCENMXlgmc0wkNl5UF8RAUts7I
A+ctVWTkoLRmv1ZFLTEDNYlrnLN8+BKpVxbbCjtJHiRNJW7xuNIOWyswUs05TptaQM9PqB4cfrsc
DcMhphZh6akUtFlLjVxYmBbfULoW30oucT6In1rMPOg3lgTdHT1/bNfbDN/JAVdSLQRyFwvPYf84
J42RVGL9e5cgQw1B/2cZ+dtZtAndFRPYoTmRkx6KDhBfJWZ0IMd5waMRC4hzf57GJjErbHsHgOta
3gIVc5QrXEeBGD6OVSQxoKttg1ql8g9v3HIHAa/RVsG9QBqOF5KXOuUiO4OPobaSmrNzeUbvInRN
xKdk+BgO5+t13ywLxU0APXhPG/1ubL9Js7+RACp3ywuG0VBHpn7r3tsQKxMuLUzHjPas3SQIPKzH
jcRUM7g/JgYlo0CzLJH4bAMzuciutlkMoz6Tz9hKsWLMzXoVVFH7CxzOBT9EzobVPU/uCw9PMwuL
WYQ2bRpuuf3Yzu8XK0KaWlsLYwBrCXAv/PfzRGL4nSKi/bQpywymNjPLLm3CsVxWaS/ALQhhT4TV
T47GHQnJFoqH1kkuSaDrjvlcCN/+O31CyCDq2d2SWhN4L9TYrz5G+8YHA5mWR8HRYohpbJOKV9Ww
RNZ/QuDn2UyHALn+6z0vOrbDL/wVQ6hcrRVPjm0K7va3Ua0ESBcvGRUrLlN1eXcccENy4+l7V+g+
mXsGKoHc2/jLZ7QD9wHbyEQkG5MnFe6vKloznWgvEA9CeIkZBmwjFOyyXQjp+EAGStYs1x2unyXA
iJDgCaqt9tPqYWQeMmH+Z1kaHmh/OFJornBQ07CvQhI0s7QScPVqLFdXjJ7ovqgQjaF33TNWY0OK
Z5GI9TVCczNQqs2u0QhOfTMR6awPfs4QirTE5nWjV6khRY1rlHqQnhvoJ8Dh/HLKaHCTzvn57D3G
7YKc3BhAk7Fc9oxTMK0N5VfJmKHuRDeDmBec8ZxmF4nSVzd1Vxh6AHgCeZT8dhlDefv0qjNN9rdF
fwChNmQV3pQHfab/TlLBLqvlBINin1goOqeIpuJDsx5Qy0Jf2v48mAa6GfXulnVAVoWAQTkAncm7
duqsf1uly1A34pAZj9Be3Xm17Dm00Fe9I7GkPSscrdf5eneedDJiZEK6SPsu+D0pNniBvEt0dQsW
NVNFpN1+zq+14VetEc7Frt/twcpZmx7uYpuJeX+oP5AaXW/uCEj//9AMts05Faq7SpVQbTgA64pS
2Er9/fnxNyfQNAL7Tz4CINVrLT/OvZqdCOHWsU9J/rvPcsetjT0zCjYWnnNp5KTW4oIQOicqSuLW
jE0d7dibEwYS/q/PBPf7/JuJKvY9r8T/1AlT6qaYdjHsgPNzJ2P/mZ4R20EXuFQNP3lp+0MXSFNN
tjOUjHVfUWhFCXOhAJMZGlqbUwMVTBYNumrodilu3s5sCdLpMCPu9bv1E70dEwBtaV0j4F74bI06
2kSR+noKA2bRzh+rBKUXSvJzfz7J4yDKXhXp8BLcp6G5qZSb8HnQSDzJE+kXuGg2rzUYYJKvDUq2
5cdmMatT516pCJaGAD74eFFhlWBEd9ra6O896CBBtD7AVcU27TgVWUdExSiwV6WNS2OrUnSDLRbb
j1U+GCwabj/Fee4JCeHMH1M4OTQ56BdME7vAr5wbBYGDLsc8JkP8EI2H+1zNOUwjhOTlLgviDQwB
lamLqyjk2AQptSsuVB77uSzLb0rCoHjJvmLXxlwbdkoGwtfyIMIrC2oGp6mntwe98HtGyxFSdJSQ
z4URckwaVWa2lASaG5K5NgzoGFZdpXSWzTIKIOSQcLXmlM/QINZ0hUnkwYrRN1PZ1Ubvb1gB57Py
KOpZljBGFtcpN5T9ws3ww2q0c7dEEPdL+OHZUKScOhJChrUPaebsy7nw08Yd02sQcolgD8TbUQ0t
Yu+StvFXq7bcipW/wFd0SYtaVHPwuXeBbEUqAfy85yL+2MtF0n80tEn19eGA/An8Y3g1Z9DYJ8OB
vY4IC4wL/f+YbNSA+mhWVal5RGFXjiY+TRXilzrh9HBx5FeeJu2uLcmsdIHLkDrHwiIftBxHZqUf
owb4mGfJWa3cDX8Z25uZ6633pYUUjDmxQibecZ4McPXoXeZIKXZlgvVA5Qr2eho8zA9NuDU3kfim
KpO2ZDG4E3wOsWRe4ujKv1g4KVtifDizLJVREdmx+2Wob3lZ5mKNuM/UYAiv2cpawdbVYNdN5nmg
LRkZ8H29Y7mLoXeuhnC5/t2nMN4HCCdjIs8Yi47YclH4PEWxfDDT0CYwZJMJaBw/DD2h1kL79l1/
q2dvlrq9DGxpiU72d4ZERFlCZkT7X7Vee/C/menHrIIQUhRkNiYNOLl6rmWxLfGxjbVfS1chttl5
Sq0vF0DVs8T4kOCT/dzjqkSFcUazE4HSt7IBSXdNLekMclUqyGKK5ciu7Dcq36kvqFhBIcRmGi1j
Bwabo+9nRd7TJQFSAlWGlnzcSDlI1B+pEbZJjY+7oz58tcavB2IjNr8ziW9ZksZge763hRsuZt5w
pnQfLtap1ZzZByhOUVpbrPVYELpzS8vPF1VAw53pmqkjMqYxnSkPAZ0hn0W9jTwRUC1h9B5HtlRg
3WXK4kTC26vMMf/OxtQn4R/WXeFQsWgXfJDxnZ41gwz9Ro0ZUQZrASXC15xdDBtfxsLYvVRQd39I
ud9REuk/Qs4I2on4jzAChF9UlHbkW+n9xs2KGBmG9em56e96L+LE5bwxxy/2iDWx3zJAeGpc7EZH
rFGdngW9FL0YTyp6UQC21e6Q3QHwXqWRa416WtvSp64dPojn9rFZBXfqJBZ6LplRpziBKC4ZmRPB
QROsL7ILvL2KVOYHyqXqwfH7QBJCqryTSanqIaBEkOk+JURAVXYHCOMjBDO358x+2yaQRRflJwjM
iAnKwVVyZidzQp9aDf1FDppw85Pcn6ol/R7SZm5nMkHB/LDjhWKCYI1QCvIZoZhAPMruiC895T5c
xXaK0MuEbAMDz58sjWNEglZBeVJMD8TspLvT9nwQsZnkOMXZVKi6ddN7GmQ29bHW5TKv1vZiBJXb
1X4v1eEjYEtOHjIDI5VooOgF7uVlHSG6572p+kKnC6mCqC3qhnZi3jOWTsdM22Cix0qUyfQ6VP0q
RVbcFZXS+GnwUkWuSiDJhSHcKZu8y4JxY/idXRVwKLTaSnyaZd7a/cijwzBGXFil62l4Ku6VQfe8
+0aOaDJs1WFdgHtX+7T3R7nraaxeu9rU8GHOEhoVnzSBoWepwh78sQjzZf6ZAfUzhvaHT/DOg9lK
YRaIXMAWjYYW1thb0+ngHwBjCXw63AhNwCyZvAk7lEFEhs99VmieOniwYLRvdJHh1JtTuQnIHxA0
Mwl9D2GIVsI6OmoQLX8kgiIOljCysoX2ifahmrhAyubMaivrOGxMpYbQQQjt/6hO0nR5baU8gjCc
l71uxT1FakHG+ScUu58K2T9jQwC1iNWkppAmjFjzS0260nznBUVM4fm7ME6uczz75ypS3O/9Qezp
EvLlXp+3dfZ5Ave0HW3GoGH17jQN8NxWlnf3leKBl/r88Jxw0L45g9afdiiHRMUeROXIlkUuDvA1
Fp//QJpaGN+JR9oTNchjqt2dxtnnW387X4CbI+GFjhCmw3i/8e+by1l591QDWMKeQo0agvsry1n7
zMOTmG5WxOwBUvl2oeGVwJ3d0E4Qn4lUKOabeAKU2jH0mlauZzHj8/CZQWwqyoAjoj0E8IVNVQJU
gJXexcrOOhc5CcBBkY6GUuTsbjZkKm62imUumwwgjGoBfSXr7m0iqlJmln2MBjUfOWdKNMAC36L5
1GedG49/mGCvk9sLCPoNxllmn7vXiROMctRNU1eYN4rRqBTyG4rN5akZmPoqt6bLB43PAaFu2HCs
4p6i8kCyxOzUwsL5Xvqs3AAOFeMJEWITkwihfuYQ5+CXV5A2KE6o1lFmvt3KlJ+SweVEO3tqDXAF
jmcDH/KBEbs8cjOv9DFyaglX8ZSVG6IWe1cq22/OUHaQtDfChFW6/W660zPeFea7Blooxo6w3vG7
+YGfyhWA6PvlilBLLtN0hca0t/AVT6wqLKS2M5RIzNKWJqg30FINqRuEIebpT3ZTnJ6kkM1xuNS2
a76aubo/G+VXFI9paxtkC7BH5MzkFb3kAfLSFFvX2eGLfF+hGNP2hTUHzz9f+aXhAbbeOu90peRR
AXebYflTaplzA22PZIJZWrtLIUX0i7W2XU4ehipd6QfV4AukM4S1+Q48vxXwDhh+Qrv7YC3vILhH
s22EcfeluN20TWJNgDVzlh9sz67xwFpCJINTvlLCtrm5aNwlsM1GpHnuKlLgeigOg8W1Px9g0TiE
6snO/nHRjuatqwTpkGM3MQKXLLLW+Ub7ohRKaIXOAw0bO7dsEz1sjIrrFtK2f5+KV1hpHaAtqegI
3LlbqMnonRrDwGiRGdZICJ4mda/e55dQ9qgy1pWfzyIyPQ4z/xP+JyVN99yxqRFGHS4RDgvyEOdk
y3M4f+Ac1cbAP63DqxgHk3XIPfenZs2gwYpQ0eFBDQKUrAdQgpyXucQyEKb0E1B4DBa5ypK7PqgX
96/LWU2Dq9jIF1y4/rzE2GoohDc8j2PYAIIkzfa0HZAYzHobCU+gTQNwPvz6Dlp5um4O45fNRtjh
Jdqxo64r9Ppi1fppXqTKOaC1C5SzO4IROXxvqiIPpKEKf3brYvP4pHeohrfgB2NfBaXccszn0xXs
ucwvaJKHdqfRlLkIHB7tTujdeCZkVMvfwjnXN8TIHDiSKdNpTPJ9HuGnloe6b3I4lm0x7EghvRtl
ViZOhlMMMzwX4xSIE32zV7UeUk7SVBa0rEhPmJYaynvej3rY2UGOkGpowR0KJF7oRoGbdi5igFXG
PTGwBJi1NL2ZvfVTcOeW1SyAjad4RQBPyvNID6FUzcCEQH7WSNqMJhFnt7xTjWXMLQ5eHcp73b2T
4l0QS7NqW9W+GCn16B0d9YW0wP53N/qzq0mD5QM04D4e4cScToBydpHzEr59itxiN1ph3UR9R76R
fSkUkPuWLCdPM7t/+PYh5rg3aqGe4YIu0VqkXyGQiXRoy6g19/l5fVfaMBqXrhvFrczus7ayi503
/af34+9BUEmBbD9t1wvcZdBaoRMoG6dRmXiCQu6pnKo+3u9Kn8Y2nROmFQGnmzP3PnjtVyPvC2sn
5J57szwLiKXFw5mDqLgJ8XeJi5CCLsXv6W1xS7mmrHnMC9IktSIK6CXDkmPuws+pSTcvYekhx1SJ
aTdJ4GVUWjBwSGRFRKf9fqASwOUrAy49jW4aPNeaxWysqgCrb8+Z/Nju0u4H/LYt2ICoAtJ0Qgkt
16AfFhsYP+EtS7oOj3oyEa6jMtybmk9soWlL7xmScoMulKR12ZRzAOPJn3Szz4/4EXeUGX8y/n0R
2tRcQcnjN7j5elFqC5PDWddjOhSLRg/PRkxvnPndwLIJx+BzlLQhEOk8P/qy3wdfmc40pFzE5vqq
B0NDNnZGh8sZF9hTjutkTofjgqRst1x3kkja2jGk3Y5/kqDEDLpHrDwwKZCl8GDO63EY81etDNyE
7EjZR5Yg8k5n3BtkETbkeN/6u/quz+Q6vO8dqG0hLRvytrF+pfdouB8PkYMHRUIjZWSH86AfU7/Z
whdyD0BBsvFOwrK1qwPYW//xgphseYK1+7mnCSwWWmNkOWG/XzNpjbvGikX2mWVPnbUGrjzV86Ob
xJemH9k8zE8HMbMqWpFlsUncGPUdnZnQ+ibjiySfNGqyuJywJ6Z5kID0BvH/H1u+AEp1Hs2moGPA
70Y1CmXC6F3Nb4j/Z+lK84i/B9sXPZKdMv5+rRk4E5nh8K/hfT8jYmwKFZbyPDufQ+40uC2R65EU
lBsehEuX9MMV8lfPI+4LPftUKPjRFTSob58kRQ2gpYiZAH1Pzf1ggiBub53p6kzb/T4kHvbaOUAf
LHB/TRQWw09CescAtqK1FM2KVUKPOT2qYzeeuKHchcWf6l8OeKYhlgAcy0Lv3mf/wWWLD0ctJmoX
nI37wjpkD7XLCvlEic5WAqzaFiJxUSXPN3u85Blwv22T+FBiSJlUWj+nJY31KspfM4c/Ou1Cg+WD
Dmx8rA1/+herDyxsjK83zyJVjLJwRLSDCcPa5wgNHm0rcebt83jjOb8VYBGUpolkWFVzvYkJjnMg
ZZFBtjlNLUw1jfGypZZYwa1r+HXhajWohw8TWoPqMW8i7tDeUFK8kYEsOm+epj3q7M8+khh6yNaK
sy+LtTm3oc9PjZLPPlqcZQ6OvO/4WsI3/ustjij9QUj2r5KGj99Y2ivNuqaozA5B52KLu/h7EpRf
GjcaiDUQRxWCxfIfpl/nH1vM33/rCdNfg8pnbKB/SYIUfbd3oaZZpgbChz9Q7VMoQtrRfx5WkUf3
FnvwWd+tI8bZLh1w8vKu4hkb691eUxHu4Qh2JfLWpMVkRPmvXN7z/Wftn4Du3jLisl7k0WJJ+bCV
HddFVp30aiFufMvlwnmvU05xrV3xvMMjThB/kmHhftTfOl5NbVPeJR2QQsjUYpQPj2nC82qb1E3N
KYvywZo+u/EnR1DFhK/ZmRg6aKf5hsNFaCwgs03j9I1cxnRLJttzUafj+UA5T/VgIP4ptBb1NGta
4+XZJyBodEnBAL2+2BbwgL8FHovD58I4AWnsYWT1DGEkOz3H01hvA2Jlv2pV/LByfxS8Y3j3uB9a
eBNL04rGn/aaH0D5G7VhO0y8oEEU+D4PfTcvsWa1tVSbHero9BuURY9a7oPL1c4xM+xwW83G5+pv
w+E+jH7pNZ47WfQjJ870utxugzjrh3G/wyLkpyqxrqEiN/whKXKxzl0QbJAyNdh2oAs3WbnwSJ/b
zB+06pIVkfloaQpBZ+VL0qGu3V4BteuLW4e3hsX3s5NfEeP13Hc5YUwMxIEE1Ird6rnXn63812jV
xYKNUfBZ+S/RPMBdNAdITkfmrMGD+zx4AdCmx5ONLAXnpZzgtMuLUYc2gsVjThBVSgJGkT4BNmQx
vuPOcMX7CnKgogBUNd7M9I3oKlDXBV/2Bsmb/morCyxcCxE1cidmNnpm1okAgMmLwUcw+AVps4FK
1HOzFMeSKYoiHBdhdt4aS2oxzwwUPeSyOmaz/SV4Qg95zIndvtWb0xmM+TdxGh02uAzpJTqUZTdc
5U2Otb8VKkdeu8yewADirM93HCF9ZLdwjuq/HoeVusmvDe4VORFPZf7q8Ph1k/agdzUOkWSXasky
aXsoYRoAKFELnkEVIDybIaI7BiRu1HN3+Z0Ch811yfmdtQbBdbVSvaoSOUqPspr9ZO1WCskKSyu8
uKbNNuJ8WS4V+OzlEDE5ONJ0vWpzobJAYCVYoNIfdHJOCEdJqcFXMlxJVaqnMjY+/3LGC6Binmy/
9CMSTjR6fL1Bl65zQlIlNMuPZIkcgHPvUBhdICMPteWSWGGD81RmRy0bUsUqikZYsakTO2vzBr38
jpnk4DH1sdu1tJjC4284eDAGYGwLBa3OYrNzWwNKkyUXs7BxRhzyDpG3f1smgBNojMMabe+65cQc
kl1XiR6+im+hxpxWOGYITE9QxjIuX+Bydc1LLp+Jo0LVA6L5znsgROxcrSX2b6+Wg0wRPhZFqMAZ
GCMdh66xAmcx7+J8SEqp7ZBW0I4sNNspQxiEtWPhWSvjPjJm6VeRvZL5rnL9VNTVM2mJ2lidg7vN
u1IvFVf1RByh77Ta2EFiH474IaFHUZAq6Wcm5jV/ceRn+3OBNwXLzE7ROPXz8O2ssgx8NqBdCJEY
aVdX+K9h6O5ezXi+G2cGokj046o9LjLG361ST/3nhpVYm6LjqvD+g5JfUoNMrUG/8iiCAG2DMz3S
ymiSn8bJLB/zlw0TCnMiVemTMyFTz2oaicFefOBO6tkCrRKQHOJBtZyNcCqn0RnYMvvLCOilVg7K
dWAMLNOHRLqF6UHM65iGQ6O2+j5fBNan0xn5otLWaqJ4SJZKeQMjed7eY0IvTzBe37sAo7KCZWlk
p3CJXWRyXGE6v0s+pQUOQYeLDqjXafSexDLrY2sGYwM7nYvVGF3pLn/lWmZD2hBYrQUPWWqbQs0n
D1ONh9XG4r25IAuPykgh0qEf3wJuwICDBECppBaLCfNJKrbgODLdaSrgL2W1crFxA5dVu5mwnBsR
yD21UZt3T7a1l4jGRsYhNcpXrjT/GjmpZAs9Cp95zVkzXMYJvSBOIWtPXja55ShNP7Fs1wk/hCUY
XiLdbbTuaYgSFnIfRhI5HNyh+Mus36ut+GANhyuqMxXBZNhMVBiJC37uKfdwn6kLIqs02c3T1qT6
h1lHPHsnsD6iHmpQLyYpsyXep8ZUbtMnL9AloZ1pdxJz4PSwNEzu5hBkUNsjlEaA8/iX0nWI0W14
79n/MWY7Uy/3VUb/PdWXIpXfZ1ijW6TdTFgGxgoLnpoH4ndHDcL5j/v3Rf+aMMMZhWgFF/+HCDAL
q6Y8WDMrGH6nTFYUhup2dIhphJpKzA9BX1NNbF2CQ5G4BNHiCT1nFAysIEjsPEAHtzjcZnQD/l/6
4tzktik+DI7t6vbu3Yzh9Yl3RCh9ghIR04UQWvdUgHVoaqK1rDoaftCqnX8kmn/NUiICKF+VceTW
YMFBHDys/b15315/DAPGg1XztFZz+Ex7cfmDza7ZQmetNrHn92IC2uuqXp21Jo9nD9AyjuRu7B+E
O6ycdxU5P+rY/sG2zsFyPuT/h+GAFAM09CDqhTI3z+RJUkTYHynBo6r6QBmOb51esbCjdsxxIaZ3
dSNedhMBOxHkcNMUhf9PvMEHrLnz1hRrXCMKLFu/fo3Yeonm2mT6X1m0Ki/h0N4EgoqdnComy8ek
4UiiAT7FBHiSTcQQlj/yy+0Bl33to2SeFqMYSC4/A2GczAiPTfITpy44KDHRkxAPF4Ai/cEYuvYC
0ZiPYcg3ntt9lQKuSlKRIAyE9mYTi3LcKvDqXk53+7XprL55ZiKdUgQH45VDp5sosQjpY1/2GDhD
q4Z6PrdxMOggGcJMsX72XETB09xUaUaQSoHbIN+Pb5sXwDsCGwbb/pGgRlKwIID7ZIduChHp53Rq
n1Zu034/qQRCV5Lgtsw+2D2jhkO9/B6vN3HW9Bn3rrtkglrM/zDM72WDY5mcpZ787Qeu5kAq14Nt
1EOsurxkRMznJLIDIGiEeMWUB50dQ5m+I7uznaxORrQ9KM4eynzVber/hXKINfd9088Fn3h3Vd+j
OHn+hcm21sm2/hKARZt6SDotfF4bGyInFuzHIe43rmVHNTlA2h2sN15zOQYqlexAbel6llrX3FAO
JxjYxGV70JsD/taIPJbJQAZupjgLWaPhlsXwbGfdDM2o3iz5hfc366viXjg/tiLFDh0mGEX+Ak5D
RgEzbaCAclNjvnDh90zDVtoQb8J7Kv3nlKXPOQsm/KXtDVfK5enavOy4gGV+miiq+96KOzkBoUZJ
5lIPaQUTwQ4U8kelEoSQ1zokTH0zSSR9K6FvqkzcrdMY2BuJYYJTTbcOG+ERJsfj2A4KkQOctX3q
O8oOHgNqwm0PgZMiKAqKehWwxnIA2dfdTvEPMMnZHvR7FrfPmT3CltOW9f/sj1ZbNTI4SrQ/TGlv
BpckF1sdfBqvv99AihE2jxKwtdaYs/W+2ixaIrwx98brwQStB1bCuuZMbFrJZU9qfH0aWtLuTZJY
ZZsVNjPoO6JZMOVyqlsxiUUc3wdKkdL7trgquLV89QsmsU7Lqog6mDijRMnN4akqJbPFTv4xeRCe
TKKtO2kysFGhkApu75hA9e9NOS/WGSP5Em2Qj5WCs4kAt1kkNr3KXkj+a3ZLdExLfrsAvXa7paSE
rUd6QcLX1ebgz/jtBOy7TjXfYJiImJ9PH/6LTSgyliFrH8YuPTuBqDmcAz0/uX1wQcYJk5sZjGNV
OWtxYOQs0K3EJNyQIbpud2aM5r09XbDwNtYBCeONcHsL+FG4FNtWkDE5nBJB6WBP8F/+lXRaHiSB
g8dtPcUSRPmThYkRidG+dOy8J15sWNZK3LS6jImTzFN609hI0ob8vyZSY0gbyFPmF2+RzeOMf/EE
g7Lquy18PVXeXCbSVLw84z0XMaZ/zCjA1MntiEvgmoQX/S1WIicxAD7GnjwxQB0hwGvldTHqwsRp
px5HZZN2wUfcFUgiSd3m8Qv/TZN/t7jm9tc/IKAtcfvQtLSIzevGynoiJyPsvbZX6JbwWZ0uI/jT
mTtRkkafuPmtZLAH5iXgH8QfR4OqiQeJQ8P2CkP3zKnLgmrptPyM3TTnBZJBhMrpLj4UHGZkKuyK
1/DBLMF1mKXOa3rbsRMYeejIw+mQ5soBBUFGRZLGSmTG5CHYPUGacbHnDqux0P6vyRNkOdYwpTmy
o2blWuyckamw6OXm6N/TxeJiDLHyTTqt/F20yHoOCMV2Z1JreH7fmQUaTBkVnvslpgqnd+wSu9Jc
TMjbt+82S3DWtko3O93u5ln9kmkr7gMgLAx7GNQDSS1XUKHHah65dvyNF6V8hS9tovp5bOC2lGyP
Us6TwiyWXzOMzCLu5mrQWPDOXpLaH8p5mDdOXFezj9yo+G7KNo2UHrExCQobZqvzO8lwghgDmM9S
S+9uqmYThM1AXXOLh0ysRR9yeKgMYoAyM8/1P4q2In0N6T0flz310qjoKJoCbtKHGMScdV16dJ5V
KJpy21jfeMVPV4q/mmoY1iAq5Dfah7k11NhS1vMz3Gc4eGvUKqplu0ku0PvvC5vH9A5tvVReB/wD
TEzRfPCr5GNxXq6h+sYRpu6Sn0asjfuIIdk+92JkcPJ3/Hp1KTkCZy3Q+PrneJcgqLg+Yd11DJye
LqzfGSgMyQOf1kL3sPonejK+MAB1jjsGsGDaP50qS/s6u+j1Irxwrz52q9LPoBY44Lttm4uRSN0B
QwvruBqI4yYiPIb7foVuBl52dCJRSMAZ5kG0dQhAzOJhr0YH1eG5rVun/fP/ypTfMaIzw3nPZqjl
+t6+XtLzRs6bfXjTkODVUKMe7Avg7OSnYus9mep6JwrvbzjHYZqW4aXLqHW4K93tX6xZzC+XMhqg
A4yZP2sr9PSDGihtcPR6fIXaBGT/4TLASnsxOVbIdyQUgbd5PY2mxEk4qGAFzoRQxbXhiNQSGMD1
o0yjaVVydTfbIgor/FNcDcAnx1NOZ+XIwaZxWdqALJIvSQsgSjAUUKbM+F6PzwOxG6Het6u4pL7N
KfruzQzo2cAHYc/vsuJBq/2OxFEuuC9ouKAbWYoARvLW6CZ8VDsLMfeN+1yzXXYRTw/uDYNt840z
aZJvMkFllVkafqHF+raxux1wOFemTnFhVKcH77b/z6Qh0CMz12OgftQY6ZLWYpcS2ePximDXSiIl
1zdEpp1CVdWQcks6y79xvYQbzgcK5U0bIRAvFBmwigIODIixOogXHfS6JODlG+KKFNNRw9n2jPYY
ysqZLq2HlgkhrwIwwOSFo3ghaJd75jHkcVL2raCTTOHV4TYhYqmgI6uv8jhRoY8benUyT9cA7Qxv
Bf5Fd4slQOFzJSobeWGmUCMMBLNH4/LlcpC9MrGSIjep9oGyob/IfhWmBzx3mN6omSP77rUQl+I8
Le51vhVIKi0Swua+M2ElMK9Mq3XTvYXH6RRFD+VZC9LK6Og5k6cLgYK48dxVAsPUVBa+5te2QzbS
dP6Po+fuxdBbUfscWXVLBOLOZZ2QO9niCIBA6Y1ejdFf6Uv8HLQL31UZDIT/g1eDBcJzsWo41eq/
KTCNp2CnOAyd4LKo6yKyNhZbpYvnqT0q/xu1FjSxLLkf8d44bTbhIywOZsDFaaLGwJ47G3fqpQCr
ufVUBcDThvldcE0vG0V/YeZOx59rsaU4q1bYxqfNSf/KuHFRUYWaDp7Rd+nEV3JrlLCsZmn5//42
CJDci0AkATH6QOAy4FHdPJSsZIbk93rUteN7wTXrisRsZmaloRUiF3yd4q3Br/MuXFciCUlBMsbl
qy7qI6+sDD8IBWMfwhmrHs6Lw7DaLaa/gRAP2OO1bJ626gcvPoeEx3/v3E1isvZRyb6u/t7RFM+H
pfJUocMlCMXbmIUioT+WCk5c8gWJXNaBSedmVSdR5j/2jV8Ouz5g7VuSb0B8VgVidOTD3jgNioFq
WryKpz3miQLHjDuTCHNk+WXxxiNLOwRcyazLmkxNidMI1UKWSZbA1U34bqempD2XYeYNitjRwRqZ
/0a4diWpb91zehrkYaVu5idPF8jPyZxCmqQZSWtTQdpdWJw+c/7gTFixCNL/Drbw9WOYsQCjHbs9
zkSD8z7p73kU0ZuFRfWJ799kkRr8uYREabeQ5y3IZgD5cFY/e0zf3I4w3LjM+m9zorfqZ21jMDmV
OGpLOTMTY/DxL5w7wjT7qF38ZKg8/DD7180RgDLrM6KgGi4rQkxsSaSIvm8Fnr+yjy/Boi3NF3oz
BsT7P7ig2K1qBnx+sQNNvTwo0ozbyvstKnog999WOVTj29zzNEfysgdaYRCt6C6Rv8/iDLxsm6Sh
daZNqbsUYwyklhRN0h6ERF5anNJ8XNuTXh10Tbtr6VisjiDG7NKElo1HN62nuLXRWWHogpa/fcX2
I51h+moR+hBUJs4dq/6zuwGlwdIj5VdulFNVyVZWzIZGD1dvI4mCZHLQUvQFDDV9cgIxthmbw4d8
2j0pZdDA0jT0iLd6xxsEVbu3GEkdzS2LGiLd0LX8cc33rZ7QCkCLiU2iWi0cFwFHMP38VeQYb3kb
jNtMrDgEa0EWa9Zvr1A8DQ5krYGPjGH5YbqHIIneZVk6imY8RdB14kEuugh6gF2lW7q10v3ssX83
j8KT1U4s/U1suKo9cBVnqGucfXgKa6zOwX00scRSnG+EVbWzoG6y+3MQGkeVnnbljcwQ9lfh7EUU
d1d73M0gIt1auTyu1Te0ECjQcqKbBddm2n3o+2O0TYFe07yri5EF3LReZlxMQvilq7Ensu7qI4H8
YVtBvhyD8hKghXC2OU9y9tsewlOC/O6H/7DIxMFouJcCyLwnRfAqB8+Ou1KI2tV93uUWXIKZghMH
s+ShCJCQz9qeNHHaNdmxzHU0QaM6YqlsoRa3nqqpW4TZcij/DevHMai2Bnqlx7H+qcWHABYTLN2S
XlrsohIlFftbxi50FfRC+cvTcijuyVR8Uh74sQzjgu/6LB1tdTeVUp+904XgVPCVNtGErgiRvo6d
l48EJbv1xqnXeB8Mx8k2Y+lIN6dx//I0vozTQTij/vCW/kbEdQU1oqircCGGlNSLAZhEH1hD30Q+
lk3lB4eGZwP1/3D8bW6cez7u7KH3ak2sXbXd77aTQdn+QqK02MLiR/q4SwEIrzUBeGyAspIyTCA6
1w2hJv7yxaUyIeLZnlEi0Y2SJX1o+bycd9b6tpXWDquWYNoQatQN4uhqm5rVOp30VZE2RWiK0akX
xs+IDfS9q/7ZbGt73hnUS6YSd7GeutUrqpaR43x5KRYQ/8PA+MGNzZNiMBHL3rlTa68KBDjdXFw6
V1xgyjPRHzByPBAqmMPYBoAPJKBhgBQqqIW+nPa1GZ33ocjk1VTGtPWmnTzYEzcuU66n7KaumAk+
GvqkrPefjGcRWe7myugf2oe5lvKTSpFITlTu533UEFNB5jPGbKLqWSXvvEr85hexVLQoyizFLx2E
wr/YR/WTKdLYfC8Lber/25ThOFD/oFmcgaxNgn+2P3Uy5sB7Too7JA4M0L3cvBIITPlMJOqU/Vfr
AaLgODRYJCLsFhBa2txkV4MyopptOXT1GJ53WvaZ1eG6xc5lTBudPCb6c+fNQwyZR8DPQeLn5/oL
WKU83oYA6GXT86dNsL9doXSbnlYphS2K+nd3tv0+SBgIvF7BM2uPxFMSN8lPdFZQsImJTtzPrvBg
GTaRKMr2hbgUWOvykU1JorvvZ1B3KTbymlIdWYurYija55sEwAW+B4liVAoOkWzQuiq27ycpEF1O
Sl0f4jF5RVwYPRLJ3lreqANDAb3Iqa9NvDU5BRSlfeIYMQOiuFH9qbeJNOKQcjTOJgjPDIou01Ko
qX5ooIHVk7fSadukT0d9v24Kgu4JajeJ3+053QQVMNX/q5Ex89ZJRlwo19Niogz02YxUUVokI+Oz
glW8kG4wqYm/KevKnhmAcMdhnJNCsUMvdRSDDu40asxPWTvnkJYB0VDPlg3nVjRGBP+/XO2mmEIr
keoleLrwSSf1vtJOruhJLxfY8loEI2dT28lJcowvNqsF8tKpTG6oA++VtgzxjVJEJpZqF5vf9koA
qYbNJmpJJKJgVjdapaWQiVU2PlK+2Whr4yTzBMYQeukKtzloFoeN/zkrIu6WIknuKsTUpNFY/By9
xrTzDWuyUPzQKC+U4egSCi5doNc5LVo8N+75rrWqnqGpkdnsk5SK/+8Y3tuiIy01PUcIv8wSWLzX
TJM+xCL03Un/OgFMsAxnBE7lDjSEhqE1DVX+OiNIojWF0/AZEmuC/Be2WDuEYDjhKyQaFECdNXMM
7Z+xYkvophQsJRCrqpyW7O8vzlUPohNM77oNWY0YKnBrj6W5QqMgFLXrOEjz6tfHDixc80IA+trg
XDegr/Q5lGp8NOS6MXlLmDckW/wRYgNlUYkvIunaiKw5am41u3pnjMMw0sBGQCb8w5G1uE5VBGWD
m+v2R4bXkGfbDsJOClp4BCz52yTL//QZJTOJJsbJ4L+uPlyTLfJYsuUzWv6BX7M9MU5h8YJaHrUu
cP9HDYDz97sLs2kMuDfg5PR5U8KCFNDAdUhVPB3/lF2koo5r/gQzbFWW5nBO6F4ylbQY05cQ4PlG
yQd00D/FQrsQgtbu5LjOr4T7D/8zpTUR9MqAj9x3ARMAsiCJ4WPzqtu2RrvY8AU4PyShBYPv+sYy
NYkkyputURVldHvtEjZ4kpXLqzMPVHnYzLOpbNvBfZCsKSOxZ1vw4jl+VWtWAwqP1coa7AU2UaTL
LMR07NQR3nARXdXjn93BiJtSGxlzY/wXL1TjRb7aRf6Mnoxqroh0z0pRrQuyaBbYR9K56F5+f8fm
8IOJ9XD48WmBhwRBjhNLh3go7Y8/oUlBL5+7xs4bcMTzmFr6Qt3OR9QV1TJ65oSAadm2MWWYr1K4
yQvwv3iHJtYtdBt9Kh8TSDO6Okwiz46D5C/44LkL9J6H+2AM5RhDUR+mTt/N44cDn7RQxQZBGxOX
Gh+t1O9TCDuleI88NkRoGAEAE5qdxMCb3DpC2tK9px9Lvl8QOxb+EdB1jN//ILzzvXiSrsqRNT4m
6gegfnLlbWFmALO+wqHQW8MUIQzKYAfIJEnRAjS35QU8XjWEwAcDPDYLBFPjzirUUaUmTYjTZXnm
wKcZtK3bC4pmrC/S4VNuuMkw6jSjh0UHTjSWDA5MVbFAwMf9lLAsyqM0YcpXvsP12bJ+siVVMsgd
/jRO150N0D6f2MuMxy2oTYP3hRVq9m0xUhlW0wZDkFEk8YVV1l2ARKWIN5lVMmyZ+ghk+0NaKEm3
Ghnii7l5sX9JSCFYzd3+1QSKGU2btgbB3T7kb17zQHRQPtb0IldMoDOtChTDqFF/5FItkRBkAtbB
xiJ/RQvWXiAUrV303Hc4AseQQpm2aSLz4j3z/iMBRaSeebvltp/ntEnXsWmXGqy3SiDMV7hfN6uk
SCM2m3UYOeIMySMZx5nv3hIjwKGdaMWQnsnYF1inuuQxI5jGZzOcW0OuHnq7UNW9X8MugrvLXXbf
2FpCw4+lN7G17uaNmYqr3xFJaRT0uT32xAWTUIspYVvJXHOimcjjoOUFb4/u7yuz+fJ+4XX1g0QD
tEhlHtJeci0Yaj330JLZNkXqfyuSR2pDFm+6rum+BztQJHqLCWBEnp7BLrcSuwOqD841zUFukpIO
3gc/705L7wcoRmDKF6vqud1yn5IcuzYxjcSFgdhB4ZSgkwCkPkPugS7SKCfCNiLZoNfRt1yL+yIh
+qcpuw0N/TOLgMIMtTOhkJTOEb9D3KfdIdRqga40xLq4sKuoVAHVkqy7UFimliCxOciBwP1cGhOV
kcjgwnh2urLnUY5Ih1nXCkbEhuoE3kIJiy3apuR9XxJ0fXkIWRzeiE3xCQzjWKSJzWePigwNooOS
+BWd/yDBU4qp3ucZwcBv2galNTBIl6ngcT9cAIdSxGtYS4z1yPgSSLCgqT7ajoo85kzsj1RA9zGF
sNqlsEycQ8Kh9tZAreTTQrWPM6b8HkiUVVz4VxAAYRlGa0m3Xk7uL99iGHAbQtHcDBiY8fG+e8iv
TwA7b7x8S5knXQFo/AhE8aivgnFR6oeynFFfn888ZxfWRS5MluRokZmXbFhNWybPNz6y3Jr7Sg4t
5zLHsGPKldv5dYVFRuajKTasBLGtaR6UyaiCyQQdTgg1dhvVsRqJPZJiW21PqQSwvceh/L+24H3d
3r0cFWelkFzsubk0j8sPMPyHl2ljtS4iH61TIWOPfr0UCQy7gIwI+b26DE5TlSaaIArsesuABD5T
yJ0z5DUjOjrzKlvGFqLTx8nyC5y0U0eH7Xi3/cLtCEgzQ+FDayKCz9vMrlsB/+sw1oYAopnp1v47
+D1lvSrT0iqHP2JUXlg5mpR0f0d6nP0p5GxVUX6FOFBaga742a3vo4vXGkhBIxYTrcRvV1uomJLg
Y+eD8fWvUmaamAGrxivc2rg5n+XwZZultZafU55ew2lJ4HzK1CbuDA1vYBoxqeXTQWw3jOJs/3IF
Cv+a3FsJBX46NirQquhpxvaoesflnNBVDxd1YZZeTJUzyxYB89QaMkwdgKReLwI/Q2QiNmw9OuLy
F6FTdZUs20CmhK9KJ53IxoE1ZxkCWMoHi1i9zZfJ8gL9DpkRMeTiiR0/Pr6aO/aZgrI2O9HP+b7M
5Gbny0tbxt3vCTIDgo68iaBPKYP+Ipn3IODVODtDvRyE2lCBYepb3B8rnWBAbWaPmgLYoHflt4f/
v1meer4Cnh3dTbNlHk4ze9qiOoUa6ujhBAz7oZBJGcvtWeFxhldIluT1qgHodM2VCK9HxKinlKUz
5KvqL+3ToRaEkli0RJOk3DO8tnmhtm/4hHGBUm8gF3Q4DEbTSLfofyefCox+HBocpHkGaqyBpPrE
qKR6YjHkjcHYNfxulm+mV58IWktXqzUHoUqAayODMrioekEHL1GPbJwLBUZY2ZYL8HZitI3TlBRf
eWrLhxsV3ndCSztYm95rtEEjn9EKxvwaLPmJMK8TujxIwe9qk0Y4LGdKNu2b+Rt08elbulJcK3Bj
8rGAv2cLQSCbqLRbHrx52JfwD2eKG7W0sJnf2i5K5OKJYxF6T41CM0nHDJ6oHNjXegf5pzUkkG8w
6X+Trrm17BlRRXvX909Bq6Q8y5exDME/GtvbXq6BTXTpk8QxTsuAH7/aeFbu1N0DW28tkJxMfbUJ
0e0iKMkagPlajgBRaA27JN/ecw55GdhcDS1cCZVTcx03ARMOGyYJBszTNqx4Ybmcanx7VW0km3Mn
dzhDD4AmE0C9Tba1Ig9CfbSNorfmKjQ6tnp/KROzFC/GU64KkiDrSyL1nC2meN9nvaSDJzGx8yWp
7Grysrt0uT+JzoMWfxYJY74BuijjMS7Winh6W0jAyWQNfS025E1i9CBCxMSuNRZWW6bpknCPPkEb
j4G4C1lqRvDS/vwjInComr1YEnNkOXVuEkslX65rJe6tAVSnSoo+Rw5zgFAgpo+Vcnbza9h2hwxt
lPbMrajPsTMqmsp7A2V+Y1yxXcyTMl507Cl7My22ghAuob+scSGHzYFGlrJfPMRG3HtnmRwgBlsO
32oe2QIXuAvV7QEDmj4TGW6DyRn7zIT8SEcBwF0nvrj3P8+WArmONLCdUIkEWepkU5oC4eqskGRc
SxYfSrhoSoF05UKYPbJYMdy+R9h9XFY3IMRn21UIbH9EscyeorA/yWvIWkF3sd4Acss/arputRBH
jqZW5hkqoJneG19e6r+aRWVCLWN1cNwNW8pMBt9bYGYrSJb3zcCcjLEb+5+DPl9HosBXM677y57h
Dm8AycTehvF/tV8bTT4RmRW7auO97VFz9yjV7Y1KsThbxU70Bh3Rs/r/n8yXIUHwACHxr/5SIuPc
wgxMYu/F45txM8g3173IYSffonmBOq8y2l5UnHNPxEJrMheP+DcnGb8rMDDAZJXTSnSx2ZE2fpCt
vSVZcurYQ1HlTrZ3L6PMazobWbePPqEyIrQOTcaFHVtPdHqewRIx446Uv9YRzQJLsEyVZE8AgvSh
HNWav5fKJbfgSc3T+GH+Iiq765BkMlxzDAp3g+GxuRG3q6MeodA+bchbAK0kzk9f8vZ7hHFohKOR
+sjFPC2z7pA/1zRyMkRn/Af0GQJ0142xsrxwheq0K5mgWc6IvbNKXLhxwMmzsryv8z6v3yfLVmUv
kFOYE+bOwhZqj0q/mut04Oxw0RB47VDfhrA1ClHQFZBAHxttpuQ+rZv4YdL7W318LTNWbMAdcGgu
HSOqsnXpb9S26AmK34c8KsLx6qbKEu0I6orHSpEZ/9bDIhYIT/wdFfCtU8NVlcLjydbGzJPoP587
dtu5TgSldgH+A1Tcg1hV8P980QI5QDQY0/IEX/q2tI6jmc473FOcmLDaHj/8RKyZF6TSdjjbd3PU
JAeo5sNwPkFBzJY3AyOUF+b2pOw3dVBYiGTcvVWGgM8FMfng5QrqVSRGa1QptuKVJFUuarZcYNIR
LnegKcaPA7yN0pe3oaoKjOjVmZzrd+/0hsnY/xbNC0f2b/whVJXt/HRroquDFtW+If9Y6MW6e8Yl
H7rl0i+q/+XDB+x+LGHohA9JU3vFeF/Qqoz3O60UF7KmmZWOEvO5wHy30ETW4oFumzuQ+CGP7p8e
6AFibmC6j5KMwWak06vKkpVyeCjy9GGOwNV2jUAuBOX9Wk/CES7ZYnwYa10YXEom5rSXIW5YNR3G
BTlTZK6a/L87VeRPaS8iYqeAF6+pRH2HOTMzBKNKaMDvn8HYfwuof8ONVWzWHOhpIRyflYxtoj4e
VtegzPW3EVbWzwsvgTm5MvinAFR7a6Uw6BU0yQI+IM3gs5Uul16kwvuJaTsJVW35mmV5QUHk6pSF
/7Wp+4p3goW5hIN5GRbAlHRlpHKf2SJGGDcyjuwOFQfrdJEWV+fabNK/8IZbi2jc1Xkwxo7lZg3R
4zkc9aqFpvtmlSZq1UOymRGO+8uhwlrzjJY1XocBRXLLq8+NLXw/r5Ph1yvkDjhR9OrPQPoLcVS0
8m2vx2FWYFtxU4U+fdFhdHO9EC0fUJ9rKi9sEWKLLKiovoM0/DHVl5LlagFRoXgxlG5/Qsmb6r8V
aqOeUQLbUvIUL+Cq8/SmX03LbovaaOOfxuo7JfbitEF7kuyfWQLiNZiS95XhmtBoQ5fCKktSfjAz
FDua6vsG0xcLHzfYBF+hiJmxjzZvDxbaW+cyyY08m31He9f/RCdzNdRW43XoZnSB8tdqLRYzwNzM
NdojsAx9IMJrMsCGs9Y6G0/yjF7jbiDFZeA1nZhGle798LO89nby1+UavIdef2rhRLaEXVxWeZV8
4yQF91aF/VyDpddKSvXyjkBZKtf0+e/U1gDWsFvDL9b7W6EFpF+3GxbxCZ2R9oCx4U/lLtJQf20J
UlWifGdx/X9m2ijpi9PAc4F2bMCgn+oW49nvVUdrx7MEK2UdGay0H29t4Na4zy/b+CQb2j8WuplM
a2phqKGf9jRe5kACrcxzuZTYhfETuzfRXyvIG0Dr14LamTb8uHKUzKY4pVav4xTzeFkJXT59SqJ4
1BqyNjI2a4G+/TWJfpCQoE7rROPhclU4puQDt8uBVkgXXPRDoNyww44zh/F/zvn31LtG0tDSykTe
9vv5LuhcvNwiH6yOI4FiuqP7SPUTspEnzfgk+YK8naBqO2ntmp0fJbhpvXxpes7/mTVbxfGvdyi7
MiXQnwQ6XWzEPPAoQLNW4R5jYnjD+fmNbBn/wv8tQZvhqxGpgelDNGx+XXZKNFnNT3nSKNbbljAU
Wk2GnxJbfq/dsDzBiXI4mRSlpw1BmGd1rFIdTwjhZBaE3swqtcPF5hHA7TLqW1MbDt5g0cY5iCZN
ka8Dw+MIK+yrNtWsF2NqfpXB6iPDBT264lpdXCxv+qoPL6WQICJHuxN/KOmBjqmb3SX+DbhS6k3R
WTUI4aTqaWkhcktsgMn6X7MP5H4TPtHlxSb6xfqSmicbIkIdfyvZ+12A7HB6zTc7WsraArWP9Mgu
k9MUY+wrhpoOV7SXC5EWFKX5viu/Fd4xYT3SkAIwLAk6dEFla84BrkSJo9o2kFhbdEEuwVbYWAwd
1PNCTHzPzXUPY0GjxQPd/IZEv8ItJCUCuDxCEqTEjJYCvflkjpN14jdnr99BWC/K9e9Nfibf1zw7
UtzXzSSU9GBWbBgNz9Oj5xugbtsMBN7MO4YUmINyljU6OicUwsBIVQU6mS5n7ukkUdFEcP4B49Gs
bZ859zc8axRFEl6Y2uXVfwxTDqcw/76kDSGY+SwGupp9UXLU79GRMfRnulDrYfZu4pF2lS1GuGCu
g9bcrYr0ZSJnipjid0WKOvZXh7fVOrTQiaf1uEuKeS1wDoVAUDy+AYqx8S1do7Xy5HvPHMRO9V+A
Jfd1iB26RkJHYmWpDYSX5lw6EH9Idl/54Vi1kacy3Kikn4TrSPpDKS2smAblVsr8LhvF8U6XmHf0
mCjxAcEuwWO+lhJj0gw+OTXhnm6MJfpTqPTJkIOjj6YKEugLtnkvlNqGR5ZbIGK0VrAT6RqtBPTo
j1GxtHpSWMzgdok1GusI1qFpXRbhmTUK/xOpLUldrYOyop4qdJo06O534y7qfeAYxHfBfEj0j4DU
uNzLu0dk4K+JPcvtMS9nNQXgfS6YccE4URJRkEywTRKDZbeKrT9oN9iC4dxI6XKynjWO+wZLfBrM
qG6ZIeU9obWLt1Qq3N8pih1I/Qbo/umY4Xw3aLEXO0tObI6qtNya0141JFItc/e4U1zFhhKUqbtT
HfV4m1aolnL1Rla3CitE4APiJyDcwscNXyZkpshiVR5tfrxqoFOodk9y/kHLNRcIpkDzdbXar8A4
EwhhMq1t/3RpK+7vnxh5LdYDJn5PcvphwZiHlfz6Ulaq95IcMwIn/tEniuDDDaaqU4Cq5g8nIGtq
GWYBPB1N4CsF4yBSKpJt0zAW9XRD4zFcIAv50iXiiY95URuDHSZfO7hNbf0Y1gXihLSxcdEyNaEs
7nnC31b4oZBmP/1RWaAxGYcM7fD8k2gSSlLMBZ2+I1H9IXcFj7O7BDOzjAYAGInW/2LDJLJvfrT8
qf/29gIqwcbSm05AqKKTJM75JLoHjjtl+SqaC7gHO4g8mNm7J8Wt8F3q9Ca/WfYMw+C4BlrDtwck
EWp2qSCLHsHVTAFNyDUhkqDs9rlRSGlwSosxBfYTPrUnYrl3UU9lP6FKerDWFVA/VJi8WVcWlMsm
EHRzEyLveaK/owbERYzwWIbsisnqWNvpyI0sSvbGjGmkGHTc3NKL6sBontBxI4fJ36VAWVhR75KJ
3f13s65AFP0OE9bPdiALOUoVMWsHCsWZfY2FQUQaXI8VGSJC24Je2sDc2JKJULStyjATu0DYcig0
FcD7YcNWwOEk31ICqnmcjBbV0iBwKCjE24YgA6uxHOz7yDY+4D9qJFRXaJURoD+dYjRHHCxd/X7q
dWfp3Y9S+T/SmMi54SdDJXZ/xtHwJCL+eCe/ABIpaWSUEBRqK6rWTm54KS1L7BvsfOBtETuI545O
Svp4aszyyD8r18jD668OzHK8bap5ZYpIVmtcbBPSz1Xz0fPuiGqCbn8PYQGa7MIAnaVOz+y3hP4f
f41GAnqw7JWUtYZ8Cd8bGQTBlLyk1y8YxJ7qUiEJQlVonLR/wbStYcmzimhOmpV7prSBtoVlWmWu
Ut8e8RU+fiLEzqLSpVgVfsHM7X/FgXZZP+vCIo4FKYdq1OaJfozGC0KzV0uMOnd3zTRsDRSFEkfh
l6UVXGReHMxPUrY+scXqPoIY/SDspEIvghz1SzzosO20qEridS29ZX5TPVVJ01XFn72XJysOT4ip
s2kfIt33LyuixaSHB6xgqBCghraPUUPWC1+zfges6LVzPW3sH3ccYEN/xeaOozpnL1AETaawMyVq
fQf57sXMWd7K8Ry5qqd23qLhPYn7a4CCBhHuGvdK/OB7PVcn0Tkqo1CVt/nV3pu6RDy+lGqs5byd
dmlf3/Nd9Po+FQQ0Bi48a0/lOh3ib8mqJDywRoWeNVNGELDaCHqq/Ce0ZGDHlmRHP2mHSWMnWH6f
Nk8cPwnrxXpLA1mDy0k3wKDs/AkwkFx4OpvYd8xOLFEE5IRubWg9c2yHnhf1e+FpWs+kF3In0FEy
JFhmCvrmcpU+lbRugvNnO5w+4v9VKQhG3KPvSu89OupW9eO4TDeWBTptjPRly2aR75QIOgTbC+0S
UQoAsyR6TPKj+F9YvzTVvme0A18s3+2EueZY7YjXLMthcYBXlmiWZe6zuwzMCWzhnUeV4rZPd79C
qT9R4Xt9SqDAXue9aW+ZfgvK/G8wlq9AT0KQp5hdGxxmkLp/ik/VtQTlTyRWaYPQ5pWSUmK/Vmju
6s+aEmNEKHwfmceu2hFAyT2NV+LLms2EVh/ivL37+o27fUg++OdbGqgo8dtzHS8LjQI8x9BsCyqw
s9V5dguN1DiinoOiWMP5aMFA80xEl8SPemkdd4NOqTymDyCEdCjh3b118WDJxoUgdl/phKoHoTl1
Nt14wfSK5y4gimENqR8XD/Vol+rjxqSgLpTggF25zfiKOafBNPfN5saRhze9C+mA/hdLXGmeChlG
SqXkK6Ty8owNWriTd325YgvVCwDt7f1vCg3QY22ealRxE9qvZwL2uad4SnfJAAuRNx7+FIVJEqUd
5WZPyiaifdiUQNk8/P2z2FtgcRZpBD1r6YWizFip0d+ii9Aqlazu1wun/tZBEMVEVch/1+5R/73T
EQgo0sTCBM+i+kEMrWWiOo+B6RqMs0G0enzU1rEsUpQ8GBea9TYHmcegKGUWyQRYS0/h4ylxWNw5
eHoEVZr5+Psm9q9uVvL/ZK+WXsDZX4tGJ3tfeF4C0HgLP83HvH+LTF8Uy/59n5ITVHf2yx6KWgIb
ml7z9jYInQFbFhSLOMfOUMfEl6XR5nsT0jcaNZ3ALXTD5oi4oDQ4CPCSEA/7oYKgTDBk58U1rAQ8
A7w24VTu/k9YlLkCu1giSjLcR0/BVQuum+smiZbEEfXD4B0FvKl9fCWJaqXjH77V/pX7McPnKlJx
Pp+KSvR5nbgyL6nKz/xlMAsW+9+nuqtLsJRrdSDziXrfzizsb6pA5jx7fTQoxA27X+IlfKp6iMy4
JZDjxn7jYj+fwdocp4hRH3xKedGhc+IjIZyZFuK/oCZRNThl2vRLN9IgHLaP1KtS96Vtc2SEGZ1d
rtLFzUIo8l85CsS5G/JpelsYZ/CcSVJrFoTMzamv8n+ZE5razuvdtufdqDXVkY75u9gQFpD7WO8N
U+Z3i8L9qvUwMH+hz+1TJjwSpVldCyNu5lduRq6REylN1bwJerC7B4z8lTvUFQdiXionRA/HBFsY
IPmGcGEBGwzN3TiYQsD02KfuFaHy2GEAxhAkG4OZcXwFrNfOGLdzSfvlAB00MWy/D8PdjosufV3f
KJA8iMP8d2EYmn0GdW3N2++jbxdldwJWKX/cmPNE760xV4l0w4Isc0mpsKwCh/E5uSN+gulsQQlP
nBtXAe/15HKCI15E8mPHijh423oYMwNQNFk7Qlj0L4PW+u5uH4Bc9g633QUHPXvRJnc5p/0WECLe
MUVLb+JcUtKZz5dEL3hrpQI8/LUjVbIVmm8nzLUt4wBuJ6ZUxscPwc6uIIupBBiHYlCiuV0XP0Q1
VgWPnZesZ4nWUFi640PsdvD7uoF8upNX7A9g26bvUBLzCceglpdHxGS7IHt1MeRoJfJIgn57aGgQ
TUDdOL4O8amRFK328AyynfyoLNY31DuVDK2P4nN7SseuzcGIA3LMNB8qNSR9Nc+5keGMRIm1Dljm
5uztdTvAZ8wbk7rbVsG52Cw0LyyjdBxbW8otqLurtZBQqecngWOts2it4PNzDKxZfynYDDoHxped
oAy0OGAXj0PlhGrwO+IXqtiFaHKbC7eMoFxpwi3+nl/GyhQ/sTgDdRwDyNELxFKw2JcbNKnCF3TA
HdZCTdcAuU/LTWg725IhFbUxoaXIBB+EX/9eVeo5jJ0PsaQ+8RZyAvv0JeNyzQRTHZV/fo80F11w
6TO3yP/RMe8WzCVKXhmUEMtxdMoJlO0yBImAuLJ08Lu0O7xkk/CACsHaG4hHsX+LUNdJlE+I/3wK
pWoaJyX2GqoszfCGpVeywl6EWBxcawC4iyIiP9xx0UPUbVpc6RFeSc00iCsDSBZwD/Yn86D67x5g
Ymkrm47+WOq3CNWg4cHJB12TX2Qllx0xMIJXV/uU3jTtHoLc8sU2WelSi9GPmFQFfFeKE/aRnXO9
sPL4uVjyQ9LjRgxaAmBh/AWzhhdK2AlEE8oJHHtNipVtTFRpikFSAxLDXPqj3DspsQFjMagFJ6Qa
GkiudxKAfINbqHyWMZBlwZB3Tcb5fw9WhM9lSK0Z9xLvWeOAJpWAfuFKJDNx4Nz11guy5mhkfwxb
xpObV/kRN4/UVeUEvrYAAMVa6eg+XYvN6klGx9W4AYCSUeUyY4fu+I6bjkJI+q2lupgurU2ooCOV
CeF9GTDyrc5uc76I+/yTkjpOzPcQslJZBJoAbYPrtZNPl15C04iCodkek8HDAG+vs27ceznVIH0/
84VIklzu2KbUXt+ucIkB7BJ61odvz0ae6G/mAln3F5Tp+fLBNUDghH2+Rvq8QcQcXC7pUhdtkAl8
LGhFzTrJoBFAUF/SVzSrTSIK7wlQK18PEyz++BjkD/fjdpVCU+ZB9c7/EI+8uLCOxhVJr29d/3+u
xhIouaMOOUKiQdQ/58x5Vfp1zwIUIdXAUE9mnCSBS4WIP1H527dWYPFq/LyMfEdpokzfWGjs1BqT
a1B1Nnrj3dAsHPO7uugOPXrPu4IaeZ+P4Fz5B+3cTPADYw/Q3zdGj4xbFH7g3L7AXJK5M81N/tTH
pbGdUTVmtPbzmXkgLMHOHpMbCV+zwZP0k2LULKS/94WJEcsK6UWKOiqqS0rImAroleczXq6Uqpyd
UK6JVaEmVeGj4fbXwbTcY2oo3Bg+Xa/MjqP9ne3hTEPoSQ5kfvUBC7LQIZxPgOu3nzFUIM9XdSrH
LBktB79/KficCBL4PDvQieJs2iGp3mdFKc+acwtw9IuNx8ZtWQ042/QFKw1rfml574YvneudKHIv
y+rVYx/4lT3fTvUAlwkfJBkc9vLH5qnT5bm2lHK8uMLzq1HrSXpJO3qJr6WGbE7A0udgelnUbPKt
h8IkA0OCG7FOH3Fj3ABm4pSSq58rVWE2YTuoOkh0oEG6S1ssMqFdS2c1XL4SIu5LtNGTIkO2+T4f
4VeNPJaRILB3antlKRRA8QJ/SWxSuKn7CpXmbKKZumx/2ns6gaNce1U0t8QVDOi2waGQX2HKqUPk
skkSXaN4ox7XDO/lDdeMj+75AzTtGdJGsxDeXio+ukJRbNw8Y7cDPNiMktdjwUy4H1qtSm8sKdJ2
jQx5Ani8Itt6QO/x1a8RwC73Z/jZjT5a16NqXbHfh82pMheCEcQNcweY3GDrG5u6LTuhThjo6Juw
PzGZ2GY/7JjWS1JJO424MaOICd4JGLvbDR4cZDLjABRhFignrkplgW2JawpK+B83t5LV7KbdhEkW
/S6v6JOegS+vJPpXIqjvUUm/rlFBKCPUivACQhu+LkBuW2kp9mJoOVSa+oSc3zGY+WdqHPpau2yX
jytHu0KBB9FpHnjyKFegw2Tf62h6/zcex0HMFhcZrdyPjs45ZZddZj8aqbQKfqmmlxoJqWkKNWFe
y/WXReMNROhk3GYox/1n2MMBw64GLYFbkNT/A89lKDHN/kssdHXxMNqVewFeeJxnkFPZhXHlq/dG
301HoXzoC/XQu7IWQLF1k+aNWXpXHU03H9Qoy89JBpCJTcOjoLeRnjDucCEc0HKsiGtaybX2HSKh
Z6Ygl56me/7YeKwf/F2o70vXr5NyQrvHxX8uJX3ZxI1LlEgLsllT4/0QykaCxxPSz8Ibj2uqLKmK
FakO6gM2t4ZoIcMsnSIGlZg41FKF+6GD9jxxHBNDJfz4nRQRg1kWlEZoY9Kp7Y6y2Y68lwbWrLzV
s7Zyio6oR/k5Bxoqs60Jlkj+teXvNODaJPPjOzhB+08fuACiiVH/vry7YRc5HvfrfRvyu76elHbK
hXqyh2u178tARx+gx3y8AxWBTcboAvnsn2tCJ+ECcb38+Q1KNzVUpIlFdEEIVX//Tj+i++d5rVrP
hoyN0BfvBmQa2rJHThU+JHxO1ZbiatkqdfLP45lY1m5oda5wjG8DfJFvC35XYxEKTZ2vFgqIMorG
cPViZPn2DAt7C/Uuk8214QHf2SiqOOqAJU1uTFKIlcyf2QYJ4Aj+5+fyw6es4GlFxnPrAfQ08u3R
zqzquaW9LGCox30btSJte6BIc9Kuf2yCfbVcToGPR62Cmb24LdnA0RJzTsv26NRBLuAIydhtME5A
8s0snwjnbRscAkP/r3UEQw1WL5RWVHrT5tJWMcZHpbTlmF4MqD1d/hC4sb4nauyBolXngz7ofOIk
UEWUgUnpr323flg2YNXvRRJn0rKlv0cUEQ+J3B2iiIR9RBd30Wr9AedxROMJHes4su/IV/0PrDbH
43KB5SCnyIiYmGC18JlEu7WQOQFV5Zpx+NRmbc4TsKmfwEzq67Cmm/ONs2yq5cFwcO2OLDfZlksc
9DsDvayrk5okseZqns1zWL7v1jxe73byB4CCw8MYp5KPjMiXUqUtYILUCNi2SfRG7wkmOT4YfT1x
CfNYuPw6aVU1GkkVfJwc1EV4hpp0yqdkaMs+BqqPgeOi2iT8PItc5NS2nm8gZqluH5VhiOKjLykO
AvfQ2pRCtqo6baaXmCp7J8uVVpM4jOIkoUBgAIzqXq+IbfnHys0aQMSsKRXUjwFxMs1c8orLKLPe
rpKPi4RSH0Vv8ioRsp7k9sURW0ChdxVVnMGs0Q1ATiXXeDdjUwMcSwcd2pml74Krvihf2lV9J/ar
jzSrrY2ghu8eoWz4X4obYlVcHjSvIOPWd4h7o/uDLyu36cLxtSzny9pAf7JeDSQbRV3A1EIMXiGW
k/W2gCHk0Co4jniqhFQpN44VHeBuHRCeMRp5Sd1bqWQCKPGpe4tNYLOgxCD5cJC/R+xkSv/e6l+9
VV5zbWvjkTtV42dOr2r2OqOjFIL9YOOCZ1dqSyLhrTqz0XQ5OAYctG6Zi8ZvBQBYYTsVc3S3UZgh
U+Ss89hhmHng+gUyAnkrGr6v+sTdKi7ogVmkw5Stkc2bqDsR+fmn8fEpweC8MSNuoCv32HoLLPQx
ygIn7JzGjLF/18AWf4yxNPyubYzBIkkg7+92v5epDK6j/K5Bq6uQiCw73xLUdRm4OqbbwuZUUHQT
oShhrGa2zi59JKNrj4pX4hwuY9ZVO5RGEQ3R7AMQirmJOAjKnswh+KvM6g3XlkhOiafaD02DSJBe
xdsFCQWDjfSwaJkK2NZ3COpP5HlHeT4q2ORc7Y8h8ClWZMBxjtuo0QZeV05+CDghzKWSBAhdoqxp
z8V3V6eg70ikdnEtRYCQhc2b20xd3j1CmDMd5Jk0qI7wm1V1CkY5Fic+6cel3ELmtLfViKi8VdHh
3HATHjBmsn2xAnb3P6yv9u96ust6Y01j12OFsW5saVwpy+09uUmS/iKgPvkWCvZL02AErJPVwj+I
OHmj2WTlq5ESVRU94XvP235rUOvjrlOr+gJOn/Wc/9fpA3QiNnPhuX0aEp8X7byRE0h6XWFxD+ZU
EP1AJ66a5iDTPtGb27s0rQBucQbGTxeBtP+80KHq+x17IaAWpCWWauS99kATXyvVLaVP5T7ryt25
7Wh//gDWfyCk/rQxuvRr7hQibt0mUx7npNQLTElAQHI2EkSQUYnkJLCgEmJLHbYz6f9NjO1OsDTX
vTcmRlt8HNOJvnAJu3TmzJkrqA1kD5Qt0U4r5xPuSglDwaOfIPhmJ3Ot/liCX63ZdQJ9xRFvfPij
pXjWGEOa/Ow3MC4kQ93a0aKCeWaUTvesx/KUQ4q0JwLRKTaqeiyWLTFbPHo2H4lumu+ZCwMUv6tR
Mp3hSk0KFSLN7um97m+pyaIMNd2TGNNLu2J+qngWiduh/EErJ3U82sx1KxmuvvZHYyQdZ1q2aH3a
Ie5IL10TYcjKwc01tDfb08N77ZULm1SDynpjdbu3fbHLMEatbKpgKlBqwzc540kmYLFqb//0eOKn
B245EBRpJLR7uZaxudfgJkIEP7b6+cVG1KSiLQ5JNu1L0fAt9S/PFdXS1GToRKJV2FgDmKxgmKRz
6pR5K+pKcyglu8ek6vAj7IH5KzHrHrX93un/KIeJJLEWS8xUbsFpUELGcXMIbckCpB1ZJdvwjxBI
1q4tVnn8E56tjmV1K0z1D331yjUoK1AvDvIVwg/KaPNvAW1EYQFBHx+Kj7jgO/eBBhEZ/3Trnt7I
lxyJ4vOcoRa08DYGuNp28XFw9CasjpT6gN0xbRl/tdepQLF/X8UTxRgiEMCkJdrmiM6pfm+qtaxp
YQJDY23Ynf5Cm78rGkRrE9JKC7PP/8A7ukSYqz7wQUwB1yYXBHfbhDA2uCQnRQuIgvDB3gST5+58
MBYCJKMhkETHNJMTO5tSggCdIF8No5bYqMuYA+gucmHrMU65SnN6MSBmhjPjgd82qtcdg08g2pGA
jX+ycYCZ/sO7TULi3tKqdcBF9RazbXu6PMEqwVeO4DJNyGfJoqhzn9JfiAjDUSSFzk/jwTNtiApt
jpjBrtUgTJnLadZnFIPUEzrSQ+CHO6rXJf59IhmjLZtKX18WJxezlfB8a9qx1G5W1Vo8CVwtudJ/
sTC8feAO2Aodp9V5b2Amngc8T7sbdLNUriXOo/jEetLx1uADBht/vWC8XGAZf4dBMCeLNFoA+n7G
GSgEU99/lyyrzdE2WAjQCJCs9zWK9/x74kKeAlxSURz1TqSGAYp7jcl80X+CNGYBvRbas22RHH80
CEWbGwEWAHWLovhm1BRYKuQXCeUd5nDmjDWwdiC79rzAtQ9nm4NDunVpB1P1q0vurDr2EeBRQPyq
jqYvAO9aOMHJvy7vPyKCgA5+OEIKbXitrA2kjcJ4JjIa1VmhU3ozkx3ZXQwZVdRfLEye8EEJrMY9
4jW2SsV10CHwdHhpE99yyAVcAsYnXioapXz80z4WEXNnFPyKQxJcnd3qNKVqzlb6Apmb0TNaUrBn
CBDClQOOWQsSIcxyXYQMlKuFuXqyMu46ejmNNwyKkQLhqDYpw+CmPHNZkCMUp8mbtbBa3EwFf+AA
RXYnbsKQSx877JFXv25iSTacF45QkYFbNwvEy/oxWW9kwOJX+BgGGMzvByozciFBmrrwRr0rbGIX
b7hCLgbG7tGIwCb+iNB/jPQqCwr1mkAxr6ACypEJ7VFTeERiFzoB6D55fqLXKXEa2m8fKr/1eLRX
PFJBEwrMi4PYIkDbNk0Jmzovydk1XGSFbPtZe5mVdud1GD4++IBNvHrda19Dc0FwK33vjRylYi/h
dKhm6EL2sfY90dbGjFJ0iQv/1gTyP8BinAm5vEEvffnGQs+ZB8g3zYIyjSQXRfHm8Xh6eg44vEkP
UnCSiDliiSeXk38yRO62eIa4cZhSTQ/DdppQ3zoruTPnHZX8WR3EZjtld5icFrEXOVj25owMLClY
bvtBsoV4l4GeLrvqOKdFUe2SvcLYFONDAcFCZwz4sDqBdTJdZdMnHSGF15RfSLIAVsRG7Da2Jw99
RXF/Qy52Za5CgLcfK0M+ZJGlm67A2fwdO8IiF7zaoH0UiJ/aVsghPYRwV2fnjFp+1t6aISyWSbrQ
YKu3zwbqVBT+GlKeEkB/CbQaHmwXnixG5A7oJyWVA5MKHz2EYzn4/ORzLAL1P2ETcJAhuFuBqvlZ
NKl34jQ0AK4GhOe0PDBdwU53yr+tzEbeJlLeQmzDvqmIleZex6hZ9kLb47Fm8aRA7JOVa1Lb5WV3
jrOsej78qExlzpSJUdz8AgEE9FsEuLz7qAegkHgPTbwiSLWdu4uT+eoZucAUpi0w17/vhj+GiYzb
w3qRsA+MJ9MkEYbRCH0rR3+F1jpja0FDHH1Py/arHCcX+UTL2Y/Xq+OVv0otzIyTTB5+KrurBNJB
7MVY8JzBOSLjNqzmEsjjoRApJjv7VNnMIsXTKe3tv+6tpjAAJchjFwTTCLWH5kh+7d9cbz5QT3A1
NpQBQ7vxcYf+3IsLOSqiXKbg+2o5ZOyq6FBFoR/78lfTUXvcLouAaCNpIhvudAiQz/FtptG98Xfc
HBNZFYU+HjndyAETUTB8dkgsOaMj/t9uqEUokNnKaaIrunjGuiocfwOTSZgeCNJgNgYChNSTxhyk
iF6pF01DMwvuNTGzwUgRNuRVWxZCg8vKjeyy+UlkX5poSJGTzPzJhgH0n3QQgE57+LgM8AqhDOqK
VhdmLIXecYfVnUCGhWhzpS/WiRiz7g8I2mHfjmU28hMZ5LCMMsXjndpCFk2pv171UiFgamPSwk79
L5yR330tfp8DSAtguSfNnDgp4hcFWqiOryXJykDv7y0KLI6bJnYNOF06vATpqkrxnpYhRrhXQxv2
rfoiHupBFJGz6sgcTke95+KNhZSdHmDFoJFIvUR3D0vpY8MlmHG7WkM6HDORKY6I3fxwJt8ufk+0
DLgC1S+5vwvEDrPgtEOxSkocg9G2RiYA9aVmRFJCP7CAx/OqX8XVkUh8LktvaCt1ONM8ZalXvEMJ
9UweRfgukJuUgr3viuEiCOJwe7BMZ9p9I5L5lRCwuFLqH0HesoSuHwwqe6KqGiYqZZ9u5fuVTlEh
j4iXMGM+sCzzySbt/AlKJKhxzT5vJKEuKZyq4EBoYndL0NQto9sVkQpn/NYzTNz6WcDOOoJokp7V
Ujmxo3bM9OIh7AmqK5iYXDWjmRadqK4SMLIwg/UIEJsHyXb3lQ4B4x4CXp1//g/6yU8Tu4oUnt6d
G/G1eMk3zrnLjk3Vqevh53FvhuZQ3lquETsNfBaXNzDoeRyRx+ALkZvX9g8qNSwG4BkjxM4emzZO
gMpjFsMEJPA7+K5rhGd4q3DM3Oq8pIS9rdBFX/7wBThpj554ZgK1CD0XPgYg2y/W1SGWud0sOpYp
7K/wgBm4nTGahpZwtVxj+fgIjAFxqJD5ii5Zlznlp6XH9iNJSM6QwPPq2UNWdsCE7uyPw5mC3jLy
4M+1dClNGIFzgYz+ypEANAYZH6F5TENuUia0Myf4k9ipE2dg+P56DUkLkcQTUmCetYUFwSrLEDII
v76W+GjaA/QY6D9eVwdEnjkWM532B4QcMAEC5OqAXpZKsgmXf/97/bFTfyuosZDcOPVEmAyzQfHu
bNDFMmafbfTnoF0r1cxni3upLkypbsI2hwK6HAwvKHesHY4goGwBcR+l3HPI6DgpV+s6fZiN+RDq
tG47bdi8wBep0HLXGdTxeb1AHQO2I0co4RjrzLiOaJMJyj717yzwyHA6eXipb2oHlQCrZdINmpRE
Oqrr+NxNYWX+VeinABp9as/YnfR1z0HrweXen/F6p2bbiIOZ/k1Tqfw7arUDhWAoeabijv+dIKXL
X7ViLvnxir4W9eMnurEuezKJxuJeblQngakRcP/GEzqsDZgafSZ3bvH6t69Fk9F3M7q8CA8dzTnS
P1upJYjtV/CjdFqL6XEhtrDyf04KUyIJAUw/dQfOBeAPSPl5SXl6qbCXwYISDkDLGDjozRtcDCxc
YWDykw9r0mBymsOpuEwwwERYYhkYXl/hl0Rr/qlWq40hAg/EqCqxIJk5UzE/Oi/dmM89HHQf+5ii
ifdBznYhB6udAlSxKa4MmEi2tETgMufxKhJ4ps8d0OEs5etUoZoQkgdlhejC6r/E75zRrgj56Wxs
xrnrSNtErtXp+GETOor8SvttN7F0Na0vM4IcDIyBAAmn4Ubn0Hq99zhCsBFIq6Fh94DThoAe5q82
90Ei3l4r3grvPqPlBeK3LH1Ckx+pLNouTRZtbjObmaUIBfeOV8kDpVdu9HK+WcbNPoLy6gvqTcHS
w7L+EQN37Q4N/ghuXAmv4tfFsc6JJ/ubGy4i73tfZCFuNuCL5x1BnbkuNwNQM1c6+XQvtAeGDQOU
JK6hNM64TS9at2FHAMI1CHEkioXkax3TDllYfQx4YdD0pf/9Ym5MWE94/MgBMfFEnUVUzX1Z6fZS
NruGJOc+Z+jlGIR7Um5iQsondwnJrYZdOrGJLaSpSK5BVNRd66jVV3Oa9wTa4zO4TEi8o64SzWQH
p7Z/VCMX8wP8RhRiH70EIG32yD/pquz+QA4zzKWHlGY1zBOqHAl0xb0oLUm+cfnmHnqmHDTfRfwA
J1XNhctG6wDon+oEI1SSew83ALXKUHwD/lWgp9m7ndn3TJs9X+t/oEWnP+TeyOAMNKgoXn7LmaSa
Z66uVNo0z8o3yt/3v+J6XqQDI3Fzg7ZspaAzwOJPL3O02ClqVQmINqiJm/OPKRbe/V+Tb7QEta3r
zq6BRBQysULFNMipOXr+nVz0MZpHqEoDh5ddT9BgIwicywxykHsAXwjl/Yti99Tr8u68+g00Zr3U
1xSGAsptRxf5y/TsUhZNLQNSEAkLHX0GfilhfJvQl1vQVbXNuoc741AEb/rtErpFlgioGo0vvcwd
UVVb01l2W9YB1f367H1WUevJgTp4/Blwll7D/uKXn34Ooblj2mEQSo/7i0ewZ9PE1Yh2vuq0lMPI
PFo9/i6hdHJtwm4wOI6iN1dKRQdTA8njmKO5Vnni23Dl/W89a7Tknsw8/y0i/gEpC1u7QWClJcKd
A5NJ0K+2rAsTTyi9Ki7Ql75bt6uqhCrnDhivkBTp/qW9wYKv+7uT9AOlAoh3KJplRO3+KN82N/c7
GODrg+wHog0KLxFrNXWfN33qDpu+DbVB3AkrsZsKLSOcb9vLmTQDuIWNT/xU1t8PIyhW18Cj6Ap9
pLl7vCa3ECOABSP9rJIGKKD4ZBMjiFE1ljEUy4mS92RKf6AUysCOd+pzLbDgtHaih7maFjxT/6c8
uxyTuShiYNB1fjj4y+sJaX2pzU3NAELbMmk48lvhwgkigfpoOCGD/qu+RjjXbYYNge/Xib1paHZ5
lMe5fJ8WwJS3ued46QAwTQQMXwABGJigyBVtUR8sQ/Pg3/PxR0WIwcc4IRkAQjVnS6cxvB1A5yVy
y9NAc0WAU7Ux9qUgwzdDVyndhSUGTe+BsE+ivHhMzU1pLwLfkRFQQ3x70AtjY1+4cF0fIV8qxgRg
9ufzeejm9UdpC1WDodmt2TD8gidqnk9fWnhtjVOo1w64n4v0tocpRg/qvFqG1HjhQioVgS+s+rmj
qHHCCrEPpY5sOl5pW2LE8ViAaHt12tsFDFXLvO1P1IFlMn85pqwAr8SDz5qYDU5NLv+qcdn37WeO
rjqCwuMOEYrlul7LHF2c5oKBY9F6A2wuP+1YWjWS9Xegnz+U0XiJeoEu8MGThebOfNeLHUkPrNi8
akOGS2lnIRjrzU25Xvj7Kw6DzAvke5VL+EpVnyreAbZICKN/w5m1mKEaqCEfm+BK3To5xuAVBthu
uCV3Co/29e+fw+03hMbBYd6LPS2RqFOBFYLRkv2nxOieAhd+v0qJxhjnvNPunEWCwSED4sslp/NS
kBn2JD8LS1LrjT13LLMoreO9Zvz00tcIlK2ukLELWTpchLNZD/YCB/Py53IRAwS4s8R/AOPPtTZ4
fk2VIVPIScPBZxLX5B3qGJdavZqij9VbWgrQA1PLR9Xa0I3iZRoR31E9ktp6TAZmRf/lWjY04G3d
JXN05/IGo1r3KgpvsVQ7Iy/94Kqfz3Dw7gKmWR4SzGbyLAKMwvXFm3JTu7YDEMBnjTXN37JW/UYd
+eeo+DxbkaWKd/5CnlQ+v8DGPZws4Xc2hdgcObpBH4CbTijbntc4ZsVIY8t9/h0sT/0/lrfqrehI
Q0fLjVrTPna+S4UJJ+OFhu7dUUf65ztfKqJly4pTtRrBQI4hH1pAlLI8Sz4ktVl+90Dk/vVFnKO2
Poxf5vjhTMjHSsTqFNOzIiDnSPIgNNNzl08YHIS8f9vgHwmy1q6rIE1kG5AsrplNb/aserTvwrZG
DhFW8l0El+/kPDzJaO9vLwoPG+HJ/Mpd8FKEnaesn9sWBvcAn2Uzg6H0ecdgrd2hzVxio36SDobx
oxBOUq0rY3G2uYpYN4F1EPpBm+oZvVtmcRg0GlE35szEc+QZoBQ05SEvPVag2ToQ4aWxptJYmMrp
AtB24oBvDPHymLJZCfG7iKfT8NwvWgaS5UcE29603e0gf4Ai3zRp3k3UMllq7JBFmDGNVslf7XQ9
VkoUuT2TJ8U339m6ZChf8A+1KVWlZCOfqXlveUSDpjF9hekHcO65edOxlRZobkJQK4gddDfyDeWn
ZLwSNBxmW2KlrcAJnm5889oFWFvR/hRqdZsNFwSZyoIPbYAWpr5ZPhsxIYxyM8McVfoKOXaoIUpT
fG0KGhuP/IZ3zxfYW8kSgAzgvi6gp6ObDbl7tQOyEc8wT8jeKOF3fUODjmLtPTA4GqpyEjmj37an
Nv5D2T04U1Gdc8/skysgO6OneIU25Ist3vaD7tSwVZ+lpniligI6ovvbKKsI1ZklgSRf8apZstIn
3HkWdMHPk5qyCH99DKk6X0DuqPJ7uzGrPMPa/H2vSe7MqlVm//9pxrQZPjtHKRetuUQNLfO7e0DC
QdPiL/rFeaZL9in1hf4lEU0BnwIcQyED656PAdd3FcHD67y66cD2c5AM4YpmOGUHz0Cwz+HtCjgD
8ZsgNdGrM5E3xv+HFUhvfwKb3gc35qQ9ypP0+dJuvwmbkxYtwhPBEHjPR/iMCAMhDMvQdag89Mt3
uh60fjhIBG2HQOtpVrJE8htMn7SJE5GxLrp4Xx23CL9gwM3t/50wodh62LRznaV0ZLyLRVYn0MY3
imn0VYhUOG4mnQP07wOIYGwsSuif2BUH2QT9C+RrPmlyb3+dk43YaYb3b1RH76dspz8IOMVf0d+s
CsxVVtd/Rbkwh4OEP1Kxlpw0eCLdmUwA0pBwNuiLBNjptnswx1XzyboC8dMMZsJ/CtKXoMDvF2kO
n90jLljo2vKxtkA7iRWPtZ84QIeZqboXpBJX1GsIAeHRWxUGHt06MIkN/RIbTfNdF4nKZt97Jtqo
+TuVli4c1C9BT17tPOoSix0ZcfpryQVfiSv9wjJhKPtFDX7oKxPvqWgCyxvXPqZ+bg8LkJZuIGEi
nVVHusnbVyNSwDENZThz9TqwJP0XlCgdCnYOuhFJlJZW4Vq4fpI42LxDTjyCmWJOm/+2wolKXWlE
J1xbjG86p4R86mZcn9FF+bu7+bI55hf5V2/HAoB9PEAxnObQ0XSvs44YJQVE75pK/ga7ldDLjFt8
wJWIC37ppfX3/ozrvtDDQkgjoc3CD1ikaM6Y0Yv/0Ct/2BLuK9sPNuTuwFARP5QBuEJjnIZsqsT9
JpBdnKhlBeiwSwI2IHyui+sBStCNu+/giR2k/arLBrUpcisJcSS8X8q9xbiWpJpjY8Xcc69DDVEO
lX9+RxzkYEzQbdQrP7U5hwWEXHvudnECaAI2Miq7Zr1a6oQ+HTQo+cU10hk7lRSHKRCoZ41iumzV
uo7MjJeqk3FYgMJz+lj6ATblMzI1r34MO+/LTU/jDFjkNYnW9lZ7tZy4M57i8WvpYHjM/t9FDoNy
ZSWGiaGQgsFM8Prmyswpdk2Nc2FmaHe71SyhmM/a6v78GCNMfqV7V14VYTZlJN3UAC7H4Vy5gclE
CCvG89AVB8BxCRv/omzThftpnJZh6qFsfbyysnasB9vJFDXtEydAkkJZj6RYxoyAZHtG2sBT8HcJ
iAntsYlxEKWIoLS90G3CqEse2a3+pTi8d2m0uX+wpMjJLLb4fckdixYiyzhqqCE+M1NESye7CYnp
EGyyQ9bq0LsMv4wWJtH2OH7/AsVB1knRsIDOk34Gm5l5a9L5cKdptaEwMti9pQ97dwO2TFY8Afkc
dhm+KoBMXXiD0CCJJTENo58gM1PNsaGv4Vs44O8gLy5m+GxTxrgXt3X068ozuQqW7wUMoMwiKwpm
z2eMZ8L7kNpb03mJL2yJoRVFRYjFywpRP+ElsLKTVfsbTkYdHDe8H87vVL7i14OAlfi5/oyZUcIx
TyuElN+QKarUfmnamGIxkEULvaGQ3iiX3Oov/yIQ9CITYMrOlxXzFyzYaYC9+oXllyAAfUy69LMn
Tth/Owxa2lxq3Y8wVez9bMk+hP/h8ttOdKYgBd3LFvHMgg0Po4VF/saCByN9YHApp7znD1dHtdgA
L0r6CjRkuc8tZtoYXfn3p16iGy24lo6G4OI3XSuD/bxuiExpjOycmLQHqPmz7AWCbLxcUUQBR+In
/e+lJSviUdAw7GLGY7hWGl/uS65Ih2yJYKnvdRGRxAr1g5E59v1EVU+7gz5/bQ7DWty+fDXA22H+
GFZBGcpWjV+Si5mTPmrQvWIgNrrmLDHNiIaOEd2uQbW4XBC5e1cVb+CbvW12L1DGXgJhFODNhJ4e
6/VmHau5+IlkDLT+xe9OZNuj9i/hrNq6nJVCpH/+O4fA94U+i6M35HBShvgrATULSEA/D+0WGsjb
wZXgPHeifQ9PvGd7uKCW0zebS0zEmpmeiRQCnl5VRphpk19BpHERtZc50y8dJ+0TOv2R/JLRhyiy
h270KoTC18aUT54bBbYX3k1ECBuoCZM2qOFD2IducNI3lFPJf0dUSUPfTAItattvh79kkPHj6E5V
zNQiN3us+CBLezMijrY3QdIN2vsq9wxJg30Id9K4dU4578WSD7yddep/Idv2gIDAH0XWmC1sYaKw
RqYTL1cFy+yLu9WrMQ98YHHdSwJo6kE2Ly/9OT0ird8KLxKyAak53DA8Ms9YnOp+wp1R+oB0FMvv
cOWJRy8aklVKM6VDybyTkU8KSAMswyWBz0VOirGDCuKITFzEZoP6Yq+gNkTppOYRSb9QOjclYFXM
efVU/cGZiRjJVrJuxjWOhWU74zL0Qra4shTp/CzYu1EVFEDwr26FHPEauY3RtM1fxvpMdoSLD4uZ
knY32M4YBmm5v+12IU/s+IKcwPu7FqoCFsu4a5yKW7k+Im7fYC48EFJFQ30BIALBt4PX85yG/DcT
D0dhNRmo/Gfx2g2O57F/Bz6uXqOVx9TifkhW95tubmocTpUsYWdeFE5v9su6weDNcHTpFu+54bk1
4Bh80hrpMFP0Sj7Npq1lF5PrAvyZyeeF4SNL1MeYGuNlVNGdoPdvSCZ3UPMvFiZcrXe3VeKy0jp1
v36wLSXA3l/d9iomJx9EvZOUzvrsl1xpg4vBrDS3lWQsyLXO58UFBm7AH134htAuv5viGdVkeSvP
HpFfDRzCF6o2ye47JUzBP9XTcVOA/kpB2zkKepbCOKmnAp3As8+KdoAA+4wCcGhf1WP6QaMEdcfx
UBoZZWSguVMCBTRYIKifonmYirg0e62SDL0uHCgvQvfCSbgZ2bm/txEWrMEvbALFpcV4nSJtsq1m
w1blK+PY8f3SFtOKecNljLud35cKTcL1UtDDBZq64nf7/HZGpetFPIR3nnOHyEw9y5T/r5eblcVr
sMfHD8nVa9gS1/Tyo8/BuszQ7xOPXSL465ANLIUMbe1s3A0rOZvpwIzAvo/iQ84xwHlHyyM73C2D
uTzMaxfIoesYdycJgV8hfq9g73+Mce881VfdQxQa0VM6qdnkaXsE9M5W+QS0Vc7OPv2mNQNxV+HV
EE4YBElNIsPPOLl9UmDhrnDDyFLphi9rahVKT+flQggQCRZ9pfq+Q40ScNMillag7LGrwd6YiC9b
tlb74kvKGm/7Ry3fsrHtlJPBlbKz8OipNVmr03i9Svq/JgpHwvE2vxW9SwDk/k31bqL2TfHLLI/A
uOlcU+Mj7HGc9Kmu3ud5wmNnMMtQjKdr+NTAwJTNYv2Fpuh/yZfipx4NKZ6yGyyXUZx+UUBXlRe9
9gX9b9zh+8uRcm0Rvu43jDmWxiGWlkmvbBDUh5tJFF/1zhiIkVKGCeuzYmVrhrLybhBBI5Aim8TE
Pd01EIW+TRhcbXgA8Rnrz1QCoHtlTJqj6IPsx80jy3fIDWMRZjq41NJjUwSQxQbrYM6/EB+DeTWE
WSF4s2IiQWMNEQ643PBOi4ZVcPple4ojnYkZf2EwykzpRcoziSARhUETirhy/OYFnJEFYVerm+ne
3wFyzHlhVlZud/so3aRcDHn6LDBg7uul+cbUp9Ol4wHhChImU5NMg1fNp7lT9dSOgoKdNq8ZYgk3
lX8fY7faItKD9YtQrENhoujkGBL+S+IH6dzAuCuqaRB/ioMmM0wenYB8qTCPOmRPGrx48coSva7w
TMfs+2/tkxqzS80nXYxg2X1rKwbYIcG97NYlYpFc7+D2H9A+YIPNJcSH4457q91namf54Za2lQc5
/D9XqEoukOqxAWdImu+jE/S+P16x6FTZswwPlXoWm6ulixcUm/AZ/fKMvt9LN7Bc+/g7BBq9dw0d
yHcbTTt5pxipJ2Ap61PPpMVSmSvoVrNO+fqsgTRIIC7iL4WiyCAFEkWBQJktz81OwSpaEgnHd66X
ES4dzMT18sYYRZqpmgR9yTzwQ/NYVM9vnHuj3F8SsoGdtVOILEYZX/k/taBH6AoFdyj7ndHQj7Xy
5fqAgGrx4ufuhZBExJAFj7L/H0XpfxQd5v5YvOoCVWyhlJy/SC5ypW9VEPlQq+z4ciLETbtahjja
+GZUFBmxB4dlcnhtoIyiXywSyYz/RUqIl4wcNgb5cDgdgUf+/K2h8IkMSYmveAMyaoqwOeck/XGF
0zfMm1tbwWRuRqLxHYebZusGJV2Ix+4cWo4t7GxuIm7jfmwUbh2zqJzOrNv6QwgbKwBTAc5kMowy
hQ64V+v//P8zpkiSKLCYdwT8ACpJ2pBqiNhBIRmivj1IkWHnyFIq+oShXPUq8QYVKLnXGjzRA2IU
DHq8jIOIb1hNL7iyexUlrTqBH3i38b/0Lr0uXVmZ4V/7sSTizCif8GQvRrVbDP4PqEuQjiJmE1z0
cqWdV4UCVDFIiEXqsvaqgTKRf/o8rfTtLmvB/rftgBXqndPcszZhSP/cWzU5c+/Uo8JBa491TthK
YK0bULTYePeFFSPxmbsM0PjYdfhip2DcuhQ93l9rKf7Z/RRFwoM6O/XKKwPTvtevs40oSw9em4Jz
btQx8N9L1W/bIiyVRv+xASEWjjs/xn+0XsjKZYc=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
WCjKBNXic0KXiU6pjAWXiq2LTkKJ7NE3g8L6OgRpnuv5wFja/4QAqU+5Vd1hH0Xxsc4vA0Nwy1zc
t7+LfMBHzQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
H5f3TRBy4525jkh1qIK2Qsh4q/GrtwJ6JVADtzts1qrfqD1bWIkorepAhRIvwZZByI2fH72x5SON
7IfG8zLpYUlD0Jk3QCBoYlUZJGWU6RDyaY2Rn7Gz5P5HI4qvPNtW766wSe1harlrLePNjoSKVhfF
4H7y4hlOm6KeJFp1y30=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
o8NUJuTvvtHQ//0yHzk4r3ROKImbnyCQ/+GiYKbHz9Jqc59WPVQMPJDi7618B5h2z5gPFkZLVKrt
oYIDayRN1eDG1k1+njjd5YRIb7DTMBqPHvFVEOao9N/cefP23vkwo+I5wXkEITLqVM0RI3al8o8t
AaA6Q0U98Bzdo+Tx+RKbiBIBi5x6wlOZOehaj7m9+DFw+updOQeJ5GNy8AZn7ul0lsua2cRf0k4L
gE8HziSaUr+ewcL1uRh7afU0No6kaXygNHGf/nl86AGwUs65q2nQnVCcL6IPPyXmKD4Bn/J0YFQN
o3G/KJKIPhXq/LL9z7Hr7LE3J/cIaba4C+44/w==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
r/Xe2Ci6RnICLxvZgN4C/9rfMRo5L4MeaOlVrWhtom9UNPVoQwQaTPdI6GiUuDDQ3ElZSB7f6p92
n6ZoBVSL1eywG+ntCU6ZxZ1/8N1sV9CjSBxGOexweAx2kmsTC0q7hVe7rZnh/KLLizk+Ny6alv8B
v1zuaJAVY3QDTrVCM18=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
BA7JOat/rOFWMLmTHh8DUAZtAhABvlT31S3WaH9xRoHVRI5E6pFuZ9+Ecgih4mhDcxdjqSGbeR/u
24jHGR1zNpOF5SfM2XuvRrQQu9K7wIyXwPdbsyw0LvXT1RLA9UeiqNrt0F8qGcaPOkn4zXH8hSn9
09AecPGhGA7p6v1GpR/up+MJJxlXdQp3HrAGMLNTw6FmURWGfU6ot/fE9/XTH828aIEuXPQv4VF8
6pJ5XDXcni32tirZKs20tbT3Ib0XzlMIzD6X0wniGigh4dlmtyYpx3VFbwNcoV0FuVHZukOeq/07
9NqJrMCoOA/h5LgKZYIh1HETLValj8txpIQaFA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 72704)
`protect data_block
HvIwe2N34SZuMjy4um7DVGxuUtmbgThSrTNwoGwEiJdlisMhSbzJPsSLzQyCVPvBWB6KRKKsL4Rb
Vu3IRL7SYFIFYCA0Qq7GVWGEpvlLVdFovlxeEyEPw7vWI0vUv5p8t7ZuGAgwgUgLWZwGpb4Wj8Wh
NY0Ig3CnlqX1XIrtDI32CboRq6okmEybBULmi2P9k61yb7SBFyAc1svnv57UYSBqImh0j1AzkSL3
wa7THm0mcJ/gVH1/KUyrhO1il+aaW6NHEGqWVwo74qZ5/fcj+YIKKJDeGiqH2YcLSG5NjtOCUbnw
Qi+LxTROphc9BKH5UAmjqDhnJgjwGvr4bQeqYaQb4SjNwDzCodQMfFlmK0ro8aTvXCg9F65L6/fq
7DuZcatrpTd3yP/baXqApZ5wPBBkqViF04/WKfDRQMsbOlqNTWJncXWrzKoiXG4UCp3CPDPI1ADA
J4IoqjvRDyOwSbaOvd/DRgou6ZW3wRtzUd3XoyUc3ams6B2Os0tjPMhgSshCr76+8KfYp9hkLacy
Sux+oKs9jY9iRaHGLFTha5pUjG9spPLty8CV1wmij25vxNiEVXbEH22Zb7UWOtcj9DyaSa1hjrIE
x7q7kKY7XnPYCLZ23ZasHnZUjRcT62+6/6DN7KmHAlEaspJwIZt+DWh8A7U1vMtZHaMtbFE2O3Y7
iQjIjy6W6P22+JSJsLUBOdzAyiY8cghioSF+0RXrqzoHtPct4n98w0sEdA9Znpf9t5pA/uSvDBL2
iOyRM89wsiLc7lsX0sihfOSjqqxPSZopH+A9h9ue2/G31af2bLetZX6UsIMrqKKz3DsUWS5jxLx2
uO4K2xiZYATkiQj0HpfZu/5QV3d2HdSUaKtqpNfRz0Lw+5VcfWZFoyYfZ0TDA85K3FoSjhCOkt5X
qnxEdhrhvJwcdP4HRT3bFDNzaQT2Bq+0qvhCP+3ZOskwvkpFPCRCYfPKKjMYd5EsWA1ipnf37Blu
P+B6FwUT4zhffqISQupWw3TQLYLkxjkHEhNe+WkTmmsJZUnWdxVsov0XpzAcnl/DTDNtJ2+ovFuW
vS5MsdjEPyPduB00/YvmzhVscA84PYzTTOYmcWkmjYSzuwP+lws5WScc40P/b1OmM6iAtf4c0rZp
VvXlFVn0n3uvmJnaGn2RIeSQIa9WTqypLxpT+BZH6En9xteyR8rIYV1pxEc0ciBiL/jAV9n5T0k5
fvUkVJZTXX+rWbtUg9+l4nYvDOHz9+T6m88MPMqocLY9yLV+dFzczAowkeQ5QYwNFIzing+a+xZv
Pxkz++cUzgMzeTl06W6wTt2ZiUgg41n/2tzqrylGQeM9VqUiEG7wCrsr9xS5nQjWvd50z1JDlsbc
XZ4wTJNrOMBD0zmEaRn0Nrb5kYjGMUBglMp7HduoiDKKRZH+kTiXGYn5btDeDwJkymeDqU52kxMM
Ua5JylcFhWPU0/QZSOzOFQ618mpAVniy7VKgh8HzuiJ1eX9hUbnNDBqI5+sFcn606kPJ3RQume2H
+YAsr15Lx5QHTXxdHTywTQc96QLzVEd+ZCoDfLy4Ita230vNXTC2z7eECslwEaytH4C21b1sLtfr
5XqqtMYgorrrvtQqTi+7Gy5tqz/yOiJ8WuC3n6rCzNi5HVLxx2lBcmoj3ck11xEwHK50HJHCLs8n
JWjh7ZyFXcnG+XxjfbJv66Q7WQUu1ZmqFkRdo1tv2iY605wT4E/Ffc4gBG5uBhjLdth8vbgwz6ZA
RRtecix3HrcRtApeT9szKzg4hejQoo6LEak3BaEMuJWHW1+RpPJdNC1m3R31OxYyz8uOz6XTCT0X
37wFk8mqDzVYvkZRZMXxSSMgW+/tTBr9J8Ydd+N8d4SJIlaUT6Z4dEKdOx88H5kAlF30H8nMnggP
SDLxrazQ2jQmdjhLK/KZ4JKgWPpaiKEvwxmejO+E1te8EtF1r6TQWyBYuNPbEGkNULWhO4R7Cida
ludH6DOYw7JB1g7LfnsGd2QuUSkIq4hSkPehzDldUnXi3vT7fG95Y24Rs1Sd0MHAm2/25gr952+p
OEN0jULZPrgA6Wy6VgpHXNYAtOIJhXgWrp2Nf57JhizlPfOy1Pcro1lFHNWmcap/4qKYMju/R7K6
GlUTWoUzIjK19xBpBj057nLzgeOTsPvmAxpJnpGyFe2QZgFs1CiqD/9SPLFhgFpFvIujjVokVuQv
Y0SW30jzxOyRztwpB3VmYHYbIWtp7IDQkHEgypOUnIvYckMEO/2gfXT85ap+CcP2xaaMSS8qRK6i
KDBOyMwHUFSKKUvAG6UKRulCPv36152OGtsh1p+qEPYuHuYz2YHhQjAbJwovXPxLIU3qSHtBp8Q3
yc2GWHdqA3P12KMBh2LyuB6FLahJbJu2cTsHXvtXfHXiWrr17pWTXZdqbJPgbxv2jRsGZVxV9TyY
7lRyR8Y3BiPwHIYd+hXW2gqNAbPAXEHzEW/FLTfzU0IEh+8un0KCVxWV+PyVOjiySHksLyZvAgtH
XSphfYqOoGZedfxOcsK8itSk1ADQRdw/hHld7+km0JITcpn6XxxASzJAe4H2mMiuXzmv0AqopF8Q
dn2hMIc1vM+o30ll48q4nzjgzZeDYHU6ZVNTqfMAzTR3cKuj2Fl/TsX+MKLc5v1LF2njBu9aaEZy
X38BjLVxv2YO1/oTbEE2W99LCX/hW/VvpGmSx3TSAWbClged3p6hKVqvXJrGE6hSeAbmJkEBf5UV
9xLSafDYk7Dwr/oug1ymI4P2KbJKuAyPMOY94jd3Zbb08xCkTgPnKXNMGjsuU14Scf6ZQQldfv/X
Vd5uymnNA/wBuAfE0+w51MJz39YGeyyQqzp+ABKGtvX1gcyGH8g37lskc0GVG2Kuko4x+IDCgmOo
tdiIPZWz2nQhwO/4vZeZ2/h2k8G21seDc3LmaeBgdDtzN4AczOgKoqoZlxiqh9XbRUQbyyUVhGEF
NRRAJbRIDhE/b2bdPrvlDrU13gXfceRigKLhSBqwrzdvhVu1t5VHThFl0xUMVG6DXaShN6LFBfkd
qMELJr5yk73mHmfi48ipz6ZDKL948hxDZ5mRLxceIYnC4G6Zvi4LpBtIFUnvtTU5XR6KbYTZNK8D
pRDt1tgs/oyKpT3j+oJOb6s4chzqzeyH6GA3/tNu0pptqc3PDRfETxx4+wq1DuudmWuvmAZ0aPdB
NCAsKw/QOJZEsMuJ6HXwdee1iMOKoPzsdIeFEmNt7XhRkOfamcXv49MHg10jX/lQ67Kfni2xnQbr
4reqFp+uoHm3eA1qOVCwJqjNDHp1WaWtSiHKH/hXz8hzyxxgUDc8MWMD37Wdb3tjHa1nggaLwGLi
rSN2SmS4RLT1AdAGlDAmxM+N7fJMoeD9aSFhQn6SY5v57Om61C8nId5zRNy9nVQxwJehQRaWF8Aq
fQGUd25hYUrTkKGV38LTKfhJeJL9dsCGZNA2VRoL7OWx1ZWNkLrEEAFjBa7TV8dwE0x+1fzcErpH
xQ16Lsmia4F9S7CxGcAz2HfcKzcNN6gt0ah8bg8asyRNgbd8MgnANmIPxgkh6lyX/KrjBP78nBiK
BoQw6t0yb7V0UGt2AfFBXTggPoW4cj3iiaaBlCgQT/IgrUopBb9Dok3+aWBDZwCDQ1Q5iqjyJ9pD
KY21xP6p2sAIGQ5xZV1L8lMQoMSJUXS/K5kXJ5BvQ6Jk7CqNXhuxV/wAflZu2vkP1asiBCBF5Ye7
s0byJmevvnQTPWCBHdrGJ6pmcurXwFdBd0BUm9krKJX0e+ggOIDrS4m28IyFCL8k9qBJZ9dyclDw
6GivtqpQ4tAMlDUr9VIEb2zUoLC4hS79W/d4Cgf9SwFGS2vcOZBsheQvadMRMpZFQQMJ9wxCXEFU
H6rhaxKzg8E6iQkFYAtxSIxcu2lyfYMFk0F4c6+4vhd0c3Z6oLW4PTn5hLYEsNOeYUzWPawLVGhN
YKDfkI/sgWtWAUFNCWwBb/kbnv0VClgQkaLJ1R0tbEMZJjoLVFfe0kjclNs5uNhbM8wDvcSbMiEq
TMCnnQb8UtEc8uriFBmwvOEezo7AL6JbxMFZ0N1oKnDkST57UCGqMOCfQ/isGpo3zjTk7uDGuITV
d+GVfw/T+U0Dcy3yqdTiyg7NT2fWEHiv3Wj1KnKKsxTRTbpDGYCxP5wHzQI03sVIB398CoeG891T
hI0s6e3pDFks7YgWvv9M0a6d9So7MsQddPE1IwjB0jVYbmNLUkU5d0BQ5JKdQiR0SL0vMH4mvwty
KXQvW01pzD/nVo1TWzvs2EfoAMcU7hoIAQhSpXFED8NKcuPLR7GZ9NSqFlKOA+Hj5Au9F7uXrS3v
XbNXiGOSbQknrXKJs6jmU6iDxESydyyhvcN5SgmrdMmZx2/Mv3PFYJhH1PAvsdw7X+gHkzhugVDe
f4vgZ254r7LVyo2qUwGAGQgynV5GBWYbRWRrYn9i8bMhMeo5s5FtiNvKpebRQRB1jccpKDqmhdYv
HtT4onhN20B6ChVUOuSYbDCC4ydVkiI0xNIOkhL3NWhXVvuJBIn4o8ELOsiLTRbCRhb0PU/07MDw
+9BpGfTrKHBeXstbnQVzjCc4CttauKv59t1KcPKmkDN8sA7EVDXh454BiEJp8VWbHqonp7dqboBs
mqr50B2lpcfUzwbCmEVTdBiOyPCVKuNkVFfcMYIXGvqt09c+7UHm0yYdwF2nlS8W+3j5VtpBp7TJ
Zb0xii99XhH7QE2CpCSj1x4he0uNUIP6enQ4xpqAlUTm8dy00jBDayQIi5em4F0nc2qcFwUkVlkO
z27S/a/MgSzOFp/fio5suNN0UOJVyGfEKBlwEFkzYFwcwgarr9niXRezbvG9E0cNGHSGMBy3t1bi
yJRFlyuB03wUPi2NY6zPHn5oqFhBkA6y4jpeVjQuJW9CaJrYByef4li0tZDyRjaI2ySPOmtgcSt1
Bv3rSwR27hQ6+3cwYRmq25ZUKrY3tpWjoUYxb94H8LuMKja1O1r0MpaNJ6kUBKP3LGgr1YHHb7IO
irtEqdKhpGd/Wl4Cr5U6jZlxN6N7WDvkP6/n4VKyEAZa2RwNRP9DxlrPEQDvcc6nZ0/lXMJpBuke
XbRfW14uzqZp4ol3Ktw9QDZqTTXmtdhroocX3oCm0E/9BIBYx+V6XKjMmeP9SVvBNFMC9prncNqi
DpOVWEpTCZvVCyLiRJ0qx3Vyk5E6jc/hBPOZKfbeyY/FIgTj/4QKptvZH2Ptz6nfMcfZdh2Ucyq3
We53hmCbGSYVLvUzFD2fEiVlpV9tSFm+lBicoyXggAbTbNnWyMxdI84UpShrNB8nYi/EfKSHy6sk
QVc0iPgqy+lwyoAjFcgNfPmJViVNFhgAnhZhDY1iQuziensvnjPIO1AGRHoZPOvtpwubJeUM5jMV
6OeN9LgeJ8RFRpXnkQv1HJlkVuo4wVPuvEaph7eZYesqM3s1CX724Pmyq9MykE4zMN1ow1YUmIJk
lrC6txSyBg7OW0n7QzRlAKfimFh0SbgZCXYMG2uvsupyf6zamMXHM7O6y3zkB1ORd7pIdCll/3Lf
Oi9YeQlNJ2o4oiljEPInuwhktLGjLpH4fJ+uWo4fvfue3hCWesgTFk2NmwT6zGeHnbSSu3kGaVrG
OX8BLyeoG0CMskQCw9YbJRBOHtI/b7dag5JRUxqN4R/bfHDkpfu4E/Ik+x/aF5mGffsZmE6pVK/4
k3M3jIlnIVHLXXQyicE8UFo2c9VJoIgR1Y30U8vRzK2d0EKAHCKyut5hKp5KytPVaa9QaIvEUDxJ
8ydYsQxl7Y2AScybaztNKlyOOB94W1IXpVkFsSEOE5P2ICh2LoDF6qk6nYsOwgQi/QrodM8aA8Y6
o3EuacF+HCN0A45oiukQN61HXwJ0qxHKVJQjYs3HZSiEBh1rAcHyp8ylj3xUyEdbKmowB+r52M2U
2a0CgPGtlwyqFE9qku6kQ/JC18nhW7CZvNyUmbKQe6J4VIF1G6mjVeP64ItH217LsQu+XeQyZ2Jx
glXpXmZKcDu0CCS92Jd+3cmx7En+WV6A8x7OJP4KoGrYnKW2YGwZTVJoKoqT3RYp7t39QHBcbjDd
96iTZJ5SJfrVbvbIA2NMmXcYyL1jmYnx9oAr1iGKr4/zQ+aCH/Sowet1D9lBI6cg+RGcSlcy+LM0
1AiVzhvLbt7KOtAYZhux7dAad/2+lw3IBzG92c4FKnF0aMp+iQIn77K4NPUwSjR2HfP7tPmjKST+
d9BTe9YiGJjgOe/5N/eZV6voCC1DNPR7yUyME7QuhfXMF+VkFfwQnZLF1g2nZeREbCjdJaSCvmt+
erBvrerL0U/GiGDtZpBWzBlbKL6kA6hyfxppJ70cPoccfYQnYs8QTyFzaYZstGZGNGcomQIUQ/Ba
tA/fBEC8472TOD2bzIw2/VMiA4YHnYQYMqLTkdi5Kuxn6iyiUDYJamg67gmyOSfVwFTF3iuc5L8u
SGK0n/FoDZYtFE0Ip6owY4tt0OqoJhDWIzlgKUhHoYsuO0rhRuAwgZHmwCjyH85PVkUoALJqTWlK
mHc18K99zEuFST9hhrgUZUdHxULXvy5pTNoTvfFZ2IYvmiX+rk7n3noVKgVLDcnzCnjKLN/ShqyG
D5GR4mrCP/rxxl9Uu7dspgTrEkl5FfO423Y3f+9iiFYekUT1rEmvGMXanhKsgCQnGo5yAE+s6SmA
sSvFytmH1lNuUDwF+8L3sw83nU6sf3fISSEW32sXlE4zdgXje6kEHoKVShgy663x7S0R6M0b5CDJ
ecveH5A7XW8YBaOtZuAD5KA7n+ejiYi3kqrLBHWEVBKVty02KyZ24RxC/UkBE2q7OpRQI31iCSFq
Ht9ifWl32SSmycQBc/pyAORd81oyYEj22zvvwYS76CICzX+B0ONl0PAAZEH/ffwb5IkHX8bFW9eC
tfwXvZyyrpma9/vGrfoc74YNALRYKZETKW67G4mtfyAdPThR5xf8EKq0/xtDQvDbXMb97npFyq3T
bOpCoRtMgfvz93JiQfC0LMpzpCj/w8RpP0u7jaFjgIIy8NiN7F68kP0HtA17COI5+9C7AU4iw0H/
ELfzjUg4DViEtMlvnL/D6fFpjtMbjZnwQ82QKaWy8FrWA/Je+elbdepn29k3pJe9aKgxAVd3+wZE
kyV8qkCaYFb6GCr56bkD3N4aI4GZ0MCB1Dgvjyt63otTqctSd2uEsu6IW7EwM6SoqB0Ni6vbMcSk
8Ngxtg5HPXK3f0EHJZNxdOOEG9+J38vjXqWhCyUGmqhCQz5+uKS2IUKF3YIhyS1qn95RuvBm7PYT
ehuDzzH14/+pKSdQ0gHAH6cUikCGtKWGUFuj6See6jywBv2C4Q31apQKA7/rvC97BIi2paggmgd7
iNpgYLDTty91dv2FkMv/DP5uDjTykeqSMj0FrOqsMuvSPAXoFHKBecKsDyxK+ZCNzdOhD1Q5srEm
DOWCRK5w7tzT1RB9VXiim0/DqFl0P4Fs+lJYanN1Qd6fpObL9IQR11fGp5C6IutXVRBGGn4HNbTO
5P6NpCoByNHxfZ2ppans4Nz6KsOmdfPCQdp6UVK40Eu7gtEmn1pcVqkimAlZ/T+bcQQBIkWCdMgR
sEFrQM/uAVNbVGiSTqnzDTopXsOzZ680K7mdfR0YwLKNt9x3xVEM9vhzJmzln3mUDl58ldZfLgFv
WILmz+qw5pB/sQFy0jkQyPaQjobPOnkiVbgQkvQUD6mkJXKFsGQJ24GsJUTaYrEb4EyALETP4o5A
f3ytrUFDHlYfuRxz9yNU8QdYs6e2+87rKAUAFg146b3hL3afUat5ZbU6wa1XwP/970AyWZTf1gRS
Ct7bvTvckA42112OtIQfq7Gt+DoihOFVMWb4wyVC5DKXK+QBBnQDVUE4q0iJHl7k122Vsrjs9+id
rCUfrRY154uJf2SuBplIL4X5vECnLUREMpuqnLZ00pJT98IyCPMvJtQtus+gshp80MgdoTVxb5Sw
Rlo/C69GBnz7iRyk3wdybLCONx8PZvUjiG3DLLtfXULPKRUsCmk+ppgQjtvKtPsBUyugdUnekR0Y
gozZEiNS5mRvpDAb+AVMfLPsI00mZzf/eUDD9RFgJnnqQEesuebHJYduD0x7m24nNVoxfZpLQ9kr
Ph0WL7tuP7gWeIhMYv0sccG+XrShoZ/r5M5CJ40CmLbedxT953SGqnS0dZrtXaaeYGO/464k9waz
KGi87zDnxoRwA3E2JXVMIhnTdEBIcqSA9kmWPnuNeL/NvDouPBDqKNtb6W9I3NbuJMqHZ+EMGAQ+
T0hfH957EsVE1dxOTvsOLqnWLkNF79aAuLtUPKrdTM34STEBLjhPfkM0CxTJVRgXfI+riH4jDJPp
J0yTF9+CZ4DJ2Pj0SlbcGsTLalg3X06sRYBK8G/7aB3G9+8N7XQkiRndDvNLr8ayF9NqpCeIigjL
u+syGsEHU9GCHsLjqLfT0ZTxJHDT9XXqCgV0xX3E0oJY1IMojlgqCdOS+cWwzMzGII3zlQwfvS7n
KxbW0I4kfhcvqEQofZkb4yHBTQx6nY3QkzxPDW+dFmmW3VrMJofveXe0uQ0QE/PWyNNj/Zcud5LR
SiyQNC8gilQU5RRTxUNcZN4SVzFVa5go4lhFVMXoTHaCwezMz7EzxH5vrh1nMAbaam86h5lqliGP
19k39GTRg/iVKmEtjOeQ01La13ZQLdp8Oy4SxZd872VJowdVjKOIQzyXy5di2jkiGoTsVPMTGRnW
BSqpgWti/mhC/kTrmTwrGRDB9oBvNbfwr3HSqcRG9CO9R4Px7V0akzBF077ge2jhGKYwLETTxqXN
fzLjFvQd214Vv9FuuKjwHp01UpDRuR7gVgKutBPzj82kVbNv866v1YJACYdkqxZTp2dwBFgxhHZh
sQHRC5QiEp/SiXZEILSROy048rh906Tfm9QYFSNRKDNkid1VCGimBOPjgS++vLmkv3h7eRZtFX2M
iwi5Or4A7nCz4TjMngtQPh3Ll8l2EX9uudfpQVF8nkaGzZmPZ+LoPAolpIXtiqHvB+hrHTRJ57Ic
DruA3qYMPH3eSAG7Xr/9wLgS9Wz5FwvGu2kxV5BT8vd3fsZ94PYTLcfRNNfymMlp9zrfQkOD13wo
/E6PoM4fM2NhQ+7ztx1YAb9bJ+NDPPnC2u9ntBC5XZZ83Xc/Pyr9pVShrd7F8AmF6vIygKTGO1HH
3hM3By/7S3fEcq4BtOkGKF73R1k1L1eilN8iqVlseaxmRNF/WRxLWcM424/+PHSQfTpdRDfaDfoN
/nvCg3kmY89muYRJle1YRH+t0seGJubaC3jUJym8Z56xhIWwwxosav0TnScVgUU/RZKMcVcNkmU7
a8WbtR6bGlLcyIESGODlb5734KNejF8BbFj+qNipIW2E/+W9al04m6WaYhXxhpGMkbEnpZC8SrBi
dpBEKLXrio0WEkwvQdgLQaDJbD0ZEbeKNZJeAqGS53N7SiKImKqlj+wMq3Bgc0HbeF5Y7oN7IvUO
ArNFhnHwg5gf1Hnkqn4UN7oLeoClUSTkZ1tSibhQVzZThO+BxR/wEb7qNLCDWv/MhnbHxNEghtS7
HN7qa38eHjYl1H45RafwBRAIOyuB00ipyboFzSPVxtLXJRt/kTIa9jYw/HeNrndMhsuSgpdWHHRS
kcTOg0Z1727nyFFwO9F/hxpDcPrKK9ehU+1aXft1dUD+GHa9d2UOTJkqBLfqHOTDUuhqYuzvfCsY
A7Xo8S7bw3Y5IpnnjYrEf0MabgEQryAjfXe9NJfAjVGkBsBqU5S4xFP9tcw+hBNRZZIua8A3Yvxq
RzHfXTOotj3FuW4oKgyveA9kR1uWHYBaYBZvnAWFvkt8LjA8/oT5WxwwPE01gORgzy3nzDyO7C/3
LV5TY4zVOdbqTYJX1SvHFzNgTWpMc4jvJ1L8juiGRQRUWMxlMM6SbL7SXNW4XsuKmYR6cwlzqUiq
ARd7WUqE14jqt1JqGtmsskzS74P7Li89ss1fAUONlhSCTmgy8MIMiJDuISWKh4gx8AL0FVNZMihN
NU89dk1FgXtOSsmNPS+hpc+oMr/RLYVSZ/xLGVMgjFZLDP+/2L+G/212xJI+n+F79rBhGTlWEI/I
3AShC+Y2bmmwc8QNP63HDQyKyeYSFs+z4lBEH8rccVkFTsG61aGUwi6WZmqZHB4nnRrwwDljk/mb
35Z+9QnYMLbV7sTNxR5XHqKE7CWK2FyQOZNvNkJhXNg456ciDZaSn9h82WwEtJFiPZIvT7YIPM58
ohCPE+rjrMvykD9HxwoGfhOec1sKblJnb6RrNM9SCcJVs9rsGm0X+WYTA1wuThLsxbu4Zhdr2tBN
EaFbaC+z7JEjBjYTye2/DsW2MdT956+xLMQulLXcT/kXJt9UVgWsElxkHQ4Ws4xdmgDwx8MzVP6z
yncHGkHsAVqCTsCSbxU/9M1jsZAKFTgs0cDsT8ST2q/Axu+e56SR1KrkFW4bCXSg0rQFTQwLaXdw
h9/lmMkolwBFKVT/8tz6S5EOKca1ihMBTXjbnoezPGzs7xA07IJ0hh3GX4hm9hF5Dk4liJdNUWaW
AsGJhKbQAa35ylAFPyV7mb3dwU86urMJUa0A/6Juqn5W0z3g2Gng1Mb65SkiyO4w3+mHYvql3FcC
ETvhSdbSj9Ib2mUxwRPNEywd6jbh1zsx15t/iBP34zE2kycmzNkaPYS9sVT9LQSKvAJjIjxGZdH+
SaYGZF118GqrHYuFLIBlthjn0+01ath4HLeoGGB44TLnZr62ngRdAETBpTv76r+GltbBsq52zp4j
qqLWR/U6BDcYqGh4bucUgw8v+TlYMrdhsuTPzBxTIz6Y11OxSkZCsM9n8IuaVWaPCoWK/LjAD8hO
w7O5YWfWoz/RIQwsfajhyrOEGvKq1uyqg+dMd22jIDSvmS+udV0h8PZ/GsRevOAYJtZfNApo94Or
JKk/3OT71MMwiDi1WyM2C2IATUqp+GY6J6E7UJq98EtBnD4nccODm2suipwESPSb28Abg8ld0EGX
UKDUVDoLRBvv6LXc7iJ8wSipJSL/6iqIhfRRaLZJ8Mv2wMiatIRtou2qICTZYwYVdg3io8HPY6uc
JxRav3TOUShkRuHShCtFwUQDZchEqHG+XxVFkzo4z0xhrMNYG/tZ9lMsFG88sbytfWoQgOxZ5yol
xghh/ARhf6XOO3lNIWSucLcslRt3O6oN+TyQWQ8PwHJcFxkZEueucIUyDV6U2fua+SqSrLlakaV6
O6+/siur8wwmo0m9CGPPFZsyIkDjhtJ3oa+NOR35YwmCGs6RJF5QlJpOO3OE/FoXHzY1Tc2zwO/5
hnUrLCuUHL08AQ5HX6N7rAvVBp61T09ojh9Vw8uUPz2zbqa6CXD0LwfJyqUVnhh80IkNMKwtD3b5
D5LVOWIk3CpogLyY3NQnjb6FRuhTZBO0sH7MtFCpXBtCVZFfGkUZN9/z8hmsTdt6lp5egXcGEOWg
66hDCyuYepxuRiJ2le3SIwBOL1GHZPp+o/M7DSjjdZmgQqVfd7pdwIeolDdzuQGozJ8CNtmFtcXm
yZLpi3xZCeMpgEvOQGVk+QglNhyUEyCBnkoGMQcbVILyhsEYCjO1r/aPu+6YQRzSSIJVWb0r1urB
rOlXry0nG8vjM0Eua1BKwZ1OJU8TJehY1W/trLzJKdTboNyh8DebFIF2M/6SONEwO2y93Qc7JKmw
SvP/pZ8L3TlHJ8IeqHPpF7tX8Syf1AobFxITCFo+pmHis1oP59A5yCEEx7npx/7cMw8XHKqSN7Ru
GKg+9GMi1UxyrD/mvsdcc+l7s2yG/GJZhtbeHUeOiNwJPUwWTleYwhqRbsybI2G20u9gNqJCzN84
fEyr6bqxwBrXlYAlZrFd06RZrdbUOwPzpT57GsKs7eMWIqp0zXLeS0wHYOtTOXy0nF0CoH/vNOtC
BLNsEr+o1ZT38xBKJmv/cDKDJCGM72vIVAxwDGivnvGO/bniWPdKGZx97gYn0U9Pw79Ox731zl9g
aQBrx6dupt9kZ2sINFU80eu4UdkAdsUshP4Ddj3FoYnckwFWjbC8yweJFxyH5lxQiMaBoxCNT5ad
LdXWxs8IBdsQQFbBphF1/RhFQdO+VUONlPiJRSAKMZ4FLS2yio1h7OFZX3BVmufTYOtmjN12Ftqf
HOMQ9UZxGxrV06GgcODlMlqjF6Ge2oYcdum7TgWaLh4wWyQOydSOOUI26tL3C5NDknpXbTC1InhI
6qAXR1WDG3YIEDy+SNq9AWPzqbPBWB1aQt4gsmLIfw9eWe1UdyaKwsIrrdleJ0pHsVirrvMiGFUi
0dfwiSmnsbdL8DE5mJualI3ug6qITkGNqqe6/+cmxDzmnFYLNK8tq2eN9/Y1Rbmm5+VczgTgkeGA
LCVRJQqI3YkaXFDlKt1ZvQAmTjw2iU5Q7o35uG29lCilJfzX5rb/2g1oAG8FM56N8Ntb3a6KZW8X
8roMuJj+01vcvZ3YUFpzuZrEVGE+nAbkULquEcrkCF3+fONxAuQLGt2qh3TKRwk2qfwlcgVLao2m
81fhe9HAWgF/pAkzxtSxYzUP/2XS8Om301CgZQpFZLhzXgTqy4ZE3YnmvTLgQaDWUWbhYynF6EH/
2W0TdRA4aZATgBRuC8qtG0vtxDBgt2owVRmFTmwSVDtK764Db3quTQlMfj0yQNncZ+iM93MW2eCt
ZiK/R9TWbSKnXy5LFDLgQ9iShJ/62l4TcmagmzPhFIlSBp8BlzfDwGrRkekJTx8rMMw31q2b2lSj
VcItDahuerwTsf+4vQSwScrJ9L7ulGaustR3do5/3Z4v7JKTyvFSkOrsFP9ckJ6lmQxlPgfGaDWH
t05GM37syz2VdG1VvrRbcC3JHQYhWb9EbKsKEP99xxdl+//CPlW8jouqYFl6Oio9wFGfEN/KawZB
NrucvLUWc/PS1p+lSb8hZHIdtp5Sk3jmCgonyZoVcU72hMBo5Ia2T6zToa4WoyvW0l/usZzLqRoD
CQV4WuDjnQiAVjczj20wPNq2o4xRiLQgiN5MtSN1vuJLOjSowphaK/mAm0C0u54nEuejSGFSvQF0
FBD2TELfYi6vP9tyzB5iiz4JFk0Twmu9cv7C1iI9Zi9Gx7/n13n4eH3beQLr/anVfPoOtWtvo/IQ
1933lVQN1vovaXQVn1yBOUFtB6qh2yVBsyHCuLUryFlh+SHlweDjjqAXASGIaRpb4zILanLUuqF8
1Dx0midw/aUsKfyRYKZgHAiRXkd1h84apmZa5w8CfO3WQUv+N9/9QVyCXsFmaUvyTGQeE5Ag5F2+
kOymfKmYZHW0Ivu1I/u2uZys4eoZsQGcIm1jqFGLCakCw/CwzdVtcuqdlVzZX9JjtnR66otRgqgu
dJB7gtXaA0l99oaxYDH3gKXmV8gAG6RBgP9garB9JtxRwfljxjWV4a/s2om8ZGiHXpRM19lQWBYO
/uVCyHm6kT7ZaRAY0Hc87iIGOMbhViCNUw9KjBRWDKmN+m7CGr4OwaB0EiTl7s+XLal+xC69ZlHf
3PTrbd8dEkPwNZw1ck5EJYNlMpnAzBiNNkcHS8JpYmUZGYR9s24fPWDnOVv/cYOFX0N/+M0kTG5F
NUgo5oVfAc09NlSx3EUuNwuGDvzHZ4GM1V7F+ZaLc5lfkiyyQMU+Mgf8iQ5927gWpA+aVYgNV2Ju
OYcqueUy/bCrF2K2XyRi/Cis73j3ZS6uDPxEP7LCSlgurHAtE85OSj4Y7LA/DM3Ov9pqMJslXEX8
hnzd/8fgoh4B5upOTn2DUGNw2jw9RrIz/dj8X1+DzmTwdsSc+ZbzOO1zBo7Qgh+iP/alcP6v3uZi
ZXsJUPBfXXTldjHU0ftgW5wQduYLHEAzmwd1gc8FHkHJDuIZgP3XkjMh2owt8YiEgC15EBZstDGs
yd3mVlDuT4dUk+nd5ZWoGVSlZ8X1suxJ+JLmWE+tss0fkxaQdN+87uxsLXo+Y6FveJOwcS4ERkjw
VritymYicUjTE6bfaA5F9pfhX8/WEvduMdUp0afRRbjm5bdfoNCpA1VEQsMAzDCU7HVWFlTnvhrq
eZcQmxdP6SCkvJ0qUmQ4hDZYLLKn0Zg/TyKhvUo+PuHLY8gJLwdMO9cIuOHjxBWENhv+hfpn5aYk
uKMfM4dojiMtGYKbx5jhDgdIKF5BbvsM1zWsfb4q6xPNdPzzUz7P+GoSTeZ8JvGsAN380+D4ekcv
hjvJ1l4v1cz7JJVQgw80KS59oMIuLgvEz6hu8Jmrm/Ehy/+z6ZoboTq98Ahr+FRSHl5rjD+l+s+T
JjoXjygL7QQb4Rh56Y1y7I1HwLqOaZhv5JSwpcA1B3LMpxJ8qcoFHMJyjd7j1vW3n2qYIR1h5pkp
dZBEGza/un7B3KLVSJVgYuNmZYAy8drbcta/9DMXvqK148TVvKK61rNymsKfHqh89AhOp+131U7F
ZAfbFt0dYiUUd3/aBZQYijOneJpAn6AXxb3TGprdEM3vT6Vjh49LbCz4/qG3C5Y/UacERJ/d1Da6
9SYtec1mEWGa6rSqziOFh+WPbcC+xD7d++o9jLwIbanaiheYuH1upZDoSSZliNYS6Nb61DOlqfkv
lScz+UEQdRNSOero+gQnABTHjwNmAx9wEXZPnKnOUKE9W6ez8fPAct91JZxf904NDvg2M1pAGHDr
9cHbgqJIm7Rtz6O7GjIv3+00KsxpUZmlUfKNq58pNnbiuqZKFdcQjIv2UqjVqfYBCjop2nFpigIS
QthIhCJat8ykeSEJMBO9JokaYsl+KF9KSePP40mlIMaE7TbzoyGkLwILwCYgrguL6mMlH7B//Eay
/+KNo/J/rgxDQKcaIk2TP3RGelRr4fX2eKSt1bBeiv7C+iJ4434kojza/WvERtJJTHnGEbxGnneQ
Suuwy6WKC+Jp/7rQICc5Le7L4HSXouSsEftVwaecOllWq3aTjmMzKgOaVRcHUzZHW4BlScYQaQxP
2ksh+ZayLAHK0RjGxhcfybSroFv6xtKvnts1HY5vaEHFbP14Kzj1Wsl/sGw5V0P8b467YCxGVRoy
m70LkRmSKzX164aBxVCEzLNfMEFQaQLPhl6Cpi7/N8W4H300hF07USkRPWXs6qgEjFqTzYkq5r6f
0jTH18JyFLkMnSoA6eHpsUveCZykkEN8Uk/3fn9cvjfnI1A2tdhcv8Qle0rFtc0v9VLOxOSx1jsY
WrkEogWk2EKy8I5r0RNKCSzKIBojk107lomVTwBpyiLtQtGaY7w2gS/S69iIVItovR27ow0rBLUa
IDbSRRTn6Rg7iY1pcMb5QUK7JOd8b6MEBYKqJIrtdYwG6zzxMVgjH1Ant+/0k0Zfg98g0bDyUE9+
OJ0T5RrK9RSUg+PvZ/iJdw2CMExZ36LEVe46yKpjAA3Y8lKDx1amkGSIpaQSFqL6akwckajxSbfK
0uz3aHeemj3uErsWVAowP4fXyMWOsIkS/EUvbbIHLHqS3sKfiK8XlQYRzYRFUfY9ipnTqnjFowCT
beWZkg+03FuiktXr3A2S+lkblthwvaAWNc1qA57dnjz/g9/C+cBPJ4uqg1jLaRILBonmQashr9R1
MCVtjdiNsQ+vMRW9s1ItUqpXG3ZOBS/yzryK/a/lKs2v+wtXgW4lyKLwh+XSlVsxLiS0QTjUvcmG
ED50HuOn6g5d8IufBZM97BF4RZn7A/DSAEICNIVYdD3qJd4GUfVPKxVRUk5uDTFtS0w94+Q7R/ei
6Oe8+GjhQQTm2DNZELkuUJnF5M4POH6/x6d3US/+x7SV27laI2ES/6Cy967wnMz3KYatE3Y7Ov8S
hjds2RCvr0MZX3MtNY98lSfSRzAcJefTDUzpHIDptz8wqdqv/v+vhLOsCfxzXPZOAJ+Tpqul8L8v
Ey3Bq3kGrpPhtIq3XaSOYa26R++rGOuWFbWFLK23UW+6gu06PMmdOoyAWhdnYA7pREwOP1X8PhDD
U+EoYwhTwwpEU4okeOc/Ikra0SepMq8C0QKFUbQaOCv9ERrb1USGVEFtrUvvlsNFGbpZE50FzacN
UHW7pysUicibltfmGwzx6we8r12JdfXV0K4XpbPqk957C37sFhxVK0ULKjfHh+ZWgmAbNUkrMQjF
0Yi1d0Z0kd1pZjH5uI1ZlNdVB17PNLDx7LPnqTm5bMJLIS89KloE6yQxWTijvWoAf/5uj1nFA3rq
loxUzqOjtCf8kT0QIRHQDs9CTikOmSkj+GA/6p8TH29rRks4PMVygV9ot8AlUvwxp9fbGFqA6Tk1
2+8btOhQ2GjymEAfi1H7DRLnMwKieez/7JsFn2Git4t1459fJgA2XP7GE662Yv01DqVRdLAc4hGL
QdwA04AKLm6l60dxY0YrsoY0ESAnvN+4bRbY3oxMWzGrLIUkz76KrhfDrmFzxG4d8P5xzD5BmaPN
LQYP3365Gdh2L6j0pLxoKBwk7oNR1SMqHUzAVf2g73vBe/u4iqfFGgAvFen6R8Z3nM47KV0yj3lb
wUkRgySU9DOEkczpBZuDp6np9dknwsi5GYq9ln9DO1zyaGw8CgQ9R5Erd/UOqtD/2PU9rFGLjv2n
jy1c6HpcQXtrhQ1OrG952e+w265V9MjSGdC6Zcg68wCdg961u8CwDgVCbNy2klRMiFgSn2cQbEXj
JnHHn186n4J424sQWkAVc3ys0oigMMaI6d9+75R/3oObaWbv9xiIHO6BBEJIE1AUyFShqHPQZjwO
+xB0vAjZGA1uLNaLzECZlRPgiUh8qUg2P4wlEv4NHWdjTcYBBerbiJpB44sx7lfSxxAgIieYRWKi
DC5bM/1edUp6uHuq1duMBk7ehg7Izx5+JnMuMAtDoIoxY2zfnoNYVFUaLg3M+BWT/bbulOabqi4m
xjF+Tf9/ZpNjaOt3GrKOH6mnBe56eZ8uVEvhyYgvXp1yO6UN2GGUs5zN70Jr8HpChdxFlXrC/sM7
dNrg4LDJxfYNNijKKrRZZmVP8j8iXNKTd5bEDLEGQmHxknFVdBO+Pyc7vNjpcFpTPeJb2G/nG1gT
Lo6LpsjbVkgdA+ldPnHgyPazkoI5yHEkvO383S+cKoBiByv9MwvgSJhiBPeYzdstT1zXSmxzJLX6
bdtZs3uMarqZpsjf6gqAqOo0akN3Yir6O1x58FLyUxx5DPbEyHov+L6N9hZN/tG4WKOOvLd4ejhW
fZjhvOZRvldkZIKwjUHp70xSh3HFKHzIwf1Bb51vPgAGrhHlzq9eK1+2gAUlFgEbKBO4ny5QfEfn
tX3mVO2FvmTEy4Q5MpIm/HOtUDcfyixYnpaf8PCkws4ra7TQJb6KPyaUXvM/BU8pZ7SuO87UVJpf
oMH7tYLYYJ1H5jFxfsm5ZD6UqbjVnWj2MQi+fR60a10QqVJxGEtcQsFmlWk4vKZTATPOeRsCO2As
kBNquL8tLyX3ddH1D1N8ICptugLv3UUJ6nwV6wi50Z/S+FOP1NTKc4QYUUPy+N90TFG7fXYe3mE1
ASQAfYyEpNXy4noQXi+AVrQ3OcFFkA3CBjJhXJByL7UAHtX6KsNM53BWAvOM8zLC1hhVxZktJm2R
TADi7xb59WyI1a1sYpTsASx08WurNnaCCBxiZ7tvmX/VYk3xhInU20SC/h+iF7bJ7JLq/aXg2DeD
R0vdgHUcLRmINELkgAQWT0Q4F6whDdx2FzjEW83mF/U8mF5v01eXrILXAxAWkvO5N2afETrj26uB
jSIyBuA7F2AH+JAucMG/H5Oze9ZrqahSE/Z2lp3ZmIpv+7c5De7N9cD8x63xPKiu1RH0N6d0YXdZ
O1ffh3qPKz8XU8nFqFhI1V+KFUd6iYA4MKTDaOpN3NFnLPDt0txhV6bFaDPVmLK+TrxiZDf6I6QO
rJgw58hrioYH0bLmGsMK33js91ODLrAzxnQ1isglukpxthtxV06H3ZO9nkBC6CMhye3KONkgwStv
fA2RQWgNt5zASqzIORbq0Rnjjia1LKEwBuB/KIeooVWfaqF1OvnEcepNYwu16TvuO6VF+3SiWA10
BQPm3VLJF5RIB56stcmAbf9pL6oJmYf2PGaSg4/vMgkAlyqhgbtLNbERwqz0/ynp1DbCbfhwhZih
puYJL0tNYIvwyRZUnuSVOmZQTFZ/5lpM9H+Stu0kk21uJkYdiJ9Dchi4ahlkYgcBdQd6PXODMuY0
2MR11RWe962OqNGq3JzQTaNM6gpB4vMzEyoWAan+Nb4WlXLmr77KWcfQJKJIH3/ZS0oyg7wW8Iis
cnJJceAUgKjw3jzC0L5rnz6KOlK6+aS4W78PJJSPCUx8cy2vsMs6OP+pC3b1cIJsvK73It/tCOX6
eiqHmCPjDf/UStfTOD0oBGHNBH6oqMGaxv2CKnbb37khPUlHHktI/p53JlcNGByQOBWX4qRFn8wJ
UlJSOiJ1+dEX9P4R9PBXCcf0ZSLKOCtUk+fytMargtrbmeTnNPxzVPJYik+Uu8e34ew6rnbBfBNS
wtwNRduJUseL4WZb4h91LYRrdny14zy+0foJQWO5exdT/sBmLa9YreWHoxTzBaDOW1aiWe8kaCaj
hCBioJ6MRB1CEInSTJ/Qot0hPrS3trRoZoG0FQ3MSid0JXZ6AwR/vjRglbwWN1voXg/sDfk8vrdt
max+FlaKcKazR+YPVeJcJmyArkvOfrvuK6Ym6OSMYQN1hfJwhaQSoP1Fiidg9VxidlgjhEEi10i/
bh+/8VeouBIfxm09K6XAQeF5h+VwxUTJMSwYNKB8P8eArw0F2rOIOhhG7y3BZSm1cQ00eewE9fSj
+oxFxppyP2dIb7qNkRaKnCRyt++9Kzn0iIRf9V3ZGH1c8xq2fUyEHlE4ICDmrBPffx+We1FWubdS
sc7tLOIODv12STJ+4RXPXTXUXCCK3ou+wi3FY5eL2IPxUKkOLzHu9hPO3864dhgVauDTMtelXIpB
PqIz20iYWpYDGOuXybvQtTBlFgVXmxCsuLnzWE66y0HPmJQjkDIuUTi077ZYNI3rCO7AxZJgW67o
jR8yr7M1dBOUE0SOCm/N+lyDOFw6X59r2WO89tRQh/2IMrDyK9t6KVnHEGasElGoYPwf9VpMzS0s
V/MkjoEautvoOC2RQcO867Ni8qt3X4b7kJRjqoi3rA4Dqsp6XBaSJIAvW1u8IwCj5zfiXFp6Q1pv
toz9KLLJ5yQM6zSwlk1cXnrLRJT6GZPazFWNodeY20IetcHWpGxFNnu/4Lces0gfcmt8COB7Gj6F
ZI2hfkOteUFWkMQu8/yMsWy+/SoCueSYJAW3w8wTVMIUcjkSBa6Ega6oY2IxrEpV3oX5JDe0L8cX
7WhnCgm66Itie1zcz3F5dhgPxjh5idKOYctfNro4EaAza1fr+OEcQ8VGPyyugGEEA+Rrrj5vhf7J
twHBBottYF2RM+847TuETJ9YWf9KRrA5/VSRB/zp/TlLSNqmrCnNLQ7gc6uozV4cirFbMaChiYvJ
xvpQVlmjzAGdGZTBaaJsZyuVeWcmfnklvourPNRFflfQ+n4Y7Awx8YAQOxmhwh4MikxNNHM4egOi
7q4okmE04QzWKx9Mh+q1gO4BF3TAsBlDNiozGHivd1rnTSE4apC0VqwEEWklPfje5SjlbT05umtK
lAh305m2Kpt+ApassAy4xny+gWUbs8oEUUbjHSqNb1wBn6jIBkWJuoXQAeiyFMB3o8fQD69yxKqq
smz0Lm/nJR9v/O/6nAiBJ1/awjbW/AiCCuOo9HpzjAXX3kR61jKcaK5Msii/9DoOd0yAJTATu7CX
jLB/HJfOw/m0PDgjFC1grU9UaajemGIjP//cm95T9tPVkX3V+DhoO/62r5tHeycF/G6SlGnICU7h
sfye1pT/NClBi5iDAwxJJczy3mIe9PF5Gz4bBQ+Lh3Tu9wbQRp3YsQU2jDsKAbbRQLA7sa+O+f3i
+1r1nWJQlN5i603kEMbeIzNWoVGVJTJIJTg+dLne1hSfyA3vjASXLX+vk9fB/CT1x1LzFc1YvPOV
JRsf54F9YjWz52Dec2GPg6K3qPXUt0nTyKhUzwcnIV3dR2PMD8i5R6Pn+rcw5pi1ey39J3vEqIqE
ZXZEL6z+hyNcA13ZcyTNp583CzKjDJ//cTRxLaWwc4wLt6Ehv72NlHnOrcCxoZKuja1BP6y9g3Ro
pwGI/qZR+e44OGIjuUoM+DzqcLoarWUcPKHwqlryuhwMYPMKalLBEoiRlIuuqW8i68V75U80aLDP
B1/SJ6LSmGC9hy41XqVrdt9cNRMc/d2mWe+G5+WoEtssjHV2ijI0E536El2gIb01izaiH+Onl0GY
aEtm48GSdc0xXG8yBXwZBVDxI0+cvUHNuuwrmX+lf+LDE6VaYccEX9CDWqYSKJ0jvPuvPi6fRMhb
wmbanzi56MtXaYSQzPRBcs91cavkvekMtO8KosuRU7jCXI2XIfh+uTstvp5DOyTkQIuc4wE+R3ZW
esmQRuKx1LhIFKkpwuUE5I+5VwZ/vt8RMPEjMXAit6KhL5opK4AtlGRoU7vbmq1jDMuZ/Rxzve8f
s+VuMwfL2xd+TPd1TnuDSpz12cW4/AKkx24L/u1LCINwVuBTWNfjiR3clPw+zjHgmFTQ/ZZGVcab
HBdsVO8W8382VDe8XAUwaIaQT6gIFVJJ5dFVWcxbSA7cvRGk21Ay0Dk1t707MGU0W9ggCOL/4O6j
oyC7E6jAE88r7cjVlHVG1aufFI1PmIz3xb8DvDeGFHVa+iUE/L2pvh1BZVLzHMUkVQwHs331g5Um
zxt551ygelsm9nd3b1MuiNrlcf3Wcv8cgdldw12yB2V9K0OSPg6oCpuxuTO/RSkYJ8+fBanHB/N2
gDjotHICBQ7y0I12gvLhjYRGaU0WUNyfU8N3DWEEKGhsz5+rTUf3XYFYggTkM78knwGd55yuexg9
Ya9/39ftCBCVbyvvC8YZFx/lrnkJ/wam+pIK0ffCYQ0eh0/V5vflCX4vESC5/K3pj7yhOsxbvCgB
qHxKZd0hgQLnFlFqMBW9WtGN2XXqXA/oezkucR0oOiT+qvoShQmoXJq79AVQOn3RPZGdRw8WPhcU
r2bDjkeoJqlmOMx8NICWn7X9maYbuypjWfDe0hCUqkOhHNW2pagqPHBIpW/FuaQONekbCDuNiqS8
zzqqc/ZHmS7/IWDCoEiGH5k3V6oAs47yVfU1z0twqKPf5QonOFHS4DYb172XVBBSuVqpi3IFZG+c
s1yp4lNaaJ4xb6U+DxSeP0WdowXUVYFQfBjjfiaEwdG0uJu3xvif2IyaL7PyLPrX3VmWRFWslETe
HCDepn6ZCvXflUclJW3/SNtLoXLV2RxKaU39LrGrvahjUUeTJ0fNeZWFl3LgO0/qbauZ62m+0uIM
tceJNT4+Vj26C6Xnvf/w/xYwelYR3IzjXLUxO6kfr0G+SqDBSpSM+fMboiIDmZz0zaaGT1WlupLG
8TN6YtsPlJOrrZOIeiPEWEujTaTj8TcbMgjboJFK0iI2y4E70cToIPQEOfC5hcWSjoSdiGlgpmho
IDWIco4SY0dPHmcSbn5Csqh9wtXi4fheS8qp1R52jdc8Ujv1/N02cYfoNn0C4lDwPjXYTOlBKNzl
na/8dq4SmxPM7HqurdkCIixBWvD7CTVqC7UZ5S+xOZTyw0kWy5hpXIgrA1q3vjIUQZz8Yb93Wdsq
ZN+9FMIZ6SJIgfOJu4WpacqL/umssef7b1wsbOd16rNC71uhhSnBZOOsmQjkiYMW6d9qOq0ErUA5
0s7gylg6dsQhSfj6pbnwxYRRLvVXvphZA8N0axH2s9dCs3XYOD2DJwiZkFnTZ/MCYZIU+BGRl+RV
ZYafioo6NfZtt6DRQAkhJADNCYTR7Kt9qGswV+S/Ezbm/sNQRYsZrmQLzhTmLzbPYmb+wIzSWVxM
fSNhTXJ0e/J9ez9Fr8R2XZ4omZfeJyobFjues30FrA4OthbahJOqsW7YZL6gHHyghlZuyDGaktY0
4L9DoiwMwHESI/dlLuVXmQsYPLPM6NHK2lIo7mkWC/gYPqYE+EJyCwOj2pzDPneQE0RmkMB3h1Qj
pVTrB6KXjCjmdxV5164ro/j49nP2We7lledMHeWgYrq7R/wMlsa83qqdgWxRZ5guoiedAFIDf+k3
oGB81zVLd6dB3OThmfK+1sJy/yE2qdX33Wi+iNMEUTzXpkWzP4PQ4U4YDcgs7vyxGumym24fpCe0
okr1nw5c4axTrR/eqJ2SZj+JIK9+rMcLdUI37ukgX06nlLEGX5R8bim3/EQUstJmzQFAHLepz8j6
vP4/eak2+j6PVspS99PUrkYxuU2hM5aZp+65QnY5aFzfDWdI7a7/mM6N9Eoyip1jFd3KKva1Qt2i
ZjocBQ49Qy+UryOhC8GrBdkI9S2opp2oKcAMGiOypSgkawXKU97IUxaU7qO08KgjJmx3hsfoNA1p
x5OCJ2Cny9EyvuF2uWdIrC9w4dZP86V4oBDjMvwzt8u6L5s+m970BgYzE9Rym9K8tsl75Sk6G0B6
oetGmQSLnBE6JnzRG4DkaTmc4lmOuvvVx3sEb2nMx9+sTLLrC5cZ9ql+hxarm27fMp/VjJeFCYDn
SqTEbV0h6YoPr15oar+VO9z4nDsB0nXIhoXfBadSYfBA/XCqHGi0hdsbOKDGWNGtR+khlUmKiOwK
FPBxd3u6hthyoyByCkJAh5cB6iVpn4cP9Hm1rJ/nDX9lGBKZVvs1Cjew1FBLsmIgQYmpa03IFTTP
WRY8xrSAviwKyfIVgM9kBOWVEgk8ah94a/4G/eyGUtejq5147MsKFWGOyZPZ/WJiV9Ucx66hwfQz
paOPQZp5FeCD7UGIH7Zrkk0wL6/6BfwMxyVF4YF7Gqlz/6g2ncgyEE0cAeSKjwXWtoi8Bfsgh3KV
PIagwpn4sh6Y/EXoZZ2U0krCMGVec5i8UN8pRNlJku5yn4JX6erxjRc8YZrMl+TyzXqA0loSFu9b
uN1c+4J165NnbGecTwtbNK5pLr+qTlsOM3bCG+RvHt3mbmQa3bMnO6eRC61rnW5YpE+H2BQra4Qv
Y768CNkkvcFztt//sArurHi3++SvdiLeAA9WSDrJoNKYoLz3JOMYawMTAhAxNXI+3KmdBno6IssI
7LTyP4/EMTplZu129IAuY1Dl8XNEeDty+GB7LrPoPX9QhIP97Cpk8HoFE7ZADfcHv8iUvfK7HA2J
xtvKSefOrAo7c9JUth+F6g+ygBb9639XrsF/lJk4tqBMSlCX4H6T5A0l9VhIR6d/wsUUsLsNC0od
MtamoCP0oesgzfSDfXtUM/lF/4sN9SFHML7/ML4OyHfw4wp18cfDUIepfvNRxe5KwssPw5xxe5RL
lg6EaKTrfEpGuMVcCCPY+b4maEKdh0wOlSqFr7It2vQXFrBKWU8uqBtQ6Q/qOTnsq1NhhRX8Bkj7
zhSiTE8GQZCobHzEfoY6wvUOkuczgqU7kRrx6PdUukl3CpiBcqSeNWDin1kL2nsRcsOxj9N/XAae
EIUguJGEL3jGl57jY0EmJJWNez3UIvLi4kXEcex+sZqMXLbmrBpAbvsl/2Wf1s1+UtT0WuT1oheT
9sXlM0b0Ihfe77SfAgvmSbHZ1yfdwkqit9DvBBiM2e6M2IZ+N2n2K2hiEfjxWV6RnS0AOm9yNTsl
+IoMDwCLf67qTC1A6Xqu7ViAsl8HRfbLjNyYFwHqK8dnpOF5I09kkKqLXbRjk5gflE+Z2P+Xx5VV
La13Xgi5PBDIfRL1yvCrIhfnXTUigKODTWNnYFTo2UGM3wkgYU9wYEFos8o+tgGmtQefg8uS7Lsv
Qn6cFJH7PJqWzugEi+fLmcsJNQ2zOz8XbRmnzQsMDzRPZXQKkpwWmunXI5oCz4iggp6IKhRaMWPW
kQuxv0UQnplvi6+XL2HnwEMM7Pw6wRhYQumitVE7OdKXSMePrhfNdKhL7lX06XqUL/v937ZfSU8k
lPjWC/uMrbJ+vDIuTZnxsT4qok2rC7vgADhrsBOdcbDZWYd87Sp3+HWkk+T4SPIyNoA+08peDNpq
cpWYfTShliscCgAJxcpLXx58oBtYC65m7UqMbYmVo6qwtVbRoCeICrcZEcNesJFKxDkgZyiCe2BH
eXiQHuHwRCOpSErNupdVQ5YQAAcpXMUMznGSkM7BWmOU/HnyM2EZQKcAzKXxdv94GMhJNgIulE/Z
znkJuyoOr68/rt25C1/iswisjP0eVtyq/lyK9K0xsMEgpuDPZ2OA5fFdbk02kBgiAVkql66QPf7R
7CvCDGQfnfOnM0ec8fPynbnxW5IHTp/Z1UnlU4EVFEKTTe+xCauy4sh+uwhdCN/nMajauZmZZ13K
y+ZvihqqlNCqGC7zRGzLRoICsbNnfc6C12hULmp1bcs6NGz8gD/0heP8CtD3oVP8vaPZBDnp+imy
DDElpY+iZ8mVFW90DRZL9vDUCs2vDmpESo6XZB7GTEzmGZiEVMelb3zRC5Hwu6MjFRxzqtzazFvC
uZvzRGEryz5v+QSEdAUrurSr4YrKgyUG3CAIz36WGgCMs8z2rHaQl+nGlPygEoGtGGOqW+lY7fD+
ATz6pWQlKCj11+1JY2fhGUVOylVxlfgx6TM7Oh7uqRU35VzX6x4vnIHs/pwZsPTXylGimGmLchSv
iGwqxd+Japp4k9E3KblLkDRkbcX88iDdtdN+Ek6c0Kd5i8te5wUXHCQDYye0ErCSvtDdTNPrXe8a
NJeDMes3WNzcYqW7yfh1Bn8xjlTAVuJ2dBPnj16CVzH/Aco8Y17rfFbRt1msdZA/UHrpzuU7TpcP
G28o1r1LlfV4trmAVRxp9k/bd7k53FcruY2ojQypfPbIfGFPfnmSi3wV8boXGZA3nCdvIO+4+x8H
Fo1hv4dMyQA8bWsz0SIw5DnIpnM/mA5FladNZbKu5WvMNxD+UCQniOu5YVLjx+WLCErERNtuSvn9
zyVmtECzUyXu6bWGpmt5SNI3S2NjB++CF3axh7kOlNLlwXwoc1ZxygfllAmfQPHt+MtHK2AyALJ3
8OLuhn+/QaMaSDJsMMPfS3vqwIytEgMULPLTpe3I2AS+MGc/wdgnVpZd/ZxErNEN0HhxsAeEuKjP
hNUC5h7Aapna8l6PNdfgNjdEMMLZxh2DnGF00m7/E/hy0CQ1pOBwHJtc/xcvOkObOQoCPu4lp9fU
bqmuMGWhigufS7pqoSWx0fTlokd79e6ig9GnQ4NYN+aisRb96JdGuMNi6ItIPHZfNAlag8DtTGoE
f3dPyve2I9q7Ve8+OrMqQGIiZDssHaGKLallzSNA/r63UUQsbU3vN3xSOiWBNHouf0kW5cxrsvZY
L7lINRKlAmOTopdwwOyPLU0I65r9RQJwX1mOPYIZtzFVp2JgrshNOEG2ZWouLgOLIGv1pb6yZy6c
Gyeod03K86bguaUZkL5iJKEBB+1LWTs9DJP8Abhzt7QQXVYdgzFZwAIWlFcH6npTcKay0U9EI3k8
BjE8XjPWYd1mdn31aOHYCLyLoFED/sy3tHpr5sYzpVxY1CM3QXOPuUYjwuUeDk7FGBhy82ax3vOZ
GRE4OZYP/GK07ZZYutmihXuvzERuYXkadNFpHYtB1uq1cBflxAT/I0WEs/6HGprMxcivcghuOApj
mbJ77oqPOqGg1vwEYPR2q3xulrxd25kq1PkGSFop2noy/g60OcE1vM9UIR433N4fk6RfeASCxjXi
pMKiC3q4dyIMp4aDBs/6g4XY6SatXA79VBKXPeB4LStNbs9mIBx8TBny94GA/XIIylPQxKjT2tPt
Fs+c9/7qGAyY8gbhGR4r5ncZtfr4+z223RJHvL+kNSjTVyIqU1kDHr98aUgMdfEMF9+iQ9pAhNoF
8tbd3lhJCxndH9S8jtshaKLemjYmC4gzWhNuJN3ehlbPq4mSa54LgQRoACv4ofI/aar0fCXdI9pD
PUrg5++DBOi/yYrxnk9UXCvb/z4KV18HSzEl4DR74QQWW09Go9Q29sL08ocj9upZyajpSc33LSCC
Eyy/Oo8FEecW+XjBRjRPSADQHXDVYYFwm/fD6Py6YCzka46d2SCSbZqH8dn5SrodeCg5JV8f9i1E
Peyamd6Ukt+DpOxkc6JXvcNJTiEKhtRfH4XSLEZNB52TItNp87H3xh8BI5eHkRGe+Uk/WJiKodvB
UrU/ufS7n0d8HnU2iiTUSG3EsljTNd2gxuAWbIvt3DwJ4qQmzKCkIZjVkSQGK+zTQ92MDEg44nID
bWyCUiTABZTP2bkpjuF47GijpmbDM538QlBoSkVKaGy3jbKTF2UJC+ugtzua/xm9S5DwIOENqqWX
VUrFjXoJeNSIW3etsnfLlhqNTMNr7enzZgZluXpmbC+rv0TyDALuyCOaik0hJHnqEaZGimrvlBeL
1/YnIeS0fw+bOkd9Z4Fa1df8FjVzGvdkU/9ilRt0n7mFh6sAA02slmM0Ws11Hq4mtZ6zQabOAL9k
sy2ACLlEiSfO8c7DsrWWGGHH8iaqPzLFgzatHcXmRd9ovb2/qaC//S+uX/pslDCUgp4alR/QmNtb
UDx1gC4zQMGBKIgjHVyB71QWlLs/okUhC/emZuQdjWOtXXm73gJ5fqX8m0NIsCysghDiz2JNOxl7
Qv1CExW2gIkppdJa4BNOBGnXFO4OcCon5yTtzwZg8XrEvO2H7exLBYUpP5ZSzniIaqE1agROXCGk
ZKbmnW6aF8uVnXVxFHqrdtK1hZHieFjMGQ6l3nHNPNwgVhg0mSe+A71eDuqYdKPbMV0k1ou/zoAv
LvFLsYzR3IRWPE9A+7b3FrwsvP9Ehh2zGc1WwDtMbsvyFJ+GpOHMBIctYtGZDOozZ4qbu5X6Rxm3
CSbvlQJpMHKFleb99Me+wy9hA7HKjUVtYGcjS4z8XCH2NswQ7P+CO2vOrsx9m8FHSxnZR0hezgzi
ZWKvDRbyxUrVe4T2CSVaxoI23icuNQCrOl/YxTAkduink6YUpR3iFAikf4bMNinVA4Dh/cTJdKw8
HSBFeDhB77i+dyj+PvwASx+wNpeOxSurig+DzS5rEYXmYTsSq3REg5f7oxJz1+sj4AE1FW4pRDdo
fxb90KozDGGoL/QxGUD+Qcn03182ZCb7D73dCYU7PoVbSsTV+ZKm8yMwkxw90sK3edLpmgcP7iiR
fTRc0wmjxArWmRbFWeMu68W6hF9FTUqGNZDS7yuEAlF5izZImhX2jWJO2JfKcJBcRNvIcTHTRGwt
im248MsPBauQ26FxPWj6ImBc6QsRxHsEl50gmfHTl7PbHTfLWpH35u5zytZJFF0pYlEooLCk8fcJ
DbYeXGcs0WjC+RshqorkV4OKLt4yBn0U8++IONVyn+f1yjxiKXrz+UZZVcPDNK1InOVs5vmmfICm
vbV/ppOcg4yluURAsoZc1sgAUVGOS3wy0BJT1CNLn0+Q5A4yfF/tufocd0pJLmcFdaaZG/dcTnKz
gkFbgaPkJGkpFspyHK8e192uLq4afzKqYUxqylrXszKx0fqu1/QP8JdC+CB7inLhDl52FzQF3reW
SIQXPJZR0gghlTa5s47K6qhhfjO+1+1W2YVDDwq/uC/nUi2Yj1A1KSpuk3weKf0IKUeUbkq71M6o
bmgXv/ozl86XC7o8yW1XVghLRM838cUw0IU2nfs2F0EtjJtas1+1kS4AfVaO4/yhKSAr0MBrgQsc
uvD22K8CP158WDjzVrtXh2rquQYmp5RyEatjR5/JWNXikZDdYZCNZBQ+D76vv5fRBFIX7zmhDKbd
DSrky5ZW2jcvQlh6CpJeEzAs+u5Z5h2iJS11fXkNKEx1QwX4LsfuQwTIk2REvLTTIl1XUFvCqnOt
nH4dKBHAIMIFbZILZbxBSAPDo0Q7RIqcgzT1OWdOItsRBp8gWZDv0kYMF3VYwo4wlqUZk/Wr4TwG
BxAwRY0giL582i/xr+OSAFByRF8fjma7mOWm6WQ3OG4mKEq5XeBo0hrPFhn/ZIRFKLXYqYSWF1ct
v+lMiFOtsqEAxyihgBOIepJfoLMTheX8YQW2uzIMjhdb6ILssMsnC3C1Z+cvFn6d+2hgEaC9gyEo
VLQhergY+bhkg1PtQhLmzxVnb8FaVyHcbWSaa37eYraCCXPC34OnMCfDlRSk58KqERq8L3UoXjGT
08PY3w3bM0mS+TMtJ6VFT8jQbo0sJOHuz/pAquOMlOBrBaBW/wfQS03NpDJLlurv/kuApz7XuY0Q
zHq0iuiCCzOGODXcHcuR8XzSdCn4DiGCSF3ZmpzgHP62EH6wyXB8ib/GvFZN+oljbWs1WIaO48wI
86wVz8foxlVKRe2Z85qRTpEVbXKh3G77Z3sAGQugnecx2bsqzY6VbBRgvmjo7TPG1PsDEezs8sq/
K4XvsBl10oNv9QeFOQzCc34YqstpYNcP/2ejekgKEGe7gRJ7jgienTc9EZKYdsxBKgqOjA1ev1Gm
N9dm61c3o9uNC67rTHmJ75ai6C7U+A0XLj8cPilo9arNhPSIRdJGdLqWhJYbWUVV5HaJlVYbdjwi
xdY3Js+g5/B/glk4/ij+FiLm27Kn0lZi1gTRDironN4ZXFn7cz2knn2E3v3sGzZf6ksDiUAlcwZ5
mwCp/XA60IlouztI+1STrFYyi5RShuEEzVC9g2PBPS50KyK/W70mQylgRuBvj5txKSGtHUyUpLnP
RrLpqaURdF/1waCkpgWx53K6kYZSVbbdmy8+kaFa1+0X1OosIs38AnUZhcX6xv1yrZv1C4DcHl4O
o/OeGA1v7d1GRRCvpcZy+OB/YPXYPc4NCMcfGO7PpAetrU5/KbU3q2yPHgGvKxMqGVWUj4+pjlFe
3GLYIRq3pmVHTNGuB4bN24NBSOOJ6xczbqGeBvn7RMUb3o83qngjoKcOhjqfEyjvRpDVo4gVIoDX
YT2jh9iLrn0DLGbaIpVCCo6VWkwm3WbD4DJaZF5HELdUnHyiVP5YTXZx9C/pHtAtwC99YiW73jAG
ZdGLs/82VshbKM0vAUG02rc7w29cCTBRLMMZcEwLJKhwgo7434jREBAOYSst1NVH8CSJr1ENnnNj
Np5L1cnZT2fLOAibpcoRogwbqnMrXvIjYPKz3U3pMxtd+1c67Zot1U/ufzsj0RZEBoyrCqHi+Tme
cjaujlK4F17w38evpD4kjdp9e2OTkv/EgmBw1DlDjFet047MdAZaSX0ifVBA/8upv6XtQdG1aCg/
QQiluFzlK/QoxTQbQYHvbwwaVejWqpCCdIUomEbiuOM1tj8BNOFMsR+dnlaPB27VIs2ljIVZWHmj
aQ/Pi/+8Kmg5UHMA1DYKIvE/6LCRLNRJWVZMV71RubOYE1HbugO9ikJJ0tFeT49szBpMLgGGmWyL
RrGZegPwQUuh046VchDjDS42IZn7xNBx38F+d+fgO6DyKpa/H8Be7fyPt1evFZRkxpWG73BgzCyR
MTGcOs+XlzAhTQDW0A8SNBh8e7uYCH+vTuNykq6wFHOZTz7RM9bSn/hf0nwCCDC7SEU1qW9SVs1B
cWK9fSHphtR8J0ywty0f7B10b5RZ/2nZZJ+S/6fooU7PKm2F4Zz563rL0c46RKK8JlzPSkNMQFtj
ep4m5ZCj2TnwXgB9NtXebTXj+9Z5Hip7lVsAZMkLC30NhV7altsKpRdGClRlmsOmlGXqPsJpjGSK
oLgWYhNbpWyk53CEpmAQS71dmyVefwNQ1/q/U2ceAm3xBleDPRVcGIXCtoxRv3y42fgOSjumEmK2
FgfbAv8BvqFmkq4kSzIG7CP/FnyC7iJzdHusvFHZhx63MVIhxPe/GqpX5u7XrzIcqY4G9ocGQZEI
Jqn7JkhcocQWYvN+fxoRBDA4kXo6FKhBrfhmlAGE96/P5uF7vG+kF5w3tYBCcnkH3ZkhX28f0WTw
j07QrHVP1J/sJo21rSWKdqTCGSg1TYa27A+FRPTRnK2LaTIGjrh/QaFrK4joucUkz5aydqzhMuSN
UNROgrhjjIm59hLD7tX5rEkO7MB3CFri89Ipfc/n6rgumB4f4SSJd7Kx4KNBZmj4QsAxbeVGtJUg
tD07PMVkf1akDUrznqpVe5tolLYVsDqMItQqw6/Xb5qG4T6i/KMgoygpxGyBgBnjIDuJBqrN4ovL
Qq14GRZLVzvyd3Co9wA0qo33ATgAFh29rsUgGxU9ADLule1NDos1Zim3bI7aEbBaC8VuDlqWp6Mc
2R42Jk/x0Ec1XGUHwMvmiUx21UYUCGS6aJUa1UN+1ITOL0swLNAKhiXsReBdrcoXrp+896VCrKXj
IB7vfpI+jP0/TG82hG6nWLMcB9NAaDgTyWv2fAYbHM0RwKbombYv0CxVPlI1GLjQcKGwmeji4Vzd
t79xoT7w+FESS2lGXDMvwNEwrtvjD4sD/KK+uIOmplJhKOJzQqb3Ooiki9UY10K+T9YS5ataw4u/
FCpLVi/2xmzs2ivPdlDoVns/yXAzzTwZdG0MwuHABKGjiLUyar6i3Bg5ozig6OlcLIX5G4t1DkJu
T4AbvrbnnVhe5uo3TZRmYMqL81MkMxVF4E5em7cy1TC2tW2ucVTtDh1BdDCo3ZUZmzPXYIteAASk
QI2Cb/6ms+uNUcOObd803yGGlfOwjUovOFFIUHbra4CJ/HwNEcRCglfulMjIKfePoGv4pICbW3Ug
SvLKtgyTmA/U6wzJEGggkd+qLwjuxT44SMaCcHwqiuVbWJAB9oH2Vx2HRV7ZVG18rkD95f/OB2t8
vR8pcx/7VK/u/xKfmYYgxg9reyG4lb9AcWGzDR3nl8l7VifC7b57ty/UZW1hag1leDt5UXKzEd43
4l6ckQB2LvO7+ApczbHHxEZgvVMejn0clIFNpOg176O1gPdEVAFkPLa0CneD5ileqFSDf/pKHMMo
+LhbrL6cnd/zl/qt++C1gTwFs8mVJ0UfjOilMUK8TG0tNBoyBSb8lwR83/yebuNROVyWVFMd3uhP
TU/D9iDWs+3u5BPrP9LX+8YREOEaX3W1pQ96CdPiNF/j0edSz482FKuN/o+/y2+lk+XnTG6U0reQ
EUVhxH5YqDdLLABR7GKfcGcWm3z1b57OG+EdsqU3LwKfjbXuzlntAAv1/ShJXUIHHaaSjsluUuw6
DnjwR7q+3iLUyt3miL4zJzOcHGF+mYGEKUE60wdvDBxk2W/Z/oUtD8lV4+QaXWhtFOp43Gv6tpJX
2M7FgasbPLgEgV5Rr+LJulGomDnFVpjDi2PWNdyifROZsd9pulSdvv+K6KM/sIYouza8simPsZ4P
Fmuk27xxpRonBOTI/8+xRcv0blWnMqSutc8UcKlwZIsS8tPGIcj/I4iLMLGeoJ6Ra5NSXrrzBTsN
1H5iZKV93oLERfgFlBWHbvgfl8Ebhttm2TP/7y0qIob7hc5HqdwrB9pKUYK0vKTkng4fzUsXLss2
jtPycKu+De6ZfqrklWSLeyUbyawCj8fS0iETjBkVbMBpre2lnx/bkRU3og7Himm2r4ety3tNINRl
MAflLBSC1AQ9I5CNNO+G3wjNtsWKvzkGFt7uy4EC3ihWxCa/RnFTuYhA3N5jKKRvQOXmA06KPzCb
jjna1W20pjVXC/JQBZZBmhUDMWJH6mIDHjd1xwiYGFbjzY//8ytcGNwVP/Cpg+9bSRwnfukt8LAM
ypzgVPLy60lyu8Ajdpeu5M7iNwW8h1DJUfzYwvKmirV9/T/kF8sl7ThlL2JoMIG1hNNXjyh+MBuH
K6Yvk1OGbUAayA5n6nY057l7eWAsGgQMA07WFTzWAD3CQnwIWJ3cABbiEdgLfblC1bzTTwAjXGjh
OLMB67tZCPfvXOM9c614dQwt4Y2IPtaUAEt+rKH26MmCGjeA4NNU/2WxoKOHkdo78ZtmE0VMcNuV
ayAtkzK+ptmg+EmzTBtXvIMUnEgmUgOLy5noGw9INgwZm24Jsds4p526doOGm5+TzSVb6EXUmaZu
iAiXJ/uTWCN3r4rEO5u/Uc8cwX+YahNFIFs+GjD3bFtq85gsL98eP3Z3wdbs/kN7Lhwv+95TYsv3
NtbA1b7bo65O4/WypmEFwZlQ0qEYuGEdZad9YejHvOScyuzuPax/DqK/ebs66WQtuweaIa8QoIdE
FLQtembxLzUpdQlkQ2kKv/os/a/V07p7uZoKqxZJp2BQLdk+0irNXzk6BCEwZRCk3+T/tH38RETF
0fEF89llk+Q5mtM8jWpmezUIhPvQAWtC0d2Km+dirhkLzUsvFlmNpOk5zaOMhVSs1H6Wne6aQMJU
HJsCTN6bN7u6wDpO8oWH9LpDnCO7/XQ5wrNa4GfX7JUxwhggvtRJKoVirLCcA5Vqa9IBEUQPxsZm
0mCic9QZv/r0Aq8b9q7ukWPVQruZQkum6AZa+dW9y5FVHEI+92iFgk4vYQHmjem8fMkWPVgZX+HB
PrAJArd0ZmSwmMtfqmLOZ9Tz9KRobh1JaWOcywvEk0h+GNO9awj+88pxl9xQUVWzqoAf6t1Tf8bw
8P07bsHFujqoA6d9HmVisq3haRQosg+Cx5BjWwehYAF4dbB4324I9NcxRNvnX+AgTROmZ1ub1s3A
tw7hvyPG4pFc8rtJF4Qh6aPEMScmwgtC01bwgx6lDCmildo9harWpSN+boQ2xVqaPMXrhi/APFLE
A7T5GvjlSM6+SE51X01BXs+KnvzsboTcSce464WPi5xQPpFNcmudmr72I+w6KovTHZHSL1Wa48PM
1T1vxXJH4v2DH9AGqb62PezKMC15bFsH2BEehYAqUcT4zKDeBBKICkhFkQUMPSvkYku3FlyRzyPU
Odj1LWh4R1V6J8E+4m3/YoG78g1xiArieIvPWl9Gk9eEmxrfgvOEt4hObLS72EEh9ol2OzlMc3yl
Xbve6YsYfVR+1YoOv7DJ/3Lj+iqRhs5Xcwn/QJZ8rerMGrsfro8ShMGfaSGBUyK8kxqXEuD1VgYl
nrnpbBtgUFz/MRodQ4GQ7f7p9fpboL7g1MIIGZNZHoS12UX5+z5jbVbfr+wvsao9N2SUy7TpgClH
QAkchm/vOGElKXmzqWkg4eMCebRPi4LS060CDU9H8O53sUkzL9BtV2+CwHlIfIbvJ0V9mQ6Vmzn0
veCu88nJ43dBR7qvtWS1ho4eHda3YGVtEB9V3HP77nZddG9QLTNfBvDn8Wigi/I2/n7ixhfKQYmP
sga9mK9rVmJ1UL7M5ZSJrCSAujUak+cdNEnlkxn1NvZGoHX9QDKBZmC0KBW0un0wg/7gNMX3iIkr
nMVchWGJDAZq0faHWQ+nEIDR01NpCjdmdLKHwx1/Jvv3Py5J2h+m/uTipQbaWNXvHGIte3jZm5z6
b/r62GIGupS5Ih7K0qmSd7vuhYs2XOKLhBLcY9X6gBu31iufhF7fg8BPOG+NPSrCUxvakzfe+rZa
zhuQ6STLUZ2oIIlIllZ9LgPFdXpXTzEYWT7xpGxoAW9B5PSr/kiju6e4MyqlzFKNCzBrE5LGsU/P
YJyrCJlJ1XhC9jaTydZzKIaq0LoDP80VSVTzWS9F27m+BVcwZgs69v4SUGklK+I5ito0Y9DBURAk
P2DvcTH89JBIVRnR2u1AgPDfqHJi4y4TmGKi+jPifLU9LJ2tBr+/jecx9EwG3Mo/pMIuk/JtlZOp
K0+5Fg3Fa7midHJKRxTMCRxnOpea+P+0GjnOzUo7TrJPAmA5/KTyipFnE0xJYZ4+ZsApVgZ6NeBh
gRY1SLwKzLcR7fVkWcT1uHwNjRFKTIH5EXH8d1lfm6DH33xF6tamIVjQ78n0ZtsGWzIa+rnLt/73
w/YjYcNDGPCztt68u8GIQQVJslQiulrF6drlXS+sro+5Q8lEJt2EDw0IONEf+IQKWfiIShnKBlYs
IAsCriElngVZF+XsokMi/l65IPc1ZQj8QgjzDeN9gc1OPj21Ir9JLzEj/3ylRTjMfSLam4PM7Fn9
W1A4asWBB49O6Ku5z81m5zjvOUkPPQniATie6N6xjZI0qrrWBTWYsyJFhhehOJlsuVIiBb+V5Dqs
fpJiVIys6hxWo9qpytWFsVq2ySIhXtEZD5cmzghDS/qjcJP9Dxv2rJM6idto5K08ehx9vZoDD9J4
aSSRNJ5QYzu6gN54O0knKnVGiZ1DpITrNa64c5Jo1NnHw/keuYsb11/cPxtzAE9UUsG6JIuzN8Y7
MpuXaruegckRjlw+oK4SAT9FZaGje0KNqJNhEFCGLs8wC7urLZ/xRATFo40FpdIDBWPMlVE83bBQ
ssQjsln7uL/WOMmT4+CTbEyRDGGRAJSytF9IBrbPD7dYUaDYPwAnTgV6+875FfHJKDXLSpNNmkrc
vtyls/Y8oGrz3hLj8Moa39n5mvOOr5rEOxvGxIiEBMLolY3j+n9iu9AvnCkHUsfymtKKHuBCr3nV
LBKDTYOdfE/eKmHRgqLWyzzZx0wIT30OerQMMW0Sj59Jc3+nZXsEWvazO+bDNlncSs3uy4ws4WhW
lGOGyFRySxTRB9q38v2eU4bKyB4U6zJGVCUkZtM3LHWFLXTL+oanG8cYjWT3vldgn7ra+7exKpTO
BHTepz794+tLnaXf3W7atZ23JITVC5XWMxdGrQIP+JdW36oHesVVJivnU7XDAhmObcoGo8T3B6b7
ujEOGaXKpQYa3DA/uPVhWr5uhsCuQgEPDp5IeXLpPBZW/CCoert62G/30GlOQbhi6CEoxHXGSsUj
6FiAAQdK2fAgZszEf1J4ZkzC71LK2ue1rLyp8aj3soH2nXgyGxn3kVL7lT7NlFN/HgT8SuhWjy1e
WCybEd5j839OcreMuQFBX0KTsIewEpHsSMO1MgLiejXEQXHeRvo817hYW65ZUIqmVb2HwE9FvhES
s6DiUm2PLlIsjNQOC4vZN3NNd36hhLKwa7r0SIUlH2KRgLOXSZ6Bq3qV2p2TKkgQ9C6zgb5yXkZn
OUN9KEDj3Ce3pkf++kFOYzEs9drCmdLeJUkVfSidT86BpkIbNPZ5fThVirNE5Fmmj4eRCCwGvG3S
klvZDepLU4mLWgNUjqSDo8880OcVf50O0U4+GN7vhg5ybbAkgiHVwqcWCU/l0sGvzJcQrFNBH7a2
Q9NT13Fpw7XrhkMDR4C1nDaBPnO4mWw0OLzBwGOS3LtqnGfUDDcHj2Xvw2E5PW0hy6L73Y6w7gV9
fgIPb/m4nvu57aoQyGES4TQsJv6vLQGDGFibXvgKfJUBjO/F4Gqh0/Y5Uo52uWFcqH8pDBaJtJcg
EfA7VBBfD3BAIXeeqc4bGntpOSkMBxrqh/+gQtpDlPZXvcWeHJFrVERUUd6QX2A1oIf5m7+za3l3
n+iLQKF3WSDPh7iG7Vr6U3LxOXNFFD9N8l22IMxVuGSI4jiOvkFV88vW0j5gfXYQIe12aG1U01U1
1i5baZcPpKruRFuLCkowI4/y8hivhxplUhyE9pKnXtBZMhWVUu9s/HX6ZKD1KuBDX8dJQ6wcWuDP
9vHSwhdLgXAl6sbPjqKDyCMEni6DqWjWbJ6A8U/F+U6dzjNp1kSaDaakTjxLZLz2axqjkD+kK53h
oQy25z8e1DYOEK+L50/G8TZ9xENhrzvSiwEBocNrdKOYnmBWV5wyIHtw3me9Rqz4wjLPwi5ezCz3
9LeSVJQuz0veTPPH0OsbCHS/GD8qdXRRvS1zmgG7hyiHIM2Y0tAzRtd79LGxaReIY4BXByq873IN
BVjBBbAMrE7vQ17Vo5/Q7ZBY87BgA80NwwEwxzBcX4j2JDZj7F8JXBps4MnYd/FVnhHhKnor8EX/
uzTiL+dBhTYw7hF8Gc+NbErZQte1fO2oS8/eBpDmksOHJD4cJYZ/F3lU3eJY68v1Sczj3sgsqnFM
SN5k8P27yLkiCUcj7LrahLcHftvlIvSChNS0KKhkYR6BwLra4CqniocDCYO7Yw6LDWRX4Td/rfkE
3QCDyvka4VDyRwe5xXIWK0D4GN3WP+xbOxVHtNygqfAsOIW0p/i9KrWsd0F5kVNom1GeuACYTzbi
r7TU9LnCHyUctNW32U1kDL0bBRFV+m44xJ66gB+0BnGB1W8mXpu6T/TOpOyUbUp0bcIHu7Nev+zf
vYxQ87ucdIjl7nfpDea6xV4HYamejIhMNwGyifyoL+kukJcn/Lb0FPF5SX2MHhIhPydKfkQdzLFr
Ei0vLxSOhIODN20KBnZGsp2yeUrqgF2OTY7Tb01A/J+4KuwR4tOVWhAvXy9Fs4YbJWeByCvy06zY
wxBhuunaE9ufI73ImT2BLT9ZaAKOMQbArIEIbFbYFwD7fRO9e8Llp85ASKTDz9kF2G2nQ1JRR8Ts
5QDcbw2+30adcjGfRh4vGnAk+Cd/vfwcpC0LhvmyS7ie7mZdwD3pXMbLcT/+F1y6a/3wpVQiHNUD
8+hE/s0Mr861+7jsNgaiweYWvHf5MsTByLTRSMi4QTRrtrGBRKLRx+pB9PQvO6/lEiiSlj+/oP7t
WngUMy0MH/KqKabztcBY9vYJmGOIQzKrvIoqDqILE0sLjMLCIVK7MfosCMxE7mj36IgRJh4Xyiz2
a+Z+aTQmZqtA6CyosxwAeOwl8byFCttkDPYooabpWqM8k9QDnlf4diARV6NKs10mz9/DgzRhiypz
NK1iPYrWrCcDjDJYpoRZys4zqJOFUqbjTpq5ZylJqUTqf9Yp5Q3v0EtC61GSmzGOcMM0oERpHvI6
MSsMgbDPD8BJPWiZsFjnD2mgLOykChT0a9cncJx+I0zKN74lMMNT3KKOBpyz5Pfpmlvtsb9cyAea
gvJ0z4JgT00PCjtToSDmjG3UsieSOAKbojhHhJZqyXKiJCUk9Q2cHtDU0nzW/cBYT/rnPwHQLbnZ
jB19kUBIxyCToasq8hwvhR0b4KGcSrVjp6tzN9acoHCzDvki9Zhk8jlxc6gf3SMEuC1oivIUtbxP
AsdbucfZ1NRoQ2RX7CvN2zfBw+bTsoe95I6NO1scGxD6y0GyfftGy8sSsZNuBD1hw1JCYdM6QSAl
97vPeyaFukP/B1Q0rg+gG8QtY+pGy8cIXAbVzcsZJhIBTNRlA54lT+0kLom6YgAAMt4z2cq8FfkR
esC2t5C8FQ+eGtEHeU6Q2hKvKY6PLTy0PyrlLbQjpP7L5DWfKwf4vE2NfU69C47sFd2P013asPjw
I6tmS23fQLKtuVwWPRd8FRuwKfShpwiVhQPkwzNsW+HRaDcbSFXt4DCfTSmBVqXmJQmvGPMVG1ZI
NN0YERYr33IIERM7RyVgDAbKgt5sTRpg5oer30AXALdMr28qUZWspdp8dzcBdYwKBUMa2d7oyA7m
BKXXw1pM279CO+hMxA2/wX349IGaVER2vhTrL5uaXDFLLmOzwdbzorb6HAk/i3BcFt8zlA3sj8Y9
1NKES7qd8n22C/ol8feWXo7eyMy9AoI41Aq8h+fQSgKYWcvcE+YQfwfxH//g4CiV8rmKy3kGaqr7
u9JEFygYA77vyrsnTgTWg0RF4/bXLKNdBg6cbTWZVaLMn+klCA0DlnmXAB1Bls3jMfBPF514P4gX
d4QN82f8HSCElploJjQ6ou9ZiQfA45GkmBndoH0t6jLAvlr83xN593rk1hYbbIACOimvkIRoLzSd
LODBxN3QpXr0iCQaduDCiHRF0MHHhNxg80RemRfEkKfs+x5YhH3YAgJkGKFPAX1X9MVgPEDnAATc
NIzwJKkdTUC54PqKKHmNBq07Mm0kNXCWl5DwHCaNb5Z+hiVgtlZ/JMGfpE/e7Jy46AhsSGGG+/nd
8zatPajUl1PVORzQelhyck7vliMTL3vn6HfQ6UJAxJSrB8AiO6bAFN6DGEnEYkJok+8YL+d8N9lE
2vvpqRfmmJP1yKTqY1Gtx4O3E7NA9fI2a4LeHvKOqd65Bhj+GeGDnBP9ukNvdc69oHTirTWDvovX
YbhbytT7ewGd8HH2FJ8sW3J0Bnr/9bsrwLnGj3WWz7bgr/7GWlxO7cBB+/sq/1O6vFh8mozIG7LF
RNMCueQDwzD4V3U9ixTMg0/87+HN/N1tn8EgYClMmiFH5EYU8OKiwf6xrpAcVEuVIZLYAkBTNZnF
v40zcTQLDflqtWYrgn+9zkukpN3ljV5Ob/lNt9kN3v6CkP/2T51uRK0/3wS4U+FdqugN3sokLsBp
W2Sam36Z/5cRMXqylxVu7aTQJkWZcTomP87ah75OARRicg5wRIkBIIc2SNHsTvGr0OvAlDfwwOHW
xRnipoCykH4/xfafyugJTLskmdt3SyhoCyuuRwsQvZoQ7C6kmYsI+vQLFF+dX9lCGFKl2Ff7j/Fo
HBpJZvZETrLq8qLgkEiHEyyaAy5rdSEfIHn7slhfNB3exOJ4kLeoasAFCizvk8unfA1dRmgl9LJS
/yaN48kTYaijJdlJDDG6ekynVyQv9Cxdgdaj1UbYWMLHmZrU6eyyvVxr2/LcyWD75pQrYpuEvvJv
7a2hosbSuVqYd6Sq9lwyqRCUFdGbXbBArNdiWCik4W7RTCvNUmzVgGuJzd3nkEtd4vP60Iy/hn40
76Gq9ljY/PjJiCGUxyehzqVzlu0o+Pl6OPQdz7OzOj2s0MasbT3wWTG0VotNuDLi/n5CDHwEIzFQ
mVHRvsqMkMh64/M7SbvJqJ2Ia7yT9mHtxdXXIbDtWDUQH9raUvnzRLYBXF75YKGJ9JJYyoQUi86N
9Lj6UAv09fuMVRUd5FjJhoRfotKlrWjM242VIx4pbjRugJe9JLfICPgHHFo65wpPgPrQGP45NhiZ
/e1tinDcof4S4by6XkHKijzicCBueT5MljpwBvAhhvWPjc2OuwIc+mnIXaVQo3oS1xhz9eIztIvv
yiRp1sBRoqt8aN2IaTQxgg9HBKHDlv9nXgz08tO1IREysj+6W1WyLEoU0HtDJ2XLeqDVpLexjlhU
pG3Z9fGJeG41np3y6/jKX/II8WDMlB/59UjesgJ5O+5mxGb2owHmsBCu0eB/1d0oq5QK27XlY+6Y
uzMnuRNMDRbLyUVsu0ipnFbnmCCo5tuowZI4oxZrDGOOqa4aibxPEuaVFZcObosr6bzGfDr+PEcC
Sa+wPdXdd2+Tk8Ok2ELQB/AOvIkGTQzEXs6tgF5T/j+8UoCG85Rw2jZiWp8mEZC/SXm5eTkWTx5L
vJ0MT9mdPwLgirNLbIh8RUzGT/6OQFmN6/Y1CqGvyZukj7Pihw4F/PZnwAesw9wLNJD3faG8GHx3
NeL+DE0SOBLOTsqSq/7ilQ86zeQhJa9rwzYeGn+IfAs4GzAeC52oUdgbkJUOT9bcW/7OlADHuNiU
kxg9kgMwMvNjIUjTZedkxnzbRQfAt/PgpyeJAsC1p0C5eIAgYD/Zcs0YlKwcY2n0ZFaertziofTh
L60ERAJg3bNX+g+CZuqLaPlzNCJesQiZL0QDBrxjwC2xE6SHefq4MjlommTfLUpeOQrQ7MukUpKx
/t4LvnDhxVH3bZcl98LQrPwvyBsiHUd1EMtVIfwbul4vWqPJVqdVEsaxnL+uloDvo9vV5KZh30eG
KDQ8kep1l26Xj23NASFBxLEDbpyPoNBPdXtJhn1/1T2y+nIFAIjExkLuIzSaS8FoZa+JTk/G+Qt0
TLN94rVBDI6yiPbPK8ESijv16A8+k1jrNhcLGxflWYxmEm3CU929jrVJDj5kCMi0T1ctalzoWctP
2+wzDwTQTGn/P6Zuymn5l56J3W2ouE5gyBujJcMAe7Ot9+gRayz3nGRtqFo9lLFMNANiEOs9y4Ai
aFumtT/VH2EJBvucfi1U0wKKduXqiqbhYUKwICMTn1ywjCZ93NnXqc3a/xAIy4XpXVq/tSxYQy9L
pRRwAfs4F8T/TNJ584XRmjKZDazvspPJCIeGYxU3IOwZZ7MZ5MxDSucU6PKRFzqpvl33XzLBqbq8
1LkN9ld1zoYQQ0f5J3iIV3TK92QgyQm8uzKFRO4fRF3okK3a8y/3RQ9fQ883BWw9/ZW2dkPL3AbG
zoahZQLaJNnqIqQgDcCJRQXQpjNrhLvpFxCp7qB3cAi7kjcATZzgg85xaPGG5Swdwv9c4w27bVsf
5JDWORov2J1/aS/JByLtAqJtpG3fvaJUkGpH1lD4oht0ON2GanJ4+N+6wL4PiZ+3rgIlrYr5P97u
URq9zAEhyV8Idlj+l56eRx5f8fZqtFnQv1iukze2yX1Bl/FjHvobFMnbeng87Fyc0rkIUSnh+QMw
I6MNpyRFA3YUcBkUC2DZG8PYhvukVxTnfTXE1qWKBzqqzVaMEdx59aPEeQgaTu8mUYPRQARw7p5A
k+mca+EGjRnKYXCf+tyKdo9LeLcG8d5dr37xRpQ3jhayliRGoyO078RWRhyhepamfosAZSFmShmj
Y1nGfStK6Kk4H+Y7kvMWSHzK75oNQirHu52S7uXZhr7ByDnnd7ed3G6RASV/ZhROwYwOvFM7y+P/
Wc08ogWz1NCy0b3Z3suOy0JEfza8uOcFEmahOJckuvMnIKIJyRdMPuivNO9y7a3fSJGvGVTczOnH
u+fYhe7/3g866xVz9iztbPxscYy2FuhsQGvdu1SLSm9e/DNr7fNaJnEA5/1HFyTQQJBsEvAaBfiC
v7WQ9NHbrqcs0QbvYkD87oleEmjiSYcB64K/KhAs2QgE686B/h/OVVeo4O4wW1XCoZ9NVW/AxfHj
1gCESPYZxtq7jarqn4V8oi7nAonqHXnwNaHYrX58hpqD+x6Q+zTHroPwfThzm12yJS0VqKa/5dL4
d4y6l7+H7RkxMJDShZXE52LRcTKckZdhOtJNI2npPZvYk2I4uHgJ6RWQKIXpnfJr7Ynxp93c0YGH
skyi+x/fuKMnukQ0EdH79Y32cuSkV36t2mPV2gcKGD7o/DbfvO5iFtrK9aSiCJbmg6Kd8pDE1a7L
6dnWW0uhsi2w/f0RFDWAvS/o2J2M9/1QjLY9sCLo5lxI4Q3uSM4yDIm74B/o3qAjjdZfssNS0RPo
JbwTlpzNPUDiaHGTkHjDJpffakneBVEvYq6eCvgMwBgstUP+laMuFpTFXp1xjlEJEeGMqcXsIuS/
S1K6c65ldY3f4GdxoxtlhcyB9OPsn/7FcB7NJCGulIaBvRXiqeDmCLqV8p1dNVzu2HN7g0cCaeRP
x0pyepomIRGuFEqfEEPLlRjkLDIEi62CzPixOkJpiorzvFievcv45Y4zZoedaFBwbGlgb1GncriC
eg1OrFJhY1pqfTSU/rZRSS52z05KzlvXHx2HOU3nzsFeeLR2tSPkz+qyf4mpY4zQKEqAmb3y0ynP
XdsOI6RAao+nYNImC6kJMXScGFx8WpXeOzuufOo2vGUUq0aUXRIXpgljs+hL6IOTDeZFV3TUPui6
GXlwBV/3oAMPwgRghUt5u7iDnUsMOJ/JbJvLJrRVbTrjwOdlO3I1xzKaDGGc60n+G1+p+A43plKG
cCDySOOsEOlBsS0R1yTAsAvNMhkGOSXEhp06KTh0CDOYRVbUiLWo75QJOLIInX6eNssli9YoB5zF
ixkJ1ayYDkMZ66qHZG98ShdTJpVXUMITWTgvqzJgGN8HvVlPkfBskSSABO2+Sr6AHOa5tHZ/6wyq
dAiMS76WKn7TlYNAsKCf7vImJYjNzvyCOuPIvJ+1mqbBd8TA0TY/QK9UUV2IPMR3D4wpAKEcql1J
4+3+zI4aHaBewOPS7k19RhPPMRlMrGVdWh3J+qMp9OozN0+2jr1tMjMKM7OvK5jrDnOVpBeKM8qA
D2R+Dnz+VEG3wHOoYIRme5aqKSv+UL7qwZSkFkVcZ7dWo1YHwC2QDJyHLNbuK2O+2qhFk5lAAoSk
zIGO+/WYTgpbjDIdwwd+ZrKRnfmZ7u2MYBo5/psmXXaIh8rxAlg98v+IloeovtlY5UX22vO8rzvT
VRVDzXsQtQSoAjAed3ZHZWpoibCa/6o4kb/5dexjDG2Kq4peUmC/4JYZXBxxVny2+HcpeI3Nc4ZJ
w2NUK6g+EbVfHGsb/traBSxS/z+xgI3YLBxfms2eyCMGdrTbzfWRiefmMwdZeJ8Wm7kTSfASbseg
33lRzZptLDBMWFqvTDhuB043kl9oXTDQEmC3GAnOCl5iO3Vv0L8vBs7B6rJf9E1IxCadZlav5T5s
1aCuPLx3JqJ4xsyyP4i8vSBUV2mXTXJLG9lge6+7Nm/6Z3kgGfDygNRnCKjb9xorBmdCeIZ/TcCk
GDVedTEMXOfMNsEFcP6fOZCoA9ielwTRRgSai7fIwF5/u5M/1sfDwfJVa4fsaBEka7c7G51NzU+X
SptqCNtYX3m21USx9uxfIybFhRqtAxKtJDxzJTf3t+nxJjqtW4wSbewkD3J6FPtwgQcV716JIhCW
fIq3Xdc7+VnYFuzLP7rKFSjEZHYfXmQrQ7Vf6zX5pPlWqzR0X9IF8vRhnlPfNPHd0pSc8bue/7bC
zexDpxWANT1wfckXPzTmdLcMgopnChrLf2KdCvZ39o8+d2NuIfnNPbfJM2VlLV2KlYidN17z8f2B
sPI+MrEb/j786Smh0y8OLxfJddVAGRXMBzKm16O626zFaI+7ZUdvFsiDU6h0ANoOzUCnG8W1QZC3
73phwTRSDZiOvem5CD7tZXi3JdYaClFHKukP8qiDgGeFREye6kLzj7oImd4Qju98NvFLuWVLcuZ6
nntYxT0vgDhbCPeiXFWsiI3qnGcP0iG4Lg0serzJe1oitox86tOEwvb9QXuOMmoCy+wm0HjBoWqs
bJV8wJzjdNBZuEt8D+69cd4vojKPT56qlurgsFRZI1ckoo0I/3D/BcOhm/XISIJ1vXXqrg0VlvfM
+yTQe/0BdHgdcxoll9A0MRYq2WIpftdqzMHYL8n2ZnZqEB6Ud7544i3uxt7spKw8A2DK1mmCy7Kt
t1rJmxtUUZFm8kHi4kWCzRukc+C0j1wPMpGCr2KQOvylLRIZLts6mzC86hA1cfAMaaW+cSWvGpW4
prCzTC3ZUl3fQqZEKau0n41BxHC1Wx185LP9ehU1Ws/3YbArb9TLkQz7AcTfn3NI8o+nW/AoVhvV
LewqPYjaxWVkHCyz3Hm1oXFZ0hT4IqmXjbF7KN5kslnGgS7GdL5gi7BakM6jfIBvHtfa+pUYOZ0b
VvgA2fi5bps2PpU3GzlLvzOgZf9jaTu1YIzs534ckUfM9CNnnnH1IVWey16dceWI8eyZaWPILc46
k+YL9oqWNftSUlsv5bjevIsDv7hiwmHYpdbkCh2koCnmV7SHku/CMjlFTesyqWb/s//Ev//1bhde
iu0YGYlQHokYAK5XWQ4Bet/PfybT1AORzwpnAuPLldKV3r46KbXW3d/6Z4P9rkTl19jupkP1XXkN
qkh9VJFjY6LQYfAzHxtEQ4X9SZW5iyYb4lbWq9c1zTxthhxu433NTrlgNLaUj50Jg3P39PDhVGwH
IwK1YtQmAxM5gGbKEzoHjaJqpjU2lbyuNC+8IqEYOxt0xlB5TU9Mqbv0R125uYTL4H8q8YP2aZmB
xUkWkYjWHEsPHQRYSEnVGFzZBe+3dOPPV1bY2WKcGVNKq3IdvXPs2MNExicnSPFXLh3R3gOmXCSn
WEdOtOS6wnOyaReFVz3h6/BBl2R5lS8ewpRZc52sSfPkd9c8lox1MPptVidTcOb8vs9ET5KSraGh
OI+ZXJ55YNL166a9jh5NrFa0wzNU4Bh8LcXFDnFJzBTn1DK29u9+swiYY3yaCymJtyLsh0jWw5eS
Y3QxBNzyoW7HOJcwEuUdHBzGm2oTmh0pObI25f6ZXc7utV/5D9vJhhnEuOHt+UfNY2oB84nujtJ6
GcNiryWhh/jJEojwQruyXoOYjb3SF2cFfyfog0G4xnUdPxqYS+xLUZRxu4/KdGPrUjCM8gY36qRG
dBN1neky7nHfW03m2059VY26A05KfMjeMlGNXoZG7anXYoOX8G6FKmmfscp76N7l8sawslLZ80X3
j6sL6l1x2v2M0k3CbLsdWRpoW26GuA97ol7dw5om+12xNzXzybQLeyHDJd4OERLO8PQLmQHV1INf
DlJRSAL3gxloJvLxCpRNY8zx57rCGtbvxASoBZfkBS1MGBcNXqbfoTKyJYEgZOatLmJ/z/wLW73k
nYgF3qRrv48gJg4EpDmbGd4ubn2zFScREJEfr+Qrxc6KXP8rzAFKcMPSjzgtmr/zS0o8bEarwx5J
G0L64MODcN6tCUKxrtKOdVZvxaG67OtSzx537XhHXLHlEdd4W+DKwxkvE1Sv5ftuf/r0cIG36BkR
AqEiaTRrSsSXh10JRJ+vDRukFR52iwYSe7oM93ue2X/ZiCwGKGtJjghh1cOfV0puIS/IFh9R6fos
eaGIACX4iwcuZoVrOH5vp6jEHjA5QJU+09PNvY6LgcSF6prS+6KPndGXznte9fUVdyZPnRQ0eIKz
nnvDhBNNCC8f8rkpyUPBF9QnOQw8j4Oz3PT1APUME+MrY6dk7EEYUKEEwzFNATtRWfveG/a1/NNt
VHQ8UBwgZFJhehl4UlXB5xw883SvvITne17rHzg2rrbKkFDfRkWnZs7n8pm5mPTaC3IyxL5Q4sNW
o22V8mNMMkCKdbjo9HYbZX8kKDtyiVEKofBpG8m4UWhr3vnk2rBjajEb5MqYzVKmVmiIDyAKuSJg
uaFwq2zFXAawr7rBnnNa7KfmyDUsaTnvmId0G6ntTWBBMWWqT+Y+m/SjD00OyuTdIsE8RzkxVz1y
XnQuf5ymq2PGJOBfMhT7rKuQgYJrdH3MzjkmH8C/K/KebgcLq4q0FM4p3kPL0BNetrr7jm4l0f2K
e34WnwkcL8gcKd+GwNFTTjkZc2WCYj9Xb0G6G6GOk6OGZ8HwERPp4QOGo3jqR/+u0TSHOelPrkmc
RaMP91qNvZh2MS9LLA7YSFFnESem7Pa/D2IM5tAoP8Ogh6pl0U02dThsh9UWM/8sdSqD9aV9QMvU
BSKlKIZ1EP3I4Pf77XeNcPPywWkJA45Bigr0Dn/Y7S0HQAfwpHNfdzG5jIfHzQ9sWhems4TWD58i
cXnEl4xDjWhMGHC/ICuar3eXx/pv61d3gDYeneFXg8DOnDUqtinNs0F7fMXFyoEMNil3X3Pwf9W4
rhRU0UImyTnVfpuCcIEmgxkS/7+rReSCCk6jTfofMowdQp0qFE8iOrxe6+kevMQB6YHdnnIc82ys
A4B7KLLBlboqfHiv6GIxq5u3Yuzw6AJOTQnpdaejwVgxPLoR114eFquSzReDsFAohOg0fc6Ahyvs
7Lsxofld1G0nFgH87E6v9dfaZkyQsKmLRQATSjzGqKSp4ubELjR1PUVtrniLnmPrxhwvMVEsYR4Y
65VAXHw513S+1cVH+IPdYKinCTxr63NSVGMBYjLin38791FM35kOQRU6gEQicD9hp1vJaH5m/Q1B
zQd+kLuGk+f+9IFFfuzj4W+5/aOdoFhkiKXc2Iw/WYEt4MAxz2Nr0HJf2L5ekh0PpLfot5gyDII9
VyEPJ437LT7qQIHR7XgAVoKmrGesV7zHXqJwog1W+Dv5MzNV/hZEMeQEk7wstCm2+B8Sj5Khri8X
5TsFKH0ApJM32dJ33Q/LEaDTXR2JECxmIinNepWN1XFKgru3NGqaSspoCyv4cOFY5ROL/itnwj0a
z93S2RSyEmINxcolETgoZ7IHkVUYqtnkrWHrcx3fE/2//YBVeht2cFSCB73uhCO+eYgwOygZdkgl
6d8+xCYqCRKIgNy6lGdjskICy9ES5HgBizEFE4pvxEW4JsTF42BjMA7RHYXBWbE6vAR4Un57nI7t
7TG5/+yNyps8brqnSxF8wyU/jnwpPjrF/gRZOqdr+mCytz8O68bCJYU+06P1vO1IobcvsWuY+HQg
/bQ4omAZ1q7wJkIflKpBnPVLHTCxkcbJIdLT+CG8wTh9ZVYLiUFTNKfnbUdRwlMzDiLvYzEM5E+S
JuiTHvRUQcz0gQi/i/IFnQnmJ6fTapsX0+W5fdeoKePGmJfa55t9eiGh3c7rvLfyzSL9ojtnImfg
QjKNSuGdrzUtrOlQd1llrisBNe+2s5bZXlRL2562CntUvQIz73SoNauBtlfA0kY2b+b0z3+aY7xJ
Lcet4IGN/N0jt36wBv2BHCbX8IDqfsE22o7uyo8d0RyZbNJWizx9P5WZ+z7EjbFJelj7E2WI42Yo
gLstLtjVKTnpBOd9/cB91sLJb5t+XDrspRRXmUCE9pDCACcRevP/sNMzAtWPOwHXNp284P6VaIJX
Ga+4TuAULfCP5N8rT80gI7H78In1sOhe58WXKgaVy/WNmJRycIyQDjMTmuB6RZEsecKrCwDRVfuX
1Yx7dB1qQVn6+vMy58dTH3czuI6mxswxg8aiy1Uu2hAyXiO3IO4s0eELL/cdQZ7FX1ctoZjBMqSb
JJXiOhXC+/j3/YHWvrfKLMi7ATdlwvh0HI+1rz04ZePSngrH4qCrHaEWLp1wy96WwKwn/u6XNxXK
HIyc5JiUili1ZszP2b+EK3nqLYtKce2qvPVAWpurS2q9vhjYB9wzqAcgZdWl5QwVRQmlXL7kb+O6
Q+9rqFr1WANjILfol0jdi4FnqGlB1E8XxmzlUH8qixirlpaJdcUoD1njSxcCfsu+xJbOtZrsNpzB
h/1VuXGRZ6IdASuM1TC9WdnOGtWrE+/reYOnhXbEg+MmL5AUA5Fr9TF/ReOci5qgMd6Qxo6rPT3x
ogCC1w0j7GY0DzqksIw2yW8CKNkRoJ0oxsAyVVALVVsU+Se2tAjgLYqwGOmxz3nEYlnU2HUtSNzu
Ewo+dhj3tRB16Qa/lD1EHgXM8q4cDr0cqxP8MCGNcxQn6MpbBSpYe65K2RAG/nL1Ry6Pmjx4C+f5
Cq1Mt3Dhfm7TIQ7kJo0etsq4eKk/IUaXJkQ1BDCA3Xpfi3eXNGiq7lTePs5v/LlHznFIAoPTHM2C
1BMHoHU7Ja50I1bfK08lBowmJix47TyzYfcbgXZmwGJ/5ewrD2dzSabCTE3Kmp1ItFPaS3dP4EHQ
NZWVtKJA2jdLmiRvjHNClTIQ8NmPUCFfaN+VbaK+7thcqLsNsqID/AzxUFK5+jX+NMnCado/0CCz
dxYIPpUpGAHz5YVuq9IKkLsfdXClRb1s4ytIWhjRstqNHVk3++l29Rb+gFgI5KwrerCMM9t6/BUn
U3AXVX9581RcIgf+SuAffMD0paUWn6dqzGTX5fdUhGgHyMcs/OwUPjNWTQTT9DEkLL+RQ+XJ2ynf
FZbrB8EX482yTkWzP2YeraLc54OufJfI6MrLejvybXAlRCwvJFR32xeVvzms6xunaAJb/w7G8dcw
oUDO2rZdcnTnR6O15S1F4urN2g/rnbrVaXkGc0ko4plwYKYRfjMwpCJ4yPjwle1qNt7KXwxwL0A9
SzLIF2tJ7+TgO9O2+OzwsuLZ9krtOih/axBWU5SJm2IY04kJQ8mLlpgwj3swz5/09qyj/RzLt8br
Nu15yomdwwpNGYSt1g32OYGwFWlqyprz4PmdxyF6cQAjo1KN7itC1i0PuVnWcUx0j4KYqL6J4Cwe
gRz7Dlf06bk1DgfeMI4IeugDjfI8R8dZme+ywfVqsatUWc9P3X8K56c3b3IEEZjhjJd/mUzHkNFw
vMGNdx4CqrjUB71TvhdFc7F00B1RvDf7ZmhYstoJXN9QHNSK92OKminD1sHh07oNdYNGOuVh35c0
jTPy6Se5Gy+ojEZxU1XzRnXExmtTvtze7xKCeggahPJLfXTzOIVhw3lKvHxC+oaLBeKPk/YsZBfM
B0v3iMNTHECxTJjBXW/4aqzz3tcVfcUJ49sFq3VPXp8C0sg1x2GuRQ5RB/pPFrvByuI7PY7UlKcA
F0wYZUJHg2jnrJuvJAKfBNvSwct21NwPmvj4uRZEw1wiGBDfksVaHWkPhx/sOHCLkQXlTxLTaXfw
3rOeafk8g78mU5RLyb5a/D8I1Dx87dNO5iwC2e9IwmI1w4CljcUpVFKdR5dC57pqWJFiJ+dFI9Nu
GyqSYhNa/fRfkQJ9kRu9OxXyKGIBa4bXAI/ufnsSxnEn9vG98RP0WizMESztOHnEagQlcuhmNkcG
PRgp7sAyfb+ehaawA7ygDIwwdv5Rfd7j7sqC9dQi7ZZR6zQAVvS8LWa0wA/udWW2n6ytH4Pk2EsB
UdB2mOsVyw+K0JoyyBZOqPEyXzTroNBWNen+HlA3wE6e+/8qM123EwygEGkHoVbHIIzQKDPWubfI
u4AauGaFvq619LBu9Sg7XbSytJaNCiqG02sZkKFN3w/UWqmkRdwry+rBAeMjVzfqBDXvawFPvCbt
fUY9O3QKfJJyQfZi4QckR7/mRkwLI5HNV2Yz573Dnmv/51F6wFlJ1n1E0zsIe45a9nOA3AKQ8Rwo
gQvTI83r2Ua3aavwmNZ0hUMvoVfkAW85C+tQIRpZJbHFrPIyStwXo8pfUdjuoI26CJ1UYebH1dVk
la1iyYMRD0VOv93iiUwDapvXI+VuKTVMkjM6x+n0jh45OE5A0u6W/JzhfIPVPuRXrKeuW2LtvAuP
URsPA7QNbv0TIpB09jNVdUZMK0CRWb9Ft9xgYXVfnLPCt2D9RK0r1JToK0CF2qVbphu7eta+ctmy
IH6gHVxspmDUwiQEA2u0DiIXr6D2Sn3geNdMuvKngqR0bdFdzNYMkFYYeOWu/FBDnyKndGrdQGWf
+KgAIhh4m7R+G0sl4LogarVx8SKnu6cZtv1KjrVhMSalbMZ3BILxY1PjaMCw+NTEwcS8GYf1dAlU
NipzbjaMvWGmahQwhUq907Mz6GJfA4iBy22xIpVQDuXWPem1mcmvO+kzPmlUnw/zXLmQnbcO/9FI
7gTEBp/4a34J7e6lVX6f0I52/Ly1Tgi6J1fdzppiMy8PXmWjpIB/g+25Xvf3A3foDHnTcbMUSkwP
+2ZUNpt+HsxFLNQeyyXofVEAAG7Jz1ECpzQPAjdXNxdDnfcjpLIaMc64dONHs/R2qXcU4Ufg6GhD
VBbN+jib5y2bmNoAC5wbTglvaiyO1kTvtOAGBtoGBzPElZwHPonFztzU72SAOVR4xxND9CmrkChG
k7BSkaDBAS4C7KTtGSEniUQEzYkeVTcvjkydzplT3ID8h2YrnhCXrzbjNikQ8haAMv5m+FZS2nGN
YJt5WpelgFXW06+Eh1QouFF7VWsH6GwNsQI4xuwebzekRB7ONGDZyVu4ase9Uo5fsQo70ZanlJ79
X2hJb1sSiQ89qtkutEdIECtEwVq/inM5FSWp36zv8DY19ZvB6bChgd/bLdsLyedGxqkfOXIrGg+g
7ol+a9Ebv93ccNCwJpFqwCvymIJerY38xSg4Z2jIhFLQQPaLD7TqpbqQgF4aLUpORRtGwweYxm52
b4026ALZHThWGUmcyQg6P3ypr9oFpzDDwlBrRT+EfBNMPOEGJVRq+ss3lOhiFfqkpWWqzfdSP+Q3
0qjk14vxIw4pihkAbPMZ3UlFyHT/wya7f3k/pXinfY1KxvX4Hgn0JnXsguhB9iOL+q1t7cTIoz0P
qjtTt0UheXuuJyJF+zgmDU6aaizz6+E4qxr5Z6uijCPfZNWndXooxMJSrOjwSgVGTSK9dutT0rxf
JMQFMytA+rUZlWPeMmX0yXsGXxd24z0bXs4o5Bf7HHc/sbdPjgNL/1IAMbG/xo0KLsJy+JCDCcGj
RG1pQ/7YfNzB+pUfULUsYye2M7T1zUROIywTXtIxc/lM7pUHae1RHlFh/pembnnNmmzvvTs5phyc
2jONlJlXAHizDSnIxMD9+WLoohY9tCS6V3w4o9sm5B6rymJc6syg0KpT6JzSjUwYW+KsVCY5xZ4N
npiTfzeaKFvGbq4DLPT3VdfitLOZ9EryBFL9f1gjClpsvxVN8NSfATrEYop5q0RZ7Ir634gOcL+N
xJilCnMBaQaWl8GQXA+AKX+/CzcRnl2k8A3oo9IcoVcJcwYUMBxNF8Bq4V6vflajSfR2i6I6YYOY
1voEalyVYlfDOf5QRF9iBZxbahagDwWl5lR2wMbtgD2EhSv/uiD2jjCiVIpn6isVSgTQ15FHM7zw
y/s066DDFO1oE/CjkRlXpOs7Xs7h0aYS8XrhDZCNUiq8MM3+ghW3QbVxf1vwLZai05iPvNCpWA8x
ile0ptTAiT9bcU/s5qMPIV2HGWE8ugmOWkxX/EPe76BDyBn4fnYPBj3yldt4esHgWLiJAyEaY+5u
jSFSio3nB3j0LmO0DimwOvwFl3fvpVYzIvQMk2VQg/4lbgja0F1gPLor2svgGu76NSbKa7ycjybl
RF3Xj+hM8qSfp+MCbMQ/LHLWqpLouZvw8A+wh5/OUUWS0KLmb6A02PPoUQspgcSYjWJy3Vj0Iw8M
v7LEWWP+/1ujMXnQBkyFnL5b/KC4923jK9TPG1Om4C+mKTY0ajVVnk5lNhJxi75xF5CXmD+NdYYr
UPBBiIOW65QAkBESBFaOrMsxeVTNkpVmcOt0a2Xp5lOOpHh/5zGN/VDyJ88buyHSEgRS2VtWOc/x
HzvvGZTBl8AJ03QQc7uPsui6Kz8p+zCJLZRzK+Unzx/J6GZp2f80g1TVbgg0Pf8sGE37f+CfIBOW
SowgMkVbyykqxPkpVHmD+kK7VXlE98yg2U91FQArhzRMt+mPR3GvvwP81jKHC+6fO9CxRWiSvnVX
fcZteLh2GU8DZO/jP/edYp3woF5Yv9Sz+seXWqmJyJU/csd4g4k5/JPJq0t5POlEdKhPS9cLJcSi
NTfOOW2sf3QXAT1AYp4KIb/p4VhAjgAFABBLrb0NZc4rEY3Fj5xIfnyBbqiQv7M7jYvifcmgnnDD
X73veKfjtDc/Plyh4Vl0Pq2qXCzD6yLtpMRPS5Nso2PBX0zx54+scpvhLSSczmGL6XBxtvQO5QMW
LoEuxKUNYTNC9r+RaIEYc5AQpNKHYhXFS+ktuJLs4UfYZJhdW8R/W+E39/qaNKaBBhhgXeJEviJa
fnu6DgQNaK6ahpUftQqeqCtJrAnH9lzFOEBYakgo9fUlz+c8JmSUcVZy461zIWRNOxu5FwFmJ5EP
Tkq8DX7w7oVoLmnR1IRCr4/OTbGtKNN9qMGikj1M2mjPlQGhwW6IUGetk9XClNei6+rPM84xV2T7
gEhNw155VVsyyevKYwZzUM2ZCBHyAB4G+4ZYS2/PlDfkBIgCTQmFI7m281BelZfjjz9msoB93Nf9
OXX9E0qkm+UBO0iTRsO/cffPJWSO74P1xNa0zb8tkR683LfnEunLumDvrO2hd/ulTTbiu8fsoOjv
qoj4BUxLUV/i5qiCtCBD09HKLvqfGp5NS9R7YHk1fH1fWS0WiiU1534MCU7FOQpEVhSgteDnqvwL
b0acpqG1cDQQqJKOrMNypEJmaAQ3VzS7DgI291FVhU6YQKU8cilHgSLLQXi6JuT60UiU9dmtHBOF
QP5LaxdNpATB4O8ZMqA0PJ7lwQ1w+h4jOJmk8W/w3KG3XV3ljKbHsoNW1kmVoo5Tr8n9HZJTHs3y
OV2LvFP3xeo7d2ViaCa0lNnL3pv03FRyC09doW0tw9GU0S5ggu3A0WExFBxjq9gBuP/EX+9IE9yg
ugIk0eIey3jYdrJ79EzVQjmOlw3nnERuJ3c9cfC74KqqrkfIuvx//bgFgmgBJXAHDUPRgOJ8/rka
ABrKJ6aXIkVzNOTn+/VR5E7MXsNlTI1Ehhn0YpKieYt/qQc2pww9/qZrdRkj1YvmqL8rpy+tEkpU
IZ02KNl5ZUVHNNwQuX9isT8E5Tn0d/AjtJckrvAxJfMDj0H63ZyC6s0tFgGZBru+fvTRItJaEeuM
LggS7FWj7K2MHzRyH5Vwaf+mK8zEb0cgDVxCECn0hoN4VjF5BvehH7RpaHRsH+XkkjsH4QtQN3XO
7+/mvRe/j84HAlQckDDJ6WyBj77z+5CkPJrrw6aQy/EkSmN22mA2NTddYT5l/aTzqMvpzHT8jvfl
ygrkd8fmt8sALi0a0oUcFr5Nwu2SN1IE8EDyuX56WsavplsscKUf6UoW0AeYJTmTaiqDLJJNv9sL
KoKRIJooAGlBd0aibALXOVro+dCUBkidmQe3UAbH6xvsLZYQQfXTXUyNbspcVfWv/ll41C7Lj3mZ
gjHo1fqkLsa7JJBpGWLAZqwjf9NAEP+HTIA2FJRUhK0k9MWYWQWWo5Bbx+kkfbRUi0ixM/g5Yq7a
wtuGaOjMipDMxZ+Al8g/ObqhBaGOKtUXHosPJQnzKA8N9JzNZOBue/2YW9MC4D9GCzIN+rCk0ZL6
PxgIclv22Sbgj4XTbqN2p1dLUAMZ/LJJTuboVEn16uoGoNDHm8DjyTxArinJpGBW2QnCxLWQzQI+
2E5Q+HF5mYUF9C+k2JTusdzmyL7oas/r2gV0yq9rsghBGPZ/pNUDRiRJ27q/gCL6uwPmaf5OjRrt
c0zfd7CL8nYyIOlNccsR+WrBEkhbmOfKwkSZIXWWwfygotN+L0lpUHNZ9g66S/g/pLVARmjT5hKL
aXSXXoUx7lrf8ofsgxOr9lruVj/c7dlTBXhZCsG9pMy4EO/t2E5+9debahSOp9UnniGOhkBpUMAC
uIG1BfmfgK1zFO0djyX9tApMJk0jgGj4eVbFDpVO5ZBp2fWYfaBY/yVfXV/DCxQDRWSoMr+mf0Yk
NtAz2RhCYbn8z47tHwfFaitLKw8Cf9Ufx1gNykGKRhczezruzOTlvWqDtA0gjvV4nvDpCGkEkryw
DulWvN+oPCvvso5NCQcSWF+gcbzmPMc+EatdyO4Rmftov6jTSHpe5bn7MjNIldT3+6f2poH9lllN
ReRH5Yv6W8m1sNrA5wUqMnJi4zeckMwWdUi/lxcZE/cX4zgsnuSo+SvWfg2PYpno9bgrYQJRONtC
LmjR5CrHKWIyEkCA91/5v9KL4YQDThslFfWK5xj+xlV1s3+Ul7zPOFbesGMboLoL8ocV1mEv7Vih
vKMbF0VlYDmiy8P69695tN5k0A9oiZMFje9jWxMtMdA2mlASmeyhaWy3S7GMBk3Q/7p3ST8F1KCJ
jNHU3scrUTiCqJTcH1nJ1eJCiZnQ6UkgBNMwDiPSdxnCo/tfGSGPRMOlLh6BQb5cYB8yP7ZietgZ
uxpSV564wVymW6U2KAYDy5ULlmrKBAquyyG5Gkib/uyN9Kt2XvTBU2/zM5LJ8W+zDalWbnsAR1fa
+NK42lzY8MrQYIautO7ca/qkiQ7oce3vgpgRLGZNkHw6j9GUCIYoJxZGKkI1yp+40h955/lVzrue
U99YY0xwqgD9fFg6aDUJBfD4Y9Q33I9gNRUJYXSmGdj4RJoMlJkCTFozR5Cjm82aitivBvHbJ1VF
Fs3vjN9/ReDPtMpx8obykOKS2O30O2jmoX87679UfJ1+klrwbxiET4STuUwxvS++N0yJL+Pj5LEz
mx1T74xPxzkCVEEc/ATHLzYopQVJ1G5bRQfWkg14uk03ZhLPn8s2ZUMRuaO2jT1gID0yEMRtNnPy
4Rn1aPL90c7F8lVguQygUWQP9Ad5MYU/S36BuTZqIR+L9LMqAmLoeCrSB2T7I4psrxsVJQGBP2tM
PxeOt/LB286SsWHNNzAXD6ayB23umlc6H349r0Vo21RxlOE1kPP13AGNDfTg+t+GnYBMUUnOdW62
6SgPl0gdJ3Sk23dMOYJqtCMRHsw/PD1koeqllFktbjC4P027SDKldHupDEBr4/R20cnjkO4GF1Hg
3QScptmD21BY3BxqrERoJPjFajYCt1lOE5vfBFNIy1QoIX6C/leqVJUtNe5DMIlxXSW3/2v1VIW/
XtU3e1ayw2f4/WeCFAN48OfwZ87r9TefVEeuMbT+CmV6obET6jispruw5E9ZGx5Cp7JbGIWrwAVR
RAbvXVI3wQ9SVMchcdmyUCJJeNV4lXER7DK9N4mcD8F51lGYfe8+paTabwK1i1V4/GrVEFkyjcAC
F42MXs2LCj8Lu8gD+2+SYsAmdQ0bnEU+tRK+YWHOw07vPQh1AEIEAFkXQrbl9IdWgDWBcX0+YhIY
IGWrH/XdNDFGJ2VWGRJ/RpP2tzSAIM7bVQVoURPDRlqhyunRkQrdaOH/l+Jm3mnCzXb5dm39Y+gG
+Ca6DBzPPKaJoyueszR808bZv4y4e2KStXJJ50a0ofcQ8/Oarq/azvXXpWNmgQOUskJUbdwzkmFE
kD8PcCRsSN0VWfHdheC8AA1bvCSvPPguXz+LHSh2IeSxpZWI5EzRtv/KRdoj2e8LDYEmpoVAksQv
4a00VROBx0HkEG9Y1Pe6a5cwtEh4A1JdRFCWUsDBUICXPOFNi51IUF+YiYVdMS0aMzhBYCYpTt/w
sR78bEuahIx0pkNoH83cLbU3Ta217OxZdKzHo64zNQR0SiH6VMmCX/QqosBch+UPw0qyFqnQAJOw
Go1oulPx9PcpnmgGkkwUJ8Gk1yelY/Rkkru1QSu3Qmj96l1OsaSW4lM0KjSnvVnFPYex80647hEA
v4P7uIftoiEPasoU/fC8Z3yyp+uqsKdzXbIgf3G1XAecb/oRuYVvBh8JoNlLA6BeQgLphwZJiehb
AcTimonPVEJQYKEkJrHvLZb5K3Hq5o4ERZEuAQcNq231rSbVaGdOyBaucn2ZJvrDWXJFxdQ+bSjb
UJk/KyAqAWpjZD8AeqOCgPVcjPj7qdAoerhTh9gpcbhxpVDyIJp/usp9QOgiXrzG7Ss/7juPzjCo
f9gSvk31/1SBf47Rtm6yGYEZy9Pv+3e/M6qdIjT/EHpyJ+KqK2rqM/LlvkEhMDQhngKFFrONHFt0
xi3oMEetDF0bxeBOF6bK9u/w/NaZPkQPVw7cOPI+05q2l2gQi7Og40wnhJu88UUbOD2t/Pqowr0t
39MEh59/YdY9HWM8IetXpHpAj6Qbh13XR13YHg63XhcF/uKZzFGLLH8Iwc2VdPJalhZKQAE/N+37
7epOzeib9mj0I6jBdi00WTLI60xgMaMmRF2uhU30xBPLCBUvulOFgmDDhaMl1tF1115u4YQIOJXU
A6gXut1dy7rv0TUqfkgNmn4CJFxcKPI+nkv0ZRQTB3tT8pFwhWyoZ2jmrU7JVvAy12JBgUqno+pR
GHFUi5Qw/gfAh6yBeGqXO5BTqrqnB5KIV27sjC+mTsZpXyLMOTYG1B5EIRWAuazxK4vy6KhX1ykr
wakPuk7bMMy7SxPTHe/vwF8TMvMgQpppzzpqWexUGA+luKky0jLqZVGKtujTKkL7Hd7lmoo6iJh0
etGCsHDckyA3+RmtWJspLWA+ekfkPaB32EcWqX5CRgGtgytQ0EF/ye5ADkMIvEJeoJJLSOKAF/yr
9JpfK0kvVkiHgPwSGDqJ021Q0trImD3XLFe8/WmObWEge0v3S949r3Ci5RwsO5/mQdeAlzvXC9RT
kXhSPnkQbfOkajAepFCT0ghkWcGN9Zr6mkeRCfXdtBEH5ZT+aFt8FlXi3cJOKB1yAWtVpy2oMS32
hXiF9RG7SwsWeN+L0RmbT639aRm0sFP3TVNBS1DM2+1XsepLMCTbgDoqREE/DiQWhexJGzmz5XXY
+2pIPY5M/V+9+3Y3lx64joOzRE/hDU1L6SUCRFs9vl353mZOe+Q07+Ieo++T2s5dSxDvi01gCFW5
uK9suJaoZ67FcweJZRSnZgs/B7hwCu9y6tkVuWd+b5+Pt/IBwMGEt0AcVyvWZZTo19yjGgect2P9
1rvKLKy7zF6a/Bkdx3A49IOtHZVBYvUag9wO1hRnxzHYv6YsdeLdP93CwmR4cYZv+mPk0RE4QQyc
He7AY6v114Kb4qBMn/ayx8hHv+X3BonmB830i9D+yt4JGSolVr9xs0YppWN63vdySz47Yh3Y5mqz
dEwg3G0YYwwvgla5xvV1HVk48Kms+6EiWXUJlhCqLKUGSfVVJI29Q/La/acfBwcgx3yqLk9IV/Df
qBKl10yhQh5+SP7zHu4oZ9ba8chFj6XCI/H4McYunNUk0r5E0SLfAp+jv+v4vqO2fA1MH2ih2vch
xomC1s2yf/K4Ah69AU37/Fm2ES4TQjtIVFMnBnwRXfXPfuRYSXmS9v/P52RL7bNNz6/4Efjp9bm3
RKKmI4e9gI+ft/s+jx//Esh2qf4kAgKyvNb8pRi0rV9GG5aN0vISgTF+KwWn5HPgL3wCgkJ3PsZJ
wMF0uSnKMjcCYqhjDdbl+DHO3xw/Sm7NIxBH1XAV57WunkLHWABy2XOGvkAdvaWizlBrm3z+VW1+
PIYW/30GsojrZFUExKtY8r5PJwfgbR/5ObwXOoqev+ReuAdEa9g4bQLshuoL4nlhIUnBdOsuY0nS
k3NdbFfWIzEc2plRXwjeLn5grjQ4xAxVfDUB/yN+AyubWAKm5iT6rSm64X7oeG+kqxmaYMIAMrbn
KRl8zi2v1ypkTVk78VOgBWKXw7IXMYpX1rT/xJ87f2AdmgcaitxPQLVXrlIZb27aOs7DDwo15+Wd
VjRJPL1FpTykRqonN8AbtZ6Q7C6KBo28+JvyfcUSYNjw9q2ZApqmXEkLq4r7Y3aUCRWDz0Dlphme
oUSQeKVDHRbMXPSDfOXMrJvBOpZJgFsmytpJl+PCHAulcgsDELfMWmxseCu4+uUo22nO3l07vH+2
7rI6FDo7OKBGvQ5UCxCLYJN8OI+Yt05lLObl0LYmqp+97eq6YHcCrgG8fhYX1/vwPKY3JEhwLETK
Hk27kvwcRISPQEd5QDN6x72xnSnd8FIb1pe8IUUIgrbY60yPiKAD3O/KnKIVm0L/kX9yCjKRE776
N0sL4+7XIruwhKxiGVvFwTiIB9UZa79tXXyaBARA3QSq2GCkrZ9bZqrq00n01lcPD98SdnnmvaX8
l5O1NZbN1rjorwOOk3JcHa2XSIvQIzPdfh4WABIDhsPTJwoZ7UMAoDtcdbgFThlEhgOBocoljGM2
B1u9RmWSdF4ZYfaSN+MmTHksJbHJTNBIHTa5t5vuqDpt3Zpj/nkKYgBDXuUC2RBYPcD64Yde4LOJ
XitLNCGoUG/uHz1VDlgWyNIv3S7rqpapf6Wd7C4LBJNPFTdNC+zAPzv+bXzsyFz3JD8O2bWWbWx+
y5SpDtMlbgnMescxkprHnjKl3MIKfijnfYwnGFPckr32SqTnDbS8CLh+X4qmiEyODZ38Zq//OkVd
Xc4EY1o8iNjvQWgccVYosLxYSJSw4mitfCtp2qcN7AwB+gKhzp9qaOIIWU8pRbRKJ+cxgG1f9rTz
iP6Yg2CtHoJn7ZsqdhsnKXCdNLX2mWy5gPdm7BIQ2k1BHZ94ht+x6mxPRuV+W8DsPsGvtwpJcLN7
IDdnLVSzn2WnT8q0vW8xIpgvNVr34XDNEMnYvidVsmo3xHg5pV4ShqSI2sHYEtTVoURlz/qGNdAb
42kOnfeWgzodDk9goum/HzRm6yqWMbqgMpt0wbh83Yq/1Q53ElIwCvZG7UPZ79DQZ07ho3wXA+7D
YLDp3D+MVjp78pL1VsDeP/ZReH2/6DzjyiTX9D7vTl/ZmszBiYoBkHfKS2fdnqE1khNKDWnpczZ8
oppC+WmJzvXYCu/qIMOJ2mwar64FTLlh/wdy2+WeHcJw06rIi89x3GXZf1g34B9v+9KO3uaoGJF7
SlD0RODd5YWaXHXcmjJ/xFhN2jDZPDfcZ9DL/koXmwK56COl42D670jSTaFobp84P7vlDUyrm5nb
1V76N7zRVXK/PwwhZze1ry1rnwIAPqav8bWoaEL7Izp2dk0cz0HPOViX6nhZB4j5/5uX/smD21uC
lWqLIfJrv+0tEdZWf7kvRhEv44/nSXs9k9hnhEWmqqODec4FWqQCENMXlgmc0wkNl5UF8RAUts7I
A+ctVWTkoLRmv1ZFLTEDNYlrnLN8+BKpVxbbCjtJHiRNJW7xuNIOWyswUs05TptaQM9PqB4cfrsc
DcMhphZh6akUtFlLjVxYmBbfULoW30oucT6In1rMPOg3lgTdHT1/bNfbDN/JAVdSLQRyFwvPYf84
J42RVGL9e5cgQw1B/2cZ+dtZtAndFRPYoTmRkx6KDhBfJWZ0IMd5waMRC4hzf57GJjErbHsHgOta
3gIVc5QrXEeBGD6OVSQxoKttg1ql8g9v3HIHAa/RVsG9QBqOF5KXOuUiO4OPobaSmrNzeUbvInRN
xKdk+BgO5+t13ywLxU0APXhPG/1ubL9Js7+RACp3ywuG0VBHpn7r3tsQKxMuLUzHjPas3SQIPKzH
jcRUM7g/JgYlo0CzLJH4bAMzuciutlkMoz6Tz9hKsWLMzXoVVFH7CxzOBT9EzobVPU/uCw9PMwuL
WYQ2bRpuuf3Yzu8XK0KaWlsLYwBrCXAv/PfzRGL4nSKi/bQpywymNjPLLm3CsVxWaS/ALQhhT4TV
T47GHQnJFoqH1kkuSaDrjvlcCN/+O31CyCDq2d2SWhN4L9TYrz5G+8YHA5mWR8HRYohpbJOKV9Ww
RNZ/QuDn2UyHALn+6z0vOrbDL/wVQ6hcrRVPjm0K7va3Ua0ESBcvGRUrLlN1eXcccENy4+l7V+g+
mXsGKoHc2/jLZ7QD9wHbyEQkG5MnFe6vKloznWgvEA9CeIkZBmwjFOyyXQjp+EAGStYs1x2unyXA
iJDgCaqt9tPqYWQeMmH+Z1kaHmh/OFJornBQ07CvQhI0s7QScPVqLFdXjJ7ovqgQjaF33TNWY0OK
Z5GI9TVCczNQqs2u0QhOfTMR6awPfs4QirTE5nWjV6khRY1rlHqQnhvoJ8Dh/HLKaHCTzvn57D3G
7YKc3BhAk7Fc9oxTMK0N5VfJmKHuRDeDmBec8ZxmF4nSVzd1Vxh6AHgCeZT8dhlDefv0qjNN9rdF
fwChNmQV3pQHfab/TlLBLqvlBINin1goOqeIpuJDsx5Qy0Jf2v48mAa6GfXulnVAVoWAQTkAncm7
duqsf1uly1A34pAZj9Be3Xm17Dm00Fe9I7GkPSscrdf5eneedDJiZEK6SPsu+D0pNniBvEt0dQsW
NVNFpN1+zq+14VetEc7Frt/twcpZmx7uYpuJeX+oP5AaXW/uCEj//9AMts05Faq7SpVQbTgA64pS
2Er9/fnxNyfQNAL7Tz4CINVrLT/OvZqdCOHWsU9J/rvPcsetjT0zCjYWnnNp5KTW4oIQOicqSuLW
jE0d7dibEwYS/q/PBPf7/JuJKvY9r8T/1AlT6qaYdjHsgPNzJ2P/mZ4R20EXuFQNP3lp+0MXSFNN
tjOUjHVfUWhFCXOhAJMZGlqbUwMVTBYNumrodilu3s5sCdLpMCPu9bv1E70dEwBtaV0j4F74bI06
2kSR+noKA2bRzh+rBKUXSvJzfz7J4yDKXhXp8BLcp6G5qZSb8HnQSDzJE+kXuGg2rzUYYJKvDUq2
5cdmMatT516pCJaGAD74eFFhlWBEd9ra6O896CBBtD7AVcU27TgVWUdExSiwV6WNS2OrUnSDLRbb
j1U+GCwabj/Fee4JCeHMH1M4OTQ56BdME7vAr5wbBYGDLsc8JkP8EI2H+1zNOUwjhOTlLgviDQwB
lamLqyjk2AQptSsuVB77uSzLb0rCoHjJvmLXxlwbdkoGwtfyIMIrC2oGp6mntwe98HtGyxFSdJSQ
z4URckwaVWa2lASaG5K5NgzoGFZdpXSWzTIKIOSQcLXmlM/QINZ0hUnkwYrRN1PZ1Ubvb1gB57Py
KOpZljBGFtcpN5T9ws3ww2q0c7dEEPdL+OHZUKScOhJChrUPaebsy7nw08Yd02sQcolgD8TbUQ0t
Yu+StvFXq7bcipW/wFd0SYtaVHPwuXeBbEUqAfy85yL+2MtF0n80tEn19eGA/An8Y3g1Z9DYJ8OB
vY4IC4wL/f+YbNSA+mhWVal5RGFXjiY+TRXilzrh9HBx5FeeJu2uLcmsdIHLkDrHwiIftBxHZqUf
owb4mGfJWa3cDX8Z25uZ6633pYUUjDmxQibecZ4McPXoXeZIKXZlgvVA5Qr2eho8zA9NuDU3kfim
KpO2ZDG4E3wOsWRe4ujKv1g4KVtifDizLJVREdmx+2Wob3lZ5mKNuM/UYAiv2cpawdbVYNdN5nmg
LRkZ8H29Y7mLoXeuhnC5/t2nMN4HCCdjIs8Yi47YclH4PEWxfDDT0CYwZJMJaBw/DD2h1kL79l1/
q2dvlrq9DGxpiU72d4ZERFlCZkT7X7Vee/C/menHrIIQUhRkNiYNOLl6rmWxLfGxjbVfS1chttl5
Sq0vF0DVs8T4kOCT/dzjqkSFcUazE4HSt7IBSXdNLekMclUqyGKK5ciu7Dcq36kvqFhBIcRmGi1j
Bwabo+9nRd7TJQFSAlWGlnzcSDlI1B+pEbZJjY+7oz58tcavB2IjNr8ziW9ZksZge763hRsuZt5w
pnQfLtap1ZzZByhOUVpbrPVYELpzS8vPF1VAw53pmqkjMqYxnSkPAZ0hn0W9jTwRUC1h9B5HtlRg
3WXK4kTC26vMMf/OxtQn4R/WXeFQsWgXfJDxnZ41gwz9Ro0ZUQZrASXC15xdDBtfxsLYvVRQd39I
ud9REuk/Qs4I2on4jzAChF9UlHbkW+n9xs2KGBmG9em56e96L+LE5bwxxy/2iDWx3zJAeGpc7EZH
rFGdngW9FL0YTyp6UQC21e6Q3QHwXqWRa416WtvSp64dPojn9rFZBXfqJBZ6LplRpziBKC4ZmRPB
QROsL7ILvL2KVOYHyqXqwfH7QBJCqryTSanqIaBEkOk+JURAVXYHCOMjBDO358x+2yaQRRflJwjM
iAnKwVVyZidzQp9aDf1FDppw85Pcn6ol/R7SZm5nMkHB/LDjhWKCYI1QCvIZoZhAPMruiC895T5c
xXaK0MuEbAMDz58sjWNEglZBeVJMD8TspLvT9nwQsZnkOMXZVKi6ddN7GmQ29bHW5TKv1vZiBJXb
1X4v1eEjYEtOHjIDI5VooOgF7uVlHSG6572p+kKnC6mCqC3qhnZi3jOWTsdM22Cix0qUyfQ6VP0q
RVbcFZXS+GnwUkWuSiDJhSHcKZu8y4JxY/idXRVwKLTaSnyaZd7a/cijwzBGXFil62l4Ku6VQfe8
+0aOaDJs1WFdgHtX+7T3R7nraaxeu9rU8GHOEhoVnzSBoWepwh78sQjzZf6ZAfUzhvaHT/DOg9lK
YRaIXMAWjYYW1thb0+ngHwBjCXw63AhNwCyZvAk7lEFEhs99VmieOniwYLRvdJHh1JtTuQnIHxA0
Mwl9D2GIVsI6OmoQLX8kgiIOljCysoX2ifahmrhAyubMaivrOGxMpYbQQQjt/6hO0nR5baU8gjCc
l71uxT1FakHG+ScUu58K2T9jQwC1iNWkppAmjFjzS0260nznBUVM4fm7ME6uczz75ypS3O/9Qezp
EvLlXp+3dfZ5Ave0HW3GoGH17jQN8NxWlnf3leKBl/r88Jxw0L45g9afdiiHRMUeROXIlkUuDvA1
Fp//QJpaGN+JR9oTNchjqt2dxtnnW387X4CbI+GFjhCmw3i/8e+by1l591QDWMKeQo0agvsry1n7
zMOTmG5WxOwBUvl2oeGVwJ3d0E4Qn4lUKOabeAKU2jH0mlauZzHj8/CZQWwqyoAjoj0E8IVNVQJU
gJXexcrOOhc5CcBBkY6GUuTsbjZkKm62imUumwwgjGoBfSXr7m0iqlJmln2MBjUfOWdKNMAC36L5
1GedG49/mGCvk9sLCPoNxllmn7vXiROMctRNU1eYN4rRqBTyG4rN5akZmPoqt6bLB43PAaFu2HCs
4p6i8kCyxOzUwsL5Xvqs3AAOFeMJEWITkwihfuYQ5+CXV5A2KE6o1lFmvt3KlJ+SweVEO3tqDXAF
jmcDH/KBEbs8cjOv9DFyaglX8ZSVG6IWe1cq22/OUHaQtDfChFW6/W660zPeFea7Blooxo6w3vG7
+YGfyhWA6PvlilBLLtN0hca0t/AVT6wqLKS2M5RIzNKWJqg30FINqRuEIebpT3ZTnJ6kkM1xuNS2
a76aubo/G+VXFI9paxtkC7BH5MzkFb3kAfLSFFvX2eGLfF+hGNP2hTUHzz9f+aXhAbbeOu90peRR
AXebYflTaplzA22PZIJZWrtLIUX0i7W2XU4ehipd6QfV4AukM4S1+Q48vxXwDhh+Qrv7YC3vILhH
s22EcfeluN20TWJNgDVzlh9sz67xwFpCJINTvlLCtrm5aNwlsM1GpHnuKlLgeigOg8W1Px9g0TiE
6snO/nHRjuatqwTpkGM3MQKXLLLW+Ub7ohRKaIXOAw0bO7dsEz1sjIrrFtK2f5+KV1hpHaAtqegI
3LlbqMnonRrDwGiRGdZICJ4mda/e55dQ9qgy1pWfzyIyPQ4z/xP+JyVN99yxqRFGHS4RDgvyEOdk
y3M4f+Ac1cbAP63DqxgHk3XIPfenZs2gwYpQ0eFBDQKUrAdQgpyXucQyEKb0E1B4DBa5ypK7PqgX
96/LWU2Dq9jIF1y4/rzE2GoohDc8j2PYAIIkzfa0HZAYzHobCU+gTQNwPvz6Dlp5um4O45fNRtjh
Jdqxo64r9Ppi1fppXqTKOaC1C5SzO4IROXxvqiIPpKEKf3brYvP4pHeohrfgB2NfBaXccszn0xXs
ucwvaJKHdqfRlLkIHB7tTujdeCZkVMvfwjnXN8TIHDiSKdNpTPJ9HuGnloe6b3I4lm0x7EghvRtl
ViZOhlMMMzwX4xSIE32zV7UeUk7SVBa0rEhPmJYaynvej3rY2UGOkGpowR0KJF7oRoGbdi5igFXG
PTGwBJi1NL2ZvfVTcOeW1SyAjad4RQBPyvNID6FUzcCEQH7WSNqMJhFnt7xTjWXMLQ5eHcp73b2T
4l0QS7NqW9W+GCn16B0d9YW0wP53N/qzq0mD5QM04D4e4cScToBydpHzEr59itxiN1ph3UR9R76R
fSkUkPuWLCdPM7t/+PYh5rg3aqGe4YIu0VqkXyGQiXRoy6g19/l5fVfaMBqXrhvFrczus7ayi503
/af34+9BUEmBbD9t1wvcZdBaoRMoG6dRmXiCQu6pnKo+3u9Kn8Y2nROmFQGnmzP3PnjtVyPvC2sn
5J57szwLiKXFw5mDqLgJ8XeJi5CCLsXv6W1xS7mmrHnMC9IktSIK6CXDkmPuws+pSTcvYekhx1SJ
aTdJ4GVUWjBwSGRFRKf9fqASwOUrAy49jW4aPNeaxWysqgCrb8+Z/Nju0u4H/LYt2ICoAtJ0Qgkt
16AfFhsYP+EtS7oOj3oyEa6jMtybmk9soWlL7xmScoMulKR12ZRzAOPJn3Szz4/4EXeUGX8y/n0R
2tRcQcnjN7j5elFqC5PDWddjOhSLRg/PRkxvnPndwLIJx+BzlLQhEOk8P/qy3wdfmc40pFzE5vqq
B0NDNnZGh8sZF9hTjutkTofjgqRst1x3kkja2jGk3Y5/kqDEDLpHrDwwKZCl8GDO63EY81etDNyE
7EjZR5Yg8k5n3BtkETbkeN/6u/quz+Q6vO8dqG0hLRvytrF+pfdouB8PkYMHRUIjZWSH86AfU7/Z
whdyD0BBsvFOwrK1qwPYW//xgphseYK1+7mnCSwWWmNkOWG/XzNpjbvGikX2mWVPnbUGrjzV86Ob
xJemH9k8zE8HMbMqWpFlsUncGPUdnZnQ+ibjiySfNGqyuJywJ6Z5kID0BvH/H1u+AEp1Hs2moGPA
70Y1CmXC6F3Nb4j/Z+lK84i/B9sXPZKdMv5+rRk4E5nh8K/hfT8jYmwKFZbyPDufQ+40uC2R65EU
lBsehEuX9MMV8lfPI+4LPftUKPjRFTSob58kRQ2gpYiZAH1Pzf1ggiBub53p6kzb/T4kHvbaOUAf
LHB/TRQWw09CescAtqK1FM2KVUKPOT2qYzeeuKHchcWf6l8OeKYhlgAcy0Lv3mf/wWWLD0ctJmoX
nI37wjpkD7XLCvlEic5WAqzaFiJxUSXPN3u85Blwv22T+FBiSJlUWj+nJY31KspfM4c/Ou1Cg+WD
Dmx8rA1/+herDyxsjK83zyJVjLJwRLSDCcPa5wgNHm0rcebt83jjOb8VYBGUpolkWFVzvYkJjnMg
ZZFBtjlNLUw1jfGypZZYwa1r+HXhajWohw8TWoPqMW8i7tDeUFK8kYEsOm+epj3q7M8+khh6yNaK
sy+LtTm3oc9PjZLPPlqcZQ6OvO/4WsI3/ustjij9QUj2r5KGj99Y2ivNuqaozA5B52KLu/h7EpRf
GjcaiDUQRxWCxfIfpl/nH1vM33/rCdNfg8pnbKB/SYIUfbd3oaZZpgbChz9Q7VMoQtrRfx5WkUf3
FnvwWd+tI8bZLh1w8vKu4hkb691eUxHu4Qh2JfLWpMVkRPmvXN7z/Wftn4Du3jLisl7k0WJJ+bCV
HddFVp30aiFufMvlwnmvU05xrV3xvMMjThB/kmHhftTfOl5NbVPeJR2QQsjUYpQPj2nC82qb1E3N
KYvywZo+u/EnR1DFhK/ZmRg6aKf5hsNFaCwgs03j9I1cxnRLJttzUafj+UA5T/VgIP4ptBb1NGta
4+XZJyBodEnBAL2+2BbwgL8FHovD58I4AWnsYWT1DGEkOz3H01hvA2Jlv2pV/LByfxS8Y3j3uB9a
eBNL04rGn/aaH0D5G7VhO0y8oEEU+D4PfTcvsWa1tVSbHero9BuURY9a7oPL1c4xM+xwW83G5+pv
w+E+jH7pNZ47WfQjJ870utxugzjrh3G/wyLkpyqxrqEiN/whKXKxzl0QbJAyNdh2oAs3WbnwSJ/b
zB+06pIVkfloaQpBZ+VL0qGu3V4BteuLW4e3hsX3s5NfEeP13Hc5YUwMxIEE1Ird6rnXn63812jV
xYKNUfBZ+S/RPMBdNAdITkfmrMGD+zx4AdCmx5ONLAXnpZzgtMuLUYc2gsVjThBVSgJGkT4BNmQx
vuPOcMX7CnKgogBUNd7M9I3oKlDXBV/2Bsmb/morCyxcCxE1cidmNnpm1okAgMmLwUcw+AVps4FK
1HOzFMeSKYoiHBdhdt4aS2oxzwwUPeSyOmaz/SV4Qg95zIndvtWb0xmM+TdxGh02uAzpJTqUZTdc
5U2Otb8VKkdeu8yewADirM93HCF9ZLdwjuq/HoeVusmvDe4VORFPZf7q8Ph1k/agdzUOkWSXasky
aXsoYRoAKFELnkEVIDybIaI7BiRu1HN3+Z0Ch811yfmdtQbBdbVSvaoSOUqPspr9ZO1WCskKSyu8
uKbNNuJ8WS4V+OzlEDE5ONJ0vWpzobJAYCVYoNIfdHJOCEdJqcFXMlxJVaqnMjY+/3LGC6Binmy/
9CMSTjR6fL1Bl65zQlIlNMuPZIkcgHPvUBhdICMPteWSWGGD81RmRy0bUsUqikZYsakTO2vzBr38
jpnk4DH1sdu1tJjC4284eDAGYGwLBa3OYrNzWwNKkyUXs7BxRhzyDpG3f1smgBNojMMabe+65cQc
kl1XiR6+im+hxpxWOGYITE9QxjIuX+Bydc1LLp+Jo0LVA6L5znsgROxcrSX2b6+Wg0wRPhZFqMAZ
GCMdh66xAmcx7+J8SEqp7ZBW0I4sNNspQxiEtWPhWSvjPjJm6VeRvZL5rnL9VNTVM2mJ2lidg7vN
u1IvFVf1RByh77Ta2EFiH474IaFHUZAq6Wcm5jV/ceRn+3OBNwXLzE7ROPXz8O2ssgx8NqBdCJEY
aVdX+K9h6O5ezXi+G2cGokj046o9LjLG361ST/3nhpVYm6LjqvD+g5JfUoNMrUG/8iiCAG2DMz3S
ymiSn8bJLB/zlw0TCnMiVemTMyFTz2oaicFefOBO6tkCrRKQHOJBtZyNcCqn0RnYMvvLCOilVg7K
dWAMLNOHRLqF6UHM65iGQ6O2+j5fBNan0xn5otLWaqJ4SJZKeQMjed7eY0IvTzBe37sAo7KCZWlk
p3CJXWRyXGE6v0s+pQUOQYeLDqjXafSexDLrY2sGYwM7nYvVGF3pLn/lWmZD2hBYrQUPWWqbQs0n
D1ONh9XG4r25IAuPykgh0qEf3wJuwICDBECppBaLCfNJKrbgODLdaSrgL2W1crFxA5dVu5mwnBsR
yD21UZt3T7a1l4jGRsYhNcpXrjT/GjmpZAs9Cp95zVkzXMYJvSBOIWtPXja55ShNP7Fs1wk/hCUY
XiLdbbTuaYgSFnIfRhI5HNyh+Mus36ut+GANhyuqMxXBZNhMVBiJC37uKfdwn6kLIqs02c3T1qT6
h1lHPHsnsD6iHmpQLyYpsyXep8ZUbtMnL9AloZ1pdxJz4PSwNEzu5hBkUNsjlEaA8/iX0nWI0W14
79n/MWY7Uy/3VUb/PdWXIpXfZ1ijW6TdTFgGxgoLnpoH4ndHDcL5j/v3Rf+aMMMZhWgFF/+HCDAL
q6Y8WDMrGH6nTFYUhup2dIhphJpKzA9BX1NNbF2CQ5G4BNHiCT1nFAysIEjsPEAHtzjcZnQD/l/6
4tzktik+DI7t6vbu3Yzh9Yl3RCh9ghIR04UQWvdUgHVoaqK1rDoaftCqnX8kmn/NUiICKF+VceTW
YMFBHDys/b15315/DAPGg1XztFZz+Ex7cfmDza7ZQmetNrHn92IC2uuqXp21Jo9nD9AyjuRu7B+E
O6ycdxU5P+rY/sG2zsFyPuT/h+GAFAM09CDqhTI3z+RJUkTYHynBo6r6QBmOb51esbCjdsxxIaZ3
dSNedhMBOxHkcNMUhf9PvMEHrLnz1hRrXCMKLFu/fo3Yeonm2mT6X1m0Ki/h0N4EgoqdnComy8ek
4UiiAT7FBHiSTcQQlj/yy+0Bl33to2SeFqMYSC4/A2GczAiPTfITpy44KDHRkxAPF4Ai/cEYuvYC
0ZiPYcg3ntt9lQKuSlKRIAyE9mYTi3LcKvDqXk53+7XprL55ZiKdUgQH45VDp5sosQjpY1/2GDhD
q4Z6PrdxMOggGcJMsX72XETB09xUaUaQSoHbIN+Pb5sXwDsCGwbb/pGgRlKwIID7ZIduChHp53Rq
n1Zu034/qQRCV5Lgtsw+2D2jhkO9/B6vN3HW9Bn3rrtkglrM/zDM72WDY5mcpZ787Qeu5kAq14Nt
1EOsurxkRMznJLIDIGiEeMWUB50dQ5m+I7uznaxORrQ9KM4eynzVber/hXKINfd9088Fn3h3Vd+j
OHn+hcm21sm2/hKARZt6SDotfF4bGyInFuzHIe43rmVHNTlA2h2sN15zOQYqlexAbel6llrX3FAO
JxjYxGV70JsD/taIPJbJQAZupjgLWaPhlsXwbGfdDM2o3iz5hfc366viXjg/tiLFDh0mGEX+Ak5D
RgEzbaCAclNjvnDh90zDVtoQb8J7Kv3nlKXPOQsm/KXtDVfK5enavOy4gGV+miiq+96KOzkBoUZJ
5lIPaQUTwQ4U8kelEoSQ1zokTH0zSSR9K6FvqkzcrdMY2BuJYYJTTbcOG+ERJsfj2A4KkQOctX3q
O8oOHgNqwm0PgZMiKAqKehWwxnIA2dfdTvEPMMnZHvR7FrfPmT3CltOW9f/sj1ZbNTI4SrQ/TGlv
BpckF1sdfBqvv99AihE2jxKwtdaYs/W+2ixaIrwx98brwQStB1bCuuZMbFrJZU9qfH0aWtLuTZJY
ZZsVNjPoO6JZMOVyqlsxiUUc3wdKkdL7trgquLV89QsmsU7Lqog6mDijRMnN4akqJbPFTv4xeRCe
TKKtO2kysFGhkApu75hA9e9NOS/WGSP5Em2Qj5WCs4kAt1kkNr3KXkj+a3ZLdExLfrsAvXa7paSE
rUd6QcLX1ebgz/jtBOy7TjXfYJiImJ9PH/6LTSgyliFrH8YuPTuBqDmcAz0/uX1wQcYJk5sZjGNV
OWtxYOQs0K3EJNyQIbpud2aM5r09XbDwNtYBCeONcHsL+FG4FNtWkDE5nBJB6WBP8F/+lXRaHiSB
g8dtPcUSRPmThYkRidG+dOy8J15sWNZK3LS6jImTzFN609hI0ob8vyZSY0gbyFPmF2+RzeOMf/EE
g7Lquy18PVXeXCbSVLw84z0XMaZ/zCjA1MntiEvgmoQX/S1WIicxAD7GnjwxQB0hwGvldTHqwsRp
px5HZZN2wUfcFUgiSd3m8Qv/TZN/t7jm9tc/IKAtcfvQtLSIzevGynoiJyPsvbZX6JbwWZ0uI/jT
mTtRkkafuPmtZLAH5iXgH8QfR4OqiQeJQ8P2CkP3zKnLgmrptPyM3TTnBZJBhMrpLj4UHGZkKuyK
1/DBLMF1mKXOa3rbsRMYeejIw+mQ5soBBUFGRZLGSmTG5CHYPUGacbHnDqux0P6vyRNkOdYwpTmy
o2blWuyckamw6OXm6N/TxeJiDLHyTTqt/F20yHoOCMV2Z1JreH7fmQUaTBkVnvslpgqnd+wSu9Jc
TMjbt+82S3DWtko3O93u5ln9kmkr7gMgLAx7GNQDSS1XUKHHah65dvyNF6V8hS9tovp5bOC2lGyP
Us6TwiyWXzOMzCLu5mrQWPDOXpLaH8p5mDdOXFezj9yo+G7KNo2UHrExCQobZqvzO8lwghgDmM9S
S+9uqmYThM1AXXOLh0ysRR9yeKgMYoAyM8/1P4q2In0N6T0flz310qjoKJoCbtKHGMScdV16dJ5V
KJpy21jfeMVPV4q/mmoY1iAq5Dfah7k11NhS1vMz3Gc4eGvUKqplu0ku0PvvC5vH9A5tvVReB/wD
TEzRfPCr5GNxXq6h+sYRpu6Sn0asjfuIIdk+92JkcPJ3/Hp1KTkCZy3Q+PrneJcgqLg+Yd11DJye
LqzfGSgMyQOf1kL3sPonejK+MAB1jjsGsGDaP50qS/s6u+j1Irxwrz52q9LPoBY44Lttm4uRSN0B
QwvruBqI4yYiPIb7foVuBl52dCJRSMAZ5kG0dQhAzOJhr0YH1eG5rVun/fP/ypTfMaIzw3nPZqjl
+t6+XtLzRs6bfXjTkODVUKMe7Avg7OSnYus9mep6JwrvbzjHYZqW4aXLqHW4K93tX6xZzC+XMhqg
A4yZP2sr9PSDGihtcPR6fIXaBGT/4TLASnsxOVbIdyQUgbd5PY2mxEk4qGAFzoRQxbXhiNQSGMD1
o0yjaVVydTfbIgor/FNcDcAnx1NOZ+XIwaZxWdqALJIvSQsgSjAUUKbM+F6PzwOxG6Het6u4pL7N
KfruzQzo2cAHYc/vsuJBq/2OxFEuuC9ouKAbWYoARvLW6CZ8VDsLMfeN+1yzXXYRTw/uDYNt840z
aZJvMkFllVkafqHF+raxux1wOFemTnFhVKcH77b/z6Qh0CMz12OgftQY6ZLWYpcS2ePximDXSiIl
1zdEpp1CVdWQcks6y79xvYQbzgcK5U0bIRAvFBmwigIODIixOogXHfS6JODlG+KKFNNRw9n2jPYY
ysqZLq2HlgkhrwIwwOSFo3ghaJd75jHkcVL2raCTTOHV4TYhYqmgI6uv8jhRoY8benUyT9cA7Qxv
Bf5Fd4slQOFzJSobeWGmUCMMBLNH4/LlcpC9MrGSIjep9oGyob/IfhWmBzx3mN6omSP77rUQl+I8
Le51vhVIKi0Swua+M2ElMK9Mq3XTvYXH6RRFD+VZC9LK6Og5k6cLgYK48dxVAsPUVBa+5te2QzbS
dP6Po+fuxdBbUfscWXVLBOLOZZ2QO9niCIBA6Y1ejdFf6Uv8HLQL31UZDIT/g1eDBcJzsWo41eq/
KTCNp2CnOAyd4LKo6yKyNhZbpYvnqT0q/xu1FjSxLLkf8d44bTbhIywOZsDFaaLGwJ47G3fqpQCr
ufVUBcDThvldcE0vG0V/YeZOx59rsaU4q1bYxqfNSf/KuHFRUYWaDp7Rd+nEV3JrlLCsZmn5//42
CJDci0AkATH6QOAy4FHdPJSsZIbk93rUteN7wTXrisRsZmaloRUiF3yd4q3Br/MuXFciCUlBMsbl
qy7qI6+sDD8IBWMfwhmrHs6Lw7DaLaa/gRAP2OO1bJ626gcvPoeEx3/v3E1isvZRyb6u/t7RFM+H
pfJUocMlCMXbmIUioT+WCk5c8gWJXNaBSedmVSdR5j/2jV8Ouz5g7VuSb0B8VgVidOTD3jgNioFq
WryKpz3miQLHjDuTCHNk+WXxxiNLOwRcyazLmkxNidMI1UKWSZbA1U34bqempD2XYeYNitjRwRqZ
/0a4diWpb91zehrkYaVu5idPF8jPyZxCmqQZSWtTQdpdWJw+c/7gTFixCNL/Drbw9WOYsQCjHbs9
zkSD8z7p73kU0ZuFRfWJ799kkRr8uYREabeQ5y3IZgD5cFY/e0zf3I4w3LjM+m9zorfqZ21jMDmV
OGpLOTMTY/DxL5w7wjT7qF38ZKg8/DD7180RgDLrM6KgGi4rQkxsSaSIvm8Fnr+yjy/Boi3NF3oz
BsT7P7ig2K1qBnx+sQNNvTwo0ozbyvstKnog999WOVTj29zzNEfysgdaYRCt6C6Rv8/iDLxsm6Sh
daZNqbsUYwyklhRN0h6ERF5anNJ8XNuTXh10Tbtr6VisjiDG7NKElo1HN62nuLXRWWHogpa/fcX2
I51h+moR+hBUJs4dq/6zuwGlwdIj5VdulFNVyVZWzIZGD1dvI4mCZHLQUvQFDDV9cgIxthmbw4d8
2j0pZdDA0jT0iLd6xxsEVbu3GEkdzS2LGiLd0LX8cc33rZ7QCkCLiU2iWi0cFwFHMP38VeQYb3kb
jNtMrDgEa0EWa9Zvr1A8DQ5krYGPjGH5YbqHIIneZVk6imY8RdB14kEuugh6gF2lW7q10v3ssX83
j8KT1U4s/U1suKo9cBVnqGucfXgKa6zOwX00scRSnG+EVbWzoG6y+3MQGkeVnnbljcwQ9lfh7EUU
d1d73M0gIt1auTyu1Te0ECjQcqKbBddm2n3o+2O0TYFe07yri5EF3LReZlxMQvilq7Ensu7qI4H8
YVtBvhyD8hKghXC2OU9y9tsewlOC/O6H/7DIxMFouJcCyLwnRfAqB8+Ou1KI2tV93uUWXIKZghMH
s+ShCJCQz9qeNHHaNdmxzHU0QaM6YqlsoRa3nqqpW4TZcij/DevHMai2Bnqlx7H+qcWHABYTLN2S
XlrsohIlFftbxi50FfRC+cvTcijuyVR8Uh74sQzjgu/6LB1tdTeVUp+904XgVPCVNtGErgiRvo6d
l48EJbv1xqnXeB8Mx8k2Y+lIN6dx//I0vozTQTij/vCW/kbEdQU1oqircCGGlNSLAZhEH1hD30Q+
lk3lB4eGZwP1/3D8bW6cez7u7KH3ak2sXbXd77aTQdn+QqK02MLiR/q4SwEIrzUBeGyAspIyTCA6
1w2hJv7yxaUyIeLZnlEi0Y2SJX1o+bycd9b6tpXWDquWYNoQatQN4uhqm5rVOp30VZE2RWiK0akX
xs+IDfS9q/7ZbGt73hnUS6YSd7GeutUrqpaR43x5KRYQ/8PA+MGNzZNiMBHL3rlTa68KBDjdXFw6
V1xgyjPRHzByPBAqmMPYBoAPJKBhgBQqqIW+nPa1GZ33ocjk1VTGtPWmnTzYEzcuU66n7KaumAk+
GvqkrPefjGcRWe7myugf2oe5lvKTSpFITlTu533UEFNB5jPGbKLqWSXvvEr85hexVLQoyizFLx2E
wr/YR/WTKdLYfC8Lber/25ThOFD/oFmcgaxNgn+2P3Uy5sB7Too7JA4M0L3cvBIITPlMJOqU/Vfr
AaLgODRYJCLsFhBa2txkV4MyopptOXT1GJ53WvaZ1eG6xc5lTBudPCb6c+fNQwyZR8DPQeLn5/oL
WKU83oYA6GXT86dNsL9doXSbnlYphS2K+nd3tv0+SBgIvF7BM2uPxFMSN8lPdFZQsImJTtzPrvBg
GTaRKMr2hbgUWOvykU1JorvvZ1B3KTbymlIdWYurYija55sEwAW+B4liVAoOkWzQuiq27ycpEF1O
Sl0f4jF5RVwYPRLJ3lreqANDAb3Iqa9NvDU5BRSlfeIYMQOiuFH9qbeJNOKQcjTOJgjPDIou01Ko
qX5ooIHVk7fSadukT0d9v24Kgu4JajeJ3+053QQVMNX/q5Ex89ZJRlwo19Niogz02YxUUVokI+Oz
glW8kG4wqYm/KevKnhmAcMdhnJNCsUMvdRSDDu40asxPWTvnkJYB0VDPlg3nVjRGBP+/XO2mmEIr
keoleLrwSSf1vtJOruhJLxfY8loEI2dT28lJcowvNqsF8tKpTG6oA++VtgzxjVJEJpZqF5vf9koA
qYbNJmpJJKJgVjdapaWQiVU2PlK+2Whr4yTzBMYQeukKtzloFoeN/zkrIu6WIknuKsTUpNFY/By9
xrTzDWuyUPzQKC+U4egSCi5doNc5LVo8N+75rrWqnqGpkdnsk5SK/+8Y3tuiIy01PUcIv8wSWLzX
TJM+xCL03Un/OgFMsAxnBE7lDjSEhqE1DVX+OiNIojWF0/AZEmuC/Be2WDuEYDjhKyQaFECdNXMM
7Z+xYkvophQsJRCrqpyW7O8vzlUPohNM77oNWY0YKnBrj6W5QqMgFLXrOEjz6tfHDixc80IA+trg
XDegr/Q5lGp8NOS6MXlLmDckW/wRYgNlUYkvIunaiKw5am41u3pnjMMw0sBGQCb8w5G1uE5VBGWD
m+v2R4bXkGfbDsJOClp4BCz52yTL//QZJTOJJsbJ4L+uPlyTLfJYsuUzWv6BX7M9MU5h8YJaHrUu
cP9HDYDz97sLs2kMuDfg5PR5U8KCFNDAdUhVPB3/lF2koo5r/gQzbFWW5nBO6F4ylbQY05cQ4PlG
yQd00D/FQrsQgtbu5LjOr4T7D/8zpTUR9MqAj9x3ARMAsiCJ4WPzqtu2RrvY8AU4PyShBYPv+sYy
NYkkyputURVldHvtEjZ4kpXLqzMPVHnYzLOpbNvBfZCsKSOxZ1vw4jl+VWtWAwqP1coa7AU2UaTL
LMR07NQR3nARXdXjn93BiJtSGxlzY/wXL1TjRb7aRf6Mnoxqroh0z0pRrQuyaBbYR9K56F5+f8fm
8IOJ9XD48WmBhwRBjhNLh3go7Y8/oUlBL5+7xs4bcMTzmFr6Qt3OR9QV1TJ65oSAadm2MWWYr1K4
yQvwv3iHJtYtdBt9Kh8TSDO6Okwiz46D5C/44LkL9J6H+2AM5RhDUR+mTt/N44cDn7RQxQZBGxOX
Gh+t1O9TCDuleI88NkRoGAEAE5qdxMCb3DpC2tK9px9Lvl8QOxb+EdB1jN//ILzzvXiSrsqRNT4m
6gegfnLlbWFmALO+wqHQW8MUIQzKYAfIJEnRAjS35QU8XjWEwAcDPDYLBFPjzirUUaUmTYjTZXnm
wKcZtK3bC4pmrC/S4VNuuMkw6jSjh0UHTjSWDA5MVbFAwMf9lLAsyqM0YcpXvsP12bJ+siVVMsgd
/jRO150N0D6f2MuMxy2oTYP3hRVq9m0xUhlW0wZDkFEk8YVV1l2ARKWIN5lVMmyZ+ghk+0NaKEm3
Ghnii7l5sX9JSCFYzd3+1QSKGU2btgbB3T7kb17zQHRQPtb0IldMoDOtChTDqFF/5FItkRBkAtbB
xiJ/RQvWXiAUrV303Hc4AseQQpm2aSLz4j3z/iMBRaSeebvltp/ntEnXsWmXGqy3SiDMV7hfN6uk
SCM2m3UYOeIMySMZx5nv3hIjwKGdaMWQnsnYF1inuuQxI5jGZzOcW0OuHnq7UNW9X8MugrvLXXbf
2FpCw4+lN7G17uaNmYqr3xFJaRT0uT32xAWTUIspYVvJXHOimcjjoOUFb4/u7yuz+fJ+4XX1g0QD
tEhlHtJeci0Yaj330JLZNkXqfyuSR2pDFm+6rum+BztQJHqLCWBEnp7BLrcSuwOqD841zUFukpIO
3gc/705L7wcoRmDKF6vqud1yn5IcuzYxjcSFgdhB4ZSgkwCkPkPugS7SKCfCNiLZoNfRt1yL+yIh
+qcpuw0N/TOLgMIMtTOhkJTOEb9D3KfdIdRqga40xLq4sKuoVAHVkqy7UFimliCxOciBwP1cGhOV
kcjgwnh2urLnUY5Ih1nXCkbEhuoE3kIJiy3apuR9XxJ0fXkIWRzeiE3xCQzjWKSJzWePigwNooOS
+BWd/yDBU4qp3ucZwcBv2galNTBIl6ngcT9cAIdSxGtYS4z1yPgSSLCgqT7ajoo85kzsj1RA9zGF
sNqlsEycQ8Kh9tZAreTTQrWPM6b8HkiUVVz4VxAAYRlGa0m3Xk7uL99iGHAbQtHcDBiY8fG+e8iv
TwA7b7x8S5knXQFo/AhE8aivgnFR6oeynFFfn888ZxfWRS5MluRokZmXbFhNWybPNz6y3Jr7Sg4t
5zLHsGPKldv5dYVFRuajKTasBLGtaR6UyaiCyQQdTgg1dhvVsRqJPZJiW21PqQSwvceh/L+24H3d
3r0cFWelkFzsubk0j8sPMPyHl2ljtS4iH61TIWOPfr0UCQy7gIwI+b26DE5TlSaaIArsesuABD5T
yJ0z5DUjOjrzKlvGFqLTx8nyC5y0U0eH7Xi3/cLtCEgzQ+FDayKCz9vMrlsB/+sw1oYAopnp1v47
+D1lvSrT0iqHP2JUXlg5mpR0f0d6nP0p5GxVUX6FOFBaga742a3vo4vXGkhBIxYTrcRvV1uomJLg
Y+eD8fWvUmaamAGrxivc2rg5n+XwZZultZafU55ew2lJ4HzK1CbuDA1vYBoxqeXTQWw3jOJs/3IF
Cv+a3FsJBX46NirQquhpxvaoesflnNBVDxd1YZZeTJUzyxYB89QaMkwdgKReLwI/Q2QiNmw9OuLy
F6FTdZUs20CmhK9KJ53IxoE1ZxkCWMoHi1i9zZfJ8gL9DpkRMeTiiR0/Pr6aO/aZgrI2O9HP+b7M
5Gbny0tbxt3vCTIDgo68iaBPKYP+Ipn3IODVODtDvRyE2lCBYepb3B8rnWBAbWaPmgLYoHflt4f/
v1meer4Cnh3dTbNlHk4ze9qiOoUa6ujhBAz7oZBJGcvtWeFxhldIluT1qgHodM2VCK9HxKinlKUz
5KvqL+3ToRaEkli0RJOk3DO8tnmhtm/4hHGBUm8gF3Q4DEbTSLfofyefCox+HBocpHkGaqyBpPrE
qKR6YjHkjcHYNfxulm+mV58IWktXqzUHoUqAayODMrioekEHL1GPbJwLBUZY2ZYL8HZitI3TlBRf
eWrLhxsV3ndCSztYm95rtEEjn9EKxvwaLPmJMK8TujxIwe9qk0Y4LGdKNu2b+Rt08elbulJcK3Bj
8rGAv2cLQSCbqLRbHrx52JfwD2eKG7W0sJnf2i5K5OKJYxF6T41CM0nHDJ6oHNjXegf5pzUkkG8w
6X+Trrm17BlRRXvX909Bq6Q8y5exDME/GtvbXq6BTXTpk8QxTsuAH7/aeFbu1N0DW28tkJxMfbUJ
0e0iKMkagPlajgBRaA27JN/ecw55GdhcDS1cCZVTcx03ARMOGyYJBszTNqx4Ybmcanx7VW0km3Mn
dzhDD4AmE0C9Tba1Ig9CfbSNorfmKjQ6tnp/KROzFC/GU64KkiDrSyL1nC2meN9nvaSDJzGx8yWp
7Grysrt0uT+JzoMWfxYJY74BuijjMS7Winh6W0jAyWQNfS025E1i9CBCxMSuNRZWW6bpknCPPkEb
j4G4C1lqRvDS/vwjInComr1YEnNkOXVuEkslX65rJe6tAVSnSoo+Rw5zgFAgpo+Vcnbza9h2hwxt
lPbMrajPsTMqmsp7A2V+Y1yxXcyTMl507Cl7My22ghAuob+scSGHzYFGlrJfPMRG3HtnmRwgBlsO
32oe2QIXuAvV7QEDmj4TGW6DyRn7zIT8SEcBwF0nvrj3P8+WArmONLCdUIkEWepkU5oC4eqskGRc
SxYfSrhoSoF05UKYPbJYMdy+R9h9XFY3IMRn21UIbH9EscyeorA/yWvIWkF3sd4Acss/arputRBH
jqZW5hkqoJneG19e6r+aRWVCLWN1cNwNW8pMBt9bYGYrSJb3zcCcjLEb+5+DPl9HosBXM677y57h
Dm8AycTehvF/tV8bTT4RmRW7auO97VFz9yjV7Y1KsThbxU70Bh3Rs/r/n8yXIUHwACHxr/5SIuPc
wgxMYu/F45txM8g3173IYSffonmBOq8y2l5UnHNPxEJrMheP+DcnGb8rMDDAZJXTSnSx2ZE2fpCt
vSVZcurYQ1HlTrZ3L6PMazobWbePPqEyIrQOTcaFHVtPdHqewRIx446Uv9YRzQJLsEyVZE8AgvSh
HNWav5fKJbfgSc3T+GH+Iiq765BkMlxzDAp3g+GxuRG3q6MeodA+bchbAK0kzk9f8vZ7hHFohKOR
+sjFPC2z7pA/1zRyMkRn/Af0GQJ0142xsrxwheq0K5mgWc6IvbNKXLhxwMmzsryv8z6v3yfLVmUv
kFOYE+bOwhZqj0q/mut04Oxw0RB47VDfhrA1ClHQFZBAHxttpuQ+rZv4YdL7W318LTNWbMAdcGgu
HSOqsnXpb9S26AmK34c8KsLx6qbKEu0I6orHSpEZ/9bDIhYIT/wdFfCtU8NVlcLjydbGzJPoP587
dtu5TgSldgH+A1Tcg1hV8P980QI5QDQY0/IEX/q2tI6jmc473FOcmLDaHj/8RKyZF6TSdjjbd3PU
JAeo5sNwPkFBzJY3AyOUF+b2pOw3dVBYiGTcvVWGgM8FMfng5QrqVSRGa1QptuKVJFUuarZcYNIR
LnegKcaPA7yN0pe3oaoKjOjVmZzrd+/0hsnY/xbNC0f2b/whVJXt/HRroquDFtW+If9Y6MW6e8Yl
H7rl0i+q/+XDB+x+LGHohA9JU3vFeF/Qqoz3O60UF7KmmZWOEvO5wHy30ETW4oFumzuQ+CGP7p8e
6AFibmC6j5KMwWak06vKkpVyeCjy9GGOwNV2jUAuBOX9Wk/CES7ZYnwYa10YXEom5rSXIW5YNR3G
BTlTZK6a/L87VeRPaS8iYqeAF6+pRH2HOTMzBKNKaMDvn8HYfwuof8ONVWzWHOhpIRyflYxtoj4e
VtegzPW3EVbWzwsvgTm5MvinAFR7a6Uw6BU0yQI+IM3gs5Uul16kwvuJaTsJVW35mmV5QUHk6pSF
/7Wp+4p3goW5hIN5GRbAlHRlpHKf2SJGGDcyjuwOFQfrdJEWV+fabNK/8IZbi2jc1Xkwxo7lZg3R
4zkc9aqFpvtmlSZq1UOymRGO+8uhwlrzjJY1XocBRXLLq8+NLXw/r5Ph1yvkDjhR9OrPQPoLcVS0
8m2vx2FWYFtxU4U+fdFhdHO9EC0fUJ9rKi9sEWKLLKiovoM0/DHVl5LlagFRoXgxlG5/Qsmb6r8V
aqOeUQLbUvIUL+Cq8/SmX03LbovaaOOfxuo7JfbitEF7kuyfWQLiNZiS95XhmtBoQ5fCKktSfjAz
FDua6vsG0xcLHzfYBF+hiJmxjzZvDxbaW+cyyY08m31He9f/RCdzNdRW43XoZnSB8tdqLRYzwNzM
NdojsAx9IMJrMsCGs9Y6G0/yjF7jbiDFZeA1nZhGle798LO89nby1+UavIdef2rhRLaEXVxWeZV8
4yQF91aF/VyDpddKSvXyjkBZKtf0+e/U1gDWsFvDL9b7W6EFpF+3GxbxCZ2R9oCx4U/lLtJQf20J
UlWifGdx/X9m2ijpi9PAc4F2bMCgn+oW49nvVUdrx7MEK2UdGay0H29t4Na4zy/b+CQb2j8WuplM
a2phqKGf9jRe5kACrcxzuZTYhfETuzfRXyvIG0Dr14LamTb8uHKUzKY4pVav4xTzeFkJXT59SqJ4
1BqyNjI2a4G+/TWJfpCQoE7rROPhclU4puQDt8uBVkgXXPRDoNyww44zh/F/zvn31LtG0tDSykTe
9vv5LuhcvNwiH6yOI4FiuqP7SPUTspEnzfgk+YK8naBqO2ntmp0fJbhpvXxpes7/mTVbxfGvdyi7
MiXQnwQ6XWzEPPAoQLNW4R5jYnjD+fmNbBn/wv8tQZvhqxGpgelDNGx+XXZKNFnNT3nSKNbbljAU
Wk2GnxJbfq/dsDzBiXI4mRSlpw1BmGd1rFIdTwjhZBaE3swqtcPF5hHA7TLqW1MbDt5g0cY5iCZN
ka8Dw+MIK+yrNtWsF2NqfpXB6iPDBT264lpdXCxv+qoPL6WQICJHuxN/KOmBjqmb3SX+DbhS6k3R
WTUI4aTqaWkhcktsgMn6X7MP5H4TPtHlxSb6xfqSmicbIkIdfyvZ+12A7HB6zTc7WsraArWP9Mgu
k9MUY+wrhpoOV7SXC5EWFKX5viu/Fd4xYT3SkAIwLAk6dEFla84BrkSJo9o2kFhbdEEuwVbYWAwd
1PNCTHzPzXUPY0GjxQPd/IZEv8ItJCUCuDxCEqTEjJYCvflkjpN14jdnr99BWC/K9e9Nfibf1zw7
UtzXzSSU9GBWbBgNz9Oj5xugbtsMBN7MO4YUmINyljU6OicUwsBIVQU6mS5n7ukkUdFEcP4B49Gs
bZ859zc8axRFEl6Y2uXVfwxTDqcw/76kDSGY+SwGupp9UXLU79GRMfRnulDrYfZu4pF2lS1GuGCu
g9bcrYr0ZSJnipjid0WKOvZXh7fVOrTQiaf1uEuKeS1wDoVAUDy+AYqx8S1do7Xy5HvPHMRO9V+A
Jfd1iB26RkJHYmWpDYSX5lw6EH9Idl/54Vi1kacy3Kikn4TrSPpDKS2smAblVsr8LhvF8U6XmHf0
mCjxAcEuwWO+lhJj0gw+OTXhnm6MJfpTqPTJkIOjj6YKEugLtnkvlNqGR5ZbIGK0VrAT6RqtBPTo
j1GxtHpSWMzgdok1GusI1qFpXRbhmTUK/xOpLUldrYOyop4qdJo06O534y7qfeAYxHfBfEj0j4DU
uNzLu0dk4K+JPcvtMS9nNQXgfS6YccE4URJRkEywTRKDZbeKrT9oN9iC4dxI6XKynjWO+wZLfBrM
qG6ZIeU9obWLt1Qq3N8pih1I/Qbo/umY4Xw3aLEXO0tObI6qtNya0141JFItc/e4U1zFhhKUqbtT
HfV4m1aolnL1Rla3CitE4APiJyDcwscNXyZkpshiVR5tfrxqoFOodk9y/kHLNRcIpkDzdbXar8A4
EwhhMq1t/3RpK+7vnxh5LdYDJn5PcvphwZiHlfz6Ulaq95IcMwIn/tEniuDDDaaqU4Cq5g8nIGtq
GWYBPB1N4CsF4yBSKpJt0zAW9XRD4zFcIAv50iXiiY95URuDHSZfO7hNbf0Y1gXihLSxcdEyNaEs
7nnC31b4oZBmP/1RWaAxGYcM7fD8k2gSSlLMBZ2+I1H9IXcFj7O7BDOzjAYAGInW/2LDJLJvfrT8
qf/29gIqwcbSm05AqKKTJM75JLoHjjtl+SqaC7gHO4g8mNm7J8Wt8F3q9Ca/WfYMw+C4BlrDtwck
EWp2qSCLHsHVTAFNyDUhkqDs9rlRSGlwSosxBfYTPrUnYrl3UU9lP6FKerDWFVA/VJi8WVcWlMsm
EHRzEyLveaK/owbERYzwWIbsisnqWNvpyI0sSvbGjGmkGHTc3NKL6sBontBxI4fJ36VAWVhR75KJ
3f13s65AFP0OE9bPdiALOUoVMWsHCsWZfY2FQUQaXI8VGSJC24Je2sDc2JKJULStyjATu0DYcig0
FcD7YcNWwOEk31ICqnmcjBbV0iBwKCjE24YgA6uxHOz7yDY+4D9qJFRXaJURoD+dYjRHHCxd/X7q
dWfp3Y9S+T/SmMi54SdDJXZ/xtHwJCL+eCe/ABIpaWSUEBRqK6rWTm54KS1L7BvsfOBtETuI545O
Svp4aszyyD8r18jD668OzHK8bap5ZYpIVmtcbBPSz1Xz0fPuiGqCbn8PYQGa7MIAnaVOz+y3hP4f
f41GAnqw7JWUtYZ8Cd8bGQTBlLyk1y8YxJ7qUiEJQlVonLR/wbStYcmzimhOmpV7prSBtoVlWmWu
Ut8e8RU+fiLEzqLSpVgVfsHM7X/FgXZZP+vCIo4FKYdq1OaJfozGC0KzV0uMOnd3zTRsDRSFEkfh
l6UVXGReHMxPUrY+scXqPoIY/SDspEIvghz1SzzosO20qEridS29ZX5TPVVJ01XFn72XJysOT4ip
s2kfIt33LyuixaSHB6xgqBCghraPUUPWC1+zfges6LVzPW3sH3ccYEN/xeaOozpnL1AETaawMyVq
fQf57sXMWd7K8Ry5qqd23qLhPYn7a4CCBhHuGvdK/OB7PVcn0Tkqo1CVt/nV3pu6RDy+lGqs5byd
dmlf3/Nd9Po+FQQ0Bi48a0/lOh3ib8mqJDywRoWeNVNGELDaCHqq/Ce0ZGDHlmRHP2mHSWMnWH6f
Nk8cPwnrxXpLA1mDy0k3wKDs/AkwkFx4OpvYd8xOLFEE5IRubWg9c2yHnhf1e+FpWs+kF3In0FEy
JFhmCvrmcpU+lbRugvNnO5w+4v9VKQhG3KPvSu89OupW9eO4TDeWBTptjPRly2aR75QIOgTbC+0S
UQoAsyR6TPKj+F9YvzTVvme0A18s3+2EueZY7YjXLMthcYBXlmiWZe6zuwzMCWzhnUeV4rZPd79C
qT9R4Xt9SqDAXue9aW+ZfgvK/G8wlq9AT0KQp5hdGxxmkLp/ik/VtQTlTyRWaYPQ5pWSUmK/Vmju
6s+aEmNEKHwfmceu2hFAyT2NV+LLms2EVh/ivL37+o27fUg++OdbGqgo8dtzHS8LjQI8x9BsCyqw
s9V5dguN1DiinoOiWMP5aMFA80xEl8SPemkdd4NOqTymDyCEdCjh3b118WDJxoUgdl/phKoHoTl1
Nt14wfSK5y4gimENqR8XD/Vol+rjxqSgLpTggF25zfiKOafBNPfN5saRhze9C+mA/hdLXGmeChlG
SqXkK6Ty8owNWriTd325YgvVCwDt7f1vCg3QY22ealRxE9qvZwL2uad4SnfJAAuRNx7+FIVJEqUd
5WZPyiaifdiUQNk8/P2z2FtgcRZpBD1r6YWizFip0d+ii9Aqlazu1wun/tZBEMVEVch/1+5R/73T
EQgo0sTCBM+i+kEMrWWiOo+B6RqMs0G0enzU1rEsUpQ8GBea9TYHmcegKGUWyQRYS0/h4ylxWNw5
eHoEVZr5+Psm9q9uVvL/ZK+WXsDZX4tGJ3tfeF4C0HgLP83HvH+LTF8Uy/59n5ITVHf2yx6KWgIb
ml7z9jYInQFbFhSLOMfOUMfEl6XR5nsT0jcaNZ3ALXTD5oi4oDQ4CPCSEA/7oYKgTDBk58U1rAQ8
A7w24VTu/k9YlLkCu1giSjLcR0/BVQuum+smiZbEEfXD4B0FvKl9fCWJaqXjH77V/pX7McPnKlJx
Pp+KSvR5nbgyL6nKz/xlMAsW+9+nuqtLsJRrdSDziXrfzizsb6pA5jx7fTQoxA27X+IlfKp6iMy4
JZDjxn7jYj+fwdocp4hRH3xKedGhc+IjIZyZFuK/oCZRNThl2vRLN9IgHLaP1KtS96Vtc2SEGZ1d
rtLFzUIo8l85CsS5G/JpelsYZ/CcSVJrFoTMzamv8n+ZE5razuvdtufdqDXVkY75u9gQFpD7WO8N
U+Z3i8L9qvUwMH+hz+1TJjwSpVldCyNu5lduRq6REylN1bwJerC7B4z8lTvUFQdiXionRA/HBFsY
IPmGcGEBGwzN3TiYQsD02KfuFaHy2GEAxhAkG4OZcXwFrNfOGLdzSfvlAB00MWy/D8PdjosufV3f
KJA8iMP8d2EYmn0GdW3N2++jbxdldwJWKX/cmPNE760xV4l0w4Isc0mpsKwCh/E5uSN+gulsQQlP
nBtXAe/15HKCI15E8mPHijh423oYMwNQNFk7Qlj0L4PW+u5uH4Bc9g633QUHPXvRJnc5p/0WECLe
MUVLb+JcUtKZz5dEL3hrpQI8/LUjVbIVmm8nzLUt4wBuJ6ZUxscPwc6uIIupBBiHYlCiuV0XP0Q1
VgWPnZesZ4nWUFi640PsdvD7uoF8upNX7A9g26bvUBLzCceglpdHxGS7IHt1MeRoJfJIgn57aGgQ
TUDdOL4O8amRFK328AyynfyoLNY31DuVDK2P4nN7SseuzcGIA3LMNB8qNSR9Nc+5keGMRIm1Dljm
5uztdTvAZ8wbk7rbVsG52Cw0LyyjdBxbW8otqLurtZBQqecngWOts2it4PNzDKxZfynYDDoHxped
oAy0OGAXj0PlhGrwO+IXqtiFaHKbC7eMoFxpwi3+nl/GyhQ/sTgDdRwDyNELxFKw2JcbNKnCF3TA
HdZCTdcAuU/LTWg725IhFbUxoaXIBB+EX/9eVeo5jJ0PsaQ+8RZyAvv0JeNyzQRTHZV/fo80F11w
6TO3yP/RMe8WzCVKXhmUEMtxdMoJlO0yBImAuLJ08Lu0O7xkk/CACsHaG4hHsX+LUNdJlE+I/3wK
pWoaJyX2GqoszfCGpVeywl6EWBxcawC4iyIiP9xx0UPUbVpc6RFeSc00iCsDSBZwD/Yn86D67x5g
Ymkrm47+WOq3CNWg4cHJB12TX2Qllx0xMIJXV/uU3jTtHoLc8sU2WelSi9GPmFQFfFeKE/aRnXO9
sPL4uVjyQ9LjRgxaAmBh/AWzhhdK2AlEE8oJHHtNipVtTFRpikFSAxLDXPqj3DspsQFjMagFJ6Qa
GkiudxKAfINbqHyWMZBlwZB3Tcb5fw9WhM9lSK0Z9xLvWeOAJpWAfuFKJDNx4Nz11guy5mhkfwxb
xpObV/kRN4/UVeUEvrYAAMVa6eg+XYvN6klGx9W4AYCSUeUyY4fu+I6bjkJI+q2lupgurU2ooCOV
CeF9GTDyrc5uc76I+/yTkjpOzPcQslJZBJoAbYPrtZNPl15C04iCodkek8HDAG+vs27ceznVIH0/
84VIklzu2KbUXt+ucIkB7BJ61odvz0ae6G/mAln3F5Tp+fLBNUDghH2+Rvq8QcQcXC7pUhdtkAl8
LGhFzTrJoBFAUF/SVzSrTSIK7wlQK18PEyz++BjkD/fjdpVCU+ZB9c7/EI+8uLCOxhVJr29d/3+u
xhIouaMOOUKiQdQ/58x5Vfp1zwIUIdXAUE9mnCSBS4WIP1H527dWYPFq/LyMfEdpokzfWGjs1BqT
a1B1Nnrj3dAsHPO7uugOPXrPu4IaeZ+P4Fz5B+3cTPADYw/Q3zdGj4xbFH7g3L7AXJK5M81N/tTH
pbGdUTVmtPbzmXkgLMHOHpMbCV+zwZP0k2LULKS/94WJEcsK6UWKOiqqS0rImAroleczXq6Uqpyd
UK6JVaEmVeGj4fbXwbTcY2oo3Bg+Xa/MjqP9ne3hTEPoSQ5kfvUBC7LQIZxPgOu3nzFUIM9XdSrH
LBktB79/KficCBL4PDvQieJs2iGp3mdFKc+acwtw9IuNx8ZtWQ042/QFKw1rfml574YvneudKHIv
y+rVYx/4lT3fTvUAlwkfJBkc9vLH5qnT5bm2lHK8uMLzq1HrSXpJO3qJr6WGbE7A0udgelnUbPKt
h8IkA0OCG7FOH3Fj3ABm4pSSq58rVWE2YTuoOkh0oEG6S1ssMqFdS2c1XL4SIu5LtNGTIkO2+T4f
4VeNPJaRILB3antlKRRA8QJ/SWxSuKn7CpXmbKKZumx/2ns6gaNce1U0t8QVDOi2waGQX2HKqUPk
skkSXaN4ox7XDO/lDdeMj+75AzTtGdJGsxDeXio+ukJRbNw8Y7cDPNiMktdjwUy4H1qtSm8sKdJ2
jQx5Ani8Itt6QO/x1a8RwC73Z/jZjT5a16NqXbHfh82pMheCEcQNcweY3GDrG5u6LTuhThjo6Juw
PzGZ2GY/7JjWS1JJO424MaOICd4JGLvbDR4cZDLjABRhFignrkplgW2JawpK+B83t5LV7KbdhEkW
/S6v6JOegS+vJPpXIqjvUUm/rlFBKCPUivACQhu+LkBuW2kp9mJoOVSa+oSc3zGY+WdqHPpau2yX
jytHu0KBB9FpHnjyKFegw2Tf62h6/zcex0HMFhcZrdyPjs45ZZddZj8aqbQKfqmmlxoJqWkKNWFe
y/WXReMNROhk3GYox/1n2MMBw64GLYFbkNT/A89lKDHN/kssdHXxMNqVewFeeJxnkFPZhXHlq/dG
301HoXzoC/XQu7IWQLF1k+aNWXpXHU03H9Qoy89JBpCJTcOjoLeRnjDucCEc0HKsiGtaybX2HSKh
Z6Ygl56me/7YeKwf/F2o70vXr5NyQrvHxX8uJX3ZxI1LlEgLsllT4/0QykaCxxPSz8Ibj2uqLKmK
FakO6gM2t4ZoIcMsnSIGlZg41FKF+6GD9jxxHBNDJfz4nRQRg1kWlEZoY9Kp7Y6y2Y68lwbWrLzV
s7Zyio6oR/k5Bxoqs60Jlkj+teXvNODaJPPjOzhB+08fuACiiVH/vry7YRc5HvfrfRvyu76elHbK
hXqyh2u178tARx+gx3y8AxWBTcboAvnsn2tCJ+ECcb38+Q1KNzVUpIlFdEEIVX//Tj+i++d5rVrP
hoyN0BfvBmQa2rJHThU+JHxO1ZbiatkqdfLP45lY1m5oda5wjG8DfJFvC35XYxEKTZ2vFgqIMorG
cPViZPn2DAt7C/Uuk8214QHf2SiqOOqAJU1uTFKIlcyf2QYJ4Aj+5+fyw6es4GlFxnPrAfQ08u3R
zqzquaW9LGCox30btSJte6BIc9Kuf2yCfbVcToGPR62Cmb24LdnA0RJzTsv26NRBLuAIydhtME5A
8s0snwjnbRscAkP/r3UEQw1WL5RWVHrT5tJWMcZHpbTlmF4MqD1d/hC4sb4nauyBolXngz7ofOIk
UEWUgUnpr323flg2YNXvRRJn0rKlv0cUEQ+J3B2iiIR9RBd30Wr9AedxROMJHes4su/IV/0PrDbH
43KB5SCnyIiYmGC18JlEu7WQOQFV5Zpx+NRmbc4TsKmfwEzq67Cmm/ONs2yq5cFwcO2OLDfZlksc
9DsDvayrk5okseZqns1zWL7v1jxe73byB4CCw8MYp5KPjMiXUqUtYILUCNi2SfRG7wkmOT4YfT1x
CfNYuPw6aVU1GkkVfJwc1EV4hpp0yqdkaMs+BqqPgeOi2iT8PItc5NS2nm8gZqluH5VhiOKjLykO
AvfQ2pRCtqo6baaXmCp7J8uVVpM4jOIkoUBgAIzqXq+IbfnHys0aQMSsKRXUjwFxMs1c8orLKLPe
rpKPi4RSH0Vv8ioRsp7k9sURW0ChdxVVnMGs0Q1ATiXXeDdjUwMcSwcd2pml74Krvihf2lV9J/ar
jzSrrY2ghu8eoWz4X4obYlVcHjSvIOPWd4h7o/uDLyu36cLxtSzny9pAf7JeDSQbRV3A1EIMXiGW
k/W2gCHk0Co4jniqhFQpN44VHeBuHRCeMRp5Sd1bqWQCKPGpe4tNYLOgxCD5cJC/R+xkSv/e6l+9
VV5zbWvjkTtV42dOr2r2OqOjFIL9YOOCZ1dqSyLhrTqz0XQ5OAYctG6Zi8ZvBQBYYTsVc3S3UZgh
U+Ss89hhmHng+gUyAnkrGr6v+sTdKi7ogVmkw5Stkc2bqDsR+fmn8fEpweC8MSNuoCv32HoLLPQx
ygIn7JzGjLF/18AWf4yxNPyubYzBIkkg7+92v5epDK6j/K5Bq6uQiCw73xLUdRm4OqbbwuZUUHQT
oShhrGa2zi59JKNrj4pX4hwuY9ZVO5RGEQ3R7AMQirmJOAjKnswh+KvM6g3XlkhOiafaD02DSJBe
xdsFCQWDjfSwaJkK2NZ3COpP5HlHeT4q2ORc7Y8h8ClWZMBxjtuo0QZeV05+CDghzKWSBAhdoqxp
z8V3V6eg70ikdnEtRYCQhc2b20xd3j1CmDMd5Jk0qI7wm1V1CkY5Fic+6cel3ELmtLfViKi8VdHh
3HATHjBmsn2xAnb3P6yv9u96ust6Y01j12OFsW5saVwpy+09uUmS/iKgPvkWCvZL02AErJPVwj+I
OHmj2WTlq5ESVRU94XvP235rUOvjrlOr+gJOn/Wc/9fpA3QiNnPhuX0aEp8X7byRE0h6XWFxD+ZU
EP1AJ66a5iDTPtGb27s0rQBucQbGTxeBtP+80KHq+x17IaAWpCWWauS99kATXyvVLaVP5T7ryt25
7Wh//gDWfyCk/rQxuvRr7hQibt0mUx7npNQLTElAQHI2EkSQUYnkJLCgEmJLHbYz6f9NjO1OsDTX
vTcmRlt8HNOJvnAJu3TmzJkrqA1kD5Qt0U4r5xPuSglDwaOfIPhmJ3Ot/liCX63ZdQJ9xRFvfPij
pXjWGEOa/Ow3MC4kQ93a0aKCeWaUTvesx/KUQ4q0JwLRKTaqeiyWLTFbPHo2H4lumu+ZCwMUv6tR
Mp3hSk0KFSLN7um97m+pyaIMNd2TGNNLu2J+qngWiduh/EErJ3U82sx1KxmuvvZHYyQdZ1q2aH3a
Ie5IL10TYcjKwc01tDfb08N77ZULm1SDynpjdbu3fbHLMEatbKpgKlBqwzc540kmYLFqb//0eOKn
B245EBRpJLR7uZaxudfgJkIEP7b6+cVG1KSiLQ5JNu1L0fAt9S/PFdXS1GToRKJV2FgDmKxgmKRz
6pR5K+pKcyglu8ek6vAj7IH5KzHrHrX93un/KIeJJLEWS8xUbsFpUELGcXMIbckCpB1ZJdvwjxBI
1q4tVnn8E56tjmV1K0z1D331yjUoK1AvDvIVwg/KaPNvAW1EYQFBHx+Kj7jgO/eBBhEZ/3Trnt7I
lxyJ4vOcoRa08DYGuNp28XFw9CasjpT6gN0xbRl/tdepQLF/X8UTxRgiEMCkJdrmiM6pfm+qtaxp
YQJDY23Ynf5Cm78rGkRrE9JKC7PP/8A7ukSYqz7wQUwB1yYXBHfbhDA2uCQnRQuIgvDB3gST5+58
MBYCJKMhkETHNJMTO5tSggCdIF8No5bYqMuYA+gucmHrMU65SnN6MSBmhjPjgd82qtcdg08g2pGA
jX+ycYCZ/sO7TULi3tKqdcBF9RazbXu6PMEqwVeO4DJNyGfJoqhzn9JfiAjDUSSFzk/jwTNtiApt
jpjBrtUgTJnLadZnFIPUEzrSQ+CHO6rXJf59IhmjLZtKX18WJxezlfB8a9qx1G5W1Vo8CVwtudJ/
sTC8feAO2Aodp9V5b2Amngc8T7sbdLNUriXOo/jEetLx1uADBht/vWC8XGAZf4dBMCeLNFoA+n7G
GSgEU99/lyyrzdE2WAjQCJCs9zWK9/x74kKeAlxSURz1TqSGAYp7jcl80X+CNGYBvRbas22RHH80
CEWbGwEWAHWLovhm1BRYKuQXCeUd5nDmjDWwdiC79rzAtQ9nm4NDunVpB1P1q0vurDr2EeBRQPyq
jqYvAO9aOMHJvy7vPyKCgA5+OEIKbXitrA2kjcJ4JjIa1VmhU3ozkx3ZXQwZVdRfLEye8EEJrMY9
4jW2SsV10CHwdHhpE99yyAVcAsYnXioapXz80z4WEXNnFPyKQxJcnd3qNKVqzlb6Apmb0TNaUrBn
CBDClQOOWQsSIcxyXYQMlKuFuXqyMu46ejmNNwyKkQLhqDYpw+CmPHNZkCMUp8mbtbBa3EwFf+AA
RXYnbsKQSx877JFXv25iSTacF45QkYFbNwvEy/oxWW9kwOJX+BgGGMzvByozciFBmrrwRr0rbGIX
b7hCLgbG7tGIwCb+iNB/jPQqCwr1mkAxr6ACypEJ7VFTeERiFzoB6D55fqLXKXEa2m8fKr/1eLRX
PFJBEwrMi4PYIkDbNk0Jmzovydk1XGSFbPtZe5mVdud1GD4++IBNvHrda19Dc0FwK33vjRylYi/h
dKhm6EL2sfY90dbGjFJ0iQv/1gTyP8BinAm5vEEvffnGQs+ZB8g3zYIyjSQXRfHm8Xh6eg44vEkP
UnCSiDliiSeXk38yRO62eIa4cZhSTQ/DdppQ3zoruTPnHZX8WR3EZjtld5icFrEXOVj25owMLClY
bvtBsoV4l4GeLrvqOKdFUe2SvcLYFONDAcFCZwz4sDqBdTJdZdMnHSGF15RfSLIAVsRG7Da2Jw99
RXF/Qy52Za5CgLcfK0M+ZJGlm67A2fwdO8IiF7zaoH0UiJ/aVsghPYRwV2fnjFp+1t6aISyWSbrQ
YKu3zwbqVBT+GlKeEkB/CbQaHmwXnixG5A7oJyWVA5MKHz2EYzn4/ORzLAL1P2ETcJAhuFuBqvlZ
NKl34jQ0AK4GhOe0PDBdwU53yr+tzEbeJlLeQmzDvqmIleZex6hZ9kLb47Fm8aRA7JOVa1Lb5WV3
jrOsej78qExlzpSJUdz8AgEE9FsEuLz7qAegkHgPTbwiSLWdu4uT+eoZucAUpi0w17/vhj+GiYzb
w3qRsA+MJ9MkEYbRCH0rR3+F1jpja0FDHH1Py/arHCcX+UTL2Y/Xq+OVv0otzIyTTB5+KrurBNJB
7MVY8JzBOSLjNqzmEsjjoRApJjv7VNnMIsXTKe3tv+6tpjAAJchjFwTTCLWH5kh+7d9cbz5QT3A1
NpQBQ7vxcYf+3IsLOSqiXKbg+2o5ZOyq6FBFoR/78lfTUXvcLouAaCNpIhvudAiQz/FtptG98Xfc
HBNZFYU+HjndyAETUTB8dkgsOaMj/t9uqEUokNnKaaIrunjGuiocfwOTSZgeCNJgNgYChNSTxhyk
iF6pF01DMwvuNTGzwUgRNuRVWxZCg8vKjeyy+UlkX5poSJGTzPzJhgH0n3QQgE57+LgM8AqhDOqK
VhdmLIXecYfVnUCGhWhzpS/WiRiz7g8I2mHfjmU28hMZ5LCMMsXjndpCFk2pv171UiFgamPSwk79
L5yR330tfp8DSAtguSfNnDgp4hcFWqiOryXJykDv7y0KLI6bJnYNOF06vATpqkrxnpYhRrhXQxv2
rfoiHupBFJGz6sgcTke95+KNhZSdHmDFoJFIvUR3D0vpY8MlmHG7WkM6HDORKY6I3fxwJt8ufk+0
DLgC1S+5vwvEDrPgtEOxSkocg9G2RiYA9aVmRFJCP7CAx/OqX8XVkUh8LktvaCt1ONM8ZalXvEMJ
9UweRfgukJuUgr3viuEiCOJwe7BMZ9p9I5L5lRCwuFLqH0HesoSuHwwqe6KqGiYqZZ9u5fuVTlEh
j4iXMGM+sCzzySbt/AlKJKhxzT5vJKEuKZyq4EBoYndL0NQto9sVkQpn/NYzTNz6WcDOOoJokp7V
Ujmxo3bM9OIh7AmqK5iYXDWjmRadqK4SMLIwg/UIEJsHyXb3lQ4B4x4CXp1//g/6yU8Tu4oUnt6d
G/G1eMk3zrnLjk3Vqevh53FvhuZQ3lquETsNfBaXNzDoeRyRx+ALkZvX9g8qNSwG4BkjxM4emzZO
gMpjFsMEJPA7+K5rhGd4q3DM3Oq8pIS9rdBFX/7wBThpj554ZgK1CD0XPgYg2y/W1SGWud0sOpYp
7K/wgBm4nTGahpZwtVxj+fgIjAFxqJD5ii5Zlznlp6XH9iNJSM6QwPPq2UNWdsCE7uyPw5mC3jLy
4M+1dClNGIFzgYz+ypEANAYZH6F5TENuUia0Myf4k9ipE2dg+P56DUkLkcQTUmCetYUFwSrLEDII
v76W+GjaA/QY6D9eVwdEnjkWM532B4QcMAEC5OqAXpZKsgmXf/97/bFTfyuosZDcOPVEmAyzQfHu
bNDFMmafbfTnoF0r1cxni3upLkypbsI2hwK6HAwvKHesHY4goGwBcR+l3HPI6DgpV+s6fZiN+RDq
tG47bdi8wBep0HLXGdTxeb1AHQO2I0co4RjrzLiOaJMJyj717yzwyHA6eXipb2oHlQCrZdINmpRE
Oqrr+NxNYWX+VeinABp9as/YnfR1z0HrweXen/F6p2bbiIOZ/k1Tqfw7arUDhWAoeabijv+dIKXL
X7ViLvnxir4W9eMnurEuezKJxuJeblQngakRcP/GEzqsDZgafSZ3bvH6t69Fk9F3M7q8CA8dzTnS
P1upJYjtV/CjdFqL6XEhtrDyf04KUyIJAUw/dQfOBeAPSPl5SXl6qbCXwYISDkDLGDjozRtcDCxc
YWDykw9r0mBymsOpuEwwwERYYhkYXl/hl0Rr/qlWq40hAg/EqCqxIJk5UzE/Oi/dmM89HHQf+5ii
ifdBznYhB6udAlSxKa4MmEi2tETgMufxKhJ4ps8d0OEs5etUoZoQkgdlhejC6r/E75zRrgj56Wxs
xrnrSNtErtXp+GETOor8SvttN7F0Na0vM4IcDIyBAAmn4Ubn0Hq99zhCsBFIq6Fh94DThoAe5q82
90Ei3l4r3grvPqPlBeK3LH1Ckx+pLNouTRZtbjObmaUIBfeOV8kDpVdu9HK+WcbNPoLy6gvqTcHS
w7L+EQN37Q4N/ghuXAmv4tfFsc6JJ/ubGy4i73tfZCFuNuCL5x1BnbkuNwNQM1c6+XQvtAeGDQOU
JK6hNM64TS9at2FHAMI1CHEkioXkax3TDllYfQx4YdD0pf/9Ym5MWE94/MgBMfFEnUVUzX1Z6fZS
NruGJOc+Z+jlGIR7Um5iQsondwnJrYZdOrGJLaSpSK5BVNRd66jVV3Oa9wTa4zO4TEi8o64SzWQH
p7Z/VCMX8wP8RhRiH70EIG32yD/pquz+QA4zzKWHlGY1zBOqHAl0xb0oLUm+cfnmHnqmHDTfRfwA
J1XNhctG6wDon+oEI1SSew83ALXKUHwD/lWgp9m7ndn3TJs9X+t/oEWnP+TeyOAMNKgoXn7LmaSa
Z66uVNo0z8o3yt/3v+J6XqQDI3Fzg7ZspaAzwOJPL3O02ClqVQmINqiJm/OPKRbe/V+Tb7QEta3r
zq6BRBQysULFNMipOXr+nVz0MZpHqEoDh5ddT9BgIwicywxykHsAXwjl/Yti99Tr8u68+g00Zr3U
1xSGAsptRxf5y/TsUhZNLQNSEAkLHX0GfilhfJvQl1vQVbXNuoc741AEb/rtErpFlgioGo0vvcwd
UVVb01l2W9YB1f367H1WUevJgTp4/Blwll7D/uKXn34Ooblj2mEQSo/7i0ewZ9PE1Yh2vuq0lMPI
PFo9/i6hdHJtwm4wOI6iN1dKRQdTA8njmKO5Vnni23Dl/W89a7Tknsw8/y0i/gEpC1u7QWClJcKd
A5NJ0K+2rAsTTyi9Ki7Ql75bt6uqhCrnDhivkBTp/qW9wYKv+7uT9AOlAoh3KJplRO3+KN82N/c7
GODrg+wHog0KLxFrNXWfN33qDpu+DbVB3AkrsZsKLSOcb9vLmTQDuIWNT/xU1t8PIyhW18Cj6Ap9
pLl7vCa3ECOABSP9rJIGKKD4ZBMjiFE1ljEUy4mS92RKf6AUysCOd+pzLbDgtHaih7maFjxT/6c8
uxyTuShiYNB1fjj4y+sJaX2pzU3NAELbMmk48lvhwgkigfpoOCGD/qu+RjjXbYYNge/Xib1paHZ5
lMe5fJ8WwJS3ued46QAwTQQMXwABGJigyBVtUR8sQ/Pg3/PxR0WIwcc4IRkAQjVnS6cxvB1A5yVy
y9NAc0WAU7Ux9qUgwzdDVyndhSUGTe+BsE+ivHhMzU1pLwLfkRFQQ3x70AtjY1+4cF0fIV8qxgRg
9ufzeejm9UdpC1WDodmt2TD8gidqnk9fWnhtjVOo1w64n4v0tocpRg/qvFqG1HjhQioVgS+s+rmj
qHHCCrEPpY5sOl5pW2LE8ViAaHt12tsFDFXLvO1P1IFlMn85pqwAr8SDz5qYDU5NLv+qcdn37WeO
rjqCwuMOEYrlul7LHF2c5oKBY9F6A2wuP+1YWjWS9Xegnz+U0XiJeoEu8MGThebOfNeLHUkPrNi8
akOGS2lnIRjrzU25Xvj7Kw6DzAvke5VL+EpVnyreAbZICKN/w5m1mKEaqCEfm+BK3To5xuAVBthu
uCV3Co/29e+fw+03hMbBYd6LPS2RqFOBFYLRkv2nxOieAhd+v0qJxhjnvNPunEWCwSED4sslp/NS
kBn2JD8LS1LrjT13LLMoreO9Zvz00tcIlK2ukLELWTpchLNZD/YCB/Py53IRAwS4s8R/AOPPtTZ4
fk2VIVPIScPBZxLX5B3qGJdavZqij9VbWgrQA1PLR9Xa0I3iZRoR31E9ktp6TAZmRf/lWjY04G3d
JXN05/IGo1r3KgpvsVQ7Iy/94Kqfz3Dw7gKmWR4SzGbyLAKMwvXFm3JTu7YDEMBnjTXN37JW/UYd
+eeo+DxbkaWKd/5CnlQ+v8DGPZws4Xc2hdgcObpBH4CbTijbntc4ZsVIY8t9/h0sT/0/lrfqrehI
Q0fLjVrTPna+S4UJJ+OFhu7dUUf65ztfKqJly4pTtRrBQI4hH1pAlLI8Sz4ktVl+90Dk/vVFnKO2
Poxf5vjhTMjHSsTqFNOzIiDnSPIgNNNzl08YHIS8f9vgHwmy1q6rIE1kG5AsrplNb/aserTvwrZG
DhFW8l0El+/kPDzJaO9vLwoPG+HJ/Mpd8FKEnaesn9sWBvcAn2Uzg6H0ecdgrd2hzVxio36SDobx
oxBOUq0rY3G2uYpYN4F1EPpBm+oZvVtmcRg0GlE35szEc+QZoBQ05SEvPVag2ToQ4aWxptJYmMrp
AtB24oBvDPHymLJZCfG7iKfT8NwvWgaS5UcE29603e0gf4Ai3zRp3k3UMllq7JBFmDGNVslf7XQ9
VkoUuT2TJ8U339m6ZChf8A+1KVWlZCOfqXlveUSDpjF9hekHcO65edOxlRZobkJQK4gddDfyDeWn
ZLwSNBxmW2KlrcAJnm5889oFWFvR/hRqdZsNFwSZyoIPbYAWpr5ZPhsxIYxyM8McVfoKOXaoIUpT
fG0KGhuP/IZ3zxfYW8kSgAzgvi6gp6ObDbl7tQOyEc8wT8jeKOF3fUODjmLtPTA4GqpyEjmj37an
Nv5D2T04U1Gdc8/skysgO6OneIU25Ist3vaD7tSwVZ+lpniligI6ovvbKKsI1ZklgSRf8apZstIn
3HkWdMHPk5qyCH99DKk6X0DuqPJ7uzGrPMPa/H2vSe7MqlVm//9pxrQZPjtHKRetuUQNLfO7e0DC
QdPiL/rFeaZL9in1hf4lEU0BnwIcQyED656PAdd3FcHD67y66cD2c5AM4YpmOGUHz0Cwz+HtCjgD
8ZsgNdGrM5E3xv+HFUhvfwKb3gc35qQ9ypP0+dJuvwmbkxYtwhPBEHjPR/iMCAMhDMvQdag89Mt3
uh60fjhIBG2HQOtpVrJE8htMn7SJE5GxLrp4Xx23CL9gwM3t/50wodh62LRznaV0ZLyLRVYn0MY3
imn0VYhUOG4mnQP07wOIYGwsSuif2BUH2QT9C+RrPmlyb3+dk43YaYb3b1RH76dspz8IOMVf0d+s
CsxVVtd/Rbkwh4OEP1Kxlpw0eCLdmUwA0pBwNuiLBNjptnswx1XzyboC8dMMZsJ/CtKXoMDvF2kO
n90jLljo2vKxtkA7iRWPtZ84QIeZqboXpBJX1GsIAeHRWxUGHt06MIkN/RIbTfNdF4nKZt97Jtqo
+TuVli4c1C9BT17tPOoSix0ZcfpryQVfiSv9wjJhKPtFDX7oKxPvqWgCyxvXPqZ+bg8LkJZuIGEi
nVVHusnbVyNSwDENZThz9TqwJP0XlCgdCnYOuhFJlJZW4Vq4fpI42LxDTjyCmWJOm/+2wolKXWlE
J1xbjG86p4R86mZcn9FF+bu7+bI55hf5V2/HAoB9PEAxnObQ0XSvs44YJQVE75pK/ga7ldDLjFt8
wJWIC37ppfX3/ozrvtDDQkgjoc3CD1ikaM6Y0Yv/0Ct/2BLuK9sPNuTuwFARP5QBuEJjnIZsqsT9
JpBdnKhlBeiwSwI2IHyui+sBStCNu+/giR2k/arLBrUpcisJcSS8X8q9xbiWpJpjY8Xcc69DDVEO
lX9+RxzkYEzQbdQrP7U5hwWEXHvudnECaAI2Miq7Zr1a6oQ+HTQo+cU10hk7lRSHKRCoZ41iumzV
uo7MjJeqk3FYgMJz+lj6ATblMzI1r34MO+/LTU/jDFjkNYnW9lZ7tZy4M57i8WvpYHjM/t9FDoNy
ZSWGiaGQgsFM8Prmyswpdk2Nc2FmaHe71SyhmM/a6v78GCNMfqV7V14VYTZlJN3UAC7H4Vy5gclE
CCvG89AVB8BxCRv/omzThftpnJZh6qFsfbyysnasB9vJFDXtEydAkkJZj6RYxoyAZHtG2sBT8HcJ
iAntsYlxEKWIoLS90G3CqEse2a3+pTi8d2m0uX+wpMjJLLb4fckdixYiyzhqqCE+M1NESye7CYnp
EGyyQ9bq0LsMv4wWJtH2OH7/AsVB1knRsIDOk34Gm5l5a9L5cKdptaEwMti9pQ97dwO2TFY8Afkc
dhm+KoBMXXiD0CCJJTENo58gM1PNsaGv4Vs44O8gLy5m+GxTxrgXt3X068ozuQqW7wUMoMwiKwpm
z2eMZ8L7kNpb03mJL2yJoRVFRYjFywpRP+ElsLKTVfsbTkYdHDe8H87vVL7i14OAlfi5/oyZUcIx
TyuElN+QKarUfmnamGIxkEULvaGQ3iiX3Oov/yIQ9CITYMrOlxXzFyzYaYC9+oXllyAAfUy69LMn
Tth/Owxa2lxq3Y8wVez9bMk+hP/h8ttOdKYgBd3LFvHMgg0Po4VF/saCByN9YHApp7znD1dHtdgA
L0r6CjRkuc8tZtoYXfn3p16iGy24lo6G4OI3XSuD/bxuiExpjOycmLQHqPmz7AWCbLxcUUQBR+In
/e+lJSviUdAw7GLGY7hWGl/uS65Ih2yJYKnvdRGRxAr1g5E59v1EVU+7gz5/bQ7DWty+fDXA22H+
GFZBGcpWjV+Si5mTPmrQvWIgNrrmLDHNiIaOEd2uQbW4XBC5e1cVb+CbvW12L1DGXgJhFODNhJ4e
6/VmHau5+IlkDLT+xe9OZNuj9i/hrNq6nJVCpH/+O4fA94U+i6M35HBShvgrATULSEA/D+0WGsjb
wZXgPHeifQ9PvGd7uKCW0zebS0zEmpmeiRQCnl5VRphpk19BpHERtZc50y8dJ+0TOv2R/JLRhyiy
h270KoTC18aUT54bBbYX3k1ECBuoCZM2qOFD2IducNI3lFPJf0dUSUPfTAItattvh79kkPHj6E5V
zNQiN3us+CBLezMijrY3QdIN2vsq9wxJg30Id9K4dU4578WSD7yddep/Idv2gIDAH0XWmC1sYaKw
RqYTL1cFy+yLu9WrMQ98YHHdSwJo6kE2Ly/9OT0ird8KLxKyAak53DA8Ms9YnOp+wp1R+oB0FMvv
cOWJRy8aklVKM6VDybyTkU8KSAMswyWBz0VOirGDCuKITFzEZoP6Yq+gNkTppOYRSb9QOjclYFXM
efVU/cGZiRjJVrJuxjWOhWU74zL0Qra4shTp/CzYu1EVFEDwr26FHPEauY3RtM1fxvpMdoSLD4uZ
knY32M4YBmm5v+12IU/s+IKcwPu7FqoCFsu4a5yKW7k+Im7fYC48EFJFQ30BIALBt4PX85yG/DcT
D0dhNRmo/Gfx2g2O57F/Bz6uXqOVx9TifkhW95tubmocTpUsYWdeFE5v9su6weDNcHTpFu+54bk1
4Bh80hrpMFP0Sj7Npq1lF5PrAvyZyeeF4SNL1MeYGuNlVNGdoPdvSCZ3UPMvFiZcrXe3VeKy0jp1
v36wLSXA3l/d9iomJx9EvZOUzvrsl1xpg4vBrDS3lWQsyLXO58UFBm7AH134htAuv5viGdVkeSvP
HpFfDRzCF6o2ye47JUzBP9XTcVOA/kpB2zkKepbCOKmnAp3As8+KdoAA+4wCcGhf1WP6QaMEdcfx
UBoZZWSguVMCBTRYIKifonmYirg0e62SDL0uHCgvQvfCSbgZ2bm/txEWrMEvbALFpcV4nSJtsq1m
w1blK+PY8f3SFtOKecNljLud35cKTcL1UtDDBZq64nf7/HZGpetFPIR3nnOHyEw9y5T/r5eblcVr
sMfHD8nVa9gS1/Tyo8/BuszQ7xOPXSL465ANLIUMbe1s3A0rOZvpwIzAvo/iQ84xwHlHyyM73C2D
uTzMaxfIoesYdycJgV8hfq9g73+Mce881VfdQxQa0VM6qdnkaXsE9M5W+QS0Vc7OPv2mNQNxV+HV
EE4YBElNIsPPOLl9UmDhrnDDyFLphi9rahVKT+flQggQCRZ9pfq+Q40ScNMillag7LGrwd6YiC9b
tlb74kvKGm/7Ry3fsrHtlJPBlbKz8OipNVmr03i9Svq/JgpHwvE2vxW9SwDk/k31bqL2TfHLLI/A
uOlcU+Mj7HGc9Kmu3ud5wmNnMMtQjKdr+NTAwJTNYv2Fpuh/yZfipx4NKZ6yGyyXUZx+UUBXlRe9
9gX9b9zh+8uRcm0Rvu43jDmWxiGWlkmvbBDUh5tJFF/1zhiIkVKGCeuzYmVrhrLybhBBI5Aim8TE
Pd01EIW+TRhcbXgA8Rnrz1QCoHtlTJqj6IPsx80jy3fIDWMRZjq41NJjUwSQxQbrYM6/EB+DeTWE
WSF4s2IiQWMNEQ643PBOi4ZVcPple4ojnYkZf2EwykzpRcoziSARhUETirhy/OYFnJEFYVerm+ne
3wFyzHlhVlZud/so3aRcDHn6LDBg7uul+cbUp9Ol4wHhChImU5NMg1fNp7lT9dSOgoKdNq8ZYgk3
lX8fY7faItKD9YtQrENhoujkGBL+S+IH6dzAuCuqaRB/ioMmM0wenYB8qTCPOmRPGrx48coSva7w
TMfs+2/tkxqzS80nXYxg2X1rKwbYIcG97NYlYpFc7+D2H9A+YIPNJcSH4457q91namf54Za2lQc5
/D9XqEoukOqxAWdImu+jE/S+P16x6FTZswwPlXoWm6ulixcUm/AZ/fKMvt9LN7Bc+/g7BBq9dw0d
yHcbTTt5pxipJ2Ap61PPpMVSmSvoVrNO+fqsgTRIIC7iL4WiyCAFEkWBQJktz81OwSpaEgnHd66X
ES4dzMT18sYYRZqpmgR9yTzwQ/NYVM9vnHuj3F8SsoGdtVOILEYZX/k/taBH6AoFdyj7ndHQj7Xy
5fqAgGrx4ufuhZBExJAFj7L/H0XpfxQd5v5YvOoCVWyhlJy/SC5ypW9VEPlQq+z4ciLETbtahjja
+GZUFBmxB4dlcnhtoIyiXywSyYz/RUqIl4wcNgb5cDgdgUf+/K2h8IkMSYmveAMyaoqwOeck/XGF
0zfMm1tbwWRuRqLxHYebZusGJV2Ix+4cWo4t7GxuIm7jfmwUbh2zqJzOrNv6QwgbKwBTAc5kMowy
hQ64V+v//P8zpkiSKLCYdwT8ACpJ2pBqiNhBIRmivj1IkWHnyFIq+oShXPUq8QYVKLnXGjzRA2IU
DHq8jIOIb1hNL7iyexUlrTqBH3i38b/0Lr0uXVmZ4V/7sSTizCif8GQvRrVbDP4PqEuQjiJmE1z0
cqWdV4UCVDFIiEXqsvaqgTKRf/o8rfTtLmvB/rftgBXqndPcszZhSP/cWzU5c+/Uo8JBa491TthK
YK0bULTYePeFFSPxmbsM0PjYdfhip2DcuhQ93l9rKf7Z/RRFwoM6O/XKKwPTvtevs40oSw9em4Jz
btQx8N9L1W/bIiyVRv+xASEWjjs/xn+0XsjKZYc=
`protect end_protected
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_ac_huffsize;
architecture augh of huff_make_dhuff_tb_ac_huffsize is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std_logic_vector(31 downto 0);
wa0_en : in std_logic
);
end huff_make_dhuff_tb_ac_huffsize;
architecture augh of huff_make_dhuff_tb_ac_huffsize is
-- Embedded RAM
type ram_type is array (0 to 256) of std_logic_vector(31 downto 0);
signal ram : ram_type := (others => (others => '0'));
-- Little utility functions to make VHDL syntactically correct
-- with the syntax to_integer(unsigned(vector)) when 'vector' is a std_logic.
-- This happens when accessing arrays with <= 2 cells, for example.
function to_integer(B: std_logic) return integer is
variable V: std_logic_vector(0 to 0);
begin
V(0) := B;
return to_integer(unsigned(V));
end;
function to_integer(V: std_logic_vector) return integer is
begin
return to_integer(unsigned(V));
end;
begin
-- Sequential process
-- It handles the Writes
process (clk)
begin
if rising_edge(clk) then
-- Write to the RAM
-- Note: there should be only one port.
if wa0_en = '1' then
ram( to_integer(wa0_addr) ) <= wa0_data;
end if;
end if;
end process;
-- The Read side (the outputs)
ra0_data <= ram( to_integer(ra0_addr) ) when to_integer(ra0_addr) < 257 else (others => '-');
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity LAB7a is
port (
KEY : in std_logic_vector(3 downto 0);
HEX0: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end LAB7a;
architecture LAB7a_estru of LAB7a is
signal QQ, q: std_logic_vector(3 downto 0);
signal F: std_logic_vector (3 downto 0);
component D_4FF
port (
CLK, RST: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end component;
component decod7seg
port (
C: in std_logic_vector(3 downto 0);
F: out std_logic_vector(6 downto 0)
);
end component;
begin
-- Inicio da FSM --
QQ(3) <= '0';
QQ(2) <= (not(q(3)) and not(q(2)) and q(1) and q(0));
QQ(1) <= (not(q(3)) and not(q(2))) and (q(1) xor q(0));
QQ(0) <= (not(q(3)) and q(2) and not(q(1))) or (not(q(3)) and not(q(2)) and q(1) and not(q(0)));
L0: D_4FF port map (KEY(1), KEY(0), QQ(3 downto 0), q(3 downto 0));
F <= q;
-- Fim da FSM –
LEDR <= "000000" & F;
L1: decod7seg port map (F(3 downto 0), HEX0);
end LAB7a_estru;
|
library ieee;
use ieee.std_logic_1164.all;
entity LAB7a is
port (
KEY : in std_logic_vector(3 downto 0);
HEX0: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end LAB7a;
architecture LAB7a_estru of LAB7a is
signal QQ, q: std_logic_vector(3 downto 0);
signal F: std_logic_vector (3 downto 0);
component D_4FF
port (
CLK, RST: in std_logic;
D: in std_logic_vector(3 downto 0);
Q: out std_logic_vector(3 downto 0)
);
end component;
component decod7seg
port (
C: in std_logic_vector(3 downto 0);
F: out std_logic_vector(6 downto 0)
);
end component;
begin
-- Inicio da FSM --
QQ(3) <= '0';
QQ(2) <= (not(q(3)) and not(q(2)) and q(1) and q(0));
QQ(1) <= (not(q(3)) and not(q(2))) and (q(1) xor q(0));
QQ(0) <= (not(q(3)) and q(2) and not(q(1))) or (not(q(3)) and not(q(2)) and q(1) and not(q(0)));
L0: D_4FF port map (KEY(1), KEY(0), QQ(3 downto 0), q(3 downto 0));
F <= q;
-- Fim da FSM –
LEDR <= "000000" & F;
L1: decod7seg port map (F(3 downto 0), HEX0);
end LAB7a_estru;
|
--
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
architecture Behavioral of vga_clk_div is
signal tmp_clkf : std_logic;
begin
my_div_fast: process (clk,tmp_clkf)
variable div_cnt : integer := 0;
begin
if (rising_edge(clk)) then
if (div_cnt = 0) then
tmp_clkf <= not tmp_clkf;
div_cnt := 0;
else
div_cnt := div_cnt + 1;
end if;
end if;
clkout <= tmp_clkf;
end process my_div_fast;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:58 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/ZyboIP/general_ip/affine_transform/affine_transform.srcs/sources_1/bd/affine_block/ip/affine_block_uint_to_ieee754_fp_0_1/affine_block_uint_to_ieee754_fp_0_1_sim_netlist.vhdl
-- Design : affine_block_uint_to_ieee754_fp_0_1
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp is
port (
\y[13]\ : out STD_LOGIC;
\y[23]\ : out STD_LOGIC;
y : out STD_LOGIC_VECTOR ( 9 downto 0 );
\y[22]\ : out STD_LOGIC;
\y[20]\ : out STD_LOGIC;
\y[18]\ : out STD_LOGIC;
\y[22]_0\ : out STD_LOGIC;
\y[22]_1\ : out STD_LOGIC;
\y[21]\ : out STD_LOGIC;
\y[20]_0\ : out STD_LOGIC;
\x_9__s_port_]\ : in STD_LOGIC;
\x[9]_0\ : in STD_LOGIC;
\x[9]_1\ : in STD_LOGIC;
\x[9]_2\ : in STD_LOGIC;
\x[9]_3\ : in STD_LOGIC;
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
\x[9]_4\ : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 2 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
p_1_out : in STD_LOGIC_VECTOR ( 0 to 0 );
\x[9]_5\ : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp : entity is "uint_to_ieee754_fp";
end affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp is
signal mantissa2_carry_i_1_n_0 : STD_LOGIC;
signal mantissa2_carry_i_2_n_0 : STD_LOGIC;
signal mantissa2_carry_i_3_n_0 : STD_LOGIC;
signal mantissa2_carry_i_4_n_0 : STD_LOGIC;
signal mantissa2_carry_n_2 : STD_LOGIC;
signal mantissa2_carry_n_3 : STD_LOGIC;
signal \x_9__s_net_1\ : STD_LOGIC;
signal \^y[13]\ : STD_LOGIC;
signal \y[13]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[13]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[14]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[15]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[16]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[17]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \^y[18]\ : STD_LOGIC;
signal \y[18]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[18]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[19]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \^y[20]\ : STD_LOGIC;
signal \^y[20]_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \^y[21]\ : STD_LOGIC;
signal \y[21]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_3_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \^y[22]\ : STD_LOGIC;
signal \^y[22]_0\ : STD_LOGIC;
signal \^y[22]_1\ : STD_LOGIC;
signal \^y[23]\ : STD_LOGIC;
signal \y[23]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[23]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[27]_INST_0_i_4_n_0\ : STD_LOGIC;
signal NLW_mantissa2_carry_CO_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 2 );
signal NLW_mantissa2_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[14]_INST_0_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[14]_INST_0_i_3\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[15]_INST_0_i_2\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \y[16]_INST_0_i_4\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[20]_INST_0_i_4\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_3\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_6\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_3\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_6\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \y[23]_INST_0_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \y[27]_INST_0_i_2\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \y[30]_INST_0_i_2\ : label is "soft_lutpair1";
begin
\x_9__s_net_1\ <= \x_9__s_port_]\;
\y[13]\ <= \^y[13]\;
\y[18]\ <= \^y[18]\;
\y[20]\ <= \^y[20]\;
\y[20]_0\ <= \^y[20]_0\;
\y[21]\ <= \^y[21]\;
\y[22]\ <= \^y[22]\;
\y[22]_0\ <= \^y[22]_0\;
\y[22]_1\ <= \^y[22]_1\;
\y[23]\ <= \^y[23]\;
mantissa2_carry: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3 downto 2) => NLW_mantissa2_carry_CO_UNCONNECTED(3 downto 2),
CO(1) => mantissa2_carry_n_2,
CO(0) => mantissa2_carry_n_3,
CYINIT => '1',
DI(3 downto 2) => B"00",
DI(1) => mantissa2_carry_i_1_n_0,
DI(0) => mantissa2_carry_i_2_n_0,
O(3 downto 0) => NLW_mantissa2_carry_O_UNCONNECTED(3 downto 0),
S(3 downto 2) => B"00",
S(1) => mantissa2_carry_i_3_n_0,
S(0) => mantissa2_carry_i_4_n_0
);
mantissa2_carry_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^y[22]\,
I1 => \^y[20]\,
O => mantissa2_carry_i_1_n_0
);
mantissa2_carry_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \^y[13]\,
I1 => \^y[23]\,
O => mantissa2_carry_i_2_n_0
);
mantissa2_carry_i_3: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^y[20]\,
I1 => \^y[22]\,
O => mantissa2_carry_i_3_n_0
);
mantissa2_carry_i_4: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^y[23]\,
I1 => \^y[13]\,
O => mantissa2_carry_i_4_n_0
);
\y[13]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"8888888C888888BF"
)
port map (
I0 => \y[14]_INST_0_i_3_n_0\,
I1 => \^y[23]\,
I2 => \y[13]_INST_0_i_1_n_0\,
I3 => \y[14]_INST_0_i_1_n_0\,
I4 => \x[9]_4\,
I5 => \y[14]_INST_0_i_2_n_0\,
O => y(0)
);
\y[13]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[13]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(6),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[13]_INST_0_i_1_n_0\
);
\y[13]_INST_0_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(4),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(8),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(0),
O => \y[13]_INST_0_i_2_n_0\
);
\y[14]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABFFAB00ABFFABFF"
)
port map (
I0 => \y[15]_INST_0_i_2_n_0\,
I1 => \y[14]_INST_0_i_1_n_0\,
I2 => \y[14]_INST_0_i_2_n_0\,
I3 => \^y[23]\,
I4 => \y[14]_INST_0_i_3_n_0\,
I5 => \y[15]_INST_0_i_1_n_0\,
O => y(1)
);
\y[14]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => mantissa2_carry_n_2,
I1 => CO(0),
O => \y[14]_INST_0_i_1_n_0\
);
\y[14]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBB8B88BBBB8BBB"
)
port map (
I0 => \y[14]_INST_0_i_4_n_0\,
I1 => \y[14]_INST_0_i_5_n_0\,
I2 => x(7),
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[14]_INST_0_i_2_n_0\
);
\y[14]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(0),
I3 => \^y[22]\,
O => \y[14]_INST_0_i_3_n_0\
);
\y[14]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"CF44CF77"
)
port map (
I0 => x(5),
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => x(1),
O => \y[14]_INST_0_i_4_n_0\
);
\y[14]_INST_0_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"AB"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => O(0),
I2 => mantissa2_carry_n_2,
O => \y[14]_INST_0_i_5_n_0\
);
\y[15]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[16]_INST_0_i_2_n_0\,
I3 => \y[15]_INST_0_i_1_n_0\,
I4 => \y[16]_INST_0_i_1_n_0\,
I5 => \y[15]_INST_0_i_2_n_0\,
O => y(2)
);
\y[15]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[15]_INST_0_i_3_n_0\,
I1 => \y[17]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[15]_INST_0_i_1_n_0\
);
\y[15]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0080"
)
port map (
I0 => \y[16]_INST_0_i_4_n_0\,
I1 => \^y[20]\,
I2 => x(1),
I3 => \^y[22]\,
O => \y[15]_INST_0_i_2_n_0\
);
\y[15]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(6),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(2),
O => \y[15]_INST_0_i_3_n_0\
);
\y[16]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[17]_INST_0_i_2_n_0\,
I3 => \y[16]_INST_0_i_1_n_0\,
I4 => \y[17]_INST_0_i_1_n_0\,
I5 => \y[16]_INST_0_i_2_n_0\,
O => y(3)
);
\y[16]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFAACAFFFF"
)
port map (
I0 => \y[16]_INST_0_i_3_n_0\,
I1 => \y[18]_INST_0_i_3_n_0\,
I2 => O(0),
I3 => \y[16]_INST_0_i_4_n_0\,
I4 => CO(0),
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_1_n_0\
);
\y[16]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(0),
I1 => \^y[22]\,
I2 => x(2),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_2_n_0\
);
\y[16]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(7),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(3),
O => \y[16]_INST_0_i_3_n_0\
);
\y[16]_INST_0_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"60"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => mantissa2_carry_n_2,
O => \y[16]_INST_0_i_4_n_0\
);
\y[17]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0AAA1BBB1BBB1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[18]_INST_0_i_2_n_0\,
I3 => \y[17]_INST_0_i_1_n_0\,
I4 => \y[18]_INST_0_i_1_n_0\,
I5 => \y[17]_INST_0_i_2_n_0\,
O => y(4)
);
\y[17]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFB0000FFFBFFFB"
)
port map (
I0 => \y[20]_INST_0_i_4_n_0\,
I1 => x(6),
I2 => \y[21]_INST_0_i_4_n_0\,
I3 => \y[20]_INST_0_i_3_n_0\,
I4 => \y[17]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[17]_INST_0_i_1_n_0\
);
\y[17]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"CFFFDDFFFFFFFFFF"
)
port map (
I0 => x(1),
I1 => \^y[22]\,
I2 => x(3),
I3 => \^y[20]\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[17]_INST_0_i_2_n_0\
);
\y[17]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(8),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(4),
O => \y[17]_INST_0_i_3_n_0\
);
\y[18]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B0BFBFBF"
)
port map (
I0 => \y[19]_INST_0_i_2_n_0\,
I1 => \y[18]_INST_0_i_1_n_0\,
I2 => \^y[23]\,
I3 => \y[18]_INST_0_i_2_n_0\,
I4 => \y[19]_INST_0_i_1_n_0\,
O => y(5)
);
\y[18]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFEF0000FFEFFFEF"
)
port map (
I0 => \y[20]_INST_0_i_3_n_0\,
I1 => \y[20]_INST_0_i_4_n_0\,
I2 => x(7),
I3 => \y[21]_INST_0_i_4_n_0\,
I4 => \y[18]_INST_0_i_3_n_0\,
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[18]_INST_0_i_1_n_0\
);
\y[18]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF00BFBFFFFFFFFF"
)
port map (
I0 => \^y[22]\,
I1 => x(2),
I2 => \^y[20]\,
I3 => \x[9]_2\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[18]_INST_0_i_2_n_0\
);
\y[18]_INST_0_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF4540FFFF757F"
)
port map (
I0 => x(9),
I1 => \^y[22]\,
I2 => mantissa2_carry_n_2,
I3 => O(1),
I4 => \y[21]_INST_0_i_4_n_0\,
I5 => x(5),
O => \y[18]_INST_0_i_3_n_0\
);
\y[19]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[20]_INST_0_i_2_n_0\,
I3 => \y[19]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_1_n_0\,
I5 => \y[19]_INST_0_i_2_n_0\,
O => y(6)
);
\y[19]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(6),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(8),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[19]_INST_0_i_1_n_0\
);
\y[19]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00FF404000000000"
)
port map (
I0 => \^y[22]\,
I1 => x(3),
I2 => \^y[20]\,
I3 => \x[9]_0\,
I4 => \^y[13]\,
I5 => mantissa2_carry_n_2,
O => \y[19]_INST_0_i_2_n_0\
);
\y[20]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"1BBB1BBB0AAA1BBB"
)
port map (
I0 => \^y[23]\,
I1 => \x[9]_4\,
I2 => \y[21]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_1_n_0\,
I4 => \y[20]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_1_n_0\,
O => y(7)
);
\y[20]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFF70FF77"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => x(7),
I2 => \y[20]_INST_0_i_3_n_0\,
I3 => \y[20]_INST_0_i_4_n_0\,
I4 => x(9),
I5 => \y[21]_INST_0_i_4_n_0\,
O => \y[20]_INST_0_i_1_n_0\
);
\y[20]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_2\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_3\,
O => \y[20]_INST_0_i_2_n_0\
);
\y[20]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[20]_INST_0_i_3_n_0\
);
\y[20]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"E1FFE100"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
O => \y[20]_INST_0_i_4_n_0\
);
\y[21]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EAFFEA00EAFFEAFF"
)
port map (
I0 => \y[21]_INST_0_i_1_n_0\,
I1 => \x_9__s_net_1\,
I2 => mantissa2_carry_n_2,
I3 => \^y[23]\,
I4 => \y[21]_INST_0_i_2_n_0\,
I5 => \y[21]_INST_0_i_3_n_0\,
O => y(8)
);
\y[21]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400044400000000"
)
port map (
I0 => \y[21]_INST_0_i_4_n_0\,
I1 => x(8),
I2 => \^y[22]\,
I3 => mantissa2_carry_n_2,
I4 => O(1),
I5 => \y[21]_INST_0_i_6_n_0\,
O => \y[21]_INST_0_i_1_n_0\
);
\y[21]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0020000000202020"
)
port map (
I0 => \y[21]_INST_0_i_6_n_0\,
I1 => \y[21]_INST_0_i_4_n_0\,
I2 => x(9),
I3 => \^y[22]\,
I4 => mantissa2_carry_n_2,
I5 => O(1),
O => \y[21]_INST_0_i_2_n_0\
);
\y[21]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"2FEF"
)
port map (
I0 => \x[9]_0\,
I1 => \^y[13]\,
I2 => mantissa2_carry_n_2,
I3 => \x[9]_1\,
O => \y[21]_INST_0_i_3_n_0\
);
\y[21]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"55A9FFFF55A90000"
)
port map (
I0 => p_1_out(0),
I1 => \^y[23]\,
I2 => \^y[18]\,
I3 => \^y[22]_0\,
I4 => mantissa2_carry_n_2,
I5 => O(2),
O => \y[21]_INST_0_i_4_n_0\
);
\y[21]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"00D0"
)
port map (
I0 => O(0),
I1 => \y[16]_INST_0_i_4_n_0\,
I2 => CO(0),
I3 => mantissa2_carry_n_2,
O => \y[21]_INST_0_i_6_n_0\
);
\y[22]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEE222E200000000"
)
port map (
I0 => \x_9__s_net_1\,
I1 => \^y[23]\,
I2 => \x[9]_1\,
I3 => \^y[13]\,
I4 => \x[9]_5\,
I5 => mantissa2_carry_n_2,
O => y(9)
);
\y[22]_INST_0_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
O => \^y[13]\
);
\y[22]_INST_0_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"E1"
)
port map (
I0 => \^y[23]\,
I1 => \^y[18]\,
I2 => \^y[22]_0\,
O => \^y[22]\
);
\y[22]_INST_0_i_7\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => \^y[18]\,
I1 => \^y[23]\,
I2 => \^y[20]_0\,
I3 => \^y[21]\,
I4 => x(8),
I5 => x(9),
O => \^y[20]\
);
\y[23]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00005504"
)
port map (
I0 => x(3),
I1 => x(0),
I2 => x(1),
I3 => x(2),
I4 => \y[23]_INST_0_i_1_n_0\,
I5 => \y[23]_INST_0_i_2_n_0\,
O => \^y[23]\
);
\y[23]_INST_0_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"FE"
)
port map (
I0 => x(5),
I1 => x(9),
I2 => x(7),
O => \y[23]_INST_0_i_1_n_0\
);
\y[23]_INST_0_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000F0FFF0F4"
)
port map (
I0 => x(5),
I1 => x(4),
I2 => x(8),
I3 => x(7),
I4 => x(6),
I5 => x(9),
O => \y[23]_INST_0_i_2_n_0\
);
\y[25]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"888888888888888A"
)
port map (
I0 => \^y[22]_1\,
I1 => \^y[21]\,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => \^y[22]_0\
);
\y[27]_INST_0_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFF01"
)
port map (
I0 => \y[27]_INST_0_i_4_n_0\,
I1 => x(7),
I2 => x(6),
I3 => x(9),
I4 => x(8),
O => \^y[18]\
);
\y[27]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(6),
I3 => x(7),
O => \^y[21]\
);
\y[27]_INST_0_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => x(1),
I1 => x(0),
I2 => x(2),
I3 => x(3),
O => \^y[20]_0\
);
\y[27]_INST_0_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"1110111011101111"
)
port map (
I0 => x(4),
I1 => x(5),
I2 => x(3),
I3 => x(2),
I4 => x(0),
I5 => x(1),
O => \y[27]_INST_0_i_4_n_0\
);
\y[30]_INST_0_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => x(8),
I1 => x(9),
O => \^y[22]_1\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity affine_block_uint_to_ieee754_fp_0_1 is
port (
x : in STD_LOGIC_VECTOR ( 9 downto 0 );
y : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of affine_block_uint_to_ieee754_fp_0_1 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of affine_block_uint_to_ieee754_fp_0_1 : entity is "affine_block_uint_to_ieee754_fp_0_1,uint_to_ieee754_fp,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of affine_block_uint_to_ieee754_fp_0_1 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of affine_block_uint_to_ieee754_fp_0_1 : entity is "uint_to_ieee754_fp,Vivado 2016.4";
end affine_block_uint_to_ieee754_fp_0_1;
architecture STRUCTURE of affine_block_uint_to_ieee754_fp_0_1 is
signal \<const0>\ : STD_LOGIC;
signal U0_n_0 : STD_LOGIC;
signal U0_n_12 : STD_LOGIC;
signal U0_n_13 : STD_LOGIC;
signal U0_n_14 : STD_LOGIC;
signal U0_n_15 : STD_LOGIC;
signal U0_n_16 : STD_LOGIC;
signal U0_n_17 : STD_LOGIC;
signal U0_n_18 : STD_LOGIC;
signal p_1_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal \^y\ : STD_LOGIC_VECTOR ( 30 downto 13 );
signal \y[20]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[20]_INST_0_i_6_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_10_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_11_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_2\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_3\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_5\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_6\ : STD_LOGIC;
signal \y[21]_INST_0_i_5_n_7\ : STD_LOGIC;
signal \y[21]_INST_0_i_7_n_0\ : STD_LOGIC;
signal \y[21]_INST_0_i_9_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_2_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_4_n_0\ : STD_LOGIC;
signal \y[22]_INST_0_i_5_n_0\ : STD_LOGIC;
signal \y[30]_INST_0_i_1_n_0\ : STD_LOGIC;
signal \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 to 2 );
signal \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \y[20]_INST_0_i_5\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \y[21]_INST_0_i_7\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_4\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \y[22]_INST_0_i_5\ : label is "soft_lutpair8";
begin
y(31) <= \<const0>\;
y(30) <= \^y\(30);
y(29) <= \^y\(27);
y(28) <= \^y\(27);
y(27 downto 13) <= \^y\(27 downto 13);
y(12) <= \<const0>\;
y(11) <= \<const0>\;
y(10) <= \<const0>\;
y(9) <= \<const0>\;
y(8) <= \<const0>\;
y(7) <= \<const0>\;
y(6) <= \<const0>\;
y(5) <= \<const0>\;
y(4) <= \<const0>\;
y(3) <= \<const0>\;
y(2) <= \<const0>\;
y(1) <= \<const0>\;
y(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
U0: entity work.affine_block_uint_to_ieee754_fp_0_1_uint_to_ieee754_fp
port map (
CO(0) => \y[21]_INST_0_i_5_n_0\,
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
p_1_out(0) => p_1_out(3),
x(9 downto 0) => x(9 downto 0),
\x[9]_0\ => \y[21]_INST_0_i_7_n_0\,
\x[9]_1\ => \y[22]_INST_0_i_2_n_0\,
\x[9]_2\ => \y[20]_INST_0_i_5_n_0\,
\x[9]_3\ => \y[20]_INST_0_i_6_n_0\,
\x[9]_4\ => \y[30]_INST_0_i_1_n_0\,
\x[9]_5\ => \y[22]_INST_0_i_4_n_0\,
\x_9__s_port_]\ => \y[22]_INST_0_i_1_n_0\,
y(9 downto 0) => \^y\(22 downto 13),
\y[13]\ => U0_n_0,
\y[18]\ => U0_n_14,
\y[20]\ => U0_n_13,
\y[20]_0\ => U0_n_18,
\y[21]\ => U0_n_17,
\y[22]\ => U0_n_12,
\y[22]_0\ => U0_n_15,
\y[22]_1\ => U0_n_16,
\y[23]\ => \^y\(23)
);
\y[20]_INST_0_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(0),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(4),
O => \y[20]_INST_0_i_5_n_0\
);
\y[20]_INST_0_i_6\: unisim.vcomponents.LUT4
generic map(
INIT => X"B080"
)
port map (
I0 => x(2),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(6),
O => \y[20]_INST_0_i_6_n_0\
);
\y[21]_INST_0_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => U0_n_12,
O => \y[21]_INST_0_i_10_n_0\
);
\y[21]_INST_0_i_11\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^y\(23),
I1 => U0_n_14,
O => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_5\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \y[21]_INST_0_i_5_n_0\,
CO(2) => \NLW_y[21]_INST_0_i_5_CO_UNCONNECTED\(2),
CO(1) => \y[21]_INST_0_i_5_n_2\,
CO(0) => \y[21]_INST_0_i_5_n_3\,
CYINIT => \^y\(23),
DI(3 downto 0) => B"0000",
O(3) => \NLW_y[21]_INST_0_i_5_O_UNCONNECTED\(3),
O(2) => \y[21]_INST_0_i_5_n_5\,
O(1) => \y[21]_INST_0_i_5_n_6\,
O(0) => \y[21]_INST_0_i_5_n_7\,
S(3) => '1',
S(2) => \y[21]_INST_0_i_9_n_0\,
S(1) => \y[21]_INST_0_i_10_n_0\,
S(0) => \y[21]_INST_0_i_11_n_0\
);
\y[21]_INST_0_i_7\: unisim.vcomponents.LUT4
generic map(
INIT => X"4F7F"
)
port map (
I0 => x(1),
I1 => U0_n_12,
I2 => U0_n_13,
I3 => x(5),
O => \y[21]_INST_0_i_7_n_0\
);
\y[21]_INST_0_i_8\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAAAAAAAAAA8"
)
port map (
I0 => U0_n_16,
I1 => U0_n_17,
I2 => x(1),
I3 => x(0),
I4 => x(2),
I5 => x(3),
O => p_1_out(3)
);
\y[21]_INST_0_i_9\: unisim.vcomponents.LUT6
generic map(
INIT => X"EEEEEEEEEEEEFF10"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_18,
I3 => U0_n_17,
I4 => x(8),
I5 => x(9),
O => \y[21]_INST_0_i_9_n_0\
);
\y[22]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"B8BB8888B8888888"
)
port map (
I0 => \y[22]_INST_0_i_5_n_0\,
I1 => U0_n_0,
I2 => x(2),
I3 => U0_n_12,
I4 => U0_n_13,
I5 => x(6),
O => \y[22]_INST_0_i_1_n_0\
);
\y[22]_INST_0_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"C888"
)
port map (
I0 => x(7),
I1 => U0_n_13,
I2 => x(3),
I3 => U0_n_12,
O => \y[22]_INST_0_i_2_n_0\
);
\y[22]_INST_0_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(5),
I1 => U0_n_12,
I2 => x(9),
I3 => U0_n_13,
I4 => x(1),
O => \y[22]_INST_0_i_4_n_0\
);
\y[22]_INST_0_i_5\: unisim.vcomponents.LUT5
generic map(
INIT => X"B833B800"
)
port map (
I0 => x(4),
I1 => U0_n_12,
I2 => x(8),
I3 => U0_n_13,
I4 => x(0),
O => \y[22]_INST_0_i_5_n_0\
);
\y[24]_INST_0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(23),
I2 => U0_n_14,
O => \^y\(24)
);
\y[25]_INST_0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0078"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => U0_n_15,
I3 => \y[30]_INST_0_i_1_n_0\,
O => \^y\(25)
);
\y[26]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => x(9),
I1 => \^y\(27),
O => \^y\(26)
);
\y[27]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000800000000"
)
port map (
I0 => U0_n_14,
I1 => \^y\(23),
I2 => x(9),
I3 => x(8),
I4 => U0_n_17,
I5 => U0_n_18,
O => \^y\(27)
);
\y[30]_INST_0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \y[30]_INST_0_i_1_n_0\,
I1 => \^y\(27),
O => \^y\(30)
);
\y[30]_INST_0_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000100000000"
)
port map (
I0 => U0_n_17,
I1 => x(1),
I2 => x(0),
I3 => x(2),
I4 => x(3),
I5 => U0_n_16,
O => \y[30]_INST_0_i_1_n_0\
);
end STRUCTURE;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized4_0 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized4_0;
ARCHITECTURE design_1_FIR_resized4_0_arch OF design_1_FIR_resized4_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized4_0_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_FIR_resized4_0_arch: ARCHITECTURE IS "fir_compiler_v7_2_6,Vivado 2016.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_FIR_resized4_0_arch : ARCHITECTURE IS "design_1_FIR_resized4_0,fir_compiler_v7_2_6,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_FIR_resized4_0_arch: ARCHITECTURE IS "design_1_FIR_resized4_0,fir_compiler_v7_2_6,{x_ipProduct=Vivado 2016.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fir_compiler,x_ipVersion=7.2,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_COMPONENT_NAME=design_1_FIR_resized4_0,C_COEF_FILE=design_1_FIR_resized4_0.mif,C_COEF_FILE_LINES=105,C_FILTER_TYPE=1,C_INTERP_RATE=1,C_DECIM_RATE=5,C_ZERO_PACKING_FACTOR=1,C_SYMMETRY=1,C_NUM_FILTS=1,C_NUM_TAPS=204,C_NUM_CHANNELS=1,C_CHANNEL_PATTERN" &
"=fixed,C_ROUND_MODE=1,C_COEF_RELOAD=0,C_NUM_RELOAD_SLOTS=1,C_COL_MODE=1,C_COL_PIPE_LEN=4,C_COL_CONFIG=21,C_OPTIMIZATION=0,C_DATA_PATH_WIDTHS=24,C_DATA_IP_PATH_WIDTHS=24,C_DATA_PX_PATH_WIDTHS=24,C_DATA_WIDTH=24,C_COEF_PATH_WIDTHS=16,C_COEF_WIDTH=16,C_DATA_PATH_SRC=0,C_COEF_PATH_SRC=0,C_PX_PATH_SRC=0,C_DATA_PATH_SIGN=0,C_COEF_PATH_SIGN=0,C_ACCUM_PATH_WIDTHS=43,C_OUTPUT_WIDTH=32,C_OUTPUT_PATH_WIDTHS=32,C_ACCUM_OP_PATH_WIDTHS=43,C_EXT_MULT_CNFG=none,C_DATA_PATH_PSAMP_SRC=0,C_OP_PATH_PSAMP_SRC=0,C_NU" &
"M_MADDS=21,C_OPT_MADDS=none,C_OVERSAMPLING_RATE=1,C_INPUT_RATE=1,C_OUTPUT_RATE=5,C_DATA_MEMTYPE=0,C_COEF_MEMTYPE=2,C_IPBUFF_MEMTYPE=2,C_OPBUFF_MEMTYPE=0,C_DATAPATH_MEMTYPE=2,C_MEM_ARRANGEMENT=1,C_DATA_MEM_PACKING=0,C_COEF_MEM_PACKING=0,C_FILTS_PACKED=0,C_LATENCY=28,C_HAS_ARESETn=0,C_HAS_ACLKEN=0,C_DATA_HAS_TLAST=0,C_S_DATA_HAS_FIFO=1,C_S_DATA_HAS_TUSER=0,C_S_DATA_TDATA_WIDTH=24,C_S_DATA_TUSER_WIDTH=1,C_M_DATA_HAS_TREADY=0,C_M_DATA_HAS_TUSER=0,C_M_DATA_TDATA_WIDTH=32,C_M_DATA_TUSER_WIDTH=1,C_HAS_" &
"CONFIG_CHANNEL=0,C_CONFIG_SYNC_MODE=0,C_CONFIG_PACKET_SIZE=0,C_CONFIG_TDATA_WIDTH=1,C_RELOAD_TDATA_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized4_0",
C_COEF_FILE => "design_1_FIR_resized4_0.mif",
C_COEF_FILE_LINES => 105,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 204,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "21",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "43",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "43",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 21,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 28,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized4_0_arch;
|
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.numeric_std.all;
Entity ULA is
port (
in0, in1: in std_logic_vector(31 downto 0);
oper: in std_logic_vector(3 downto 0);
zero: out std_logic;
output : out std_logic_vector(31 downto 0)
);
end ULA;
architecture rtl of ULA is
signal sig_output: std_logic_vector(31 downto 0);
begin
process(oper, in0, in1)
begin
case oper is
when "0000" =>
sig_output <= in0 and in1;
when "0001" =>
sig_output <= in0 or in1;
when "0010" =>
sig_output <= in0 + in1;
--when "0011" =>
--sig_output <= in0 * in1;
--when "0100" =>
--sig_output <= in0 / in1;
when "0101" =>
sig_output <= in0 nor in1;
when "0110" =>
sig_output <= in0 - in1;
when "0111" => -- verificar
sig_output <= (0 => '1', others => '0');
when "1000" =>
sig_output <= in0 xor in1;
when "1001" =>
sig_output <= std_logic_vector(signed(in0) sll to_integer(signed(in1)));
when "1010" =>
sig_output <= std_logic_vector(signed(in0) srl to_integer(signed(in1)));
when "1011" =>
sig_output <= std_logic_vector(shift_right(signed(in0),to_integer(signed(in1))));
when "1100" =>
if (in0 < in1) then
sig_output <= "00000000000000000000000000000001";
else
sig_output <= "00000000000000000000000000000000";
end if;
when "1101" =>
if (unsigned(in0) < unsigned(in1)) then
sig_output <= "00000000000000000000000000000001";
else
sig_output <= "00000000000000000000000000000000";
end if;
WHEN OTHERS =>
sig_output <= in0;
end case;
end process;
zero <= '1' when sig_output = "00000000000000000000000000000000"
else '0';
output <= sig_output;
end rtl; |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_3 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_3;
ARCHITECTURE design_1_FIR_resized1_3_arch OF design_1_FIR_resized1_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_3",
C_COEF_FILE => "design_1_FIR_resized1_3.mif",
C_COEF_FILE_LINES => 35,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 62,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "7",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "42",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "42",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 7,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 14,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_3_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_3 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_3;
ARCHITECTURE design_1_FIR_resized1_3_arch OF design_1_FIR_resized1_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_3",
C_COEF_FILE => "design_1_FIR_resized1_3.mif",
C_COEF_FILE_LINES => 35,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 62,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "7",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "42",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "42",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 7,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 14,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_3_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_3 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_3;
ARCHITECTURE design_1_FIR_resized1_3_arch OF design_1_FIR_resized1_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_3",
C_COEF_FILE => "design_1_FIR_resized1_3.mif",
C_COEF_FILE_LINES => 35,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 62,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "7",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "42",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "42",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 7,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 14,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_3_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:fir_compiler:7.2
-- IP Revision: 6
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY fir_compiler_v7_2_6;
USE fir_compiler_v7_2_6.fir_compiler_v7_2_6;
ENTITY design_1_FIR_resized1_3 IS
PORT (
aclk : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_FIR_resized1_3;
ARCHITECTURE design_1_FIR_resized1_3_arch OF design_1_FIR_resized1_3 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_FIR_resized1_3_arch: ARCHITECTURE IS "yes";
COMPONENT fir_compiler_v7_2_6 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_COMPONENT_NAME : STRING;
C_COEF_FILE : STRING;
C_COEF_FILE_LINES : INTEGER;
C_FILTER_TYPE : INTEGER;
C_INTERP_RATE : INTEGER;
C_DECIM_RATE : INTEGER;
C_ZERO_PACKING_FACTOR : INTEGER;
C_SYMMETRY : INTEGER;
C_NUM_FILTS : INTEGER;
C_NUM_TAPS : INTEGER;
C_NUM_CHANNELS : INTEGER;
C_CHANNEL_PATTERN : STRING;
C_ROUND_MODE : INTEGER;
C_COEF_RELOAD : INTEGER;
C_NUM_RELOAD_SLOTS : INTEGER;
C_COL_MODE : INTEGER;
C_COL_PIPE_LEN : INTEGER;
C_COL_CONFIG : STRING;
C_OPTIMIZATION : INTEGER;
C_DATA_PATH_WIDTHS : STRING;
C_DATA_IP_PATH_WIDTHS : STRING;
C_DATA_PX_PATH_WIDTHS : STRING;
C_DATA_WIDTH : INTEGER;
C_COEF_PATH_WIDTHS : STRING;
C_COEF_WIDTH : INTEGER;
C_DATA_PATH_SRC : STRING;
C_COEF_PATH_SRC : STRING;
C_PX_PATH_SRC : STRING;
C_DATA_PATH_SIGN : STRING;
C_COEF_PATH_SIGN : STRING;
C_ACCUM_PATH_WIDTHS : STRING;
C_OUTPUT_WIDTH : INTEGER;
C_OUTPUT_PATH_WIDTHS : STRING;
C_ACCUM_OP_PATH_WIDTHS : STRING;
C_EXT_MULT_CNFG : STRING;
C_DATA_PATH_PSAMP_SRC : STRING;
C_OP_PATH_PSAMP_SRC : STRING;
C_NUM_MADDS : INTEGER;
C_OPT_MADDS : STRING;
C_OVERSAMPLING_RATE : INTEGER;
C_INPUT_RATE : INTEGER;
C_OUTPUT_RATE : INTEGER;
C_DATA_MEMTYPE : INTEGER;
C_COEF_MEMTYPE : INTEGER;
C_IPBUFF_MEMTYPE : INTEGER;
C_OPBUFF_MEMTYPE : INTEGER;
C_DATAPATH_MEMTYPE : INTEGER;
C_MEM_ARRANGEMENT : INTEGER;
C_DATA_MEM_PACKING : INTEGER;
C_COEF_MEM_PACKING : INTEGER;
C_FILTS_PACKED : INTEGER;
C_LATENCY : INTEGER;
C_HAS_ARESETn : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_DATA_HAS_TLAST : INTEGER;
C_S_DATA_HAS_FIFO : INTEGER;
C_S_DATA_HAS_TUSER : INTEGER;
C_S_DATA_TDATA_WIDTH : INTEGER;
C_S_DATA_TUSER_WIDTH : INTEGER;
C_M_DATA_HAS_TREADY : INTEGER;
C_M_DATA_HAS_TUSER : INTEGER;
C_M_DATA_TDATA_WIDTH : INTEGER;
C_M_DATA_TUSER_WIDTH : INTEGER;
C_HAS_CONFIG_CHANNEL : INTEGER;
C_CONFIG_SYNC_MODE : INTEGER;
C_CONFIG_PACKET_SIZE : INTEGER;
C_CONFIG_TDATA_WIDTH : INTEGER;
C_RELOAD_TDATA_WIDTH : INTEGER
);
PORT (
aresetn : IN STD_LOGIC;
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_data_tvalid : IN STD_LOGIC;
s_axis_data_tready : OUT STD_LOGIC;
s_axis_data_tlast : IN STD_LOGIC;
s_axis_data_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_data_tdata : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axis_config_tvalid : IN STD_LOGIC;
s_axis_config_tready : OUT STD_LOGIC;
s_axis_config_tlast : IN STD_LOGIC;
s_axis_config_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_reload_tvalid : IN STD_LOGIC;
s_axis_reload_tready : OUT STD_LOGIC;
s_axis_reload_tlast : IN STD_LOGIC;
s_axis_reload_tdata : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tvalid : OUT STD_LOGIC;
m_axis_data_tready : IN STD_LOGIC;
m_axis_data_tlast : OUT STD_LOGIC;
m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_data_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
event_s_data_tlast_missing : OUT STD_LOGIC;
event_s_data_tlast_unexpected : OUT STD_LOGIC;
event_s_data_chanid_incorrect : OUT STD_LOGIC;
event_s_config_tlast_missing : OUT STD_LOGIC;
event_s_config_tlast_unexpected : OUT STD_LOGIC;
event_s_reload_tlast_missing : OUT STD_LOGIC;
event_s_reload_tlast_unexpected : OUT STD_LOGIC
);
END COMPONENT fir_compiler_v7_2_6;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
BEGIN
U0 : fir_compiler_v7_2_6
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_COMPONENT_NAME => "design_1_FIR_resized1_3",
C_COEF_FILE => "design_1_FIR_resized1_3.mif",
C_COEF_FILE_LINES => 35,
C_FILTER_TYPE => 1,
C_INTERP_RATE => 1,
C_DECIM_RATE => 5,
C_ZERO_PACKING_FACTOR => 1,
C_SYMMETRY => 1,
C_NUM_FILTS => 1,
C_NUM_TAPS => 62,
C_NUM_CHANNELS => 1,
C_CHANNEL_PATTERN => "fixed",
C_ROUND_MODE => 1,
C_COEF_RELOAD => 0,
C_NUM_RELOAD_SLOTS => 1,
C_COL_MODE => 1,
C_COL_PIPE_LEN => 4,
C_COL_CONFIG => "7",
C_OPTIMIZATION => 0,
C_DATA_PATH_WIDTHS => "24",
C_DATA_IP_PATH_WIDTHS => "24",
C_DATA_PX_PATH_WIDTHS => "24",
C_DATA_WIDTH => 24,
C_COEF_PATH_WIDTHS => "16",
C_COEF_WIDTH => 16,
C_DATA_PATH_SRC => "0",
C_COEF_PATH_SRC => "0",
C_PX_PATH_SRC => "0",
C_DATA_PATH_SIGN => "0",
C_COEF_PATH_SIGN => "0",
C_ACCUM_PATH_WIDTHS => "42",
C_OUTPUT_WIDTH => 32,
C_OUTPUT_PATH_WIDTHS => "32",
C_ACCUM_OP_PATH_WIDTHS => "42",
C_EXT_MULT_CNFG => "none",
C_DATA_PATH_PSAMP_SRC => "0",
C_OP_PATH_PSAMP_SRC => "0",
C_NUM_MADDS => 7,
C_OPT_MADDS => "none",
C_OVERSAMPLING_RATE => 1,
C_INPUT_RATE => 1,
C_OUTPUT_RATE => 5,
C_DATA_MEMTYPE => 0,
C_COEF_MEMTYPE => 2,
C_IPBUFF_MEMTYPE => 2,
C_OPBUFF_MEMTYPE => 0,
C_DATAPATH_MEMTYPE => 2,
C_MEM_ARRANGEMENT => 1,
C_DATA_MEM_PACKING => 0,
C_COEF_MEM_PACKING => 0,
C_FILTS_PACKED => 0,
C_LATENCY => 14,
C_HAS_ARESETn => 0,
C_HAS_ACLKEN => 0,
C_DATA_HAS_TLAST => 0,
C_S_DATA_HAS_FIFO => 1,
C_S_DATA_HAS_TUSER => 0,
C_S_DATA_TDATA_WIDTH => 24,
C_S_DATA_TUSER_WIDTH => 1,
C_M_DATA_HAS_TREADY => 0,
C_M_DATA_HAS_TUSER => 0,
C_M_DATA_TDATA_WIDTH => 32,
C_M_DATA_TUSER_WIDTH => 1,
C_HAS_CONFIG_CHANNEL => 0,
C_CONFIG_SYNC_MODE => 0,
C_CONFIG_PACKET_SIZE => 0,
C_CONFIG_TDATA_WIDTH => 1,
C_RELOAD_TDATA_WIDTH => 1
)
PORT MAP (
aresetn => '1',
aclk => aclk,
aclken => '1',
s_axis_data_tvalid => s_axis_data_tvalid,
s_axis_data_tready => s_axis_data_tready,
s_axis_data_tlast => '0',
s_axis_data_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_data_tdata => s_axis_data_tdata,
s_axis_config_tvalid => '0',
s_axis_config_tlast => '0',
s_axis_config_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_reload_tvalid => '0',
s_axis_reload_tlast => '0',
s_axis_reload_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
m_axis_data_tvalid => m_axis_data_tvalid,
m_axis_data_tready => '1',
m_axis_data_tdata => m_axis_data_tdata
);
END design_1_FIR_resized1_3_arch;
|
----------------------------------------------------------------------------------
--
-- Lab session #1: vga controller
--
-- Author: David Estévez Fernández
-- David Estévez Fernández
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity vga is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
RGB : in STD_LOGIC_VECTOR (2 downto 0);
HSync : out STD_LOGIC;
VSync : out STD_LOGIC;
R : out STD_LOGIC;
G : out STD_LOGIC;
B : out STD_LOGIC;
X : out STD_LOGIC_VECTOR (9 downto 0);
Y : out STD_LOGIC_VECTOR (9 downto 0));
end vga;
architecture Behavioral of vga is
begin
process(reset, clk)
-- XCount -> holds the count for the X dimension ( monitor resolution is 640x480 )
variable HCount: integer range 0 to 800:= 0;
variable VCount: integer range 0 to 521 := 0;
variable prescaler: std_logic := '0';
begin
-- When resetting, set all outputs to 0
if reset = '1' then
HSync <= '1';
VSync <= '1';
R <= '0';
G <= '0';
B <= '0';
X <= "0000000000";
Y <= "0000000000";
elsif clk'event and clk = '1' then
-- Prescaler
if prescaler = '1' then
prescaler := '0';
else
prescaler := '1';
end if;
-- Counters:
if prescaler = '0' then
if HCount = 800 then
HCount := 0;
if VCount = 521 then
VCount := 0;
else
VCount := VCount + 1;
end if;
else
HCount := HCount + 1;
end if;
end if;
-- HSync:
if HCount >= 654 and HCount < 752 then
HSync <= '0';
else
HSync <= '1';
end if;
-- VSync:
if VCount >= 490 and VCount < 492 then
VSync <= '0';
else
VSync <= '1';
end if;
-- X / Y position:
if HCount < 640 then
X <= std_logic_vector( to_unsigned( HCount, 10) );
end if;
if VCount < 480 then
Y <= std_logic_vector( to_unsigned( VCount, 10) );
end if;
-- Color:
if VCount < 480 and HCount < 640 then
R <= RGB(2);
G <= RGB(1);
B <= RGB(0);
else
R <= '0';
G <= '0';
B <= '0';
end if;
end if;
end process;
end Behavioral;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eERg1Iy1WKSyjyVvoRwacqCMp6BGKmDEq9r28RNgx3LfpZEXyRjRjfoMT8jsQEUXCvWsQwc21AwH
0wziVaSXeQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ATVzf6PK/3N4J3XI+hCP4pb0u280D51igWJGNsvKHd38o0xuKqBiQQreMmMGnnhWZU0LTrnoJ4mJ
o+he4xAmtRk3S29Wmb8VCmNGbjF71CKo9TMzF+EuMgwjYwea628q/aiJVn7EVEpEdVlRAUuHQ1Nc
1MDu0ciOFoo1Rybp1gM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NW27jfO0i5E2NNydzeSOPFdtWdWfN2YrLekSOukVCUWdx8QlZpAlOxEp2nscm0+tAASDHpTH4aAQ
lyrGIYWao9kuaWtsRJOWrhuXg1M6tcn35HarblKiJdVU1DyYfcY9h+Gfzvpjc/pF3kqAAIvzhxKn
QSanLNBq9gUuDS3llM5NEclvuyRVDIqBX/swc58gjOp88AG2NBGwxxuEuzWiSVwyZZT42Xxj4jnA
Or9xkCEU/eAI3eNLBfT8OK6YrVLC6TGs76d3dtToE9LmIAS45QgqMjh/ctR0jQgNOZbo87YPX0/c
oBL9YJRuWLlCBgDcHAEk3HxFl8FWvXJP0pX8WQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4flJUe5VqP9x8iD/a62oF9gaDnyRxRoifIQ5baBGmnFj+4BGNd4klnKOEDOBB1aPoqM3Uoa3Nt7z
jjADEbQznD48oWi6KIdtSIS9G+hCheFwtIx5yBiLvUdDrM6U/ORiHwEYybqkHuROVnziw9+1l+MC
AityTqqOx3hGuynUD0Q=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LYhQ7tfXgIfRrGBioeyvxTZvEIjEKfmFuFA3JIpmJ2Dq/5XACdHxi9+bg8AiYGZO0bQb3d3oCo+z
5Rh2V7SzJKSAwkHy+VXLuX7Yw6SptZBr0fdSbowIUVyYvtEwU2U4qbBJEmdp9nSAHPQ7Fv6hR3pD
8DdQrt4tF5ZKZE3uR30x5zE5kJgArrgTtbvmcrlfURq7kL9xNVfRTpwptT5CZqPdG9stN2VV8D8q
GVf7lhgvKYgoeY/o1JDOPMzVmMBeCjtVXXBjAALCDyPLAHjnS0GtDUoH69ibBPJQw0m8dxU66eq3
Il1VPNzwf/ftaZpANLaMvllRLVlaYIMH2l99CA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184)
`protect data_block
YPeuHY8srKBBQOsWKmwNtSgvLAP9taPcKVblqrCClJzflZwaji2E5Mmk0/9xx6WFxiwlhymxo00e
Ll+FPWOrjYR0WOi9qy0Ny0icaklLKCQxIUhk1rHHIUmBJ+0VZRQJIV+0+wL5RFw464uf4AO4ZhrW
TluAfdUKrfkxge6QdX0sC7LWx/h2p5HT/FQABQXly03Hh1uLqJNogz9Q7YMt6epa6mEeZeVe0vL7
VJ449ZHorA2R/DR4zOLS3SgckYMYoEBtS5DjYsqa9FYKMtVf7cuJ6uSl2iIro2yuqIeekHZCtoOo
3IjYqYdHugTkWMrbXEAlwiPjr3ShOLZRsxY30T4mCuCNmwnzK6YSLc0lH016FzuQMCbUmVKdAM0O
8IJ4AVvhwLhlXZsgckV8Eq3FQoP0BQ07BLJuFSVQF+XUIwamDeRAQV2bj6hfnyJyq7YG4st4PqIG
UNL9GYce8GRkoKMHzLOXkJFimtE4F3daW09yIY+j1Fovst/hN6+nahTfBRMa03jYePeCB3zVhYSo
NIdRa58jiNSQW/Yj1ZADOtg5LKDOwyNPTVSQq8+UBq4x2eImoqN0KibvzpayviI1O8ZfYMlChxc8
oCmBCf4l73YFDrB3ggbj4miXA34qZhV9tlpwqlPg9veeL0okKhneE5zJPbx9hrycnAMGFQWYX2nw
2Zi292xVzi3FnHUj3C7FZ214SggINQcBbcCM4n59azO5xgMUboaDew7wvh7obDUQwf5rZZBq3Sfg
oxt7cSXumet9Rd+YJjgoBPGMyDU1qfkyktRDka2IILzufTbK5UVxFiNjncTmeD6/xBfL4xga0jqr
Han7EbIxTzqKybqV5jqawFTmHy7ymtvyQLHVFv5hVxHUN/+puMvUxEUGXDGtThZDHF5AZ8yWEu2S
KaT6XLwg+yZaVVNifrAsDcwTfepe3824es5VxRGKPGDqewnvZxetEfrpxKyGiEa25ZBKDt3CNaF/
J14SKAkH11FaN41cJX0D/7sGGN1Kr8sOv9SNYb42dQwiL0FXLEuJys8pqW1gZzDP7j1KeQtG99pW
lldhry1mjvEBmEDK2OBwXsvQfPF3ARRo6/Owkkf0+nDqnkKWQnX5rnGVsxPKiFnFfzV+7VlF7pI1
+e2PlFgHpd1xtqYTakAyduGlWpkRI0JASwUT0hclFFDsueDId9ChC/AdKoVUcQ6VtxyDAf0qCBXY
qceQHp2aWOoJWXvsg6KwSxDmi5gi8rdVEuGXQAf465pWFwbzvQVAEvnu0KMAhTcADO//xCKgc+N/
OPyGQrbTzPdumF+5DilrHNf4OjZ5VZlYIP7xCbXUMZZuJmZLqRRAYyt+BH+FmxKc5ImKu9fZiAQ2
f/sKAkV1ifIZcOZNp5LufC+f3TcjubQxZedulHeHQxogWLvrq1f+JJuLRfAYM9Ybcc9YG5XxlXcI
xBws53htYyND78s9XyJZhhbLB9Vh6/+XNzozjxM3aJoOacd6p0uJlhKmPUgqeH/c+9afltbS/9Hb
zQwFab5u2E0h0pyzlKRTcxSKhw1UI/FyagqA62QGGWMz9GQFyR2OkdEyffWUjOPcmLMZSbRcdGCe
X29rx6oapyElTcO2kbuUlTdNcARhlEwwjm0od7YYvUQhHsHeWVFfXG93Ck9ahfA+oxBqZA7v1wud
E/2Is+C8K7m7zdpU5WgTTp8r68Hh0y6Oo5t/HlU+cMviY1aXBvUtv5bSutQh4126CPkJBmvisBz4
pNHFw7fXh83td3ArMaYav4f5rAM5eLuWZtj+Xv9I4txG0STm6wOYKVGeM9JwK8ffplLUNSgwbI1W
IUnWynhDWCcW7qEAoGcYpeo3wnRLQ6YnoE3LGWjUK3B1+YivoyjxAHCrJw0LUV0oR3HKxkD40BOK
QX10e+1cj1kZWewgmkp2X/tPT6wNWg5WmY6RqMrYb68a8SNmrZFCUn5BL37Td4YLk20inaH2gz5u
lRnTtFuuSwy2S4EafErqlNeZ+I2j6/4GAXuwDBKmHjh43d9ptybU60qTOAR66sNiKrv5doFwX6Q7
l/fjF+oqqIPyrhM9RGPAIYwbtZdzvB+ivLqEhzIqYNtCoO/LT9V5yaisL/2YDOaJ0iuB/aJl2Xe6
cFDSnM7rxWAsIwD5fqL7GVj8DqwSaEZbStZIgFd7BdPvzb8567ndKM43Ir7DFWEnrjz8TB6FodTV
vSfYq6p6AMmKjHxj9b4E2Ki/TjE9XXydJBHT22e2yv7FFW7tTakcErTWa8ddMIwjECDFSxaNyVB3
H2QZ4DWN1XJNMggvlZTbwbKEMFWeGwA4Bzpqn2NGMWLkFXALmUWOk76w0/kinoLnr/ht3XB3BXGq
Idy3DC1ibBoaqju+J7MJdCISE8h4G/YMtFYxAfg5+5D9gzX8g/LmA7GTciJ40HvAFg5EzLNc16p1
vsMjpfkHS4t2g4//whPI272I8IfuHMnge/nS2yZzn2Dxor2obOgA27lF4FMYxyEWaV8jN9HcYpbW
LDoMS4f+wnUdD1rJP6mQDqwXk2EFItoYYmuVIMQ/Iw07ec++1SyIe6f0TPKZ0FqWToN1VbBO0Ugl
F40TlJ/S24uCXLVAGJ/sG/Z6hPlcaeLEOZOcQFsyYgBzgZMR+4/XHr7TCnlS9ovpBgiA5aH+zweU
kL0eyQWYQtycW+5UgEaPArX7VoSJRIUab8DDj1lA5gW0oco/hxDG/hvMGHuOzB7iyifl3IvvdZS+
g6hkKrvavOO0k82AwMMgAR2pq4GZDnivcxCYZpe+KV1CBz4SGnxyLjoCTdRFSvW/3qpEAY5SdvLS
Wc5gTeqR3Z5l0CxE4ttbjnJYbsuKh+0m/eWYe4jfrvMmgJzEFvNqj0wUWOGJBsCbJuocofosxcuR
y7xoV5siRnZ57As2SFwDdeGY2LYDAj1sZjRhlnPlwdpJl02dsaBZz07xucsFUAdbS9qclEOYDL/r
bjUo1wJt8PinAM3hLx3OG7Gr4xPnmNqrma0UuECCRxWPaQxP8w1clATDuNnKObWk3Ul0/olA9B3z
LTUeXnq0zliMuN4UIQFgMwRytVZuZqnOObff60ajkfcafJHrz7Viyvv2RVT1s04wNKlBqghYtinV
OoTRtubG/bdqHhVZeecTcxyKh9j9Zkf8TyIcW5zFHcbC40L+7mve/96mtl0TnXoSBIDn91UMIPrG
3vrcx6d1ZmtV6bPNo06j3EsQoATX9h4cUTJj/DceHdgRLxF6vnktURKW72a3+E8IswT0XR5p7kkO
OX7ABiGx7GBGD98fDqhNoAmPbgDTavhmJ2RlZYJKyn1pXNJ0QRiwXLtXYxhhmL/kbhKZyMwV5Hfm
VEW0r3niyim/Qndxu/hmsYfWcC8LScgcLMzTET4Ft26aJcmtNRvYKpF4Ru1Pt7IvUDqhavEqJlaJ
lGG79+/p/Y3dWkwsQeT/Rxma1AKIgllq0lfQAooGtcs+Mp6DBpKklHL0VVSUVvVQdTFLh4GKkTLA
/MJAmIspe/VbzFClaIVoJKmWW6wNlqYRejfO1W5F5uby8qHXkC7XUOEJHPlLqxzZCR1p3uZVTwb1
VRj654/bsIgDNy2t+IpnyPov5be+a+LPmEWZWCf2BFrju7Of/WCSdMP5Xi4mARvSYIJr68rf5DJH
8BkEwYfGt/ls78QVb2WbZxw7KhcdzIgP7yv5IuK2f0fPOseM476DXQhTqwZlsXCAWcjeH/tIOsBe
Ok8lHEuWaR3GPYESx14UjGVqj2iDqF3+ky1c74T3D8uTzh2cvc15T71ylmUwH5zIyznDCq/yoN/k
G6RKkb8hL4lQE1XCNVGy81Yy0ABO/T7ca8qlcXHP/KYkiZB0S5m0egmIFHIAGA8MtBgyFYPMZBnt
MB24afif/wgsoJcRtN0RZVkrHIblySM2Lv5hQChlmBENtNd5t7wP8UP5P2AbzzQYMQ/089jq1YpT
Tp2PhGiphEF/COup2M4cEZoNEgLiQHoHRaHipB2/AbDrSRVIhKIYY23/P/V3fmw/OBSM2j3t2A3Z
GLrsPQmOQoBjhtksLIDpX1rYAcaHnXpFCTyJrl7aAIzh4AAfkDrVSO59I0qBf6ZAkTDJ0e+fUGtM
8WzLjIJhAtf4isvHjsEiED9w/T5Oe6Cf8PHnpybNQ7ZhdLS4CjSWAbj3MIhl1PUKcc4rqQPYgCVX
PQcJvXPzzwOAtBWwlzc4cyfX1ElJbT8qwpj+gXj+d04jI11iEgKixDmCpcFTZH/319QlwGvo4Mis
MsGvMbVIRrOoZaL2cf9Haqse1dvVU1bQ+wvA//2XX+1BasWpEjcoYPRHjCff4kYAa+NL/FKVDdsK
06JzYB/pPN4hQ9/5HB9Zt1BaI08h5MQUTsgdtUAY5BsXjUYuDtFMAozirjkbl8IBHKbof6T8MYO9
BFO7Mb5fAfGVIgBOGaR70Mb1uRgCd5WJZpezJ/EF0TLVSmcKsT2eS2PLNo9bnbQDTslsjcLEJtFC
YFre+ypguShDbB/oFudreACnZKwFjAtkxsLYNS8QS0n8o1Pz8ugcjpK+fA4MhFJQ2KuFMEBEhhJy
7wE9ectEXQy4bg3s1jMt64tk7QAgGC5hymuZ8z+R0RbZfeGVzuW5XjuRqoz0GLQqCnQy84vUdhFW
ru9itICU2H9tnl/jIdSrMESCye2moi+Bk0XC1NKG+RMILydcQO4wFUAY/MAyyK3H1SURHr+afMD0
ZNdEcwkwLma9GXZUu/go0NBZkAvf5ftrbC60YnhZUvagviXK+niQu5IazT1iEY9okLg63eHrdUMD
UiXPiZttHlkuKv2aQhKcPFXX50mwfLU6yOksSxWn9TGYZQc2DI5Jd7sCX0fLLMLDasJtZPWuGGrn
R+oJNnL44+FbdjQZMSeGCCwr39pLCR0OVyGclAYFvbBok75qhJWSpIqSIn0oXl29Fm5qtrkuhsDw
t27Gzj2IWNVwNiQ9TMfr/wasiEi8A4yVwxlV9sffcuGPtFnm8LK7FzOhYrb3Rrn9DwUGfg6N+CFg
DNNDSkzE7H5rbwNmOJCdjHtNxj4G6kxf1TJvq0IVIDF/ueufjajmYTKddzg/xQ6yZW807Yxc2rZ0
rNC0NipfIUmU43calKetvF8QK6Wc1gutF8oXWm1nQGswptBIuRd54rsPgbIsDtTRgWuyAuiXsIst
+x5Kx/n+XCRG1iS7Jvu2ZrJ2OddQn3WIrws6LkbZS0wWywSRZvW/eZgtP2ur6Ih4eKzHQYicWqVe
O1J6KVNmIVNLPirJAaqLo7Qu9HW//z/s+n6aDqtGh3GtD9osxgygNtPpY/rIKddzQNKNh4xDaule
O6VxCST2RWP2vlmpPvT9k2AZ23wqspnXlnryL56KLRmsvzDMhIAJ2uRfHBqsNfqv3t0wTJjDg6YA
WU8Q9Fw1HWsemfwSrdZ7VBXEZcWbALqoxfBuMsqo6s0pv34xMuwkm4wVn1AwxvrXNQDUwr8eEG6m
A00mG1yHu444MZftqk/yoW7QjyW5W4EKAvv3cC/X5xuh4nQtWQBtOdlHkFAyM57mMtZTvHAxkVDB
Eyvl/QEzHLXwxko4MgZlLvw9laDR2My0DG235l7wWSMLmuZJmTVK7fkTy6EuGOBdhXArdp+pZgRs
CgeaE6y01qy+fg8U9iqnA4VsxNNQPMg7/5eHAIhcthhzW6kCSID/Mtof04wGs5UASReG4w/Xrbdx
0eudkEDieIkH0CNw2C2DXiZM/7ehqjMkFQMwDyBno0Dd/zOxVXZTyC93w6nPbVH6xhUXSVCDnbYI
nbeOTkda91LNvv65XTKQzSXiTWX8tY5cG3GIOPpmX84jMArMfYCNIaVuOVrBwH2XsqN5o67n2hih
6MNJQLyuROMeUsM3huU2coLCpPDFcJ3FCObMo8Mn9o2Xzq/JQErOHXloQLhTNeaHRwXSx0gb2sAT
Yyc774P1EmepfWzC9Ztf459BR/ys4sfttpSVN5ftR9WYaEwjw8iYb9mZ/QXEcfIF9cEpYsTGVT4f
X/Kk1L8BMv8lHX0K82JXMuymI7B1dSYvDSxWK/OHzusOaEImmlzT94bq4UGuyWSfTTKgc81qpFpo
FxyiYaFI95IZwGiz14CyVQJzrUk0bcTXX2VZ07IwCRBGx0lsnt5Eyh62tvUrJgx93tp8UEVKaHM2
0fGjVF+WEbOSx8EWKWRf6KvRhoxGlP9sfebUq3JzweBS1xMk8ZvYBK8BUhY7rHZSMAOxPtz3V1k4
npypHvRBymuuFU51I7B6X+DlOx6wMK/L9Vjftg4WnzvFi/xt1eBGxun3qH4Ek/2ITBF56kgGYdx4
Zwhry7efwECuRY0C1fnMkvDqLNV/95S7Q8Jj5WRUZshWIr9ht1slMcYT2Fox5hsoKCsZrizHkgQL
irNJpuBwK2t+avMk65u17X9SZEpoVrSdlqQ3KewDMGe/R8Ii9msiw3KtwklAz8MzJo+Bs5Ru5B5d
MXKweb4VI3DeLpoIz9fxix5VSNay4C3v4VmHcZxGp5ZDmScw68UuNTIvBPwQQH+J5fJg7Sj6LhNb
EuBcUmDlgYGNB3R3424QoGeOZRVjCQJ3GC3p2BUKSDoo/9MvhTkHMM0beqYM/8bERmJdz2a5jQD7
ucW21eoqwvwrND0OiMKGZMDvUtS1V58MLjvKFZNmete26/QQrr7N2zs9D9reGb5mgVMIn0qzXRC9
vfY/jYdhu/+sOqQk2rkyhndagd0KX887t5OPhiT72bvZ8fj/PDElgE2Ep4vaT/74EqkF3NhPO1XT
Z8/VbG1EQxHk7oSUISRIaRO3VnIOAgn03WesX2aDfmHNPmz7jvxgnbpemVhfwggBRlF59FlNXmjk
FDvTa4v9XgmBhdvTHjNOwjds+p2YlLlkkCRJdQ7xOcuN23fpdEjldf6JyNnPIMEUZllWXFAfgaNK
/l4lq0W/Ydfbwu5P+GMmgO7oaJZewLtxOMx+eaqQMwdc9AwiQRJxVO+pFakQWAJwim7M0C76XsYz
sCBpthYWRdP2lVyJGWrgOe6RfzzfvZuRKDrhHK5lvP8JNMDR2QI+czoasDlkAfPwKEi4/ZqceTCn
tEeZdYlsBKNw7HC0QVkRkRnvylRw+jaO9Q3wPAmQSzZlc6WLexcIWQMveCPRqFAZdRKg7NPr6534
JtAebViwtDeOHHu0n00iNXU2qHTC1fSMw9aukhUbZHHOpzKdt8NdnwWqt5y7m58h4fVQlK7BqrUU
1yJQz5Na0b+LLwwPJCrWx663a9tKouBm4PDMY7nkJmfbP3TcwyrT7F5lEz26rAFBS2N2q5cYkgz+
O5AQotkwPjF7Tlqg2MCZPK4ck7ilKADOKctjHqVaR+ajcCEf57AaR88c/ZJua+5BMRpR2FtmhXZq
pc6RJzCIPQhb/rzsKlWpgnHo2n6R+lWA4dOzQddmYrfvkTC9uAY+VykGtY0T7O58IoJqpZeIgRix
Eq1ucJ5qd/3IiDGGA9I6XkmgapYXfkmMNdAYn+hIUdyaP3luIehVmIWwVd90EbgkWN+tjsfZIBfM
5ouWUlQgUhwFcdnQLEFmegzoZXUrST3YvhHjzjmcmwjy0SfwdFKrdVwyhgTyKdG0bn9mcjgNKKDR
8GNAXmPIZ+PaurRxYTG5zyNWoTlM8ACTbPWgdeqIiYzos8BY60MP/UMYEf6CQiG/UOXjjmNyG2OJ
OSh/tg+shW9B4E96QqiPqgF+rVkAufCaW7p/9gYtzWog25+b9I30iTSKxhpawo9vu+HWCm4eYGMJ
VUVvF46fR7NwhyvaNMkTlzS+agqmZb8mrxoFqGKCM9Hjv/yxHJcwDyqw6bPyN1Q3eXEp23Hsy5YQ
KmQoDif8RO6kTZFkOHa8m5B+nanOD6ixULs4+bwWfX1A7hF1XbmcM3Q/+JAQ9ipkfRx2Ndq9bfN8
f62jvSZajeMO4EZrRxpl6q746g46ly1FauS1kH7r4K4TtvK8L0zmVGPzhuKdai6tdtyh74q96IAW
pAbNlyMG9h0uHn6CPJh2hg3mENgpR3FCMAq0CDknpo2b0JXkLzad5GenSB2u95ifwZIFutvwD94P
2HN4omf8YjrZ8V2C9lgtUNY4i17JW0bCEb32hPuCcK+52o5vNIW/mqq7jvVwVkD2gM2L2qG0AtVt
sNhIRZ07NSL+Qnc+v1iXRlCNXNHXmmE/wuX5DEv02SWoPl72y+dcLAtUZGE85oOyOlxPbQDM/COy
0DTlNxlJTrxAsgO12aVK28sdUbsVNfxrHZ1p1qbamC1l15KnIXSqq8ruHUx/cUrij9aFOrJZew9W
x0aCG5jqXfSaNNo8/+mHyD4eoabmz32V9/9OTqfqLJppI6I8YDPA0vH0wgZNKvOFkVABeA/3oZWc
eNRn6E4n2dU6u9lJZENQrSwaQIfMoKtVjTY5ZH5qrZk0KzsZcO2/IG48EGWDxFsT0JLf6/WJymoU
CsI3s1u2kv5qzWAUUSOayfgir0uDyx5CxtstvetRDLgb2/2fqQgjIDOaZRH1z77qysw68/9mE8ds
9PKbik+IscH/HvGc0e3bKKsFBSKiK77D1MajzzRNEeN9CBuYCewhYm1VazRcsQAL68dsqHZQScDU
SNydSz+aHNFBVWZ0b/ChFo7ufrU7cMOkHsENEzFgL/VKU+rKLK/Gd85fjQnBQv2mU+4KAEx43mKN
kjsdkRWXZky8qPNRsq0J8lwcQZRFWvURAVRpCmxUSSt969DxCMLn1EDyFsmIfp7k1JelOoo1mHrA
mI7U5sCCIJOYpCDJd89o9/M6ttk4xXuSzaoXIgVDECdRtaEoo2xE2CNsCy7RLv3i929a2O236J3+
dpWG0dbk2sZuiCQ0fWKZ+abWFWNtPoj4YH+M/LBsy/vzofdpl4zFZPRPl3k9K++2vqH+IHOO//EH
lCoQuPfcY0sZ0gk0k/4Jg+1v8uzhLF/LlPvVJFXeL86ROMR0fh7jHWAUiQTNUyNtGS3kq9R2vbRD
SQqQ57qCPsSRGvIhng6TtZEdnvWKQa8webYBhVZnOPGI2OEBaCcDVMczb/4zFsEzvY6zRAou0nCb
4Dlz4ZT+nqcowEWXf8D4rqhDWk2Fi0DsA0l6FjRw4fz2B8+Bh+AuwSMNsXo25M3j/9e9mUEd5tBZ
lT0TXvGULRTeI5ljBq4H/hLW7QnJAjO/pFR87ataK05VyG581PnfIJt9LeJDPEwvrG9TtUFYnBy4
Ieoutj7X+Su+WJEL4M+XjKMl2Sm7JesucmgGpeNpgWhn6kv7b8rVIWiK3RREb3lnAKCspxbFr/bH
4AuVNjV9iuc8WNAgBAggKW6VRjDqnLjWFvjyjXchoUr1aOFK/RMp8+xIzCwYuuuK3JZkAO1SxC8H
h3vAm+RdloredtxNCgExvOzGUsBwH/gXf/lAWiM4L0XKdifGFPTfa76/PWwLdDgAP3hujZMD4rpH
fuQmXv/LUD87RUIyvM4VblNKl2mJiGjOhZKIxCHVoIeNqXikt2y+5CtHRiePvk6enf/R/T/S3Jdn
VE+PKtRGy9x9IWMicWjaGNQ4tvnN1kpABsG/2EimTQBfK/uuiP7za+BBcum/OqZkTT5oKYXDWfQU
UDw2m9vHH1UNQ+KNzIyPl0wP1wlvdpfOTKWPjLeLMk07TklKvtFG5SzxDhYBbqVkwEi0/lhlCh+K
jDGg1KxdOfMI1df0Nj9yNnXK/eG5hVG1SYQWgSEuuhAyrb0B9JLxCfDZW86j64tnM+BXc5+xWzwx
tr0UZfp6f7QZPYW8b+VcjKRJf8omiG/g+lY+QKNMWIumU6tVU3enJSAYFeRDrg67CwrP3SjydmVS
TsVS23Cl+mfyBIw9kUz73VuTz0E5woGpGtXST5Zn0pAb9RqCZf6qNEjpHDcKzX4tMU/3VVocmGi/
HHAmvMONUEOkBqTrKC9V3yvrQiUN6epc8IfypsiE/lZUg0ykOGhc1EPIfCG/6LQKYYpRbfGOQVPM
Fh/tY+6CM7TSq2/6jvcmRE/shnN/J4UGfcuDplUa+0pSkdg0tDBtk0f/+SRQBo/3r+AnohPrPXdd
GSNxRZmf2W7/MaM//U5iMwYR4+lutBeMbn+eS5To737Sk1VwTeDaHd/fb+5SVeJrJjMIKUuGWLO6
vSiv6dTpBfHt4x7XEwABWhokFAfWmi42+I5E35zf5yMVHnyPVsW41A6sln5p3L1xtXAi3dbIFGAx
BbZdzgQ5tWGC05/CnF2anopZbz5sJLwqncWnoMu9k9iOqHdRdmmFj2S+esZYpVyl2AA/XTttX6jF
eRKagJgv10qWjtJuDgtP8Qovkl6M2P5REPoMSxdTjSa5El5eymNmw+p1MUGuHJ55S8ccB023D2TO
rRgZqUo7oqkQ2tHWM+3VsiKUXZTKQJ99Rlg5EPWwTsdHOP5b6NWNfjdL2zM3JgzA8XeFG8wmSBn7
Tp/qwxt2NzQO++QX52byqUbCsT/HxvgIQqeZ2ijIlIvzxYskxxcnVwzsAYuIbR9Ldt6gYe/XJDbY
ks11tHmF0JvJg+iyp4fCUyoDzg+ivVrhjco4K3CD3goJYA5Ypmg8QdvVbH7YHdk4n3ZrPm7Rg+AZ
GilfiybTGJ41fbfbJxLEmJcxv/7NBf7ERNdMwJ0rQvBDSQIE/i0Dn9ra8fFXbxqlfcTnSKdm5qjs
jdwMhUkjGfqonji8NusiWYu2OQq0N2Re7kZ0i3abobDw2b+wvf04uMeLup+82dCaOd80CZGGXWO8
Qjwq2cKupVrUFezBF66ogMsmRPwMq1AkAstZyfSxFlwvB4EJmhgiP+uWhatkCL31ML3cqH/u6EDt
AlA4Se4jp3mbHZg6lXwoIbyhJo5hj7ogItx/ho/u5gRavHrnl0yfM1Kowe2E+qSGa5G42Z5TLu6k
/rnDVTxXhbjASWEPYpwUq6KE1fl2Haj9CDg4D2Dtj4jgy+gPAOEtb96/ck3EcpgcOsGA9ukmoOpE
9uos7VZYMX53eji9IlKvF9nzj9hHWhzgCeuudW82iGyNw2ikd4R/DC95CTzA14QS7Wlobe+7tQaJ
VaE9pjCyqytyAvczKuENxqnj19T4Vr3E3hY62tEKb0u93V5zRIe4uwqOpMIs//VX+hKkMVjBSB+p
eHgNlqM6OYhfVo1d/mV8IBT+84peGqgiTQqgKh8ETLXivwv9JBXD2hOGgArGvSPX/kwy698K+Tpn
619AiiFaWBncE2bW9acVyTRJezTk4REToeT587O0ZsDshNqECUj7I3ZSNYTOmSxm62F8FnEJQwLB
qEiCW/7XmOm93P1COnR/25c3jDmGoJ61gTpNH2JcLr2V4w+XuI/xbnsWvadUKDSudZg+v9htXzAM
zjJOU32JiUSoUxaVr5MGjl1hcFIG9m7IVnZciQIHIa5RlyTqHpekAOtSPbGOQHcQhk81m4a+4nNa
XTuf4fEjcOZpVRVPURCz7Vj8Th8kb0eL4363eIFX3K+Gew3Mh0uhcNE5LQLeFryw0a7eqLMk+y3f
TWsi3GqA4g755oh4k4PGbIAOE1B4EWBnPR+/cIn2ckwf1f9t5yACgaEnFabl3Xm3AgDr/ApzAZ4P
ijOqK3bldiOQlYZ4wVyC9tnGmxcwjsMO5FJRSlBapC66lWpb4BNvPFxkpBY+5gO6f4HemKMZmwYd
/GRloXuYvD9/FDKINaita8dGFLj7kCo5dKAcY+7QA2hBV5xio3sx4YApugt2IbKkuIyhNPfMhw6f
AGIXgYeuuCA99QvckZixTMzcquZ0FIpmGQ/G7M5fGk8ZzoJ/U7SLqRiN4V4zHNiwmSS8pORsKBjV
RJh5giybVmEXlXZLc+1PznchaKBdo2FTEZKDdAZV/xxMHOdFUkmlRcn/PABA9Y8qE/O6np6P+1tW
fVDnBZsV+s6I0HPZ/qhsKTV+VbQTmoZHDMghwsB85q8HGfp2X/SzBdRTirkUpP2ZICtMwgFmYOrT
iL1FsGqq8RXDvpWJtdgxzoe1T9vQ8x+gQElm7bs+MSwqQoYeopwhUSha4dNIBJ4Ww9cWfkVD/BdP
jh+s0YN6Wgw8CraxJH1YMVKBgTLHaL3R6pQwqduLkegfDxpfyhGS/jGjT2LUXLMHvwwSFHizP70/
vo6b4K69pMd7UpjPQ4aC9BzL/0O6tuylMhpbEJf4raLa3OX13BtqMvzcXCXw4b57g7IyL8LP7P5O
sqgikDSg05Y4YOFUeopY/aANY0ZXnjlkqXrgYwyuga9ZnB7zNjhcdGkljnKnCS2OC6IZXJieQGCL
1q3/dwKSZJY1/eOWcKbvi3DHT6W+ryytvoUNAgQKoxuwRkSzX5HgvUCD0d3f1gj7CI/qBrQ1VfIV
oZvr2br761XdgL0SR0y+qNTKSwmOQHgslaH3rsHAERoMWZ4Zr/i/B4oc4MvA/65fW9KsMOt4da3U
R2gtRK+sjRVgsbG+jG/zH4+bfOvSz32r1NFH9RlY4qKdVt3NW4MzZh7bjm042h7uXSjjFXP4HDg7
xRRv5GTXF0O6jZ6aLvAa/YKDrQySgk9rUtHjci0EzYZwTs9henuuHzIa16TDmku5rVc7mDMA2X6+
D/fuvmatbvXD8sLgHawlql4IwCdrBLvz3Mu5K5fbmgiY834YSx+pnrrKbhm943Wv279rxvbbpf8S
ewcdE7JXuqvIdpWK1zI6blxc4DSqOQRXIR88fjLAwlOxMdhHFo6uq/5e+NM+PX+9SHQ40B/Q+05c
ZUgAnYvhH4kjf+qRgxLhxjxkFNotTaozYUcRKCIOp5ATlN4rJSlYzqOawFxYXdMR4K9qN8/aC0sz
Ez5q0glTSxHOF12J3U1Umx69le8xc25LOMbGIJY/6WZwvK85PiFz21M3mMCddkRp0mkC2Id2ycDd
1cdCHruyyJLxGFkgVdw3wLvwSKbcVkyQs/5ofF3Vl99/r8wdfazL6oDvLzd9FrY7DBsl9V0fhUjv
Lii9JMkh+tRWx8JESI2ISRVmaf+ySMVAkC+RwuekRSSG6QcnOhLwhc9CBpB0ne93LaFIjQ2SRX4C
ZG3uQVxia5D0Waa5Mqs0FYQrc1+qV427ak0ml4VGkxR9Q+bMOEpY07as9QGeJ8rcvIaIE96nBsNJ
XN5JVmYshWftbjZzJHFSuQ84VM2eelEv6d6fdkGNULJf7vpNgVQssd+VKwSilqhCaLCRNJd2KO1v
Ui8bS9A5O0ft9/FcnadUE8c599VINueVXIaWrZQmXP2Cti5QkicOrKB6/1FulMWk6WLbwiTCT/nd
VUohg5oyoyUDxgQsZ93YTGeTEh17XWtROBMt11aGBJo/s6lBhmxleOg7SDwpOF6ZQFCkLmWDJKnz
8yzMpadBLA6TUlgSyJYdXAW36Gg3bbsar5oYeVxizPE/7ALjNIbtaAiBxj5lBmK/dKUHm6H8ouBP
CTei1ZrpcnwaZnoja8AJbA7aJwOg4bpt2ZMDrhtqE4TxfP+kQ83VgJWP2QSjUj3MRUam4pJNuhiy
MmNHEBnCFWnXfe24g4qaAu0t5RDWa1gF+FN2Wswidw4duJwguWt1YV93qVXO4T72lLr+ZaYCCRnZ
GVt3T0ApuLkdaW/Tvdnb5kFI6EVKTlbkyPHTX5cHy6ZkwB9UurQ36jJYz+GixvhbGiLeddEtPMAN
+vV/47mOVa3HuTi+jViTC4UILvqYC5pCMPQB8Z82pUhM2Vytq0m0yYGXulcFYNR8flGkDkPrXJDQ
In9htMHRM0112ZYoD5aUAkq8BfuOxP66/BsqrOhDBXOYxYJNmX3SGQaQBsisLuA65uZh+pUOoljR
uzOJCGGnz9v4OqGJNzuSw44AbdThEljORKspYFy464eAzhBL5oGDhzZaGi8qjWZ2xgFAkFi5C5fr
W+mut4Hlk+krGJE1FDkKsje4I7rxyT/BHzjIAdzw7W5CXQ/zNioQCc+AYGcIkIYFO+xt2VJAfp4Q
TaQnCsBUm341CxLFiurN1kpTSbNvg1nygK/WtuCYMocXh+xMmGvemCu+BQOmsfwzuOd/CTz7Qbv7
5lh8BCcppqwpAvBCypbSHOU+uc179mXYe59/P3EyKMsxGjl+Zy6mYj1iwInh1yxTl71NWkp3DSmX
9IrWVnlGJZZuGa6oymr1PMytOAoWyoyCykigVGqq/kyv4PmBELGlzSRwXXtPNY7GSL2+GOvQlbdE
MQIleYMBotTuI4uKTbUMnBy14HRHVMsVjfAAJC9hbFSPwijQEYiJJJkdu7NRfpVSRXJvO7yV16Kk
PovXFcpqhyIkXm9YoBHpvSSE6OGKmLVhjGahPh1TtKvCa4PIh1VF2bouNqHixInUQ8zYl1u0Ho52
lAg11p0W+G+2Phw+oqsh8ZUoLKAiTu+H2MDkB7cRAfaqZG6w4P1saqOJ+/ManIK07DkMInigRGVY
xe4yUIIe/vTMIwzO1SK33CLdgfqm89HrEPhb1m6YT82Gkqsj1cl/KdLHD8dJV5RX/oDPVqwSg/ip
2RPskjQCm5IPwDUuu7nHiYi+SPYx6n/qgDx9ybq4MINyl6ZB6ToLc/qHX2nTITOdYJtw+BDAFadR
qWEbJWLExiEEGc3sQOZ5Q7a6O0oJufOKJ210Ps1aj8BysYmUKI4kHqm7SjObJ+wG4siukMOn+uZT
o/ueEF3q11/kCrm1OgB/sNUI2dlPfrIRlnHGOCKJZZgB+gul6P229LiL316NoVnZ37+EZI4ED4fh
fpJBItCU0dzrfZBAV2So8+yYr83liiEvSM5pShwf7v+l9BAvkq46VhyrjC1kj1UhRvTsLds73nBn
zuTnvSJGdumiPIeF0Sq3Jziz4n0oTBeITpPQK6G0G4EGskn1xOmv9jMtIpKFmaEPTTI8H6VUvxFE
OyH5Zrg8cqWmFgQBFyizZ3gg3rEHyZEtKZRRk4na4Zfn4PsRgOXqZWookbKHbnW+TM9mUb9C48Vw
djRxz0davhW52sJ+3btyFdpmxbKOEcB/Iq+FUvbNYnzKLOkuRFkvHdQlx+/y3Y25Ka318mjjFuah
lcpSmV84FtFsK1ZBRs8Sa5rBK3izt/d/264T8+VOyFJUEaAV7+PtnL+WCg4ZLSNq+X1mOwFVtz3P
8uX6ormvxmu2Hd5MbFCkmczFy7Ze57mJIscmyfBNzesLeWcJSz6GlOgevm8FgYA3ul1B8MB1id+N
1cRJlk5lS1wisIZMtCq1fGzdMN3bpWW/BlxRtzepUaDqKJ+YLEAlvzGCUmGUc2CC8z96iD1JoTQ1
6LYPs87F+FpafGmDZdGpEZfoeTmdRCYqy9iTUAIv4x/eW8JkPNW3v1Uy32HhPYmNR7rwC2Uvei6U
42CKTPj+GAN5dttff2u6/hxSrLkMNGHmf4OBEfQPq+sDoE/7zuOzr95FzODcJ9DYrLz/XW3IcJdt
mq1chxErcnqgMjmTgiS3AuQPbp3RHzoeULzvPU5C4KV7iKF0jWcQ9Ljv1wrekzGNJwIaMdtFJmWF
Fwa4wENcn/jnMti6uNvD4HujZNFl/4pdCMp4BUBbXySZs8Vp3cmwmhEW5WwM3bJmWNGV5ucusqTZ
mVpISPLcq2XkIHL/5uXycBC0e+Ur/xYHAgQS+mSek1Hap7SKuB0x7fWI+K3K+xBJ/W3wA6ndvcop
TDU4kI88cI9t+M6mS98qy8wj6mjqc4RkFeRPwxmCEFt4Bmb6PlG0wpk2cti6Z5oZeg/HZSSu0XG2
DfD0ZT6YMzw5+X2c/tDCkW/cYd4uLlD2InTv3r0B3zVo67VHw7Tex3yXZuWFPws5krogB6OJSVRQ
a5jZvd/ctg3Ov9WojLtsUfh3kBAS9b7HmHha4MRN2Rb++mrksAWbVNQheeM68S+ZeVkGO89SIb64
Z8a7PYavhUdhnJOslr8Ab/ZGZZhsmmEzqtQ36LeeieyGIPaIDY+8oP4jCvDP/iR7tabpcKlKllV4
MA5mvK8IsganLU7eg0f0h6QqGvXz7AOoqID8hzt4unt6Bt/OYB9iPSoOLvuGfDyfuoOn0OPUbi//
eH2CovzmkJWx0RdYmHMTbwA18mxE/ghSLVh59/XABbaKIjmdW6kXIT26R/vhhdSfyo60mKf/eiv3
DFHz6bJi3AQNfMjhsCdP5XYT7mDNCb9Zj2SEDTKPudrwBpxR6dyhkgDE7M695rp7NVoxtn9PJRSG
tIhsbRMzSikE1/u/MjAiCzYJnHIalctx4rhdxt6Vzhg/2Mi9w0f7oovWNQGOzQY+B+FbJp1w9gzf
Pznla4BbwJz66lxtMywVVO6n/x6aRdNCc/MbDLJ8zB19CyL9/RAXM7wAti+nYUhMif5UE01AVmEl
Zy9ArFV+AjB7sgkXuNELu4K2U/OCfv74Z/4BeHZbZe+G3LYq4uyiEPhoe5Vm4M90ha8pX2hs4eZd
FdGOI5TAFunrAjLMaiGBIWPLP/txXy/tzaYJyBMxGgNbXtkLQxGlgrUvs2L6U5A6v8U/3164m8IB
fKQBY4yx9tdWC6/lAk2RW+VXWMGTN3HiQVEH66hVC1E5/I1m9Htt2ILRTvUMk9ppiIP2dvaOqWiP
wAOXBeQn66VtH+zEMdtTbbSMXANxi47kI3vMz5c7lc6EZudVmAdn1FORrBDHmAcFNxqqxn5FWkei
LqV17aooaj7zTFQfaKLuWuuEPXsWp0jVGMAKKuHWE3O8Vkrb1ghDuUWWoWlobkbM6VAs+9CANTe3
SGWMvqwZrf05uLbaUAOXRs2hBpFFF5UTBTrO996hVUDlNcasMxHrIgBWso7bwomDQqr6SsbofgwT
ORO/ap4hYComStEIiHkzvx+ZFR2tWX3uKPG8SET+lGSNlg3AxaE1Ql3YLE3SZe5ENNqVFFxhoMeM
w6uMSehdaLyj7R6Fhkc697lpb1rmbBs/aC4B46UCcWtD47UwmX56zaTnUWK4Sr7e8cS3rqBdTkuB
lnrikdW8eSXKdxJCB3napsbSODP6INz7TPm9bOB/6IqCWYP0Xi7+hBb5w1J/zyVmRgwthpyA2gLn
jPu3xb7FejXSUXdBOyIW1PAR2g7u55xENHYkQ0kQffC5uFceGQkGU3xUiYwmMxVq4Pv3voVZHRS/
jP//3CALLEf14IzAjdItb5yCrQId8q1gI5rnvgkqc+Yh6qxapv+8e0wKZwq9x2IcMzeNC0uoNP8k
7+txCdu+YPm9jM7tcffSrNf9gCYQ8ZXydCX7Jksl2lV6FyPvWJb4n4M8x58gBKiAW2Zqfx3CO28M
vFvaSfaGpAQmmE1n4lYlAtVwwQ0areLaahwgklOBN5FSLKtGlpnlZiIrUPtG53IeAjcqW7BzTwAs
4yARI/sbR65vfbKXSHoeYPMag0VTX4UuivPLFXkhV4zlVH+wIQ6xOsl41B/LAZ13Hz8464MJ3rwQ
IxfNZ6jmJEblBLDfY7NlnRu6/XavH10pYBZOaXdS+ngBQQFwC5thnhNb7Uri/qRciqKwUV+xUKf7
YYyQkHSw+u0E/XjqycK+EZ2gXNSgzrgJjqjH3hr4QipNcyAHvDplxwjgHHjXBzssfB+dRr8dHt5b
HeTadcjEcek2vrdJJSUw1XxkOoCIGRxU3CkGnsE35zW4IhZI4cwqlk2FnwlX+zWlK8jvr9LES95I
q8Nw59Q3nzwIazbGdDxQfUo=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
eERg1Iy1WKSyjyVvoRwacqCMp6BGKmDEq9r28RNgx3LfpZEXyRjRjfoMT8jsQEUXCvWsQwc21AwH
0wziVaSXeQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ATVzf6PK/3N4J3XI+hCP4pb0u280D51igWJGNsvKHd38o0xuKqBiQQreMmMGnnhWZU0LTrnoJ4mJ
o+he4xAmtRk3S29Wmb8VCmNGbjF71CKo9TMzF+EuMgwjYwea628q/aiJVn7EVEpEdVlRAUuHQ1Nc
1MDu0ciOFoo1Rybp1gM=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
NW27jfO0i5E2NNydzeSOPFdtWdWfN2YrLekSOukVCUWdx8QlZpAlOxEp2nscm0+tAASDHpTH4aAQ
lyrGIYWao9kuaWtsRJOWrhuXg1M6tcn35HarblKiJdVU1DyYfcY9h+Gfzvpjc/pF3kqAAIvzhxKn
QSanLNBq9gUuDS3llM5NEclvuyRVDIqBX/swc58gjOp88AG2NBGwxxuEuzWiSVwyZZT42Xxj4jnA
Or9xkCEU/eAI3eNLBfT8OK6YrVLC6TGs76d3dtToE9LmIAS45QgqMjh/ctR0jQgNOZbo87YPX0/c
oBL9YJRuWLlCBgDcHAEk3HxFl8FWvXJP0pX8WQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
4flJUe5VqP9x8iD/a62oF9gaDnyRxRoifIQ5baBGmnFj+4BGNd4klnKOEDOBB1aPoqM3Uoa3Nt7z
jjADEbQznD48oWi6KIdtSIS9G+hCheFwtIx5yBiLvUdDrM6U/ORiHwEYybqkHuROVnziw9+1l+MC
AityTqqOx3hGuynUD0Q=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
LYhQ7tfXgIfRrGBioeyvxTZvEIjEKfmFuFA3JIpmJ2Dq/5XACdHxi9+bg8AiYGZO0bQb3d3oCo+z
5Rh2V7SzJKSAwkHy+VXLuX7Yw6SptZBr0fdSbowIUVyYvtEwU2U4qbBJEmdp9nSAHPQ7Fv6hR3pD
8DdQrt4tF5ZKZE3uR30x5zE5kJgArrgTtbvmcrlfURq7kL9xNVfRTpwptT5CZqPdG9stN2VV8D8q
GVf7lhgvKYgoeY/o1JDOPMzVmMBeCjtVXXBjAALCDyPLAHjnS0GtDUoH69ibBPJQw0m8dxU66eq3
Il1VPNzwf/ftaZpANLaMvllRLVlaYIMH2l99CA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13184)
`protect data_block
YPeuHY8srKBBQOsWKmwNtSgvLAP9taPcKVblqrCClJzflZwaji2E5Mmk0/9xx6WFxiwlhymxo00e
Ll+FPWOrjYR0WOi9qy0Ny0icaklLKCQxIUhk1rHHIUmBJ+0VZRQJIV+0+wL5RFw464uf4AO4ZhrW
TluAfdUKrfkxge6QdX0sC7LWx/h2p5HT/FQABQXly03Hh1uLqJNogz9Q7YMt6epa6mEeZeVe0vL7
VJ449ZHorA2R/DR4zOLS3SgckYMYoEBtS5DjYsqa9FYKMtVf7cuJ6uSl2iIro2yuqIeekHZCtoOo
3IjYqYdHugTkWMrbXEAlwiPjr3ShOLZRsxY30T4mCuCNmwnzK6YSLc0lH016FzuQMCbUmVKdAM0O
8IJ4AVvhwLhlXZsgckV8Eq3FQoP0BQ07BLJuFSVQF+XUIwamDeRAQV2bj6hfnyJyq7YG4st4PqIG
UNL9GYce8GRkoKMHzLOXkJFimtE4F3daW09yIY+j1Fovst/hN6+nahTfBRMa03jYePeCB3zVhYSo
NIdRa58jiNSQW/Yj1ZADOtg5LKDOwyNPTVSQq8+UBq4x2eImoqN0KibvzpayviI1O8ZfYMlChxc8
oCmBCf4l73YFDrB3ggbj4miXA34qZhV9tlpwqlPg9veeL0okKhneE5zJPbx9hrycnAMGFQWYX2nw
2Zi292xVzi3FnHUj3C7FZ214SggINQcBbcCM4n59azO5xgMUboaDew7wvh7obDUQwf5rZZBq3Sfg
oxt7cSXumet9Rd+YJjgoBPGMyDU1qfkyktRDka2IILzufTbK5UVxFiNjncTmeD6/xBfL4xga0jqr
Han7EbIxTzqKybqV5jqawFTmHy7ymtvyQLHVFv5hVxHUN/+puMvUxEUGXDGtThZDHF5AZ8yWEu2S
KaT6XLwg+yZaVVNifrAsDcwTfepe3824es5VxRGKPGDqewnvZxetEfrpxKyGiEa25ZBKDt3CNaF/
J14SKAkH11FaN41cJX0D/7sGGN1Kr8sOv9SNYb42dQwiL0FXLEuJys8pqW1gZzDP7j1KeQtG99pW
lldhry1mjvEBmEDK2OBwXsvQfPF3ARRo6/Owkkf0+nDqnkKWQnX5rnGVsxPKiFnFfzV+7VlF7pI1
+e2PlFgHpd1xtqYTakAyduGlWpkRI0JASwUT0hclFFDsueDId9ChC/AdKoVUcQ6VtxyDAf0qCBXY
qceQHp2aWOoJWXvsg6KwSxDmi5gi8rdVEuGXQAf465pWFwbzvQVAEvnu0KMAhTcADO//xCKgc+N/
OPyGQrbTzPdumF+5DilrHNf4OjZ5VZlYIP7xCbXUMZZuJmZLqRRAYyt+BH+FmxKc5ImKu9fZiAQ2
f/sKAkV1ifIZcOZNp5LufC+f3TcjubQxZedulHeHQxogWLvrq1f+JJuLRfAYM9Ybcc9YG5XxlXcI
xBws53htYyND78s9XyJZhhbLB9Vh6/+XNzozjxM3aJoOacd6p0uJlhKmPUgqeH/c+9afltbS/9Hb
zQwFab5u2E0h0pyzlKRTcxSKhw1UI/FyagqA62QGGWMz9GQFyR2OkdEyffWUjOPcmLMZSbRcdGCe
X29rx6oapyElTcO2kbuUlTdNcARhlEwwjm0od7YYvUQhHsHeWVFfXG93Ck9ahfA+oxBqZA7v1wud
E/2Is+C8K7m7zdpU5WgTTp8r68Hh0y6Oo5t/HlU+cMviY1aXBvUtv5bSutQh4126CPkJBmvisBz4
pNHFw7fXh83td3ArMaYav4f5rAM5eLuWZtj+Xv9I4txG0STm6wOYKVGeM9JwK8ffplLUNSgwbI1W
IUnWynhDWCcW7qEAoGcYpeo3wnRLQ6YnoE3LGWjUK3B1+YivoyjxAHCrJw0LUV0oR3HKxkD40BOK
QX10e+1cj1kZWewgmkp2X/tPT6wNWg5WmY6RqMrYb68a8SNmrZFCUn5BL37Td4YLk20inaH2gz5u
lRnTtFuuSwy2S4EafErqlNeZ+I2j6/4GAXuwDBKmHjh43d9ptybU60qTOAR66sNiKrv5doFwX6Q7
l/fjF+oqqIPyrhM9RGPAIYwbtZdzvB+ivLqEhzIqYNtCoO/LT9V5yaisL/2YDOaJ0iuB/aJl2Xe6
cFDSnM7rxWAsIwD5fqL7GVj8DqwSaEZbStZIgFd7BdPvzb8567ndKM43Ir7DFWEnrjz8TB6FodTV
vSfYq6p6AMmKjHxj9b4E2Ki/TjE9XXydJBHT22e2yv7FFW7tTakcErTWa8ddMIwjECDFSxaNyVB3
H2QZ4DWN1XJNMggvlZTbwbKEMFWeGwA4Bzpqn2NGMWLkFXALmUWOk76w0/kinoLnr/ht3XB3BXGq
Idy3DC1ibBoaqju+J7MJdCISE8h4G/YMtFYxAfg5+5D9gzX8g/LmA7GTciJ40HvAFg5EzLNc16p1
vsMjpfkHS4t2g4//whPI272I8IfuHMnge/nS2yZzn2Dxor2obOgA27lF4FMYxyEWaV8jN9HcYpbW
LDoMS4f+wnUdD1rJP6mQDqwXk2EFItoYYmuVIMQ/Iw07ec++1SyIe6f0TPKZ0FqWToN1VbBO0Ugl
F40TlJ/S24uCXLVAGJ/sG/Z6hPlcaeLEOZOcQFsyYgBzgZMR+4/XHr7TCnlS9ovpBgiA5aH+zweU
kL0eyQWYQtycW+5UgEaPArX7VoSJRIUab8DDj1lA5gW0oco/hxDG/hvMGHuOzB7iyifl3IvvdZS+
g6hkKrvavOO0k82AwMMgAR2pq4GZDnivcxCYZpe+KV1CBz4SGnxyLjoCTdRFSvW/3qpEAY5SdvLS
Wc5gTeqR3Z5l0CxE4ttbjnJYbsuKh+0m/eWYe4jfrvMmgJzEFvNqj0wUWOGJBsCbJuocofosxcuR
y7xoV5siRnZ57As2SFwDdeGY2LYDAj1sZjRhlnPlwdpJl02dsaBZz07xucsFUAdbS9qclEOYDL/r
bjUo1wJt8PinAM3hLx3OG7Gr4xPnmNqrma0UuECCRxWPaQxP8w1clATDuNnKObWk3Ul0/olA9B3z
LTUeXnq0zliMuN4UIQFgMwRytVZuZqnOObff60ajkfcafJHrz7Viyvv2RVT1s04wNKlBqghYtinV
OoTRtubG/bdqHhVZeecTcxyKh9j9Zkf8TyIcW5zFHcbC40L+7mve/96mtl0TnXoSBIDn91UMIPrG
3vrcx6d1ZmtV6bPNo06j3EsQoATX9h4cUTJj/DceHdgRLxF6vnktURKW72a3+E8IswT0XR5p7kkO
OX7ABiGx7GBGD98fDqhNoAmPbgDTavhmJ2RlZYJKyn1pXNJ0QRiwXLtXYxhhmL/kbhKZyMwV5Hfm
VEW0r3niyim/Qndxu/hmsYfWcC8LScgcLMzTET4Ft26aJcmtNRvYKpF4Ru1Pt7IvUDqhavEqJlaJ
lGG79+/p/Y3dWkwsQeT/Rxma1AKIgllq0lfQAooGtcs+Mp6DBpKklHL0VVSUVvVQdTFLh4GKkTLA
/MJAmIspe/VbzFClaIVoJKmWW6wNlqYRejfO1W5F5uby8qHXkC7XUOEJHPlLqxzZCR1p3uZVTwb1
VRj654/bsIgDNy2t+IpnyPov5be+a+LPmEWZWCf2BFrju7Of/WCSdMP5Xi4mARvSYIJr68rf5DJH
8BkEwYfGt/ls78QVb2WbZxw7KhcdzIgP7yv5IuK2f0fPOseM476DXQhTqwZlsXCAWcjeH/tIOsBe
Ok8lHEuWaR3GPYESx14UjGVqj2iDqF3+ky1c74T3D8uTzh2cvc15T71ylmUwH5zIyznDCq/yoN/k
G6RKkb8hL4lQE1XCNVGy81Yy0ABO/T7ca8qlcXHP/KYkiZB0S5m0egmIFHIAGA8MtBgyFYPMZBnt
MB24afif/wgsoJcRtN0RZVkrHIblySM2Lv5hQChlmBENtNd5t7wP8UP5P2AbzzQYMQ/089jq1YpT
Tp2PhGiphEF/COup2M4cEZoNEgLiQHoHRaHipB2/AbDrSRVIhKIYY23/P/V3fmw/OBSM2j3t2A3Z
GLrsPQmOQoBjhtksLIDpX1rYAcaHnXpFCTyJrl7aAIzh4AAfkDrVSO59I0qBf6ZAkTDJ0e+fUGtM
8WzLjIJhAtf4isvHjsEiED9w/T5Oe6Cf8PHnpybNQ7ZhdLS4CjSWAbj3MIhl1PUKcc4rqQPYgCVX
PQcJvXPzzwOAtBWwlzc4cyfX1ElJbT8qwpj+gXj+d04jI11iEgKixDmCpcFTZH/319QlwGvo4Mis
MsGvMbVIRrOoZaL2cf9Haqse1dvVU1bQ+wvA//2XX+1BasWpEjcoYPRHjCff4kYAa+NL/FKVDdsK
06JzYB/pPN4hQ9/5HB9Zt1BaI08h5MQUTsgdtUAY5BsXjUYuDtFMAozirjkbl8IBHKbof6T8MYO9
BFO7Mb5fAfGVIgBOGaR70Mb1uRgCd5WJZpezJ/EF0TLVSmcKsT2eS2PLNo9bnbQDTslsjcLEJtFC
YFre+ypguShDbB/oFudreACnZKwFjAtkxsLYNS8QS0n8o1Pz8ugcjpK+fA4MhFJQ2KuFMEBEhhJy
7wE9ectEXQy4bg3s1jMt64tk7QAgGC5hymuZ8z+R0RbZfeGVzuW5XjuRqoz0GLQqCnQy84vUdhFW
ru9itICU2H9tnl/jIdSrMESCye2moi+Bk0XC1NKG+RMILydcQO4wFUAY/MAyyK3H1SURHr+afMD0
ZNdEcwkwLma9GXZUu/go0NBZkAvf5ftrbC60YnhZUvagviXK+niQu5IazT1iEY9okLg63eHrdUMD
UiXPiZttHlkuKv2aQhKcPFXX50mwfLU6yOksSxWn9TGYZQc2DI5Jd7sCX0fLLMLDasJtZPWuGGrn
R+oJNnL44+FbdjQZMSeGCCwr39pLCR0OVyGclAYFvbBok75qhJWSpIqSIn0oXl29Fm5qtrkuhsDw
t27Gzj2IWNVwNiQ9TMfr/wasiEi8A4yVwxlV9sffcuGPtFnm8LK7FzOhYrb3Rrn9DwUGfg6N+CFg
DNNDSkzE7H5rbwNmOJCdjHtNxj4G6kxf1TJvq0IVIDF/ueufjajmYTKddzg/xQ6yZW807Yxc2rZ0
rNC0NipfIUmU43calKetvF8QK6Wc1gutF8oXWm1nQGswptBIuRd54rsPgbIsDtTRgWuyAuiXsIst
+x5Kx/n+XCRG1iS7Jvu2ZrJ2OddQn3WIrws6LkbZS0wWywSRZvW/eZgtP2ur6Ih4eKzHQYicWqVe
O1J6KVNmIVNLPirJAaqLo7Qu9HW//z/s+n6aDqtGh3GtD9osxgygNtPpY/rIKddzQNKNh4xDaule
O6VxCST2RWP2vlmpPvT9k2AZ23wqspnXlnryL56KLRmsvzDMhIAJ2uRfHBqsNfqv3t0wTJjDg6YA
WU8Q9Fw1HWsemfwSrdZ7VBXEZcWbALqoxfBuMsqo6s0pv34xMuwkm4wVn1AwxvrXNQDUwr8eEG6m
A00mG1yHu444MZftqk/yoW7QjyW5W4EKAvv3cC/X5xuh4nQtWQBtOdlHkFAyM57mMtZTvHAxkVDB
Eyvl/QEzHLXwxko4MgZlLvw9laDR2My0DG235l7wWSMLmuZJmTVK7fkTy6EuGOBdhXArdp+pZgRs
CgeaE6y01qy+fg8U9iqnA4VsxNNQPMg7/5eHAIhcthhzW6kCSID/Mtof04wGs5UASReG4w/Xrbdx
0eudkEDieIkH0CNw2C2DXiZM/7ehqjMkFQMwDyBno0Dd/zOxVXZTyC93w6nPbVH6xhUXSVCDnbYI
nbeOTkda91LNvv65XTKQzSXiTWX8tY5cG3GIOPpmX84jMArMfYCNIaVuOVrBwH2XsqN5o67n2hih
6MNJQLyuROMeUsM3huU2coLCpPDFcJ3FCObMo8Mn9o2Xzq/JQErOHXloQLhTNeaHRwXSx0gb2sAT
Yyc774P1EmepfWzC9Ztf459BR/ys4sfttpSVN5ftR9WYaEwjw8iYb9mZ/QXEcfIF9cEpYsTGVT4f
X/Kk1L8BMv8lHX0K82JXMuymI7B1dSYvDSxWK/OHzusOaEImmlzT94bq4UGuyWSfTTKgc81qpFpo
FxyiYaFI95IZwGiz14CyVQJzrUk0bcTXX2VZ07IwCRBGx0lsnt5Eyh62tvUrJgx93tp8UEVKaHM2
0fGjVF+WEbOSx8EWKWRf6KvRhoxGlP9sfebUq3JzweBS1xMk8ZvYBK8BUhY7rHZSMAOxPtz3V1k4
npypHvRBymuuFU51I7B6X+DlOx6wMK/L9Vjftg4WnzvFi/xt1eBGxun3qH4Ek/2ITBF56kgGYdx4
Zwhry7efwECuRY0C1fnMkvDqLNV/95S7Q8Jj5WRUZshWIr9ht1slMcYT2Fox5hsoKCsZrizHkgQL
irNJpuBwK2t+avMk65u17X9SZEpoVrSdlqQ3KewDMGe/R8Ii9msiw3KtwklAz8MzJo+Bs5Ru5B5d
MXKweb4VI3DeLpoIz9fxix5VSNay4C3v4VmHcZxGp5ZDmScw68UuNTIvBPwQQH+J5fJg7Sj6LhNb
EuBcUmDlgYGNB3R3424QoGeOZRVjCQJ3GC3p2BUKSDoo/9MvhTkHMM0beqYM/8bERmJdz2a5jQD7
ucW21eoqwvwrND0OiMKGZMDvUtS1V58MLjvKFZNmete26/QQrr7N2zs9D9reGb5mgVMIn0qzXRC9
vfY/jYdhu/+sOqQk2rkyhndagd0KX887t5OPhiT72bvZ8fj/PDElgE2Ep4vaT/74EqkF3NhPO1XT
Z8/VbG1EQxHk7oSUISRIaRO3VnIOAgn03WesX2aDfmHNPmz7jvxgnbpemVhfwggBRlF59FlNXmjk
FDvTa4v9XgmBhdvTHjNOwjds+p2YlLlkkCRJdQ7xOcuN23fpdEjldf6JyNnPIMEUZllWXFAfgaNK
/l4lq0W/Ydfbwu5P+GMmgO7oaJZewLtxOMx+eaqQMwdc9AwiQRJxVO+pFakQWAJwim7M0C76XsYz
sCBpthYWRdP2lVyJGWrgOe6RfzzfvZuRKDrhHK5lvP8JNMDR2QI+czoasDlkAfPwKEi4/ZqceTCn
tEeZdYlsBKNw7HC0QVkRkRnvylRw+jaO9Q3wPAmQSzZlc6WLexcIWQMveCPRqFAZdRKg7NPr6534
JtAebViwtDeOHHu0n00iNXU2qHTC1fSMw9aukhUbZHHOpzKdt8NdnwWqt5y7m58h4fVQlK7BqrUU
1yJQz5Na0b+LLwwPJCrWx663a9tKouBm4PDMY7nkJmfbP3TcwyrT7F5lEz26rAFBS2N2q5cYkgz+
O5AQotkwPjF7Tlqg2MCZPK4ck7ilKADOKctjHqVaR+ajcCEf57AaR88c/ZJua+5BMRpR2FtmhXZq
pc6RJzCIPQhb/rzsKlWpgnHo2n6R+lWA4dOzQddmYrfvkTC9uAY+VykGtY0T7O58IoJqpZeIgRix
Eq1ucJ5qd/3IiDGGA9I6XkmgapYXfkmMNdAYn+hIUdyaP3luIehVmIWwVd90EbgkWN+tjsfZIBfM
5ouWUlQgUhwFcdnQLEFmegzoZXUrST3YvhHjzjmcmwjy0SfwdFKrdVwyhgTyKdG0bn9mcjgNKKDR
8GNAXmPIZ+PaurRxYTG5zyNWoTlM8ACTbPWgdeqIiYzos8BY60MP/UMYEf6CQiG/UOXjjmNyG2OJ
OSh/tg+shW9B4E96QqiPqgF+rVkAufCaW7p/9gYtzWog25+b9I30iTSKxhpawo9vu+HWCm4eYGMJ
VUVvF46fR7NwhyvaNMkTlzS+agqmZb8mrxoFqGKCM9Hjv/yxHJcwDyqw6bPyN1Q3eXEp23Hsy5YQ
KmQoDif8RO6kTZFkOHa8m5B+nanOD6ixULs4+bwWfX1A7hF1XbmcM3Q/+JAQ9ipkfRx2Ndq9bfN8
f62jvSZajeMO4EZrRxpl6q746g46ly1FauS1kH7r4K4TtvK8L0zmVGPzhuKdai6tdtyh74q96IAW
pAbNlyMG9h0uHn6CPJh2hg3mENgpR3FCMAq0CDknpo2b0JXkLzad5GenSB2u95ifwZIFutvwD94P
2HN4omf8YjrZ8V2C9lgtUNY4i17JW0bCEb32hPuCcK+52o5vNIW/mqq7jvVwVkD2gM2L2qG0AtVt
sNhIRZ07NSL+Qnc+v1iXRlCNXNHXmmE/wuX5DEv02SWoPl72y+dcLAtUZGE85oOyOlxPbQDM/COy
0DTlNxlJTrxAsgO12aVK28sdUbsVNfxrHZ1p1qbamC1l15KnIXSqq8ruHUx/cUrij9aFOrJZew9W
x0aCG5jqXfSaNNo8/+mHyD4eoabmz32V9/9OTqfqLJppI6I8YDPA0vH0wgZNKvOFkVABeA/3oZWc
eNRn6E4n2dU6u9lJZENQrSwaQIfMoKtVjTY5ZH5qrZk0KzsZcO2/IG48EGWDxFsT0JLf6/WJymoU
CsI3s1u2kv5qzWAUUSOayfgir0uDyx5CxtstvetRDLgb2/2fqQgjIDOaZRH1z77qysw68/9mE8ds
9PKbik+IscH/HvGc0e3bKKsFBSKiK77D1MajzzRNEeN9CBuYCewhYm1VazRcsQAL68dsqHZQScDU
SNydSz+aHNFBVWZ0b/ChFo7ufrU7cMOkHsENEzFgL/VKU+rKLK/Gd85fjQnBQv2mU+4KAEx43mKN
kjsdkRWXZky8qPNRsq0J8lwcQZRFWvURAVRpCmxUSSt969DxCMLn1EDyFsmIfp7k1JelOoo1mHrA
mI7U5sCCIJOYpCDJd89o9/M6ttk4xXuSzaoXIgVDECdRtaEoo2xE2CNsCy7RLv3i929a2O236J3+
dpWG0dbk2sZuiCQ0fWKZ+abWFWNtPoj4YH+M/LBsy/vzofdpl4zFZPRPl3k9K++2vqH+IHOO//EH
lCoQuPfcY0sZ0gk0k/4Jg+1v8uzhLF/LlPvVJFXeL86ROMR0fh7jHWAUiQTNUyNtGS3kq9R2vbRD
SQqQ57qCPsSRGvIhng6TtZEdnvWKQa8webYBhVZnOPGI2OEBaCcDVMczb/4zFsEzvY6zRAou0nCb
4Dlz4ZT+nqcowEWXf8D4rqhDWk2Fi0DsA0l6FjRw4fz2B8+Bh+AuwSMNsXo25M3j/9e9mUEd5tBZ
lT0TXvGULRTeI5ljBq4H/hLW7QnJAjO/pFR87ataK05VyG581PnfIJt9LeJDPEwvrG9TtUFYnBy4
Ieoutj7X+Su+WJEL4M+XjKMl2Sm7JesucmgGpeNpgWhn6kv7b8rVIWiK3RREb3lnAKCspxbFr/bH
4AuVNjV9iuc8WNAgBAggKW6VRjDqnLjWFvjyjXchoUr1aOFK/RMp8+xIzCwYuuuK3JZkAO1SxC8H
h3vAm+RdloredtxNCgExvOzGUsBwH/gXf/lAWiM4L0XKdifGFPTfa76/PWwLdDgAP3hujZMD4rpH
fuQmXv/LUD87RUIyvM4VblNKl2mJiGjOhZKIxCHVoIeNqXikt2y+5CtHRiePvk6enf/R/T/S3Jdn
VE+PKtRGy9x9IWMicWjaGNQ4tvnN1kpABsG/2EimTQBfK/uuiP7za+BBcum/OqZkTT5oKYXDWfQU
UDw2m9vHH1UNQ+KNzIyPl0wP1wlvdpfOTKWPjLeLMk07TklKvtFG5SzxDhYBbqVkwEi0/lhlCh+K
jDGg1KxdOfMI1df0Nj9yNnXK/eG5hVG1SYQWgSEuuhAyrb0B9JLxCfDZW86j64tnM+BXc5+xWzwx
tr0UZfp6f7QZPYW8b+VcjKRJf8omiG/g+lY+QKNMWIumU6tVU3enJSAYFeRDrg67CwrP3SjydmVS
TsVS23Cl+mfyBIw9kUz73VuTz0E5woGpGtXST5Zn0pAb9RqCZf6qNEjpHDcKzX4tMU/3VVocmGi/
HHAmvMONUEOkBqTrKC9V3yvrQiUN6epc8IfypsiE/lZUg0ykOGhc1EPIfCG/6LQKYYpRbfGOQVPM
Fh/tY+6CM7TSq2/6jvcmRE/shnN/J4UGfcuDplUa+0pSkdg0tDBtk0f/+SRQBo/3r+AnohPrPXdd
GSNxRZmf2W7/MaM//U5iMwYR4+lutBeMbn+eS5To737Sk1VwTeDaHd/fb+5SVeJrJjMIKUuGWLO6
vSiv6dTpBfHt4x7XEwABWhokFAfWmi42+I5E35zf5yMVHnyPVsW41A6sln5p3L1xtXAi3dbIFGAx
BbZdzgQ5tWGC05/CnF2anopZbz5sJLwqncWnoMu9k9iOqHdRdmmFj2S+esZYpVyl2AA/XTttX6jF
eRKagJgv10qWjtJuDgtP8Qovkl6M2P5REPoMSxdTjSa5El5eymNmw+p1MUGuHJ55S8ccB023D2TO
rRgZqUo7oqkQ2tHWM+3VsiKUXZTKQJ99Rlg5EPWwTsdHOP5b6NWNfjdL2zM3JgzA8XeFG8wmSBn7
Tp/qwxt2NzQO++QX52byqUbCsT/HxvgIQqeZ2ijIlIvzxYskxxcnVwzsAYuIbR9Ldt6gYe/XJDbY
ks11tHmF0JvJg+iyp4fCUyoDzg+ivVrhjco4K3CD3goJYA5Ypmg8QdvVbH7YHdk4n3ZrPm7Rg+AZ
GilfiybTGJ41fbfbJxLEmJcxv/7NBf7ERNdMwJ0rQvBDSQIE/i0Dn9ra8fFXbxqlfcTnSKdm5qjs
jdwMhUkjGfqonji8NusiWYu2OQq0N2Re7kZ0i3abobDw2b+wvf04uMeLup+82dCaOd80CZGGXWO8
Qjwq2cKupVrUFezBF66ogMsmRPwMq1AkAstZyfSxFlwvB4EJmhgiP+uWhatkCL31ML3cqH/u6EDt
AlA4Se4jp3mbHZg6lXwoIbyhJo5hj7ogItx/ho/u5gRavHrnl0yfM1Kowe2E+qSGa5G42Z5TLu6k
/rnDVTxXhbjASWEPYpwUq6KE1fl2Haj9CDg4D2Dtj4jgy+gPAOEtb96/ck3EcpgcOsGA9ukmoOpE
9uos7VZYMX53eji9IlKvF9nzj9hHWhzgCeuudW82iGyNw2ikd4R/DC95CTzA14QS7Wlobe+7tQaJ
VaE9pjCyqytyAvczKuENxqnj19T4Vr3E3hY62tEKb0u93V5zRIe4uwqOpMIs//VX+hKkMVjBSB+p
eHgNlqM6OYhfVo1d/mV8IBT+84peGqgiTQqgKh8ETLXivwv9JBXD2hOGgArGvSPX/kwy698K+Tpn
619AiiFaWBncE2bW9acVyTRJezTk4REToeT587O0ZsDshNqECUj7I3ZSNYTOmSxm62F8FnEJQwLB
qEiCW/7XmOm93P1COnR/25c3jDmGoJ61gTpNH2JcLr2V4w+XuI/xbnsWvadUKDSudZg+v9htXzAM
zjJOU32JiUSoUxaVr5MGjl1hcFIG9m7IVnZciQIHIa5RlyTqHpekAOtSPbGOQHcQhk81m4a+4nNa
XTuf4fEjcOZpVRVPURCz7Vj8Th8kb0eL4363eIFX3K+Gew3Mh0uhcNE5LQLeFryw0a7eqLMk+y3f
TWsi3GqA4g755oh4k4PGbIAOE1B4EWBnPR+/cIn2ckwf1f9t5yACgaEnFabl3Xm3AgDr/ApzAZ4P
ijOqK3bldiOQlYZ4wVyC9tnGmxcwjsMO5FJRSlBapC66lWpb4BNvPFxkpBY+5gO6f4HemKMZmwYd
/GRloXuYvD9/FDKINaita8dGFLj7kCo5dKAcY+7QA2hBV5xio3sx4YApugt2IbKkuIyhNPfMhw6f
AGIXgYeuuCA99QvckZixTMzcquZ0FIpmGQ/G7M5fGk8ZzoJ/U7SLqRiN4V4zHNiwmSS8pORsKBjV
RJh5giybVmEXlXZLc+1PznchaKBdo2FTEZKDdAZV/xxMHOdFUkmlRcn/PABA9Y8qE/O6np6P+1tW
fVDnBZsV+s6I0HPZ/qhsKTV+VbQTmoZHDMghwsB85q8HGfp2X/SzBdRTirkUpP2ZICtMwgFmYOrT
iL1FsGqq8RXDvpWJtdgxzoe1T9vQ8x+gQElm7bs+MSwqQoYeopwhUSha4dNIBJ4Ww9cWfkVD/BdP
jh+s0YN6Wgw8CraxJH1YMVKBgTLHaL3R6pQwqduLkegfDxpfyhGS/jGjT2LUXLMHvwwSFHizP70/
vo6b4K69pMd7UpjPQ4aC9BzL/0O6tuylMhpbEJf4raLa3OX13BtqMvzcXCXw4b57g7IyL8LP7P5O
sqgikDSg05Y4YOFUeopY/aANY0ZXnjlkqXrgYwyuga9ZnB7zNjhcdGkljnKnCS2OC6IZXJieQGCL
1q3/dwKSZJY1/eOWcKbvi3DHT6W+ryytvoUNAgQKoxuwRkSzX5HgvUCD0d3f1gj7CI/qBrQ1VfIV
oZvr2br761XdgL0SR0y+qNTKSwmOQHgslaH3rsHAERoMWZ4Zr/i/B4oc4MvA/65fW9KsMOt4da3U
R2gtRK+sjRVgsbG+jG/zH4+bfOvSz32r1NFH9RlY4qKdVt3NW4MzZh7bjm042h7uXSjjFXP4HDg7
xRRv5GTXF0O6jZ6aLvAa/YKDrQySgk9rUtHjci0EzYZwTs9henuuHzIa16TDmku5rVc7mDMA2X6+
D/fuvmatbvXD8sLgHawlql4IwCdrBLvz3Mu5K5fbmgiY834YSx+pnrrKbhm943Wv279rxvbbpf8S
ewcdE7JXuqvIdpWK1zI6blxc4DSqOQRXIR88fjLAwlOxMdhHFo6uq/5e+NM+PX+9SHQ40B/Q+05c
ZUgAnYvhH4kjf+qRgxLhxjxkFNotTaozYUcRKCIOp5ATlN4rJSlYzqOawFxYXdMR4K9qN8/aC0sz
Ez5q0glTSxHOF12J3U1Umx69le8xc25LOMbGIJY/6WZwvK85PiFz21M3mMCddkRp0mkC2Id2ycDd
1cdCHruyyJLxGFkgVdw3wLvwSKbcVkyQs/5ofF3Vl99/r8wdfazL6oDvLzd9FrY7DBsl9V0fhUjv
Lii9JMkh+tRWx8JESI2ISRVmaf+ySMVAkC+RwuekRSSG6QcnOhLwhc9CBpB0ne93LaFIjQ2SRX4C
ZG3uQVxia5D0Waa5Mqs0FYQrc1+qV427ak0ml4VGkxR9Q+bMOEpY07as9QGeJ8rcvIaIE96nBsNJ
XN5JVmYshWftbjZzJHFSuQ84VM2eelEv6d6fdkGNULJf7vpNgVQssd+VKwSilqhCaLCRNJd2KO1v
Ui8bS9A5O0ft9/FcnadUE8c599VINueVXIaWrZQmXP2Cti5QkicOrKB6/1FulMWk6WLbwiTCT/nd
VUohg5oyoyUDxgQsZ93YTGeTEh17XWtROBMt11aGBJo/s6lBhmxleOg7SDwpOF6ZQFCkLmWDJKnz
8yzMpadBLA6TUlgSyJYdXAW36Gg3bbsar5oYeVxizPE/7ALjNIbtaAiBxj5lBmK/dKUHm6H8ouBP
CTei1ZrpcnwaZnoja8AJbA7aJwOg4bpt2ZMDrhtqE4TxfP+kQ83VgJWP2QSjUj3MRUam4pJNuhiy
MmNHEBnCFWnXfe24g4qaAu0t5RDWa1gF+FN2Wswidw4duJwguWt1YV93qVXO4T72lLr+ZaYCCRnZ
GVt3T0ApuLkdaW/Tvdnb5kFI6EVKTlbkyPHTX5cHy6ZkwB9UurQ36jJYz+GixvhbGiLeddEtPMAN
+vV/47mOVa3HuTi+jViTC4UILvqYC5pCMPQB8Z82pUhM2Vytq0m0yYGXulcFYNR8flGkDkPrXJDQ
In9htMHRM0112ZYoD5aUAkq8BfuOxP66/BsqrOhDBXOYxYJNmX3SGQaQBsisLuA65uZh+pUOoljR
uzOJCGGnz9v4OqGJNzuSw44AbdThEljORKspYFy464eAzhBL5oGDhzZaGi8qjWZ2xgFAkFi5C5fr
W+mut4Hlk+krGJE1FDkKsje4I7rxyT/BHzjIAdzw7W5CXQ/zNioQCc+AYGcIkIYFO+xt2VJAfp4Q
TaQnCsBUm341CxLFiurN1kpTSbNvg1nygK/WtuCYMocXh+xMmGvemCu+BQOmsfwzuOd/CTz7Qbv7
5lh8BCcppqwpAvBCypbSHOU+uc179mXYe59/P3EyKMsxGjl+Zy6mYj1iwInh1yxTl71NWkp3DSmX
9IrWVnlGJZZuGa6oymr1PMytOAoWyoyCykigVGqq/kyv4PmBELGlzSRwXXtPNY7GSL2+GOvQlbdE
MQIleYMBotTuI4uKTbUMnBy14HRHVMsVjfAAJC9hbFSPwijQEYiJJJkdu7NRfpVSRXJvO7yV16Kk
PovXFcpqhyIkXm9YoBHpvSSE6OGKmLVhjGahPh1TtKvCa4PIh1VF2bouNqHixInUQ8zYl1u0Ho52
lAg11p0W+G+2Phw+oqsh8ZUoLKAiTu+H2MDkB7cRAfaqZG6w4P1saqOJ+/ManIK07DkMInigRGVY
xe4yUIIe/vTMIwzO1SK33CLdgfqm89HrEPhb1m6YT82Gkqsj1cl/KdLHD8dJV5RX/oDPVqwSg/ip
2RPskjQCm5IPwDUuu7nHiYi+SPYx6n/qgDx9ybq4MINyl6ZB6ToLc/qHX2nTITOdYJtw+BDAFadR
qWEbJWLExiEEGc3sQOZ5Q7a6O0oJufOKJ210Ps1aj8BysYmUKI4kHqm7SjObJ+wG4siukMOn+uZT
o/ueEF3q11/kCrm1OgB/sNUI2dlPfrIRlnHGOCKJZZgB+gul6P229LiL316NoVnZ37+EZI4ED4fh
fpJBItCU0dzrfZBAV2So8+yYr83liiEvSM5pShwf7v+l9BAvkq46VhyrjC1kj1UhRvTsLds73nBn
zuTnvSJGdumiPIeF0Sq3Jziz4n0oTBeITpPQK6G0G4EGskn1xOmv9jMtIpKFmaEPTTI8H6VUvxFE
OyH5Zrg8cqWmFgQBFyizZ3gg3rEHyZEtKZRRk4na4Zfn4PsRgOXqZWookbKHbnW+TM9mUb9C48Vw
djRxz0davhW52sJ+3btyFdpmxbKOEcB/Iq+FUvbNYnzKLOkuRFkvHdQlx+/y3Y25Ka318mjjFuah
lcpSmV84FtFsK1ZBRs8Sa5rBK3izt/d/264T8+VOyFJUEaAV7+PtnL+WCg4ZLSNq+X1mOwFVtz3P
8uX6ormvxmu2Hd5MbFCkmczFy7Ze57mJIscmyfBNzesLeWcJSz6GlOgevm8FgYA3ul1B8MB1id+N
1cRJlk5lS1wisIZMtCq1fGzdMN3bpWW/BlxRtzepUaDqKJ+YLEAlvzGCUmGUc2CC8z96iD1JoTQ1
6LYPs87F+FpafGmDZdGpEZfoeTmdRCYqy9iTUAIv4x/eW8JkPNW3v1Uy32HhPYmNR7rwC2Uvei6U
42CKTPj+GAN5dttff2u6/hxSrLkMNGHmf4OBEfQPq+sDoE/7zuOzr95FzODcJ9DYrLz/XW3IcJdt
mq1chxErcnqgMjmTgiS3AuQPbp3RHzoeULzvPU5C4KV7iKF0jWcQ9Ljv1wrekzGNJwIaMdtFJmWF
Fwa4wENcn/jnMti6uNvD4HujZNFl/4pdCMp4BUBbXySZs8Vp3cmwmhEW5WwM3bJmWNGV5ucusqTZ
mVpISPLcq2XkIHL/5uXycBC0e+Ur/xYHAgQS+mSek1Hap7SKuB0x7fWI+K3K+xBJ/W3wA6ndvcop
TDU4kI88cI9t+M6mS98qy8wj6mjqc4RkFeRPwxmCEFt4Bmb6PlG0wpk2cti6Z5oZeg/HZSSu0XG2
DfD0ZT6YMzw5+X2c/tDCkW/cYd4uLlD2InTv3r0B3zVo67VHw7Tex3yXZuWFPws5krogB6OJSVRQ
a5jZvd/ctg3Ov9WojLtsUfh3kBAS9b7HmHha4MRN2Rb++mrksAWbVNQheeM68S+ZeVkGO89SIb64
Z8a7PYavhUdhnJOslr8Ab/ZGZZhsmmEzqtQ36LeeieyGIPaIDY+8oP4jCvDP/iR7tabpcKlKllV4
MA5mvK8IsganLU7eg0f0h6QqGvXz7AOoqID8hzt4unt6Bt/OYB9iPSoOLvuGfDyfuoOn0OPUbi//
eH2CovzmkJWx0RdYmHMTbwA18mxE/ghSLVh59/XABbaKIjmdW6kXIT26R/vhhdSfyo60mKf/eiv3
DFHz6bJi3AQNfMjhsCdP5XYT7mDNCb9Zj2SEDTKPudrwBpxR6dyhkgDE7M695rp7NVoxtn9PJRSG
tIhsbRMzSikE1/u/MjAiCzYJnHIalctx4rhdxt6Vzhg/2Mi9w0f7oovWNQGOzQY+B+FbJp1w9gzf
Pznla4BbwJz66lxtMywVVO6n/x6aRdNCc/MbDLJ8zB19CyL9/RAXM7wAti+nYUhMif5UE01AVmEl
Zy9ArFV+AjB7sgkXuNELu4K2U/OCfv74Z/4BeHZbZe+G3LYq4uyiEPhoe5Vm4M90ha8pX2hs4eZd
FdGOI5TAFunrAjLMaiGBIWPLP/txXy/tzaYJyBMxGgNbXtkLQxGlgrUvs2L6U5A6v8U/3164m8IB
fKQBY4yx9tdWC6/lAk2RW+VXWMGTN3HiQVEH66hVC1E5/I1m9Htt2ILRTvUMk9ppiIP2dvaOqWiP
wAOXBeQn66VtH+zEMdtTbbSMXANxi47kI3vMz5c7lc6EZudVmAdn1FORrBDHmAcFNxqqxn5FWkei
LqV17aooaj7zTFQfaKLuWuuEPXsWp0jVGMAKKuHWE3O8Vkrb1ghDuUWWoWlobkbM6VAs+9CANTe3
SGWMvqwZrf05uLbaUAOXRs2hBpFFF5UTBTrO996hVUDlNcasMxHrIgBWso7bwomDQqr6SsbofgwT
ORO/ap4hYComStEIiHkzvx+ZFR2tWX3uKPG8SET+lGSNlg3AxaE1Ql3YLE3SZe5ENNqVFFxhoMeM
w6uMSehdaLyj7R6Fhkc697lpb1rmbBs/aC4B46UCcWtD47UwmX56zaTnUWK4Sr7e8cS3rqBdTkuB
lnrikdW8eSXKdxJCB3napsbSODP6INz7TPm9bOB/6IqCWYP0Xi7+hBb5w1J/zyVmRgwthpyA2gLn
jPu3xb7FejXSUXdBOyIW1PAR2g7u55xENHYkQ0kQffC5uFceGQkGU3xUiYwmMxVq4Pv3voVZHRS/
jP//3CALLEf14IzAjdItb5yCrQId8q1gI5rnvgkqc+Yh6qxapv+8e0wKZwq9x2IcMzeNC0uoNP8k
7+txCdu+YPm9jM7tcffSrNf9gCYQ8ZXydCX7Jksl2lV6FyPvWJb4n4M8x58gBKiAW2Zqfx3CO28M
vFvaSfaGpAQmmE1n4lYlAtVwwQ0areLaahwgklOBN5FSLKtGlpnlZiIrUPtG53IeAjcqW7BzTwAs
4yARI/sbR65vfbKXSHoeYPMag0VTX4UuivPLFXkhV4zlVH+wIQ6xOsl41B/LAZ13Hz8464MJ3rwQ
IxfNZ6jmJEblBLDfY7NlnRu6/XavH10pYBZOaXdS+ngBQQFwC5thnhNb7Uri/qRciqKwUV+xUKf7
YYyQkHSw+u0E/XjqycK+EZ2gXNSgzrgJjqjH3hr4QipNcyAHvDplxwjgHHjXBzssfB+dRr8dHt5b
HeTadcjEcek2vrdJJSUw1XxkOoCIGRxU3CkGnsE35zW4IhZI4cwqlk2FnwlX+zWlK8jvr9LES95I
q8Nw59Q3nzwIazbGdDxQfUo=
`protect end_protected
|
--
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--
-- A simple test program for the Xilinx ZCU104605 development board that
-- makes the user GPIO LEDs flash for the binary sequence 0..7, with a
-- reset from the push button GPIO_PB_SW3 SW18 at a 1 second frequency.
library ieee;
use ieee.std_logic_1164.all;
package counter_package is
subtype count_type is natural range 0 to 15;
component mkModule1 is
port(signal CLK : in std_ulogic;
signal RST_N : in std_ulogic;
signal EN_count_value : in std_ulogic;
signal count_value : out count_type;
signal RDY_count_value : out std_ulogic);
end component mkModule1;
end package counter_package;
library ieee;
use ieee.std_logic_1164.all;
use work.counter_package.all;
entity counter4 is
port (signal CLK_125_P : in std_ulogic; -- 125MHz clock P at pin H11 LVDS
signal CLK_125_N : in std_ulogic; -- 125MHz clock N at pin G11 LVDS
signal GPIO_PB_SW3 : in std_ulogic; -- pin C3 LVCMOS33 connected to push-button GPIO_PB_SW3 SW18
signal GPIO_LED : out count_type -- LEDs at pins D5 (LSB), D6, A5, B5 (MSB) LVCMOS33
);
end entity counter4;
library unisim;
use unisim.vcomponents.all;
architecture behavioral of counter4 is
signal count : count_type;
signal clk125MHz, clk1Hz : std_ulogic := '0';
signal inv_rest : std_ulogic;
signal en : std_ulogic := '1';
signal inv_reset : std_ulogic;
begin
clock_buffer : ibufgds port map (o => clk125MHz, i => CLK_125_P, ib => CLK_125_N);
clock_divider : process is
variable divider_count : natural := 0;
begin
wait until clk125MHz'event and clk125MHz = '1';
if divider_count = 62500000 then
clk1Hz <= not clk1Hz;
divider_count := 0;
else
divider_count := divider_count + 1;
end if;
end process clock_divider;
inv_reset <= not GPIO_PB_SW3;
kami_counter : mkModule1 port map (CLK => clk1Hz,
RST_N => inv_reset,
EN_count_value => en,
count_value => count,
RDY_count_value => open);
GPIO_LED <= count;
end architecture behavioral;
|
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
y <= 4;
end case;
end process;
process is
begin
wait for 1 ns;
assert y = 4;
x <= 2;
wait for 1 ns;
assert y = 1;
x <= 10;
wait for 1 ns;
assert y = 3;
wait;
end process;
end architecture;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package clock_pkg is
constant Tpw : delay_length := 4 ns;
signal clock_phase1, clock_phase2 : std_ulogic;
end package clock_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package clock_pkg is
constant Tpw : delay_length := 4 ns;
signal clock_phase1, clock_phase2 : std_ulogic;
end package clock_pkg;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_08_fg_08_03.vhd,v 1.2 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library ieee; use ieee.std_logic_1164.all;
package clock_pkg is
constant Tpw : delay_length := 4 ns;
signal clock_phase1, clock_phase2 : std_ulogic;
end package clock_pkg;
|
-------------------------------------------------------------------------------
-- $Id: cross_clk_sync_fifo_0.vhd
-------------------------------------------------------------------------------
-- cross_clk_sync_fifo_0.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- *******************************************************************
-- ** (c) Copyright [2010] - [2012] Xilinx, Inc. All rights reserved.*
-- ** *
-- ** This file contains confidential and proprietary information *
-- ** of Xilinx, Inc. and is protected under U.S. and *
-- ** international copyright and other intellectual property *
-- ** laws. *
-- ** *
-- ** DISCLAIMER *
-- ** This disclaimer is not a license and does not grant any *
-- ** rights to the materials distributed herewith. Except as *
-- ** otherwise provided in a valid license issued to you by *
-- ** Xilinx, and to the maximum extent permitted by applicable *
-- ** law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND *
-- ** WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES *
-- ** AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING *
-- ** BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- *
-- ** INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and *
-- ** (2) Xilinx shall not be liable (whether in contract or tort, *
-- ** including negligence, or under any other theory of *
-- ** liability) for any loss or damage of any kind or nature *
-- ** related to, arising under or in connection with these *
-- ** materials, including for any direct, or any indirect, *
-- ** special, incidental, or consequential loss or damage *
-- ** (including loss of data, profits, goodwill, or any type of *
-- ** loss or damage suffered as a result of any action brought *
-- ** by a third party) even if such damage or loss was *
-- ** reasonably foreseeable or Xilinx had been advised of the *
-- ** possibility of the same. *
-- ** *
-- ** CRITICAL APPLICATIONS *
-- ** Xilinx products are not designed or intended to be fail- *
-- ** safe, or for use in any application requiring fail-safe *
-- ** performance, such as life-support or safety devices or *
-- ** systems, Class III medical devices, nuclear facilities, *
-- ** applications related to the deployment of airbags, or any *
-- ** other applications that could lead to death, personal *
-- ** injury, or severe property or environmental damage *
-- ** (individually and collectively, "Critical *
-- ** Applications"). Customer assumes the sole risk and *
-- ** liability of any use of Xilinx products in Critical *
-- ** Applications, subject only to applicable laws and *
-- ** regulations governing limitations on product liability. *
-- ** *
-- ** THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS *
-- ** PART OF THIS FILE AT ALL TIMES. *
-- *******************************************************************
--
-------------------------------------------------------------------------------
-- Filename: cross_clk_sync_fifo_0.vhd
-- Version: v3.1
-- Description: This is the CDC logic when FIFO = 0.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_quad_spi.vhd
-- |--Legacy_mode
-- |-- axi_lite_ipif.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--Enhanced_mode
-- |--axi_qspi_enhanced_mode.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- qspi_core_interface.vhd
-- |-- qspi_cntrl_reg.vhd
-- |-- qspi_status_slave_sel_reg.vhd
-- |-- qspi_occupancy_reg.vhd
-- |-- qspi_fifo_ifmodule.vhd
-- |-- qspi_mode_0_module.vhd
-- |-- qspi_receive_transmit_reg.vhd
-- |-- qspi_startup_block.vhd
-- |-- comp_defs.vhd -- (helper lib)
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- qspi_look_up_logic.vhd
-- |-- qspi_mode_control_logic.vhd
-- |-- interrupt_control.vhd
-- |-- soft_reset.vhd
-- |--XIP_mode
-- |-- axi_lite_ipif.vhd
-- |-- xip_cntrl_reg.vhd
-- |-- reset_sync_module.vhd
-- |-- xip_status_reg.vhd
-- |-- axi_qspi_xip_if.vhd
-- |-- qspi_addr_decoder.vhd
-- |-- async_fifo_fg.vhd -- (helper lib)
-- |-- comp_defs.vhd -- (helper lib)
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- History:
-- ~~~~~~
-- SK 19/01/11 -- created v1.00.a version
-- ^^^^^^
-- 1. Created first version of the core.
-- ~~~~~~
-- ~~~~~~
-- SK 12/16/12 -- v3.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.conv_std_logic_vector;
use ieee.std_logic_arith.all;
use ieee.std_logic_signed.all;
use ieee.std_logic_misc.all;
-- library unsigned is used for overloading of "=" which allows integer to
-- be compared to std_logic_vector
use ieee.std_logic_unsigned.all;
library proc_common_v4_0;
use proc_common_v4_0.proc_common_pkg.all;
use proc_common_v4_0.ipif_pkg.all;
use proc_common_v4_0.family.all;
use proc_common_v4_0.all;
use proc_common_v4_0.cdc_sync;
library axi_quad_spi_v3_1;
use axi_quad_spi_v3_1.all;
library unisim;
use unisim.vcomponents.FDRE;
use unisim.vcomponents.FDR;
-------------------------------------------------------------------------------
entity cross_clk_sync_fifo_0 is
generic (
C_NUM_TRANSFER_BITS : integer;
C_NUM_SS_BITS : integer--;
--C_AXI_SPI_CLK_EQ_DIFF : integer
);
port (
EXT_SPI_CLK : in std_logic;
Bus2IP_Clk : in std_logic;
Soft_Reset_op : in std_logic;
Rst_from_axi_cdc_to_spi : in std_logic;
----------------------------
Tx_FIFO_Empty_cdc_from_axi : in std_logic;
Tx_FIFO_Empty_cdc_to_spi : out std_logic;
----------------------------------------------------------
Tx_FIFO_Empty_SPISR_cdc_from_spi : in std_logic;
Tx_FIFO_Empty_SPISR_cdc_to_axi : out std_logic;
----------------------------------------------------------
spisel_d1_reg_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_d1_reg_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spisel_pulse_cdc_from_spi : in std_logic; -- = spisel_pulse_cdc_from_spi_clk , -- in
spisel_pulse_cdc_to_axi : out std_logic; -- = spisel_pulse_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
spiXfer_done_cdc_from_spi : in std_logic; -- = spiXfer_done_cdc_from_spi_clk, -- in
spiXfer_done_cdc_to_axi : out std_logic; -- = spiXfer_done_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
modf_strobe_cdc_from_spi : in std_logic; -- = modf_strobe_cdc_from_spi_clk, -- in
modf_strobe_cdc_to_axi : out std_logic; -- = modf_strobe_cdc_to_axi_clk , -- out
--------------------------:-------------------------------
Slave_MODF_strobe_cdc_from_spi : in std_logic; -- = slave_MODF_strobe_cdc_from_spi_clk,-- in
Slave_MODF_strobe_cdc_to_axi : out std_logic; -- = slave_MODF_strobe_cdc_to_axi_clk ,-- out
--------------------------:-------------------------------
receive_Data_cdc_from_spi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_Data_cdc_from_spi_clk, -- in
receive_Data_cdc_to_axi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = receive_data_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
drr_Overrun_int_cdc_from_spi : in std_logic;
drr_Overrun_int_cdc_to_axi : out std_logic;
--------------------------:-------------------------------
dtr_underrun_cdc_from_spi : in std_logic; -- = dtr_underrun_cdc_from_spi_clk, -- in
dtr_underrun_cdc_to_axi : out std_logic; -- = dtr_underrun_cdc_to_axi_clk, -- out
--------------------------:-------------------------------
transmit_Data_cdc_from_axi : in std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_from_axi_clk, -- in
transmit_Data_cdc_to_spi : out std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1)); -- = transmit_Data_cdc_to_spi_clk -- out
----------------------------
SPICR_0_LOOP_cdc_from_axi : in std_logic;
SPICR_0_LOOP_cdc_to_spi : out std_logic;
----------------------------
SPICR_1_SPE_cdc_from_axi : in std_logic;
SPICR_1_SPE_cdc_to_spi : out std_logic;
----------------------------
SPICR_2_MST_N_SLV_cdc_from_axi : in std_logic;
SPICR_2_MST_N_SLV_cdc_to_spi : out std_logic;
----------------------------
SPICR_3_CPOL_cdc_from_axi : in std_logic;
SPICR_3_CPOL_cdc_to_spi : out std_logic;
----------------------------
SPICR_4_CPHA_cdc_from_axi : in std_logic;
SPICR_4_CPHA_cdc_to_spi : out std_logic;
----------------------------
SPICR_5_TXFIFO_cdc_from_axi : in std_logic;
SPICR_5_TXFIFO_cdc_to_spi : out std_logic;
----------------------------
SPICR_6_RXFIFO_RST_cdc_from_axi: in std_logic;
SPICR_6_RXFIFO_RST_cdc_to_spi : out std_logic;
----------------------------
SPICR_7_SS_cdc_from_axi : in std_logic;
SPICR_7_SS_cdc_to_spi : out std_logic;
----------------------------
SPICR_8_TR_INHIBIT_cdc_from_axi: in std_logic;
SPICR_8_TR_INHIBIT_cdc_to_spi : out std_logic;
----------------------------
SPICR_9_LSB_cdc_from_axi : in std_logic;
SPICR_9_LSB_cdc_to_spi : out std_logic;
----------------------------
SPICR_bits_7_8_cdc_from_axi : in std_logic_vector(1 downto 0); -- in std_logic_vector
SPICR_bits_7_8_cdc_to_spi : out std_logic_vector(1 downto 0);
----------------------------
SR_3_modf_cdc_from_axi : in std_logic;
SR_3_modf_cdc_to_spi : out std_logic;
----------------------------
SPISSR_cdc_from_axi : in std_logic_vector(0 to (C_NUM_SS_BITS-1));
SPISSR_cdc_to_spi : out std_logic_vector(0 to (C_NUM_SS_BITS-1))
----------------------------
);
end entity cross_clk_sync_fifo_0;
architecture imp of cross_clk_sync_fifo_0 is
--------------------------------------------
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- signal declaration
signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
signal spiXfer_done_cdc_from_spi_d1 : std_logic;
signal spiXfer_done_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d1 : std_logic;
signal modf_strobe_cdc_from_spi_d2 : std_logic;
signal modf_strobe_cdc_from_spi_d3 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal dtr_underrun_cdc_from_spi_d1 : std_logic;
signal dtr_underrun_cdc_from_spi_d2 : std_logic;
signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
signal spisel_pulse_cdc_from_spi_d1 : std_logic;
signal spisel_pulse_cdc_from_spi_d2 : std_logic;
signal spisel_pulse_cdc_from_spi_d3 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_d4 : std_logic;
signal SR_3_modf_cdc_from_axi_d1 : std_logic;
signal SR_3_modf_cdc_from_axi_d2 : std_logic;
signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
signal spiXfer_done_d1 : std_logic;
signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- signal declaration
-- signal spisel_d1_reg_cdc_from_spi_d1 : std_logic;
-- signal spisel_d1_reg_cdc_from_spi_d2 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d1 : std_logic;
-- signal spiXfer_done_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d1 : std_logic;
-- signal modf_strobe_cdc_from_spi_d2 : std_logic;
-- signal modf_strobe_cdc_from_spi_d3 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d1 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_d3 : std_logic;
-- signal receive_Data_cdc_from_spi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal receive_Data_cdc_from_spi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal dtr_underrun_cdc_from_spi_d1 : std_logic;
-- signal dtr_underrun_cdc_from_spi_d2 : std_logic;
-- signal transmit_Data_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal transmit_Data_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_TRANSFER_BITS-1));
-- signal spisel_pulse_cdc_from_spi_d1 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d2 : std_logic;
-- signal spisel_pulse_cdc_from_spi_d3 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d1 : std_logic;
-- signal SPICR_0_LOOP_cdc_from_axi_d2 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d1 : std_logic;
-- signal SPICR_1_SPE_cdc_from_axi_d2 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d1 : std_logic;
-- signal SPICR_2_MST_N_SLV_cdc_from_axi_d2 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d1 : std_logic;
-- signal SPICR_3_CPOL_cdc_from_axi_d2 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d1 : std_logic;
-- signal SPICR_4_CPHA_cdc_from_axi_d2 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d1 : std_logic;
-- signal SPICR_5_TXFIFO_cdc_from_axi_d2 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d1 : std_logic;
-- signal SPICR_7_SS_cdc_from_axi_d2 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d1 : std_logic;
-- signal SPICR_8_TR_INHIBIT_cdc_from_axi_d2 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d1 : std_logic;
-- signal SPICR_9_LSB_cdc_from_axi_d2 : std_logic;
-- signal SPICR_bits_7_8_cdc_from_axi_d1 : std_logic_vector(1 downto 0);
-- signal SPICR_bits_7_8_cdc_from_axi_d2 : std_logic_vector(1 downto 0);
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d1 : std_logic;
-- signal SPICR_6_RXFIFO_RST_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d1 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d3 : std_logic;
-- signal Tx_FIFO_Empty_SPISR_cdc_from_spi_d4 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d1 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d2 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_d3 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d1 : std_logic;
-- signal SR_3_modf_cdc_from_axi_d2 : std_logic;
-- signal SPISSR_cdc_from_axi_d1 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal SPISSR_cdc_from_axi_d2 : std_logic_vector(0 to (C_NUM_SS_BITS-1));
-- signal spiXfer_done_cdc_from_spi_int_2 : std_logic;
-- signal spiXfer_done_d1 : std_logic;
-- signal spiXfer_done_d2, spiXfer_done_d3 : std_logic;
-- signal spisel_pulse_cdc_from_spi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_int_2 : std_logic;
-- signal Tx_FIFO_Empty_cdc_from_axi_d3 : std_logic;
-- signal drr_Overrun_int_cdc_from_spi_int_2 : std_logic;
-- signal Slave_MODF_strobe_cdc_from_spi_int_2 : std_logic;
-- signal modf_strobe_cdc_from_spi_int_2 : std_logic;
-- attribute ASYNC_REG : string;
-- attribute ASYNC_REG of SPISEL_D1_REG_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1 : label is "TRUE";
-- attribute ASYNC_REG of SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: label is "TRUE";
-- attribute ASYNC_REG of MODF_STROBE_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_9_LSB_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_8_TR_INHIBIT_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_7_SS_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_6_RXFIFO_RST_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_5_TXFIFO_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_4_CPHA_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_3_CPOL_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_2_MST_N_SLV_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_1_SPE_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SPICR_0_LOOP_AX2S_1 : label is "TRUE";
-- attribute ASYNC_REG of SR_3_MODF_AX2S_1 : label is "TRUE";
constant LOGIC_CHANGE : integer range 0 to 1 := 1;
constant MTBF_STAGES_AXI2S : integer range 0 to 6 := 3 ;
constant MTBF_STAGES_S2AXI : integer range 0 to 6 := 4 ;
-----
begin
-----
-- SPI_AXI_EQUAL_GEN: AXI and SPI domain clocks are same
---------------------
--SPI_AXI_EQUAL_GEN: if C_AXI_SPI_CLK_EQ_DIFF = 0 generate
-----
--begin
-----
LOGIC_GENERATION_FDR : if (LOGIC_CHANGE =0) generate
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI: process(Bus2IP_Clk) is
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
if(Soft_Reset_op = '1')then
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= '1';
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= '1';
else
Tx_FIFO_Empty_SPISR_cdc_from_spi_d1 <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
Tx_FIFO_Empty_SPISR_cdc_from_spi_d2 <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d1;
end if;
end if;
end process TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI;
-----------------------------------------
Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_from_spi_d2;
-------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_1: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_int_2,
R => Rst_from_axi_cdc_to_spi
);
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_3: component FDR
generic map(INIT => '1'
)port map (
Q => Tx_FIFO_Empty_cdc_from_axi_d3,
C => EXT_SPI_CLK,
D => Tx_FIFO_Empty_cdc_from_axi_d2,
R => Rst_from_axi_cdc_to_spi
);
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
-------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi,
R => Soft_Reset_op
);
SPISEL_D1_REG_SYNC_SPI_2_AXI_2: component FDR
port map (
Q => spisel_d1_reg_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_d1_reg_cdc_from_spi_d1,
R => Soft_Reset_op
);
spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_from_spi_d2;
SPISEL_PULSE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1;
SPISEL_PULSE_SPI_2_AXI_1: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_2: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d1,
R => Soft_Reset_op
);
SPISEL_PULSE_SPI_2_AXI_3: component FDR
port map (
Q => spisel_pulse_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => spisel_pulse_cdc_from_spi_d2,
R => Soft_Reset_op
);
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
---------------------------------------------
SPI_XFER_DONE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d1,
C => Bus2IP_Clk,
D => spiXfer_done_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d2,
C => Bus2IP_Clk,
D => spiXfer_done_d1,
R => Soft_Reset_op
);
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => spiXfer_done_d3,
C => Bus2IP_Clk,
D => spiXfer_done_d2,
R => Soft_Reset_op
);
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => modf_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => modf_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
---------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_int_2,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d1,
R => Soft_Reset_op
);
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => Slave_MODF_strobe_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => Slave_MODF_strobe_cdc_from_spi_d2,
R => Soft_Reset_op
);
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
---------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P: process(Bus2IP_Clk) is
-------------------------
begin
-----
if(Bus2IP_Clk'event and Bus2IP_Clk = '1')then
receive_Data_cdc_from_spi_d1 <= receive_Data_cdc_from_spi;
receive_Data_cdc_from_spi_d2 <= receive_Data_cdc_from_spi_d1;
end if;
end process RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P;
-------------------------------------------
receive_Data_cdc_to_axi <= receive_Data_cdc_from_spi_d2;
-----------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d2 xor drr_Overrun_int_cdc_from_spi_d3; --spiXfer_done_cdc_from_spi_d2;
-----------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi,
R => Soft_Reset_op
);
DTR_UNDERRUN_SYNC_SPI_2_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => dtr_underrun_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => dtr_underrun_cdc_from_spi_d1,
R => Soft_Reset_op
);
dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_from_spi_d2;
-----------------------------------------------
TR_DATA_SYNC_AX2SP_GEN: for i in 0 to (C_NUM_TRANSFER_BITS-1) generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of TR_DATA_SYNC_AX2SP_1: label is "TRUE";
-----
begin
-----
TR_DATA_SYNC_AX2SP_1: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
TR_DATA_SYNC_AX2SP_2: component FDR
generic map(INIT => '0'
)port map (
Q => transmit_Data_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => transmit_Data_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate TR_DATA_SYNC_AX2SP_GEN;
transmit_Data_cdc_to_spi <= transmit_Data_cdc_from_axi_d2;
-----------------------------------------------
SPICR_0_LOOP_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_0_LOOP_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_0_LOOP_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_from_axi_d2;
-----------------------------------------------
SPICR_1_SPE_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_1_SPE_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_1_SPE_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_from_axi_d2;
---------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_2_MST_N_SLV_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_2_MST_N_SLV_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_from_axi_d2;
---------------------------------------------------------
SPICR_3_CPOL_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_3_CPOL_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_3_CPOL_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_from_axi_d2;
-----------------------------------------------
SPICR_4_CPHA_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_4_CPHA_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_4_CPHA_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_from_axi_d2;
-----------------------------------------------
SPICR_5_TXFIFO_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_5_TXFIFO_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_5_TXFIFO_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_from_axi_d2;
---------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_6_RXFIFO_RST_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_6_RXFIFO_RST_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_7_SS_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_7_SS_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_7_SS_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_from_axi_d2;
-------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_AX2S_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPICR_8_TR_INHIBIT_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_8_TR_INHIBIT_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_from_axi_d2;
-----------------------------------------------------------
SPICR_9_LSB_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_9_LSB_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SPICR_9_LSB_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_from_axi_d2;
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1 : label is "TRUE";
begin
-----
SPICR_BITS_7_8_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPICR_BITS_7_8_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SPICR_bits_7_8_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPICR_bits_7_8_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPICR_BITS_7_8_SYNC_GEN;
-------------------------------------
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
---------------------------------------------------
SR_3_MODF_AX2S_1: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d1,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi,
R => Rst_from_axi_cdc_to_spi
);
SR_3_MODF_AX2S_2: component FDR
generic map(INIT => '0'
)port map (
Q => SR_3_modf_cdc_from_axi_d2,
C => EXT_SPI_CLK,
D => SR_3_modf_cdc_from_axi_d1,
R => Rst_from_axi_cdc_to_spi
);
SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_from_axi_d2;
-----------------------------------------
SPISSR_SYNC_GEN: for i in 0 to C_NUM_SS_BITS-1 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPISSR_AX2S_1 : label is "TRUE";
-----
begin
-----
SPISSR_AX2S_1: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d1(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi(i),
R => Rst_from_axi_cdc_to_spi
);
SPISSR_SYNC_AXI_2_SPI_2: component FDR
generic map(INIT => '1'
)port map (
Q => SPISSR_cdc_from_axi_d2(i),
C => EXT_SPI_CLK,
D => SPISSR_cdc_from_axi_d1(i),
R => Rst_from_axi_cdc_to_spi
);
end generate SPISSR_SYNC_GEN;
SPISSR_cdc_to_spi <= SPISSR_cdc_from_axi_d2;
-----------------------------------
end generate LOGIC_GENERATION_FDR ;
--============================================================================================================
LOGIC_GENERATION_CDC : if (LOGIC_CHANGE =1) generate
--============================================================================================================
-- Tx_FIFO_Empty_cdc_from_axi <= Tx_FIFO_Empty_cdc_from_axi;
-- Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_cdc_to_spi;
-- Tx_FIFO_Empty_SPISR_cdc_from_spi <= Tx_FIFO_Empty_SPISR_cdc_from_spi;
-- Tx_FIFO_Empty_SPISR_cdc_to_axi <= Tx_FIFO_Empty_SPISR_cdc_cdc_to_axi;
-- spisel_d1_reg_cdc_from_spi <= spisel_d1_reg_cdc_from_spi;
-- spisel_d1_reg_cdc_to_axi <= spisel_d1_reg_cdc_cdc_to_axi;
-- spisel_pulse_cdc_from_spi <= spisel_pulse_cdc_from_spi;
-- spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_cdc_to_axi;
-- spiXfer_done_cdc_from_spi <= spiXfer_done_cdc_from_spi;
-- spiXfer_done_cdc_to_axi <= spiXfer_done_cdc_cdc_to_axi;
-- modf_strobe_cdc_from_spi <= modf_strobe_cdc_from_spi;
-- modf_strobe_cdc_to_axi <= modf_strobe_cdc_cdc_to_axi;
-- Slave_MODF_strobe_cdc_from_spi <= Slave_MODF_strobe_cdc_from_spi;
-- Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_cdc_to_axi;
-- receive_Data_cdc_from_spi <= receive_Data_cdc_from_spi;
-- receive_Data_cdc_to_axi <= receive_Data_cdc_cdc_to_axi;
-- drr_Overrun_int_cdc_from_spi <= drr_Overrun_int_cdc_from_spi;
-- drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_cdc_to_axi;
-- dtr_underrun_cdc_from_spi <= dtr_underrun_cdc_from_spi;
-- dtr_underrun_cdc_to_axi <= dtr_underrun_cdc_cdc_to_axi;
-- transmit_Data_cdc_from_axi <= transmit_Data_cdc_from_axi;
-- transmit_Data_cdc_to_spi <= transmit_Data_cdc_cdc_to_spi;
-- SPICR_0_LOOP_cdc_from_axi <= SPICR_0_LOOP_cdc_from_axi;
-- SPICR_0_LOOP_cdc_to_spi <= SPICR_0_LOOP_cdc_cdc_to_spi;
-- SPICR_1_SPE_cdc_from_axi <= SPICR_1_SPE_cdc_from_axi;
-- SPICR_1_SPE_cdc_to_spi <= SPICR_1_SPE_cdc_cdc_to_spi;
-- SPICR_2_MST_N_SLV_cdc_from_axi <= SPICR_2_MST_N_SLV_cdc_from_axi;
-- SPICR_2_MST_N_SLV_cdc_to_spi <= SPICR_2_MST_N_SLV_cdc_cdc_to_spi;
-- SPICR_3_CPOL_cdc_from_axi <= SPICR_3_CPOL_cdc_from_axi;
-- SPICR_3_CPOL_cdc_to_spi <= SPICR_3_CPOL_cdc_cdc_to_spi;
-- SPICR_4_CPHA_cdc_from_axi <= SPICR_4_CPHA_cdc_from_axi;
-- SPICR_4_CPHA_cdc_to_spi <= SPICR_4_CPHA_cdc_cdc_to_spi;
-- SPICR_5_TXFIFO_cdc_from_axi <= SPICR_5_TXFIFO_cdc_from_axi;
-- SPICR_5_TXFIFO_cdc_to_spi <= SPICR_5_TXFIFO_cdc_cdc_to_spi;
-- SPICR_6_RXFIFO_RST_cdc_from_axi <= SPICR_6_RXFIFO_RST_cdc_from_axi;
-- SPICR_6_RXFIFO_RST_cdc_to_spi <= SPICR_6_RXFIFO_RST_cdc_cdc_to_spi;
-- SPICR_7_SS_cdc_from_axi <= SPICR_7_SS_cdc_from_axi;
-- SPICR_7_SS_cdc_to_spi <= SPICR_7_SS_cdc_cdc_to_spi;
-- SPICR_8_TR_INHIBIT_cdc_from_axi <= SPICR_8_TR_INHIBIT_cdc_from_axi;
-- SPICR_8_TR_INHIBIT_cdc_to_spi <= SPICR_8_TR_INHIBIT_cdc_cdc_to_spi;
-- SPICR_9_LSB_cdc_from_axi <= SPICR_9_LSB_cdc_from_axi;
-- SPICR_9_LSB_cdc_to_spi <= SPICR_9_LSB_cdc_cdc_to_spi;
-- SPICR_bits_7_8_cdc_from_axi <= SPICR_bits_7_8_cdc_from_axi;
-- SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_cdc_to_spi;
-- SR_3_modf_cdc_from_axi <= SR_3_modf_cdc_from_axi;
-- SR_3_modf_cdc_to_spi <= SR_3_modf_cdc_cdc_to_spi;
-- SPISSR_cdc_from_axi <= SPISSR_cdc_from_axi;
-- SPISSR_cdc_to_spi <= SPISSR_cdc_cdc_to_spi;
--============================================================================================================
-- all the signals pass through FF with reset before CDC_SYNC module to initialise the value of the signal
-- at its reset state. As many signals coming from bram have initial value of XX.
TX_FIFO_EMPTY_FOR_SPISR_SYNC_SPI_2_AXI_CDC : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Tx_FIFO_Empty_SPISR_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0') ,
scndry_resetn => Soft_Reset_op ,
scndry_out => Tx_FIFO_Empty_SPISR_cdc_to_axi
);
----------------------------------------------------------------------------------------------------------
TX_FIFO_EMPTY_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Tx_FIFO_Empty_cdc_from_axi_int_2 <= '1';
else
Tx_FIFO_Empty_cdc_from_axi_int_2 <= Tx_FIFO_Empty_cdc_from_axi xor
Tx_FIFO_Empty_cdc_from_axi_int_2;
end if;
end if;
end process TX_FIFO_EMPTY_STRETCH_1;
TX_FIFO_EMPTY_SYNC_AXI_2_SPI_CDC : entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1, -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => Tx_FIFO_Empty_cdc_from_axi_int_2,--Tx_FIFO_Empty_cdc_from_axi_d1 ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => Tx_FIFO_Empty_cdc_from_axi_d2--Tx_FIFO_Empty_cdc_to_spi
);
TX_FIFO_EMPTY_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
Tx_FIFO_Empty_cdc_from_axi_d3 <= Tx_FIFO_Empty_cdc_from_axi_d2;
end if;
end process TX_FIFO_EMPTY_STRETCH_1_CDC;
Tx_FIFO_Empty_cdc_to_spi <= Tx_FIFO_Empty_cdc_from_axi_d2 xor Tx_FIFO_Empty_cdc_from_axi_d3;
----------------------------------------------------------------------------------------------------------
SPISEL_D1_REG_SYNC_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_d1_reg_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_d1_reg_cdc_to_axi
);
-----------------------------------------------------------------------------------------------------------
SPISEL_PULSE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spisel_pulse_cdc_from_spi_int_2 <= '0';
--spisel_pulse_cdc_from_spi_d1 <= '0';
else
spisel_pulse_cdc_from_spi_int_2 <= spisel_pulse_cdc_from_spi xor
spisel_pulse_cdc_from_spi_int_2;
--spisel_pulse_cdc_from_spi_d1 <= spisel_pulse_cdc_from_spi_int_2;
end if;
end if;
end process SPISEL_PULSE_STRETCH_1_CDC;
SPISEL_PULSE_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spisel_pulse_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spisel_pulse_cdc_from_spi_d2
);
SPISEL_PULSE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk = '1') then
spisel_pulse_cdc_from_spi_d3 <= spisel_pulse_cdc_from_spi_d2;
end if;
end process SPISEL_PULSE_STRETCH_1;
spisel_pulse_cdc_to_axi <= spisel_pulse_cdc_from_spi_d2 xor spisel_pulse_cdc_from_spi_d3;
--------------------------------------------------------------------------------------------------------------
SPI_XFER_DONE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
spiXfer_done_cdc_from_spi_int_2 <= '0';
-- spiXfer_done_d2 <= '0';
else
spiXfer_done_cdc_from_spi_int_2 <= spiXfer_done_cdc_from_spi xor
spiXfer_done_cdc_from_spi_int_2;
-- spiXfer_done_d2 <= spiXfer_done_cdc_from_spi_int_2;
end if;
end if;
end process SPI_XFER_DONE_STRETCH_1_CDC;
SYNC_SPIXFER_DONE_SYNC_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 ,-- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => spiXfer_done_cdc_from_spi_int_2,--spiXfer_done_d2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => spiXfer_done_d2--spiXfer_done_cdc_to_axi
);
SPI_XFER_DONE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
spiXfer_done_d3 <= spiXfer_done_d2 ;
end if;
end process SPI_XFER_DONE_STRETCH_1;
spiXfer_done_cdc_to_axi <= spiXfer_done_d2 xor spiXfer_done_d3;
--------------------------------------------------------------------------------------------------------------
MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
modf_strobe_cdc_from_spi_int_2 <= '0';
--modf_strobe_cdc_from_spi_d1 <= '0';
else
modf_strobe_cdc_from_spi_int_2 <= modf_strobe_cdc_from_spi xor
modf_strobe_cdc_from_spi_int_2;
-- modf_strobe_cdc_from_spi_d1 <= modf_strobe_cdc_from_spi_int_2;
end if;
end if;
end process MODF_STROBE_STRETCH_1_CDC;
MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => modf_strobe_cdc_from_spi_int_2,--modf_strobe_cdc_from_spi_d1 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => modf_strobe_cdc_from_spi_d2--modf_strobe_cdc_to_axi
);
MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
modf_strobe_cdc_from_spi_d3 <= modf_strobe_cdc_from_spi_d2 ;
end if;
end process MODF_STROBE_STRETCH_1;
modf_strobe_cdc_to_axi <= modf_strobe_cdc_from_spi_d2 xor modf_strobe_cdc_from_spi_d3;
----------------------------------------------------------------------------------------------------------------
SLAVE_MODF_STROBE_STRETCH_1_CDC: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
Slave_MODF_strobe_cdc_from_spi_int_2 <= '0';
-- Slave_MODF_strobe_cdc_from_spi_d1 <= '0';
else
Slave_MODF_strobe_cdc_from_spi_int_2 <= Slave_MODF_strobe_cdc_from_spi xor
Slave_MODF_strobe_cdc_from_spi_int_2;
-- Slave_MODF_strobe_cdc_from_spi_d1 <= Slave_MODF_strobe_cdc_from_spi_int_2;
end if;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1_CDC;
SLAVE_MODF_STROBE_SYNC_SPI_cdc_to_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 2 is ack based level sync
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => Slave_MODF_strobe_cdc_from_spi_int_2 ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => Slave_MODF_strobe_cdc_from_spi_d2
);
SLAVE_MODF_STROBE_STRETCH_1: process(Bus2IP_Clk)is
begin
if(Bus2IP_Clk'event and Bus2IP_Clk= '1') then
Slave_MODF_strobe_cdc_from_spi_d3 <= Slave_MODF_strobe_cdc_from_spi_d2 ;
end if;
end process SLAVE_MODF_STROBE_STRETCH_1;
Slave_MODF_strobe_cdc_to_axi <= Slave_MODF_strobe_cdc_from_spi_d2 xor
Slave_MODF_strobe_cdc_from_spi_d3;
-----------------------------------------------------------------------------------------------------
RECEIVE_DATA_SYNC_SPI_cdc_to_AXI_P_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK,
prmry_resetn => Rst_from_axi_cdc_to_spi,
prmry_vect_in => receive_Data_cdc_from_spi,
scndry_aclk => Bus2IP_Clk,
prmry_in => '0',
scndry_resetn => Soft_Reset_op,
scndry_vect_out => receive_Data_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
DRR_OVERRUN_STRETCH_1: process(EXT_SPI_CLK)is
begin
if(EXT_SPI_CLK'event and EXT_SPI_CLK= '1') then
if(Rst_from_axi_cdc_to_spi = '1') then
drr_Overrun_int_cdc_from_spi_int_2 <= '0';
else
drr_Overrun_int_cdc_from_spi_int_2 <= drr_Overrun_int_cdc_from_spi xor
drr_Overrun_int_cdc_from_spi_int_2;
end if;
end if;
end process DRR_OVERRUN_STRETCH_1;
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_1: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d1,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_int_2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_2: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d2,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d1,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_3: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d3,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d2,
R => Soft_Reset_op
);
DRR_OVERRUN_SYNC_SPI_cdc_to_AXI_4: component FDR
generic map(INIT => '0'
)port map (
Q => drr_Overrun_int_cdc_from_spi_d4,
C => Bus2IP_Clk,
D => drr_Overrun_int_cdc_from_spi_d3,
R => Soft_Reset_op
);
drr_Overrun_int_cdc_to_axi <= drr_Overrun_int_cdc_from_spi_d4 xor drr_Overrun_int_cdc_from_spi_d3;
-------------------------------------------------------------------------------------------------------
DTR_UNDERRUN_SYNC_SPI_2_AXI_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 ,-- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_S2AXI
)
port map (
prmry_aclk => EXT_SPI_CLK ,
prmry_resetn => Rst_from_axi_cdc_to_spi ,
prmry_in => dtr_underrun_cdc_from_spi ,
scndry_aclk => Bus2IP_Clk ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Soft_Reset_op ,
scndry_out => dtr_underrun_cdc_to_axi
);
-------------------------------------------------------------------------------------------------------
SPICR_0_LOOP_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_0_LOOP_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_0_LOOP_cdc_to_spi
);
------------------------------------------------------------------------------------------------------
SPICR_1_SPE_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_1_SPE_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_1_SPE_cdc_to_spi
);
----------------------------------------------------------------------------------------------------
SPICR_2_MST_N_SLV_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_2_MST_N_SLV_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_2_MST_N_SLV_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_3_CPOL_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_3_CPOL_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_3_CPOL_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_4_CPHA_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_4_CPHA_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_4_CPHA_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_5_TXFIFO_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_5_TXFIFO_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_5_TXFIFO_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_6_RXFIFO_RST_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_6_RXFIFO_RST_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_6_RXFIFO_RST_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_7_SS_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_7_SS_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_7_SS_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_8_TR_INHIBIT_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_8_TR_INHIBIT_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_8_TR_INHIBIT_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SPICR_9_LSB_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SPICR_9_LSB_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SPICR_9_LSB_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
TR_DATA_SYNC_AX2SP_GEN_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_TRANSFER_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => transmit_Data_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => transmit_Data_cdc_to_spi
);
--------------------------------------------------------------------------------------------------
SR_3_MODF_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk ,
prmry_resetn => Soft_Reset_op ,
prmry_in => SR_3_modf_cdc_from_axi ,
scndry_aclk => EXT_SPI_CLK ,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi ,
scndry_out => SR_3_modf_cdc_to_spi
);
-----------------------------------------------------------------------------------------------------
SPISSR_SYNC_GEN_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 0 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => C_NUM_SS_BITS ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_vect_in => SPISSR_cdc_from_axi,
scndry_aclk => EXT_SPI_CLK,
prmry_in => '0' ,
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_vect_out => SPISSR_cdc_to_spi
);
---------------------------------------------
SPICR_BITS_7_8_SYNC_GEN_CDC: for i in 1 downto 0 generate
attribute ASYNC_REG : string;
attribute ASYNC_REG of SPICR_BITS_7_8_AX2S_1_CDC : label is "TRUE";
begin
SPICR_BITS_7_8_AX2S_1_CDC: entity proc_common_v4_0.cdc_sync
generic map (
C_CDC_TYPE => 1 , -- 1 is level synch
C_RESET_STATE => 0 , -- no reset to be used in synchronisers
C_SINGLE_BIT => 1 ,
C_FLOP_INPUT => 0 ,
C_VECTOR_WIDTH => 0 ,
C_MTBF_STAGES => MTBF_STAGES_AXI2S
)
port map (
prmry_aclk => Bus2IP_Clk,
prmry_resetn => Soft_Reset_op,
prmry_in => SPICR_bits_7_8_cdc_from_axi(i),
scndry_aclk => EXT_SPI_CLK,
prmry_vect_in => (others => '0' ),
scndry_resetn => Rst_from_axi_cdc_to_spi,
scndry_out => SPICR_bits_7_8_cdc_from_axi_d2(i)
);
-----------------------------------------
end generate SPICR_BITS_7_8_SYNC_GEN_CDC;
SPICR_bits_7_8_cdc_to_spi <= SPICR_bits_7_8_cdc_from_axi_d2;
end generate LOGIC_GENERATION_CDC;
end architecture imp;
|
-- Automatically generated: write_netlist -wrapapp -vhdl -instance reconflogic-wrapadt7310-instance.vhd
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_s,
Clk_i => Clk_i,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcValue_i,
I2C_Busy_i => I2C_Busy,
I2C_DataIn_o => I2C_DataIn,
I2C_DataOut_i => I2C_DataOut,
I2C_Divider800_o => I2C_Divider800,
I2C_ErrAckParam_o => I2C_ErrAckParam,
I2C_Error_i => I2C_Error,
I2C_F100_400_n_o => I2C_F100_400_n,
I2C_FIFOEmpty_i => I2C_FIFOEmpty,
I2C_FIFOFull_i => I2C_FIFOFull,
I2C_FIFOReadNext_o => I2C_FIFOReadNext,
I2C_FIFOWrite_o => I2C_FIFOWrite,
I2C_ReadCount_o => I2C_ReadCount,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n,
I2C_StartProcess_o => I2C_StartProcess,
Inputs_i => Inputs_i,
Outputs_o => Outputs_o,
ReconfModuleIRQs_o => ReconfModuleIRQs_s,
SPI_CPHA_o => SPI_CPHA,
SPI_CPOL_o => SPI_CPOL,
SPI_DataIn_o => SPI_DataIn,
SPI_DataOut_i => SPI_DataOut,
SPI_FIFOEmpty_i => SPI_FIFOEmpty,
SPI_FIFOFull_i => SPI_FIFOFull,
SPI_LSBFE_o => SPI_LSBFE,
SPI_ReadNext_o => SPI_ReadNext,
SPI_SPPR_SPR_o => SPI_SPPR_SPR,
SPI_Transmission_i => SPI_Transmission,
SPI_Write_o => SPI_Write,
ReconfModuleIn_i => ReconfModuleIn_s,
ReconfModuleOut_o => ReconfModuleOut_s,
I2C_Errors_i => I2C_Errors,
PerAddr_i => Per_Addr_s,
PerDIn_i => Per_DIn_s,
PerWr_i => Per_Wr_s,
PerEn_i => Per_En_s,
CfgIntfDOut_o => CfgIntf_DOut_s,
ParamIntfDOut_o => ParamIntf_DOut_s
);
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_alu_control IS
END tb_alu_control;
ARCHITECTURE behavior OF tb_alu_control IS
--Inputs
SIGNAL tb_funct : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_ALUop : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_operation : std_logic_vector(3 DOWNTO 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut : ENTITY work.alu_control(Behavioral)
PORT MAP(
funct => tb_funct,
ALUop => tb_ALUop,
operation => tb_operation
);
-- Stimulus process
stim_proc : PROCESS
BEGIN
-- R-type commands (see green sheet)
tb_ALUop <= "10";
tb_funct <= "100100"; -- and
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "100101"; -- or
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "100000"; -- add
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "100010"; -- sub
WAIT FOR 20 ns;
tb_ALUop <= "10";
tb_funct <= "101010"; -- slt
WAIT FOR 20 ns;
-- I type commands
-- load word command
tb_ALUop <= "00";
tb_funct <= "XXXXXX"; -- and
WAIT FOR 20 ns;
-- store word command
tb_ALUop <= "00";
tb_funct <= "XXXXXX"; -- and
WAIT FOR 20 ns;
-- branch equal command
tb_ALUop <= "00";
tb_funct <= "XXXXXX"; -- and
WAIT FOR 20 ns;
ASSERT false
REPORT "END"
SEVERITY failure;
END PROCESS;
END; |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_rnd;
architecture behaviour of sse_rnd is
constant st11: std_logic_vector(3 downto 0) := "1101";
constant st10: std_logic_vector(3 downto 0) := "0010";
constant st4: std_logic_vector(3 downto 0) := "1011";
constant st12: std_logic_vector(3 downto 0) := "1110";
constant st7: std_logic_vector(3 downto 0) := "1111";
constant st6: std_logic_vector(3 downto 0) := "0001";
constant st1: std_logic_vector(3 downto 0) := "0110";
constant st0: std_logic_vector(3 downto 0) := "0000";
constant st8: std_logic_vector(3 downto 0) := "1010";
constant st9: std_logic_vector(3 downto 0) := "1000";
constant st3: std_logic_vector(3 downto 0) := "0100";
constant st2: std_logic_vector(3 downto 0) := "1001";
constant st5: std_logic_vector(3 downto 0) := "1100";
constant st13: std_logic_vector(3 downto 0) := "0011";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st11 =>
if std_match(input, "0------") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10----0") then next_state <= st10; output <= "00110-0";
elsif std_match(input, "10----1") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "11----0") then next_state <= st4; output <= "0011010";
elsif std_match(input, "11----1") then next_state <= st4; output <= "0001010";
end if;
when st10 =>
if std_match(input, "100----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "101-1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "101-0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st7 =>
if std_match(input, "10-----") then next_state <= st6; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st6 =>
if std_match(input, "10--0--") then next_state <= st7; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st12 =>
if std_match(input, "10-----") then next_state <= st1; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st1 =>
if std_match(input, "10-1---") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10--1--") then next_state <= st12; output <= "10000-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st0 =>
if std_match(input, "10---0-") then next_state <= st0; output <= "0100000";
elsif std_match(input, "10---1-") then next_state <= st8; output <= "01000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st8 =>
if std_match(input, "10-----") then next_state <= st9; output <= "0000010";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st9 =>
if std_match(input, "10---0-") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10---1-") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st3 =>
if std_match(input, "10-----") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st2 =>
if std_match(input, "1001---") then next_state <= st2; output <= "00000-0";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "00010-0";
elsif std_match(input, "10-00--") then next_state <= st0; output <= "0100010";
elsif std_match(input, "1011---") then next_state <= st3; output <= "10000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
elsif std_match(input, "11-----") then next_state <= st4; output <= "0000010";
end if;
when st4 =>
if std_match(input, "0----0-") then next_state <= st4; output <= "000--00";
elsif std_match(input, "11---0-") then next_state <= st4; output <= "0000000";
elsif std_match(input, "0----1-") then next_state <= st11; output <= "000---1";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "11---1-") then next_state <= st5; output <= "00001-0";
end if;
when st5 =>
if std_match(input, "11-----") then next_state <= st5; output <= "00001-0";
elsif std_match(input, "10-----") then next_state <= st10; output <= "00000-0";
elsif std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st13 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st14 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when st15 =>
if std_match(input, "0------") then next_state <= st4; output <= "000--10";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:12:07 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top zqynq_lab_1_design_auto_pc_0 -prefix
-- zqynq_lab_1_design_auto_pc_0_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.zqynq_lab_1_design_auto_pc_0_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zqynq_lab_1_design_auto_pc_0 is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zqynq_lab_1_design_auto_pc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zqynq_lab_1_design_auto_pc_0 : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of zqynq_lab_1_design_auto_pc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of zqynq_lab_1_design_auto_pc_0 : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
end zqynq_lab_1_design_auto_pc_0;
architecture STRUCTURE of zqynq_lab_1_design_auto_pc_0 is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.zqynq_lab_1_design_auto_pc_0_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: mod12counter.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mod12counter IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END mod12counter;
ARCHITECTURE SYN OF mod12counter IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(3 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 12,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 4
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "12"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: mod12counter.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Full Version
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY mod12counter IS
PORT
(
clock : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END mod12counter;
ARCHITECTURE SYN OF mod12counter IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (3 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
sclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(3 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 12,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 4
)
PORT MAP (
sclr => sclr,
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria GX"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "12"
-- Retrieval info: PRIVATE: SCLR NUMERIC "1"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "4"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "12"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "4"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 4 0 OUTPUT NODEFVAL q[3..0]
-- Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 4 0 @q 0 0 4 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.cmp FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL mod12counter_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo hex2seg.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Visualizza un numero esadecimale sul display a 7 segmenti.
-- **********************************************************
library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
entity hex2seg is port (
hex: in std_logic_vector(3 downto 0);
seg: out std_logic_vector(6 downto 0)
);
end hex2seg;
architecture behaviour of hex2seg is
begin
with hex select seg <=
"1000000" when "0000", -- 0
"1111001" when "0001", -- 1
"0100100" when "0010", -- 2
"0110000" when "0011", -- 3
"0011001" when "0100", -- 4
"0010010" when "0101", -- 5
"0000010" when "0110", -- 6
"1111000" when "0111", -- 7
"0000000" when "1000", -- 8
"0010000" when "1001", -- 9
"0001000" when "1010", -- A
"0000011" when "1011", -- B
"1000110" when "1100", -- C
"0100001" when "1101", -- D
"0000110" when "1110", -- E
"0001110" when "1111", -- F
"1111111" when others;
end behaviour; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <hamster@sanp.net.nz>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
advance : in STD_LOGIC;
command : out std_logic_vector(15 downto 0);
finished : out STD_LOGIC);
end ov7670_registers;
architecture Behavioral of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
-- when x"10" => sreg <= x"703a"; -- SCALING_XSC
-- when x"11" => sreg <= x"7135"; -- SCALING_YSC
-- when x"12" => sreg <= x"7200"; -- SCALING_DCWCTR -- zzz was 11
-- when x"13" => sreg <= x"7300"; -- SCALING_PCLK_DIV
-- when x"14" => sreg <= x"a200"; -- SCALING_PCLK_DELAY must match COM14
-- when x"15" => sreg <= x"1500"; -- COM10 Use HREF not hSYNC
--
-- when x"1D" => sreg <= x"B104"; -- ABLC1 - Turn on auto black level
-- when x"1F" => sreg <= x"138F"; -- COM8 - AGC, White balance
-- when x"21" => sreg <= x"FFFF"; -- spare
-- when x"22" => sreg <= x"FFFF"; -- spare
-- when x"23" => sreg <= x"0000"; -- spare
-- when x"24" => sreg <= x"0000"; -- spare
-- when x"25" => sreg <= x"138F"; -- COM8 - AGC, White balance
-- when x"26" => sreg <= x"0000"; -- spare
-- when x"27" => sreg <= x"1000"; -- AECH Exposure
-- when x"28" => sreg <= x"0D40"; -- COMM4 - Window Size
-- when x"29" => sreg <= x"0000"; -- spare
-- when x"2a" => sreg <= x"a505"; -- AECGMAX banding filter step
-- when x"2b" => sreg <= x"2495"; -- AEW AGC Stable upper limite
-- when x"2c" => sreg <= x"2533"; -- AEB AGC Stable lower limi
-- when x"2d" => sreg <= x"26e3"; -- VPT AGC fast mode limits
-- when x"2e" => sreg <= x"9f78"; -- HRL High reference level
-- when x"2f" => sreg <= x"A068"; -- LRL low reference level
-- when x"30" => sreg <= x"a103"; -- DSPC3 DSP control
-- when x"31" => sreg <= x"A6d8"; -- LPH Lower Prob High
-- when x"32" => sreg <= x"A7d8"; -- UPL Upper Prob Low
-- when x"33" => sreg <= x"A8f0"; -- TPL Total Prob Low
-- when x"34" => sreg <= x"A990"; -- TPH Total Prob High
-- when x"35" => sreg <= x"AA94"; -- NALG AEC Algo select
-- when x"36" => sreg <= x"13E5"; -- COM8 AGC Settings
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <hamster@sanp.net.nz>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity ov7670_registers is
Port ( clk : in STD_LOGIC;
resend : in STD_LOGIC;
advance : in STD_LOGIC;
command : out std_logic_vector(15 downto 0);
finished : out STD_LOGIC);
end ov7670_registers;
architecture Behavioral of ov7670_registers is
signal sreg : std_logic_vector(15 downto 0);
signal address : std_logic_vector(7 downto 0) := (others => '0');
begin
command <= sreg;
with sreg select finished <= '1' when x"FFFF", '0' when others;
process(clk)
begin
if rising_edge(clk) then
if resend = '1' then
address <= (others => '0');
elsif advance = '1' then
address <= std_logic_vector(unsigned(address)+1);
end if;
case address is
when x"00" => sreg <= x"1280"; -- COM7 Reset
when x"01" => sreg <= x"1280"; -- COM7 Reset
when x"02" => sreg <= x"1204"; -- COM7 Size & RGB output
when x"03" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"04" => sreg <= x"0C00"; -- COM3 Lots of stuff, enable scaling, all others off
when x"05" => sreg <= x"3E00"; -- COM14 PCLK scaling off
when x"06" => sreg <= x"8C00"; -- RGB444 Set RGB format
when x"07" => sreg <= x"0400"; -- COM1 no CCIR601
when x"08" => sreg <= x"4010"; -- COM15 Full 0-255 output, RGB 565
when x"09" => sreg <= x"3a04"; -- TSLB Set UV ordering, do not auto-reset window
when x"0A" => sreg <= x"1438"; -- COM9 - AGC Celling
when x"0B" => sreg <= x"4fb3"; -- MTX1 - colour conversion matrix
when x"0C" => sreg <= x"50b3"; -- MTX2 - colour conversion matrix
when x"0D" => sreg <= x"5100"; -- MTX3 - colour conversion matrix
when x"0E" => sreg <= x"523d"; -- MTX4 - colour conversion matrix
when x"0F" => sreg <= x"53a7"; -- MTX5 - colour conversion matrix
when x"10" => sreg <= x"54e4"; -- MTX6 - colour conversion matrix
when x"11" => sreg <= x"589e"; -- MTXS - Matrix sign and auto contrast
when x"12" => sreg <= x"3dc0"; -- COM13 - Turn on GAMMA and UV Auto adjust
when x"13" => sreg <= x"1100"; -- CLKRC Prescaler - Fin/(1+1)
when x"14" => sreg <= x"1711"; -- HSTART HREF start (high 8 bits)
when x"15" => sreg <= x"1861"; -- HSTOP HREF stop (high 8 bits)
when x"16" => sreg <= x"32A4"; -- HREF Edge offset and low 3 bits of HSTART and HSTOP
when x"17" => sreg <= x"1903"; -- VSTART VSYNC start (high 8 bits)
when x"18" => sreg <= x"1A7b"; -- VSTOP VSYNC stop (high 8 bits)
when x"19" => sreg <= x"030a"; -- VREF VSYNC low two bits
-- when x"10" => sreg <= x"703a"; -- SCALING_XSC
-- when x"11" => sreg <= x"7135"; -- SCALING_YSC
-- when x"12" => sreg <= x"7200"; -- SCALING_DCWCTR -- zzz was 11
-- when x"13" => sreg <= x"7300"; -- SCALING_PCLK_DIV
-- when x"14" => sreg <= x"a200"; -- SCALING_PCLK_DELAY must match COM14
-- when x"15" => sreg <= x"1500"; -- COM10 Use HREF not hSYNC
--
-- when x"1D" => sreg <= x"B104"; -- ABLC1 - Turn on auto black level
-- when x"1F" => sreg <= x"138F"; -- COM8 - AGC, White balance
-- when x"21" => sreg <= x"FFFF"; -- spare
-- when x"22" => sreg <= x"FFFF"; -- spare
-- when x"23" => sreg <= x"0000"; -- spare
-- when x"24" => sreg <= x"0000"; -- spare
-- when x"25" => sreg <= x"138F"; -- COM8 - AGC, White balance
-- when x"26" => sreg <= x"0000"; -- spare
-- when x"27" => sreg <= x"1000"; -- AECH Exposure
-- when x"28" => sreg <= x"0D40"; -- COMM4 - Window Size
-- when x"29" => sreg <= x"0000"; -- spare
-- when x"2a" => sreg <= x"a505"; -- AECGMAX banding filter step
-- when x"2b" => sreg <= x"2495"; -- AEW AGC Stable upper limite
-- when x"2c" => sreg <= x"2533"; -- AEB AGC Stable lower limi
-- when x"2d" => sreg <= x"26e3"; -- VPT AGC fast mode limits
-- when x"2e" => sreg <= x"9f78"; -- HRL High reference level
-- when x"2f" => sreg <= x"A068"; -- LRL low reference level
-- when x"30" => sreg <= x"a103"; -- DSPC3 DSP control
-- when x"31" => sreg <= x"A6d8"; -- LPH Lower Prob High
-- when x"32" => sreg <= x"A7d8"; -- UPL Upper Prob Low
-- when x"33" => sreg <= x"A8f0"; -- TPL Total Prob Low
-- when x"34" => sreg <= x"A990"; -- TPH Total Prob High
-- when x"35" => sreg <= x"AA94"; -- NALG AEC Algo select
-- when x"36" => sreg <= x"13E5"; -- COM8 AGC Settings
when others => sreg <= x"ffff";
end case;
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
package TRFSMParts is
component StateSelectionGate
generic (
StateWidth : integer range 1 to 10);
port (
Reset_n_i : in std_logic;
State_i : in std_logic_vector(StateWidth-1 downto 0);
Match_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component InputSwitchingMatrix
generic (
InputWidth : integer range 1 to 256;
OutputWidth : integer range 1 to 256);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component InputPatternGate
generic (
InputWidth : integer range 1 to 10);
port (
Reset_n_i : in std_logic;
Enable_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Match_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component ConfigRegister
generic (
Width : integer range 1 to 1024);
port (
Reset_n_i : in std_logic;
Output_o : out std_logic_vector(Width-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component TransitionRow
generic (
TotalInputWidth : integer range 1 to 256;
MyInputWidth : integer range 0 to 10;
StateWidth : integer range 1 to 10;
OutputWidth : integer range 1 to 256);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(TotalInputWidth-1 downto 0);
State_i : in std_logic_vector(StateWidth-1 downto 0);
Match_o : out std_logic;
NextState_o : out std_logic_vector(StateWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component LargeMux
generic (
NumTransitionRows : integer;
Width : integer);
port (
Select_i : in std_logic_vector(NumTransitionRows -1 downto 0);
Inputs_i : in std_logic_vector(NumTransitionRows*Width-1 downto 0);
Output_o : out std_logic_vector(Width-1 downto 0));
end component;
component StateRegister
generic (
StateWidth : integer range 1 to 8);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
State_o : out std_logic_vector(StateWidth-1 downto 0);
NextState_i : in std_logic_vector(StateWidth-1 downto 0));
end component;
end TRFSMParts;
package body TRFSMParts is
end TRFSMParts;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
package TRFSMParts is
component StateSelectionGate
generic (
StateWidth : integer range 1 to 10);
port (
Reset_n_i : in std_logic;
State_i : in std_logic_vector(StateWidth-1 downto 0);
Match_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component InputSwitchingMatrix
generic (
InputWidth : integer range 1 to 256;
OutputWidth : integer range 1 to 256);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component InputPatternGate
generic (
InputWidth : integer range 1 to 10);
port (
Reset_n_i : in std_logic;
Enable_i : in std_logic;
Input_i : in std_logic_vector(InputWidth-1 downto 0);
Match_o : out std_logic;
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component ConfigRegister
generic (
Width : integer range 1 to 1024);
port (
Reset_n_i : in std_logic;
Output_o : out std_logic_vector(Width-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component TransitionRow
generic (
TotalInputWidth : integer range 1 to 256;
MyInputWidth : integer range 0 to 10;
StateWidth : integer range 1 to 10;
OutputWidth : integer range 1 to 256);
port (
Reset_n_i : in std_logic;
Input_i : in std_logic_vector(TotalInputWidth-1 downto 0);
State_i : in std_logic_vector(StateWidth-1 downto 0);
Match_o : out std_logic;
NextState_o : out std_logic_vector(StateWidth-1 downto 0);
Output_o : out std_logic_vector(OutputWidth-1 downto 0);
CfgMode_i : in std_logic;
CfgClk_i : in std_logic;
CfgShift_i : in std_logic;
CfgDataIn_i : in std_logic;
CfgDataOut_o : out std_logic);
end component;
component LargeMux
generic (
NumTransitionRows : integer;
Width : integer);
port (
Select_i : in std_logic_vector(NumTransitionRows -1 downto 0);
Inputs_i : in std_logic_vector(NumTransitionRows*Width-1 downto 0);
Output_o : out std_logic_vector(Width-1 downto 0));
end component;
component StateRegister
generic (
StateWidth : integer range 1 to 8);
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
State_o : out std_logic_vector(StateWidth-1 downto 0);
NextState_i : in std_logic_vector(StateWidth-1 downto 0));
end component;
end TRFSMParts;
package body TRFSMParts is
end TRFSMParts;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UART is
port (
Clkin :in std_logic;
READin :in std_logic;
RXDin :in std_logic;
ASCIIin :in std_logic_vector (7 downto 0);
ASCII_out:out std_logic_vector (7 downto 0);
TXD_out :out std_logic;
READ_out : out std_logic);
end UART;
architecture Behavioral of UART is
signal TEST : std_logic;
signal CLKTXD : std_logic;
signal CLKRXD : std_logic;
signal X : std_logic_vector(1 downto 0);
-----------------------------------------------
component UartClkDiv
port(
CLKin : in std_logic;
CLKTXD_out : inout std_logic;
CLKRXD_out : inout std_logic);
end component;
-----------------------------------------------
component UartLogic is
port (
reset :in std_logic;
txclk :in std_logic;
ld_tx_data :in std_logic;
tx_data :in std_logic_vector (7 downto 0);
tx_enable :in std_logic;
tx_out :out std_logic;
tx_empty :out std_logic;
---------------
rxclk :in std_logic;
uld_rx_data :in std_logic;
rx_data :out std_logic_vector (7 downto 0);
rx_enable :in std_logic;
rx_in :in std_logic;
rx_empty :out std_logic);
end component;
-----------------------------------------------
begin
UART_CLK_DIV : UartClkDiv port map( CLKin => CLKin,
CLKTXD_out => CLKTXD,
CLKRXD_out => CLKRXD);
UART_LOGIC : UartLogic port map( reset => '0',
-------------------------
txclk => CLKTXD,
ld_tx_data => READin,
tx_data => ASCIIin,
tx_enable => '1',
tx_out => TXD_out,
tx_empty => X(0),
------------------------
rxclk => CLKRXD,
uld_rx_data => '1',
rx_data => ASCII_out,
rx_enable => '1',
rx_in => RXDin,
rx_empty => READ_out);
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal count : natural range 0 to g_duration-1;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
pulse_out <= '0';
count <= 0;
elsif pulse_in='1' then
pulse_out <= '1';
count <= g_duration-1;
elsif count = 0 then
pulse_out <= '0';
else
count <= count - 1;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal count : natural range 0 to g_duration-1;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
pulse_out <= '0';
count <= 0;
elsif pulse_in='1' then
pulse_out <= '1';
count <= g_duration-1;
elsif count = 0 then
pulse_out <= '0';
else
count <= count - 1;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal count : natural range 0 to g_duration-1;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
pulse_out <= '0';
count <= 0;
elsif pulse_in='1' then
pulse_out <= '1';
count <= g_duration-1;
elsif count = 0 then
pulse_out <= '0';
else
count <= count - 1;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal count : natural range 0 to g_duration-1;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
pulse_out <= '0';
count <= 0;
elsif pulse_in='1' then
pulse_out <= '1';
count <= g_duration-1;
elsif count = 0 then
pulse_out <= '0';
else
count <= count - 1;
end if;
end if;
end process;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal count : natural range 0 to g_duration-1;
begin
process(clock)
begin
if rising_edge(clock) then
if reset='1' then
pulse_out <= '0';
count <= 0;
elsif pulse_in='1' then
pulse_out <= '1';
count <= g_duration-1;
elsif count = 0 then
pulse_out <= '0';
else
count <= count - 1;
end if;
end if;
end process;
end rtl;
|
entity test is
subtype t is foo(open)(open);
end;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.