content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:32:02 04/01/2014
-- Design Name:
-- Module Name: C:/Users/fafik/Dropbox/infa/xilinx/ethernet4/disp_test.vhd
-- Project Name: ethernet
-- Target Device:
-- Tool versions:
-- Descri... |
architecture rtl of fifo is
begin
process
begin
var1 := '0' when rd_en = '1' ELSE '1';
var2 := '0' when rd_en = '1' else '1';
wr_en_a <= force '0' when rd_en = '1' ELSE '1';
wr_en_b <= force '0' when rd_en = '1' else '1';
end process;
concurrent_wr_en_a <= '0' when rd_en = '1' ELSE '1';... |
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- Complete implementation of Patterson and Hennessy single cycle MIPS processor
-- Copyright (C) 2015 Darci Luiz Tomasi Junior
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the ... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_FSM i... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:45:56 05/22/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_n_cycles_delayer.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- ... |
-- Eric Bainville
-- Mar 2013
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.math_real.all;
entity basic_uart is
generic (
DIVISOR: natural -- DIVISOR = 100,000,000 / (16 x BAUD_RATE)
-- 2400 -> 2604
-- 9600 -> 651
-- 115200 -> 54
-- 1562500 -... |
library ieee;
use ieee.std_logic_1164.all;
entity split_48_bits_to_8x6 is
port( data_in: in std_logic_vector(0 to 47);
data_out_1: out std_logic_vector(0 to 5); --holds data 0 to 5
data_out_2: out std_logic_vector(0 to 5); --holds data 6 to 11
data_out_3: out std_logic_vector(0 to 5); --holds data 12 to 17
data_o... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
------------------------------------------------------------------------
--
-- Filename : xlconcat.vhd
--
-- Date : 03/14/2014
--
-- Description : VHDL description of a concat block. This
-- block does not use a core.
--
--------------------------------------------------------------... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := ... |
--Copyright (C) 2016 Siavoosh Payandeh Azad
library ieee;
use ieee.std_logic_1164.all;
--use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity router_credit_based_PD_C_SHMU is --fault classifier plus packet-dropping
generic (
DATA_WIDTH: integer := 32;
current_address : integer := ... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity IO_ctl is
port(clk : in std_logic;
rst : in std_logic;
iport : in std_logic_vector(31 downto 0);
iport_data : out std_logic_vector(3... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity IO_ctl is
port(clk : in std_logic;
rst : in std_logic;
iport : in std_logic_vector(31 downto 0);
iport_data : out std_logic_vector(3... |
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : xd_output_scalars_fifo.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created ... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later ver... |
library IEEE;
use IEEE.std_logic_1164.all;
-- Contador BCD 0-9 con flag
entity bcd is
port (
clk: in std_logic;
rst: in std_logic;
ena: in std_logic;
q: out std_logic_vector(3 downto 0);
c: out std_logic -- Flag de carry
);
end;
architecture bcd_arq of bcd is
signal rst_aux: std_logic :... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
-----------------------------------------------------------------------------
-- Altera DSP Builder Advanced Flow Tools Release Version 13.1
-- Quartus II development tool and MATLAB/Simulink Interface
--
-- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation... |
--========================================================================================================================
-- Copyright (c) 2017 by Bitvis AS. All rights reserved.
-- You should have received a copy of the license file containing the MIT License (see LICENSE.TXT), if not,
-- contact Bitvis AS <support... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:03:50 10/08/2011
-- Design Name:
-- Module Name: C:/Users/BOB/Calculadora/Source/ArithmeticTest.vhd
-- Project Name: Calculadora
-- Target Device:
-- Tool versions:
-- Description... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std... |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity huff_make_dhuff_tb_ac_huffsize is
port (
wa0_data : in std_logic_vector(31 downto 0);
wa0_addr : in std_logic_vector(8 downto 0);
clk : in std_logic;
ra0_addr : in std_logic_vector(8 downto 0);
ra0_data : out std... |
library ieee;
use ieee.std_logic_1164.all;
entity LAB7a is
port (
KEY : in std_logic_vector(3 downto 0);
HEX0: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end LAB7a;
architecture LAB7a_estru of LAB7a is
signal QQ, q: std_logic_vector(3 downto 0);
signal F: std_logic_vector (3 downto 0... |
library ieee;
use ieee.std_logic_1164.all;
entity LAB7a is
port (
KEY : in std_logic_vector(3 downto 0);
HEX0: out std_logic_vector(6 downto 0);
LEDR : out std_logic_vector(9 downto 0)
);
end LAB7a;
architecture LAB7a_estru of LAB7a is
signal QQ, q: std_logic_vector(3 downto 0);
signal F: std_logic_vector (3 downto 0... |
--
-- Declares a clock divider to synchronize the VGA scanlines
--
-- Original author: unknown
--
-- Peter Heatwole, Aaron Barton
-- CPE233, Winter 2012, CalPoly
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity vga_clk_div is
port(clk : in std_logic;
clkout : out std_logic);
end vga_clk_div;
ar... |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 20 13:53:58 2017
-- Host : GILAMONSTER running 64-bit major rel... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
Library IEEE;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
Use ieee.numeric_std.all;
Entity ULA is
port (
in0, in1: in std_logic_vector(31 downto 0);
oper: in std_logic_vector(3 downto 0);
zero: out std_logic;
output : out std_logic_vector(31 downto 0)
);
end ULA;
architecture rtl o... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
----------------------------------------------------------------------------------
--
-- Lab session #1: vga controller
--
-- Author: David Estévez Fernández
-- David Estévez Fernández
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect ke... |
--
-- Copyright 2019 The Project Oak Authors
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law o... |
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
... |
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
... |
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
... |
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
... |
entity case6 is
end entity;
architecture test of case6 is
signal x, y : integer;
begin
process (x) is
begin
case x is
when 1 to 5 =>
y <= 1;
when 6 =>
y <= 2;
when 7 to 10 =>
y <= 3;
when others =>
... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-------------------------------------------------------------------------------
-- $Id: cross_clk_sync_fifo_0.vhd
-------------------------------------------------------------------------------
-- cross_clk_sync_fifo_0.vhd - Entity and architecture
-----------------------------------------------------------------------... |
-- Automatically generated: write_netlist -wrapapp -vhdl -instance reconflogic-wrapadt7310-instance.vhd
MyReconfigLogic_0: MyReconfigLogic
port map (
Reset_n_i => Reset_n_s,
Clk_i => Clk_i,
AdcConvComplete_i => AdcConvComplete_i,
AdcDoConvert_o => AdcDoConvert_o,
AdcValue_i => AdcVa... |
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_alu_control IS
END tb_alu_control;
ARCHITECTURE behavior OF tb_alu_control IS
--Inputs
SIGNAL tb_funct : std_logic_vector(5 DOWNTO 0) := (OTHERS => '0');
SIGNAL tb_ALUop : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0');
--Outputs
SIGNAL tb_operation : std_logic... |
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity sse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end sse_rnd;
architecture behaviour of sse_rnd is
constant st11: std_logic_vector(3 downto 0) := "11... |
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Wed Sep 20 21:12:07 2017
-- Host : EffulgentTome running 64-bit major r... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: mod12counter.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: mod12counter.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- =============================... |
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo hex2seg.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- ****************************************... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <hamster@sanp.net.nz>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
-------------------------------------------------------... |
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Mike Field <hamster@sanp.net.nz>
--
-- Description: Register settings for the OV7670 Caamera (partially from OV7670.c
-- in the Linux Kernel
-------------------------------------------------------... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
package TRFSMParts is
component StateSelectionGate
generic (
StateWidth : integer range 1 to 10);
port (
Reset_n_i : in std_logic;
State_i : in std_logic_vector(StateWidth-1 down... |
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
package TRFSMParts is
component StateSelectionGate
generic (
StateWidth : integer range 1 to 10);
port (
Reset_n_i : in std_logic;
State_i : in std_logic_vector(StateWidth-1 down... |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity UART is
port (
Clkin :in std_logic;
READin :in std_logic;
RXDin :in std_logic;
ASCIIin :in std_logic_vector (7 downto 0);
ASCII_out:out std_logic_vector (7 downto 0);
TXD_out :out std_logic;
READ_out : out std_logic);
end UART;
archit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity pulse_stretch is
generic (
g_duration : natural := 200 );
port (
clock : in std_logic;
reset : in std_logic;
pulse_in : in std_logic;
pulse_out : out std_logic );
end;
architecture rtl of pulse_stretch is
signal... |
entity test is
subtype t is foo(open)(open);
end;
|
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