content stringlengths 1 1.04M ⌀ |
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ForLoop is
generic(n : natural := 2);
port(A : in std_logic_vector(n - 1 downto 0);
B : in std_logic_vector(n - 1 downto 0);
carry : out std_logic;
sum : out std_logic_vector(n - 1 downto 0));
end ForLoop;
architecture behaviour of ForLoop is
signal result : std_logic_vector(n downto 0);
begin
forLoopProc : process
variable M : natural := 42;
variable F : natural := 10;
begin
for I in 1 to 2 loop
for J in 1 to 2 loop
for F in 1 to 2 loop
F := I + J;
end loop;
for M in 1 to 2 loop
M := I + J;
end loop;
end loop;
end loop;
end process forLoopProc;
end behaviour;
|
entity testcase is
port(clk: in bit);
begin
check: process is
begin
-- Require at least 10ns between clock edges
assert clk'delayed'last_event >= 10 ns;
wait on clk;
end process check;
end entity testcase;
-- Keep the compiler happy
architecture empty of testcase is
begin
end architecture empty;
|
entity testcase is
port(clk: in bit);
begin
check: process is
begin
-- Require at least 10ns between clock edges
assert clk'delayed'last_event >= 10 ns;
wait on clk;
end process check;
end entity testcase;
-- Keep the compiler happy
architecture empty of testcase is
begin
end architecture empty;
|
-------------------------------------------------------------------------------
--
-- The clock generation unit.
-- PHI1 clock and input/output clock enables are generated here.
--
-- $Id: t400_clkgen.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_opt_pack.all;
entity t400_clkgen is
generic (
opt_ck_div_g : integer := t400_opt_ck_div_16_c
);
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
-- Clock Interface --------------------------------------------------------
phi1_o : out std_logic;
out_en_o : out boolean;
in_en_o : out boolean;
icyc_en_o : out boolean
);
end t400_clkgen;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_clkgen is
subtype ck_div_t is unsigned(5 downto 0);
type ck_div_a_t is array(natural range t400_opt_ck_div_32_c
downto t400_opt_ck_div_4_c) of
ck_div_t;
-- reload values for the CK dividing counter
constant ck_div_a_c : ck_div_a_t := (
t400_opt_ck_div_32_c => to_unsigned(31, ck_div_t'length),
t400_opt_ck_div_16_c => to_unsigned(15, ck_div_t'length),
t400_opt_ck_div_8_c => to_unsigned( 7, ck_div_t'length),
t400_opt_ck_div_4_c => to_unsigned( 3, ck_div_t'length));
signal ck_div_cnt_q : ck_div_t;
signal ck_div_zero_s,
ck_div_half_s : boolean;
signal phi1_q : std_logic;
begin
-----------------------------------------------------------------------------
-- Process ck_div
--
-- Purpose:
-- Divide the incoming clock on ck_i and generate the derived clock
-- enable for the core.
--
ck_div: process (ck_i, por_i)
begin
if por_i then
ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
phi1_q <= '0';
elsif ck_i'event and ck_i = '1' then
if ck_en_i then
if ck_div_zero_s then
ck_div_cnt_q <= ck_div_a_c(opt_ck_div_g);
phi1_q <= '0';
else
ck_div_cnt_q <= ck_div_cnt_q - 1;
if ck_div_half_s then
phi1_q <= '1';
end if;
end if;
end if;
end if;
end process ck_div;
--
ck_div_zero_s <= ck_div_cnt_q = 0;
ck_div_half_s <= ck_div_cnt_q = SHIFT_RIGHT(ck_div_a_c(opt_ck_div_g), 1) + 1;
--
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- Output mapping
-----------------------------------------------------------------------------
phi1_o <= phi1_q;
-- Instruction cycle enable
icyc_en_o <= ck_en_i and ck_div_zero_s;
-- Output update enable
out_en_o <= ck_en_i and ck_div_zero_s;
-- Input sample enable
in_en_o <= ck_en_i and ck_div_half_s;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 04/18/2016 03:13:06 PM
-- Design Name:
-- Module Name: test3 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test3 is
-- Port ( );
end test3;
architecture Behavioral of test3 is
begin
end Behavioral;
|
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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3ul1mLnDjQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 6240)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
component internal_osc is
port (
oscena : in std_logic := 'X'; -- oscena
clkout : out std_logic -- clk
);
end component internal_osc;
u0 : component internal_osc
port map (
oscena => CONNECTED_TO_oscena, -- oscena.oscena
clkout => CONNECTED_TO_clkout -- clkout.clk
);
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Binarization_example is
end entity;
architecture rtl of tb_Binarization_example is
component tb_Binarization
end component;
begin
tb_Binarization_instance :
component tb_Binarization
port map();
end architecture rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity tb_Binarization_example is
end entity;
architecture rtl of tb_Binarization_example is
component tb_Binarization
end component;
begin
tb_Binarization_instance :
component tb_Binarization
port map();
end architecture rtl;
|
-- SIMON 64/128
-- Simon core component
--
-- @Author: Jos Wetzels
-- @Author: Wouter Bokslag
--
-- Parameters:
-- clk: clock
-- rst: reset state
-- enc: encrypt/decrypt mode
-- key: key
-- block_in: plaintext block
-- block_out: ciphertext block
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity simon is
port(clk : in std_logic;
rst : in std_logic; -- state indicator (1 = init, 0 = run)
enc : in std_logic; -- (0 = enc, 1 = dec)
key : in std_logic_vector(127 downto 0);
block_in : in std_logic_vector(63 downto 0);
block_out : out std_logic_vector(63 downto 0));
end simon;
architecture Behavioral of simon is
component key_schedule is
port (
k_in_0 : in std_logic_vector(31 downto 0);
k_in_1 : in std_logic_vector(31 downto 0);
k_in_2 : in std_logic_vector(31 downto 0);
k_in_3 : in std_logic_vector(31 downto 0);
k_0 : out std_logic_vector(31 downto 0);
k_1 : out std_logic_vector(31 downto 0);
k_2 : out std_logic_vector(31 downto 0);
k_3 : out std_logic_vector(31 downto 0);
k_4 : out std_logic_vector(31 downto 0);
k_5 : out std_logic_vector(31 downto 0);
k_6 : out std_logic_vector(31 downto 0);
k_7 : out std_logic_vector(31 downto 0);
k_8 : out std_logic_vector(31 downto 0);
k_9 : out std_logic_vector(31 downto 0);
k_10 : out std_logic_vector(31 downto 0);
k_11 : out std_logic_vector(31 downto 0);
k_12 : out std_logic_vector(31 downto 0);
k_13 : out std_logic_vector(31 downto 0);
k_14 : out std_logic_vector(31 downto 0);
k_15 : out std_logic_vector(31 downto 0);
k_16 : out std_logic_vector(31 downto 0);
k_17 : out std_logic_vector(31 downto 0);
k_18 : out std_logic_vector(31 downto 0);
k_19 : out std_logic_vector(31 downto 0);
k_20 : out std_logic_vector(31 downto 0);
k_21 : out std_logic_vector(31 downto 0);
k_22 : out std_logic_vector(31 downto 0);
k_23 : out std_logic_vector(31 downto 0);
k_24 : out std_logic_vector(31 downto 0);
k_25 : out std_logic_vector(31 downto 0);
k_26 : out std_logic_vector(31 downto 0);
k_27 : out std_logic_vector(31 downto 0);
k_28 : out std_logic_vector(31 downto 0);
k_29 : out std_logic_vector(31 downto 0);
k_30 : out std_logic_vector(31 downto 0);
k_31 : out std_logic_vector(31 downto 0);
k_32 : out std_logic_vector(31 downto 0);
k_33 : out std_logic_vector(31 downto 0);
k_34 : out std_logic_vector(31 downto 0);
k_35 : out std_logic_vector(31 downto 0);
k_36 : out std_logic_vector(31 downto 0);
k_37 : out std_logic_vector(31 downto 0);
k_38 : out std_logic_vector(31 downto 0);
k_39 : out std_logic_vector(31 downto 0);
k_40 : out std_logic_vector(31 downto 0);
k_41 : out std_logic_vector(31 downto 0);
k_42 : out std_logic_vector(31 downto 0);
k_43 : out std_logic_vector(31 downto 0));
end component;
component round_f
port(clk : in std_logic;
rst : in std_logic;
enc : std_logic;
v_in : in std_logic_vector(63 downto 0);
v_k_e : in std_logic_vector(31 downto 0);
v_k_d : in std_logic_vector(31 downto 0);
v_out : out std_logic_vector(63 downto 0)
);
END component;
component reg_64 is
port(clk : in std_logic;
rst : in std_logic;
data_in : in std_logic_vector(63 downto 0);
data_out : out std_logic_vector(63 downto 0));
end component;
type key_t is array (0 to 3) of std_logic_vector(31 downto 0);
signal key_s : key_t; -- intermediate key (in words)
signal k_0 : std_logic_vector(31 downto 0);
signal k_1 : std_logic_vector(31 downto 0);
signal k_2 : std_logic_vector(31 downto 0);
signal k_3 : std_logic_vector(31 downto 0);
signal k_4 : std_logic_vector(31 downto 0);
signal k_5 : std_logic_vector(31 downto 0);
signal k_6 : std_logic_vector(31 downto 0);
signal k_7 : std_logic_vector(31 downto 0);
signal k_8 : std_logic_vector(31 downto 0);
signal k_9 : std_logic_vector(31 downto 0);
signal k_10 : std_logic_vector(31 downto 0);
signal k_11 : std_logic_vector(31 downto 0);
signal k_12 : std_logic_vector(31 downto 0);
signal k_13 : std_logic_vector(31 downto 0);
signal k_14 : std_logic_vector(31 downto 0);
signal k_15 : std_logic_vector(31 downto 0);
signal k_16 : std_logic_vector(31 downto 0);
signal k_17 : std_logic_vector(31 downto 0);
signal k_18 : std_logic_vector(31 downto 0);
signal k_19 : std_logic_vector(31 downto 0);
signal k_20 : std_logic_vector(31 downto 0);
signal k_21 : std_logic_vector(31 downto 0);
signal k_22 : std_logic_vector(31 downto 0);
signal k_23 : std_logic_vector(31 downto 0);
signal k_24 : std_logic_vector(31 downto 0);
signal k_25 : std_logic_vector(31 downto 0);
signal k_26 : std_logic_vector(31 downto 0);
signal k_27 : std_logic_vector(31 downto 0);
signal k_28 : std_logic_vector(31 downto 0);
signal k_29 : std_logic_vector(31 downto 0);
signal k_30 : std_logic_vector(31 downto 0);
signal k_31 : std_logic_vector(31 downto 0);
signal k_32 : std_logic_vector(31 downto 0);
signal k_33 : std_logic_vector(31 downto 0);
signal k_34 : std_logic_vector(31 downto 0);
signal k_35 : std_logic_vector(31 downto 0);
signal k_36 : std_logic_vector(31 downto 0);
signal k_37 : std_logic_vector(31 downto 0);
signal k_38 : std_logic_vector(31 downto 0);
signal k_39 : std_logic_vector(31 downto 0);
signal k_40 : std_logic_vector(31 downto 0);
signal k_41 : std_logic_vector(31 downto 0);
signal k_42 : std_logic_vector(31 downto 0);
signal k_43 : std_logic_vector(31 downto 0);
signal ct_in_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_in_1 : std_logic_vector(63 downto 0);
signal ct_in_2 : std_logic_vector(63 downto 0);
signal ct_in_3 : std_logic_vector(63 downto 0);
signal ct_in_4 : std_logic_vector(63 downto 0);
signal ct_in_5 : std_logic_vector(63 downto 0);
signal ct_in_6 : std_logic_vector(63 downto 0);
signal ct_in_7 : std_logic_vector(63 downto 0);
signal ct_in_8 : std_logic_vector(63 downto 0);
signal ct_in_9 : std_logic_vector(63 downto 0);
signal ct_in_10 : std_logic_vector(63 downto 0);
signal ct_in_11 : std_logic_vector(63 downto 0);
signal ct_in_12 : std_logic_vector(63 downto 0);
signal ct_in_13 : std_logic_vector(63 downto 0);
signal ct_in_14 : std_logic_vector(63 downto 0);
signal ct_in_15 : std_logic_vector(63 downto 0);
signal ct_in_16 : std_logic_vector(63 downto 0);
signal ct_in_17 : std_logic_vector(63 downto 0);
signal ct_in_18 : std_logic_vector(63 downto 0);
signal ct_in_19 : std_logic_vector(63 downto 0);
signal ct_in_20 : std_logic_vector(63 downto 0);
signal ct_in_21 : std_logic_vector(63 downto 0);
signal ct_in_22 : std_logic_vector(63 downto 0);
signal ct_in_23 : std_logic_vector(63 downto 0);
signal ct_in_24 : std_logic_vector(63 downto 0);
signal ct_in_25 : std_logic_vector(63 downto 0);
signal ct_in_26 : std_logic_vector(63 downto 0);
signal ct_in_27 : std_logic_vector(63 downto 0);
signal ct_in_28 : std_logic_vector(63 downto 0);
signal ct_in_29 : std_logic_vector(63 downto 0);
signal ct_in_30 : std_logic_vector(63 downto 0);
signal ct_in_31 : std_logic_vector(63 downto 0);
signal ct_in_32 : std_logic_vector(63 downto 0);
signal ct_in_33 : std_logic_vector(63 downto 0);
signal ct_in_34 : std_logic_vector(63 downto 0);
signal ct_in_35 : std_logic_vector(63 downto 0);
signal ct_in_36 : std_logic_vector(63 downto 0);
signal ct_in_37 : std_logic_vector(63 downto 0);
signal ct_in_38 : std_logic_vector(63 downto 0);
signal ct_in_39 : std_logic_vector(63 downto 0);
signal ct_in_40 : std_logic_vector(63 downto 0);
signal ct_in_41 : std_logic_vector(63 downto 0);
signal ct_in_42 : std_logic_vector(63 downto 0);
signal ct_in_43 : std_logic_vector(63 downto 0);
signal ct_out_0 : std_logic_vector(63 downto 0); -- intermediate ciphertext after round 0
signal ct_out_1 : std_logic_vector(63 downto 0);
signal ct_out_2 : std_logic_vector(63 downto 0);
signal ct_out_3 : std_logic_vector(63 downto 0);
signal ct_out_4 : std_logic_vector(63 downto 0);
signal ct_out_5 : std_logic_vector(63 downto 0);
signal ct_out_6 : std_logic_vector(63 downto 0);
signal ct_out_7 : std_logic_vector(63 downto 0);
signal ct_out_8 : std_logic_vector(63 downto 0);
signal ct_out_9 : std_logic_vector(63 downto 0);
signal ct_out_10 : std_logic_vector(63 downto 0);
signal ct_out_11 : std_logic_vector(63 downto 0);
signal ct_out_12 : std_logic_vector(63 downto 0);
signal ct_out_13 : std_logic_vector(63 downto 0);
signal ct_out_14 : std_logic_vector(63 downto 0);
signal ct_out_15 : std_logic_vector(63 downto 0);
signal ct_out_16 : std_logic_vector(63 downto 0);
signal ct_out_17 : std_logic_vector(63 downto 0);
signal ct_out_18 : std_logic_vector(63 downto 0);
signal ct_out_19 : std_logic_vector(63 downto 0);
signal ct_out_20 : std_logic_vector(63 downto 0);
signal ct_out_21 : std_logic_vector(63 downto 0);
signal ct_out_22 : std_logic_vector(63 downto 0);
signal ct_out_23 : std_logic_vector(63 downto 0);
signal ct_out_24 : std_logic_vector(63 downto 0);
signal ct_out_25 : std_logic_vector(63 downto 0);
signal ct_out_26 : std_logic_vector(63 downto 0);
signal ct_out_27 : std_logic_vector(63 downto 0);
signal ct_out_28 : std_logic_vector(63 downto 0);
signal ct_out_29 : std_logic_vector(63 downto 0);
signal ct_out_30 : std_logic_vector(63 downto 0);
signal ct_out_31 : std_logic_vector(63 downto 0);
signal ct_out_32 : std_logic_vector(63 downto 0);
signal ct_out_33 : std_logic_vector(63 downto 0);
signal ct_out_34 : std_logic_vector(63 downto 0);
signal ct_out_35 : std_logic_vector(63 downto 0);
signal ct_out_36 : std_logic_vector(63 downto 0);
signal ct_out_37 : std_logic_vector(63 downto 0);
signal ct_out_38 : std_logic_vector(63 downto 0);
signal ct_out_39 : std_logic_vector(63 downto 0);
signal ct_out_40 : std_logic_vector(63 downto 0);
signal ct_out_41 : std_logic_vector(63 downto 0);
signal ct_out_42 : std_logic_vector(63 downto 0);
begin
KEY_SCHEDULE_0 : key_schedule port map (
key_s(0), key_s(1), key_s(2), key_s(3),
k_0, k_1, k_2, k_3, k_4, k_5, k_6, k_7, k_8, k_9, k_10,
k_11, k_12, k_13, k_14, k_15, k_16, k_17, k_18, k_19, k_20,
k_21, k_22, k_23, k_24, k_25, k_26, k_27, k_28, k_29, k_30,
k_31, k_32, k_33, k_34, k_35, k_36, k_37, k_38, k_39, k_40,
k_41, k_42, k_43);
-- Outer-round registers
REG_STAGE_0 : reg_64 port map (clk, rst, ct_in_0, ct_out_0);
REG_STAGE_1 : reg_64 port map (clk, rst, ct_in_1, ct_out_1);
REG_STAGE_2 : reg_64 port map (clk, rst, ct_in_2, ct_out_2);
REG_STAGE_3 : reg_64 port map (clk, rst, ct_in_3, ct_out_3);
REG_STAGE_4 : reg_64 port map (clk, rst, ct_in_4, ct_out_4);
REG_STAGE_5 : reg_64 port map (clk, rst, ct_in_5, ct_out_5);
REG_STAGE_6 : reg_64 port map (clk, rst, ct_in_6, ct_out_6);
REG_STAGE_7 : reg_64 port map (clk, rst, ct_in_7, ct_out_7);
REG_STAGE_8 : reg_64 port map (clk, rst, ct_in_8, ct_out_8);
REG_STAGE_9 : reg_64 port map (clk, rst, ct_in_9, ct_out_9);
REG_STAGE_10 : reg_64 port map (clk, rst, ct_in_10, ct_out_10);
REG_STAGE_11 : reg_64 port map (clk, rst, ct_in_11, ct_out_11);
REG_STAGE_12 : reg_64 port map (clk, rst, ct_in_12, ct_out_12);
REG_STAGE_13 : reg_64 port map (clk, rst, ct_in_13, ct_out_13);
REG_STAGE_14 : reg_64 port map (clk, rst, ct_in_14, ct_out_14);
REG_STAGE_15 : reg_64 port map (clk, rst, ct_in_15, ct_out_15);
REG_STAGE_16 : reg_64 port map (clk, rst, ct_in_16, ct_out_16);
REG_STAGE_17 : reg_64 port map (clk, rst, ct_in_17, ct_out_17);
REG_STAGE_18 : reg_64 port map (clk, rst, ct_in_18, ct_out_18);
REG_STAGE_19 : reg_64 port map (clk, rst, ct_in_19, ct_out_19);
REG_STAGE_20 : reg_64 port map (clk, rst, ct_in_20, ct_out_20);
REG_STAGE_21 : reg_64 port map (clk, rst, ct_in_21, ct_out_21);
REG_STAGE_22 : reg_64 port map (clk, rst, ct_in_22, ct_out_22);
REG_STAGE_23 : reg_64 port map (clk, rst, ct_in_23, ct_out_23);
REG_STAGE_24 : reg_64 port map (clk, rst, ct_in_24, ct_out_24);
REG_STAGE_25 : reg_64 port map (clk, rst, ct_in_25, ct_out_25);
REG_STAGE_26 : reg_64 port map (clk, rst, ct_in_26, ct_out_26);
REG_STAGE_27 : reg_64 port map (clk, rst, ct_in_27, ct_out_27);
REG_STAGE_28 : reg_64 port map (clk, rst, ct_in_28, ct_out_28);
REG_STAGE_29 : reg_64 port map (clk, rst, ct_in_29, ct_out_29);
REG_STAGE_30 : reg_64 port map (clk, rst, ct_in_30, ct_out_30);
REG_STAGE_31 : reg_64 port map (clk, rst, ct_in_31, ct_out_31);
REG_STAGE_32 : reg_64 port map (clk, rst, ct_in_32, ct_out_32);
REG_STAGE_33 : reg_64 port map (clk, rst, ct_in_33, ct_out_33);
REG_STAGE_34 : reg_64 port map (clk, rst, ct_in_34, ct_out_34);
REG_STAGE_35 : reg_64 port map (clk, rst, ct_in_35, ct_out_35);
REG_STAGE_36 : reg_64 port map (clk, rst, ct_in_36, ct_out_36);
REG_STAGE_37 : reg_64 port map (clk, rst, ct_in_37, ct_out_37);
REG_STAGE_38 : reg_64 port map (clk, rst, ct_in_38, ct_out_38);
REG_STAGE_39 : reg_64 port map (clk, rst, ct_in_39, ct_out_39);
REG_STAGE_40 : reg_64 port map (clk, rst, ct_in_40, ct_out_40);
REG_STAGE_41 : reg_64 port map (clk, rst, ct_in_41, ct_out_41);
REG_STAGE_42 : reg_64 port map (clk, rst, ct_in_42, ct_out_42);
-- round function combinatorial logic
ROUND_F_0 : round_f port map (clk, rst, enc, block_in, k_0, k_43, ct_in_0);
ROUND_F_1 : round_f port map (clk, rst, enc, ct_out_0, k_1, k_42, ct_in_1);
ROUND_F_2 : round_f port map (clk, rst, enc, ct_out_1, k_2, k_41, ct_in_2);
ROUND_F_3 : round_f port map (clk, rst, enc, ct_out_2, k_3, k_40, ct_in_3);
ROUND_F_4 : round_f port map (clk, rst, enc, ct_out_3, k_4, k_39, ct_in_4);
ROUND_F_5 : round_f port map (clk, rst, enc, ct_out_4, k_5, k_38, ct_in_5);
ROUND_F_6 : round_f port map (clk, rst, enc, ct_out_5, k_6, k_37, ct_in_6);
ROUND_F_7 : round_f port map (clk, rst, enc, ct_out_6, k_7, k_36, ct_in_7);
ROUND_F_8 : round_f port map (clk, rst, enc, ct_out_7, k_8, k_35, ct_in_8);
ROUND_F_9 : round_f port map (clk, rst, enc, ct_out_8, k_9, k_34, ct_in_9);
ROUND_F_10 : round_f port map (clk, rst, enc, ct_out_9, k_10, k_33, ct_in_10);
ROUND_F_11 : round_f port map (clk, rst, enc, ct_out_10, k_11, k_32, ct_in_11);
ROUND_F_12 : round_f port map (clk, rst, enc, ct_out_11, k_12, k_31, ct_in_12);
ROUND_F_13 : round_f port map (clk, rst, enc, ct_out_12, k_13, k_30, ct_in_13);
ROUND_F_14 : round_f port map (clk, rst, enc, ct_out_13, k_14, k_29, ct_in_14);
ROUND_F_15 : round_f port map (clk, rst, enc, ct_out_14, k_15, k_28, ct_in_15);
ROUND_F_16 : round_f port map (clk, rst, enc, ct_out_15, k_16, k_27, ct_in_16);
ROUND_F_17 : round_f port map (clk, rst, enc, ct_out_16, k_17, k_26, ct_in_17);
ROUND_F_18 : round_f port map (clk, rst, enc, ct_out_17, k_18, k_25, ct_in_18);
ROUND_F_19 : round_f port map (clk, rst, enc, ct_out_18, k_19, k_24, ct_in_19);
ROUND_F_20 : round_f port map (clk, rst, enc, ct_out_19, k_20, k_23, ct_in_20);
ROUND_F_21 : round_f port map (clk, rst, enc, ct_out_20, k_21, k_22, ct_in_21);
ROUND_F_22 : round_f port map (clk, rst, enc, ct_out_21, k_22, k_21, ct_in_22);
ROUND_F_23 : round_f port map (clk, rst, enc, ct_out_22, k_23, k_20, ct_in_23);
ROUND_F_24 : round_f port map (clk, rst, enc, ct_out_23, k_24, k_19, ct_in_24);
ROUND_F_25 : round_f port map (clk, rst, enc, ct_out_24, k_25, k_18, ct_in_25);
ROUND_F_26 : round_f port map (clk, rst, enc, ct_out_25, k_26, k_17, ct_in_26);
ROUND_F_27 : round_f port map (clk, rst, enc, ct_out_26, k_27, k_16, ct_in_27);
ROUND_F_28 : round_f port map (clk, rst, enc, ct_out_27, k_28, k_15, ct_in_28);
ROUND_F_29 : round_f port map (clk, rst, enc, ct_out_28, k_29, k_14, ct_in_29);
ROUND_F_30 : round_f port map (clk, rst, enc, ct_out_29, k_30, k_13, ct_in_30);
ROUND_F_31 : round_f port map (clk, rst, enc, ct_out_30, k_31, k_12, ct_in_31);
ROUND_F_32 : round_f port map (clk, rst, enc, ct_out_31, k_32, k_11, ct_in_32);
ROUND_F_33 : round_f port map (clk, rst, enc, ct_out_32, k_33, k_10, ct_in_33);
ROUND_F_34 : round_f port map (clk, rst, enc, ct_out_33, k_34, k_9, ct_in_34);
ROUND_F_35 : round_f port map (clk, rst, enc, ct_out_34, k_35, k_8, ct_in_35);
ROUND_F_36 : round_f port map (clk, rst, enc, ct_out_35, k_36, k_7, ct_in_36);
ROUND_F_37 : round_f port map (clk, rst, enc, ct_out_36, k_37, k_6, ct_in_37);
ROUND_F_38 : round_f port map (clk, rst, enc, ct_out_37, k_38, k_5, ct_in_38);
ROUND_F_39 : round_f port map (clk, rst, enc, ct_out_38, k_39, k_4, ct_in_39);
ROUND_F_40 : round_f port map (clk, rst, enc, ct_out_39, k_40, k_3, ct_in_40);
ROUND_F_41 : round_f port map (clk, rst, enc, ct_out_40, k_41, k_2, ct_in_41);
ROUND_F_42 : round_f port map (clk, rst, enc, ct_out_41, k_42, k_1, ct_in_42);
ROUND_F_43 : round_f port map (clk, rst, enc, ct_out_42, k_43, k_0, ct_in_43);
block_out <= ct_in_43;
-- SIMON Core
pr_smn : process(clk, rst, enc, key, key_s)
begin
key_s(0) <= key(31 downto 0);
key_s(1) <= key(63 downto 32);
key_s(2) <= key(95 downto 64);
key_s(3) <= key(127 downto 96);
end process;
end Behavioral; |
---------------------------------------------------------------------
--
-- Inputs: a, b, c, d, e, f, g, h
-- Output(s): i
-- Expressions:
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
--
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity test_me_tb is
end test_me_tb;
architecture test_me of test_me_tb is
component input
port
(
a, b, c, d, e, f, g, h : IN std_logic_vector(3 downto 0);
i : OUT std_logic_vector(3 downto 0);
clear, clock, s_tart : IN std_logic;
finish : OUT std_logic
);
end component;
for all : input use entity work.input(rtl2);
signal a, b, c, d, e, f, g, h, i : std_logic_vector(3 downto 0) := "0000";
signal clear, clock, finish, s_tart : std_logic := '0';
begin
test_input : input port map (a, b, c, d, e, f, g, h, i, clear, clock, s_tart, finish);
process
begin
wait for 1 ns;
-- i = f(a, b, c, d, e, f, g, h) = (a * b * c * d) - h - (g * e * f)
a <= "0010"; -- 2
b <= "0001"; -- 1
c <= "0010"; -- 2
d <= "0011"; -- 3
e <= "0010"; -- 2
f <= "0001"; -- 1
g <= "0010"; -- 2
h <= "0010"; -- 2
s_tart <= '1';
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
clock <= '1'; wait for 1 ns;
clock <= '0'; wait for 1 ns;
assert i = "0110" report "6 = f(2, 1, 2, 3, 2, 1, 2, 2) = (2 * 1 * 2 * 3) - 2 - (2 * 2 * 1)" severity failure;
wait;
end process;
end test_me;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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OHsAQlQrGQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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bEZhoOjusaup1X0FHY/TyHvEOtnrmxkvUbgz/AADykySrHfeBuy9o4w6mTwNtwt3pA89GcwboOkr
JkpQAt7nw4fkkhAyTfc=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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AM1ots6l23wy6+TedhXNPMZT3shd8Aqdd72tiQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
laGbLjwbjeJ1P3UPtdUe8LiEuGpWKHEVwa544tFk/WzaSeDZUP8esXw2yz3buTctc7mh1fzEY9+o
N97yXaK4J9AcDNwdHHYH2S4sBrwcfNTya/74ZgAv6uCuxGdE+mVkA3GrxAqqhpZNNxKraDRWyANg
Oy//2H3bg1BanfGhiKY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
YA3+3LIscFTVnZVQYgOsy0z/8EI1v6llbJTY4+K+4uMKcgjoOQChRSbjSaPlytPIarA91jLeXkjn
AhS4WEvP9h3hba7q2LF0VFWgsq2r9NlTd2j0SVKTI5lBk+xTppM+K8Ho5OoKU3pPf2Bhk/g5T/bj
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opuVyTiKR9iScBaZqVCCWRvZHlAO49kzJot0eA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15616)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15616)
`protect data_block
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`protect end_protected
|
--
-- Copyright (C) 2009-2012 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity producer is
port(
clk_in : in std_logic;
data_out : out std_logic_vector(7 downto 0);
write_out : out std_logic;
full_in : in std_logic;
trigger_in : in std_logic;
count_in : in unsigned(31 downto 0);
alarm_out : out std_logic;
ch_in : in std_logic
--ch_in : in std_logic_vector(1 downto 0)
);
end producer;
architecture behavioural of producer is
type StateType is (
STATE_IDLE,
STATE_GET0,
STATE_GET1,
STATE_GET2,
STATE_GET3
);
signal state, state_next : StateType := STATE_IDLE;
signal count, count_next : unsigned(31 downto 0); -- Write count
signal alarm, alarm_next : std_logic := '0';
signal chanBits, chanBits_next : std_logic_vector(5 downto 0) := "000000";
signal ch_sync1 : std_logic;
signal ch_sync2 : std_logic;
signal ch_sync3 : std_logic;
--signal ch_sync1 : std_logic_vector(1 downto 0) := "00";
--signal ch_sync2 : std_logic_vector(1 downto 0) := "00";
--signal ch_sync3 : std_logic_vector(1 downto 0) := "00";
--signal ch, ch_next : std_logic_vector(1 downto 0) := "00";
begin
process(clk_in)
begin
if ( rising_edge(clk_in) ) then
state <= state_next;
count <= count_next;
alarm <= alarm_next;
chanBits <= chanBits_next;
ch_sync1 <= ch_in;
ch_sync2 <= ch_sync1;
ch_sync3 <= ch_sync2;
--ch <= ch_next;
end if;
end process;
--ch_next <=
-- ch_sync2 when ch_sync1 = ch_sync2 and ch_sync2 = ch_sync3 else
-- ch;
alarm_next <=
'1' when full_in = '1'
else alarm;
alarm_out <= alarm;
process(state, count, chanBits, ch_sync2, ch_sync3, count_in, trigger_in)
begin
state_next <= state;
count_next <= count;
write_out <= '0';
chanBits_next <= chanBits;
data_out <= (others => '0');
case state is
when STATE_GET0 =>
chanBits_next(1 downto 0) <= ch_sync2 & ch_sync3;
state_next <= STATE_GET1;
when STATE_GET1 =>
chanBits_next(3 downto 2) <= ch_sync2 & ch_sync3;
state_next <= STATE_GET2;
when STATE_GET2 =>
chanBits_next(5 downto 4) <= ch_sync2 & ch_sync3;
state_next <= STATE_GET3;
when STATE_GET3 =>
--data_out <= std_logic_vector(count(7 downto 0));
data_out <= ch_sync2 & ch_sync3 & chanBits;
write_out <= '1';
count_next <= count - 1;
if ( count = 1 ) then
state_next <= STATE_IDLE;
else
state_next <= STATE_GET0;
end if;
-- STATE_IDLE and others
when others =>
if ( trigger_in = '1' ) then
state_next <= STATE_GET0;
count_next <= count_in;
end if;
end case;
end process;
end behavioural;
|
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity test_s_box is
end test_s_box;
architecture behavior of test_s_box is
signal data_in: std_logic_vector(0 to 47);
signal data_out: std_logic_vector(0 to 31);
begin
uut: entity s_box port map(data_in, data_out);
testprocess: process is
begin
data_in<="000010000000000000000000000000000000000000000000";
wait for 10 ns;
end process testprocess;
end architecture behavior;
|
-------------------------------------------------------------------------------
-- lmb_mux.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_mux.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_mux.vhd
-- pselct_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end entity lmb_mux;
architecture imp of lmb_mux is
component pselect_mask
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := X"00000000";
C_MASK : std_logic_vector(0 to 31) := X"00800000");
port (
A : in std_logic_vector(0 to 31);
CS : out std_logic;
Valid : in std_logic);
end component;
signal one : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
LMB1_no: if (C_NUM_LMB < 2) generate
Sl1_DBus <= (others => '0');
Sl1_Ready <= '0';
Sl1_Wait <= '0';
Sl1_UE <= '0';
Sl1_CE <= '0';
end generate LMB1_no;
LMB2_no: if (C_NUM_LMB < 3) generate
Sl2_DBus <= (others => '0');
Sl2_Ready <= '0';
Sl2_Wait <= '0';
Sl2_UE <= '0';
Sl2_CE <= '0';
end generate LMB2_no;
LMB3_no: if (C_NUM_LMB < 4) generate
Sl3_DBus <= (others => '0');
Sl3_Ready <= '0';
Sl3_Wait <= '0';
Sl3_UE <= '0';
Sl3_CE <= '0';
end generate LMB3_no;
one <= '1';
one_lmb: if (C_NUM_LMB = 1) generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_MASK)
port map (
A => LMB0_ABus,
CS => lmb_select,
Valid => one);
LMB_ABus <= LMB0_ABus;
LMB_WriteDBus <= LMB0_WriteDBus;
LMB_AddrStrobe <= LMB0_AddrStrobe;
LMB_ReadStrobe <= LMB0_ReadStrobe;
LMB_WriteStrobe <= LMB0_WriteStrobe;
LMB_BE <= LMB0_BE;
Sl0_DBus <= Sl_DBus;
Sl0_Ready <= Sl_Ready;
Sl0_Wait <= Sl_Wait;
Sl0_UE <= Sl_UE;
Sl0_CE <= Sl_CE;
end generate one_lmb;
more_than_one_lmb: if (C_NUM_LMB > 1) generate
type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 31);
constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1);
type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1);
type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
signal LMB_ABus_vec : ABus_vec_T;
signal LMB_ABus_vec_i : ABus_vec_T;
signal LMB_ABus_vec_Q : ABus_vec_T;
signal LMB_WriteDBus_vec : DBus_vec_T;
signal LMB_WriteDBus_vec_i : DBus_vec_T;
signal LMB_WriteDBus_vec_Q : DBus_vec_T;
signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_BE_vec : BE_vec_T;
signal LMB_BE_vec_i : BE_vec_T;
signal LMB_BE_vec_Q : BE_vec_T;
signal Sl_DBus_vec : DBus_vec_T;
signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal ongoing : natural range 0 to C_NUM_LMB-1;
signal ongoing_new : natural range 0 to C_NUM_LMB-1;
signal ongoing_Q : natural range 0 to C_NUM_LMB-1;
begin
LMB_ABus_vec(0) <= LMB0_ABus;
LMB_WriteDBus_vec(0) <= LMB0_WriteDBus;
LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe;
LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe;
LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
LMB_BE_vec(0) <= LMB0_BE;
Sl0_DBus <= Sl_DBus_vec(0);
Sl0_Ready <= Sl_Ready_vec(0);
Sl0_Wait <= Sl_Wait_vec(0);
Sl0_UE <= Sl_UE_vec(0);
Sl0_CE <= Sl_CE_vec(0);
LMB_ABus_vec(1) <= LMB1_ABus;
LMB_WriteDBus_vec(1) <= LMB1_WriteDBus;
LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe;
LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe;
LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
LMB_BE_vec(1) <= LMB1_BE;
Sl1_DBus <= Sl_DBus_vec(1);
Sl1_Ready <= Sl_Ready_vec(1);
Sl1_Wait <= Sl_Wait_vec(1);
Sl1_UE <= Sl_UE_vec(1);
Sl1_CE <= Sl_CE_vec(1);
LMB2_yes: if (C_NUM_LMB > 2) generate
LMB_ABus_vec(2) <= LMB2_ABus;
LMB_WriteDBus_vec(2) <= LMB2_WriteDBus;
LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe;
LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe;
LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
LMB_BE_vec(2) <= LMB2_BE;
Sl2_DBus <= Sl_DBus_vec(2);
Sl2_Ready <= Sl_Ready_vec(2);
Sl2_Wait <= Sl_Wait_vec(2);
Sl2_UE <= Sl_UE_vec(2);
Sl2_CE <= Sl_CE_vec(2);
end generate LMB2_yes;
LMB3_yes: if (C_NUM_LMB > 3) generate
LMB_ABus_vec(3) <= LMB3_ABus;
LMB_WriteDBus_vec(3) <= LMB3_WriteDBus;
LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe;
LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe;
LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
LMB_BE_vec(3) <= LMB3_BE;
Sl3_DBus <= Sl_DBus_vec(3);
Sl3_Ready <= Sl_Ready_vec(3);
Sl3_Wait <= Sl_Wait_vec(3);
Sl3_UE <= Sl_UE_vec(3);
Sl3_CE <= Sl_CE_vec(3);
end generate LMB3_yes;
lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_Mask_Vec(I))
port map (
A => LMB_ABus_vec(I),
CS => lmb_select_vec(I),
Valid => one);
as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
remember_access : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
LMB_ABus_vec_Q(I) <= (others => '0');
LMB_WriteDBus_vec_Q(I) <= (others => '0');
LMB_AddrStrobe_vec_Q(I) <= '0';
LMB_ReadStrobe_vec_Q(I) <= '0';
LMB_WriteStrobe_vec_Q(I) <= '0';
LMB_BE_vec_Q(I) <= (others => '0');
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I);
LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
LMB_BE_vec_Q(I) <= LMB_BE_vec(I);
end if;
end if;
end process remember_access;
wait_proc : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
wait_vec(I) <= '0';
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
wait_vec(I) <= '1';
elsif (wait_vec(I) = '1' and ongoing = I) then
wait_vec(I) <= '0';
end if;
end if;
end process wait_proc;
LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
LMB_ABus_vec(I);
LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteStrobe_vec(I);
LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
LMB_BE_vec(I);
-- Assign selected LMB from internal signals
Sl_DBus_vec(I) <= Sl_DBus;
Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
'0';
Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else
wait_vec(I);
Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else
'0';
Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else
'0';
end generate lmb_mux_generate;
OnGoing_Reg : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
ongoing_Q <= 0;
else
ongoing_Q <= ongoing;
end if;
end if;
end process OnGoing_Reg;
Arbit : process (as_and_lmb_select_vec, wait_vec) is
variable N : natural range 0 to C_NUM_LMB-1;
begin
ongoing_new <= 0;
for N in 0 to C_NUM_LMB - 1 loop
if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
ongoing_new <= N;
exit;
end if;
end loop;
end process Arbit;
ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
ongoing_new;
-- Assign selected LMB
LMB_ABus <= LMB_ABus_vec_i(ongoing);
LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing);
LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing);
LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing);
LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
LMB_BE <= LMB_BE_vec_i(ongoing);
lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing);
end generate more_than_one_lmb;
end imp;
|
-------------------------------------------------------------------------------
-- lmb_mux.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_mux.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_mux.vhd
-- pselct_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end entity lmb_mux;
architecture imp of lmb_mux is
component pselect_mask
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := X"00000000";
C_MASK : std_logic_vector(0 to 31) := X"00800000");
port (
A : in std_logic_vector(0 to 31);
CS : out std_logic;
Valid : in std_logic);
end component;
signal one : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
LMB1_no: if (C_NUM_LMB < 2) generate
Sl1_DBus <= (others => '0');
Sl1_Ready <= '0';
Sl1_Wait <= '0';
Sl1_UE <= '0';
Sl1_CE <= '0';
end generate LMB1_no;
LMB2_no: if (C_NUM_LMB < 3) generate
Sl2_DBus <= (others => '0');
Sl2_Ready <= '0';
Sl2_Wait <= '0';
Sl2_UE <= '0';
Sl2_CE <= '0';
end generate LMB2_no;
LMB3_no: if (C_NUM_LMB < 4) generate
Sl3_DBus <= (others => '0');
Sl3_Ready <= '0';
Sl3_Wait <= '0';
Sl3_UE <= '0';
Sl3_CE <= '0';
end generate LMB3_no;
one <= '1';
one_lmb: if (C_NUM_LMB = 1) generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_MASK)
port map (
A => LMB0_ABus,
CS => lmb_select,
Valid => one);
LMB_ABus <= LMB0_ABus;
LMB_WriteDBus <= LMB0_WriteDBus;
LMB_AddrStrobe <= LMB0_AddrStrobe;
LMB_ReadStrobe <= LMB0_ReadStrobe;
LMB_WriteStrobe <= LMB0_WriteStrobe;
LMB_BE <= LMB0_BE;
Sl0_DBus <= Sl_DBus;
Sl0_Ready <= Sl_Ready;
Sl0_Wait <= Sl_Wait;
Sl0_UE <= Sl_UE;
Sl0_CE <= Sl_CE;
end generate one_lmb;
more_than_one_lmb: if (C_NUM_LMB > 1) generate
type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 31);
constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1);
type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1);
type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
signal LMB_ABus_vec : ABus_vec_T;
signal LMB_ABus_vec_i : ABus_vec_T;
signal LMB_ABus_vec_Q : ABus_vec_T;
signal LMB_WriteDBus_vec : DBus_vec_T;
signal LMB_WriteDBus_vec_i : DBus_vec_T;
signal LMB_WriteDBus_vec_Q : DBus_vec_T;
signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_BE_vec : BE_vec_T;
signal LMB_BE_vec_i : BE_vec_T;
signal LMB_BE_vec_Q : BE_vec_T;
signal Sl_DBus_vec : DBus_vec_T;
signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal ongoing : natural range 0 to C_NUM_LMB-1;
signal ongoing_new : natural range 0 to C_NUM_LMB-1;
signal ongoing_Q : natural range 0 to C_NUM_LMB-1;
begin
LMB_ABus_vec(0) <= LMB0_ABus;
LMB_WriteDBus_vec(0) <= LMB0_WriteDBus;
LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe;
LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe;
LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
LMB_BE_vec(0) <= LMB0_BE;
Sl0_DBus <= Sl_DBus_vec(0);
Sl0_Ready <= Sl_Ready_vec(0);
Sl0_Wait <= Sl_Wait_vec(0);
Sl0_UE <= Sl_UE_vec(0);
Sl0_CE <= Sl_CE_vec(0);
LMB_ABus_vec(1) <= LMB1_ABus;
LMB_WriteDBus_vec(1) <= LMB1_WriteDBus;
LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe;
LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe;
LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
LMB_BE_vec(1) <= LMB1_BE;
Sl1_DBus <= Sl_DBus_vec(1);
Sl1_Ready <= Sl_Ready_vec(1);
Sl1_Wait <= Sl_Wait_vec(1);
Sl1_UE <= Sl_UE_vec(1);
Sl1_CE <= Sl_CE_vec(1);
LMB2_yes: if (C_NUM_LMB > 2) generate
LMB_ABus_vec(2) <= LMB2_ABus;
LMB_WriteDBus_vec(2) <= LMB2_WriteDBus;
LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe;
LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe;
LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
LMB_BE_vec(2) <= LMB2_BE;
Sl2_DBus <= Sl_DBus_vec(2);
Sl2_Ready <= Sl_Ready_vec(2);
Sl2_Wait <= Sl_Wait_vec(2);
Sl2_UE <= Sl_UE_vec(2);
Sl2_CE <= Sl_CE_vec(2);
end generate LMB2_yes;
LMB3_yes: if (C_NUM_LMB > 3) generate
LMB_ABus_vec(3) <= LMB3_ABus;
LMB_WriteDBus_vec(3) <= LMB3_WriteDBus;
LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe;
LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe;
LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
LMB_BE_vec(3) <= LMB3_BE;
Sl3_DBus <= Sl_DBus_vec(3);
Sl3_Ready <= Sl_Ready_vec(3);
Sl3_Wait <= Sl_Wait_vec(3);
Sl3_UE <= Sl_UE_vec(3);
Sl3_CE <= Sl_CE_vec(3);
end generate LMB3_yes;
lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_Mask_Vec(I))
port map (
A => LMB_ABus_vec(I),
CS => lmb_select_vec(I),
Valid => one);
as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
remember_access : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
LMB_ABus_vec_Q(I) <= (others => '0');
LMB_WriteDBus_vec_Q(I) <= (others => '0');
LMB_AddrStrobe_vec_Q(I) <= '0';
LMB_ReadStrobe_vec_Q(I) <= '0';
LMB_WriteStrobe_vec_Q(I) <= '0';
LMB_BE_vec_Q(I) <= (others => '0');
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I);
LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
LMB_BE_vec_Q(I) <= LMB_BE_vec(I);
end if;
end if;
end process remember_access;
wait_proc : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
wait_vec(I) <= '0';
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
wait_vec(I) <= '1';
elsif (wait_vec(I) = '1' and ongoing = I) then
wait_vec(I) <= '0';
end if;
end if;
end process wait_proc;
LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
LMB_ABus_vec(I);
LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteStrobe_vec(I);
LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
LMB_BE_vec(I);
-- Assign selected LMB from internal signals
Sl_DBus_vec(I) <= Sl_DBus;
Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
'0';
Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else
wait_vec(I);
Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else
'0';
Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else
'0';
end generate lmb_mux_generate;
OnGoing_Reg : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
ongoing_Q <= 0;
else
ongoing_Q <= ongoing;
end if;
end if;
end process OnGoing_Reg;
Arbit : process (as_and_lmb_select_vec, wait_vec) is
variable N : natural range 0 to C_NUM_LMB-1;
begin
ongoing_new <= 0;
for N in 0 to C_NUM_LMB - 1 loop
if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
ongoing_new <= N;
exit;
end if;
end loop;
end process Arbit;
ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
ongoing_new;
-- Assign selected LMB
LMB_ABus <= LMB_ABus_vec_i(ongoing);
LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing);
LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing);
LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing);
LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
LMB_BE <= LMB_BE_vec_i(ongoing);
lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing);
end generate more_than_one_lmb;
end imp;
|
-------------------------------------------------------------------------------
-- lmb_mux.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_mux.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_mux.vhd
-- pselct_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end entity lmb_mux;
architecture imp of lmb_mux is
component pselect_mask
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := X"00000000";
C_MASK : std_logic_vector(0 to 31) := X"00800000");
port (
A : in std_logic_vector(0 to 31);
CS : out std_logic;
Valid : in std_logic);
end component;
signal one : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
LMB1_no: if (C_NUM_LMB < 2) generate
Sl1_DBus <= (others => '0');
Sl1_Ready <= '0';
Sl1_Wait <= '0';
Sl1_UE <= '0';
Sl1_CE <= '0';
end generate LMB1_no;
LMB2_no: if (C_NUM_LMB < 3) generate
Sl2_DBus <= (others => '0');
Sl2_Ready <= '0';
Sl2_Wait <= '0';
Sl2_UE <= '0';
Sl2_CE <= '0';
end generate LMB2_no;
LMB3_no: if (C_NUM_LMB < 4) generate
Sl3_DBus <= (others => '0');
Sl3_Ready <= '0';
Sl3_Wait <= '0';
Sl3_UE <= '0';
Sl3_CE <= '0';
end generate LMB3_no;
one <= '1';
one_lmb: if (C_NUM_LMB = 1) generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_MASK)
port map (
A => LMB0_ABus,
CS => lmb_select,
Valid => one);
LMB_ABus <= LMB0_ABus;
LMB_WriteDBus <= LMB0_WriteDBus;
LMB_AddrStrobe <= LMB0_AddrStrobe;
LMB_ReadStrobe <= LMB0_ReadStrobe;
LMB_WriteStrobe <= LMB0_WriteStrobe;
LMB_BE <= LMB0_BE;
Sl0_DBus <= Sl_DBus;
Sl0_Ready <= Sl_Ready;
Sl0_Wait <= Sl_Wait;
Sl0_UE <= Sl_UE;
Sl0_CE <= Sl_CE;
end generate one_lmb;
more_than_one_lmb: if (C_NUM_LMB > 1) generate
type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 31);
constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1);
type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1);
type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
signal LMB_ABus_vec : ABus_vec_T;
signal LMB_ABus_vec_i : ABus_vec_T;
signal LMB_ABus_vec_Q : ABus_vec_T;
signal LMB_WriteDBus_vec : DBus_vec_T;
signal LMB_WriteDBus_vec_i : DBus_vec_T;
signal LMB_WriteDBus_vec_Q : DBus_vec_T;
signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_BE_vec : BE_vec_T;
signal LMB_BE_vec_i : BE_vec_T;
signal LMB_BE_vec_Q : BE_vec_T;
signal Sl_DBus_vec : DBus_vec_T;
signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal ongoing : natural range 0 to C_NUM_LMB-1;
signal ongoing_new : natural range 0 to C_NUM_LMB-1;
signal ongoing_Q : natural range 0 to C_NUM_LMB-1;
begin
LMB_ABus_vec(0) <= LMB0_ABus;
LMB_WriteDBus_vec(0) <= LMB0_WriteDBus;
LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe;
LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe;
LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
LMB_BE_vec(0) <= LMB0_BE;
Sl0_DBus <= Sl_DBus_vec(0);
Sl0_Ready <= Sl_Ready_vec(0);
Sl0_Wait <= Sl_Wait_vec(0);
Sl0_UE <= Sl_UE_vec(0);
Sl0_CE <= Sl_CE_vec(0);
LMB_ABus_vec(1) <= LMB1_ABus;
LMB_WriteDBus_vec(1) <= LMB1_WriteDBus;
LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe;
LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe;
LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
LMB_BE_vec(1) <= LMB1_BE;
Sl1_DBus <= Sl_DBus_vec(1);
Sl1_Ready <= Sl_Ready_vec(1);
Sl1_Wait <= Sl_Wait_vec(1);
Sl1_UE <= Sl_UE_vec(1);
Sl1_CE <= Sl_CE_vec(1);
LMB2_yes: if (C_NUM_LMB > 2) generate
LMB_ABus_vec(2) <= LMB2_ABus;
LMB_WriteDBus_vec(2) <= LMB2_WriteDBus;
LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe;
LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe;
LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
LMB_BE_vec(2) <= LMB2_BE;
Sl2_DBus <= Sl_DBus_vec(2);
Sl2_Ready <= Sl_Ready_vec(2);
Sl2_Wait <= Sl_Wait_vec(2);
Sl2_UE <= Sl_UE_vec(2);
Sl2_CE <= Sl_CE_vec(2);
end generate LMB2_yes;
LMB3_yes: if (C_NUM_LMB > 3) generate
LMB_ABus_vec(3) <= LMB3_ABus;
LMB_WriteDBus_vec(3) <= LMB3_WriteDBus;
LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe;
LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe;
LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
LMB_BE_vec(3) <= LMB3_BE;
Sl3_DBus <= Sl_DBus_vec(3);
Sl3_Ready <= Sl_Ready_vec(3);
Sl3_Wait <= Sl_Wait_vec(3);
Sl3_UE <= Sl_UE_vec(3);
Sl3_CE <= Sl_CE_vec(3);
end generate LMB3_yes;
lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_Mask_Vec(I))
port map (
A => LMB_ABus_vec(I),
CS => lmb_select_vec(I),
Valid => one);
as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
remember_access : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
LMB_ABus_vec_Q(I) <= (others => '0');
LMB_WriteDBus_vec_Q(I) <= (others => '0');
LMB_AddrStrobe_vec_Q(I) <= '0';
LMB_ReadStrobe_vec_Q(I) <= '0';
LMB_WriteStrobe_vec_Q(I) <= '0';
LMB_BE_vec_Q(I) <= (others => '0');
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I);
LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
LMB_BE_vec_Q(I) <= LMB_BE_vec(I);
end if;
end if;
end process remember_access;
wait_proc : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
wait_vec(I) <= '0';
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
wait_vec(I) <= '1';
elsif (wait_vec(I) = '1' and ongoing = I) then
wait_vec(I) <= '0';
end if;
end if;
end process wait_proc;
LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
LMB_ABus_vec(I);
LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteStrobe_vec(I);
LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
LMB_BE_vec(I);
-- Assign selected LMB from internal signals
Sl_DBus_vec(I) <= Sl_DBus;
Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
'0';
Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else
wait_vec(I);
Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else
'0';
Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else
'0';
end generate lmb_mux_generate;
OnGoing_Reg : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
ongoing_Q <= 0;
else
ongoing_Q <= ongoing;
end if;
end if;
end process OnGoing_Reg;
Arbit : process (as_and_lmb_select_vec, wait_vec) is
variable N : natural range 0 to C_NUM_LMB-1;
begin
ongoing_new <= 0;
for N in 0 to C_NUM_LMB - 1 loop
if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
ongoing_new <= N;
exit;
end if;
end loop;
end process Arbit;
ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
ongoing_new;
-- Assign selected LMB
LMB_ABus <= LMB_ABus_vec_i(ongoing);
LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing);
LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing);
LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing);
LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
LMB_BE <= LMB_BE_vec_i(ongoing);
lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing);
end generate more_than_one_lmb;
end imp;
|
-------------------------------------------------------------------------------
-- lmb_mux.vhd - Entity and architecture
-------------------------------------------------------------------------------
--
-- (c) Copyright [2003] - [2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES
--
------------------------------------------------------------------------------
-- Filename: lmb_mux.vhd
--
-- Description:
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- lmb_mux.vhd
-- pselct_mask.vhd
--
-------------------------------------------------------------------------------
-- Author: rolandp
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity lmb_mux is
generic (
C_BASEADDR : std_logic_vector(0 to 31) := X"FFFFFFFF";
C_MASK : std_logic_vector(0 to 31) := X"00800000";
C_MASK1 : std_logic_vector(0 to 31) := X"00800000";
C_MASK2 : std_logic_vector(0 to 31) := X"00800000";
C_MASK3 : std_logic_vector(0 to 31) := X"00800000";
C_LMB_AWIDTH : integer := 32;
C_LMB_DWIDTH : integer := 32;
C_NUM_LMB : integer := 1);
port (
LMB_Clk : in std_logic := '0';
LMB_Rst : in std_logic := '0';
-- LMB Bus 0
LMB0_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB0_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB0_AddrStrobe : in std_logic;
LMB0_ReadStrobe : in std_logic;
LMB0_WriteStrobe : in std_logic;
LMB0_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl0_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl0_Ready : out std_logic;
Sl0_Wait : out std_logic;
Sl0_UE : out std_logic;
Sl0_CE : out std_logic;
-- LMB Bus 1
LMB1_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB1_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB1_AddrStrobe : in std_logic;
LMB1_ReadStrobe : in std_logic;
LMB1_WriteStrobe : in std_logic;
LMB1_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl1_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl1_Ready : out std_logic;
Sl1_Wait : out std_logic;
Sl1_UE : out std_logic;
Sl1_CE : out std_logic;
-- LMB Bus 2
LMB2_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB2_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB2_AddrStrobe : in std_logic;
LMB2_ReadStrobe : in std_logic;
LMB2_WriteStrobe : in std_logic;
LMB2_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl2_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl2_Ready : out std_logic;
Sl2_Wait : out std_logic;
Sl2_UE : out std_logic;
Sl2_CE : out std_logic;
-- LMB Bus 3
LMB3_ABus : in std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB3_WriteDBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB3_AddrStrobe : in std_logic;
LMB3_ReadStrobe : in std_logic;
LMB3_WriteStrobe : in std_logic;
LMB3_BE : in std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl3_DBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl3_Ready : out std_logic;
Sl3_Wait : out std_logic;
Sl3_UE : out std_logic;
Sl3_CE : out std_logic;
-- Muxed LMB Bus
LMB_ABus : out std_logic_vector(0 to C_LMB_AWIDTH-1);
LMB_WriteDBus : out std_logic_vector(0 to C_LMB_DWIDTH-1);
LMB_AddrStrobe : out std_logic;
LMB_ReadStrobe : out std_logic;
LMB_WriteStrobe : out std_logic;
LMB_BE : out std_logic_vector(0 to (C_LMB_DWIDTH/8 - 1));
Sl_DBus : in std_logic_vector(0 to C_LMB_DWIDTH-1);
Sl_Ready : in std_logic;
Sl_Wait : in std_logic;
Sl_UE : in std_logic;
Sl_CE : in std_logic;
lmb_select : out std_logic);
end entity lmb_mux;
architecture imp of lmb_mux is
component pselect_mask
generic (
C_AW : integer := 32;
C_BAR : std_logic_vector(0 to 31) := X"00000000";
C_MASK : std_logic_vector(0 to 31) := X"00800000");
port (
A : in std_logic_vector(0 to 31);
CS : out std_logic;
Valid : in std_logic);
end component;
signal one : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture section
-------------------------------------------------------------------------------
begin -- VHDL_RTL
LMB1_no: if (C_NUM_LMB < 2) generate
Sl1_DBus <= (others => '0');
Sl1_Ready <= '0';
Sl1_Wait <= '0';
Sl1_UE <= '0';
Sl1_CE <= '0';
end generate LMB1_no;
LMB2_no: if (C_NUM_LMB < 3) generate
Sl2_DBus <= (others => '0');
Sl2_Ready <= '0';
Sl2_Wait <= '0';
Sl2_UE <= '0';
Sl2_CE <= '0';
end generate LMB2_no;
LMB3_no: if (C_NUM_LMB < 4) generate
Sl3_DBus <= (others => '0');
Sl3_Ready <= '0';
Sl3_Wait <= '0';
Sl3_UE <= '0';
Sl3_CE <= '0';
end generate LMB3_no;
one <= '1';
one_lmb: if (C_NUM_LMB = 1) generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_MASK)
port map (
A => LMB0_ABus,
CS => lmb_select,
Valid => one);
LMB_ABus <= LMB0_ABus;
LMB_WriteDBus <= LMB0_WriteDBus;
LMB_AddrStrobe <= LMB0_AddrStrobe;
LMB_ReadStrobe <= LMB0_ReadStrobe;
LMB_WriteStrobe <= LMB0_WriteStrobe;
LMB_BE <= LMB0_BE;
Sl0_DBus <= Sl_DBus;
Sl0_Ready <= Sl_Ready;
Sl0_Wait <= Sl_Wait;
Sl0_UE <= Sl_UE;
Sl0_CE <= Sl_CE;
end generate one_lmb;
more_than_one_lmb: if (C_NUM_LMB > 1) generate
type C_Mask_Vec_T is array (0 to 3) of std_logic_vector(0 to 31);
constant C_Mask_Vec : C_MASK_Vec_T := (C_MASK, C_MASK1, C_MASK2, C_MASK3);
type ABus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_AWIDTH - 1);
type DBus_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH - 1);
type BE_vec_T is array (0 to C_NUM_LMB-1) of std_logic_vector(0 to C_LMB_DWIDTH/8 - 1);
signal LMB_ABus_vec : ABus_vec_T;
signal LMB_ABus_vec_i : ABus_vec_T;
signal LMB_ABus_vec_Q : ABus_vec_T;
signal LMB_WriteDBus_vec : DBus_vec_T;
signal LMB_WriteDBus_vec_i : DBus_vec_T;
signal LMB_WriteDBus_vec_Q : DBus_vec_T;
signal LMB_AddrStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_AddrStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_ReadStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_i : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_WriteStrobe_vec_Q : std_logic_vector(0 to C_NUM_LMB-1);
signal LMB_BE_vec : BE_vec_T;
signal LMB_BE_vec_i : BE_vec_T;
signal LMB_BE_vec_Q : BE_vec_T;
signal Sl_DBus_vec : DBus_vec_T;
signal Sl_Ready_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_Wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_UE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal Sl_CE_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal wait_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal as_and_lmb_select_vec : std_logic_vector(0 to C_NUM_LMB-1);
signal ongoing : natural range 0 to C_NUM_LMB-1;
signal ongoing_new : natural range 0 to C_NUM_LMB-1;
signal ongoing_Q : natural range 0 to C_NUM_LMB-1;
begin
LMB_ABus_vec(0) <= LMB0_ABus;
LMB_WriteDBus_vec(0) <= LMB0_WriteDBus;
LMB_AddrStrobe_vec(0) <= LMB0_AddrStrobe;
LMB_ReadStrobe_vec(0) <= LMB0_ReadStrobe;
LMB_WriteStrobe_vec(0) <= LMB0_WriteStrobe;
LMB_BE_vec(0) <= LMB0_BE;
Sl0_DBus <= Sl_DBus_vec(0);
Sl0_Ready <= Sl_Ready_vec(0);
Sl0_Wait <= Sl_Wait_vec(0);
Sl0_UE <= Sl_UE_vec(0);
Sl0_CE <= Sl_CE_vec(0);
LMB_ABus_vec(1) <= LMB1_ABus;
LMB_WriteDBus_vec(1) <= LMB1_WriteDBus;
LMB_AddrStrobe_vec(1) <= LMB1_AddrStrobe;
LMB_ReadStrobe_vec(1) <= LMB1_ReadStrobe;
LMB_WriteStrobe_vec(1) <= LMB1_WriteStrobe;
LMB_BE_vec(1) <= LMB1_BE;
Sl1_DBus <= Sl_DBus_vec(1);
Sl1_Ready <= Sl_Ready_vec(1);
Sl1_Wait <= Sl_Wait_vec(1);
Sl1_UE <= Sl_UE_vec(1);
Sl1_CE <= Sl_CE_vec(1);
LMB2_yes: if (C_NUM_LMB > 2) generate
LMB_ABus_vec(2) <= LMB2_ABus;
LMB_WriteDBus_vec(2) <= LMB2_WriteDBus;
LMB_AddrStrobe_vec(2) <= LMB2_AddrStrobe;
LMB_ReadStrobe_vec(2) <= LMB2_ReadStrobe;
LMB_WriteStrobe_vec(2) <= LMB2_WriteStrobe;
LMB_BE_vec(2) <= LMB2_BE;
Sl2_DBus <= Sl_DBus_vec(2);
Sl2_Ready <= Sl_Ready_vec(2);
Sl2_Wait <= Sl_Wait_vec(2);
Sl2_UE <= Sl_UE_vec(2);
Sl2_CE <= Sl_CE_vec(2);
end generate LMB2_yes;
LMB3_yes: if (C_NUM_LMB > 3) generate
LMB_ABus_vec(3) <= LMB3_ABus;
LMB_WriteDBus_vec(3) <= LMB3_WriteDBus;
LMB_AddrStrobe_vec(3) <= LMB3_AddrStrobe;
LMB_ReadStrobe_vec(3) <= LMB3_ReadStrobe;
LMB_WriteStrobe_vec(3) <= LMB3_WriteStrobe;
LMB_BE_vec(3) <= LMB3_BE;
Sl3_DBus <= Sl_DBus_vec(3);
Sl3_Ready <= Sl_Ready_vec(3);
Sl3_Wait <= Sl_Wait_vec(3);
Sl3_UE <= Sl_UE_vec(3);
Sl3_CE <= Sl_CE_vec(3);
end generate LMB3_yes;
lmb_mux_generate: for I in 0 to C_NUM_LMB-1 generate
begin
-----------------------------------------------------------------------------
-- Do the LMB address decoding
-----------------------------------------------------------------------------
pselect_mask_lmb : pselect_mask
generic map (
C_AW => LMB_ABus'length,
C_BAR => C_BASEADDR,
C_MASK => C_Mask_Vec(I))
port map (
A => LMB_ABus_vec(I),
CS => lmb_select_vec(I),
Valid => one);
as_and_lmb_select_vec(I) <= lmb_select_vec(I) and LMB_AddrStrobe_vec(I);
remember_access : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
LMB_ABus_vec_Q(I) <= (others => '0');
LMB_WriteDBus_vec_Q(I) <= (others => '0');
LMB_AddrStrobe_vec_Q(I) <= '0';
LMB_ReadStrobe_vec_Q(I) <= '0';
LMB_WriteStrobe_vec_Q(I) <= '0';
LMB_BE_vec_Q(I) <= (others => '0');
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
LMB_ABus_vec_Q(I) <= LMB_ABus_vec(I);
LMB_WriteDBus_vec_Q(I) <= LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_Q(I) <= LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_Q(I) <= LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_Q(I) <= LMB_WriteStrobe_vec(I);
LMB_BE_vec_Q(I) <= LMB_BE_vec(I);
end if;
end if;
end process remember_access;
wait_proc : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
wait_vec(I) <= '0';
elsif (as_and_lmb_select_vec(I) = '1' and ongoing /= I) then
wait_vec(I) <= '1';
elsif (wait_vec(I) = '1' and ongoing = I) then
wait_vec(I) <= '0';
end if;
end if;
end process wait_proc;
LMB_ABus_vec_i(I) <= LMB_ABus_vec_Q(I) when wait_vec(I) = '1' else
LMB_ABus_vec(I);
LMB_WriteDBus_vec_i(I) <= LMB_WriteDBus_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteDBus_vec(I);
LMB_AddrStrobe_vec_i(I) <= LMB_AddrStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_AddrStrobe_vec(I);
LMB_ReadStrobe_vec_i(I) <= LMB_ReadStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_ReadStrobe_vec(I);
LMB_WriteStrobe_vec_i(I) <= LMB_WriteStrobe_vec_Q(I) when wait_vec(I) = '1' else
LMB_WriteStrobe_vec(I);
LMB_BE_vec_i(I) <= LMB_BE_vec_Q(I) when wait_vec(I) = '1' else
LMB_BE_vec(I);
-- Assign selected LMB from internal signals
Sl_DBus_vec(I) <= Sl_DBus;
Sl_Ready_vec(I) <= Sl_Ready when ongoing_Q = I else
'0';
Sl_Wait_vec(I) <= Sl_Wait when ongoing_Q = I else
wait_vec(I);
Sl_UE_vec(I) <= Sl_UE when ongoing_Q = I else
'0';
Sl_CE_vec(I) <= Sl_CE when ongoing_Q = I else
'0';
end generate lmb_mux_generate;
OnGoing_Reg : process (LMB_Clk) is
begin
if (LMB_Clk'event and LMB_Clk = '1') then
if (LMB_Rst = '1') then
ongoing_Q <= 0;
else
ongoing_Q <= ongoing;
end if;
end if;
end process OnGoing_Reg;
Arbit : process (as_and_lmb_select_vec, wait_vec) is
variable N : natural range 0 to C_NUM_LMB-1;
begin
ongoing_new <= 0;
for N in 0 to C_NUM_LMB - 1 loop
if as_and_lmb_select_vec(N) = '1' or wait_vec(N) = '1' then
ongoing_new <= N;
exit;
end if;
end loop;
end process Arbit;
ongoing <= ongoing_Q when Sl_Wait = '1' and Sl_Ready = '0' else
ongoing_new;
-- Assign selected LMB
LMB_ABus <= LMB_ABus_vec_i(ongoing);
LMB_WriteDBus <= LMB_WriteDBus_vec_i(ongoing);
LMB_AddrStrobe <= LMB_AddrStrobe_vec_i(ongoing);
LMB_ReadStrobe <= LMB_ReadStrobe_vec_i(ongoing);
LMB_WriteStrobe <= LMB_WriteStrobe_vec_i(ongoing);
LMB_BE <= LMB_BE_vec_i(ongoing);
lmb_select <= lmb_select_vec(ongoing) or wait_vec(ongoing);
end generate more_than_one_lmb;
end imp;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:31:59 05/28/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_char_rom_mux.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: char_rom_mux
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.types.all;
ENTITY test_char_rom_mux IS
END test_char_rom_mux;
ARCHITECTURE behavior OF test_char_rom_mux IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT char_rom_mux
PORT(
nrst : IN std_logic;
clk108 : IN std_logic;
active_pixgen_source : IN PIXGEN_SOURCE_T;
time_base_char : IN short_character;
time_base_char_pos_x : IN integer range 0 to 7;
time_base_char_pos_y : IN integer range 0 to 15;
settings_char : IN short_character;
settings_char_pos_x : IN integer range 0 to 7;
settings_char_pos_y : IN integer range 0 to 15;
char_pixel : OUT std_logic
);
END COMPONENT;
--Inputs
signal nrst : std_logic := '0';
signal clk108 : std_logic := '0';
signal active_pixgen_source : PIXGEN_SOURCE_T := BLANK_PIXGEN_T;
signal time_base_char : short_character := short_character'val (0);
signal time_base_char_pos_x : integer range 0 to 7 := 0;
signal time_base_char_pos_y : integer range 0 to 15 := 0;
signal settings_char : short_character := short_character'val (0);
signal settings_char_pos_x : integer range 0 to 7 := 0;
signal settings_char_pos_y : integer range 0 to 15 := 0;
--Outputs
signal char_pixel : std_logic;
-- Clock period definitions
constant clk108_period : time := 10 ns;
type chars_8 is array (0 to 7) of character;
type letter is array (0 to 15) of chars_8;
constant a_letter : letter :=
( "--------",
"--------",
"---X----",
"--XXX---",
"-XX-XX--",
"XX---XX-",
"XX---XX-",
"XXXXXXX-",
"XX---XX-",
"XX---XX-",
"XX---XX-",
"XX---XX-",
"--------",
"--------",
"--------",
"--------" );
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: char_rom_mux PORT MAP (
nrst => nrst,
clk108 => clk108,
active_pixgen_source => active_pixgen_source,
time_base_char => time_base_char,
time_base_char_pos_x => time_base_char_pos_x,
time_base_char_pos_y => time_base_char_pos_y,
settings_char => settings_char,
settings_char_pos_x => settings_char_pos_x,
settings_char_pos_y => settings_char_pos_y,
char_pixel => char_pixel
);
-- Clock process definitions
clk108_process :process
begin
clk108 <= '0';
wait for clk108_period/2;
clk108 <= '1';
wait for clk108_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
nrst <= '0';
wait for 100 ns;
nrst <= '1';
wait for clk108_period*10;
-- Testing memory against some random character: 'A'
active_pixgen_source <= TIME_BASE_PIXGEN_T;
time_base_char <= 'A';
time_base_char_pos_y <= 0;
for y in 0 to 15 loop
time_base_char_pos_x <= 0;
for x in 0 to 7 loop
wait for clk108_period;
if char_pixel = '1' then
assert a_letter (y)(x) = 'X' report "char_pixel should be '1', but is not";
else
assert a_letter (y)(x) = '-' report "char_pixel should be '0', but is not";
end if;
if time_base_char_pos_x = 7 then
time_base_char_pos_x <= 0;
else
time_base_char_pos_x <= time_base_char_pos_x + 1;
end if;
end loop;
if time_base_char_pos_y = 15 then
time_base_char_pos_y <= 0;
else
time_base_char_pos_y <= time_base_char_pos_y + 1;
end if;
end loop;
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: FIT CTU
-- Engineer: Elena Filipenkova
--
-- Create Date: 15:21:19 03/20/2015
-- Design Name: FPGA deska rizena procesorem
-- Module Name: rate_generator - Behavioral
-- Target Devices: Spartan-3E Starter Kit
-- Revision 0.01 - File Created
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity rate_generator is
generic(
dvsr : integer := 2604
-- divisor = 50000000 / (16 * baud)
-- 1200 -> 2604 +
-- 2400 -> 1302 +
-- 4800 -> 651 +
-- 9600 -> 326
-- 19200 -> 163
-- 38400 -> 81
-- 57600 -> 54 +
-- 115200 -> 27 +
-- 230400 -> 14
-- 460800 -> 7
-- 500000 -> 6
-- 576000 -> 5
-- 921600 -> 3
-- 1000000 -> 3 +
-- 1152000 -> 3
-- 1500000 -> 2 +
-- 2000000 -> 2
-- 2500000 -> 1
-- 3000000 -> 1 +
);
port(
clk : in std_logic;
reset : in std_logic;
b_edge : out std_logic
);
end rate_generator;
architecture Behavioral of rate_generator is
signal b_count : integer range 1 to dvsr := 1;
begin
b_clock : process (clk)
begin
if clk = '1' and clk'event then
if reset = '1' then
b_count <= 1;
b_edge <= '0';
elsif b_count = dvsr then
b_count <= 1;
b_edge <= '1';
else
b_count <= b_count + 1;
b_edge <= '0';
end if;
end if;
end process;
end Behavioral;
|
--! @file GPIOsingle.vhd
--! @author Salvatore Barone <salvator.barone@gmail.com>
--! @date 07 04 2017
--!
--! @copyright
--! Copyright 2017 Salvatore Barone <salvator.barone@gmail.com>
--!
--! This file is part of Zynq7000DriverPack
--!
--! Zynq7000DriverPack is free software; you can redistribute it and/or modify it under the terms of
--! the GNU General Public License as published by the Free Software Foundation; either version 3 of
--! the License, or any later version.
--!
--! Zynq7000DriverPack is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
--! without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--! GNU General Public License for more details.
--!
--! You should have received a copy of the GNU General Public License along with this program; if not,
--! write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
--! USA.
--!
--! @addtogroup myGPIO
--! @{
--! @addtogroup GPIO-single
--! @{
library ieee;
use ieee.std_logic_1164.all;
--! @brief Cella base GPIO
entity GPIOsingle is
Port ( GPIO_enable : in std_logic; --!
--! segnale di abilitazione, permette di pilotare la linea "GPIO_inout".
--! Quando GPIO_enable=1, la linea GPIO_inout e quella GPIO_write sono connesse tra loro, consentendo
--! la scrittura del valore del segnale GPIO_inout
GPIO_write : in std_logic; --!
--! segnale di input, diretto verso l'esterno del device GPIOsingle.
--! Quando GPIO_enable=1, la linea GPIO_inout e quella GPIO_write sono connesse tra loro, consentendo
--! la scrittura del valore del pin GPIO_inout.
GPIO_inout : inout std_logic; --!
--! segnale bidirezionale diretto verso l'esterno del device. Può essere usato per leggere/scrivere
--! segnali digitali da/verso l'esterno del device GPIOsingle
GPIO_read : out std_logic); --!
--! segnale di output, diretto verso l'esterno del device.
--! Quando GPIO_enable=1, la linea GPIO_inout e quella GPIO_write sono connesse tra loro, consentendo
--! la scrittura del valore dei pin, per cui questo segnale assume esattamente il valore con cui viene
--! impostato il segnale GPIO_write
end GPIOsingle;
architecture Structural of GPIOsingle is
begin
GPIO_read <= GPIO_inout;
with GPIO_enable select
GPIO_inout <= GPIO_write when '1',
'Z' when others;
end Structural;
--! @}
--! @}
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port (clk : in std_logic;
rom_enable: in std_logic;
direccion : in std_logic_vector(9 downto 0);
rom_datos : out std_logic_vector(7 downto 0));
end ROM;
architecture syn of ROM is
type rom_type is array (0 to 1023) of std_logic_vector (7 downto 0);
signal ROM : rom_type:= (X"20", X"2C", X"13", X"00", X"20", X"24", X"1C", X"05",
X"B0", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
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X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00",
X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00");
signal rdata : std_logic_vector(7 downto 0);
begin
rdata <= ROM(conv_integer(direccion));
process (clk)
begin
if (clk'event and clk = '1') then
if (rom_enable = '1') then
rom_datos <= rdata;
else
rom_datos <= "ZZZZZZZZ";
end if;
end if;
end process;
end syn;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WindowsManager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0'));
end WindowsManager;
architecture Behavioral of WindowsManager is
signal int_rs1, int_rs2, int_rd : integer range 0 to 39 := 0;
begin
process(cwp,rs1,rs2,rd,op,op3)
begin
--guardar instruccion save
if (op = "10" and op3 = "111100") then
cwpout <= '0';
--reset instruction
elsif (op = "10" and op3 = "111101") then
cwpout <= '1';
end if;
--registros goli rs1
if (rs1 >= "11000" and rs1 <= "11111") then
int_rs1 <= conv_integer(rs1) - conv_integer(cwp) * 16; --input
elsif (rs1 >= "10000" and rs1 <= "10111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --local
elsif (rs1 >= "01000" and rs1 <= "01111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --output
elsif (rs1 >= "00000" and rs1 <= "00111") then
int_rs1 <= conv_integer(rs1); --global
end if;
--registros goli rs2
if (rs2 >= "11000" and rs2 <= "11111") then
int_rs2 <= conv_integer(rs2) - conv_integer(cwp) * 16; --input
elsif (rs2 >= "10000" and rs2 <= "10111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --local
elsif (rs2 >= "01000" and rs2 <= "01111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --output
elsif (rs2 >= "00000" and rs2 <= "00111") then
int_rs2 <= conv_integer(rs2); --global
end if;
--registros goli rd
if (rd >= "11000" and rd <= "11111") then
int_rd <= conv_integer(rd) - conv_integer(cwp) * 16; --input
elsif (rd >= "10000" and rd <= "10111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --local
elsif (rd >= "01000" and rd <= "01111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --output
elsif (rd >= "00000" and rd <= "00111") then
int_rd <= conv_integer(rd); --global
end if;
end process;
rs1out <= conv_std_logic_vector(int_rs1, 6);
rs2out <= conv_std_logic_vector(int_rs2, 6);
rdout <= conv_std_logic_vector(int_rd, 6);
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_arith.ALL;
use IEEE.STD_LOGIC_unsigned.ALL;
entity WindowsManager is
Port ( cwp : in STD_LOGIC;
rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
op : in STD_LOGIC_VECTOR (1 downto 0);
op3 : in STD_LOGIC_VECTOR (5 downto 0);
cwpout : out STD_LOGIC;
rs1out : out STD_LOGIC_VECTOR (5 downto 0);
rs2out : out STD_LOGIC_VECTOR (5 downto 0);
rdout : out STD_LOGIC_VECTOR (5 downto 0):=(others=>'0'));
end WindowsManager;
architecture Behavioral of WindowsManager is
signal int_rs1, int_rs2, int_rd : integer range 0 to 39 := 0;
begin
process(cwp,rs1,rs2,rd,op,op3)
begin
--guardar instruccion save
if (op = "10" and op3 = "111100") then
cwpout <= '0';
--reset instruction
elsif (op = "10" and op3 = "111101") then
cwpout <= '1';
end if;
--registros goli rs1
if (rs1 >= "11000" and rs1 <= "11111") then
int_rs1 <= conv_integer(rs1) - conv_integer(cwp) * 16; --input
elsif (rs1 >= "10000" and rs1 <= "10111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --local
elsif (rs1 >= "01000" and rs1 <= "01111") then
int_rs1 <= conv_integer(rs1) + conv_integer(cwp) * 16; --output
elsif (rs1 >= "00000" and rs1 <= "00111") then
int_rs1 <= conv_integer(rs1); --global
end if;
--registros goli rs2
if (rs2 >= "11000" and rs2 <= "11111") then
int_rs2 <= conv_integer(rs2) - conv_integer(cwp) * 16; --input
elsif (rs2 >= "10000" and rs2 <= "10111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --local
elsif (rs2 >= "01000" and rs2 <= "01111") then
int_rs2 <= conv_integer(rs2) + conv_integer(cwp) * 16; --output
elsif (rs2 >= "00000" and rs2 <= "00111") then
int_rs2 <= conv_integer(rs2); --global
end if;
--registros goli rd
if (rd >= "11000" and rd <= "11111") then
int_rd <= conv_integer(rd) - conv_integer(cwp) * 16; --input
elsif (rd >= "10000" and rd <= "10111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --local
elsif (rd >= "01000" and rd <= "01111") then
int_rd <= conv_integer(rd) + conv_integer(cwp) * 16; --output
elsif (rd >= "00000" and rd <= "00111") then
int_rd <= conv_integer(rd); --global
end if;
end process;
rs1out <= conv_std_logic_vector(int_rs1, 6);
rs2out <= conv_std_logic_vector(int_rs2, 6);
rdout <= conv_std_logic_vector(int_rd, 6);
end Behavioral; |
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : mux7seg.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Multiplexer 4 inputs, 4 selector and one output
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 24.10.2017 0.1 Martin Angermair init
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity mux7seg is
port (
sw_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0);
ss_sel_o : out std_logic_vector(3 downto 0);
dp_o : out std_logic
);
end mux7seg;
architecture rtl of mux7seg is
component mux44to1 is
port (
digits_i : in std_logic_vector(15 downto 0);
sel_i : in std_logic_vector(1 downto 0);
digit_o : out std_logic_vector(3 downto 0)
);
end component;
component hex7seg is
port(
digit_i : in std_logic_vector(3 downto 0);
ss_o : out std_logic_vector(6 downto 0)
);
end component;
signal digits_i : std_logic_vector(15 downto 0);
signal sel_i : std_logic_vector(1 downto 0);
signal digit_i : std_logic_vector(3 downto 0);
begin
digits_i <= X"1234";
ss_sel_o <= not sw_i;
sel_i(1) <= sw_i(2) or sw_i(3);
sel_i(0) <= sw_i(1) or sw_i(3);
dp_o <= '1';
comp1: mux44to1
port map(
digits_i => digits_i,
sel_i => sel_i,
digit_o => digit_i
);
comp2: hex7seg
port map(
digit_i => digit_i,
ss_o => ss_o
);
end rtl; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dffg IS
generic(
width : integer := 16
);
PORT(
rst : in std_logic;
clk : in std_logic;
en : in std_logic;
d : in std_logic_vector(width-1 downto 0);
q : out std_logic_vector(width-1 downto 0)
);
END dffg;
ARCHITECTURE main OF dffg IS
BEGIN
PROCESS(clk, rst)
BEGIN
if rst='1' then
q <= (others => '0');
elsif(rising_edge(clk)) then
if(en = '1') then
q <= d;
end if;
end if;
END PROCESS;
END main; |
entity tb_memmux03 is
end tb_memmux03;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_memmux03 is
signal wen : std_logic;
signal addr : std_logic_vector (3 downto 0);
signal rdat : std_logic;
signal wdat : std_logic_vector (12 downto 0);
signal clk : std_logic;
signal rst : std_logic;
begin
dut : entity work.memmux03
port map (
wen => wen,
addr => addr,
rdat => rdat,
wdat => wdat,
clk => clk,
rst => rst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
constant c : std_logic_vector (12 downto 0) := b"1_0101_1100_1001";
begin
rst <= '1';
wen <= '0';
wdat <= c;
addr <= x"0";
pulse;
rst <= '0';
pulse;
assert rdat = '0' severity failure;
addr <= x"3";
wen <= '1';
pulse;
assert rdat = '0' severity failure;
wen <= '0';
pulse;
assert rdat = '1' severity failure;
for i in c'range loop
addr <= std_logic_vector (to_unsigned (i, 4));
pulse;
assert rdat = c(i) severity failure;
end loop;
wait;
end process;
end behav;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:00:40 11/20/2013
-- Design Name:
-- Module Name: C:/Users/etingi01/Mips32_948282_20.11.2013/My_TOP_tb_948282.vhd
-- Project Name: Mips32_948282_20.11.2013
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: My_TOP_948282
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY My_TOP_tb_948282 IS
END My_TOP_tb_948282;
ARCHITECTURE behavior OF My_TOP_tb_948282 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT My_TOP_948282
PORT(
Clock : IN std_logic;
Reset : IN std_logic;
address: out std_logic_vector (9 downto 0)
);
END COMPONENT;
--Inputs
signal Clock : std_logic := '0';
signal Reset : std_logic := '0';
signal address: std_logic_vector(9 downto 0);
-- Clock period definitions
constant Clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: My_TOP_948282 PORT MAP (
Clock => Clock,
Reset => Reset,
address=>address
);
-- Clock process definitions
--Clock_process :process
--begin
--Clock <= '0';
--wait for Clock_period/2;
--Clock <= '1';
--wait for Clock_period/2;
--end process;
-- Stimulus process
stim_proc: process
begin
Reset<='1';
Clock<='1';
wait for 100 ns;
Clock<='0';
Reset<='0';
wait for 100 ns;
--Reset<='1';
Clock<='1';
wait for 100 ns;
Clock<='0';
--Reset<='0';
wait for 100 ns;
Clock<='1';
wait for 100 ns;
Clock<='0';
wait for 100 ns;
Clock<='1';
wait for 100 ns;
Clock<='0';
wait for 100 ns;
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity VOICE is
port
(
start:in std_logic;
inclk,inclk_n:in std_logic;
init_clk:in std_logic;
init_wea:in std_logic_vector(0 downto 0);
init_addr:in std_logic_vector(5 downto 0);
init_din:in std_logic_vector(15 downto 0);
list_clk:in std_logic;
list_wea:in std_logic_vector(0 downto 0);
list_addr:in std_logic_vector(7 downto 0);
list_din:in std_logic_vector(7 downto 0);
clk_voice:out std_logic;
n_wr,n_cs,n_rd,n_rst:out std_logic:='1';
n_int:in std_logic:='0';
add_en:out std_logic:='0';
data_voice:inout std_logic_vector(7 downto 0);
voice_result:out std_logic_vector(7 downto 0):=x"00";
reco_rqu:in std_logic:='0';
reco_fin:out std_logic:='0';
voice_state:out std_logic_vector(7 downto 0):=x"00";
voice_ram:out std_logic_vector(15 downto 0):=x"0000"
);
end entity;
architecture voicex of VOICE is
component VOICE_ROM_INIT is
PORT
(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
end component;
component LIST is
PORT
(
clka : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN std_logic_vector(7 downto 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN std_logic_vector(7 downto 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
end component;
component VOICE_DELAY is
port
(
clk:in std_logic;
start:in std_logic:='0';
total:in std_logic_vector(7 downto 0);
finish:out std_logic:='1'
);
end component;
-------------------æ¶éã?0MHz---------------------
signal clk_self,clk_out:std_logic;
-----------------------å¤ä½------------------------
signal reset:std_logic:='0';
--------------------åå§åROM----------------------
signal rom_init_addr:std_logic_vector(5 downto 0):="000000";
signal rom_init_data:std_logic_vector(15 downto 0);
signal rom_en:std_logic:='1';
---------------------å表ROM-----------------------
signal rom_list_addr:std_logic_vector(7 downto 0):=x"00";
signal rom_list_data:std_logic_vector(7 downto 0);
-----------------------延æ¶------------------------
signal delay_start,delay_finish:std_logic:='0';
signal delay_total:std_logic_vector(7 downto 0);
----------------------é
ç½®ç¶æ?----------------------
signal init_done,list_done,all_wait,all_done,all_done_last:std_logic:='0';
----------------------è¯å«ç¶æ?----------------------
signal reco_allow,reco_allow_last,reco_start:std_logic:='0';
signal reco_rqu_last:std_logic:='0';
signal n_int_last:std_logic:='1';
signal add_en_s:std_logic:='1';
begin
voice_state(1)<=start;
voice_state(0)<=reco_rqu;
clk_voice<=inclk_n;
VOICE_ROM_INITX:voice_rom_init
port map
(
clka=>init_clk,
wea=>init_wea,
addra=>init_addr,
dina=>init_din,
clkb=>clk_out,
addrb=>rom_init_addr,
doutb=>rom_init_data
);
VOICE_ROM_LIST:list
port map
(
clka=>list_clk,
wea=>list_wea,
addra=>list_addr,
dina=>list_din,
clkb=>clk_out,
addrb=>rom_list_addr,
doutb=>rom_list_data
);
VOICE_DLLAYX:voice_delay port map(clk=>clk_self,start=>delay_start,finish=>delay_finish,total=>delay_total);
clk_self<=inclk;
clk_out<=inclk_n;
add_en<=add_en_s;
rom_en<='1';
process(clk_self,reset)
variable con_reset:integer range 0 to 127:=0;
variable con_init_start:integer range 0 to 2047:=0;
variable con:integer range 0 to 5:=0;
variable con_total:integer range 0 to 26:=0;
variable con_type:integer range 0 to 31:=0;
variable con_init_fin_start:integer range 0 to 3:=0;
begin
if clk_self'event and clk_self='1' then
voice_state(7)<='1';
--------------------å¤ä½-----------------------
if con_reset=127 then
reset<='1';
end if;
if reset='1' then
con_reset:=0;
reset<='0';
reco_fin<='0';
init_done<='0';
list_done<='0';
all_wait<='0';
all_done<='0';
reco_allow<='0';
rom_init_addr<="000000";
rom_list_addr<="00000000";
con_init_start:=0;
end if;
---------------------åå§å?---------------------
if start='1' then
if con_init_start=2047 then
con_init_start:=2047;
else
con_init_start:=con_init_start+1;
con:=0;
con_type:=0;
con_total:=0;
con_init_fin_start:=0;
end if;
end if;
if con_init_start=500 then
n_rst<='0';
elsif con_init_start=1000 then
n_rst<='1';
elsif con_init_start=1500 then
n_cs<='0';
elsif con_init_start=2000 then
n_cs<='1';
delay_start<='1';
delay_total<=x"5F";
end if;
--------------------åå§å?--------------------
if con_init_start=2047 and init_done='0' and delay_finish='1' then
voice_state(6)<='1';
if con=5 then
con:=0;
elsif con=0 then
if con_total=26 then
init_done<='1';
con:=0;
con_type:=0;
con_total:=0;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
-------------------------------------------------------
if con_total=0 or con_total=2 then
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=x"06";
else
add_en_s<='0';
data_voice<="ZZZZZZZZ";
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_type=0 then
n_wr<='0';
else
n_rd<='0';
end if;
elsif con=4 then
if add_en_s='0' then
delay_total<=x"0A";
delay_start<='1';
end if;
if con_type=0 then
n_wr<='1';
else
n_rd<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
-------------------------------------------------------
else
if con=1 then
delay_start<='0';
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
delay_total<=x"0A";
delay_start<='1';
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
-------------------å¾
è¯å«å表åå
?---------------
if init_done='1' and list_done='0' and delay_finish='1' then
voice_state(5)<='1';
if con=0 then
delay_start<='0';
con:=con+1;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
elsif con_type=10 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=1 then
if rom_list_data=x"FF" then
con_type:=20;
--list_done<='1';
delay_total<=x"5F";
delay_start<='1';
con:=0;
--con_type:=0;
else
add_en_s<='1';
data_voice<=x"C1";
con:=con+1;
con_type:=2;
end if;
elsif con_type=20 then
add_en_s<='1';
data_voice<=x"BF";
con:=con+1;
elsif con_type=21 then
add_en_s<='0';
data_voice<="ZZZZZZZZ";
con:=con+1;
elsif con_type=2 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=12;
elsif con_type=12 then
add_en_s<='1';
data_voice<=x"C3";
con:=con+1;
con_type:=13;
elsif con_type=13 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=14;
elsif con_type=14 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=15;
elsif con_type=15 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=16;
elsif con_type=16 then
add_en_s<='1';
data_voice<=x"08";
con:=con+1;
con_type:=17;
elsif con_type=17 then
add_en_s<='0';
data_voice<=x"00";
con:=con+1;
con_type:=3;
elsif con_type=3 then
add_en_s<='1';
data_voice<=x"05";
con:=con+1;
con_type:=11;
rom_list_addr<=rom_list_addr+1;
elsif con_type=4 then
add_en_s<='1';
data_voice<=x"B9";
con:=con+1;
con_type:=5;
rom_list_addr<=rom_list_addr+1;
elsif con_type=5 then
add_en_s<='0';
data_voice<=rom_list_data;
con:=con+1;
con_type:=6;
elsif con_type=6 then
add_en_s<='1';
data_voice<=x"B2";
con:=con+1;
con_type:=7;
elsif con_type=7 then
add_en_s<='0';
data_voice<=x"FF";
con:=con+1;
con_type:=8;
elsif con_type=8 then
add_en_s<='1';
data_voice<=x"37";
con:=con+1;
con_type:=9;
elsif con_type=9 then
add_en_s<='0';
data_voice<=x"04";
con:=con+1;
con_type:=0;
rom_list_addr<=rom_list_addr+1;
elsif con_type=11 then
if rom_list_data=x"FF" then
con_type:=4;
con:=0;
else
add_en_s<='0';
data_voice<=rom_list_data;
rom_list_addr<=rom_list_addr+1;
con:=con+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
con:=con+1;
elsif con=3 then
con:=con+1;
if con_type=10 or con_type=21 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
con:=con+1;
if add_en_s='0' and con_type/=11 then
delay_total<=x"01";
delay_start<='1';
end if;
if con_type=21 or con_type=10 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
con:=0;
if con_type=10 then
voice_ram(15 downto 8)<=data_voice;
voice_ram(5 downto 0)<=rom_init_addr;
if data_voice=x"21" then
con_type:=1;
else
delay_total<=x"0A";
delay_start<='1';
con_type:=0;
con_reset:=con_reset+1;
end if;
elsif con_type=0 then
con_type:=10;
elsif con_type=20 then
con_type:=21;
elsif con_type=21 then
if data_voice=x"31" then
con_type:=0;
list_done<='1';
con:=0;
con_type:=0;
else
reset<='1';
end if;
end if;
end if;
end if;
-------------------------è¯å«åå¤------------------------
reco_rqu_last<=reco_rqu;
if reco_rqu_last='0' and reco_rqu='1' then
reco_start<='1';
end if;
if list_done='1' and all_wait='0' and reco_start='1' and delay_finish='1' then
voice_state(4)<='1';
if con_init_fin_start=3 then
con_init_fin_start:=3;
else
rom_init_addr<="100000";
con_init_fin_start:=con_init_fin_start+1;
end if;
if con_init_fin_start=3 then
if con=5 then
con:=0;
elsif con=0 then
if con_total=5 then
all_wait<='1';
reco_start<='0';
con:=0;
con_type:=0;
con_total:=0;
con_reset:=0;
elsif con_total=0 then
con:=con+1;
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
data_voice<=rom_init_data(15 downto 8);
else
add_en_s<='0';
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
n_wr<='0';
elsif con=4 then
n_wr<='1';
if add_en_s='0' then
delay_total<=x"01";
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
con_total:=con_total+1;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
---------------------------è¯å«--------------------------
if all_wait='1' and delay_finish='1' then
voice_state(3)<='1';
if con=5 then
con:=0;
elsif con=0 then
if con_total=7 then
con_total:=0;
con_type:=0;
con:=0;
all_wait<='0';
all_done<='1';
else
con:=con+1;
end if;
else
con:=con+1;
end if;
if con=0 then
delay_start<='0';
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"B2";
elsif con_total=3 then
data_voice<=x"BF";
else
data_voice<=rom_init_data(15 downto 8);
end if;
else
add_en_s<='0';
if con_total=0 or con_total=3 then
data_voice<="ZZZZZZZZ";
else
data_voice<=rom_init_data(7 downto 0);
rom_init_addr<=rom_init_addr+1;
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if (con_total=0 or con_total=3) and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
if add_en_s='0' then
if con_total=2 then
delay_total<=x"05";
else
delay_total<=x"01";
end if;
delay_start<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_total=0 and con_type=1 then
if data_voice=x"21" then
con_total:=con_total+1;
else
con_reset:=con_reset+1;
con_total:=0;
end if;
elsif con_total=3 and con_type=1 then
if data_voice=x"31" then
con_total:=con_total+1;
else
reco_fin<='1';
data_voice<=x"FF";
reset<='1';
end if;
elsif con_type=1 then
con_total:=con_total+1;
end if;
if con_type=1 then
con_type:=0;
else
con_type:=con_type+1;
end if;
end if;
end if;
-----------------------è¯å«ç»æ---------------------
if all_done='1' and delay_finish='1' then
n_int_last<=n_int;
if n_int_last='1' and n_int='0' then
reco_allow<='1';
end if;
end if;
reco_allow_last<=reco_allow;
if reco_allow_last='1' and reco_allow='0' then
reco_fin<='0';
end if;
if reco_allow='1' then
voice_state(2)<='1';
if con=5 then
con:=0;
else
con:=con+1;
end if;
if con=0 then
if con_total=6 then
reco_allow<='0';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con=1 then
if con_type=0 then
add_en_s<='1';
if con_total=0 then
data_voice<=x"29";
elsif con_total=1 then
data_voice<=x"02";
elsif con_total=2 then
data_voice<=x"BF";
elsif con_total=3 then
data_voice<=x"2B";
elsif con_total=4 then
data_voice<=x"BA";
elsif con_total=5 then
data_voice<=x"C5";
end if;
else
add_en_s<='0';
if con_total<2 then
data_voice<=x"00";
else
data_voice<="ZZZZZZZZ";
end if;
end if;
elsif con=2 then
n_cs<='0';
elsif con=3 then
if con_total>1 and con_type=1 then
n_rd<='0';
else
n_wr<='0';
end if;
elsif con=4 then
if con_total>1 and con_type=1 then
n_rd<='1';
else
n_wr<='1';
end if;
elsif con=5 then
n_cs<='1';
if con_type=1 then
con_type:=0;
if con_total<2 then
con_total:=con_total+1;
elsif con_total=2 and data_voice=x"35" then
con_total:=con_total+1;
elsif con_total=3 and data_voice(3)='0' then
con_total:=con_total+1;
elsif con_total=4 then
if data_voice>x"00" and data_voice<x"05" then
con_total:=con_total+1;
else
voice_result<=x"FD";
reco_allow<='0';
reco_fin<='1';
all_done<='0';
con:=0;
con_type:=0;
con_total:=0;
end if;
elsif con_total=5 then
reco_fin<='1';
voice_result<=data_voice;
con_total:=con_total+1;
else
reset<='1';
end if;
else
con_type:=con_type+1;
end if;
end if;
end if;
end if;
end process;
end voicex;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity dynroiBinMask_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
status_reg_bypass_bit : out std_logic;
in_size_reg_in_w_reg : out std_logic_vector(11 downto 0);
in_size_reg_in_h_reg : out std_logic_vector(11 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(1 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end dynroiBinMask_slave;
architecture rtl of dynroiBinMask_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant IN_SIZE_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal status_reg_bypass_bit_reg : std_logic;
signal in_size_reg_in_w_reg_reg : std_logic_vector (11 downto 0);
signal in_size_reg_in_h_reg_reg : std_logic_vector (11 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
status_reg_bypass_bit_reg <= '0';
in_size_reg_in_w_reg_reg <= "000000000000";
in_size_reg_in_h_reg_reg <= "000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
status_reg_enable_bit_reg <= datawr_i(0);
status_reg_bypass_bit_reg <= datawr_i(1);
when IN_SIZE_REG_REG_ADDR =>
in_size_reg_in_w_reg_reg <= datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
in_size_reg_in_h_reg_reg <= datawr_i(27) & datawr_i(26) & datawr_i(25) & datawr_i(24) & datawr_i(23) & datawr_i(22) & datawr_i(21) & datawr_i(20) & datawr_i(19) & datawr_i(18) & datawr_i(17) & datawr_i(16);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case to_integer(unsigned(addr_rel_i)) is
when STATUS_REG_REG_ADDR =>
datard_o <= "000000000000000000000000000000" & status_reg_bypass_bit_reg & status_reg_enable_bit_reg;
when IN_SIZE_REG_REG_ADDR =>
datard_o <= "0000" & in_size_reg_in_h_reg_reg(11) & in_size_reg_in_h_reg_reg(10) & in_size_reg_in_h_reg_reg(9) & in_size_reg_in_h_reg_reg(8) & in_size_reg_in_h_reg_reg(7) & in_size_reg_in_h_reg_reg(6) & in_size_reg_in_h_reg_reg(5) & in_size_reg_in_h_reg_reg(4) & in_size_reg_in_h_reg_reg(3) & in_size_reg_in_h_reg_reg(2) & in_size_reg_in_h_reg_reg(1) & in_size_reg_in_h_reg_reg(0) & "0000" & in_size_reg_in_w_reg_reg(11) & in_size_reg_in_w_reg_reg(10) & in_size_reg_in_w_reg_reg(9) & in_size_reg_in_w_reg_reg(8) & in_size_reg_in_w_reg_reg(7) & in_size_reg_in_w_reg_reg(6) & in_size_reg_in_w_reg_reg(5) & in_size_reg_in_w_reg_reg(4) & in_size_reg_in_w_reg_reg(3) & in_size_reg_in_w_reg_reg(2) & in_size_reg_in_w_reg_reg(1) & in_size_reg_in_w_reg_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
status_reg_bypass_bit <= status_reg_bypass_bit_reg;
in_size_reg_in_w_reg <= in_size_reg_in_w_reg_reg;
in_size_reg_in_h_reg <= in_size_reg_in_h_reg_reg;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2402.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n02i02402ent IS
END c07s03b02x00p08n02i02402ent;
ARCHITECTURE c07s03b02x00p08n02i02402arch OF c07s03b02x00p08n02i02402ent IS
BEGIN
TESTING: PROCESS
type rec_type is record
ele_1 : integer;
ele_2 : integer;
end record;
variable v20 : rec_type;
BEGIN
v20 := (1 + 1 => 20, ele_2 => 0); -- Failure_here
-- simple expression
-- associations allowed only in array agregates.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n02i02402 - Element associations by simple expressions allowed only in array aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n02i02402arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2402.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n02i02402ent IS
END c07s03b02x00p08n02i02402ent;
ARCHITECTURE c07s03b02x00p08n02i02402arch OF c07s03b02x00p08n02i02402ent IS
BEGIN
TESTING: PROCESS
type rec_type is record
ele_1 : integer;
ele_2 : integer;
end record;
variable v20 : rec_type;
BEGIN
v20 := (1 + 1 => 20, ele_2 => 0); -- Failure_here
-- simple expression
-- associations allowed only in array agregates.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n02i02402 - Element associations by simple expressions allowed only in array aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n02i02402arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2402.vhd,v 1.2 2001-10-26 16:30:18 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b02x00p08n02i02402ent IS
END c07s03b02x00p08n02i02402ent;
ARCHITECTURE c07s03b02x00p08n02i02402arch OF c07s03b02x00p08n02i02402ent IS
BEGIN
TESTING: PROCESS
type rec_type is record
ele_1 : integer;
ele_2 : integer;
end record;
variable v20 : rec_type;
BEGIN
v20 := (1 + 1 => 20, ele_2 => 0); -- Failure_here
-- simple expression
-- associations allowed only in array agregates.
assert FALSE
report "***FAILED TEST: c07s03b02x00p08n02i02402 - Element associations by simple expressions allowed only in array aggregates."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b02x00p08n02i02402arch;
|
-- Testbench for the instruction decode stage
-- 2015-08-04 Lukas Jäger created
-- 2015-08-04 Lukas Jäger added test cases for forwarding
-- 2015-08-05 Lukas Jaeger adjusted dut to new interface
-- 2015-08-05 Lukas Jaeger added expected data for ip_out
-- 2015-08-06 Lukas, Carlos added test cases for Jump-instructions
-- 2015-08-06 Lukas Fixed some minor bugs
library IEEE;
use IEEE.std_logic_1164.all;
entity instruction_decode_tb is
end instruction_decode_tb;
architecture behavioural of instruction_decode_tb is
-- DUT
component instruction_decode
port(instr,ip_in, writeback, alu_result, mem_result: in std_logic_vector (31 downto 0);
writeback_reg, regdest_ex, regdest_mem : in std_logic_vector (4 downto 0);
regdest_mux, regshift_mux: in std_logic_vector (1 downto 0);
clk, reset, enable_regs: in std_logic;
reg_a, reg_b, imm, ip_out : out std_logic_vector (31 downto 0);
reg_dest, shift_out : out std_logic_vector (4 downto 0)
);
end component;
signal instr : std_logic_vector (31 downto 0) := x"00000000";
signal ip_in : std_logic_vector (31 downto 0) := x"00000000";
signal writeback : std_logic_vector (31 downto 0) := x"00000000";
signal alu_result : std_logic_vector (31 downto 0) := x"00000000";
signal mem_result : std_logic_vector (31 downto 0) := x"00000000";
signal writeback_reg : std_logic_vector (4 downto 0) := "00001";
signal regdest_mem : std_logic_vector (4 downto 0) := "00000";
signal regdest_ex : std_logic_vector (4 downto 0) := "00000";
signal regdest_mux : std_logic_vector (1 downto 0) := "00";
signal regshift_mux : std_logic_vector (1 downto 0) := "00";
signal clk : std_logic := '0';
signal reset : std_logic := '0';
signal enable_regs : std_logic := '0';
-- Tweak clock frequency here
constant clk_time : time := 10 ns;
begin
dut: instruction_decode port map(
instr => instr,
ip_in => ip_in,
writeback => writeback,
writeback_reg => writeback_reg,
alu_result => alu_result,
mem_result => mem_result,
regdest_mux => regdest_mux,
regshift_mux => regshift_mux,
clk => clk,
reset => reset,
enable_regs => enable_regs,
regdest_ex => regdest_ex,
regdest_mem => regdest_mem
);
clk_proc : process
begin
clk <= '0';
wait for clk_time / 2;
clk <= '1';
wait for clk_time / 2;
end process;
data_proc : process
begin
reset <= '0';
wait for clk_time/2;
reset <= '1';
enable_regs <= '1';
-- Writing some test values to the register file:
-- r1 becomes 01234567
writeback_reg <= "00001";
writeback <= x"01234567";
wait for clk_time;
-- r2 becomes 76543210
writeback_reg <= "00010";
writeback <= x"76543210";
mem_result <= x"76543210";
wait for clk_time;
-- r3 becomes -1 (signed)
writeback_reg <= "00011";
writeback <= X"FFFFFFFF";
wait for clk_time;
enable_regs <= '0';
writeback_reg <= "00000";
wait for clk_time;
-- Real testing starts here
--inserting an add-instruction that adds r1 and r2 to r3
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
instr <= x"00221820";
wait for clk_time;
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: fedcba98
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
alu_result <= x"fedcba98";
regdest_ex <= "00010";
instr <= x"00221820";
wait for clk_time;
regdest_ex <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 01101001
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
mem_result <= x"01101001";
regdest_mem <= "00010";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in both stages
--outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 01101001
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00000000
regdest_ex <= "00010";
regdest_mem <= "00010";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
regdest_ex <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r1 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a: fedcba98
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00006080
regdest_ex <= "00001";
instr <= x"00221820";
wait for clk_time;
regdest_ex <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r1 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a: 01101001
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00006080
regdest_mem <= "00001";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
-- inserting an add instruction that adds r1 and r2 to r3 while r2 is still in both stages
--outputs should be (all vals in hex notation):
-- reg_a: 01101001
-- reg_b: 76543210
-- reg_dest: 3;
-- imm: 1820
-- shift: 0
-- ip_out: 00006080
regdest_ex <= "00001";
regdest_mem <= "00001";
instr <= x"00221820";
wait for clk_time;
regdest_mem <= "00000";
regdest_ex <= "00000";
-- inserting an addi instruction that adds abcd in hex notation to r1 and stores it in r2
-- outputs should be (all vals in hex notation):
-- reg_a: 01234567
-- reg_b: 76543210;
-- reg_dest: 2;
-- imm: 0000abcd
-- shift: 0
-- ip_out: fffeaf34
instr <= x"2422abcd";
regdest_mux <= "01";
wait for clk_time;
regdest_mux <= "00";
-- Jump Register - Jump to the address contained in register $s
-- encoding 0000 00ss sss0 0000 0000 0000 0000 1000
-- Test: jump using register 1 value. Encoding 0020_0008
-- reg_a: 01234567
-- reg_b: 00000000;
-- reg_dest: 2;
-- imm: 0000abcd
-- shift: 0
-- ip_out: 01234567
instr <= x"00200008";
wait for clk_time;
-- Jump
-- ip_out : 02af37bc
ip_in <= x"01010101";
instr <= x"08abcdef";
wait for clk_time;
-- JAL
-- ip_out : 02af37bc
instr <= x"0cabcdef";
wait for clk_time;
-- JAL with negative immediate
-- ip_out: 0ffffffc
instr <= x"0fffffff";
wait for clk_time;
-- Forwarding test for regdest_ex and alu_result using a jump
-- jump to register value instruction that r1 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: fedcba98
alu_result <= x"fedcba98";
regdest_ex <= "00001";
instr <= x"00200008";
wait for clk_time;
regdest_ex <= "00000";
wait for clk_time;
-- Forwarding test for regdest_ex and alu_result using a jump
-- jump to register value instruction that r2 is still in memory stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: 1edf2a98
alu_result <= x"1edf2a98";
regdest_ex <= "00010";
instr <= x"00400008";
wait for clk_time;
regdest_ex <= "00000";
wait for clk_time;
-- Forwarding test for regdest_mem and writeback using a jump
-- jump to register value instruction that r1 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: fedcba98
mem_result <= x"fedcba98";
regdest_mem <= "00001";
instr <= x"00200008";
wait for clk_time;
regdest_mem <= "00000";
wait for clk_time;
-- Forwarding test for regdest_mem and writeback using a jump
-- jump to register value instruction that r2 is still in writeback stage
--outputs should be (all vals in hex notation):
-- reg_a:
-- reg_b:
-- reg_dest: ;
-- imm: 1820
-- shift: 0
-- ip_out: 1edf2a98
mem_result <= x"1edf2a98";
regdest_mem <= "00010";
instr <= x"00400008";
wait for clk_time;
regdest_mem <= "00000";
wait for clk_time;
-- Test for unsigned immediate expansion
-- reg_a: 01234567
-- reg_b: 76543210
-- imm: 0000ffff;
instr <= x"2422ffff";
wait for clk_time;
-- Test for signed immediate expansion
-- reg_a: 01234567
-- reg_b: 76543210
-- imm: ffffffff;
instr <= x"2022ffff";
wait for clk_time;
-- Test for a LW-Operation
-- imm: FFFF8010
instr <= x"8f828010";
wait for clk_time;
ip_in <=x"01010100";
-- Test for BEQ-Op (condition is true)
-- ip_out : 0103C0F8
instr <= x"1000AFFE";
wait for clk_time;
-- Test for BEQ-Op (condition is false)
-- ip_out : 01010100
instr <= x"1020AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is greater)
-- ip_out : 0103C0F8
instr <= x"0421AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is equal)
-- ip_out : 0103C0F8
instr <= x"0401AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is smaller)
-- ip_out : 01010100
instr <= x"0461AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is greater)
-- ip_out : 0103C0F8
-- R31: 01010100
instr <= x"0431AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is equal)
-- ip_out : 0103C0F8
instr <= x"0411AFFE";
wait for clk_time;
-- Test for BGEZAL-Op (var is smaller)
-- ip_out : 01010100
instr <= x"0471AFFE";
wait for clk_time;
-- Test for BGTZ (true)
-- ip_out: 0103C0F8
instr <=x"1C20AFFE";
wait for clk_time;
-- Test for BGTZ (false)
-- ip_out: 01010100
instr <= x"1C00AFFE";
wait for clk_time;
-- Test for BNEZ (true)
-- ip_out: 34
ip_in <= x"00000050";
instr <= x"1440fff8";
wait for clk_time;
-- Test for BNEZ (true)
-- ip_out: 58
ip_in <= x"00000050";
instr <= x"1400fff8";
wait for clk_time;
end process;
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:03:48 07/08/2015
-- Design Name:
-- Module Name: D:/Descargas/Frecuencimentro - Presentacion/ttop_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ttop_TB IS
END ttop_TB;
ARCHITECTURE behavior OF ttop_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:03:48 07/08/2015
-- Design Name:
-- Module Name: D:/Descargas/Frecuencimentro - Presentacion/ttop_TB.vhd
-- Project Name: Frecuencimentro
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: top
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ttop_TB IS
END ttop_TB;
ARCHITECTURE behavior OF ttop_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT top
PORT(
entrada : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
led : OUT std_logic_vector(6 downto 0);
led_unidades : OUT std_logic_vector(1 downto 0);
selector : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
signal entrada : std_logic := '0';
signal clk : std_logic := '0';
signal reset : std_logic := '0';
--Outputs
signal led : std_logic_vector(6 downto 0);
signal led_unidades : std_logic_vector(1 downto 0);
signal selector : std_logic_vector(3 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: top PORT MAP (
entrada => entrada,
clk => clk,
reset => reset,
led => led,
led_unidades => led_unidades,
selector => selector
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- This unit will simulate a AD
-- It will read form a file
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use std.textio.all;
library simio;
use simio.SIMIO_PACKAGE.all;
entity IQADemulator is
generic ( AD_FILE : string := "UNUSED";
DATA_WIDTH : integer := 6 );
port (
clk : in std_logic;
ce : in std_logic;
Iout : out std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' );
Qout : out std_logic_vector(DATA_WIDTH-1 downto 0) := ( others => '0' ));
end IQADemulator;
architecture behavior of IQADemulator is
signal state: integer:=0;
begin
process( clk )
variable buf: line ;
variable lineno:integer:=0;
FILE data_file: TEXT IS IN AD_FILE;
variable dataTemp: std_logic_vector(15 downto 0):="0000000000000000";
variable booval: boolean :=false;
variable strData : string(4 downto 1);
begin
if(AD_FILE = "UNUSED") then
ASSERT FALSE
REPORT "file not found!"
SEVERITY WARNING;
end if;
if clk'event and clk='1' then
if ce='1' then
if NOT ENDFILE(data_file) then
booval := true;
READLINE(data_file, buf);
lineno:=lineno+1;
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
dataTemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),16);
Iout<=dataTemp(DATA_WIDTH-1 downto 0 );
shrink_line(buf, 1);
READ(L=>buf, VALUE=>strData, good=>booval);
if not (booval) then
ASSERT FALSE
REPORT "[Line "& int_to_str(lineno) & "]:Illegal File Format! no time domain "
SEVERITY ERROR;
end if;
dataTemp:=CONV_STD_LOGIC_VECTOR(hex_str_to_int(strData),16);
Qout<=dataTemp(DATA_WIDTH-1 downto 0 );
else
Iout <= ( others => '0' );
Qout <= ( others => '0' );
end if;
end if;
end if;
end process;
end behavior;
|
entity test is
end entity test;
architecture rtl of test is
type test_t is record
t1 : natural;
t2 : natural;
end record test_t;
constant C_TEST_T : test_t :=
(
t1 => 1,
t2 => 2);
constant C_TEST : bit_vector(0 to 7) :=
(C_TEST_T.t1 => '1', others => '0');
begin
end architecture rtl;
|
entity test is
end entity test;
architecture rtl of test is
type test_t is record
t1 : natural;
t2 : natural;
end record test_t;
constant C_TEST_T : test_t :=
(
t1 => 1,
t2 => 2);
constant C_TEST : bit_vector(0 to 7) :=
(C_TEST_T.t1 => '1', others => '0');
begin
end architecture rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity tri_state_buffer is
Port ( din : in STD_LOGIC_VECTOR (7 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0);
en : in STD_LOGIC);
end tri_state_buffer;
architecture Behavioral of tri_state_buffer is
begin
dout <= din when (en='1') else
"ZZZZZZZZ" when (en='0') else
"ZZZZZZZZ";
end Behavioral;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: address_decoder.vhd
-- Version: v2.0
-- Description: Address decoder utilizing unconstrained arrays for Base
-- Address specification and ce number.
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 08/09/2010 --
-- - updated the core with optimziation. Closed CR 574507
-- - combined the CE generation logic to further optimize the code.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI LITE IPIF to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_base_v5_0
-- 4. No Logic Updates
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
--library proc_common_base_v5_0;
--use proc_common_base_v5_0.proc_common_pkg.clog2;
--use proc_common_base_v5_0.pselect_f;
--use proc_common_base_v5_0.ipif_pkg.all;
library axi_lite_ipif_v3_0_3;
use axi_lite_ipif_v3_0_3.ipif_pkg.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_BUS_AWIDTH -- Address bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- Bus_clk -- Clock
-- Bus_rst -- Reset
-- Address_In_Erly -- Adddress in
-- Address_Valid_Erly -- Address is valid
-- Bus_RNW -- Read or write registered
-- Bus_RNW_Erly -- Read or Write
-- CS_CE_ld_enable -- chip select and chip enable registered
-- Clear_CS_CE_Reg -- Clear_CS_CE_Reg clear
-- RW_CE_ld_enable -- Read or Write Chip Enable
-- CS_for_gaps -- CS generation for the gaps between address ranges
-- CS_Out -- Chip select
-- RdCE_Out -- Read Chip enable
-- WrCE_Out -- Write chip enable
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Entity Declaration
-------------------------------------------------------------------------------
entity address_decoder is
generic (
C_BUS_AWIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(0 to 31) := X"000001FF";
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_1000_0000", -- IP user0 base address
X"0000_0000_1000_01FF", -- IP user0 high address
X"0000_0000_1000_0200", -- IP user1 base address
X"0000_0000_1000_02FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
8, -- User0 CE Number
1 -- User1 CE Number
);
C_FAMILY : string := "virtex6"
);
port (
Bus_clk : in std_logic;
Bus_rst : in std_logic;
-- PLB Interface signals
Address_In_Erly : in std_logic_vector(0 to C_BUS_AWIDTH-1);
Address_Valid_Erly : in std_logic;
Bus_RNW : in std_logic;
Bus_RNW_Erly : in std_logic;
-- Registering control signals
CS_CE_ld_enable : in std_logic;
Clear_CS_CE_Reg : in std_logic;
RW_CE_ld_enable : in std_logic;
CS_for_gaps : out std_logic;
-- Decode output signals
CS_Out : out std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
RdCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1);
WrCE_Out : out std_logic_vector
(0 to calc_num_ce(C_ARD_NUM_CE_ARRAY)-1)
);
end entity address_decoder;
-------------------------------------------------------------------------------
-- Architecture section
-------------------------------------------------------------------------------
architecture IMP of address_decoder is
----------------------------------------------------------------------------------
-- below attributes are added to reduce the synth warnings in Vivado tool
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
----------------------------------------------------------------------------------
-- local type declarations ----------------------------------------------------
type decode_bit_array_type is Array(natural range 0 to (
(C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1) of
integer;
type short_addr_array_type is Array(natural range 0 to
C_ARD_ADDR_RANGE_ARRAY'LENGTH-1) of
std_logic_vector(0 to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- Function Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- This function converts a 64 bit address range array to a AWIDTH bit
-- address range array.
-------------------------------------------------------------------------------
function slv64_2_slv_awidth(slv64_addr_array : SLV64_ARRAY_TYPE;
awidth : integer)
return short_addr_array_type is
variable temp_addr : std_logic_vector(0 to 63);
variable slv_array : short_addr_array_type;
begin
for array_index in 0 to slv64_addr_array'length-1 loop
temp_addr := slv64_addr_array(array_index);
slv_array(array_index) := temp_addr((64-awidth) to 63);
end loop;
return(slv_array);
end function slv64_2_slv_awidth;
-------------------------------------------------------------------------------
--Function Addr_bits
--function to convert an address range (base address and an upper address)
--into the number of upper address bits needed for decoding a device
--select signal. will handle slices and big or little endian
-------------------------------------------------------------------------------
function Addr_Bits (x,y : std_logic_vector(0 to C_BUS_AWIDTH-1))
return integer is
variable addr_nor : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
addr_nor := x xor y;
for i in 0 to C_BUS_AWIDTH-1 loop
if addr_nor(i)='1' then
return i;
end if;
end loop;
--coverage off
return(C_BUS_AWIDTH);
--coverage on
end function Addr_Bits;
-------------------------------------------------------------------------------
--Function Get_Addr_Bits
--function calculates the array which has the decode bits for the each address
--range.
-------------------------------------------------------------------------------
function Get_Addr_Bits (baseaddrs : short_addr_array_type)
return decode_bit_array_type is
variable num_bits : decode_bit_array_type;
begin
for i in 0 to ((baseaddrs'length)/2)-1 loop
num_bits(i) := Addr_Bits (baseaddrs(i*2),
baseaddrs(i*2+1));
end loop;
return(num_bits);
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- NEEDED_ADDR_BITS
--
-- Function Description:
-- This function calculates the number of address bits required
-- to support the CE generation logic. This is determined by
-- multiplying the number of CEs for an address space by the
-- data width of the address space (in bytes). Each address
-- space entry is processed and the biggest of the spaces is
-- used to set the number of address bits required to be latched
-- and used for CE decoding. A minimum value of 1 is returned by
-- this function.
--
-------------------------------------------------------------------------------
function needed_addr_bits (ce_array : INTEGER_ARRAY_TYPE)
return integer is
constant NUM_CE_ENTRIES : integer := CE_ARRAY'length;
variable biggest : integer := 2;
variable req_ce_addr_size : integer := 0;
variable num_addr_bits : integer := 0;
begin
for i in 0 to NUM_CE_ENTRIES-1 loop
req_ce_addr_size := ce_array(i) * 4;
if (req_ce_addr_size > biggest) Then
biggest := req_ce_addr_size;
end if;
end loop;
num_addr_bits := clog2(biggest);
return(num_addr_bits);
end function NEEDED_ADDR_BITS;
-----------------------------------------------------------------------------
-- Function calc_high_address
--
-- This function is used to calculate the high address of the each address
-- range
-----------------------------------------------------------------------------
function calc_high_address (high_address : short_addr_array_type;
index : integer) return std_logic_vector is
variable calc_high_addr : std_logic_vector(0 to C_BUS_AWIDTH-1);
begin
If (index = (C_ARD_ADDR_RANGE_ARRAY'length/2-1)) Then
calc_high_addr := C_S_AXI_MIN_SIZE(32-C_BUS_AWIDTH to 31);
else
calc_high_addr := high_address(index*2+2);
end if;
return(calc_high_addr);
end function calc_high_address;
----------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant ARD_ADDR_RANGE_ARRAY : short_addr_array_type :=
slv64_2_slv_awidth(C_ARD_ADDR_RANGE_ARRAY,
C_BUS_AWIDTH);
constant NUM_BASE_ADDRS : integer := (C_ARD_ADDR_RANGE_ARRAY'length)/2;
constant DECODE_BITS : decode_bit_array_type :=
Get_Addr_Bits(ARD_ADDR_RANGE_ARRAY);
constant NUM_CE_SIGNALS : integer :=
calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant NUM_S_H_ADDR_BITS : integer :=
needed_addr_bits(C_ARD_NUM_CE_ARRAY);
-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------
signal pselect_hit_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal cs_out_i : std_logic_vector
(0 to ((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2)-1);
signal ce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal rdce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal ce_out_i : std_logic_vector(0 to NUM_CE_SIGNALS-1); --
signal cs_ce_clr : std_logic;
signal addr_out_s_h : std_logic_vector(0 to NUM_S_H_ADDR_BITS-1);
signal Bus_RNW_reg : std_logic;
-------------------------------------------------------------------------------
-- Begin architecture
-------------------------------------------------------------------------------
begin -- architecture IMP
-- Register clears
cs_ce_clr <= not Bus_rst or Clear_CS_CE_Reg;
addr_out_s_h <= Address_In_Erly(C_BUS_AWIDTH-NUM_S_H_ADDR_BITS
to C_BUS_AWIDTH-1);
-------------------------------------------------------------------------------
-- MEM_DECODE_GEN: Universal Address Decode Block
-------------------------------------------------------------------------------
MEM_DECODE_GEN: for bar_index in 0 to NUM_BASE_ADDRS-1 generate
---------------
constant CE_INDEX_START : integer
:= calc_start_ce_index(C_ARD_NUM_CE_ARRAY,bar_index);
constant CE_ADDR_SIZE : Integer range 0 to 15
:= clog2(C_ARD_NUM_CE_ARRAY(bar_index));
constant OFFSET : integer := 2;
constant BASE_ADDR_x : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= ARD_ADDR_RANGE_ARRAY(bar_index*2+1);
constant HIGH_ADDR_X : std_logic_vector(0 to C_BUS_AWIDTH-1)
:= calc_high_address(ARD_ADDR_RANGE_ARRAY,bar_index);
--constant DECODE_BITS_0 : integer:= DECODE_BITS(0);
---------
begin
---------
-- GEN_FOR_MULTI_CS: Below logic generates the CS for decoded address
-- -----------------
GEN_FOR_MULTI_CS : if C_ARD_ADDR_RANGE_ARRAY'length > 2 generate
-- Instantiate the basic Base Address Decoders
MEM_SELECT_I: entity axi_lite_ipif_v3_0_3.pselect_f
generic map
(
C_AB => DECODE_BITS(bar_index),
C_AW => C_BUS_AWIDTH,
C_BAR => ARD_ADDR_RANGE_ARRAY(bar_index*2),
C_FAMILY => C_FAMILY
)
port map
(
A => Address_In_Erly, -- [in]
AValid => Address_Valid_Erly, -- [in]
CS => pselect_hit_i(bar_index) -- [out]
);
end generate GEN_FOR_MULTI_CS;
-- GEN_FOR_ONE_CS: below logic decodes the CS for single address range
-- ---------------
GEN_FOR_ONE_CS : if C_ARD_ADDR_RANGE_ARRAY'length = 2 generate
pselect_hit_i(bar_index) <= Address_Valid_Erly;
end generate GEN_FOR_ONE_CS;
-- Instantate backend registers for the Chip Selects
BKEND_CS_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(Bus_Rst='0' or Clear_CS_CE_Reg = '1')then
cs_out_i(bar_index) <= '0';
elsif(CS_CE_ld_enable='1')then
cs_out_i(bar_index) <= pselect_hit_i(bar_index);
end if;
end if;
end process BKEND_CS_REG;
-------------------------------------------------------------------------
-- PER_CE_GEN: Now expand the individual CEs for each base address.
-------------------------------------------------------------------------
PER_CE_GEN: for j in 0 to C_ARD_NUM_CE_ARRAY(bar_index) - 1 generate
-----------
begin
-----------
----------------------------------------------------------------------
-- CE decoders for multiple CE's
----------------------------------------------------------------------
MULTIPLE_CES_THIS_CS_GEN : if CE_ADDR_SIZE > 0 generate
constant BAR : std_logic_vector(0 to CE_ADDR_SIZE-1) :=
std_logic_vector(to_unsigned(j,CE_ADDR_SIZE));
begin
CE_I : entity axi_lite_ipif_v3_0_3.pselect_f
generic map (
C_AB => CE_ADDR_SIZE ,
C_AW => CE_ADDR_SIZE ,
C_BAR => BAR ,
C_FAMILY => C_FAMILY
)
port map (
A => addr_out_s_h
(NUM_S_H_ADDR_BITS-OFFSET-CE_ADDR_SIZE
to NUM_S_H_ADDR_BITS - OFFSET - 1) ,
AValid => pselect_hit_i(bar_index) ,
CS => ce_expnd_i(CE_INDEX_START+j)
);
end generate MULTIPLE_CES_THIS_CS_GEN;
--------------------------------------
----------------------------------------------------------------------
-- SINGLE_CE_THIS_CS_GEN: CE decoders for single CE
----------------------------------------------------------------------
SINGLE_CE_THIS_CS_GEN : if CE_ADDR_SIZE = 0 generate
ce_expnd_i(CE_INDEX_START+j) <= pselect_hit_i(bar_index);
end generate;
-------------
end generate PER_CE_GEN;
------------------------
end generate MEM_DECODE_GEN;
-- RNW_REG_P: Register the incoming RNW signal at the time of registering the
-- address. This is need to generate the CE's separately.
RNW_REG_P:process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(RW_CE_ld_enable='1')then
Bus_RNW_reg <= Bus_RNW_Erly;
end if;
end if;
end process RNW_REG_P;
---------------------------------------------------------------------------
-- GEN_BKEND_CE_REGISTERS
-- This ForGen implements the backend registering for
-- the CE, RdCE, and WrCE output buses.
---------------------------------------------------------------------------
GEN_BKEND_CE_REGISTERS : for ce_index in 0 to NUM_CE_SIGNALS-1 generate
signal rdce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
signal wrce_expnd_i : std_logic_vector(0 to NUM_CE_SIGNALS-1);
------
begin
------
BKEND_RDCE_REG : process(Bus_Clk)
begin
if(Bus_Clk'EVENT and Bus_Clk = '1')then
if(cs_ce_clr='1')then
ce_out_i(ce_index) <= '0';
elsif(RW_CE_ld_enable='1')then
ce_out_i(ce_index) <= ce_expnd_i(ce_index);
end if;
end if;
end process BKEND_RDCE_REG;
rdce_out_i(ce_index) <= ce_out_i(ce_index) and Bus_RNW_reg;
wrce_out_i(ce_index) <= ce_out_i(ce_index) and not Bus_RNW_reg;
-------------------------------
end generate GEN_BKEND_CE_REGISTERS;
-------------------------------------------------------------------------------
CS_for_gaps <= '0'; -- Removed the GAP adecoder logic
---------------------------------
CS_Out <= cs_out_i ;
RdCE_Out <= rdce_out_i ;
WrCE_Out <= wrce_out_i ;
end architecture IMP;
|
----------------------------------------------------------------------------------
-- Responsáveis: Danillo Neves
-- Luiz Gustavo
-- Rodrigo Guimarães
-- Ultima mod.: 03/jun/2017
-- Nome do Módulo: TestBench do Banco de Registradores
-- Descrição: TestBench para o Conjunto de registradores com largura de
-- palavra parametrizável e com habilitação
----------------------------------------------------------------------------------
----------------------------------
-- Importando a biblioteca IEEE e especificando o uso dos estados lógicos
-- padrão
----------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
----------------------------------
-- Definiçao da entidade
----------------------------------
entity RegBank_TB is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
end RegBank_TB;
----------------------------------
-- Descritivo da operacionalidade da entidade
----------------------------------
architecture RegBank_TB_Op of RegBank_TB is
component RegBank is
Generic (DATA_WIDTH : natural := 32;
ADDRESS_WIDTH : natural := 5;
AMOUNT_REG : natural := 32);
Port (clk, wren : in std_logic;
radd1, radd2 : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wadd : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
wdata : in std_logic_vector(DATA_WIDTH-1 downto 0);
rdata1, rdata2: out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
type vector_array1 is array (natural range <>) of std_logic_vector(ADDRESS_WIDTH-1 downto 0);
type vector_array2 is array (natural range <>) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal CLK : std_logic := '0';
constant PERIOD : time := 5 ps;
signal WREN : std_logic;
signal RADD1, RADD2 : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal WADD : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal WDATA : std_logic_vector(DATA_WIDTH - 1 downto 0);
signal RDATA1, RDATA2 : std_logic_vector(DATA_WIDTH - 1 downto 0);
begin
CLK <= not CLK after PERIOD;
RB_TB: RegBank port map
(CLK, WREN,
RADD1, RADD2,
WADD,
WDATA,
RDATA1, RDATA2);
teste: process
variable init0 : std_logic := '0';
variable init1 : std_logic_vector(ADDRESS_WIDTH - 1 downto 0) := (others => '0');
variable init2 : std_logic_vector(DATA_WIDTH - 1 downto 0) := (others => '0');
variable ender : vector_array1(7 downto 0);
variable valor : vector_array2(15 downto 0);
begin
WREN <= init0;
RADD1 <= init1;
RADD2 <= init1;
WADD <= init1;
WDATA <= init2;
RDATA1 <= init2;
RDATA2 <= init2;
ender(0) := "00000";
ender(1) := "11111";
ender(2) := "00110";
ender(3) := "01101";
ender(4) := "00011";
ender(5) := "01010";
ender(6) := "01110";
ender(7) := "00010";
valor(0) := x"00025900";
valor(1) := x"00026797";
valor(2) := x"00092430";
valor(3) := x"00059664";
valor(4) := x"00008572";
valor(5) := x"00004416";
valor(6) := x"00000016";
valor(7) := x"00030581";
valor(8) := x"00006963";
valor(9) := x"00009871";
valor(10) := x"00091257";
valor(11) := x"00082022";
valor(12) := x"00089633";
valor(13) := x"00058236";
valor(14) := x"00052965";
valor(15) := x"00000001";
for var1 in std_logic range '0' to '1' loop
WREN <= var1;
wait for PERIOD;
for var2 in ender'range loop
WADD <= ender(var2);
wait for PERIOD;
for var3 in valor'range loop
WDATA <= valor(var3);
wait for PERIOD;
report "Testando WREN = " & std_logic'image(WREN) severity NOTE;
report "Testando WADD = " & integer'image(to_integer(unsigned(WADD))) & " e WDATA = " & integer'image(to_integer(unsigned(WDATA))) severity NOTE;
end loop;
end loop;
end loop;
wait for PERIOD;
end process teste;
end architecture RegBank_TB_Op; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_reset : in std_logic;
cpu_ready : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_ready,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cpu6502 is
port (
cpu_clk : in std_logic;
cpu_reset : in std_logic;
cpu_ready : in std_logic;
cpu_write : out std_logic;
cpu_wdata : out std_logic_vector(7 downto 0);
cpu_rdata : in std_logic_vector(7 downto 0);
cpu_addr : out std_logic_vector(16 downto 0);
cpu_pc : out std_logic_vector(15 downto 0);
IRQn : in std_logic; -- IRQ interrupt (level sensitive)
NMIn : in std_logic; -- NMI interrupt (edge sensitive)
SOn : in std_logic -- set Overflow flag
);
end cpu6502;
architecture cycle_exact of cpu6502 is
signal read_write_n : std_logic;
begin
core: entity work.proc_core
generic map (
support_bcd => true )
port map(
clock => cpu_clk,
clock_en => cpu_ready,
reset => cpu_reset,
irq_n => IRQn,
nmi_n => NMIn,
so_n => SOn,
pc_out => cpu_pc,
addr_out => cpu_addr,
data_in => cpu_rdata,
data_out => cpu_wdata,
read_write_n => read_write_n );
cpu_write <= not read_write_n;
end cycle_exact;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use work.time_pkg.all;
entity vhdl_time is
port(a : out std_logic;
b : in std_logic;
tout : out time;
tin : in time);
end vhdl_time;
architecture test of vhdl_time is
signal time_sig : time_subtype := 100 ns;
begin
tout <= 140 ns;
process(b)
variable time_var : time;
begin
if(rising_edge(b)) then
time_var := 100 ns;
time_sig := 500 ns;
a := '0';
wait for 50 ns;
a := '1';
wait for time_sig; -- signal
a := '0';
wait for time_const; -- constant
a := '1';
wait for time_var; -- variable
a := '0';
wait for (time_sig + time_const + time_var);
a := '1';
-- Modify variable & signal values
time_var := 10 ns;
wait for time_var;
a := '0';
time_sig := 20 ns;
wait for time_sig;
a := '1';
-- Test time read from port
wait for tin;
a := '0';
end if;
end process;
end test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use work.time_pkg.all;
entity vhdl_time is
port(a : out std_logic;
b : in std_logic;
tout : out time;
tin : in time);
end vhdl_time;
architecture test of vhdl_time is
signal time_sig : time_subtype := 100 ns;
begin
tout <= 140 ns;
process(b)
variable time_var : time;
begin
if(rising_edge(b)) then
time_var := 100 ns;
time_sig := 500 ns;
a := '0';
wait for 50 ns;
a := '1';
wait for time_sig; -- signal
a := '0';
wait for time_const; -- constant
a := '1';
wait for time_var; -- variable
a := '0';
wait for (time_sig + time_const + time_var);
a := '1';
-- Modify variable & signal values
time_var := 10 ns;
wait for time_var;
a := '0';
time_sig := 20 ns;
wait for time_sig;
a := '1';
-- Test time read from port
wait for tin;
a := '0';
end if;
end process;
end test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test for time related expressions.
library ieee;
use ieee.std_logic_1164.all;
use work.time_pkg.all;
entity vhdl_time is
port(a : out std_logic;
b : in std_logic;
tout : out time;
tin : in time);
end vhdl_time;
architecture test of vhdl_time is
signal time_sig : time_subtype := 100 ns;
begin
tout <= 140 ns;
process(b)
variable time_var : time;
begin
if(rising_edge(b)) then
time_var := 100 ns;
time_sig := 500 ns;
a := '0';
wait for 50 ns;
a := '1';
wait for time_sig; -- signal
a := '0';
wait for time_const; -- constant
a := '1';
wait for time_var; -- variable
a := '0';
wait for (time_sig + time_const + time_var);
a := '1';
-- Modify variable & signal values
time_var := 10 ns;
wait for time_var;
a := '0';
time_sig := 20 ns;
wait for time_sig;
a := '1';
-- Test time read from port
wait for tin;
a := '0';
end if;
end process;
end test;
|
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`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14000)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14000)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 14000)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
-- Copyright (c) 2009 Frank Buss (fb@frank-buss.de)
-- See license.txt for license
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.all;
entity test is
port(
clk_50mhz: in std_logic;
rs232_dce_txd: out std_logic;
rs232_dce_rxd: in std_logic;
led: out unsigned(7 downto 0);
VGA_BLUE: out std_logic;
VGA_GREEN: out std_logic;
VGA_HSYNC: out std_logic;
VGA_RED: out std_logic;
VGA_VSYNC: out std_logic
);
end entity test;
architecture rtl of test is
constant ADDRESS_WIDTH: natural := 17;
constant BIT_DEPTH: natural := 1;
constant SYSTEM_SPEED: natural := 50e6;
constant BAUDRATE: natural := 115200;
signal rs232DataReceived: std_logic := '0';
signal rs232DataIn: unsigned(7 downto 0) := (others => '0');
signal rs232SendTrigger: std_logic := '0';
signal rs232DataOut: unsigned(7 downto 0);
signal ledLatch: unsigned(7 downto 0) := (others => '0');
signal counter: natural range 0 to (system_speed / 2) := 0;
signal spiChipSelect: std_logic;
signal spiData: std_logic;
signal spiClock: std_logic;
signal busy: std_logic;
signal busyVector: unsigned(1 downto 0);
signal vsync: std_logic;
signal pixel: unsigned(BIT_DEPTH-1 downto 0);
signal vgaHsync: std_logic;
signal vgaVsync: std_logic;
begin
YaGraphCon_instance: entity YaGraphCon
generic map(ADDRESS_WIDTH, BIT_DEPTH)
port map(
clock => clk_50mhz,
spiChipSelect => spiChipSelect,
spiData => spiData,
spiClock => spiClock,
busy => busy,
vsync => vsync,
pixel => pixel,
vgaHsync => vgaHsync,
vgaVsync => vgaVsync
);
sender: entity rs232_sender
generic map(SYSTEM_SPEED, BAUDRATE)
port map(
clock => clk_50mhz,
data => rs232DataOut,
tx => rs232_dce_txd,
sendTrigger => rs232SendTrigger,
dataSent => ledLatch(4)
);
receiver: entity rs232_receiver
generic map(SYSTEM_SPEED, BAUDRATE)
port map(
clock => clk_50mhz,
reset => '0',
data => rs232DataIn,
rx => rs232_dce_rxd,
dataReceived => rs232DataReceived
);
process(clk_50mhz)
begin
if rising_edge(clk_50mhz) then
rs232SendTrigger <= '0';
if rs232DataReceived = '1' then
case rs232DataIn is
-- "t" for testing: invert LED
when x"74" =>
ledLatch(3) <= not ledLatch(3);
-- other commands for the SPI signals
when x"00" =>
spiChipSelect <= '1';
when x"01" =>
spiChipSelect <= '0';
when x"02" =>
spiClock <= '1';
when x"03" =>
spiClock <= '0';
when x"04" =>
spiData <= '1';
when x"05" =>
spiData <= '0';
-- other bytes: echo, for RS232 TX/RX test
when others =>
rs232DataOut <= rs232DataIn;
rs232SendTrigger <= '1';
end case;
end if;
-- signal falling busy signal with "o" for "ok"
busyVector <= busyVector(0) & busy;
if busyVector = "10" then
rs232DataOut <= x"6f";
rs232SendTrigger <= '1';
end if;
-- 1 Hz LED blinker
if counter = 0 then
ledLatch(0) <= not ledLatch(0);
counter <= SYSTEM_SPEED / 2;
else
counter <= counter - 1;
end if;
-- routing some internal signals to the LEDs
ledLatch(1) <= busy;
ledLatch(2) <= vsync;
ledLatch(3) <= rs232_dce_rxd;
ledLatch(5) <= pixel(0);
ledLatch(6) <= vgaHsync;
ledLatch(7) <= vgaVsync;
end if;
end process;
led <= ledLatch;
VGA_RED <= pixel(0);
VGA_GREEN <= pixel(0);
VGA_BLUE <= pixel(0);
VGA_HSYNC <= vgaHsync;
VGA_VSYNC <= vgaVsync;
end architecture rtl;
|
entity tb_aggr02 is
end tb_aggr02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_aggr02 is
signal a, b : std_logic_vector(7 downto 0);
begin
dut: entity work.aggr02
port map (a, b);
process
begin
a <= x"ff";
wait for 1 ns;
assert b = x"fe" severity failure;
a <= x"ee";
wait for 1 ns;
assert b = x"ee" severity failure;
wait;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc134.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00134ent IS
END c04s03b02x02p08n01i00134ent;
ARCHITECTURE c04s03b02x02p08n01i00134arch OF c04s03b02x02p08n01i00134ent IS
type AT1 is array (INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if ( P = ref ) then
P := set;
end if;
end;
variable V1, V2 : INTEGER;
BEGIN
V1 := 1;
V2 := 2;
Proc1(P(1) => V2, P(2) => V1, ref => (2, 1), set => (2, 3));
-- test here
assert V1 = 3 report "FAIL: actual V1 didn't get set right";
assert V2 = 2 report "FAIL: actual V2 didn't get set right";
assert NOT( V1 = 3 and V2 = 2 )
report "***PASSED TEST: c04s03b02x02p08n01i00134"
severity NOTE;
assert ( V1 = 3 and V2 = 2 )
report "***FAILED TEST: c04s03b02x02p08n01i00134 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00134arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc134.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00134ent IS
END c04s03b02x02p08n01i00134ent;
ARCHITECTURE c04s03b02x02p08n01i00134arch OF c04s03b02x02p08n01i00134ent IS
type AT1 is array (INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if ( P = ref ) then
P := set;
end if;
end;
variable V1, V2 : INTEGER;
BEGIN
V1 := 1;
V2 := 2;
Proc1(P(1) => V2, P(2) => V1, ref => (2, 1), set => (2, 3));
-- test here
assert V1 = 3 report "FAIL: actual V1 didn't get set right";
assert V2 = 2 report "FAIL: actual V2 didn't get set right";
assert NOT( V1 = 3 and V2 = 2 )
report "***PASSED TEST: c04s03b02x02p08n01i00134"
severity NOTE;
assert ( V1 = 3 and V2 = 2 )
report "***FAILED TEST: c04s03b02x02p08n01i00134 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00134arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc134.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p08n01i00134ent IS
END c04s03b02x02p08n01i00134ent;
ARCHITECTURE c04s03b02x02p08n01i00134arch OF c04s03b02x02p08n01i00134ent IS
type AT1 is array (INTEGER range <>) of INTEGER;
subtype ST1 is AT1(1 to 2);
BEGIN
TESTING: PROCESS
procedure Proc1(P : inout ST1; ref : in ST1; set : in ST1) is
begin
if ( P = ref ) then
P := set;
end if;
end;
variable V1, V2 : INTEGER;
BEGIN
V1 := 1;
V2 := 2;
Proc1(P(1) => V2, P(2) => V1, ref => (2, 1), set => (2, 3));
-- test here
assert V1 = 3 report "FAIL: actual V1 didn't get set right";
assert V2 = 2 report "FAIL: actual V2 didn't get set right";
assert NOT( V1 = 3 and V2 = 2 )
report "***PASSED TEST: c04s03b02x02p08n01i00134"
severity NOTE;
assert ( V1 = 3 and V2 = 2 )
report "***FAILED TEST: c04s03b02x02p08n01i00134 - Association element in an association list test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p08n01i00134arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 12288)
`protect data_block
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`protect end_protected
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2025.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02025ent IS
END c07s02b04x00p01n01i02025ent;
ARCHITECTURE c07s02b04x00p01n01i02025arch OF c07s02b04x00p01n01i02025ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + '0';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02025 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02025arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2025.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02025ent IS
END c07s02b04x00p01n01i02025ent;
ARCHITECTURE c07s02b04x00p01n01i02025arch OF c07s02b04x00p01n01i02025ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + '0';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02025 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02025arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2025.vhd,v 1.2 2001-10-26 16:30:15 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p01n01i02025ent IS
END c07s02b04x00p01n01i02025ent;
ARCHITECTURE c07s02b04x00p01n01i02025arch OF c07s02b04x00p01n01i02025ent IS
BEGIN
TESTING: PROCESS
type SWITCH_LEVEL is ('0', '1', 'X');
subtype LOGIC_SWITCH is SWITCH_LEVEL range '0' to '1';
variable LOGICV : LOGIC_SWITCH := '0';
BEGIN
LOGICV := LOGICV + '0';
assert FALSE
report "***FAILED TEST: c07s02b04x00p01n01i02025 - The adding operators + and - are predefined for any numeric type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p01n01i02025arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greths
-- File: greths.vhd
-- Authors: Andrea Gianarro
-- Description: Gigabit Ethernet Media Access Controller with Ethernet Debug
-- Communication Link and Serial GMII interface
------------------------------------------------------------------------------
library ieee;
library grlib;
library gaisler;
use ieee.std_logic_1164.all;
use grlib.stdlib.all;
use grlib.amba.all;
use grlib.devices.all;
library techmap;
use techmap.gencomp.all;
use gaisler.net.all;
use gaisler.ethernet_mac.all;
library eth;
use eth.ethcomp.all;
entity greths is
generic(
hindex : integer := 0;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#FFF#;
pirq : integer := 0;
fabtech : integer := 0;
memtech : integer := 0;
transtech : integer := 0;
ifg_gap : integer := 24;
attempt_limit : integer := 16;
backoff_limit : integer := 10;
slot_time : integer := 128;
mdcscaler : integer range 0 to 255 := 25;
enable_mdio : integer range 0 to 1 := 0;
fifosize : integer range 4 to 64 := 8;
nsync : integer range 1 to 2 := 2;
edcl : integer range 0 to 3 := 0;
edclbufsz : integer range 1 to 64 := 1;
burstlength : integer range 4 to 128 := 32;
macaddrh : integer := 16#00005E#;
macaddrl : integer := 16#000000#;
ipaddrh : integer := 16#c0a8#;
ipaddrl : integer := 16#0035#;
phyrstadr : integer range 0 to 32 := 0;
rmii : integer range 0 to 1 := 0;
sim : integer range 0 to 1 := 0;
giga : integer range 0 to 1 := 0;
oepol : integer range 0 to 1 := 0;
scanen : integer range 0 to 1 := 0;
ft : integer range 0 to 2 := 0;
edclft : integer range 0 to 2 := 0;
mdint_pol : integer range 0 to 1 := 0;
enable_mdint : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
ramdebug : integer range 0 to 2 := 0;
mdiohold : integer := 1;
maxsize : integer := 1500;
pcs_phyaddr : integer range 0 to 32 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
ahbmi : in ahb_mst_in_type;
ahbmo : out ahb_mst_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
-- High-speed Serial Interface
clk_125 : in std_logic;
rst_125 : in std_logic;
eth_rx_p : in std_logic;
eth_rx_n : in std_logic := '0';
eth_tx_p : out std_logic;
eth_tx_n : out std_logic;
-- MDIO interface
reset : out std_logic;
mdio_o : out std_logic;
mdio_oe : out std_logic;
mdio_i : in std_logic;
mdc : out std_logic;
mdint : in std_logic;
-- Control signals
phyrstaddr : in std_logic_vector(4 downto 0);
edcladdr : in std_logic_vector(3 downto 0);
edclsepahb : in std_logic;
edcldisable : in std_logic;
debug_pcs_mdio : in std_logic := '0';
-- added for igloo2_serdes
apbin : in apb_in_serdes := apb_in_serdes_none;
apbout : out apb_out_serdes;
m2gl_padin : in pad_in_serdes := pad_in_serdes_none;
m2gl_padout : out pad_out_serdes;
serdes_clk125 : out std_logic;
rx_aligned : out std_logic
);
end entity;
architecture rtl of greths is
-- GMII and MII signals between MAC and PCS
signal mac_ethi : eth_in_type;
signal pcs_ethi : eth_in_type;
signal mac_etho : eth_out_type;
signal pcs_etho : eth_out_type;
signal int_tx_rstn : std_logic;
signal int_rx_rstn : std_logic;
-- MDIO signals
signal mdio_o_pcs : std_logic;
signal mdio_oe_pcs : std_logic;
signal mdio_i_pcs : std_logic;
begin
-------------------------------------------------------------------------------
-- Ethernet MAC
-------------------------------------------------------------------------------
u0 : grethm
generic map (
hindex => hindex,
pindex => pindex,
paddr => paddr,
pmask => pmask,
pirq => pirq,
memtech => memtech,
ifg_gap => ifg_gap,
attempt_limit => attempt_limit,
backoff_limit => backoff_limit,
slot_time => slot_time,
mdcscaler => mdcscaler,
enable_mdio => enable_mdio,
fifosize => fifosize,
nsync => nsync,
edcl => edcl,
edclbufsz => edclbufsz,
burstlength => burstlength,
macaddrh => macaddrh,
macaddrl => macaddrl,
ipaddrh => ipaddrh,
ipaddrl => ipaddrl,
phyrstadr => phyrstadr,
rmii => rmii,
sim => sim,
giga => giga,
oepol => oepol,
scanen => scanen,
ft => ft,
edclft => edclft,
mdint_pol => mdint_pol,
enable_mdint => enable_mdint,
multicast => multicast,
ramdebug => ramdebug,
mdiohold => mdiohold,
maxsize => maxsize,
gmiimode => 1
)
port map (
rst => rst,
clk => clk,
ahbmi => ahbmi,
ahbmo => ahbmo,
apbi => apbi,
apbo => apbo,
ethi => mac_ethi,
etho => mac_etho
);
-------------------------------------------------------------------------------
-- 1000baseX-compliant SGMII bridge
-------------------------------------------------------------------------------
sgmii0: sgmii
generic map (
fabtech => fabtech,
memtech => memtech,
transtech => transtech,
phy_addr => pcs_phyaddr
)
port map(
clk_125 => clk_125,
rst_125 => rst_125,
ser_rx_p => eth_rx_p,
ser_rx_n => eth_rx_n,
ser_tx_p => eth_tx_p,
ser_tx_n => eth_tx_n,
txd => pcs_etho.txd,
tx_en => pcs_etho.tx_en,
tx_er => pcs_etho.tx_er,
tx_clk => pcs_ethi.gtx_clk,
tx_rstn => int_tx_rstn,
rxd => pcs_ethi.rxd,
rx_dv => pcs_ethi.rx_dv,
rx_er => pcs_ethi.rx_er,
rx_col => pcs_ethi.rx_col,
rx_crs => pcs_ethi.rx_crs,
rx_clk => pcs_ethi.rx_clk,
rx_rstn => int_rx_rstn,
-- optional MDIO interface to PCS
mdc => pcs_etho.mdc,
mdio_o => mdio_o_pcs,
mdio_oe => mdio_oe_pcs,
mdio_i => mdio_i_pcs,
-- added for igloo2_serdes
apbin => apbin,
apbout => apbout,
m2gl_padin => m2gl_padin,
m2gl_padout => m2gl_padout,
serdes_clk125 => serdes_clk125,
rx_aligned => rx_aligned
);
-- 10/100 Mbit GMII to MII adapter
adapt_10_100_0 : gmii_to_mii
port map (
tx_rstn => int_tx_rstn,
rx_rstn => int_rx_rstn,
gmiii => mac_ethi, -- OUT
gmiio => mac_etho, -- IN
miii => pcs_ethi, -- IN
miio => pcs_etho -- OUT
);
-- Drive MDIO signals (including PCS bypass to MAC)
reset <= pcs_etho.reset;
mdc <= pcs_etho.mdc;
mdio_oe <= '1' when debug_pcs_mdio = '1' else pcs_etho.mdio_oe;
mdio_o <= '0' when debug_pcs_mdio = '1' else pcs_etho.mdio_o;
mdio_oe_pcs <= pcs_etho.mdio_oe when debug_pcs_mdio = '1' else '1';
mdio_o_pcs <= pcs_etho.mdio_o when debug_pcs_mdio = '1' else '0';
pcs_ethi.mdint <= mdint;
pcs_ethi.mdio_i <= mdio_i_pcs when debug_pcs_mdio = '1' else mdio_i;
-- MAC input signals integration
pcs_ethi.tx_clk <= pcs_ethi.gtx_clk;
pcs_ethi.phyrstaddr <= phyrstaddr;
pcs_ethi.edcladdr <= edcladdr;
pcs_ethi.edclsepahb <= edclsepahb;
pcs_ethi.edcldisable <= edcldisable;
end architecture;
|
-- file: spi_master.vhd
-- description: SPI master interface
-- date: 03/2018
-- author: Sergio Johann Filho <sergio.filho@pucrs.br>
--
-- This is a simple SPI master interface that works in SPI MODE 0.
-- Chip select logic is not included in this design and should be
-- implemented externally.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity spi_master is
generic (
BYTE_SIZE: integer := 8
);
port ( -- core interface
clk_i: in std_logic;
rst_i: in std_logic;
data_i: in std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data in (clocked on rising spi_clk after last bit)
data_o: out std_logic_vector(BYTE_SIZE-1 downto 0); -- parallel data output (clocked on rising spi_clk after last bit)
data_valid_o: out std_logic; -- data valid (read / write finished)
wren_i: in std_logic; -- data write enable, starts transmission when interface is idle
-- SPI interface
spi_clk_o: out std_logic; -- spi bus sck
spi_mosi_o: out std_logic; -- spi bus mosi output
spi_miso_i: in std_logic -- spi bus miso input
);
end spi_master;
architecture spi_master_arch of spi_master is
type states is (idle, data1, clock1, data2, clock2, done);
signal state: states;
signal data_reg: std_logic_vector(BYTE_SIZE-1 downto 0);
signal counter: std_logic_vector(BYTE_SIZE-1 downto 0);
begin
process(clk_i, rst_i)
begin
if rst_i = '1' then
data_reg <= (others => '0');
counter <= (others => '0');
data_valid_o <= '0';
spi_clk_o <= '0';
spi_mosi_o <= '0';
elsif clk_i'event and clk_i = '1' then
case state is
when idle =>
counter <= (others => '0');
spi_clk_o <= '0';
spi_mosi_o <= '0';
data_valid_o <= '0';
data_reg <= data_i;
when data1 =>
data_valid_o <= '0';
spi_mosi_o <= data_reg(BYTE_SIZE-1);
when clock1 =>
spi_clk_o <= '1';
when data2 =>
data_reg <= data_reg(BYTE_SIZE-2 downto 0) & spi_miso_i;
when clock2 =>
spi_clk_o <= '0';
counter <= counter + 1;
when done =>
counter <= (others => '0');
data_valid_o <= '1';
spi_mosi_o <= '0';
when others => null;
end case;
end if;
end process;
data_o <= data_reg;
process(clk_i, rst_i, state, counter, wren_i)
begin
if rst_i = '1' then
state <= idle;
elsif clk_i'event and clk_i = '1' then
case state is
when idle =>
if (wren_i = '1') then
state <= data1;
end if;
when data1 =>
state <= clock1;
when clock1 =>
state <= data2;
when data2 =>
state <= clock2;
when clock2 =>
if (counter < BYTE_SIZE-1) then
state <= data1;
else
state <= done;
end if;
when done =>
if (wren_i = '0') then
state <= idle;
end if;
when others => null;
end case;
end if;
end process;
end spi_master_arch;
|
entity x is
port(
t :out bit_vector(0 to 0);
z :out bit_vector(0 to 0)
);
end entity;
architecture a of x is begin end architecture;
entity e is end entity;
architecture a of e is
constant z :integer := 0;
subtype t is bit_vector(0 to 0);
signal actual_for_t :bit;
signal actual_for_z :t;
begin
inst: entity work.x port map(
t(z) => actual_for_t,
t(z) => actual_for_z
);
end architecture;
|
entity tb_repro_sgn is
end tb_repro_sgn;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture behav of tb_repro_sgn is
signal clk : std_logic;
signal a : signed(7 downto 0);
signal b : signed(7 downto 0);
begin
dut: entity work.repro_sgn
port map (
clk => clk, a => a, b => b);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
a <= x"ab";
pulse;
assert b = x"ab" severity failure;
a <= x"12";
pulse;
assert b = x"12" severity failure;
wait;
end process;
end behav;
|
---------------------------------------------------------------------------
-- Copyright 2015 - 2017 Systems Group, ETH Zurich
--
-- This hardware module is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
USE IEEE.STD_LOGIC_TEXTIO.all;
LIBRARY STD;
USE STD.TEXTIO.ALL;
-------------------------------------------------------------------------------
-- This module is used to filter the input to the hash-table pipeline.
-- It acts as FIFO with a lookup, where the 'find' input is matched to all
-- elements in the queue.
-- The idea is that every write operation is pushed into the filter when
-- entering the pipeline, and popped when the memroy was written.
-- Read operations just need to be checked for address conflicts with the
-- writes, but need not be stored inside the filter .
-------------------------------------------------------------------------------
entity zk_session_Filter is
generic (
CONCURRENT_ADDR : integer := 8;
ADDR_WIDTH : integer := 16
);
port (
clk : in std_logic;
rst : in std_logic;
-- push in a new address. Only addresses not inside should pe pushed.
push_valid : in std_logic;
push_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-- the probe interface. Use it to check if an address is inside
find_loc : out std_logic_vector(CONCURRENT_ADDR-1 downto 0);
-- pop the oldest address.
pop_valid : in std_logic;
pop_loc: in std_logic_vector(CONCURRENT_ADDR-1 downto 0)
);
end zk_session_Filter;
architecture beh of zk_session_Filter is
type StackType is array(CONCURRENT_ADDR-1 downto 0) of std_logic_vector(ADDR_WIDTH-1 downto 0);
signal stack : StackType;
signal match : std_logic_vector(CONCURRENT_ADDR-1 downto 0);
signal empty : std_logic_vector(CONCURRENT_ADDR-1 downto 0);
signal findAddr : std_logic_vector(ADDR_WIDTH-1 downto 0);
signal tryPush : std_logic := '0';
signal waiting : std_logic;
begin -- beh
find_loc <= match;
comparison: process (clk)
begin
-- the probe input is checked in parallel with other operations
if (clk'event and clk='1') then
if (rst='1') then
waiting <= '0';
else
match <= (others => '0');
if (push_valid='1') then
findAddr <= push_addr;
for X in 0 to CONCURRENT_ADDR-1 loop
if push_addr=stack(X) then
match(X) <= '1';
else
match(X) <= '0';
end if;
--if (not stack(X))=0 then
-- empty(X) <= '1';
--end if;
end loop; -- X
else
for X in 0 to CONCURRENT_ADDR-1 loop
if findAddr=stack(X) then
match(X) <= '1';
else
match(X) <= '0';
end if;
end loop; -- X
end if;
end if;
end if;
end process comparison;
main: process (clk)
variable pos : integer;
begin -- process main
if (clk='1' and clk'event) then
if rst='1' then
tryPush <= '0';
-- the queue is empty
for X in 0 to CONCURRENT_ADDR-1 loop
stack(X) <= (others => '1');
empty(X) <= '1';
end loop;
else
-- DELETE
for X in 0 to CONCURRENT_ADDR-1 loop
if (pop_valid='1' and pop_loc(X)='1') then
stack(X) <= (others => '1');
empty(X) <= '1';
end if;
end loop;
-- PUSH
if (tryPush='0') then
tryPush <= push_valid;
end if;
if (tryPush='1' and match>0) then
tryPush <= '0';
end if;
if (tryPush='1' and match=0 and empty/=0) then
for X in CONCURRENT_ADDR-1 downto 0 loop
if (empty(X)='1') then
pos := X;
end if;
end loop;
stack(pos) <= findAddr;
empty(pos) <= '0';
tryPush <= '0';
end if;
end if;
end if;
end process main;
end beh;
|
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|
`protect begin_protected
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RPzqSbZ2u+4SMzLspFjthoG1RDtff91qNKMPOm2Op/1L/mtdpwWFkUj7acaXBNuABcwcMSkexD3E
WOuknKOdOL/3Du5qZY+QSV7gZYQGK/oaepQBLmFNoG2UPloi164hcQA7I9Rcw5ehJvhXkC9iYNK0
G9u4OfrPjav3y58GkBKPdHrFU4I87w2Bcl9yz7EQqYh5AVjUJ6vc8jE2otLmRBkHn31VgfphT8Xy
RhrQuc1Xusr3uR6FRNhFHVIAuWgNf56iz9P+qqorLPM3hbAfOClRAdJRcS94ChWbpYC9woD7Y1Gg
tztHxhBILvw7HilxEp/5oWDZm64JTuOh9nQ34+bN8HQQrlsZkve92QAld4W8zc2j1Nw+eu6QpDPG
BVyKRVoZYkjUSM4rVOap3QGMhfpaBrFtlOlXsKHuipDx4dq/Q26Ynq81N2k06eae4OAnkjO8I+Uw
G3UMtGEEqB8/c+XwYy+izpAiyL0QWQEPVZYIkp3o/WKrmDywjvAzwizCfWXF4NOps0eMGHbbvmSp
DHUEpUoQD+N2XDO3urrd6I3tqfRX7XIfwdYK0sPAcJcZcgLYAI6RtpJy7w7FWJNbz+kylC8ILQ==
`protect end_protected
|
-------------------------------------------------------------------------------
-- Title :
-------------------------------------------------------------------------------
-- File : Code8b10bPkg.vhd
-- Author : Benjamin Reese <bareese@slac.stanford.edu>
-- Company : SLAC National Accelerator Laboratory
-- Created : 2013-05-02
-- Last update: 2014-07-14
-- Platform :
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2013 SLAC National Accelerator Laboratory
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.StdRtlPkg.all;
package Code8b10bPkg is
-------------------------------------------------------------------------------------------------
-- Control Code Constants
-------------------------------------------------------------------------------------------------
constant K_28_0_C : slv(7 downto 0) := "00011100"; -- K28.0, 0x1C
constant K_28_1_C : slv(7 downto 0) := "00111100"; -- K28.1, 0x3C (Comma)
constant K_28_2_C : slv(7 downto 0) := "01011100"; -- K28.2, 0x5C
constant K_28_3_C : slv(7 downto 0) := "01111100"; -- K28.3, 0x7C
constant K_28_4_C : slv(7 downto 0) := "10011100"; -- K28.4, 0x9C
constant K_28_5_C : slv(7 downto 0) := "10111100"; -- K28.5, 0xBC (Comma)
constant K_28_6_C : slv(7 downto 0) := "11011100"; -- K28.6, 0xDC
constant K_28_7_C : slv(7 downto 0) := "11111100"; -- K28.7, 0xFC (Comma)
constant K_23_7_C : slv(7 downto 0) := "11110111"; -- K23.7, 0xF7
constant K_27_7_C : slv(7 downto 0) := "11111011"; -- K27.7, 0xFB
constant K_29_7_C : slv(7 downto 0) := "11111101"; -- K29.7, 0xFD
constant K_30_7_C : slv(7 downto 0) := "11111110"; -- K30.7, 0xFE
constant D_10_2_C : slv(7 downto 0) := "01001010"; -- D10.2, 0x4A
constant D_21_5_C : slv(7 downto 0) := "10110101"; -- D21.5, 0xB5
procedure encode8b10b (
dataIn : in slv(7 downto 0);
dataKIn : in sl;
dispIn : in sl;
dataOut : out slv(9 downto 0);
dispOut : out sl);
procedure decode8b10b (
dataIn : in slv(9 downto 0);
dispIn : in sl;
dataOut : out slv(7 downto 0);
dataKOut : out sl;
dispOut : out sl;
codeErr : out sl;
dispErr : out sl);
end package Code8b10bPkg;
package body Code8b10bPkg is
procedure encode8b10b (
dataIn : in slv(7 downto 0);
dataKIn : in sl;
dispIn : in sl;
dataOut : out slv(9 downto 0);
dispOut : out sl)
is
variable ai, bi, ci, di, ei, fi, gi, hi, ki : sl;
variable aeqb, ceqd : sl;
variable l22, l40, l04, l13, l31 : sl;
variable ao, bo, co, do, eo, io, fo, go, ho, jo : sl;
variable pd1s6, nd1s6, ndos6, pdos6 : sl;
variable alt6, alt7 : sl;
variable nd1s4, pd1s4, ndos4, pdos4 : sl;
variable illegalk : sl;
variable compls6, disp6, compls4 : sl;
begin
ai := dataIn(0);
bi := dataIn(1);
ci := dataIn(2);
di := dataIn(3);
ei := dataIn(4);
fi := dataIn(5);
gi := dataIn(6);
hi := dataIn(7);
ki := dataKIn;
aeqb := (ai and bi) or (not ai and not bi);
ceqd := (ci and di) or (not ci and not di);
l22 := (ai and bi and not ci and not di) or
(ci and di and not ai and not bi) or
(not aeqb and not ceqd);
l40 := ai and bi and ci and di;
l04 := not ai and not bi and not ci and not di;
l13 := (not aeqb and not ci and not di) or
(not ceqd and not ai and not bi);
l31 := (not aeqb and ci and di) or
(not ceqd and ai and bi);
-- The 5B/6B encoding
ao := ai;
bo := (bi and not l40) or l04;
co := l04 or ci or (ei and di and not ci and not bi and not ai);
do := di and not (ai and bi and ci);
eo := (ei or l13) and not (ei and di and not ci and not bi and not ai);
io := (l22 and not ei) or
(ei and not di and not ci and not (ai and bi)) or -- D16, D17, D18
(ei and l40) or
(ki and ei and di and ci and not bi and not ai) or -- K.28
(ei and not di and ci and not bi and not ai);
-- pds16 indicates cases where d-1 is assumed + to get our encoded value
pd1s6 := (ei and di and not ci and not bi and not ai) or (not ei and not l22 and not l31);
-- nds16 indicates cases where d-1 is assumed - to get our encoded value
nd1s6 := ki or (ei and not l22 and not l13) or (not ei and not di and ci and bi and ai);
-- ndos6 is pds16 cases where d-1 is + yields - disp out - all of them
ndos6 := pd1s6;
-- pdos6 is nds16 cases where d-1 is - yields + disp out - all but one
pdos6 := ki or (ei and not l22 and not l13);
-- some Dx.7 and all Kx.7 cases result in run length of 5 case unless
-- an alternate coding is used (referred to as Dx.A7, normal is Dx.P7)
-- specifically, D11, D13, D14, D17, D18, D19.
if (dispIn = '1') then
alt6 := (not ei and di and l31);
else
alt6 := (ei and not di and l13);
end if;
alt7 := fi and gi and hi and (ki or alt6);
fo := fi and not alt7;
go := gi or (not fi and not gi and not hi);
ho := hi;
jo := (not hi and (gi xor fi)) or alt7;
-- nd1s4 is cases where d-1 is assumed - to get our encoded value
nd1s4 := fi and gi;
-- pd1s4 is cases where d-1 is assumed + to get our encoded value
pd1s4 := (not fi and not gi) or (ki and ((fi and not gi) or (not fi and gi)));
-- ndos4 is pd1s4 cases where d-1 is + yields - disp out - just some
ndos4 := (not fi and not gi);
-- pdos4 is nd1s4 cases where d-1 is - yields + disp out
pdos4 := fi and gi and hi;
-- only legal K codes are K28.0- > .7, K23/27/29/30.7
-- K28.0- > 7 is ei = di = ci = 1, bi = ai = 0
-- K23 is 10111
-- K27 is 11011
-- K29 is 11101
-- K30 is 11110 - so K23/27/29/30 are ei and l31
illegalk := ki and
(ai or bi or not ci or not di or not ei) and -- not K28.0- > 7
(not fi or not gi or not hi or not ei or not l31); -- not K23/27/29/30.7
-- now determine whether to do the complementing
-- complement if prev disp is - and pd1s6 is set, or + and nd1s6 is set
compls6 := (pd1s6 and not dispin) or (nd1s6 and dispin);
-- disparity out of 5b6b is disp in with pdso6 and ndso6
-- pds16 indicates cases where d-1 is assumed + to get our encoded value
-- ndos6 is cases where d-1 is + yields - disp out
-- nds16 indicates cases where d-1 is assumed - to get our encoded value
-- pdos6 is cases where d-1 is - yields + disp out
-- disp toggles in all ndis16 cases, and all but that 1 nds16 case
disp6 := dispin xor (ndos6 or pdos6);
compls4 := (pd1s4 and not disp6) or (nd1s4 and disp6);
dispOut := disp6 xor (ndos4 or pdos4);
dataOut := (jo xor compls4) & (ho xor compls4) &
(go xor compls4) & (fo xor compls4) &
(io xor compls6) & (eo xor compls6) &
(do xor compls6) & (co xor compls6) &
(bo xor compls6) & (ao xor compls6);
end procedure encode8b10b;
procedure decode8b10b (
dataIn : in slv(9 downto 0);
dispIn : in sl;
dataOut : out slv(7 downto 0);
dataKOut : out sl;
dispOut : out sl;
codeErr : out sl;
dispErr : out sl)
is
variable ai, bi, ci, di, ei, ii, fi, gi, hi, ji : sl;
variable aeqb, ceqd : sl;
variable p22, p13, p31, p40, p04 : sl;
variable disp6a, disp6a2, disp6a0, disp6b : sl;
variable p22bceeqi, p22bncneeqi, p13in, p31i, p13dei : sl;
variable p22aceeqi, p22ancneeqi : sl;
variable p13en, anbnenin, abei, cdei, cndnenin : sl;
variable p22enin, p22ei, p31dnenin, p31e : sl;
variable compa, compb, compc, compd, compe : sl;
variable ao, bo, co, do, eo, ko, fo, go, ho : sl;
variable feqg, heqj, fghj22, fghjp13, fghjp31 : sl;
variable alt7, k28, k28p : sl;
variable disp6p, disp6n, disp4p, disp4n : sl;
begin
ai := dataIn(0);
bi := dataIn(1);
ci := dataIn(2);
di := dataIn(3);
ei := dataIn(4);
ii := dataIn(5);
fi := dataIn(6);
gi := dataIn(7);
hi := dataIn(8);
ji := dataIn(9);
aeqb := (ai and bi) or (not ai and not bi);
ceqd := (ci and di) or (not ci and not di);
p22 := (ai and bi and not ci and not di) or
(ci and di and not ai and not bi) or
(not aeqb and not ceqd);
p13 := (not aeqb and not ci and not di) or
(not ceqd and not ai and not bi);
p31 := (not aeqb and ci and di) or
(not ceqd and ai and bi);
p40 := ai and bi and ci and di;
p04 := not ai and not bi and not ci and not di;
disp6a := p31 or (p22 and dispin); -- pos disp if p22 and was pos, or p31.
disp6a2 := p31 and dispin; -- disp is ++ after 4 bits
disp6a0 := p13 and not dispin; -- -- disp after 4 bits
disp6b := (((ei and ii and not disp6a0) or (disp6a and (ei or ii)) or disp6a2 or
(ei and ii and di)) and (ei or ii or di)) ;
-- The 5B/6B decoding special cases where ABCDE not = abcde
p22bceeqi := p22 and bi and ci and (ei xnor ii);
p22bncneeqi := p22 and not bi and not ci and (ei xnor ii);
p13in := p13 and not ii;
p31i := p31 and ii;
p13dei := p13 and di and ei and ii;
p22aceeqi := p22 and ai and ci and (ei xnor ii);
p22ancneeqi := p22 and not ai and not ci and (ei xnor ii);
p13en := p13 and not ei;
anbnenin := not ai and not bi and not ei and not ii;
abei := ai and bi and ei and ii;
cdei := ci and di and ei and ii;
cndnenin := not ci and not di and not ei and not ii;
-- non-zero disparity cases:
p22enin := p22 and not ei and not ii;
p22ei := p22 and ei and ii;
-- p13in := p12 and not ii ;
-- p31i := p31 and ii ;
p31dnenin := p31 and not di and not ei and not ii;
-- p13dei := p13 and di and ei and ii ;
p31e := p31 and ei;
compa := p22bncneeqi or p31i or p13dei or p22ancneeqi or
p13en or abei or cndnenin;
compb := p22bceeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin;
compc := p22bceeqi or p31i or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin;
compd := p22bncneeqi or p31i or p13dei or p22aceeqi or
p13en or abei or cndnenin;
compe := p22bncneeqi or p13in or p13dei or p22ancneeqi or
p13en or anbnenin or cndnenin;
ao := ai xor compa;
bo := bi xor compb;
co := ci xor compc;
do := di xor compd;
eo := ei xor compe;
feqg := (fi and gi) or (not fi and not gi);
heqj := (hi and ji) or (not hi and not ji);
fghj22 := (fi and gi and not hi and not ji) or
(not fi and not gi and hi and ji) or
(not feqg and not heqj);
fghjp13 := (not feqg and not hi and not ji) or
(not heqj and not fi and not gi);
fghjp31 := ((not feqg) and hi and ji) or
(not heqj and fi and gi);
dispout := (fghjp31 or (disp6b and fghj22) or (hi and ji)) and (hi or ji);
ko := ((ci and di and ei and ii) or (not ci and not di and not ei and not ii) or
(p13 and not ei and ii and gi and hi and ji) or
(p31 and ei and not ii and not gi and not hi and not ji)) ;
alt7 := (fi and not gi and not hi and -- 1000 cases, where disp6b is 1
((dispin and ci and di and not ei and not ii) or ko or
(dispin and not ci and di and not ei and not ii))) or
(not fi and gi and hi and -- 0111 cases, where disp6b is 0
((not dispin and not ci and not di and ei and ii) or ko or
(not dispin and ci and not di and ei and ii))) ;
k28 := (ci and di and ei and ii) or not (ci or di or ei or ii);
-- k28 with positive disp into fghi - .1, .2, .5, and .6 special cases
k28p := not (ci or di or ei or ii);
fo := (ji and not fi and (hi or not gi or k28p)) or
(fi and not ji and (not hi or gi or not k28p)) or
(k28p and gi and hi) or
(not k28p and not gi and not hi);
go := (ji and not fi and (hi or not gi or not k28p)) or
(fi and not ji and (not hi or gi or k28p)) or
(not k28p and gi and hi) or
(k28p and not gi and not hi);
ho := ((ji xor hi) and not ((not fi and gi and not hi and ji and not k28p) or (not fi and gi and hi and not ji and k28p) or
(fi and not gi and not hi and ji and not k28p) or (fi and not gi and hi and not ji and k28p))) or
(not fi and gi and hi and ji) or (fi and not gi and not hi and not ji);
disp6p := (p31 and (ei or ii)) or (p22 and ei and ii);
disp6n := (p13 and not (ei and ii)) or (p22 and not ei and not ii);
disp4p := fghjp31;
disp4n := fghjp13;
codeErr := p40 or p04 or (fi and gi and hi and ji) or (not fi and not gi and not hi and not ji) or
(p13 and not ei and not ii) or (p31 and ei and ii) or
(ei and ii and fi and gi and hi) or (not ei and not ii and not fi and not gi and not hi) or
(ei and not ii and gi and hi and ji) or (not ei and ii and not gi and not hi and not ji) or
(not p31 and ei and not ii and not gi and not hi and not ji) or
(not p13 and not ei and ii and gi and hi and ji) or
(((ei and ii and not gi and not hi and not ji) or
(not ei and not ii and gi and hi and ji)) and
not ((ci and di and ei) or (not ci and not di and not ei))) or
(disp6p and disp4p) or (disp6n and disp4n) or
(ai and bi and ci and not ei and not ii and ((not fi and not gi) or fghjp13)) or
(not ai and not bi and not ci and ei and ii and ((fi and gi) or fghjp31)) or
(fi and gi and not hi and not ji and disp6p) or
(not fi and not gi and hi and ji and disp6n) or
(ci and di and ei and ii and not fi and not gi and not hi) or
(not ci and not di and not ei and not ii and fi and gi and hi);
dataOut := ho & go & fo & eo & do & co & bo & ao;
dataKOut := ko;
--my disp err fires for any legal codes that violate disparity, may fire for illegal codes
dispErr := ((dispin and disp6p) or (disp6n and not dispin) or
(dispin and not disp6n and fi and gi) or
(dispin and ai and bi and ci) or
(dispin and not disp6n and disp4p) or
(not dispin and not disp6p and not fi and not gi) or
(not dispin and not ai and not bi and not ci) or
(not dispin and not disp6p and disp4n) or
(disp6p and disp4p) or (disp6n and disp4n)) ;
end procedure decode8b10b;
end package body Code8b10bPkg;
|
library ieee;
package body fifo_pkg is
end package body;
-- Comments are allowed
package body fifo_pkg is
end package body;
-- Violation below
library ieee;
package body fifo_pkg is
end package body;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
--------------------------------------------------
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
|
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