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-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
--------------------------------------------------
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
package mem_pkg is
subtype word is bit_vector(0 to 31);
type word_array is array (natural range <>) of word;
procedure load_array ( words : out word_array; file_name : string );
end package mem_pkg;
--------------------------------------------------
package body mem_pkg is
procedure load_array ( words : out word_array; file_name : string ) is
-- words'path_name = ":project:mem_pkg:load_array:words"
use std.textio.all;
file load_file : text open read_mode is file_name;
-- load_file'path_name = ":project:mem_pkg:load_array:load_file"
procedure read_line is
-- read_line'path_name = ":project:mem_pkg:load_array:read_line:"
variable current_line : line;
-- current_line'path_name =
-- ":project:mem_pkg:load_array:read_line:current_line"
begin
-- . . .
-- not in book
report current_line'path_name;
-- end not in book
end procedure read_line;
begin -- load_array
-- . . .
-- not in book
report mem_pkg'path_name;
report words'path_name;
report load_file'path_name;
report read_line'path_name;
read_line;
-- end not in book
end procedure load_array;
end package body mem_pkg;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1364.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01364ent IS
END c08s05b00x00p03n01i01364ent;
ARCHITECTURE c08s05b00x00p03n01i01364arch OF c08s05b00x00p03n01i01364ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01364"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01364 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01364arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1364.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01364ent IS
END c08s05b00x00p03n01i01364ent;
ARCHITECTURE c08s05b00x00p03n01i01364arch OF c08s05b00x00p03n01i01364ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01364"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01364 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01364arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1364.vhd,v 1.2 2001-10-26 16:29:40 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s05b00x00p03n01i01364ent IS
END c08s05b00x00p03n01i01364ent;
ARCHITECTURE c08s05b00x00p03n01i01364arch OF c08s05b00x00p03n01i01364ent IS
BEGIN
TESTING: PROCESS
--
-- Define constants for package
--
constant lowb : integer := 1 ;
constant highb : integer := 5 ;
constant lowb_i2 : integer := 0 ;
constant highb_i2 : integer := 1000 ;
constant lowb_p : integer := -100 ;
constant highb_p : integer := 1000 ;
constant lowb_r : real := 0.0 ;
constant highb_r : real := 1000.0 ;
constant lowb_r2 : real := 8.0 ;
constant highb_r2 : real := 80.0 ;
constant c_boolean_1 : boolean := false ;
constant c_boolean_2 : boolean := true ;
--
-- bit
constant c_bit_1 : bit := '0' ;
constant c_bit_2 : bit := '1' ;
-- severity_level
constant c_severity_level_1 : severity_level := NOTE ;
constant c_severity_level_2 : severity_level := WARNING ;
--
-- character
constant c_character_1 : character := 'A' ;
constant c_character_2 : character := 'a' ;
-- integer types
-- predefined
constant c_integer_1 : integer := lowb ;
constant c_integer_2 : integer := highb ;
--
-- user defined integer type
type t_int1 is range 0 to 100 ;
constant c_t_int1_1 : t_int1 := 0 ;
constant c_t_int1_2 : t_int1 := 10 ;
subtype st_int1 is t_int1 range 8 to 60 ;
constant c_st_int1_1 : st_int1 := 8 ;
constant c_st_int1_2 : st_int1 := 9 ;
--
-- physical types
-- predefined
constant c_time_1 : time := 1 ns ;
constant c_time_2 : time := 2 ns ;
--
--
-- floating point types
-- predefined
constant c_real_1 : real := 0.0 ;
constant c_real_2 : real := 1.0 ;
--
-- simple record
type t_rec1 is record
f1 : integer range lowb_i2 to highb_i2 ;
f2 : time ;
f3 : boolean ;
f4 : real ;
end record ;
constant c_t_rec1_1 : t_rec1 :=
(c_integer_1, c_time_1, c_boolean_1, c_real_1) ;
constant c_t_rec1_2 : t_rec1 :=
(c_integer_2, c_time_2, c_boolean_2, c_real_2) ;
subtype st_rec1 is t_rec1 ;
constant c_st_rec1_1 : st_rec1 := c_t_rec1_1 ;
constant c_st_rec1_2 : st_rec1 := c_t_rec1_2 ;
--
-- more complex record
type t_rec2 is record
f1 : boolean ;
f2 : st_rec1 ;
f3 : time ;
end record ;
constant c_t_rec2_1 : t_rec2 :=
(c_boolean_1, c_st_rec1_1, c_time_1) ;
constant c_t_rec2_2 : t_rec2 :=
(c_boolean_2, c_st_rec1_2, c_time_2) ;
subtype st_rec2 is t_rec2 ;
constant c_st_rec2_1 : st_rec2 := c_t_rec2_1 ;
constant c_st_rec2_2 : st_rec2 := c_t_rec2_2 ;
--
-- simple array
type t_arr1 is array (integer range <>) of st_int1 ;
subtype t_arr1_range1 is integer range lowb to highb ;
subtype st_arr1 is t_arr1 (t_arr1_range1) ;
constant c_st_arr1_1 : st_arr1 := (others => c_st_int1_1) ;
constant c_st_arr1_2 : st_arr1 := (others => c_st_int1_2) ;
constant c_t_arr1_1 : st_arr1 := c_st_arr1_1 ;
constant c_t_arr1_2 : st_arr1 := c_st_arr1_2 ;
--
-- more complex array
type t_arr2 is array (integer range <>, boolean range <>) of st_arr1 ;
subtype t_arr2_range1 is integer range lowb to highb ;
subtype t_arr2_range2 is boolean range false to true ;
subtype st_arr2 is t_arr2 (t_arr2_range1, t_arr2_range2);
constant c_st_arr2_1 : st_arr2 := (others => (others => c_st_arr1_1)) ;
constant c_st_arr2_2 : st_arr2 := (others => (others => c_st_arr1_2)) ;
constant c_t_arr2_1 : st_arr2 := c_st_arr2_1 ;
constant c_t_arr2_2 : st_arr2 := c_st_arr2_2 ;
--
-- most complex record
type t_rec3 is record
f1 : boolean ;
f2 : st_rec2 ;
f3 : st_arr2 ;
end record ;
constant c_t_rec3_1 : t_rec3 :=
(c_boolean_1, c_st_rec2_1, c_st_arr2_1) ;
constant c_t_rec3_2 : t_rec3 :=
(c_boolean_2, c_st_rec2_2, c_st_arr2_2) ;
subtype st_rec3 is t_rec3 ;
constant c_st_rec3_1 : st_rec3 := c_t_rec3_1 ;
constant c_st_rec3_2 : st_rec3 := c_t_rec3_2 ;
--
-- most complex array
type t_arr3 is array (integer range <>, boolean range <>) of st_rec3 ;
subtype t_arr3_range1 is integer range lowb to highb ;
subtype t_arr3_range2 is boolean range true downto false ;
subtype st_arr3 is t_arr3 (t_arr3_range1, t_arr3_range2) ;
constant c_st_arr3_1 : st_arr3 := (others => (others => c_st_rec3_1)) ;
constant c_st_arr3_2 : st_arr3 := (others => (others => c_st_rec3_2)) ;
constant c_t_arr3_1 : st_arr3 := c_st_arr3_1 ;
constant c_t_arr3_2 : st_arr3 := c_st_arr3_2 ;
--
variable v_st_arr1 : st_arr1 := c_st_arr1_1 ;
--
BEGIN
v_st_arr1(st_arr1'Left) :=
c_st_arr1_2(st_arr1'Right) ;
assert NOT(v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***PASSED TEST: c08s05b00x00p03n01i01364"
severity NOTE;
assert (v_st_arr1(st_arr1'Left) = c_st_int1_2)
report "***FAILED TEST: c08s05b00x00p03n01i01364 - The types of the variable and the assigned variable must match."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s05b00x00p03n01i01364arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_2;
USE floating_point_v7_1_2.floating_point_v7_1_2;
ENTITY doHistStretch_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END doHistStretch_ap_fmul_2_max_dsp_32;
ARCHITECTURE doHistStretch_ap_fmul_2_max_dsp_32_arch OF doHistStretch_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_2 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_2,Vivado 2016.1";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF doHistStretch_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF doHistStretch_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "doHistStretch_ap_fmul_2_max_dsp_32,floating_point_v7_1_2,{x_ipProduct=Vivado 2016.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=zynq,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0," &
"C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_TH" &
"ROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_2
GENERIC MAP (
C_XDEVICEFAMILY => "zynq",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END doHistStretch_ap_fmul_2_max_dsp_32_arch;
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "TRI_PORT_X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
--remove this part if you are using behavioral ram
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0)
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni, ram_data_r_uart,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address) or (ram_address_late = NI_reconfiguration_address)
or (ram_address_late = NI_self_diagnosis_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address) or (ram_address_late = NI_reconfiguration_address)
or (ram_address_late = NI_self_diagnosis_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
--ramgen_tri: if memory_type = "TRI_PORT_X" generate
-- u2_ramgen: ram
-- generic map (memory_type => memory_type, stim_file => stim_file)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
ramgen_tri: if memory_type = "TRI_PORT_X" generate
u2_ramgen: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r,
IJTAG_select => IJTAG_select,
IJTAG_clk => IJTAG_clk,
IJTAG_reset => IJTAG_reset,
IJTAG_enable => IJTAG_enable,
IJTAG_write_byte_enable => IJTAG_write_byte_enable,
IJTAG_address => IJTAG_address,
IJTAG_data_write => IJTAG_data_write,
IJTAG_data_read => IJTAG_data_read );
end generate;
-- ramgen_xil: if memory_type = "XILINX_16X" generate
-- node_0: -- node_0:
-- if current_address = 0 generate
-- u2_ram: entity work.ram_0 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
-- node_1: -- node_1:
-- if current_address = 1 generate
-- u2_ram: entity work.ram_1 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
--
-- node_2: -- node_2:
-- if current_address = 2 generate
-- u2_ram: entity work.ram_2 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
--
-- node_3: -- node_3:
-- if current_address = 3 generate
-- u2_ram: entity work.ram_3 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
-- end generate;
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail,
reg_enable =>ram_enable,
reg_write_byte_enable =>ram_byte_we,
reg_address =>ram_address,
reg_data_write =>ram_data_w,
reg_data_read =>ram_data_r_uart);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address)
port map (clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
-- fault information signals from the router
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "TRI_PORT_X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
--remove this part if you are using behavioral ram
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0)
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni, ram_data_r_uart,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address) or (ram_address_late = NI_reconfiguration_address)
or (ram_address_late = NI_self_diagnosis_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address) or (ram_address_late = NI_reconfiguration_address)
or (ram_address_late = NI_self_diagnosis_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
--ramgen_tri: if memory_type = "TRI_PORT_X" generate
-- u2_ramgen: ram
-- generic map (memory_type => memory_type, stim_file => stim_file)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
ramgen_tri: if memory_type = "TRI_PORT_X" generate
u2_ramgen: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r,
IJTAG_select => IJTAG_select,
IJTAG_clk => IJTAG_clk,
IJTAG_reset => IJTAG_reset,
IJTAG_enable => IJTAG_enable,
IJTAG_write_byte_enable => IJTAG_write_byte_enable,
IJTAG_address => IJTAG_address,
IJTAG_data_write => IJTAG_data_write,
IJTAG_data_read => IJTAG_data_read );
end generate;
-- ramgen_xil: if memory_type = "XILINX_16X" generate
-- node_0: -- node_0:
-- if current_address = 0 generate
-- u2_ram: entity work.ram_0 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
-- node_1: -- node_1:
-- if current_address = 1 generate
-- u2_ram: entity work.ram_1 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
--
-- node_2: -- node_2:
-- if current_address = 2 generate
-- u2_ram: entity work.ram_2 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
--
-- node_3: -- node_3:
-- if current_address = 3 generate
-- u2_ram: entity work.ram_3 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
-- end generate;
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail,
reg_enable =>ram_enable,
reg_write_byte_enable =>ram_byte_we,
reg_address =>ram_address,
reg_data_write =>ram_data_w,
reg_data_read =>ram_data_r_uart);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address)
port map (clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
-- fault information signals from the router
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- This entity combines the CPU core with memory and a UART.
--
-- Memory Map:
-- 0x00000000 - 0x0000ffff Internal RAM (8KB)
-- 0x10000000 - 0x100fffff External RAM (1MB)
-- Access all Misc registers with 32-bit accesses
-- 0x20000000 Uart Write (will pause CPU if busy)
-- 0x20000000 Uart Read
-- 0x20000010 IRQ Mask
-- 0x20000020 IRQ Status
-- 0x20000030 GPIO0 Out Set bits
-- 0x20000040 GPIO0 Out Clear bits
-- 0x20000050 GPIOA In
-- 0x20000060 Counter
-- 0x20000070 Ethernet transmit count
-- IRQ bits:
-- 7 GPIO31
-- 6 ^GPIO31
-- 5 EthernetSendDone
-- 4 EthernetReceive
-- 3 Counter(18)
-- 2 ^Counter(18)
-- 1 ^UartWriteBusy
-- 0 UartDataAvailable
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been instantiated!
-- * some changes has been applied to the ports of the CPU to facilitate the new NI!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.mlite_pack.all;
entity plasma is
generic(memory_type : string := "TRI_PORT_X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 0;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
--remove this part if you are using behavioral ram
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0)
);
end; --entity plasma
architecture logic of plasma is
signal address_next : std_logic_vector(31 downto 2);
signal byte_we_next : std_logic_vector(3 downto 0);
signal cpu_address : std_logic_vector(31 downto 0);
signal cpu_byte_we : std_logic_vector(3 downto 0);
signal cpu_data_w : std_logic_vector(31 downto 0);
signal cpu_data_r : std_logic_vector(31 downto 0);
signal cpu_pause : std_logic;
signal data_read_uart : std_logic_vector(7 downto 0);
signal write_enable : std_logic;
signal eth_pause_in : std_logic;
signal eth_pause : std_logic;
signal mem_busy : std_logic;
signal enable_misc : std_logic;
signal enable_uart : std_logic;
signal enable_uart_read : std_logic;
signal enable_uart_write : std_logic;
signal enable_eth : std_logic;
signal gpio0_reg : std_logic_vector(31 downto 0);
signal uart_write_busy : std_logic;
signal uart_data_avail : std_logic;
signal irq_mask_reg : std_logic_vector(7 downto 0);
signal irq_status : std_logic_vector(7 downto 0);
signal irq : std_logic;
signal irq_eth_rec : std_logic;
signal irq_eth_send : std_logic;
signal counter_reg : std_logic_vector(31 downto 0);
signal ram_enable : std_logic;
signal ram_byte_we : std_logic_vector(3 downto 0);
signal ram_address, ram_address_late : std_logic_vector(31 downto 2);
signal ram_data_w : std_logic_vector(31 downto 0);
signal ram_data_r, ram_data_r_ni, ram_data_r_uart : std_logic_vector(31 downto 0);
signal NI_irq_out : std_logic;
--signal NI_read_flag : std_logic;
--signal NI_write_flag : std_logic;
signal cache_access : std_logic;
signal cache_checking : std_logic;
signal cache_miss : std_logic;
signal cache_hit : std_logic;
begin --architecture
write_enable <= '1' when cpu_byte_we /= "0000" else '0';
mem_busy <= eth_pause or mem_pause_in;
cache_hit <= cache_checking and not cache_miss;
cpu_pause <= (uart_write_busy and enable_uart and write_enable) or --UART busy
cache_miss or --Cache wait
(cpu_address(28) and not cache_hit and mem_busy); --DDR or flash
irq_status <= gpioA_in(31) & not gpioA_in(31) &
irq_eth_send & irq_eth_rec &
counter_reg(18) & not counter_reg(18) &
not uart_write_busy & uart_data_avail;
irq <= '1' when ((irq_status and irq_mask_reg) /= ZERO(7 downto 0) or (NI_irq_out = '1')) else '0'; -- modified by Behrad
gpio0_out(31 downto 29) <= gpio0_reg(31 downto 29);
gpio0_out(23 downto 0) <= gpio0_reg(23 downto 0);
enable_misc <= '1' when cpu_address(30 downto 28) = "010" else '0';
enable_uart <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0000" else '0';
enable_uart_read <= enable_uart and not write_enable;
enable_uart_write <= enable_uart and write_enable;
enable_eth <= '1' when enable_misc = '1' and cpu_address(7 downto 4) = "0111" else '0';
cpu_address(1 downto 0) <= "00";
u1_cpu: mlite_cpu
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset_in => reset,
intr_in => irq,
--NI_read_flag => NI_read_flag,
--NI_write_flag => NI_write_flag,
address_next => address_next, --before rising_edge(clk)
byte_we_next => byte_we_next,
address => cpu_address(31 downto 2), --after rising_edge(clk)
byte_we => cpu_byte_we,
data_w => cpu_data_w,
data_r => cpu_data_r,
mem_pause => cpu_pause);
opt_cache: if use_cache = '0' generate
cache_access <= '0';
cache_checking <= '0';
cache_miss <= '0';
end generate;
opt_cache2: if use_cache = '1' generate
--Control 4KB unified cache that uses the upper 4KB of the 8KB
--internal RAM. Only lowest 2MB of DDR is cached.
u_cache: cache
generic map (memory_type => memory_type)
PORT MAP (
clk => clk,
reset => reset,
address_next => address_next,
byte_we_next => byte_we_next,
cpu_address => cpu_address(31 downto 2),
mem_busy => mem_busy,
cache_access => cache_access, --access 4KB cache
cache_checking => cache_checking, --checking if cache hit
cache_miss => cache_miss); --cache miss
end generate; --opt_cache2
no_ddr_start <= not eth_pause and cache_checking;
no_ddr_stop <= not eth_pause and cache_miss;
eth_pause_in <= mem_pause_in or (not eth_pause and cache_miss and not cache_checking);
misc_proc: process(clk, reset, cpu_address, enable_misc,
ram_data_r, ram_address_late, ram_data_r_ni, ram_data_r_uart,
data_read, data_read_uart, cpu_pause,
irq_mask_reg, irq_status, gpio0_reg, write_enable,
cache_checking,
gpioA_in, counter_reg, cpu_data_w)
begin
case cpu_address(30 downto 28) is
when "000" => --internal RAM
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address) or (ram_address_late = NI_reconfiguration_address)
or (ram_address_late = NI_self_diagnosis_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r;
end if;
when "001" => --external RAM
if cache_checking = '1' then
--cpu_data_r <= ram_data_r; --cache
if ((ram_address_late = NI_reserved_data_address) or (ram_address_late = NI_flag_address)
or (ram_address_late = NI_counter_address) or (ram_address_late = NI_reconfiguration_address)
or (ram_address_late = NI_self_diagnosis_address)) then
cpu_data_r <= ram_data_r_ni;
elsif ram_address_late = uart_count_value_address then
cpu_data_r <= ram_data_r_uart;
else
cpu_data_r <= ram_data_r; --cache
end if;
else
cpu_data_r <= data_read; --DDR
end if;
when "010" => --misc
case cpu_address(6 downto 4) is
when "000" => --uart
cpu_data_r <= ZERO(31 downto 8) & data_read_uart;
when "001" => --irq_mask
cpu_data_r <= ZERO(31 downto 8) & irq_mask_reg;
when "010" => --irq_status
cpu_data_r <= ZERO(31 downto 8) & irq_status;
when "011" => --gpio0
cpu_data_r <= gpio0_reg;
when "101" => --gpioA
cpu_data_r <= gpioA_in;
when "110" => --counter
cpu_data_r <= counter_reg;
when others =>
cpu_data_r <= gpioA_in;
end case;
when "011" => --flash
cpu_data_r <= data_read;
when others =>
cpu_data_r <= ZERO;
end case;
if reset = '1' then
irq_mask_reg <= ZERO(7 downto 0);
gpio0_reg <= ZERO;
counter_reg <= ZERO;
elsif rising_edge(clk) then
counter_reg <= bv_inc(counter_reg);
if cpu_pause = '0' then
if enable_misc = '1' and write_enable = '1' then
if cpu_address(6 downto 4) = "001" then
irq_mask_reg <= cpu_data_w(7 downto 0);
elsif cpu_address(6 downto 4) = "011" then
gpio0_reg <= gpio0_reg or cpu_data_w;
elsif cpu_address(6 downto 4) = "100" then
gpio0_reg <= gpio0_reg and not cpu_data_w;
elsif cpu_address(6 downto 4) = "110" then
counter_reg <= cpu_data_w;
end if;
end if;
end if;
end if;
end process;
process(ram_address, reset, clk)begin
if reset = '1' then
ram_address_late <= (others => '0');
elsif clk'event and clk = '1' then
ram_address_late <= ram_address;
end if;
end process;
ram_proc: process(cache_access, cache_miss,
address_next, cpu_address,
byte_we_next, cpu_data_w, data_read)
begin
if cache_access = '1' then --Check if cache hit or write through
ram_enable <= '1';
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & address_next(11 downto 2);
ram_data_w <= cpu_data_w;
elsif cache_miss = '1' then --Update cache after cache miss
ram_enable <= '1';
ram_byte_we <= "1111";
ram_address(31 downto 2) <= ZERO(31 downto 16) &
"0001" & cpu_address(11 downto 2);
ram_data_w <= data_read;
else --Normal non-cache access
if address_next(30 downto 28) = "000" then
ram_enable <= '1';
else
ram_enable <= '0';
end if;
ram_byte_we <= byte_we_next;
ram_address(31 downto 2) <= address_next(31 downto 2);
ram_data_w <= cpu_data_w;
end if;
end process;
--ramgen_tri: if memory_type = "TRI_PORT_X" generate
-- u2_ramgen: ram
-- generic map (memory_type => memory_type, stim_file => stim_file)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
ramgen_tri: if memory_type = "TRI_PORT_X" generate
u2_ramgen: ram
generic map (memory_type => memory_type, stim_file => stim_file)
port map (
clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r,
IJTAG_select => IJTAG_select,
IJTAG_clk => IJTAG_clk,
IJTAG_reset => IJTAG_reset,
IJTAG_enable => IJTAG_enable,
IJTAG_write_byte_enable => IJTAG_write_byte_enable,
IJTAG_address => IJTAG_address,
IJTAG_data_write => IJTAG_data_write,
IJTAG_data_read => IJTAG_data_read );
end generate;
-- ramgen_xil: if memory_type = "XILINX_16X" generate
-- node_0: -- node_0:
-- if current_address = 0 generate
-- u2_ram: entity work.ram_0 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
-- node_1: -- node_1:
-- if current_address = 1 generate
-- u2_ram: entity work.ram_1 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
--
-- node_2: -- node_2:
-- if current_address = 2 generate
-- u2_ram: entity work.ram_2 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
--
--
-- node_3: -- node_3:
-- if current_address = 3 generate
-- u2_ram: entity work.ram_3 generic map (memory_type => memory_type)
-- port map (
-- clk => clk,
-- reset => reset,
-- enable => ram_enable,
-- write_byte_enable => ram_byte_we,
-- address => ram_address,
-- data_write => ram_data_w,
-- data_read => ram_data_r);
-- end generate;
-- end generate;
u3_uart: uart
generic map (log_file => log_file)
port map(
clk => clk,
reset => reset,
enable_read => enable_uart_read,
enable_write => enable_uart_write,
data_in => cpu_data_w(7 downto 0),
data_out => data_read_uart,
uart_read => uart_read,
uart_write => uart_write,
busy_write => uart_write_busy,
data_avail => uart_data_avail,
reg_enable =>ram_enable,
reg_write_byte_enable =>ram_byte_we,
reg_address =>ram_address,
reg_data_write =>ram_data_w,
reg_data_read =>ram_data_r_uart);
dma_gen: if ethernet = '0' generate
address <= cpu_address(31 downto 2);
byte_we <= cpu_byte_we;
data_write <= cpu_data_w;
eth_pause <= '0';
gpio0_out(28 downto 24) <= ZERO(28 downto 24);
irq_eth_rec <= '0';
irq_eth_send <= '0';
end generate;
dma_gen2: if ethernet = '1' generate
u4_eth: eth_dma
port map(
clk => clk,
reset => reset,
enable_eth => gpio0_reg(24),
select_eth => enable_eth,
rec_isr => irq_eth_rec,
send_isr => irq_eth_send,
address => address, --to DDR
byte_we => byte_we,
data_write => data_write,
data_read => data_read,
pause_in => eth_pause_in,
mem_address => cpu_address(31 downto 2), --from CPU
mem_byte_we => cpu_byte_we,
data_w => cpu_data_w,
pause_out => eth_pause,
E_RX_CLK => gpioA_in(20),
E_RX_DV => gpioA_in(19),
E_RXD => gpioA_in(18 downto 15),
E_TX_CLK => gpioA_in(14),
E_TX_EN => gpio0_out(28),
E_TXD => gpio0_out(27 downto 24));
end generate;
u4_ni: NI
generic map(current_address => current_address)
port map (clk => clk,
reset => reset,
enable => ram_enable,
write_byte_enable => ram_byte_we,
address => ram_address,
data_write => ram_data_w,
data_read => ram_data_r_ni,
irq_out => NI_irq_out,
credit_in => credit_in,
valid_out => valid_out,
TX => TX,
credit_out => credit_out,
valid_in => valid_in,
RX => RX,
-- fault information signals from the router
link_faults => link_faults,
turn_faults => turn_faults,
Rxy_reconf_PE => Rxy_reconf_PE,
Cx_reconf_PE => Cx_reconf_PE,
Reconfig_command => Reconfig_command
);
end; --architecture logic
|
-- NEED RESULT: ARCH00399.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00399.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00399: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: ARCH00399: Inertial semantics check on a concurrent signal asg passed
-- NEED RESULT: P2: Inertial transactions completed entirely passed
-- NEED RESULT: P1: Inertial transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00399
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.5 (3)
-- 9.5.2 (1)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00399(ARCH00399)
-- ENT00399_Test_Bench(ARCH00399_Test_Bench)
--
-- REVISION HISTORY:
--
-- 30-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00399 is
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
end ENT00399 ;
--
--
architecture ARCH00399 of ENT00399 is
subtype chk_time_type is Time ;
signal s_st_arr2_vector_savt : chk_time_type := 0 ns ;
signal s_st_arr3_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr2_vector_cnt : chk_cnt_type := 0 ;
signal s_st_arr3_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 6 ;
signal st_arr2_vector_select : select_type := 1 ;
signal st_arr3_vector_select : select_type := 1 ;
--
begin
CHG1 :
process
variable correct : boolean ;
begin
case s_st_arr2_vector_cnt is
when 0
=> null ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00399.P1" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr2_vector_select <= transport 2 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr2_vector_select <= transport 3 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_1(lowb)(highb,false) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 4 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_1(lowb)(highb,false) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 5 ;
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
-- c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_2(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr2_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr2_vector(lowb)(highb,false) <=
-- c_st_arr2_vector_1(lowb)(highb,false) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr2_vector(lowb)(highb,false) =
c_st_arr2_vector_1(lowb)(highb,false) and
(s_st_arr2_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00399" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr2_vector_savt <= transport Std.Standard.Now ;
chk_st_arr2_vector <= transport s_st_arr2_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr2_vector_cnt <= transport s_st_arr2_vector_cnt + 1 ;
wait until (not s_st_arr2_vector(lowb)(highb,false)'Quiet) and
(s_st_arr2_vector_savt /= Std.Standard.Now) ;
--
end process CHG1 ;
--
PGEN_CHKP_1 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions completed entirely",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr2_vector_select select
s_st_arr2_vector(lowb)(highb,false) <=
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns
when 1,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 2,
--
c_st_arr2_vector_1(lowb)(highb,false) after 5 ns
when 3,
--
c_st_arr2_vector_1(lowb)(highb,false) after 100 ns
when 4,
--
c_st_arr2_vector_2(lowb)(highb,false) after 10 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 20 ns ,
c_st_arr2_vector_2(lowb)(highb,false) after 30 ns ,
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr2_vector_1(lowb)(highb,false) after 40 ns when 6 ;
--
CHG2 :
process
variable correct : boolean ;
begin
case s_st_arr3_vector_cnt is
when 0
=> null ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00399.P2" ,
"Multi inertial transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
st_arr3_vector_select <= transport 2 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
st_arr3_vector_select <= transport 3 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_1(highb)(lowb,true) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_vector_select <= transport 4 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_1(highb)(lowb,true) after 100 ns ;
--
when 5
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
st_arr3_vector_select <= transport 5 ;
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
-- c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 6
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_2(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"One inertial transaction occurred on a " &
"concurrent signal asg",
correct ) ;
st_arr3_vector_select <= transport 6 ;
-- Last transaction above is marked
-- s_st_arr3_vector(highb)(lowb,true) <=
-- c_st_arr3_vector_1(highb)(lowb,true) after 40 ns ;
--
when 7
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct :=
correct and
s_st_arr3_vector(highb)(lowb,true) =
c_st_arr3_vector_1(highb)(lowb,true) and
(s_st_arr3_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00399" ,
"Inertial semantics check on a concurrent " &
"signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00399" ,
"Inertial semantics check on a concurrent " &
"signal asg",
false ) ;
--
end case ;
--
s_st_arr3_vector_savt <= transport Std.Standard.Now ;
chk_st_arr3_vector <= transport s_st_arr3_vector_cnt
after (1 us - Std.Standard.Now) ;
s_st_arr3_vector_cnt <= transport s_st_arr3_vector_cnt + 1 ;
wait until (not s_st_arr3_vector(highb)(lowb,true)'Quiet) and
(s_st_arr3_vector_savt /= Std.Standard.Now) ;
--
end process CHG2 ;
--
PGEN_CHKP_2 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions completed entirely",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
--
with st_arr3_vector_select select
s_st_arr3_vector(highb)(lowb,true) <=
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns
when 1,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 2,
--
c_st_arr3_vector_1(highb)(lowb,true) after 5 ns
when 3,
--
c_st_arr3_vector_1(highb)(lowb,true) after 100 ns
when 4,
--
c_st_arr3_vector_2(highb)(lowb,true) after 10 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 20 ns ,
c_st_arr3_vector_2(highb)(lowb,true) after 30 ns ,
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns
when 5,
--
-- Last transaction above is marked
c_st_arr3_vector_1(highb)(lowb,true) after 40 ns when 6 ;
--
end ARCH00399 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00399_Test_Bench is
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
end ENT00399_Test_Bench ;
--
--
architecture ARCH00399_Test_Bench of ENT00399_Test_Bench is
begin
L1:
block
component UUT
port (
s_st_arr2_vector : inout st_arr2_vector
; s_st_arr3_vector : inout st_arr3_vector
) ;
end component ;
--
for CIS1 : UUT use entity WORK.ENT00399 ( ARCH00399 ) ;
begin
CIS1 : UUT
port map (
s_st_arr2_vector
, s_st_arr3_vector
)
;
end block L1 ;
end ARCH00399_Test_Bench ;
|
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
--MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
--copies of the Software, and to permit persons to whom the Software is
--furnished to do so, subject to the following conditions:
--
--The above copyright notice and this permission notice shall be included in all
--copies or substantial portions of the Software.
--
--THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
--IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
--FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
--AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
--LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
--OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
--SOFTWARE.
-- ############################################################################
-- The official specifications of the SHA-256 algorithm can be found here:
-- http://nvlpubs.nist.gov/nistpubs/FIPS/NIST.FIPS.180-4.pdf
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package sha_512_pkg is
constant WORD_SIZE : natural := 64; --SHA-512 uses 64-bit words
--array types for SHA-512
type K_DATA is array (0 to 79) of std_logic_vector(WORD_SIZE-1 downto 0);
type M_DATA is array (0 to 15) of std_logic_vector(WORD_SIZE-1 downto 0);
type H_DATA is array (0 to 7) of std_logic_vector(WORD_SIZE-1 downto 0);
--Message blocks, the padded message should be a multiple of 512 bits,
signal M : M_DATA;
--function definitions
function ROTR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector;
function ROTL (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector;
function SHR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector;
function CH (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function MAJ (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_UCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_UCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_LCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
function SIGMA_LCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector;
end package;
package body sha_512_pkg is
function ROTR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector is
--result : std_logic_vector(WORD_SIZE-1 downto 0);
begin
--signal result : std_logic_vector(WORD_SIZE-1 downto 0);
return (std_logic_vector(shift_right(unsigned(a), n))) or std_logic_vector((shift_left(unsigned(a), (WORD_SIZE-n))));
end function;
function ROTL (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector is
--result : std_logic_vector(WORD_SIZE-1 downto 0);
begin
--signal result : std_logic_vector(WORD_SIZE-1 downto 0);
return (std_logic_vector(shift_left(unsigned(a), n))) or std_logic_vector((shift_right(unsigned(a), (WORD_SIZE-n))));
end function;
function SHR (a : std_logic_vector(WORD_SIZE-1 downto 0); n : natural)
return std_logic_vector is
begin
return std_logic_vector(shift_right(unsigned(a), n));
end function;
function CH (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return (x and y) xor (not(x) and z);
end function;
function MAJ (x : std_logic_vector(WORD_SIZE-1 downto 0);
y : std_logic_vector(WORD_SIZE-1 downto 0);
z : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return (x and y) xor (x and z) xor (y and z);
end function;
function SIGMA_UCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 28) xor ROTR(x, 34) xor ROTR(x, 39);
end function;
function SIGMA_UCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 14) xor ROTR(x, 18) xor ROTR(x, 41);
end function;
function SIGMA_LCASE_0 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 1) xor ROTR(x, 8) xor SHR(x, 7);
end function;
function SIGMA_LCASE_1 (x : std_logic_vector(WORD_SIZE-1 downto 0))
return std_logic_vector is
begin
return ROTR(x, 19) xor ROTR(x, 61) xor SHR(x, 6);
end function;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1657.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01657ent IS
END c09s01b00x00p02n01i01657ent;
ARCHITECTURE c09s01b00x00p02n01i01657arch OF c09s01b00x00p02n01i01657ent IS
BEGIN
lab : block ( ) --guard condition must not be empty
begin
end block lab;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01657 - Guard condition must not be empty."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01657arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1657.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01657ent IS
END c09s01b00x00p02n01i01657ent;
ARCHITECTURE c09s01b00x00p02n01i01657arch OF c09s01b00x00p02n01i01657ent IS
BEGIN
lab : block ( ) --guard condition must not be empty
begin
end block lab;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01657 - Guard condition must not be empty."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01657arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1657.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c09s01b00x00p02n01i01657ent IS
END c09s01b00x00p02n01i01657ent;
ARCHITECTURE c09s01b00x00p02n01i01657arch OF c09s01b00x00p02n01i01657ent IS
BEGIN
lab : block ( ) --guard condition must not be empty
begin
end block lab;
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c09s01b00x00p02n01i01657 - Guard condition must not be empty."
severity ERROR;
wait;
END PROCESS TESTING;
END c09s01b00x00p02n01i01657arch;
|
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- H_i_calculator.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
-- DS_bitcoin_miner is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
library ieee;
use ieee.std_logic_1164.all; -- std_logic
entity H_i_calculator is
port (
H_iminus1_A,
H_iminus1_B,
H_iminus1_C,
H_iminus1_D,
H_iminus1_E,
H_iminus1_F,
H_iminus1_G,
H_iminus1_H : in std_ulogic_vector(31 downto 0); -- intermediate hash value H_(i-1)
A_i,
B_i,
C_i,
D_i,
E_i,
F_i,
G_i,
H_i : in std_ulogic_vector(31 downto 0); -- A-F registers values
H_i_A,
H_i_B,
H_i_C,
H_i_D,
H_i_E,
H_i_F,
H_i_G,
H_i_H : out std_ulogic_vector(31 downto 0) -- resulting hash value H_(i)
);
end entity H_i_calculator;
architecture rtl of H_i_calculator is
begin
Hcalc_claA : entity work.cla
generic map (
n => 32
)
port map (
x => A_i,
y => H_iminus1_A,
sum => H_i_A,
cout => open
);
Hcalc_claB : entity work.cla
generic map (
n => 32
)
port map (
x => B_i,
y => H_iminus1_B,
sum => H_i_B,
cout => open
);
Hcalc_claC : entity work.cla
generic map (
n => 32
)
port map (
x => C_i,
y => H_iminus1_C,
sum => H_i_C,
cout => open
);
Hcalc_claD : entity work.cla
generic map (
n => 32
)
port map (
x => D_i,
y => H_iminus1_D,
sum => H_i_D,
cout => open
);
Hcalc_claE : entity work.cla
generic map (
n => 32
)
port map (
x => E_i,
y => H_iminus1_E,
sum => H_i_E,
cout => open
);
Hcalc_claF : entity work.cla
generic map (
n => 32
)
port map (
x => F_i,
y => H_iminus1_F,
sum => H_i_F,
cout => open
);
Hcalc_claG : entity work.cla
generic map (
n => 32
)
port map (
x => G_i,
y => H_iminus1_G,
sum => H_i_G,
cout => open
);
Hcalc_claH : entity work.cla
generic map (
n => 32
)
port map (
x => H_i,
y => H_iminus1_H,
sum => H_i_H,
cout => open
);
end architecture rtl; |
--###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
--#
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_COMPARE is
end tb_COMPARE;
architecture stimulus of tb_COMPARE is
-- COMPONENTS --
component COMPARE
port(
MCLK : in std_logic;
nRST : in std_logic;
TIC : in std_logic;
COMPLETED : in std_logic;
RESCAN : out std_logic;
XREG : in std_logic_vector(7 downto 0);
YREG : in std_logic_vector(7 downto 0);
ZREG : in std_logic_vector(7 downto 0);
LEDX : out std_logic;
LEDY : out std_logic;
LEDZ : out std_logic;
SIGN : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal TIC : std_logic;
signal COMPLETED : std_logic;
signal RESCAN : std_logic;
signal XREG : std_logic_vector(7 downto 0);
signal YREG : std_logic_vector(7 downto 0);
signal ZREG : std_logic_vector(7 downto 0);
signal LEDX : std_logic;
signal LEDY : std_logic;
signal LEDZ : std_logic;
signal SIGN : std_logic;
--
signal RUNNING : std_logic := '1';
signal counter : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_COMPARE_0 : COMPARE
port map (
MCLK => MCLK,
nRST => nRST,
TIC => TIC,
COMPLETED => COMPLETED,
RESCAN => RESCAN,
XREG => XREG,
YREG => YREG,
ZREG => ZREG,
LEDX => LEDX,
LEDY => LEDY,
LEDZ => LEDZ,
SIGN => SIGN
);
TIC <= counter(7) and counter(5); -- 2.56 + 0.64 uS (~300 khz ) for ~100 kbit
GEN: process(MCLK, nRST)
begin
if (nRST = '0') then
counter <= (others=>'0');
elsif (MCLK'event and MCLK='1') then
if (TIC = '1') then
counter <= (others=>'0');
else
counter <= std_logic_vector(to_unsigned(to_integer(unsigned( counter )) + 1, 8));
end if;
end if;
end process GEN;
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
begin
nRST <= '0';
XREG <= "00000000";
YREG <= "10000000";
ZREG <= "10000001";
COMPLETED <= '1';
wait for 1000 ns;
nRST <= '1';
wait for 4000 ns;
XREG <= "00000001";
YREG <= "00000010";
ZREG <= "00000011";
wait for 4000 ns;
XREG <= "10000001";
YREG <= "10000010";
ZREG <= "10000011";
wait for 4000 ns;
RUNNING <= '0';
wait;
end process GO;
end stimulus;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ***
--*** DP_RSFTPIPE64X64.VHD ***
--*** ***
--*** Function: Pipelined Right Shift ***
--*** (max 64.0 to 1.52) ***
--*** ***
--*** 07/12/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 29/07/09 - signed number problem fixed ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_rsftpipe64x64 IS
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1);
shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1);
outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1)
);
END dp_rsftpipe64x64;
ARCHITECTURE rtl of dp_rsftpipe64x64 IS
signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal levtwoff : STD_LOGIC_VECTOR (116 DOWNTO 1);
signal shiftff : STD_LOGIC_VECTOR (6 DOWNTO 5);
BEGIN
levzip <= inbus;
-- unsigned input
gla: FOR k IN 1 TO 113 GENERATE
levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR
(levzip(k+2) AND shift(2) AND NOT(shift(1))) OR
(levzip(k+3) AND shift(2) AND shift(1));
END GENERATE;
-- 29/07/65 always shift 116, else will fill with zeros
-- fixed here and other lines
levone(114) <= (levzip(114) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(115) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(115) <= (levzip(115) AND NOT(shift(2)) AND NOT(shift(1))) OR
(levzip(116) AND NOT(shift(2)) AND shift(1)) OR
(levzip(116) AND shift(2) AND NOT(shift(1))) OR
(levzip(116) AND shift(2) AND shift(1));
levone(116) <= levzip(116);
glba: FOR k IN 1 TO 104 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(k+12) AND shift(4) AND shift(3));
END GENERATE;
glbb: FOR k IN 105 TO 108 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(k+8) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbc: FOR k IN 109 TO 112 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(k+4) AND NOT(shift(4)) AND shift(3)) OR
(levone(116) AND shift(4) AND NOT(shift(3))) OR
(levone(116) AND shift(4) AND shift(3));
END GENERATE;
glbd: FOR k IN 113 TO 116 GENERATE
levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR
(levone(116) AND (shift(4) OR shift(3)));
END GENERATE;
pp: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 116 LOOP
levtwoff(k) <= '0';
END LOOP;
shiftff <= "00";
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
levtwoff <= levtwo;
shiftff <= shift(6 DOWNTO 5);
END IF;
END IF;
END PROCESS;
glca: FOR k IN 1 TO 66 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(k+48) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcb: FOR k IN 67 TO 84 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shift(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shift(5)) OR
(levtwoff(k+32) AND shiftff(6) AND NOT(shift(5))) OR
(levtwoff(116) AND shiftff(6) AND shift(5));
END GENERATE;
glcc: FOR k IN 85 TO 100 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(k+16) AND NOT(shiftff(6)) AND shiftff(5)) OR
(levtwoff(116) AND shiftff(6) AND NOT(shiftff(5))) OR
(levtwoff(116) AND shiftff(6) AND shiftff(5));
END GENERATE;
glcd: FOR k IN 101 TO 116 GENERATE
levthr(k) <= (levtwoff(k) AND NOT(shiftff(6)) AND NOT(shiftff(5))) OR
(levtwoff(116) AND (shiftff(6) OR shiftff(5)));
END GENERATE;
outbus <= levthr;
END rtl;
|
entity tb_slice01 is
end tb_slice01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice01 is
signal rst : std_logic;
signal clk : std_logic;
signal di : std_logic;
signal do : std_logic_vector (3 downto 0);
begin
dut: entity work.slice01
generic map (w => 4)
port map (rst, clk, di, do);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
constant b0 : std_logic_vector (3 downto 0) := "1101";
begin
rst <= '1';
pulse;
rst <= '0';
for i in b0'reverse_range loop
di <= b0 (i);
pulse;
end loop;
assert do = b0 severity error;
wait;
end process;
end behav;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc953.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00953ent IS
END c06s01b00x00p10n01i00953ent;
ARCHITECTURE c06s01b00x00p10n01i00953arch OF c06s01b00x00p10n01i00953ent IS
BEGIN
TESTING: PROCESS
type TWO is range 1 to 2;
type R1 is record
X1: TWO;
RE1: BOOLEAN;
end record;
type A11 is array (TWO, TWO) of R1;
variable V1: BOOLEAN;
variable V4: A11;
BEGIN
V1 := V4(1,2).RE1;
assert NOT(V1 = false)
report "***PASSED TEST: c06s01b00x00p10n01i00953"
severity NOTE;
assert (V1 = false)
report "***FAILED TEST: c06s01b00x00p10n01i00953 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00953arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc953.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00953ent IS
END c06s01b00x00p10n01i00953ent;
ARCHITECTURE c06s01b00x00p10n01i00953arch OF c06s01b00x00p10n01i00953ent IS
BEGIN
TESTING: PROCESS
type TWO is range 1 to 2;
type R1 is record
X1: TWO;
RE1: BOOLEAN;
end record;
type A11 is array (TWO, TWO) of R1;
variable V1: BOOLEAN;
variable V4: A11;
BEGIN
V1 := V4(1,2).RE1;
assert NOT(V1 = false)
report "***PASSED TEST: c06s01b00x00p10n01i00953"
severity NOTE;
assert (V1 = false)
report "***FAILED TEST: c06s01b00x00p10n01i00953 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00953arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc953.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s01b00x00p10n01i00953ent IS
END c06s01b00x00p10n01i00953ent;
ARCHITECTURE c06s01b00x00p10n01i00953arch OF c06s01b00x00p10n01i00953ent IS
BEGIN
TESTING: PROCESS
type TWO is range 1 to 2;
type R1 is record
X1: TWO;
RE1: BOOLEAN;
end record;
type A11 is array (TWO, TWO) of R1;
variable V1: BOOLEAN;
variable V4: A11;
BEGIN
V1 := V4(1,2).RE1;
assert NOT(V1 = false)
report "***PASSED TEST: c06s01b00x00p10n01i00953"
severity NOTE;
assert (V1 = false)
report "***FAILED TEST: c06s01b00x00p10n01i00953 - Prefix of a selected name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s01b00x00p10n01i00953arch;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex6;
constant CFG_MEMTECH : integer := virtex6;
constant CFG_PADTECH : integer := virtex6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 1 + 4*1;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 4;
constant CFG_ATBSZ : integer := 4;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 1;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 16;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020789#;
constant CFG_ETH_ENL : integer := 16#000123#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
constant CFG_GRETH_FT : integer := 0;
constant CFG_GRETH_EDCLFT : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (16);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- I2C master
constant CFG_I2C_ENABLE : integer := 1;
-- VGA and PS2/ interface
constant CFG_KBD_ENABLE : integer := 0;
constant CFG_VGA_ENABLE : integer := 0;
constant CFG_SVGA_ENABLE : integer := 1;
-- AMBA System ACE Interface Controller
constant CFG_GRACECTRL : integer := 1;
-- PCIEXP interface
constant CFG_PCIEXP : integer := 0;
constant CFG_PCIE_TYPE : integer := 0;
constant CFG_PCIE_SIM_MAS : integer := 0;
constant CFG_PCIEXPVID : integer := 16#0#;
constant CFG_PCIEXPDID : integer := 16#0#;
constant CFG_NO_OF_LANES : integer := 1;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
-- Xilinx MIG DDR2 controller
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_CLK4 : integer := 16;
end;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: fifo_32 - Behavioral
--
-- Description: A 32-entry singla-clock FIFO of unknown data width.
--
------------------------------------------------------------------------------------
-- FPGA_Webserver from https://github.com/hamsternz/FPGA_Webserver
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <hamster@snap.net.nz>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity fifo_32 is
port (
clk : in std_logic;
full : out std_logic := '0';
write_en : in std_logic := '0';
data_in : in std_logic_vector := (others => '1');
data_out : out std_logic_vector := (others => '1');
empty : out std_logic := '0';
read_en : in std_logic := '0'
);
end fifo_32;
architecture Behavioral of fifo_32 is
signal i_full : std_logic := '0';
signal i_empty : std_logic := '1';
type mem_array is array(31 downto 0) of std_logic_vector(data_in'high downto 0);
signal memory : mem_array := (others => (others => '0'));
signal wr_ptr : unsigned(4 downto 0) := (others => '0');
signal rd_ptr : unsigned(4 downto 0) := (others => '0');
signal i_data_out : std_logic_vector(data_in'high downto 0) := (others => '0');
begin
full <= i_full;
empty <= i_empty;
data_out <= i_data_out;
flag_proc: process(wr_ptr, rd_ptr)
begin
if wr_ptr = rd_ptr then
i_empty <= '1';
else
i_empty <= '0';
end if;
if wr_ptr+1 = rd_ptr then
i_full <= '1';
else
i_full <= '0';
end if;
end process;
clk_proc: process(clk)
begin
if rising_edge(clk) then
if read_en = '1' then
if write_en = '1' then
if i_empty = '0' then
i_data_out <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr + 1;
end if;
memory(to_integer(wr_ptr)) <= data_in;
wr_ptr <= wr_ptr + 1;
elsif i_empty = '0' then
i_data_out <= memory(to_integer(rd_ptr));
rd_ptr <= rd_ptr + 1;
end if;
elsif write_en = '1' then
if i_full = '0' then
memory(to_integer(wr_ptr)) <= data_in;
wr_ptr <= wr_ptr + 1;
end if;
end if;
end if;
end process;
end Behavioral;
|
package foo is new bar;
|
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ghdl_test is
end entity tb_ghdl_test;
architecture tb of tb_ghdl_test is
begin
p_test : process is
file f_in : text;
variable v_line : line;
begin
file_open(f_in, "ghdl_test.txt", read_mode);
while not endfile(f_in) loop
readline(f_in, v_line);
report v_line.all;
end loop;
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:05 11/15/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_RS232_RX.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: RS232_RX
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY tb_RS232_RX IS
END tb_RS232_RX;
ARCHITECTURE behavior OF tb_RS232_RX IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RS232_RX
PORT(
Clk : IN std_logic;
Reset : IN std_logic;
LineRD_in : IN std_logic;
Valid_out : OUT std_logic;
Code_out : OUT std_logic;
Store_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal Clk : std_logic := '0';
signal Reset : std_logic := '0';
signal LineRD_in : std_logic := '1';
--Outputs
signal Valid_out : std_logic;
signal Code_out : std_logic;
signal Store_out : std_logic;
-- Clock period definitions
constant Clk_period : time := 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RS232_RX PORT MAP (
Clk => Clk,
Reset => Reset,
LineRD_in => LineRD_in,
Valid_out => Valid_out,
Code_out => Code_out,
Store_out => Store_out
);
-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc_1: process
begin
Reset <= '0';
wait for 200 ns;
Reset <= '1';
wait for 117800 ns;
end process;
stim_proc_2: process
begin
LineRD_in <= '1',
'0' after 500 ns, -- StartBit
'1' after 9150 ns, -- LSb
'0' after 17800 ns,
'1' after 26450 ns,
'0' after 35100 ns,
'1' after 43750 ns,
'0' after 52400 ns,
'1' after 61050 ns,
'1' after 69700 ns, -- MSb
'0' after 78350 ns, -- Stopbit
'1' after 87000 ns;
wait for 100000 ns;
end process;
END;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- _ ______ ____ ____ __ __ __
-- | |/ / ___| _ \/ ___|| \/ |/ /_
-- | ' / | | |_) \___ \| |\/| | '_ \
-- | . \ |___| __/ ___) | | | | (_) )
-- |_|\_\____|_| |____/|_| |_|\___/
--
--
--
-- KCPSM6 reference design on Xilinx KC705 Evaluation Board (www.xilinx.com).
--
-- XC7K325T-1FFG900 Device
--
-- Ken Chapman - Xilinx Ltd.
--
-- 21st September 2012 - Initial version
-- 9th October 2012 - Corrections to comments
-- 18th March 2013 - Alterations to names of modules.
--
--
-- The primary purpose of this reference design is to illustrate how KCPSM6 can implement
-- the signaling and protocol required to communicate and control an SPI Flash memory
-- that was initially connected to the device to facilitate device configuration.
--
-- The design is based on the standard reference designs provided with KCPSM6 (PicoBlaze).
-- These provide a UART-USB connection allowing messages to be displayed on a terminal and
-- for keyboard entries to allow a degree of control and data input. Please refer to the
-- documentation provided with KCPSM6 and the UART macros if you need to know more about
-- PicoBlaze and UART communication. PicoTerm is also supplied with KCPSM6 and ideally
-- suited to this application so please use it.
--
-- In this example the aim is to communicate with the Micron/Numonyx N25Q128 device on the
-- KC705 board. There will be some items specific to this device and board but it is hoped
-- that this design can be a reference starting point for other arrangements. The design
-- implements a classic 4-wire interface and serial communication. Most of the work is
-- perfomed by KCPSM6 which is defined and described in the PSM code provided. However, the
-- starting point is to set up those four connections.
--
-- The SPI Flash memory is initially connected to the device to facilitate configuration so
-- this leads to a very precise set of pins being used. Obviously this design must use those
-- same pins but whilst three of those pins become regular I/O after configuration the CCLK
-- can only be accessed via the STARTUPE2 primitive so that is a critical part of this design
-- to look out for.
--
-- The SPI interface is formed of the signals listed below...
--
-- spi_clk Clock from FPGA to SPI Flash Pin B10 (CCLK) accessed via STARTUPE2
-- spi_cs_b Chip Select from FPGA to SPI Flash Pin U19 (FCS_B)
-- spi_mosi Data from FPGA to SPI Flash Pin P24 (D00)
-- spi_miso Data from SPI Flash to FPGA Pin R25 (D01/DIN)
--
--
-- IMPORTANT: The KC705 board requirs the 'M0' switch on SW13 to be set to '1' so that
-- the 'spi_cs_b' signal is routed through to the SPI Flash rather than the
-- alternative parallel Flash. For Master SPI configuration the required mode
-- switch setting is M[2:0] = "001" so when the SPI Flash is used to
-- configure the device as well the M0 switch will already be High.
--
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
-------------------------------------------------------------------------------------------
--
--
entity kc705_kcpsm6_spi_flash is
Port ( uart_rx : in std_logic;
uart_tx : out std_logic;
spi_cs_b : out std_logic := '1';
spi_mosi : out std_logic := '0';
spi_miso : in std_logic;
cpu_rst : in std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic);
end kc705_kcpsm6_spi_flash;
--
-------------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of kc705_kcpsm6_spi_flash is
--
-------------------------------------------------------------------------------------------
--
-- Components
--
-------------------------------------------------------------------------------------------
--
--
-- declaration of KCPSM6
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- Development Program Memory
--
component n25q128_spi_uart_bridge
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
component uart_tx6
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
-- UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx6
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
--
-------------------------------------------------------------------------------------------
--
-- Signals
--
-------------------------------------------------------------------------------------------
--
--
--
-- Signals to create and distribute a 100MHz clock from the 200MHz differential input
--
signal clock_divide : std_logic := '0';
signal clk200 : std_logic;
signal clk : std_logic;
--
--
-- Signals used to connect KCPSM6
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal rdl : std_logic;
--
-- Signals used to connect UART_TX6
--
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_logic;
signal uart_tx_data_present : std_logic;
signal uart_tx_half_full : std_logic;
signal uart_tx_full : std_logic;
signal uart_tx_reset : std_logic;
--
-- Signals used to connect UART_RX6
--
signal uart_rx_data_out : std_logic_vector(7 downto 0);
signal read_from_uart_rx : std_logic;
signal uart_rx_data_present : std_logic;
signal uart_rx_half_full : std_logic;
signal uart_rx_full : std_logic;
signal uart_rx_reset : std_logic;
--
-- Signals used to define baud rate
--
signal baud_count : integer range 0 to 53 := 0;
signal en_16_x_baud : std_logic := '0';
--
--
-- Signals for communication with SPI Flash Memory
--
-- An internal signal is required for 'spi_clk' but 'spi_cs_b', 'spi_mosi' and
-- 'spi_miso' are all direct pin connections
--
signal spi_clk : std_logic := '0';
--
--
-------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
-------------------------------------------------------------------------------------------
--
begin
--
-----------------------------------------------------------------------------------------
-- Create 100MHz clock from 200MHz differential input
-----------------------------------------------------------------------------------------
--
-- A simple toggle flip-flop arrangement is used to divide the clock as no phase
-- relationship with the original 200MHz clock is required in this application.
--
--
-- 200MHz differential input clock
--
clk200_input_buffer: IBUFGDS
port map ( I => clk200_p,
IB => clk200_n,
O => clk200);
clock_generation: process(clk200)
begin
if clk200'event and clk200 = '1' then
clock_divide <= not(clock_divide);
end if;
end process clock_generation;
--
-- BUFG to distribute 100MHz clock
--
clock_100mhz_buffer: BUFG
port map ( I => clock_divide,
O => clk);
--
-----------------------------------------------------------------------------------------
-- Instantiate KCPSM6 and connect to program ROM
-----------------------------------------------------------------------------------------
--
-- The generics can be defined as required. In this case the 'hwbuild' value is used to
-- define a version using the ASCII code for the desired letter and the interrupt vector
-- has been set to 7F0 to provide 16 instructions for an Interrupt Service Routine (ISR)
-- before reaching the end of a 2K memory.
--
--
processor: kcpsm6
generic map ( hwbuild => X"42", -- 42 hex is ASCII character "B"
interrupt_vector => X"7F0",
scratch_pad_memory_size => 256)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
--
-- Reset by press button (active Low) or JTAG Loader enabled Program Memory
--
kcpsm6_reset <= rdl or cpu_rst;
--
-- Unused signals tied off until required.
-- Tying to other signals used to minimise warning messages.
--
kcpsm6_sleep <= write_strobe and k_write_strobe; -- Always '0'
interrupt <= interrupt_ack;
--
-- Development Program Memory
-- JTAG Loader enabled for rapid code development.
--
program_rom: n25q128_spi_uart_bridge
generic map( C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 2,
C_JTAG_LOADER_ENABLE => 1)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- SPI Flash Memory interface
-----------------------------------------------------------------------------------------
--
-- The KC705 board has a 128Mbit SPI Flash connected to the appropriate pins necessary
-- for device configuration. The memory is an Micron/Numonyx N25Q128 device.
--
-- To access this SPI Flash device after configuration three of the configuration pins
-- become regular I/O but the clock must reuse CCLK and that is only accessible via the
-- STARTUPE2 primitive defined here.
--
-- The SPI interface is formed of 4 signals which are 'bit-banged' by KCPSM6 to
-- implement all operations.
-- Pins on XC7K325T-1FFG900
-- spi_clk Clock from FPGA to SPI Flash Pin B10 (CCLK) accessed via STARTUPE2
-- spi_cs_b Chip Select from FPGA to SPI Flash Pin U19 (FCS_B)
-- spi_mosi Data from FPGA to SPI Flash Pin P24 (D00)
-- spi_miso Data from SPI Flash to FPGA Pin R25 (D01/DIN)
--
spi_connect: STARTUPE2
generic map( PROG_USR => "FALSE",
SIM_CCLK_FREQ => 0.0)
port map ( CFGCLK => open,
CFGMCLK => open,
EOS => open,
PREQ => open,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '0',
PACK => '0',
USRCCLKO => spi_clk, -- Provide signal to output on CCLK pin
USRCCLKTS => '0', -- Enable CCLK pin
USRDONEO => '1', -- Drive DONE pin High even though tri-state
USRDONETS => '1' ); -- Maintain tri-state of DONE pin
--
-----------------------------------------------------------------------------------------
-- UART Transmitter with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Write to buffer in UART Transmitter at port address 01 hex
--
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => uart_tx_data_present,
buffer_half_full => uart_tx_half_full,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Receiver with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Read from buffer in UART Receiver at port address 01 hex.
--
-- When KCPMS6 reads data from the receiver a pulse must be generated so that the
-- FIFO buffer presents the next character to be read and updates the buffer flags.
--
rx: uart_rx6
port map ( serial_in => uart_rx,
en_16_x_baud => en_16_x_baud,
data_out => uart_rx_data_out,
buffer_read => read_from_uart_rx,
buffer_data_present => uart_rx_data_present,
buffer_half_full => uart_rx_half_full,
buffer_full => uart_rx_full,
buffer_reset => uart_rx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- RS232 (UART) baud rate
-----------------------------------------------------------------------------------------
--
-- To set serial communication baud rate to 115,200 then en_16_x_baud must pulse
-- High at 1,843,200Hz which is every 54.28 cycles at 100MHz. In this implementation
-- a pulse is generated every 54 cycles resulting is a baud rate of 115,741 baud which
-- is only 0.5% high and well within limits.
--
baud_rate: process(clk)
begin
if clk'event and clk = '1' then
if baud_count = 53 then -- counts 54 states including zero
baud_count <= 0;
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_count <= baud_count + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
--
-----------------------------------------------------------------------------------------
-- General Purpose Input Ports.
-----------------------------------------------------------------------------------------
--
-- Two input ports are used with the UART macros. The first is used to monitor the flags
-- on both the UART transmitter and receiver. The second is used to read the data from
-- the UART receiver. Note that the read also requires a 'buffer_read' pulse to be
-- generated.
--
-- This design includes a third input port to read 8 general purpose switches.
--
input_ports: process(clk)
begin
if clk'event and clk = '1' then
case port_id(1 downto 0) is
-- Read UART status at port address 00 hex
when "00" => in_port(0) <= uart_tx_data_present;
in_port(1) <= uart_tx_half_full;
in_port(2) <= uart_tx_full;
in_port(3) <= uart_rx_data_present;
in_port(4) <= uart_rx_half_full;
in_port(5) <= uart_rx_full;
-- Read UART_RX6 data at port address 01 hex
-- (see 'buffer_read' pulse generation below)
when "01" => in_port <= uart_rx_data_out;
-- Unused port address 02 hex
-- when "10" => in_port <= ????;
-- Read SPI serial data MISO at address 03 hex
-- Bit7 used to help with MSB first nature of SPI communication
when "11" => in_port <= spi_miso & "0000000";
-- Don't Care for unsued case(s) ensures minimum logic implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Generate 'buffer_read' pulse following read from port address 01
if (read_strobe = '1') and (port_id(1 downto 0) = "01") then
read_from_uart_rx <= '1';
else
read_from_uart_rx <= '0';
end if;
end if;
end process input_ports;
--
-----------------------------------------------------------------------------------------
-- General Purpose Output Ports
-----------------------------------------------------------------------------------------
--
-- In this design there are two output ports.
-- A simple output port used to output signals to the SPI Flash.
-- A port used to write data directly to the FIFO buffer within 'uart_tx6' macro.
--
output_ports: process(clk)
begin
if clk'event and clk = '1' then
-- 'write_strobe' is used to qualify all writes to general output ports.
if write_strobe = '1' then
-- Signals to SPI Flash Memory at address 04 hex.
-- Bit7 used for MOSI to help with MSB first nature of SPI communication
if port_id(2) = '1' then
spi_clk <= out_port(0);
spi_cs_b <= out_port(1);
spi_mosi <= out_port(7);
end if;
end if;
end if;
end process output_ports;
--
-- Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
-- Note the direct connection of 'out_port' to the UART transmitter macro and the
-- way that a single clock cycle write pulse is generated to capture the data.
--
uart_tx_data_in <= out_port;
write_to_uart_tx <= '1' when (write_strobe = '1') and (port_id(0) = '1')
else '0';
--
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
constant_output_ports: process(clk)
begin
if clk'event and clk = '1' then
if k_write_strobe = '1' then
if port_id(0) = '1' then
uart_tx_reset <= out_port(0);
uart_rx_reset <= out_port(1);
end if;
end if;
end if;
end process constant_output_ports;
--
-----------------------------------------------------------------------------------------
--
end Behavioral;
-------------------------------------------------------------------------------------------
--
-- END OF FILE kc705_kcpsm6_spi_flash.vhd
--
-------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Filename: ram_16x8k_dp_tb.vhd
-- Description:
-- Testbench Top
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY work;
USE work.ALL;
ENTITY ram_16x8k_dp_tb IS
END ENTITY;
ARCHITECTURE ram_16x8k_dp_tb_ARCH OF ram_16x8k_dp_tb IS
SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0);
SIGNAL CLK : STD_LOGIC := '1';
SIGNAL CLKB : STD_LOGIC := '1';
SIGNAL RESET : STD_LOGIC;
BEGIN
CLK_GEN: PROCESS BEGIN
CLK <= NOT CLK;
WAIT FOR 100 NS;
CLK <= NOT CLK;
WAIT FOR 100 NS;
END PROCESS;
CLKB_GEN: PROCESS BEGIN
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
CLKB <= NOT CLKB;
WAIT FOR 100 NS;
END PROCESS;
RST_GEN: PROCESS BEGIN
RESET <= '1';
WAIT FOR 1000 NS;
RESET <= '0';
WAIT;
END PROCESS;
--STOP_SIM: PROCESS BEGIN
-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS
-- ASSERT FALSE
-- REPORT "END SIMULATION TIME REACHED"
-- SEVERITY FAILURE;
--END PROCESS;
--
PROCESS BEGIN
WAIT UNTIL STATUS(8)='1';
IF( STATUS(7 downto 0)/="0") THEN
ASSERT false
REPORT "Simulation Failed"
SEVERITY FAILURE;
ELSE
ASSERT false
REPORT "Test Completed Successfully"
SEVERITY FAILURE;
END IF;
END PROCESS;
ram_16x8k_dp_synth_inst:ENTITY work.ram_16x8k_dp_synth
PORT MAP(
CLK_IN => CLK,
CLKB_IN => CLK,
RESET_IN => RESET,
STATUS => STATUS
);
END ARCHITECTURE;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.dlx_instr.all;
architecture behavior of ir_extender is
subtype upper_6_bits is std_logic_vector(0 to 5);
subtype upper_16_bits is std_logic_vector(0 to 15);
begin
extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
begin
if To_bit(immed_en) = '1' then
if To_bit(immed_size_26) = '1' then -- 26-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
else
q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
end if;
else -- 16-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
else
q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
end if;
end if;
else
q <= disabled_dlx_word after Tpd;
end if;
end process extender;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.dlx_instr.all;
architecture behavior of ir_extender is
subtype upper_6_bits is std_logic_vector(0 to 5);
subtype upper_16_bits is std_logic_vector(0 to 15);
begin
extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
begin
if To_bit(immed_en) = '1' then
if To_bit(immed_size_26) = '1' then -- 26-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
else
q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
end if;
else -- 16-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
else
q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
end if;
end if;
else
q <= disabled_dlx_word after Tpd;
end if;
end process extender;
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_ire-b.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $
-- $Revision: 1.1.1.1 $
--
-- ---------------------------------------------------------------------
use work.dlx_instr.all;
architecture behavior of ir_extender is
subtype upper_6_bits is std_logic_vector(0 to 5);
subtype upper_16_bits is std_logic_vector(0 to 15);
begin
extender : process ( d, immed_en, immed_size_26, immed_unsigned ) is
begin
if To_bit(immed_en) = '1' then
if To_bit(immed_size_26) = '1' then -- 26-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_6_bits'(others => '0') & d(6 to 31) after Tpd;
else
q <= upper_6_bits'(others => d(6)) & d(6 to 31) after Tpd;
end if;
else -- 16-bit immediate
if To_bit(immed_unsigned) = '1' then
q <= upper_16_bits'(others => '0') & d(16 to 31) after Tpd;
else
q <= upper_16_bits'(others => d(16)) & d(16 to 31) after Tpd;
end if;
end if;
else
q <= disabled_dlx_word after Tpd;
end if;
end process extender;
end architecture behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2114.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02114ent IS
END c07s02b04x00p20n01i02114ent;
ARCHITECTURE c07s02b04x00p20n01i02114arch OF c07s02b04x00p20n01i02114ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_4;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
alias l_alias : real_v (1 to 2) is l_operand (2 to 3);
alias r_alias : real_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***PASSED TEST:c07s02b04x00p20n01i02114"
severity NOTE;
assert ((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***FAILED TEST: c07s02b04x00p20n01i02114 - Concatenation of two REAL aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02114arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2114.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02114ent IS
END c07s02b04x00p20n01i02114ent;
ARCHITECTURE c07s02b04x00p20n01i02114arch OF c07s02b04x00p20n01i02114ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_4;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
alias l_alias : real_v (1 to 2) is l_operand (2 to 3);
alias r_alias : real_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***PASSED TEST:c07s02b04x00p20n01i02114"
severity NOTE;
assert ((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***FAILED TEST: c07s02b04x00p20n01i02114 - Concatenation of two REAL aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02114arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2114.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b04x00p20n01i02114ent IS
END c07s02b04x00p20n01i02114ent;
ARCHITECTURE c07s02b04x00p20n01i02114arch OF c07s02b04x00p20n01i02114ent IS
TYPE real_v is array (integer range <>) of real;
SUBTYPE real_8 is real_v (1 to 8);
SUBTYPE real_4 is real_v (1 to 4);
BEGIN
TESTING : PROCESS
variable result : real_4;
variable l_operand : real_4 := (12.345, -67.890,12.345, -67.890);
variable r_operand : real_4 := ( -67.890, -67.890,12.345,12.345);
alias l_alias : real_v (1 to 2) is l_operand (2 to 3);
alias r_alias : real_v (1 to 2) is r_operand (3 to 4);
BEGIN
result := l_alias & r_alias;
wait for 20 ns;
assert NOT((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***PASSED TEST:c07s02b04x00p20n01i02114"
severity NOTE;
assert ((result = ( -67.890,12.345,12.345,12.345)) and (result(1)=-67.890))
report "***FAILED TEST: c07s02b04x00p20n01i02114 - Concatenation of two REAL aliases failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b04x00p20n01i02114arch;
|
--------------------------------------------------------------------------------
-- File Name: m25p80.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License version 2 as
-- published by the Free Software Foundation.
--
-- MODIFICATION HISTORY:
--
-- version: | author: | mod date: | changes made:
-- V1.0 G.Gojanovic 05 Jun 27 initial version
--
--------------------------------------------------------------------------------
-- PART DESCRIPTION:
--
-- Library: FLASH MEMORY
-- Technology: CMOS
-- Part: M25P80
--
-- Description: 8Mbit Serial Flash memory w/ 40MHz SPI Bus Interface
--
--------------------------------------------------------------------------------
LIBRARY IEEE; USE IEEE.std_logic_1164.ALL;
USE STD.textio.ALL;
USE IEEE.VITAL_timing.ALL;
USE IEEE.VITAL_primitives.ALL;
LIBRARY FMF; USE FMF.gen_utils.ALL;
USE FMF.conversions.ALL;
-------------------------------------------------------------------------------
-- ENTITY DECLARATION
-------------------------------------------------------------------------------
ENTITY m25p80 IS
GENERIC (
-- tipd delays: interconnect path delays
tipd_C : VitalDelayType01 := VitalZeroDelay01;
tipd_D : VitalDelayType01 := VitalZeroDelay01;
tipd_SNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_HOLDNeg : VitalDelayType01 := VitalZeroDelay01;
tipd_WNeg : VitalDelayType01 := VitalZeroDelay01;
-- tpd delays
tpd_C_Q : VitalDelayType01 := UnitDelay01;--tV
tpd_SNeg_Q : VitalDelayType01Z := UnitDelay01Z;--tDIS
tpd_HOLDNeg_Q : VitalDelayType01Z := UnitDelay01Z;--tLZ,tHZ
--tsetup values
tsetup_D_C : VitalDelayType := UnitDelay; --tDVCH /
tsetup_SNeg_C : VitalDelayType := UnitDelay; --tSLCH /
tsetup_HOLDNeg_C : VitalDelayType := UnitDelay; --tHHCH /
tsetup_C_HOLDNeg : VitalDelayType := UnitDelay; --tHLCH \
tsetup_WNeg_SNeg : VitalDelayType := UnitDelay; --tWHSL \
--thold values
thold_D_C : VitalDelayType := UnitDelay; --tCHDX /
thold_SNeg_C : VitalDelayType := UnitDelay; --tCHSL /
thold_HOLDNeg_C : VitalDelayType := UnitDelay; --tCHHL /
thold_C_HOLDNeg : VitalDelayType := UnitDelay; --tCHHH \
thold_WNeg_SNeg : VitalDelayType := UnitDelay; --tWPH \
--tpw values: pulse width
tpw_C_posedge : VitalDelayType := UnitDelay; --tCH
tpw_C_negedge : VitalDelayType := UnitDelay; --tCL
tpw_SNeg_posedge : VitalDelayType := UnitDelay; --tSHSL
-- tperiod min (calculated as 1/max freq)
tperiod_C_rd : VitalDelayType := UnitDelay; -- fC=20MHz
tperiod_C_fast_rd : VitalDelayType := UnitDelay; -- fC=25/40MHz
-- tdevice values: values for internal delays
-- Page Program Operation
tdevice_PP : VitalDelayType := 5 ms; --tPP
--Sector Erase Operation
tdevice_SE : VitalDelayType := 3 sec; --tSE
--Bulk Erase Operation
tdevice_BE : VitalDelayType := 20 sec; --tBE
--Write Status Register Operation
tdevice_WR : VitalDelayType := 15 ms; --tW
--Deep Power Down
tdevice_DP : VitalDelayType := 3 us; --tDP
--Release from Deep Power Down ES not read
tdevice_RES1 : VitalDelayType := 3 us; --tRES1
--Release from Deep Power Down ES read
tdevice_RES2 : VitalDelayType := 1.8 us; --tRES2
--VCC (min) to S# Low
tdevice_VSL : VitalDelayType := 10 us; --tVSL
--Time delay to Write instruction
tdevice_PUW : VitalDelayType := 10 ms; --tPUW
-- generic control parameters
InstancePath : STRING := DefaultInstancePath;
TimingChecksOn : BOOLEAN := DefaultTimingChecks;
MsgOn : BOOLEAN := DefaultMsgOn;
XOn : BOOLEAN := DefaultXon;
-- memory file to be loaded
mem_file_name : STRING := "m25p80.mem";
UserPreload : BOOLEAN := FALSE; --TRUE;
DebugInfo : BOOLEAN := FALSE;
LongTimming : BOOLEAN := TRUE;
-- For FMF SDF technology file usage
TimingModel : STRING := DefaultTimingModel
);
PORT (
C : IN std_ulogic := 'U'; --serial clock input
D : IN std_ulogic := 'U'; --serial data input
SNeg : IN std_ulogic := 'U'; -- chip select input
HOLDNeg : IN std_ulogic := 'U'; -- hold input
WNeg : IN std_ulogic := 'U'; -- write protect input
Q : OUT std_ulogic := 'U' --serial data output
);
ATTRIBUTE VITAL_LEVEL0 of m25p80 : ENTITY IS TRUE;
END m25p80;
-------------------------------------------------------------------------------
-- ARCHITECTURE DECLARATION
-------------------------------------------------------------------------------
ARCHITECTURE vhdl_behavioral of m25p80 IS
ATTRIBUTE VITAL_LEVEL0 OF vhdl_behavioral : ARCHITECTURE IS TRUE;
CONSTANT PartID : STRING := "m25p80";
CONSTANT MaxData : NATURAL := 16#FF#; --255;
CONSTANT SecSize : NATURAL := 16#FFFF#; --65535
CONSTANT SecNum : NATURAL := 15;
CONSTANT HiAddrBit : NATURAL := 23;
CONSTANT AddrRANGE : NATURAL := 16#FFFFF#;
CONSTANT BYTE : NATURAL := 8;
--Electronic Signature
CONSTANT ES : NATURAL := 16#13#;
-- interconnect path delay signals
SIGNAL C_ipd : std_ulogic := 'U';
SIGNAL D_ipd : std_ulogic := 'U';
SIGNAL SNeg_ipd : std_ulogic := 'U';
SIGNAL HOLDNeg_ipd : std_ulogic := 'U';
SIGNAL WNeg_ipd : std_ulogic := 'U';
--- internal delays
SIGNAL PP_in : std_ulogic := '0';
SIGNAL PP_out : std_ulogic := '0';
SIGNAL PUW_in : std_ulogic := '0';
SIGNAL PUW_out : std_ulogic := '0';
SIGNAL SE_in : std_ulogic := '0';
SIGNAL SE_out : std_ulogic := '0';
SIGNAL BE_in : std_ulogic := '0';
SIGNAL BE_out : std_ulogic := '0';
SIGNAL WR_in : std_ulogic := '0';
SIGNAL WR_out : std_ulogic := '0';
SIGNAL DP_in : std_ulogic := '0';
SIGNAL DP_out : std_ulogic := '0';
SIGNAL RES1_in : std_ulogic := '0';
SIGNAL RES1_out : std_ulogic := '0';
SIGNAL RES2_in : std_ulogic := '0';
SIGNAL RES2_out : std_ulogic := '0';
SIGNAL VSL_in : std_ulogic := '0';
SIGNAL VSL_out : std_ulogic := '0';
BEGIN
---------------------------------------------------------------------------
-- Internal Delays
---------------------------------------------------------------------------
-- Artificial VITAL primitives to incorporate internal delays
PP :VitalBuf(PP_out, PP_in, (tdevice_PP ,UnitDelay));
PUW :VitalBuf(PUW_out, PUW_in, (tdevice_PUW ,UnitDelay));
SE :VitalBuf(SE_out, SE_in, (tdevice_SE ,UnitDelay));
BE :VitalBuf(BE_out, BE_in, (tdevice_BE ,UnitDelay));
WR :VitalBuf(WR_out, WR_in, (tdevice_WR ,UnitDelay));
DP :VitalBuf(DP_out, DP_in, (tdevice_DP ,UnitDelay));
RES1 :VitalBuf(RES1_out, RES1_in, (tdevice_RES1 ,UnitDelay));
RES2 :VitalBuf(RES2_out, RES2_in, (tdevice_RES2 ,UnitDelay));
VSL :VitalBuf(VSL_out, VSL_in, (tdevice_VSL ,UnitDelay));
---------------------------------------------------------------------------
-- Wire Delays
---------------------------------------------------------------------------
WireDelay : BLOCK
BEGIN
w_1 : VitalWireDelay (C_ipd, C, tipd_C);
w_2 : VitalWireDelay (D_ipd, D, tipd_D);
w_3 : VitalWireDelay (SNeg_ipd, SNeg, tipd_SNeg);
w_4 : VitalWireDelay (HOLDNeg_ipd, HOLDNeg, tipd_HOLDNeg);
w_5 : VitalWireDelay (WNeg_ipd, WNeg, tipd_WNeg);
END BLOCK;
---------------------------------------------------------------------------
-- Main Behavior Block
---------------------------------------------------------------------------
Behavior: BLOCK
-- State Machine : State_Type
TYPE state_type IS (IDLE,
DP_DOWN,
WRITE_SR,
SECTOR_ER,
BULK_ER,
PAGE_PG
);
-- Instruction Type
TYPE instruction_type IS (NONE,
WREN,
WRDI,
WRSR,
RDSR,
READ,
FAST_READ,
SE,
BE,
PP,
DP,
RES_READ_ES
);
TYPE WByteType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
--Flash Memory Array
TYPE MemArray IS ARRAY (0 TO AddrRANGE) OF INTEGER RANGE -1 TO MaxData;
---------------------------------------------------------------------------
-- memory declaration
---------------------------------------------------------------------------
SHARED VARIABLE Mem : MemArray := (OTHERS => MaxData);
-- states
SIGNAL current_state : state_type; --
SIGNAL next_state : state_type; --
SIGNAL WByte : WByteType := (others => 0);
SIGNAL Instruct : instruction_type;
--zero delay signal
SIGNAL Q_zd : std_logic :='Z';
SIGNAL Q_temp : std_logic :='Z';
-- powerup parameters
SIGNAL ChipSelectOk : std_logic := '0';
SIGNAL WriteOk : std_logic := '0';
SHARED VARIABLE Status_reg : std_logic_vector(7 downto 0)
:= (others => '0');
SIGNAL Status_reg_in : std_logic_vector(7 downto 0)
:= (others => '0');
ALIAS WIP :std_logic IS Status_reg(0);
ALIAS WEL :std_logic IS Status_reg(1);
ALIAS BP0 :std_logic IS Status_reg(2);
ALIAS BP1 :std_logic IS Status_reg(3);
ALIAS BP2 :std_logic IS Status_reg(4);
ALIAS SRWD :std_logic IS Status_reg(7);
--Command Register
SIGNAL write : std_logic := '0';
SIGNAL read_out : std_logic := '0';
SIGNAL fast_rd : boolean := true;
SIGNAL rd : boolean := false;
SIGNAL es_read : boolean := false;
SIGNAL change_addr : std_logic := '0';
--FSM control signals
SIGNAL PDONE : std_logic := '1'; --Page Prog. Done
SIGNAL PSTART : std_logic := '0'; --Start Page Programming
SIGNAL WDONE : std_logic := '1'; --Write. Done
SIGNAL WSTART : std_logic := '0'; --Start Write
SIGNAL ESTART : std_logic := '0'; --Start Erase
SIGNAL EDONE : std_logic := '1'; --Erase Done
SIGNAL RES_in : std_logic := '0'; --RES1_in OR RES2_in
SIGNAL SA : NATURAL RANGE 0 TO SecNum := 0;
SIGNAL Byte_number : NATURAL RANGE 0 TO 255 := 0;
SHARED VARIABLE Sec_Prot : std_logic_vector(SecNum downto 0) :=
(OTHERS => '0');
SIGNAL Address : NATURAL RANGE 0 TO AddrRANGE := 0;
-- timing check violation
SIGNAL Viol : X01 := '0';
PROCEDURE ADDRHILO_SEC(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE sector : NATURAL RANGE 0 TO SecNum;
BEGIN
sector := Addr/16#10000#;
AddrLOW := sector*16#10000#;
AddrHIGH := sector*16#10000# + 16#0FFFF#;
END AddrHILO_SEC;
PROCEDURE ADDRHILO_PG(
VARIABLE AddrLOW : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE AddrHIGH : INOUT NATURAL RANGE 0 to ADDRRange;
VARIABLE Addr : NATURAL) IS
VARIABLE page : NATURAL RANGE 0 TO 65535;
BEGIN
page := Addr/16#100#;
AddrLOW := Page*16#100#;
AddrHIGH := Page*16#100# + 16#FF#;
END AddrHILO_PG;
BEGIN
----------------------------------------------------------------------------
--Power Up parameters timing
---------------------------------------------------------------------------
ChipSelectOk <= '1' AFTER tdevice_VSL;
WriteOk <= '1' AFTER tdevice_PUW;
---------------------------------------------------------------------------
-- VITAL Timing Checks Procedures
---------------------------------------------------------------------------
VITALTimingCheck: PROCESS(D_ipd, C_ipd, SNeg_ipd, HOLDNeg_ipd,
WNeg_ipd)
-- Timing Check Variables
VARIABLE Tviol_D_C : X01 := '0';
VARIABLE TD_D_C : VitalTimingDataType;
VARIABLE Tviol_HOLD_C : X01 := '0';
VARIABLE TD_HOLD_C : VitalTimingDataType;
VARIABLE Tviol_S_C : X01 := '0';
VARIABLE TD_S_C : VitalTimingDataType;
VARIABLE Tviol_WS_S : X01 := '0';
VARIABLE TD_WS_S : VitalTimingDataType;
VARIABLE Tviol_WH_S : X01 := '0';
VARIABLE TD_WH_S : VitalTimingDataType;
VARIABLE Pviol_S : X01 := '0';
VARIABLE PD_S : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_C : X01 := '0';
VARIABLE PD_C : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_C_rd : X01 := '0';
VARIABLE PD_C_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Pviol_C_fast_rd : X01 := '0';
VARIABLE PD_C_fast_rd : VitalPeriodDataType := VitalPeriodDataInit;
VARIABLE Violation : X01 := '0';
BEGIN
---------------------------------------------------------------------------
-- Timing Check Section
---------------------------------------------------------------------------
IF (TimingChecksOn) THEN
-- Setup/Hold Check between D and C
VitalSetupHoldCheck (
TestSignal => D_ipd,
TestSignalName => "D",
RefSignal => C_ipd,
RefSignalName => "C",
SetupHigh => tsetup_D_C,
SetupLow => tsetup_D_C,
HoldHigh => thold_D_C,
HoldLow => thold_D_C,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_D_C,
Violation => Tviol_D_C
);
-- Setup/Hold Check between HOLD# and C /
VitalSetupHoldCheck (
TestSignal => HOLDNeg_ipd,
TestSignalName => "HOLD#",
RefSignal => C_ipd,
RefSignalName => "C",
SetupHigh => tsetup_C_HOLDNeg,
SetupLow => tsetup_HOLDNeg_C,
HoldHigh => thold_C_HOLDNeg,
HoldLow => thold_HOLDNeg_C,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_HOLD_C,
Violation => Tviol_HOLD_C
);
-- Setup/Hold Check between CS# and C
VitalSetupHoldCheck (
TestSignal => SNeg_ipd,
TestSignalName => "S#",
RefSignal => C_ipd,
RefSignalName => "C",
SetupHigh => tsetup_SNeg_C,
SetupLow => tsetup_SNeg_C,
HoldHigh => thold_SNeg_C,
HoldLow => thold_SNeg_C,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_S_C,
Violation => Tviol_S_C
);
-- Setup Check between W# and CS# \
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => SNeg_ipd,
RefSignalName => "S#",
SetupHigh => tsetup_WNeg_SNeg,
CheckEnabled => true,
RefTransition => '\',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WS_S,
Violation => Tviol_WS_S
);
-- Hold Check between W# and CS# /
VitalSetupHoldCheck (
TestSignal => WNeg_ipd,
TestSignalName => "W#",
RefSignal => SNeg_ipd,
RefSignalName => "S#",
HoldHigh => thold_WNeg_SNeg,
CheckEnabled => true,
RefTransition => '/',
HeaderMsg => InstancePath & PartID,
TimingData => TD_WH_S,
Violation => Tviol_WH_S
);
-- Period Check S#
VitalPeriodPulseCheck (
TestSignal => SNeg_ipd,
TestSignalName => "S#",
PulseWidthHigh => tpw_SNeg_posedge,
PeriodData => PD_S,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_S,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check C for everything but READ
VitalPeriodPulseCheck (
TestSignal => C_ipd,
TestSignalName => "C",
PulseWidthLow => tpw_C_negedge,
PulseWidthHigh => tpw_C_posedge,
PeriodData => PD_C,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_C,
HeaderMsg => InstancePath & PartID,
CheckEnabled => true );
-- Period Check C for READ
VitalPeriodPulseCheck (
TestSignal => C_ipd,
TestSignalName => "C",
Period => tperiod_C_rd,
PeriodData => PD_C_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_C_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => rd );
-- Period Check C for other than READ
VitalPeriodPulseCheck (
TestSignal => C_ipd,
TestSignalName => "C",
Period => tperiod_C_fast_rd,
PeriodData => PD_C_fast_rd,
XOn => XOn,
MsgOn => MsgOn,
Violation => Pviol_C_fast_rd,
HeaderMsg => InstancePath & PartID,
CheckEnabled => fast_rd );
Violation := Tviol_D_C OR
Tviol_HOLD_C OR
Tviol_S_C OR
Tviol_WS_S OR
Tviol_WH_S OR
Pviol_C OR
Pviol_C_rd OR
Pviol_C_fast_rd OR
Pviol_S;
Viol <= Violation;
ASSERT Violation = '0'
REPORT InstancePath & partID & ": simulation may be" &
" inaccurate due to timing violations"
SEVERITY WARNING;
END IF;
END PROCESS VITALTimingCheck;
----------------------------------------------------------------------------
-- sequential process for FSM state transition
----------------------------------------------------------------------------
StateTransition : PROCESS(next_state, WriteOk)
BEGIN
IF WriteOk = '1' THEN
current_state <= next_state;
END IF;
END PROCESS StateTransition;
---------------------------------------------------------------------------
-- Write cycle decode
---------------------------------------------------------------------------
BusCycleDecode : PROCESS(C_ipd, SNeg_ipd, HOLDNeg_ipd, D_ipd, RES_in)
TYPE bus_cycle_type IS (STAND_BY,
CODE_BYTE,
ADDRESS_BYTES,
DUMMY_BYTES,
DATA_BYTES
);
VARIABLE bus_cycle_state : bus_cycle_type;
VARIABLE data_cnt : NATURAL := 0;
VARIABLE addr_cnt : NATURAL := 0;
VARIABLE code_cnt : NATURAL := 0;
VARIABLE dummy_cnt : NATURAL := 0;
VARIABLE bit_cnt : NATURAL := 0;
VARIABLE Data_in : std_logic_vector(2047 downto 0)
:= (others => '0');
VARIABLE code : std_logic_vector(7 downto 0);
VARIABLE code_in : std_logic_vector(7 downto 0);
VARIABLE Byte_slv : std_logic_vector(7 downto 0);
VARIABLE addr_bytes : std_logic_vector(HiAddrBit downto 0);
VARIABLE Address_in : std_logic_vector(23 downto 0);
BEGIN
CASE bus_cycle_state IS
WHEN STAND_BY =>
IF falling_edge(SNeg_ipd) THEN
Instruct <= NONE;
write <= '1';
code_cnt := 0;
addr_cnt := 0;
data_cnt := 0;
dummy_cnt := 0;
bus_cycle_state := CODE_BYTE;
END IF;
WHEN CODE_BYTE =>
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
Code_in(code_cnt) := D_ipd;
code_cnt := code_cnt + 1;
IF code_cnt = BYTE THEN
--MSB first
FOR I IN 7 DOWNTO 0 LOOP
code(i) := code_in(7-i);
END LOOP;
CASE code IS
WHEN "00000110" =>
Instruct <= WREN;
bus_cycle_state := DATA_BYTES;
WHEN "00000100" =>
Instruct <= WRDI;
bus_cycle_state := DATA_BYTES;
WHEN "00000001" =>
Instruct <= WRSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000101" =>
Instruct <= RDSR;
bus_cycle_state := DATA_BYTES;
WHEN "00000011" =>
Instruct <= READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "00001011" =>
Instruct <= FAST_READ;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10101011" =>
Instruct <= RES_READ_ES;
bus_cycle_state := DUMMY_BYTES;
WHEN "11011000" =>
Instruct <= SE;
bus_cycle_state := ADDRESS_BYTES;
WHEN "11000111" =>
Instruct <= BE;
bus_cycle_state := DATA_BYTES;
WHEN "00000010" =>
Instruct <= PP;
bus_cycle_state := ADDRESS_BYTES;
WHEN "10111001" =>
Instruct <= DP;
bus_cycle_state := DATA_BYTES;
WHEN others =>
null;
END CASE;
END IF;
END IF;
WHEN ADDRESS_BYTES =>
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
Address_in(addr_cnt) := D_ipd;
addr_cnt := addr_cnt + 1;
IF addr_cnt = 3*BYTE THEN
FOR I IN 23 DOWNTO 0 LOOP
addr_bytes(23-i) := Address_in(i);
END LOOP;
Address <= to_nat(addr_bytes);
change_addr <= '1','0' AFTER 1 ns;
IF Instruct = FAST_READ THEN
bus_cycle_state := DUMMY_BYTES;
ELSE
bus_cycle_state := DATA_BYTES;
END IF;
END IF;
END IF;
WHEN DUMMY_BYTES =>
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
dummy_cnt := dummy_cnt + 1;
IF dummy_cnt = BYTE THEN
IF Instruct = FAST_READ THEN
bus_cycle_state := DATA_BYTES;
END IF;
ELSIF dummy_cnt = 3*BYTE THEN
bus_cycle_state := DATA_BYTES;
es_read <= true;
END IF;
END IF;
IF rising_edge(SNeg_ipd) THEN
IF (HOLDNeg_ipd = '1' AND dummy_cnt = 0 AND
Instruct = RES_READ_ES) THEN
write <= '0';
es_read <= false;
END IF;
bus_cycle_state := STAND_BY;
END IF;
WHEN DATA_BYTES =>
IF falling_edge(C_ipd) AND SNeg_ipd = '0' AND
HOLDNeg_ipd = '1' THEN
IF Instruct = READ OR Instruct = RES_READ_ES
OR Instruct = FAST_READ OR Instruct = RDSR THEN
read_out <= '1', '0' AFTER 1 ns;
END IF;
END IF;
IF rising_edge(C_ipd) AND HOLDNeg_ipd = '1' THEN
IF data_cnt > 2047 THEN
--In case of PP, if more than 256 bytes are
--sent to the device
IF bit_cnt = 0 THEN
FOR I IN 0 TO (255*BYTE - 1) LOOP
Data_in(i) := Data_in(i+8);
END LOOP;
END IF;
Data_in(2040 + bit_cnt) := D_ipd;
bit_cnt := bit_cnt + 1;
IF bit_cnt = 8 THEN
bit_cnt := 0;
END IF;
data_cnt := data_cnt + 1;
ELSE
Data_in(data_cnt) := D_ipd;
data_cnt := data_cnt + 1;
bit_cnt := 0;
END IF;
END IF;
IF rising_edge(SNeg_ipd) THEN
bus_cycle_state := STAND_BY;
es_read <= true;
IF HOLDNeg_ipd = '1' AND WriteOk = '1' THEN
CASE Instruct IS
WHEN WREN | WRDI | DP | BE | SE =>
IF data_cnt = 0 THEN
write <= '0';
END IF;
WHEN RES_READ_ES =>
write <= '0';
WHEN WRSR =>
IF data_cnt = 8 THEN
write <= '0';
Status_reg_in <= Data_in(7 downto 0);
--MSB first
END IF;
WHEN PP =>
IF ((data_cnt mod 8) = 0 AND
data_cnt > BYTE) THEN
write <= '0';
FOR I IN 0 TO 255 LOOP
FOR J IN 7 DOWNTO 0 LOOP
Byte_slv(j) :=
Data_in((i*8) + (7-j));
END LOOP;
WByte(i) <= to_nat(Byte_slv);
END LOOP;
IF data_cnt > 256*BYTE THEN
Byte_number <= 255;
ELSE
Byte_number <= data_cnt/8-1;
END IF;
END IF;
WHEN others =>
null;
END CASE;
END IF;
END IF;
END CASE;
END PROCESS BusCycleDecode;
---------------------------------------------------------------------------
-- Timing control for the Page Program
---------------------------------------------------------------------------
ProgTime : PROCESS(PSTART)
VARIABLE pob : time;
BEGIN
IF LongTimming THEN
pob := tdevice_PP;
ELSE
pob := tdevice_PP / 100;
END IF;
IF rising_edge(PSTART) AND PDONE = '1' THEN
IF NOT Sec_Prot(SA) = '1' THEN
PDONE <= '0', '1' AFTER pob;
END IF;
END IF;
END PROCESS ProgTime;
---------------------------------------------------------------------------
-- Timing control for the Write Status Register
---------------------------------------------------------------------------
WriteTime : PROCESS(WSTART)
VARIABLE wob : time;
BEGIN
IF LongTimming THEN
wob := tdevice_WR;
ELSE
wob := tdevice_WR / 100;
END IF;
IF rising_edge(WSTART) AND WDONE = '1' THEN
WDONE <= '0', '1' AFTER wob;
END IF;
END PROCESS WriteTime;
---------------------------------------------------------------------------
-- Timing control for the Bulk Erase
---------------------------------------------------------------------------
ErsTime : PROCESS(ESTART)
VARIABLE seo : time;
VARIABLE beo : time;
VARIABLE duration : time;
BEGIN
IF LongTimming THEN
seo := tdevice_SE;
beo := tdevice_BE;
ELSE
seo := tdevice_SE / 100;
beo := tdevice_BE / 100;
END IF;
IF rising_edge(ESTART) AND EDONE = '1' THEN
IF Instruct = BE THEN
duration := beo;
ELSE --Instruct = SE
duration := seo;
END IF;
EDONE <= '0', '1' AFTER duration;
END IF;
END PROCESS ErsTime;
---------------------------------------------------------------------------
-- Main Behavior Process
-- combinational process for next state generation
---------------------------------------------------------------------------
StateGen :PROCESS(write, SNeg, WDONE, PDONE, EDONE)
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) THEN
IF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
next_state <= WRITE_SR;
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= PAGE_PG;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
next_state <= SECTOR_ER;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
next_state <= BULK_ER;
ELSIF Instruct = DP THEN
next_state <= DP_DOWN;
ELSE
next_state <= IDLE;
END IF;
END IF;
WHEN WRITE_SR =>
IF rising_edge(WDONE) THEN
next_state <= IDLE;
END IF;
WHEN PAGE_PG =>
IF rising_edge(PDONE) THEN
next_state <= IDLE;
END IF;
WHEN BULK_ER | SECTOR_ER =>
IF rising_edge(EDONE) THEN
next_state <= IDLE;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) AND Instruct = RES_READ_ES THEN
next_state <= IDLE;
END IF;
END CASE;
END PROCESS StateGen;
---------------------------------------------------------------------------
--FSM Output generation and general funcionality
---------------------------------------------------------------------------
Functional : PROCESS(write,read_out, WDONE, PDONE, EDONE, current_state,
SNeg_ipd, HOLDNeg_ipd, Instruct, Address, WByte,
WriteOk, RES1_out, RES2_out, change_addr,
ChipSelectOk, WNeg_ipd, RES1_in, RES2_in)
TYPE WDataType IS ARRAY (0 TO 255) OF INTEGER RANGE -1 TO MaxData;
VARIABLE WData : WDataType:= (OTHERS => 0);
VARIABLE oe : boolean := FALSE;
VARIABLE AddrLo : NATURAL;
VARIABLE AddrHi : NATURAL;
VARIABLE Addr : NATURAL;
VARIABLE read_cnt : NATURAL;
VARIABLE read_addr : NATURAL RANGE 0 TO AddrRANGE;
VARIABLE data_out : std_logic_vector(7 downto 0);
VARIABLE ident_out : std_logic_vector(23 downto 0);
VARIABLE old_bit : std_logic_vector(7 downto 0);
VARIABLE new_bit : std_logic_vector(7 downto 0);
VARIABLE old_int : INTEGER RANGE -1 to MaxData;
VARIABLE new_int : INTEGER RANGE -1 to MaxData;
VARIABLE wr_cnt : NATURAL RANGE 0 TO 255;
VARIABLE sect : NATURAL RANGE 0 TO SecNum;
VARIABLE BP : std_logic_vector(2 downto 0) := "000";
BEGIN
-----------------------------------------------------------------------
-- Functionality Section
-----------------------------------------------------------------------
oe := rising_edge(read_out) AND ChipSelectOk = '1';
RES_in <= RES1_in OR RES2_in; --this way, both timing conditions on
--Release from Deep Power Down are merged
IF Instruct'EVENT THEN
read_cnt := 0;
fast_rd <= true;
rd <= false;
END IF;
IF rising_edge(change_addr) THEN
read_addr := Address;
END IF;
IF RES1_out'EVENT AND RES1_out = '1' THEN
RES1_in <= '0';
END IF;
IF RES2_out'EVENT AND RES2_out = '1' THEN
RES2_in <= '0';
END IF;
CASE current_state IS
WHEN IDLE =>
IF falling_edge(write) AND WriteOK = '1' THEN
IF RES_in = '1' AND Instruct /= DP THEN
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
IF Instruct = WREN THEN
WEL := '1';
ELSIF Instruct = WRDI THEN
WEL := '0';
ELSIF Instruct = WRSR AND WEL = '1'
AND not(SRWD = '1' AND WNeg_ipd = '0') THEN
-- can not execute if HPM is entered
-- or if WEL bit is zero
WSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
ELSIF Instruct = PP AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
PSTART <= '1', '0' AFTER 1 ns;
WIP := '1';
SA <= sect;
Addr := Address;
wr_cnt := Byte_number;
FOR I IN wr_cnt DOWNTO 0 LOOP
IF Viol /= '0' AND Sec_Prot(SA) /= '0' THEN
WData(i) := -1;
ELSE
WData(i) := WByte(i);
END IF;
END LOOP;
END IF;
ELSIF Instruct = SE AND WEL = '1' THEN
sect := Address / 16#10000#;
IF Sec_Prot(sect) = '0' THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
Addr := Address;
END IF;
ELSIF Instruct = BE AND WEL = '1' AND
(BP0 = '0' AND BP1 = '0' AND BP2 = '0') THEN
ESTART <= '1', '0' AFTER 1 ns;
WIP := '1';
END IF;
ELSIF oe AND RES_in = '0' THEN
IF Instruct = RDSR THEN
--Read Status Register
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ELSIF Instruct = READ OR Instruct = FAST_READ THEN
--Read Memory array
IF Instruct = READ THEN
fast_rd <= false;
rd <= true;
END IF;
data_out := to_slv(Mem(read_addr),8);
Q_zd <= data_out(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
IF read_addr = AddrRANGE THEN
read_addr := 0;
ELSE
read_addr := read_addr + 1;
END IF;
END IF;
ELSE --IF Instruct = RES_READ_ES - look at assertion of oe
data_out := to_slv(ES, 8);
Q_zd <= data_out(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ELSIF oe AND RES_in = '1' THEN
Q_zd <= 'X';
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
ASSERT false
REPORT InstancePath & partID & "Command results" &
" can be corrupted, a delay of tRES" &
" currently in progress."
SEVERITY WARNING;
END IF;
WHEN WRITE_SR =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
IF WDONE = '1' THEN
WIP := '0';
WEL := '0';
SRWD := Status_reg_in(0);--MSB first
BP2 := Status_reg_in(3);
BP1 := Status_reg_in(4);
BP0 := Status_reg_in(5);
BP := BP2 & BP1 & BP0;
CASE BP IS
WHEN "000" =>
Sec_Prot := (others => '0');
WHEN "001" =>
Sec_Prot(15) := '1';
WHEN "010" =>
Sec_Prot(15 downto 14):= "11";
WHEN "011" =>
Sec_Prot(15 downto 12):= to_slv(16#F#,4);
WHEN "100" =>
Sec_Prot(15 downto 8):= to_slv(16#FF#,8);
WHEN others =>
Sec_Prot := (others => '1');
END CASE;
END IF;
WHEN PAGE_PG =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_PG(AddrLo, AddrHi, Addr);
FOR I IN Addr TO Addr + wr_cnt LOOP
new_int := WData(i-Addr);
IF (i - AddrLo) >= 256 THEN
old_int := Mem(i - 256);
IF new_int > -1 THEN
new_bit := to_slv(new_int,8);
IF old_int > -1 THEN
old_bit := to_slv(old_int,8);
FOR j IN 0 TO 7 LOOP
IF old_bit(j) = '0' THEN
new_bit(j) := '0';
END IF;
END LOOP;
new_int := to_nat(new_bit);
END IF;
WData(i-Addr) := new_int;
ELSE
WData(i-Addr) := -1;
END IF;
ELSE
old_int := Mem(i);
IF new_int > -1 THEN
new_bit := to_slv(new_int,8);
IF old_int > -1 THEN
old_bit := to_slv(old_int,8);
FOR j IN 0 TO 7 LOOP
IF old_bit(j) = '0' THEN
new_bit(j) := '0';
END IF;
END LOOP;
new_int := to_nat(new_bit);
END IF;
WData(i-Addr) := new_int;
ELSE
WData(i-Addr) := -1;
END IF;
END IF;
END LOOP;
FOR I IN Addr TO Addr + wr_cnt LOOP
IF (i - AddrLo) >= 256 THEN
Mem (i - 256) := -1;
ELSE
Mem (i) := -1;
END IF;
END LOOP;
IF PDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN Addr TO Addr + wr_cnt LOOP
IF (i - AddrLo) >= 256 THEN
Mem(i - 256) := WData(i-Addr);
ELSE
Mem (i) := WData(i-Addr);
END IF;
END LOOP;
END IF;
WHEN SECTOR_ER =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
ADDRHILO_SEC(AddrLo, AddrHi, Addr);
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN AddrLo TO AddrHi LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN BULK_ER =>
IF oe AND Instruct = RDSR THEN
Q_zd <= Status_reg(7-read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := -1;
END LOOP;
IF EDONE = '1' THEN
WIP := '0';
WEL := '0';
FOR i IN 0 TO AddrRANGE LOOP
Mem(i) := MaxData;
END LOOP;
END IF;
WHEN DP_DOWN =>
IF falling_edge(write) THEN
IF Instruct = RES_READ_ES THEN
IF es_read THEN
RES1_in <= '1';
ELSE
RES2_in <= '1';
END IF;
END IF;
ELSIF oe AND Instruct = RES_READ_ES THEN
--Read Electronic Signature
data_out := to_slv(ES,8);
Q_zd <= data_out(7 - read_cnt);
read_cnt := read_cnt + 1;
IF read_cnt = 8 THEN
read_cnt := 0;
END IF;
END IF;
END CASE;
--Output Disable Control
IF ((SNeg_ipd = '1') OR (HOLDNeg_ipd = '0')) THEN
Q_temp <= Q_zd;
Q_zd <= 'Z';
END IF;
IF ((SNeg_ipd = '0') AND rising_edge(HOLDNeg_ipd) AND C_ipd = '0') THEN
Q_zd <= Q_temp;
END IF;
END PROCESS Functional;
---------------------------------------------------------------------------
---- File Read Section - Preload Control
---------------------------------------------------------------------------
MemPreload : PROCESS
-- text file input variables
FILE mem_file : text is mem_file_name;
VARIABLE ind : NATURAL RANGE 0 TO AddrRANGE := 0;
VARIABLE buf : line;
BEGIN
---------------------------------------------------------------------------
--m25p80 memory preload file format -----------------------------------
---------------------------------------------------------------------------
-- / - comment
-- @aaaaa - <aaaaa> stands for address
-- dd - <dd> is byte to be written at Mem(aaaaa++)
-- (aaaaa is incremented at every load)
-- only first 1-6 columns are loaded. NO empty lines !!!!!!!!!!!!!!!!
---------------------------------------------------------------------------
-- memory preload
IF (mem_file_name /= "none" AND UserPreload) THEN
ind := 0;
Mem := (OTHERS => MaxData);
WHILE (not ENDFILE (mem_file)) LOOP
READLINE (mem_file, buf);
IF buf(1) = '/' THEN
NEXT;
ELSIF buf(1) = '@' THEN
ind := h(buf(2 to 6)); --address
ELSE
IF ind <= AddrRANGE THEN
Mem(ind) := h(buf(1 to 2));
END IF;
IF ind < AddrRANGE THEN
ind := ind + 1;
ELSIF ind >= AddrRANGE THEN
ASSERT false
REPORT "Given preload address is out of" &
"memory address range"
SEVERITY warning;
END IF;
END IF;
END LOOP;
END IF;
WAIT;
END PROCESS MemPreload;
Q_OUT: PROCESS(Q_zd)
VARIABLE Q_GlitchData : VitalGlitchDataType;
BEGIN
VitalPathDelay01Z (
OutSignal => Q,
OutSignalName => "Q",
OutTemp => Q_zd,
GlitchData => Q_GlitchData,
XOn => XOn,
MsgOn => MsgOn,
Paths => (
0 => (InputChangeTime => C_ipd'LAST_EVENT,
PathDelay => VitalExtendtofillDelay(tpd_C_Q),
PathCondition => true),
1 => (InputChangeTime => SNeg_ipd'LAST_EVENT,
PathDelay => tpd_SNeg_Q,
PathCondition => SNeg_ipd = '1'),
2 => (InputChangeTime => HOLDNeg_ipd'LAST_EVENT,
PathDelay => tpd_HOLDNeg_Q,
PathCondition => TRUE)
)
);
END PROCESS Q_OUT;
END BLOCK behavior;
END vhdl_behavioral;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
-- 8 bit, no parity, 1 stop bit
--
-- This module was made for use with Spartan-6 Generation Devices and is also ideally
-- suited for use with Virtex-6 and 7-Series devices.
--
-- Version 1 - 31st March 2011.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- chapman@xilinx.com
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the
-- implementation. The Unisim Library is used to define Xilinx primitives. It is also
-- used during simulation.
-- The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for
--
entity uart_tx6 is
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end uart_tx6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for uart_tx6
--
architecture low_level_definition of uart_tx6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in uart_tx6
--
-------------------------------------------------------------------------------------------
--
signal store_data : std_logic_vector(7 downto 0);
signal data : std_logic_vector(7 downto 0);
signal pointer_value : std_logic_vector(3 downto 0);
signal pointer : std_logic_vector(3 downto 0);
signal en_pointer : std_logic;
signal zero : std_logic;
signal full_int : std_logic;
signal data_present_value : std_logic;
signal data_present_int : std_logic;
signal sm_value : std_logic_vector(3 downto 0);
signal sm : std_logic_vector(3 downto 0);
signal div_value : std_logic_vector(3 downto 0);
signal div : std_logic_vector(3 downto 0);
signal lsb_data : std_logic;
signal msb_data : std_logic;
signal last_bit : std_logic;
signal serial_data : std_logic;
signal next_value : std_logic;
signal next_bit : std_logic;
signal buffer_read_value : std_logic;
signal buffer_read : std_logic;
--
-------------------------------------------------------------------------------------------
--
-- Attributes to guide mapping of logic into Slices.
-------------------------------------------------------------------------------------------
--
--
attribute hblknm : string;
attribute hblknm of pointer3_lut : label is "uart_tx6_1";
attribute hblknm of pointer3_flop : label is "uart_tx6_1";
attribute hblknm of pointer2_lut : label is "uart_tx6_1";
attribute hblknm of pointer2_flop : label is "uart_tx6_1";
attribute hblknm of pointer01_lut : label is "uart_tx6_1";
attribute hblknm of pointer1_flop : label is "uart_tx6_1";
attribute hblknm of pointer0_flop : label is "uart_tx6_1";
attribute hblknm of data_present_lut : label is "uart_tx6_1";
attribute hblknm of data_present_flop : label is "uart_tx6_1";
--
attribute hblknm of sm0_lut : label is "uart_tx6_2";
attribute hblknm of sm0_flop : label is "uart_tx6_2";
attribute hblknm of sm1_lut : label is "uart_tx6_2";
attribute hblknm of sm1_flop : label is "uart_tx6_2";
attribute hblknm of sm2_lut : label is "uart_tx6_2";
attribute hblknm of sm2_flop : label is "uart_tx6_2";
attribute hblknm of sm3_lut : label is "uart_tx6_2";
attribute hblknm of sm3_flop : label is "uart_tx6_2";
--
attribute hblknm of div01_lut : label is "uart_tx6_3";
attribute hblknm of div23_lut : label is "uart_tx6_3";
attribute hblknm of div0_flop : label is "uart_tx6_3";
attribute hblknm of div1_flop : label is "uart_tx6_3";
attribute hblknm of div2_flop : label is "uart_tx6_3";
attribute hblknm of div3_flop : label is "uart_tx6_3";
attribute hblknm of next_lut : label is "uart_tx6_3";
attribute hblknm of next_flop : label is "uart_tx6_3";
attribute hblknm of read_flop : label is "uart_tx6_3";
--
attribute hblknm of lsb_data_lut : label is "uart_tx6_4";
attribute hblknm of msb_data_lut : label is "uart_tx6_4";
attribute hblknm of serial_lut : label is "uart_tx6_4";
attribute hblknm of serial_flop : label is "uart_tx6_4";
attribute hblknm of full_lut : label is "uart_tx6_4";
--
--
-------------------------------------------------------------------------------------------
--
-- Start of uart_tx6 circuit description
--
-------------------------------------------------------------------------------------------
--
begin
-- SRL16E data storage
data_width_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of storage_srl : label is "uart_tx6_5";
attribute hblknm of storage_flop : label is "uart_tx6_5";
begin
storage_srl: SRL16E
generic map (INIT => X"0000")
port map( D => data_in(i),
CE => buffer_write,
CLK => clk,
A0 => pointer(0),
A1 => pointer(1),
A2 => pointer(2),
A3 => pointer(3),
Q => store_data(i) );
storage_flop: FD
port map ( D => store_data(i),
Q => data(i),
C => clk);
end generate data_width_loop;
pointer3_lut: LUT6
generic map (INIT => X"FF00FE00FF80FF00")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(3));
pointer3_flop: FDR
port map ( D => pointer_value(3),
Q => pointer(3),
R => buffer_reset,
C => clk);
pointer2_lut: LUT6
generic map (INIT => X"F0F0E1E0F878F0F0")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => buffer_write,
I5 => buffer_read,
O => pointer_value(2));
pointer2_flop: FDR
port map ( D => pointer_value(2),
Q => pointer(2),
R => buffer_reset,
C => clk);
pointer01_lut: LUT6_2
generic map (INIT => X"CC9060CCAA5050AA")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => en_pointer,
I3 => buffer_write,
I4 => buffer_read,
I5 => '1',
O5 => pointer_value(0),
O6 => pointer_value(1));
pointer1_flop: FDR
port map ( D => pointer_value(1),
Q => pointer(1),
R => buffer_reset,
C => clk);
pointer0_flop: FDR
port map ( D => pointer_value(0),
Q => pointer(0),
R => buffer_reset,
C => clk);
data_present_lut: LUT6_2
generic map (INIT => X"F4FCF4FC040004C0")
port map( I0 => zero,
I1 => data_present_int,
I2 => buffer_write,
I3 => buffer_read,
I4 => full_int,
I5 => '1',
O5 => en_pointer,
O6 => data_present_value);
data_present_flop: FDR
port map ( D => data_present_value,
Q => data_present_int,
R => buffer_reset,
C => clk);
full_lut: LUT6_2
generic map (INIT => X"0001000080000000")
port map( I0 => pointer(0),
I1 => pointer(1),
I2 => pointer(2),
I3 => pointer(3),
I4 => '1',
I5 => '1',
O5 => full_int,
O6 => zero);
lsb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(0),
I1 => data(1),
I2 => data(2),
I3 => data(3),
I4 => sm(0),
I5 => sm(1),
O => lsb_data);
msb_data_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => data(4),
I1 => data(5),
I2 => data(6),
I3 => data(7),
I4 => sm(0),
I5 => sm(1),
O => msb_data);
serial_lut: LUT6_2
generic map (INIT => X"CFAACC0F0FFFFFFF")
port map( I0 => lsb_data,
I1 => msb_data,
I2 => sm(1),
I3 => sm(2),
I4 => sm(3),
I5 => '1',
O5 => last_bit,
O6 => serial_data);
serial_flop: FD
port map ( D => serial_data,
Q => serial_out,
C => clk);
sm0_lut: LUT6
generic map (INIT => X"85500000AAAAAAAA")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(0));
sm0_flop: FD
port map ( D => sm_value(0),
Q => sm(0),
C => clk);
sm1_lut: LUT6
generic map (INIT => X"26610000CCCCCCCC")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(1));
sm1_flop: FD
port map ( D => sm_value(1),
Q => sm(1),
C => clk);
sm2_lut: LUT6
generic map (INIT => X"88700000F0F0F0F0")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(2));
sm2_flop: FD
port map ( D => sm_value(2),
Q => sm(2),
C => clk);
sm3_lut: LUT6
generic map (INIT => X"87440000FF00FF00")
port map( I0 => sm(0),
I1 => sm(1),
I2 => sm(2),
I3 => sm(3),
I4 => data_present_int,
I5 => next_bit,
O => sm_value(3));
sm3_flop: FD
port map ( D => sm_value(3),
Q => sm(3),
C => clk);
div01_lut: LUT6_2
generic map (INIT => X"6C0000005A000000")
port map( I0 => div(0),
I1 => div(1),
I2 => en_16_x_baud,
I3 => '1',
I4 => '1',
I5 => '1',
O5 => div_value(0),
O6 => div_value(1));
div0_flop: FD
port map ( D => div_value(0),
Q => div(0),
C => clk);
div1_flop: FD
port map ( D => div_value(1),
Q => div(1),
C => clk);
div23_lut: LUT6_2
generic map (INIT => X"7F80FF007878F0F0")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => '1',
O5 => div_value(2),
O6 => div_value(3));
div2_flop: FD
port map ( D => div_value(2),
Q => div(2),
C => clk);
div3_flop: FD
port map ( D => div_value(3),
Q => div(3),
C => clk);
next_lut: LUT6_2
generic map (INIT => X"0000000080000000")
port map( I0 => div(0),
I1 => div(1),
I2 => div(2),
I3 => div(3),
I4 => en_16_x_baud,
I5 => last_bit,
O5 => next_value,
O6 => buffer_read_value);
next_flop: FD
port map ( D => next_value,
Q => next_bit,
C => clk);
read_flop: FD
port map ( D => buffer_read_value,
Q => buffer_read,
C => clk);
-- assign internal signals to outputs
buffer_full <= full_int;
buffer_half_full <= pointer(3);
buffer_data_present <= data_present_int;
end low_level_definition;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart_tx6.vhd
--
-------------------------------------------------------------------------------------------
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
architecture adder_struct of adder is
component full_adder is
port(
A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end component;
signal C: std_logic_vector(0 to N);
begin
C(0) <= Cin;
Cout <= C(N);
overflow <= C(N-1) xor C(N);
gen_adders:
for I in 0 to N-1 generate
gen_fa : full_adder port map(
A => A(I), B => B(I), Cin => C(I),
S => S(I), Cout => C(I+1)
);
end generate;
end architecture; |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
architecture adder_struct of adder is
component full_adder is
port(
A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end component;
signal C: std_logic_vector(0 to N);
begin
C(0) <= Cin;
Cout <= C(N);
overflow <= C(N-1) xor C(N);
gen_adders:
for I in 0 to N-1 generate
gen_fa : full_adder port map(
A => A(I), B => B(I), Cin => C(I),
S => S(I), Cout => C(I+1)
);
end generate;
end architecture; |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
architecture adder_struct of adder is
component full_adder is
port(
A, B, Cin: in std_logic;
S, Cout: out std_logic
);
end component;
signal C: std_logic_vector(0 to N);
begin
C(0) <= Cin;
Cout <= C(N);
overflow <= C(N-1) xor C(N);
gen_adders:
for I in 0 to N-1 generate
gen_fa : full_adder port map(
A => A(I), B => B(I), Cin => C(I),
S => S(I), Cout => C(I+1)
);
end generate;
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity execute_block is
generic (
SIZE : integer := 32
);
port (
IMM_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in std_logic_vector(4 downto 0);
MUXED_B_i : in std_logic_vector(SIZE - 1 downto 0);
S_MUX_ALUIN_i : in std_logic;
FW_X_i : in std_logic_vector(SIZE - 1 downto 0);
FW_W_i : in std_logic_vector(SIZE - 1 downto 0);
FW_4_i : in std_logic_vector(SIZE - 1 downto 0);
S_FW_A_i : in std_logic_vector(1 downto 0);
S_FW_B_i : in std_logic_vector(1 downto 0);
muxed_dest : out std_logic_vector(4 downto 0);
muxed_B : out std_logic_vector(SIZE -1 downto 0);
S_MUX_DEST_i : in std_logic_vector(1 downto 0);
OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end execute_block;
architecture struct of execute_block is
component mux21
port (
IN0 : in std_logic_vector(SIZE - 1 downto 0);
IN1 : in std_logic_vector(SIZE - 1 downto 0);
CTRL : in std_logic;
OUT1 : out std_logic_vector(SIZE - 1 downto 0)
);
end component;
component mux41
generic (
MUX_SIZE : integer := 5
);
port (
IN0 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN1 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN2 : in std_logic_vector(MUX_SIZE - 1 downto 0);
IN3 : in std_logic_vector(MUX_SIZE - 1 downto 0);
CTRL : in std_logic_vector(1 downto 0);
OUT1 : out std_logic_vector(MUX_SIZE - 1 downto 0)
);
end component;
component real_alu
generic (
DATA_SIZE : integer := 32);
port (
IN1 : in std_logic_vector(DATA_SIZE - 1 downto 0);
IN2 : in std_logic_vector(DATA_SIZE - 1 downto 0);
--OP : in AluOp;
ALUW_i : in std_logic_vector(12 downto 0);
DOUT : out std_logic_vector(DATA_SIZE - 1 downto 0);
stall_o : out std_logic;
Clock : in std_logic;
Reset : in std_logic
);
end component;
signal FWB2mux : std_logic_vector(SIZE - 1 downto 0);
signal FWA2alu : std_logic_vector(SIZE - 1 downto 0);
signal FWB2alu : std_logic_vector(SIZE - 1 downto 0);
begin
ALUIN_MUX: mux21 port map(
IN0 => FWB2mux,
IN1 => IMM_i,
CTRL => S_MUX_ALUIN_i,
OUT1 => FWB2alu);
ALU: real_alu generic map (
DATA_SIZE => 32
)
port map (
IN1 => FWA2alu,
IN2 => FWB2alu,
-- OP => OP,
ALUW_i => ALUW_i,
DOUT => DOUT,
stall_o => stall_o,
Clock => Clock,
Reset => Reset
);
MUXDEST: mux41 generic map(
MUX_SIZE => 5
)
port map(
IN0 => "00000", -- THIS VALUE SHOULD NEVER APPEAR!!
IN1 => rC_i,
IN2 => rB_i,
IN3 => "11111",
CTRL => S_MUX_DEST_i,
OUT1 => muxed_dest
);
MUX_FWA: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => A_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => FW_4_i,
CTRL => S_FW_A_i,
OUT1 => FWA2alu
);
MUX_FWB: mux41 generic map(
MUX_SIZE => 32
)
port map(
IN0 => MUXED_B_i,
IN1 => FW_X_i,
IN2 => FW_W_i,
IN3 => FW_4_i,
CTRL => S_FW_B_i,
OUT1 => FWB2mux
);
muxed_B <= FWB2mux;
end struct;
|
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1, z1, z2 : integer;
begin
sub1_i: entity work.sub
port map (
x => x1,
y => 2,
z => z1 );
sub2_i: entity work.sub
port map (
x => 6 + 15,
y => 2 * 4,
z => z2 );
process is
begin
x1 <= 5;
wait for 1 ns;
assert z1 = 7;
assert z2 = 29;
wait;
end process;
end architecture;
|
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end architecture;
|
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end architecture;
|
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end architecture;
|
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end architecture;
|
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end architecture;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:axi_quad_spi:3.2
-- IP Revision: 8
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY axi_quad_spi_v3_2_8;
USE axi_quad_spi_v3_2_8.axi_quad_spi;
ENTITY PmodNAV_axi_quad_spi_0_0 IS
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END PmodNAV_axi_quad_spi_0_0;
ARCHITECTURE PmodNAV_axi_quad_spi_0_0_arch OF PmodNAV_axi_quad_spi_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF PmodNAV_axi_quad_spi_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT axi_quad_spi IS
GENERIC (
Async_Clk : INTEGER;
C_FAMILY : STRING;
C_SELECT_XPM : INTEGER;
C_SUB_FAMILY : STRING;
C_INSTANCE : STRING;
C_SPI_MEM_ADDR_BITS : INTEGER;
C_TYPE_OF_AXI4_INTERFACE : INTEGER;
C_XIP_MODE : INTEGER;
C_UC_FAMILY : INTEGER;
C_FIFO_DEPTH : INTEGER;
C_SCK_RATIO : INTEGER;
C_NUM_SS_BITS : INTEGER;
C_NUM_TRANSFER_BITS : INTEGER;
C_SPI_MODE : INTEGER;
C_USE_STARTUP : INTEGER;
C_SPI_MEMORY : INTEGER;
C_S_AXI_ADDR_WIDTH : INTEGER;
C_S_AXI_DATA_WIDTH : INTEGER;
C_S_AXI4_ADDR_WIDTH : INTEGER;
C_S_AXI4_DATA_WIDTH : INTEGER;
C_S_AXI4_ID_WIDTH : INTEGER;
C_SHARED_STARTUP : INTEGER;
C_S_AXI4_BASEADDR : STD_LOGIC_VECTOR;
C_S_AXI4_HIGHADDR : STD_LOGIC_VECTOR;
C_LSB_STUP : INTEGER
);
PORT (
ext_spi_clk : IN STD_LOGIC;
s_axi_aclk : IN STD_LOGIC;
s_axi_aresetn : IN STD_LOGIC;
s_axi4_aclk : IN STD_LOGIC;
s_axi4_aresetn : IN STD_LOGIC;
s_axi_awaddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_araddr : IN STD_LOGIC_VECTOR(6 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi4_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_awaddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_awlock : IN STD_LOGIC;
s_axi4_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_awvalid : IN STD_LOGIC;
s_axi4_awready : OUT STD_LOGIC;
s_axi4_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_wlast : IN STD_LOGIC;
s_axi4_wvalid : IN STD_LOGIC;
s_axi4_wready : OUT STD_LOGIC;
s_axi4_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_bvalid : OUT STD_LOGIC;
s_axi4_bready : IN STD_LOGIC;
s_axi4_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_araddr : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
s_axi4_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi4_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_arlock : IN STD_LOGIC;
s_axi4_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi4_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi4_arvalid : IN STD_LOGIC;
s_axi4_arready : OUT STD_LOGIC;
s_axi4_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi4_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi4_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi4_rlast : OUT STD_LOGIC;
s_axi4_rvalid : OUT STD_LOGIC;
s_axi4_rready : IN STD_LOGIC;
io0_i : IN STD_LOGIC;
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC;
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
io2_i : IN STD_LOGIC;
io2_o : OUT STD_LOGIC;
io2_t : OUT STD_LOGIC;
io3_i : IN STD_LOGIC;
io3_o : OUT STD_LOGIC;
io3_t : OUT STD_LOGIC;
spisel : IN STD_LOGIC;
sck_i : IN STD_LOGIC;
sck_o : OUT STD_LOGIC;
sck_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC;
cfgclk : OUT STD_LOGIC;
cfgmclk : OUT STD_LOGIC;
eos : OUT STD_LOGIC;
preq : OUT STD_LOGIC;
clk : IN STD_LOGIC;
gsr : IN STD_LOGIC;
gts : IN STD_LOGIC;
keyclearb : IN STD_LOGIC;
usrcclkts : IN STD_LOGIC;
usrdoneo : IN STD_LOGIC;
usrdonets : IN STD_LOGIC;
pack : IN STD_LOGIC;
ip2intc_irpt : OUT STD_LOGIC
);
END COMPONENT axi_quad_spi;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF ext_spi_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 spi_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 lite_clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 lite_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 AXI_LITE RREADY";
ATTRIBUTE X_INTERFACE_INFO OF io0_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_I";
ATTRIBUTE X_INTERFACE_INFO OF io0_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_O";
ATTRIBUTE X_INTERFACE_INFO OF io0_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO0_T";
ATTRIBUTE X_INTERFACE_INFO OF io1_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_I";
ATTRIBUTE X_INTERFACE_INFO OF io1_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_O";
ATTRIBUTE X_INTERFACE_INFO OF io1_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 IO1_T";
ATTRIBUTE X_INTERFACE_INFO OF sck_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_I";
ATTRIBUTE X_INTERFACE_INFO OF sck_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_O";
ATTRIBUTE X_INTERFACE_INFO OF sck_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SCK_T";
ATTRIBUTE X_INTERFACE_INFO OF ss_i: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_I";
ATTRIBUTE X_INTERFACE_INFO OF ss_o: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_O";
ATTRIBUTE X_INTERFACE_INFO OF ss_t: SIGNAL IS "xilinx.com:interface:spi:1.0 SPI_0 SS_T";
ATTRIBUTE X_INTERFACE_INFO OF ip2intc_irpt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 interrupt INTERRUPT";
BEGIN
U0 : axi_quad_spi
GENERIC MAP (
Async_Clk => 1,
C_FAMILY => "zynq",
C_SELECT_XPM => 0,
C_SUB_FAMILY => "zynq",
C_INSTANCE => "axi_quad_spi_inst",
C_SPI_MEM_ADDR_BITS => 24,
C_TYPE_OF_AXI4_INTERFACE => 0,
C_XIP_MODE => 0,
C_UC_FAMILY => 0,
C_FIFO_DEPTH => 16,
C_SCK_RATIO => 16,
C_NUM_SS_BITS => 1,
C_NUM_TRANSFER_BITS => 8,
C_SPI_MODE => 0,
C_USE_STARTUP => 0,
C_SPI_MEMORY => 1,
C_S_AXI_ADDR_WIDTH => 7,
C_S_AXI_DATA_WIDTH => 32,
C_S_AXI4_ADDR_WIDTH => 24,
C_S_AXI4_DATA_WIDTH => 32,
C_S_AXI4_ID_WIDTH => 1,
C_SHARED_STARTUP => 0,
C_S_AXI4_BASEADDR => X"FFFFFFFF",
C_S_AXI4_HIGHADDR => X"00000000",
C_LSB_STUP => 0
)
PORT MAP (
ext_spi_clk => ext_spi_clk,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi4_aclk => '0',
s_axi4_aresetn => '0',
s_axi_awaddr => s_axi_awaddr,
s_axi_awvalid => s_axi_awvalid,
s_axi_awready => s_axi_awready,
s_axi_wdata => s_axi_wdata,
s_axi_wstrb => s_axi_wstrb,
s_axi_wvalid => s_axi_wvalid,
s_axi_wready => s_axi_wready,
s_axi_bresp => s_axi_bresp,
s_axi_bvalid => s_axi_bvalid,
s_axi_bready => s_axi_bready,
s_axi_araddr => s_axi_araddr,
s_axi_arvalid => s_axi_arvalid,
s_axi_arready => s_axi_arready,
s_axi_rdata => s_axi_rdata,
s_axi_rresp => s_axi_rresp,
s_axi_rvalid => s_axi_rvalid,
s_axi_rready => s_axi_rready,
s_axi4_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_awlock => '0',
s_axi4_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_awvalid => '0',
s_axi4_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi4_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_wlast => '0',
s_axi4_wvalid => '0',
s_axi4_bready => '0',
s_axi4_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi4_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 24)),
s_axi4_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi4_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi4_arlock => '0',
s_axi4_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi4_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi4_arvalid => '0',
s_axi4_rready => '0',
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
io2_i => '0',
io3_i => '0',
spisel => '1',
sck_i => sck_i,
sck_o => sck_o,
sck_t => sck_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
clk => '0',
gsr => '0',
gts => '0',
keyclearb => '0',
usrcclkts => '0',
usrdoneo => '0',
usrdonets => '0',
pack => '0',
ip2intc_irpt => ip2intc_irpt
);
END PmodNAV_axi_quad_spi_0_0_arch;
|
-- $Id: nexys2lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: nexys2lib
-- Description: Nexys 2 components
--
-- Dependencies: -
-- Tool versions: xst 11.4-14.7; ghdl 0.26-0.31
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-01 467 1.4 add nexys2_cuff_aif, nexys2_fusp_cuff_aif
-- 2011-12-23 444 1.3 remove clksys output hack
-- 2011-11-26 433 1.2 remove n2_cram_* modules, now in nxcramlib
-- 2011-11-23 432 1.1 remove O_FLA_CE_N port in cram controller/dummy
-- 2010-11-13 338 1.0.2 add O_CLKSYS to aif's (DCM derived system clock)
-- 2010-11-06 336 1.0.4 rename input pin CLK -> I_CLK50
-- 2010-05-28 295 1.0.3 use _ADV_N also for n2_cram_dummy
-- 2010-05-23 294 1.0.2 add n2_cram_dummy;
-- 2010-05-23 293 1.0.1 use _ADV_N rather _ADV; add generic for memctl
-- 2010-05-21 292 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys2lib is
component nexys2_aif is -- NEXYS 2, abstract iface, base
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit -- flash ce.. (act.low)
);
end component;
component nexys2_fusp_aif is -- NEXYS 2, abstract iface, base+fusp
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit -- fusp: rs232 tx
);
end component;
component nexys2_cuff_aif is -- NEXYS 2, abstract iface, base+cuff
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
component nexys2_fusp_cuff_aif is -- NEXYS 2, abstract iface, +fusp+cuff
port (
I_CLK50 : in slbit; -- 50 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv8; -- n2 switches
I_BTN : in slv4; -- n2 buttons
O_LED : out slv8; -- n2 leds
O_ANO_N : out slv4; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
O_MEM_CE_N : out slbit; -- cram: chip enable (act.low)
O_MEM_BE_N : out slv2; -- cram: byte enables (act.low)
O_MEM_WE_N : out slbit; -- cram: write enable (act.low)
O_MEM_OE_N : out slbit; -- cram: output enable (act.low)
O_MEM_ADV_N : out slbit; -- cram: address valid (act.low)
O_MEM_CLK : out slbit; -- cram: clock
O_MEM_CRE : out slbit; -- cram: command register enable
I_MEM_WAIT : in slbit; -- cram: mem wait
O_MEM_ADDR : out slv23; -- cram: address lines
IO_MEM_DATA : inout slv16; -- cram: data lines
O_FLA_CE_N : out slbit; -- flash ce.. (act.low)
O_FUSP_RTS_N : out slbit; -- fusp: rs232 rts_n
I_FUSP_CTS_N : in slbit; -- fusp: rs232 cts_n
I_FUSP_RXD : in slbit; -- fusp: rs232 rx
O_FUSP_TXD : out slbit; -- fusp: rs232 tx
I_FX2_IFCLK : in slbit; -- fx2: interface clock
O_FX2_FIFO : out slv2; -- fx2: fifo address
I_FX2_FLAG : in slv4; -- fx2: fifo flags
O_FX2_SLRD_N : out slbit; -- fx2: read enable (act.low)
O_FX2_SLWR_N : out slbit; -- fx2: write enable (act.low)
O_FX2_SLOE_N : out slbit; -- fx2: output enable (act.low)
O_FX2_PKTEND_N : out slbit; -- fx2: packet end (act.low)
IO_FX2_DATA : inout slv8 -- fx2: data lines
);
end component;
end package nexys2lib;
|
library ieee;
library std;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity core_c is
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
wr_i : in std_logic;
bidir_io : inout std_logic_vector( 7 downto 0 )
);
end entity;
architecture IMP of core_c is
signal cnt : unsigned( 7 downto 0 );
begin
p : process( clk, rst )
begin
if clk'event and clk='1' then
if rst = '1' then
cnt <= ( others => '0' );
bidir <= ( others => 'Z' );
else
-- default case: we increase the counter
cnt <= cnt+1;
if en = '0' then
if wr = '1' then
cnt <= unsigned( bidir );
end if;
bidir <= ( others => 'Z' );
else
bidir <= std_logic_vector( cnt );
end if;
end if;
end if;
end process;
end architecture IMP;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3009.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03009pkg is
subtype S1 is Integer;
subtype S2 is Integer;
constant C : S1;
end c02s06b00x00p07n01i03009pkg;
package body c02s06b00x00p07n01i03009pkg is
constant C : S2 := 0; --Failure_here
end c02s06b00x00p07n01i03009pkg;
ENTITY c02s06b00x00p07n01i03009ent IS
END c02s06b00x00p07n01i03009ent;
ARCHITECTURE c02s06b00x00p07n01i03009arch OF c02s06b00x00p07n01i03009ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03009 - The subtype of deferred constant does not conform to that given in the deferred constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3009.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03009pkg is
subtype S1 is Integer;
subtype S2 is Integer;
constant C : S1;
end c02s06b00x00p07n01i03009pkg;
package body c02s06b00x00p07n01i03009pkg is
constant C : S2 := 0; --Failure_here
end c02s06b00x00p07n01i03009pkg;
ENTITY c02s06b00x00p07n01i03009ent IS
END c02s06b00x00p07n01i03009ent;
ARCHITECTURE c02s06b00x00p07n01i03009arch OF c02s06b00x00p07n01i03009ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03009 - The subtype of deferred constant does not conform to that given in the deferred constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03009arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3009.vhd,v 1.2 2001-10-26 16:30:24 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s06b00x00p07n01i03009pkg is
subtype S1 is Integer;
subtype S2 is Integer;
constant C : S1;
end c02s06b00x00p07n01i03009pkg;
package body c02s06b00x00p07n01i03009pkg is
constant C : S2 := 0; --Failure_here
end c02s06b00x00p07n01i03009pkg;
ENTITY c02s06b00x00p07n01i03009ent IS
END c02s06b00x00p07n01i03009ent;
ARCHITECTURE c02s06b00x00p07n01i03009arch OF c02s06b00x00p07n01i03009ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c02s06b00x00p07n01i03009 - The subtype of deferred constant does not conform to that given in the deferred constant declaration."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s06b00x00p07n01i03009arch;
|
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
|
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
|
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
|
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
|
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
x := x + 1;
end procedure;
begin
process is
variable v : integer := 0;
begin
proc(v);
assert v = 3;
wait;
end process;
end architecture;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00009_Test_Bench is
end ENT00009_Test_Bench;
architecture ARCH00009_Test_Bench of ENT00009_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b2 : byte2 := x"00";
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal ea : enum_array(0 to 3) := (others => a_v);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
signal
bit_1, bit_2, bit_3, bit_4
, bit_5, bit_6, bit_7, bit_8
, bit_9, bit_10, bit_11, bit_12 : bit;
begin
bit_1 <= bv'Transaction;
bit_2 <= ra'Transaction;
bit_3 <= r'Transaction;
bit_4 <= ea'Transaction;
bit_5 <= e'Transaction;
bit_6 <= I_sa'Transaction;
bit_7 <= I_baa'Transaction;
bit_8 <= I_saa'Transaction;
bit_9 <= b1'Transaction;
bit_10 <= b2'Transaction;
bit_11 <= clk'Transaction;
bit_12 <= clk2'Transaction;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00009_Test_Bench; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end usb1_ulpi_rx;
architecture gideon of usb1_ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.usb1_data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : in std_logic_vector(7 downto 0);
rx_last : in std_logic;
rx_valid : in std_logic;
rx_store : in std_logic;
pid : out std_logic_vector(3 downto 0);
valid_token : out std_logic;
valid_handsh : out std_logic;
token : out std_logic_vector(10 downto 0);
valid_packet : out std_logic;
data_valid : out std_logic;
data_start : out std_logic;
data_out : out std_logic_vector(7 downto 0);
error : out std_logic );
end usb1_ulpi_rx;
architecture gideon of usb1_ulpi_rx is
type t_state is (idle, token1, token2, check_token, check_token2, resync,
data, data_check, handshake );
signal state : t_state;
signal token_i : std_logic_vector(10 downto 0) := (others => '0');
signal token_crc : std_logic_vector(4 downto 0) := (others => '0');
signal crc_in : std_logic_vector(4 downto 0);
signal crc_dvalid : std_logic;
signal crc_sync : std_logic;
signal data_crc : std_logic_vector(15 downto 0);
begin
token <= token_i;
data_out <= rx_data;
data_valid <= rx_store when state = data else '0';
process(clock)
begin
if rising_edge(clock) then
data_start <= '0';
error <= '0';
valid_token <= '0';
valid_packet <= '0';
valid_handsh <= '0';
case state is
when idle =>
if rx_valid='1' and rx_store='1' then -- wait for first byte
if rx_data(7 downto 4) = not rx_data(3 downto 0) then
pid <= rx_data(3 downto 0);
if is_handshake(rx_data(3 downto 0)) then
if rx_last = '1' then
valid_handsh <= '1';
else
state <= handshake;
end if;
elsif is_token(rx_data(3 downto 0)) then
if g_allow_token then
state <= token1;
else
error <= '1';
end if;
else
data_start <= '1';
state <= data;
end if;
else -- error in PID
error <= '1';
end if;
end if;
when handshake =>
if rx_store='1' then -- more data? error
error <= '1';
state <= resync;
elsif rx_last = '1' then
valid_handsh <= '1';
state <= idle;
end if;
when token1 =>
if rx_store='1' then
token_i(7 downto 0) <= rx_data;
state <= token2;
end if;
if rx_last='1' then -- should not occur here
error <= '1';
state <= idle; -- good enough?
end if;
when token2 =>
if rx_store='1' then
token_i(10 downto 8) <= rx_data(2 downto 0);
crc_in <= rx_data(7 downto 3);
state <= check_token;
end if;
when data =>
if rx_last='1' then
state <= data_check;
end if;
when data_check =>
if data_crc = X"4FFE" then
valid_packet <= '1';
else
error <= '1';
end if;
state <= idle;
when check_token =>
state <= check_token2; -- delay
when check_token2 =>
if crc_in = token_crc then
valid_token <= '1';
else
error <= '1';
end if;
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
else
state <= resync;
end if;
when resync =>
if rx_last='1' then
state <= idle;
elsif rx_valid='0' then
state <= idle;
end if;
when others =>
null;
end case;
if reset = '1' then
state <= idle;
pid <= X"0";
end if;
end if;
end process;
r_token: if g_allow_token generate
i_token_crc: entity work.usb1_token_crc
port map (
clock => clock,
sync => '1',
token_in => token_i,
crc => token_crc );
end generate;
crc_sync <= '1' when state = idle else '0';
crc_dvalid <= rx_store when state = data else '0';
i_data_crc: entity work.usb1_data_crc
port map (
clock => clock,
sync => crc_sync,
valid => crc_dvalid,
data_in => rx_data,
crc => data_crc );
end gideon;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ae
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ent_ae-e.vhd,v 1.3 2005/07/15 16:20:07 wig Exp $
-- $Date: 2005/07/15 16:20:07 $
-- $Log: ent_ae-e.vhd,v $
-- Revision 1.3 2005/07/15 16:20:07 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- Generated use statements
library use_ae;
use use_ae.c_ae.all;
use use_ae.c_ae2.all;
--
--
-- Start of Generated Entity ent_ae
--
entity ent_ae is
-- Generics:
-- No Generated Generics for Entity ent_ae
-- Generated Port Declaration:
port(
-- Generated Port for Entity ent_ae
port_ae_2 : in std_ulogic_vector(4 downto 0);
port_ae_5 : in std_ulogic_vector(3 downto 0);
port_ae_6 : in std_ulogic_vector(3 downto 0);
sig_07 : in std_ulogic_vector(5 downto 0);
sig_08 : in std_ulogic_vector(8 downto 2);
sig_i_ae : in std_ulogic_vector(6 downto 0);
sig_o_ae : out std_ulogic_vector(7 downto 0)
-- End of Generated Port for Entity ent_ae
);
end ent_ae;
--
-- End of Generated Entity ent_ae
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: Serial multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpupack.all;
entity serial_mul is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end serial_mul;
architecture rtl of serial_mul is
type t_state is (waiting,busy);
signal s_fract_o: std_logic_vector(47 downto 0);
signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_start_i, s_ready_o : std_logic;
signal s_state : t_state;
signal s_count : integer range 0 to 23;
signal s_tem_prod : std_logic_vector(23 downto 0);
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_start_i <= start_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
ready_o <= s_ready_o;
end if;
end process;
s_sign_o <= signa_i xor signb_i;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
s_count <= 0;
elsif s_count=23 then
s_state <= waiting;
s_ready_o <= '1';
s_count <=0;
elsif s_state=busy then
s_count <= s_count + 1;
else
s_state <= waiting;
s_ready_o <= '0';
end if;
end if;
end process;
g1: for i in 0 to 23 generate
s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
end generate;
process(clk_i)
variable v_prod_shl : std_logic_vector(47 downto 0);
begin
if rising_edge(clk_i) then
if s_state=busy then
v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
if s_count /= 0 then
s_fract_o <= v_prod_shl + s_fract_o;
else
s_fract_o <= v_prod_shl;
end if;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: Serial multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpupack.all;
entity serial_mul is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end serial_mul;
architecture rtl of serial_mul is
type t_state is (waiting,busy);
signal s_fract_o: std_logic_vector(47 downto 0);
signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_start_i, s_ready_o : std_logic;
signal s_state : t_state;
signal s_count : integer range 0 to 23;
signal s_tem_prod : std_logic_vector(23 downto 0);
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_start_i <= start_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
ready_o <= s_ready_o;
end if;
end process;
s_sign_o <= signa_i xor signb_i;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
s_count <= 0;
elsif s_count=23 then
s_state <= waiting;
s_ready_o <= '1';
s_count <=0;
elsif s_state=busy then
s_count <= s_count + 1;
else
s_state <= waiting;
s_ready_o <= '0';
end if;
end if;
end process;
g1: for i in 0 to 23 generate
s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
end generate;
process(clk_i)
variable v_prod_shl : std_logic_vector(47 downto 0);
begin
if rising_edge(clk_i) then
if s_state=busy then
v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
if s_count /= 0 then
s_fract_o <= v_prod_shl + s_fract_o;
else
s_fract_o <= v_prod_shl;
end if;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: Serial multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: jidan@gmx.net
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library work;
use work.fpupack.all;
entity serial_mul is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end serial_mul;
architecture rtl of serial_mul is
type t_state is (waiting,busy);
signal s_fract_o: std_logic_vector(47 downto 0);
signal s_fracta_i, s_fractb_i : std_logic_vector(23 downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_start_i, s_ready_o : std_logic;
signal s_state : t_state;
signal s_count : integer range 0 to 23;
signal s_tem_prod : std_logic_vector(23 downto 0);
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_start_i <= start_i;
end if;
end process;
-- Output Register
process(clk_i)
begin
if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
ready_o <= s_ready_o;
end if;
end process;
s_sign_o <= signa_i xor signb_i;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
s_count <= 0;
elsif s_count=23 then
s_state <= waiting;
s_ready_o <= '1';
s_count <=0;
elsif s_state=busy then
s_count <= s_count + 1;
else
s_state <= waiting;
s_ready_o <= '0';
end if;
end if;
end process;
g1: for i in 0 to 23 generate
s_tem_prod(i) <= s_fracta_i(i) and s_fractb_i(s_count);
end generate;
process(clk_i)
variable v_prod_shl : std_logic_vector(47 downto 0);
begin
if rising_edge(clk_i) then
if s_state=busy then
v_prod_shl := shl(conv_std_logic_vector(0,24)&s_tem_prod, conv_std_logic_vector(s_count,5));
if s_count /= 0 then
s_fract_o <= v_prod_shl + s_fract_o;
else
s_fract_o <= v_prod_shl;
end if;
end if;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN2_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
--! direct data driver for EPROC_IN2 module
entity EPROC_IN2_direct is
port (
bitCLK : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
edataIN : in std_logic_vector (1 downto 0);
dataOUT : out std_logic_vector(9 downto 0);
dataOUTrdy : out std_logic
);
end EPROC_IN2_direct;
architecture Behavioral of EPROC_IN2_direct is
----------------------------------
----------------------------------
component pulse_pdxx_pwxx
generic(
pd : integer := 0;
pw : integer := 1);
port(
clk : in std_logic;
trigger : in std_logic;
pulseout : out std_logic
);
end component pulse_pdxx_pwxx;
----------------------------------
----------------------------------
signal word10b : std_logic_vector (9 downto 0) := "1100000000"; -- comma
signal word8b : std_logic_vector (7 downto 0) := (others=>'0');
signal inpcount : std_logic_vector (1 downto 0) := (others=>'0');
signal word8bRdy, word10bRdy : std_logic := '0';
begin
-------------------------------------------------------------------------------------------
-- input counter 0 to 3
-------------------------------------------------------------------------------------------
input_count: process(bitCLK, rst)
begin
if rst = '1' then
inpcount <= (others=>'0');
elsif bitCLK'event and bitCLK = '1' then
inpcount <= inpcount + 1;
end if;
end process;
-------------------------------------------------------------------------------------------
-- input mapping
-------------------------------------------------------------------------------------------
input_map: process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
case inpcount is
when "00" => word8b(1 downto 0) <= edataIN;
when "01" => word8b(3 downto 2) <= edataIN;
when "10" => word8b(5 downto 4) <= edataIN;
when "11" => word8b(7 downto 6) <= edataIN;
when others =>
end case;
end if;
end process;
-------------------------------------------------------------------------------------------
-- output (code = "00" = data)
-------------------------------------------------------------------------------------------
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if inpcount = "11" then
word8bRdy <= '1';
else
word8bRdy <= '0';
end if;
end if;
end process;
--
process(bitCLK)
begin
if bitCLK'event and bitCLK = '1' then
if word8bRdy = '1' then
word10b <= "00" & word8b; -- data
word10bRdy <= '1';
else
word10bRdy <= '0';
end if;
end if;
end process;
dataOUT <= word10b;
dataOUTrdy_pulse: pulse_pdxx_pwxx GENERIC MAP(pd=>0,pw=>1) PORT MAP(bitCLKx4, word10bRdy, dataOUTrdy);
end Behavioral;
|
-- NEED RESULT: ARCH00151.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151.P2: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151.P3: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151: Old transactions were removed on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: One inertial transaction occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151: Inertial semantics check on a signal asg with selected name on LHS passed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00151
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00151(ARCH00151)
-- ENT00151_Test_Bench(ARCH00151_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00151 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1 : chk_sig_type := -1 ;
signal chk_st_rec2 : chk_sig_type := -1 ;
signal chk_st_rec3 : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1 : inout st_rec1 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns,
c_st_rec1_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1.f2 <= c_st_rec1_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= transport
c_st_rec1_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <=
c_st_rec1_2.f2 after 10 ns ,
c_st_rec1_1.f2 after 20 ns ,
c_st_rec1_2.f2 after 30 ns ,
c_st_rec1_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec1.f2 = c_st_rec1_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec1.f2 <= -- Last transaction above is marked
c_st_rec1_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1.f2 = c_st_rec1_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2 : inout st_rec2 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns,
c_st_rec2_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2.f2 <= c_st_rec2_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= transport
c_st_rec2_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <=
c_st_rec2_2.f2 after 10 ns ,
c_st_rec2_1.f2 after 20 ns ,
c_st_rec2_2.f2 after 30 ns ,
c_st_rec2_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec2.f2 = c_st_rec2_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec2.f2 <= -- Last transaction above is marked
c_st_rec2_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2.f2 = c_st_rec2_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3 : inout st_rec3 ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3 : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns,
c_st_rec3_1.f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3.f2 <= c_st_rec3_1.f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= transport
c_st_rec3_1.f2 after 100 ns ;
--
when 5
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Old transactions were removed on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <=
c_st_rec3_2.f2 after 10 ns ,
c_st_rec3_1.f2 after 20 ns ,
c_st_rec3_2.f2 after 30 ns ,
c_st_rec3_1.f2 after 40 ns ;
--
when 6
=> correct :=
s_st_rec3.f2 = c_st_rec3_2.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"One inertial transaction occurred on signal " &
"asg with selected name on LHS",
correct ) ;
s_st_rec3.f2 <= -- Last transaction above is marked
c_st_rec3_1.f2 after 40 ns ;
--
when 7
=> correct :=
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3.f2 = c_st_rec3_1.f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00151" ,
"Inertial semantics check on a signal " &
"asg with selected name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3 <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00151 ;
--
architecture ARCH00151 of ENT00151 is
signal s_st_rec1 : st_rec1
:= c_st_rec1_1 ;
signal s_st_rec2 : st_rec2
:= c_st_rec2_1 ;
signal s_st_rec3 : st_rec3
:= c_st_rec3_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1,
counter,
correct,
savtime,
chk_st_rec1
) ;
wait until (not s_st_rec1'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_rec1 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_rec1 = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2,
counter,
correct,
savtime,
chk_st_rec2
) ;
wait until (not s_st_rec2'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_rec2 = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3,
counter,
correct,
savtime,
chk_st_rec3
) ;
wait until (not s_st_rec3'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3 )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_rec3 = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
--
end ARCH00151 ;
--
entity ENT00151_Test_Bench is
end ENT00151_Test_Bench ;
--
architecture ARCH00151_Test_Bench of ENT00151_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00151 ( ARCH00151 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00151_Test_Bench ;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- package: sui
-- File: sui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package sui is
type sui_in_type is record
post_code_in : std_logic_vector(7 downto 0);
switch_in : std_logic_vector(31 downto 0);
button_in : std_logic_vector(31 downto 0);
lcd_in : std_logic_vector(7 downto 0);
end record;
type sui_out_type is record
led_a_out : std_logic_vector(3 downto 0);
led_b_out : std_logic_vector(3 downto 0);
led_c_out : std_logic_vector(3 downto 0);
led_d_out : std_logic_vector(3 downto 0);
led_e_out : std_logic_vector(3 downto 0);
led_f_out : std_logic_vector(3 downto 0);
led_g_out : std_logic_vector(3 downto 0);
led_dp_out : std_logic_vector(3 downto 0);
led_com_out : std_logic_vector(31 downto 0);
led_out : std_logic_vector(31 downto 0);
lcd_out : std_logic_vector(7 downto 0);
lcd_oe : std_logic;
lcd_en : std_logic_vector(3 downto 0);
lcd_rs : std_logic;
lcd_r_wn : std_logic;
lcd_backlight : std_logic;
buzzer : std_logic;
end record;
component apbsui
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end component;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- package: sui
-- File: sui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package sui is
type sui_in_type is record
post_code_in : std_logic_vector(7 downto 0);
switch_in : std_logic_vector(31 downto 0);
button_in : std_logic_vector(31 downto 0);
lcd_in : std_logic_vector(7 downto 0);
end record;
type sui_out_type is record
led_a_out : std_logic_vector(3 downto 0);
led_b_out : std_logic_vector(3 downto 0);
led_c_out : std_logic_vector(3 downto 0);
led_d_out : std_logic_vector(3 downto 0);
led_e_out : std_logic_vector(3 downto 0);
led_f_out : std_logic_vector(3 downto 0);
led_g_out : std_logic_vector(3 downto 0);
led_dp_out : std_logic_vector(3 downto 0);
led_com_out : std_logic_vector(31 downto 0);
led_out : std_logic_vector(31 downto 0);
lcd_out : std_logic_vector(7 downto 0);
lcd_oe : std_logic;
lcd_en : std_logic_vector(3 downto 0);
lcd_rs : std_logic;
lcd_r_wn : std_logic;
lcd_backlight : std_logic;
buzzer : std_logic;
end record;
component apbsui
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end component;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- package: sui
-- File: sui.vhd
-- Author: Antti Lukats, OpenChip
-- Description: Simple User Interface types and components
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
package sui is
type sui_in_type is record
post_code_in : std_logic_vector(7 downto 0);
switch_in : std_logic_vector(31 downto 0);
button_in : std_logic_vector(31 downto 0);
lcd_in : std_logic_vector(7 downto 0);
end record;
type sui_out_type is record
led_a_out : std_logic_vector(3 downto 0);
led_b_out : std_logic_vector(3 downto 0);
led_c_out : std_logic_vector(3 downto 0);
led_d_out : std_logic_vector(3 downto 0);
led_e_out : std_logic_vector(3 downto 0);
led_f_out : std_logic_vector(3 downto 0);
led_g_out : std_logic_vector(3 downto 0);
led_dp_out : std_logic_vector(3 downto 0);
led_com_out : std_logic_vector(31 downto 0);
led_out : std_logic_vector(31 downto 0);
lcd_out : std_logic_vector(7 downto 0);
lcd_oe : std_logic;
lcd_en : std_logic_vector(3 downto 0);
lcd_rs : std_logic;
lcd_r_wn : std_logic;
lcd_backlight : std_logic;
buzzer : std_logic;
end record;
component apbsui
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
pirq : integer := 0;
-- active level for Segment LED segments
led7act : integer := 1;
-- active level for single LED's
ledact : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
suii : in sui_in_type;
suio : out sui_out_type);
end component;
end;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- ____ _ ____ _ _ _ _
-- | _ \(_) ___ ___ | __ )| | __ _ _______ | | (_) |__ _ __ __ _ _ __ _ _
-- | |_) | |/ __/ _ \| _ \| |/ _` |_ / _ \ | | | | '_ \| '__/ _` | '__| | | |
-- | __/| | (_| (_) | |_) | | (_| |/ / __/ | |___| | |_) | | | (_| | | | |_| |
-- |_| |_|\___\___/|____/|_|\__,_/___\___| |_____|_|_.__/|_| \__,_|_| \__, |
-- |___/
-- =============================================================================
-- Authors: Patrick Lehmann
--
-- Module: Wrapper module for up to 8 PicoBlaze ROM pages. All ROMs are
-- reprogrammable via JTAG_Loader
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- -----------------------------------------------------------------------------
-- Copyright 2007-2015 Patrick Lehmann - Dresden, Germany
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.components.all;
use PoC.ocram.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
use L_PicoBlaze.pb_comp.all;
entity pb_InstructionROM_Device is
generic (
PAGES : POSITIVE := 1;
SOURCE_DIRECTORY : STRING := "";
DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE;
ENABLE_JTAG_LOADER : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
Fetch : in STD_LOGIC;
InstructionPointer : in T_PB_ADDRESS;
Instruction : out T_PB_INSTRUCTION;
Reboot : out STD_LOGIC;
-- PicoBlaze interface
Address : in T_SLV_8;
WriteStrobe : in STD_LOGIC;
WriteStrobe_K : in STD_LOGIC;
ReadStrobe : in STD_LOGIC;
DataIn : in T_SLV_8;
DataOut : out T_SLV_8;
Interrupt : out STD_LOGIC;
Interrupt_Ack : in STD_LOGIC;
Message : out T_SLV_8;
PageNumber : out STD_LOGIC_VECTOR(2 downto 0)
);
end;
architecture rtl of pb_InstructionROM_Device is
type T_PB_INSTRUCTION_VECTOR is array (NATURAL range <>) of T_PB_INSTRUCTION;
function reverse(vec : T_PB_INSTRUCTION_VECTOR) return T_PB_INSTRUCTION_VECTOR is
variable res : T_PB_INSTRUCTION_VECTOR(vec'range);
begin
for i in vec'low to vec'high loop
res(vec'low + (vec'high - i)) := vec(i);
end loop;
return res;
end function;
constant ENABLE_LOADER : BOOLEAN := ite((VENDOR = VENDOR_XILINX), ENABLE_JTAG_LOADER, FALSE);
constant FILENAME_PATTERN : STRING := ite((VENDOR = VENDOR_ALTERA), "main_Page#.mif", "main_Page#.hex");
constant REG_RW_PAGE_NUMBER : STD_LOGIC_VECTOR(0 downto 0) := "0";
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reg_PageNumber : T_SLV_8 := (others => '0');
signal Reg_PageNumber_us : UNSIGNED(log2ceilnz(PAGES) - 1 downto 0) := (others => '0');
signal Page_Instructions : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
signal Pages_DataOut : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
signal JTAGLoader_Clock : STD_LOGIC;
signal JTAGLoader_Enable : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal JTAGLoader_Address : T_PB_ADDRESS;
signal JTAGLoader_WriteEnable : STD_LOGIC;
signal JTAGLoader_DataOut : T_PB_INSTRUCTION;
signal JTAGLoader_PB_Reset : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal Page_n_rst : STD_LOGIC;
signal Page_0_rst : STD_LOGIC;
signal Page_n_rst_d : STD_LOGIC := '0';
signal Page_0_rst_d : STD_LOGIC := '0';
signal Page_n_rst_re : STD_LOGIC;
signal Page_0_rst_fe : STD_LOGIC;
signal Reset_r : STD_LOGIC := '0';
begin
assert (PAGES <= 8) report "This ROM and JTAGLoader6 support 8 pages maximum." severity FAILURE;
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => Clock,
Reset => Reset_r,
-- PicoBlaze interface
In_WriteStrobe => WriteStrobe,
In_WriteStrobe_K => WriteStrobe_K,
In_ReadStrobe => ReadStrobe,
In_Address => Address,
In_Data => DataIn,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => AdrDec_re,
Out_WriteAddress => AdrDec_WriteAddress,
Out_ReadAddress => AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
-- Registers
process(Clock)
begin
if rising_edge(Clock) then
if (Reset_r = '1') then
Reg_PageNumber <= (others => '0');
elsif (AdrDec_we = '1') then
case AdrDec_WriteAddress(0 downto 0) is
when REG_RW_PAGE_NUMBER => Reg_PageNumber <= AdrDec_Data;
when others => null;
end case;
end if;
end if;
end process;
process(AdrDec_re, AdrDec_ReadAddress, Reg_PageNumber)
begin
case AdrDec_ReadAddress(0 downto 0) IS
when REG_RW_PAGE_NUMBER => DataOut <= Reg_PageNumber;
when others => DataOut <= Reg_PageNumber;
end case;
end process;
Interrupt <= '0';
Message <= x"00";
--
PageNumber <= Reg_PageNumber(PageNumber'range);
Reg_PageNumber_us <= unsigned(Reg_PageNumber(Reg_PageNumber_us'range));
Instruction <= Page_Instructions(to_index(Reg_PageNumber_us, Page_Instructions'length));
-- Reset control: keep PB in reset while programming, release after last ROM is written => reboot
Page_n_rst <= JTAGLoader_PB_Reset(PAGES - 1);
Page_0_rst <= JTAGLoader_PB_Reset(0);
Page_n_rst_d <= Page_n_rst when rising_edge(Clock);
Page_0_rst_d <= Page_0_rst when rising_edge(Clock);
Page_n_rst_re <= not Page_n_rst_d and Page_n_rst;
Page_0_rst_fe <= Page_0_rst_d and not Page_0_rst;
Reset_r <= ffrs(q => Reset_r, set => Page_n_rst_re, rst => Page_0_rst_fe) when rising_edge(Clock);
Reboot <= Reset_r;
genTemplate : if (str_length(SOURCE_DIRECTORY) = 0) generate
genPage0 : if (TRUE) generate
constant PAGE_NUMBER : NATURAL := 0;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page0
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage1 : if (PAGES > 1) generate
constant PAGE_NUMBER : NATURAL := 1;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page1
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage2 : if (PAGES > 2) generate
constant PAGE_NUMBER : NATURAL := 2;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page2
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage3 : if (PAGES > 3) generate
constant PAGE_NUMBER : NATURAL := 3;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page3
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage4 : if (PAGES > 4) generate
constant PAGE_NUMBER : NATURAL := 4;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page4
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage5 : if (PAGES > 5) generate
constant PAGE_NUMBER : NATURAL := 5;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page5
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage6 : if (PAGES > 6) generate
constant PAGE_NUMBER : NATURAL := 6;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page6
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
genPage7 : if (PAGES > 7) generate
constant PAGE_NUMBER : NATURAL := 7;
constant PAGE_INDEX : NATURAL := imin(PAGES - 1, PAGE_NUMBER);
begin
page : main_Page7
port map (
Clock => Clock,
Fetch => Fetch,
Address => InstructionPointer,
Instruction => Page_Instructions(PAGE_INDEX),
JTAGLoader_Clock => JTAGLoader_Clock,
JTAGLoader_Enable => JTAGLoader_Enable(PAGE_INDEX),
JTAGLoader_Address => JTAGLoader_Address,
JTAGLoader_WriteEnable => JTAGLoader_WriteEnable,
JTAGLoader_DataOut => Pages_DataOut(PAGE_INDEX),
JTAGLoader_DataIn => JTAGLoader_DataOut
);
end generate;
end generate;
genLoadFile : if (str_length(SOURCE_DIRECTORY) /= 0) generate
genPages : for i in 0 to PAGES - 1 generate
constant FILENAME : STRING := SOURCE_DIRECTORY & str_replace(FILENAME_PATTERN, "#", INTEGER'image(i));
signal Port1_Address : UNSIGNED(InstructionPointer'range);
signal Port2_Address : UNSIGNED(JTAGLoader_Address'range);
begin
assert PB_VERBOSE report "Loading ROM file: '" & FILENAME & "'" severity NOTE;
genOCROM : if (ENABLE_LOADER = FALSE) generate
Port1_Address <= unsigned(InstructionPointer);
genericMemory : ocrom_sp
generic map (
A_BITS => 12,
D_BITS => 18,
FILENAME => FILENAME
)
port map (
clk => Clock,
ce => Fetch,
a => Port1_Address,
q => Page_Instructions(i)
);
end generate;
genOCRAM : if (ENABLE_LOADER = TRUE) generate
Port1_Address <= unsigned(InstructionPointer);
Port2_Address <= unsigned(JTAGLoader_Address);
genericMemory : ocram_tdp
generic map (
A_BITS => 12,
D_BITS => 18,
FILENAME => FILENAME
)
port map (
clk1 => Clock,
ce1 => Fetch,
we1 => '0',
a1 => Port1_Address,
d1 => (others => '0'),
q1 => Page_Instructions(i),
clk2 => JTAGLoader_Clock,
ce2 => JTAGLoader_Enable(i),
we2 => JTAGLoader_WriteEnable,
a2 => Port2_Address,
d2 => JTAGLoader_DataOut,
q2 => Pages_DataOut(i)
);
end generate;
end generate;
end generate;
genNoJTAGLoader : if (ENABLE_LOADER = FALSE) generate
JTAGLoader_Clock <= '0';
JTAGLoader_Enable <= (others => '0');
JTAGLoader_Address <= (others => '0');
JTAGLoader_WriteEnable <= '0';
JTAGLoader_DataOut <= (others => '0');
end generate;
genJTAGLoader : if (ENABLE_LOADER = TRUE) generate
signal WorkAround_Enable : STD_LOGIC_VECTOR(PAGES - 1 downto 0);
signal WorkAround_DataIn : T_PB_INSTRUCTION_VECTOR(PAGES - 1 downto 0);
begin
JTAGLoader : JTAGLoader6
generic map (
C_NUM_PICOBLAZE => PAGES,
C_ADDR_WIDTH => (others => T_PB_ADDRESS'length)
)
port map (
jtag_clk => JTAGLoader_Clock,
jtag_en => WorkAround_Enable,
jtag_din => JTAGLoader_DataOut,
jtag_addr => JTAGLoader_Address,
jtag_we => JTAGLoader_WriteEnable,
jtag_dout_0 => WorkAround_DataIn(imin(PAGES - 1, 0)),
jtag_dout_1 => WorkAround_DataIn(imin(PAGES - 1, 1)),
jtag_dout_2 => WorkAround_DataIn(imin(PAGES - 1, 2)),
jtag_dout_3 => WorkAround_DataIn(imin(PAGES - 1, 3)),
jtag_dout_4 => WorkAround_DataIn(imin(PAGES - 1, 4)),
jtag_dout_5 => WorkAround_DataIn(imin(PAGES - 1, 5)),
jtag_dout_6 => WorkAround_DataIn(imin(PAGES - 1, 6)),
jtag_dout_7 => WorkAround_DataIn(imin(PAGES - 1, 7)),
picoblaze_reset => JTAGLoader_PB_Reset
);
-- work around for a bug in JTAGLoader.exe
WorkAround_DataIn <= reverse(Pages_DataOut);
JTAGLoader_Enable <= reverse(WorkAround_Enable);
end generate;
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: WR_FLASH_FIFO_top.vhd
--
-- Description:
-- This is the FIFO core wrapper with BUFG instances for clock connections.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity WR_FLASH_FIFO_top is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end WR_FLASH_FIFO_top;
architecture xilinx of WR_FLASH_FIFO_top is
SIGNAL wr_clk_i : std_logic;
SIGNAL rd_clk_i : std_logic;
component WR_FLASH_FIFO is
PORT (
WR_CLK : IN std_logic;
RD_CLK : IN std_logic;
RST : IN std_logic;
PROG_FULL : OUT std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(256-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
wr_clk_buf: bufg
PORT map(
i => WR_CLK,
o => wr_clk_i
);
rd_clk_buf: bufg
PORT map(
i => RD_CLK,
o => rd_clk_i
);
fg0 : WR_FLASH_FIFO PORT MAP (
WR_CLK => wr_clk_i,
RD_CLK => rd_clk_i,
RST => rst,
PROG_FULL => prog_full,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_unbounded_func_pkg.all;
package included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector;
end included_pkg;
package body included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector is
variable word_o : std_logic_vector (word_i'left downto word_i'right);
begin
for I in word_i'range loop
word_o (I) := not word_i(I);
end loop;
return word_o;
end function;
end included_pkg;
entity vhdl_unbounded_func is
end vhdl_unbounded_func;
architecture test of vhdl_unbounded_func is
signal test_out1 : std_logic_vector(9 downto 0);
signal test_out2 : std_logic_vector(5 downto 0);
signal neg_test_out1 : std_logic_vector(9 downto 0);
signal neg_test_out2 : std_logic_vector(5 downto 0);
begin
test_out1 <= f_manch_encoder(B"11101");
test_out2 <= f_manch_encoder(B"001");
neg_test_out1 <= negator(test_out1);
neg_test_out2 <= negator(test_out2);
end test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_unbounded_func_pkg.all;
package included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector;
end included_pkg;
package body included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector is
variable word_o : std_logic_vector (word_i'left downto word_i'right);
begin
for I in word_i'range loop
word_o (I) := not word_i(I);
end loop;
return word_o;
end function;
end included_pkg;
entity vhdl_unbounded_func is
end vhdl_unbounded_func;
architecture test of vhdl_unbounded_func is
signal test_out1 : std_logic_vector(9 downto 0);
signal test_out2 : std_logic_vector(5 downto 0);
signal neg_test_out1 : std_logic_vector(9 downto 0);
signal neg_test_out2 : std_logic_vector(5 downto 0);
begin
test_out1 <= f_manch_encoder(B"11101");
test_out2 <= f_manch_encoder(B"001");
neg_test_out1 <= negator(test_out1);
neg_test_out2 <= negator(test_out2);
end test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Basic test for functions that work with unbounded vectors as return
-- and param types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.vhdl_unbounded_func_pkg.all;
package included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector;
end included_pkg;
package body included_pkg is
function negator(word_i : std_logic_vector) return std_logic_vector is
variable word_o : std_logic_vector (word_i'left downto word_i'right);
begin
for I in word_i'range loop
word_o (I) := not word_i(I);
end loop;
return word_o;
end function;
end included_pkg;
entity vhdl_unbounded_func is
end vhdl_unbounded_func;
architecture test of vhdl_unbounded_func is
signal test_out1 : std_logic_vector(9 downto 0);
signal test_out2 : std_logic_vector(5 downto 0);
signal neg_test_out1 : std_logic_vector(9 downto 0);
signal neg_test_out2 : std_logic_vector(5 downto 0);
begin
test_out1 <= f_manch_encoder(B"11101");
test_out2 <= f_manch_encoder(B"001");
neg_test_out1 <= negator(test_out1);
neg_test_out2 <= negator(test_out2);
end test;
|
library verilog;
use verilog.vl_types.all;
entity alt_cal_sv is
generic(
number_of_channels: integer := 1;
channel_address_width: integer := 1;
sim_model_mode : string := "TRUE";
lpm_type : string := "alt_cal_sv";
lpm_hint : string := "UNUSED";
sample_length : vl_logic_vector(0 to 7) := (Hi0, Hi1, Hi1, Hi0, Hi0, Hi1, Hi0, Hi0);
pma_base_address: vl_logic_vector(0 to 11) := (Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0, Hi0)
);
port(
busy : out vl_logic;
clock : in vl_logic;
dprio_addr : out vl_logic_vector(15 downto 0);
dprio_busy : in vl_logic;
dprio_datain : in vl_logic_vector(15 downto 0);
dprio_dataout : out vl_logic_vector(15 downto 0);
dprio_rden : out vl_logic;
dprio_wren : out vl_logic;
quad_addr : out vl_logic_vector(8 downto 0);
remap_addr : in vl_logic_vector(11 downto 0);
reset : in vl_logic;
start : in vl_logic;
testbuses : in vl_logic_vector(7 downto 0)
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of number_of_channels : constant is 1;
attribute mti_svvh_generic_type of channel_address_width : constant is 1;
attribute mti_svvh_generic_type of sim_model_mode : constant is 1;
attribute mti_svvh_generic_type of lpm_type : constant is 1;
attribute mti_svvh_generic_type of lpm_hint : constant is 1;
attribute mti_svvh_generic_type of sample_length : constant is 1;
attribute mti_svvh_generic_type of pma_base_address : constant is 1;
end alt_cal_sv;
|
-- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: LCD Test Application designed for the
-- Spartan-3 Evaluation Kit.
--
-- Authors: Thomas B. Preußer <thomas.preusser@utexas.edu>
-------------------------------------------------------------------------------
-- Copyright 2007-2014 Technische Universität Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity lcd_test is
generic(
CLOCK_FREQ : freq := 100 MHz;
DATA_WIDTH : positive := 8
);
port(
-- Global Reset / Clock
rst, clk : in std_logic;
-- LCD Control Signals
lcd_e : out std_logic;
lcd_rs : out std_logic;
lcd_rw : out std_logic;
lcd_dat : inout std_logic_vector(7 downto 0)
);
end entity lcd_test;
library IEEE;
use IEEE.numeric_std.all;
library PoC;
use PoC.lcd.all;
architecture rtl of lcd_test is
----------------------------------------------------------------------------
-- Transmission Sequence
type tSeq is array (natural range<>) of std_logic_vector(8 downto 0);
constant OutSeq : tSeq := (
'1' & lcd_functionset(DATA_WIDTH, 2, 0), -- two line, 5x8 font
'1' & lcd_displayctrl(true, false, false),-- on, no cursor, no blink
"100000001", -- Display Clear: "00000001"
'1' & lcd_entrymode(true, false), -- inc, no shift
"10000001-", -- Return Home: "0000001-"
"001010000", -- P
"001100001", -- a
"001110011", -- s
"001110011", -- s
"111000000", -- Goto 0x40
"001010100", -- T
"001100101", -- e
"001110011", -- s
"001110100", -- t
"011011010" -- v
);
signal SeqCnt : unsigned(3 downto 0) := (others => '0');
signal Step : std_logic;
-- Synchronized Inputs
signal rst_i : std_logic;
-- LCD Connectivity
signal rdy : std_logic;
signal dat : std_logic_vector(7 downto 0);
signal stb : std_logic;
signal cmd : std_logic;
begin
-- Synchronization of Inputs
process(clk)
begin
if clk'event and clk = '1' then
rst_i <= rst;
end if;
end process;
-- Instantiate LCD Bit Level Module
blkLCD: block
signal lcd_rw_l : std_logic;
signal lcd_dat_i : std_logic_vector(DATA_WIDTH-1 downto 0);
signal lcd_dat_o : std_logic_vector(DATA_WIDTH-1 downto 0);
begin
lcd : lcd_dotmatrix
generic map (
CLOCK_FREQ => CLOCK_FREQ,
DATA_WIDTH => DATA_WIDTH
)
port map(
clk => clk,
rst => rst_i,
rdy => rdy,
stb => stb,
cmd => cmd,
dat => dat,
lcd_e => lcd_e,
lcd_rs => lcd_rs,
lcd_rw => lcd_rw_l,
lcd_dat_i => lcd_dat_i,
lcd_dat_o => lcd_dat_o
);
lcd_rw <= lcd_rw_l;
lcd_dat_i <= lcd_dat(DATA_WIDTH-1 downto 0);
process(lcd_rw_l, lcd_dat_o)
begin
if lcd_rw_l = '1' then
lcd_dat <= (others => 'Z');
else
lcd_dat <= (others => '0');
lcd_dat(7 downto 8-DATA_WIDTH) <= lcd_dat_o;
end if;
end process;
end block;
-- Sequence Counter
process(clk)
begin
if clk'event and clk = '1' then
if rst_i = '1' then
SeqCnt <= (others => '0');
elsif Step = '1' then
SeqCnt <= SeqCnt + 1;
end if;
end if;
end process;
Step <= rdy when (SeqCnt and to_unsigned(OutSeq'length, SeqCnt'length))
/= to_unsigned(OutSeq'length, SeqCnt'length) else '0';
-- LCD Feed
process(SeqCnt, Step)
variable w : std_logic_vector(8 downto 0);
begin
--w := OutSeq(to_integer(SeqCnt))
w := (others => '0');
for i in OutSeq'range loop
if i = to_integer(SeqCnt) then
w := w or OutSeq(i);
end if;
end loop;
stb <= Step;
cmd <= w(8);
dat <= w(7 downto 0);
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc657.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:22 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:34 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00657ent IS
END c03s04b01x00p01n01i00657ent;
ARCHITECTURE c03s04b01x00p01n01i00657arch OF c03s04b01x00p01n01i00657ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type real_vector is array (natural range <>) of real;
subtype real_vector_range is real_vector(hi_to_low_range);
constant C1 : real_vector_range := (others => 3.0);
type real_vector_range_file is file of real_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_range_file open read_mode is "iofile.05";
variable v : real_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00657"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00657 - File reading of real_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00657arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc657.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:22 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:34 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00657ent IS
END c03s04b01x00p01n01i00657ent;
ARCHITECTURE c03s04b01x00p01n01i00657arch OF c03s04b01x00p01n01i00657ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type real_vector is array (natural range <>) of real;
subtype real_vector_range is real_vector(hi_to_low_range);
constant C1 : real_vector_range := (others => 3.0);
type real_vector_range_file is file of real_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_range_file open read_mode is "iofile.05";
variable v : real_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00657"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00657 - File reading of real_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00657arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc657.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:55 1996 --
-- **************************** --
-- **************************** --
-- Reversed to VHDL 87 by reverse87.pl - Tue Nov 5 11:26:22 1996 --
-- **************************** --
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Mon Nov 4 17:36:34 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00657ent IS
END c03s04b01x00p01n01i00657ent;
ARCHITECTURE c03s04b01x00p01n01i00657arch OF c03s04b01x00p01n01i00657ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type real_vector is array (natural range <>) of real;
subtype real_vector_range is real_vector(hi_to_low_range);
constant C1 : real_vector_range := (others => 3.0);
type real_vector_range_file is file of real_vector_range;
signal k : integer := 0;
BEGIN
TESTING: PROCESS
file filein : real_vector_range_file open read_mode is "iofile.05";
variable v : real_vector_range := C1;
BEGIN
for i in 1 to 100 loop
assert(endfile(filein) = false) report"end of file reached before expected";
read(filein,v);
if (v /= C1) then
k <= 1;
end if;
end loop;
wait for 1 ns;
assert NOT(k = 0)
report "***PASSED TEST: c03s04b01x00p01n01i00657"
severity NOTE;
assert (k = 0)
report "***FAILED TEST: c03s04b01x00p01n01i00657 - File reading of real_vector_range_file operation failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00657arch;
|
---------------------------------------------------------------------------------------------------------
-- MMU in
-- This block handles input values for the DRAM, to perform read/write operation.
-- It is in charge for translating virtual aligned address in physical uniligned addresses and feed
-- the DRAM with the correct data. In case of unaligned access to memory unaligned control signal is
-- asserted
---------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.globals.all;
---------------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------------
entity mmu_in_dram is
port (
--INPUTS
mem_op : in std_logic_vector(5 downto 0); -- control signal which groups the control signals directed to the memory (sb, sw, lbu, lw, lhu, lb)
aligned_address : in std_logic_vector(31 downto 0); -- aligned access to be translated
data : in std_logic_vector(31 downto 0); -- data to be written at the address specified in aligned address
--OUTPUTS
unaligned : out std_logic; -- signal directed to the PSW, asserted in case of unaligned access to the memory
nibble : out std_logic_vector(1 downto 0); -- last two bit of the incoming address in case of lb, sb, lbu, lhu
write_op : out std_logic; -- write signal to the memory
read_op : out std_logic; -- read signal to the memory
mem_address : out std_logic_vector(31 downto 0); -- physical address to memory
mem_data : out std_logic_vector(31 downto 0); -- data to written in the right format
write_byte : out std_logic -- Inform DRAM that we want to write a byte
);
end mmu_in_dram;
------------------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------------------------------
architecture behavioral of mmu_in_dram is
begin
-----------------------
-- Name: Comb Logic
-- Type: Combinational
-- Purpose: Implement
-- the combinational
-- logic of the MMU
-----------------------
comb_logic:process(mem_op, aligned_address, data)
begin
case mem_op is
when "000100" => -- lw
-- check address alignement
if (aligned_address(1 downto 0) = "00") then
unaligned <= '0';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0'); -- not used here
else
-- raise exception
unaligned <= '1';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
end if;
when "000010" => -- lhu2
-- check address alignement
if (aligned_address(0) = '0') then
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
write_byte <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0'); -- not used here
else
unaligned <= '1';
nibble <= "00";
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
end if;
when "000001" => -- lb
-- unaligned access are allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
when "001000" => -- lbu
-- unaligned access are allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '0';
read_op <= '1';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
when "010000" => -- sw
-- check for alignement
if (aligned_address(1 downto 0) = "00") then
unaligned <= '0';
nibble <= "00";
write_op <= '1';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= data;
write_byte <= '0';
else
-- raise exception, write is not performed
unaligned <= '1';
nibble <= "00";
write_op <= '0';
read_op <= '0';
mem_address <= "00" & aligned_address(31 downto 2);
mem_data <= (others => '0');
write_byte <= '0';
end if;
when "100000" => -- sb
-- unaligned access is allowed
unaligned <= '0';
nibble <= aligned_address(1 downto 0);
write_op <= '1';
write_byte <= '1';
read_op <= '0';
mem_data(7 downto 0) <= data(7 downto 0);
mem_data(31 downto 8) <= (others => '0');
mem_address <= "00" & aligned_address(31 downto 2);
when others =>
unaligned <= '0';
nibble <= "00";
write_op <= '0';
write_byte <= '0';
read_op <= '0';
mem_data <= (others => '0');
mem_address <= (others => '0');
end case;
end process;
end architecture;
|
package pack is
function "=" (L: bit; R: bit) return bit;
end package;
use work.pack.all;
entity issue568 is
generic (x : boolean);
end entity;
architecture test of issue568 is
signal y : bit;
begin
p1: assert (y = '1') or (not x);
end architecture;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact office@br-automation.com
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.math_real.log2;
use ieee.math_real.ceil;
library work;
use work.global.all;
entity openMAC_DMAmaster is
generic(
simulate : boolean := false;
dma_highadr_g : integer := 31;
gen_tx_fifo_g : boolean := true;
gen_rx_fifo_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_burstcount_const_g : boolean := true;
m_tx_burst_size_g : integer := 16;
m_rx_burst_size_g : integer := 16;
tx_fifo_word_size_g : integer := 32;
rx_fifo_word_size_g : integer := 32;
fifo_data_width_g : integer := 16;
gen_dma_observer_g : boolean := true
);
port(
dma_clk : in std_logic;
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_dout : in std_logic_vector(15 downto 0);
dma_rd_len : in std_logic_vector(11 downto 0);
m_readdata : in std_logic_vector(fifo_data_width_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_rd_err : out std_logic;
dma_wr_err : out std_logic;
m_read : out std_logic;
m_write : out std_logic;
dma_din : out std_logic_vector(15 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_writedata : out std_logic_vector(fifo_data_width_g-1 downto 0)
);
end openMAC_DMAmaster;
architecture strct of openMAC_DMAmaster is
---- Component declarations -----
component dma_handler
generic(
dma_highadr_g : integer := 31;
gen_dma_observer_g : boolean := true;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr : in std_logic_vector(dma_highadr_g downto 1);
dma_clk : in std_logic;
dma_rd_len : in std_logic_vector(11 downto 0);
dma_req_overflow : in std_logic;
dma_req_rd : in std_logic;
dma_req_wr : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_wr_clk : in std_logic;
rx_wr_empty : in std_logic;
rx_wr_full : in std_logic;
rx_wr_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_rd_clk : in std_logic;
tx_rd_empty : in std_logic;
tx_rd_full : in std_logic;
tx_rd_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
dma_ack_rd : out std_logic;
dma_ack_wr : out std_logic;
dma_addr_out : out std_logic_vector(dma_highadr_g downto 1);
dma_new_addr_rd : out std_logic;
dma_new_addr_wr : out std_logic;
dma_new_len : out std_logic;
dma_rd_err : out std_logic;
dma_rd_len_out : out std_logic_vector(11 downto 0);
dma_wr_err : out std_logic;
rx_aclr : out std_logic;
rx_wr_req : out std_logic;
tx_rd_req : out std_logic
);
end component;
component master_handler
generic(
dma_highadr_g : integer := 31;
fifo_data_width_g : integer := 16;
gen_rx_fifo_g : boolean := true;
gen_tx_fifo_g : boolean := true;
m_burst_wr_const_g : boolean := true;
m_burstcount_width_g : integer := 4;
m_rx_burst_size_g : integer := 16;
m_tx_burst_size_g : integer := 16;
rx_fifo_word_size_log2_g : natural := 5;
tx_fifo_word_size_log2_g : natural := 5
);
port (
dma_addr_in : in std_logic_vector(dma_highadr_g downto 1);
dma_len_rd : in std_logic_vector(11 downto 0);
dma_new_addr_rd : in std_logic;
dma_new_addr_wr : in std_logic;
dma_new_len_rd : in std_logic;
m_clk : in std_logic;
m_readdatavalid : in std_logic;
m_waitrequest : in std_logic;
mac_rx_off : in std_logic;
mac_tx_off : in std_logic;
rst : in std_logic;
rx_rd_clk : in std_logic;
rx_rd_empty : in std_logic;
rx_rd_full : in std_logic;
rx_rd_usedw : in std_logic_vector(rx_fifo_word_size_log2_g-1 downto 0);
tx_wr_clk : in std_logic;
tx_wr_empty : in std_logic;
tx_wr_full : in std_logic;
tx_wr_usedw : in std_logic_vector(tx_fifo_word_size_log2_g-1 downto 0);
m_address : out std_logic_vector(dma_highadr_g downto 0);
m_burstcount : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_burstcounter : out std_logic_vector(m_burstcount_width_g-1 downto 0);
m_byteenable : out std_logic_vector(fifo_data_width_g/8-1 downto 0);
m_read : out std_logic;
m_write : out std_logic;
rx_rd_req : out std_logic;
tx_aclr : out std_logic;
tx_wr_req : out std_logic
);
end component;
---- Architecture declarations -----
--constants
constant tx_fifo_word_size_c : natural := natural(tx_fifo_word_size_g);
constant tx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(tx_fifo_word_size_c))));
constant rx_fifo_word_size_c : natural := natural(rx_fifo_word_size_g);
constant rx_fifo_word_size_log2_c : natural := natural(ceil(log2(real(rx_fifo_word_size_c))));
---- Signal declarations used on the diagram ----
signal dma_new_addr_rd : std_logic;
signal dma_new_addr_wr : std_logic;
signal dma_new_rd_len : std_logic;
signal m_dma_new_addr_rd : std_logic;
signal m_dma_new_addr_wr : std_logic;
signal m_dma_new_rd_len : std_logic;
signal m_mac_rx_off : std_logic;
signal m_mac_tx_off : std_logic;
signal rx_aclr : std_logic;
signal rx_rd_clk : std_logic;
signal rx_rd_empty : std_logic;
signal rx_rd_full : std_logic;
signal rx_rd_req : std_logic;
signal rx_wr_clk : std_logic;
signal rx_wr_empty : std_logic;
signal rx_wr_full : std_logic;
signal rx_wr_req : std_logic;
signal rx_wr_req_s : std_logic;
signal tx_aclr : std_logic;
signal tx_rd_clk : std_logic;
signal tx_rd_empty : std_logic;
signal tx_rd_empty_s : std_logic;
signal tx_rd_empty_s_l : std_logic;
signal tx_rd_full : std_logic;
signal tx_rd_req : std_logic;
signal tx_rd_req_s : std_logic;
signal tx_rd_sel_word : std_logic;
signal tx_wr_clk : std_logic;
signal tx_wr_empty : std_logic;
signal tx_wr_full : std_logic;
signal tx_wr_req : std_logic;
signal dma_addr_trans : std_logic_vector (dma_highadr_g downto 1);
signal dma_rd_len_trans : std_logic_vector (11 downto 0);
signal rd_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal rx_rd_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal rx_wr_usedw : std_logic_vector (rx_fifo_word_size_log2_c-1 downto 0);
signal tx_rd_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal tx_wr_usedw : std_logic_vector (tx_fifo_word_size_log2_c-1 downto 0);
signal wr_data : std_logic_vector (fifo_data_width_g-1 downto 0);
signal wr_data_s : std_logic_vector (fifo_data_width_g/2-1 downto 0);
begin
---- Component instantiations ----
THE_DMA_HANDLER : dma_handler
generic map (
dma_highadr_g => dma_highadr_g,
gen_dma_observer_g => gen_dma_observer_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_ack_rd => dma_ack_rd,
dma_ack_wr => dma_ack_wr,
dma_addr => dma_addr( dma_highadr_g downto 1 ),
dma_addr_out => dma_addr_trans( dma_highadr_g downto 1 ),
dma_clk => dma_clk,
dma_new_addr_rd => dma_new_addr_rd,
dma_new_addr_wr => dma_new_addr_wr,
dma_new_len => dma_new_rd_len,
dma_rd_err => dma_rd_err,
dma_rd_len => dma_rd_len,
dma_rd_len_out => dma_rd_len_trans,
dma_req_overflow => dma_req_overflow,
dma_req_rd => dma_req_rd,
dma_req_wr => dma_req_wr,
dma_wr_err => dma_wr_err,
mac_rx_off => mac_rx_off,
mac_tx_off => mac_tx_off,
rst => rst,
rx_aclr => rx_aclr,
rx_wr_clk => rx_wr_clk,
rx_wr_empty => rx_wr_empty,
rx_wr_full => rx_wr_full,
rx_wr_req => rx_wr_req,
rx_wr_usedw => rx_wr_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_rd_clk => tx_rd_clk,
tx_rd_empty => tx_rd_empty,
tx_rd_full => tx_rd_full,
tx_rd_req => tx_rd_req,
tx_rd_usedw => tx_rd_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
THE_MASTER_HANDLER : master_handler
generic map (
dma_highadr_g => dma_highadr_g,
fifo_data_width_g => fifo_data_width_g,
gen_rx_fifo_g => gen_rx_fifo_g,
gen_tx_fifo_g => gen_tx_fifo_g,
m_burst_wr_const_g => m_burstcount_const_g,
m_burstcount_width_g => m_burstcount_width_g,
m_rx_burst_size_g => m_rx_burst_size_g,
m_tx_burst_size_g => m_tx_burst_size_g,
rx_fifo_word_size_log2_g => rx_fifo_word_size_log2_c,
tx_fifo_word_size_log2_g => tx_fifo_word_size_log2_c
)
port map(
dma_addr_in => dma_addr_trans( dma_highadr_g downto 1 ),
dma_len_rd => dma_rd_len_trans,
dma_new_addr_rd => m_dma_new_addr_rd,
dma_new_addr_wr => m_dma_new_addr_wr,
dma_new_len_rd => m_dma_new_rd_len,
m_address => m_address( dma_highadr_g downto 0 ),
m_burstcount => m_burstcount( m_burstcount_width_g-1 downto 0 ),
m_burstcounter => m_burstcounter( m_burstcount_width_g-1 downto 0 ),
m_byteenable => m_byteenable( fifo_data_width_g/8-1 downto 0 ),
m_clk => m_clk,
m_read => m_read,
m_readdatavalid => m_readdatavalid,
m_waitrequest => m_waitrequest,
m_write => m_write,
mac_rx_off => m_mac_rx_off,
mac_tx_off => m_mac_tx_off,
rst => rst,
rx_rd_clk => rx_rd_clk,
rx_rd_empty => rx_rd_empty,
rx_rd_full => rx_rd_full,
rx_rd_req => rx_rd_req,
rx_rd_usedw => rx_rd_usedw( rx_fifo_word_size_log2_c-1 downto 0 ),
tx_aclr => tx_aclr,
tx_wr_clk => tx_wr_clk,
tx_wr_empty => tx_wr_empty,
tx_wr_full => tx_wr_full,
tx_wr_req => tx_wr_req,
tx_wr_usedw => tx_wr_usedw( tx_fifo_word_size_log2_c-1 downto 0 )
);
rx_rd_clk <= m_clk;
tx_rd_clk <= dma_clk;
rx_wr_clk <= dma_clk;
tx_wr_clk <= m_clk;
sync1 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_tx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_tx_off
);
sync2 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => mac_rx_off,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_mac_rx_off
);
---- Generate statements ----
gen16bitFifo : if fifo_data_width_g = 16 generate
begin
txFifoGen : if gen_tx_fifo_g generate
begin
TX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_empty_proc :
process(tx_aclr, tx_rd_clk)
begin
if tx_aclr = '1' then
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end process;
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
end generate txFifoGen;
rxFifoGen : if gen_rx_fifo_g generate
begin
RX_FIFO_16 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
end generate rxFifoGen;
wr_data <= dma_dout;
dma_din <= rd_data;
end generate gen16bitFifo;
genRxAddrSync : if gen_rx_fifo_g generate
begin
sync4 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map (
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_wr,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_wr
);
end generate genRxAddrSync;
genTxAddrSync : if gen_tx_fifo_g generate
begin
sync5 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_addr_rd,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_addr_rd
);
sync6 : entity work.syncTog
generic map (
gStages => 2,
gInit => cInactivated
)
port map(
iSrc_rst => rst,
iSrc_clk => dma_clk,
iSrc_data => dma_new_rd_len,
iDst_rst => rst,
iDst_clk => m_clk,
oDst_data => m_dma_new_rd_len
);
end generate genTxAddrSync;
gen32bitFifo : if fifo_data_width_g = 32 generate
begin
txFifoGen32 : if gen_tx_fifo_g generate
begin
TX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => tx_fifo_word_size_c,
gSyncStages => 2,
gMemRes => "ON"
)
port map(
iAclr => tx_aclr,
iWrClk => tx_wr_clk,
iWrReq => tx_wr_req,
iWrData => m_readdata,
oWrEmpty => tx_wr_empty,
oWrFull => tx_wr_full,
oWrUsedw => tx_wr_usedw,
iRdClk => tx_rd_clk,
iRdReq => tx_rd_req_s,
oRdData => rd_data,
oRdEmpty => tx_rd_empty_s,
oRdFull => tx_rd_full,
oRdUsedw => tx_rd_usedw
);
tx_rd_proc :
process (tx_rd_clk, rst)
begin
if rst = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif rising_edge(tx_rd_clk) then
if mac_tx_off = '1' then
tx_rd_sel_word <= '0';
tx_rd_empty_s_l <= '0';
elsif tx_rd_req = '1' then
if tx_rd_sel_word = '0' then
tx_rd_sel_word <= '1';
else
tx_rd_sel_word <= '0';
--workaround...
if tx_rd_empty_s = '0' then
tx_rd_empty_s_l <= '1';
else
tx_rd_empty_s_l <= '0';
end if;
end if;
end if;
end if;
end process;
tx_rd_req_s <= tx_rd_req when tx_rd_sel_word = '0' else '0';
tx_rd_empty <= tx_rd_empty_s when tx_rd_empty_s_l = '0' else '0';
dma_din <= rd_data(15 downto 0) when tx_rd_sel_word = '1' else
rd_data(31 downto 16);
end generate txFifoGen32;
rxFifoGen32 : if gen_rx_fifo_g generate
begin
RX_FIFO_32 : entity work.asyncFifo
generic map (
gDataWidth => fifo_data_width_g,
gWordSize => rx_fifo_word_size_c,
gSyncStages => rx_fifo_word_size_log2_c,
gMemRes => "ON"
)
port map(
iAclr => rx_aclr,
iWrClk => rx_wr_clk,
iWrReq => rx_wr_req_s,
iWrData => wr_data,
oWrEmpty => rx_wr_empty,
oWrFull => rx_wr_full,
oWrUsedw => rx_wr_usedw,
iRdClk => rx_rd_clk,
iRdReq => rx_rd_req,
oRdData => m_writedata,
oRdEmpty => rx_rd_empty,
oRdFull => rx_rd_full,
oRdUsedw => rx_rd_usedw
);
rx_wr_proc :
process (rx_wr_clk, rst)
variable toggle : std_logic;
begin
if rst = '1' then
wr_data_s <= (others => '0');
toggle := '0';
rx_wr_req_s <= '0';
elsif rising_edge(rx_wr_clk) then
rx_wr_req_s <= '0';
if mac_rx_off = '1' then
if toggle = '1' then
rx_wr_req_s <= '1';
end if;
toggle := '0';
elsif rx_wr_req = '1' then
if toggle = '0' then
--capture data
wr_data_s <= dma_dout;
toggle := '1';
else
rx_wr_req_s <= '1';
toggle := '0';
end if;
end if;
end if;
end process;
wr_data <= dma_dout & wr_data_s;
end generate rxFifoGen32;
end generate gen32bitFifo;
end strct;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity key_schedule is
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
round_counter: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)-1 downto 0)
);
end key_schedule;
architecture structural of key_schedule is
signal shifted: std_logic_vector(key_bits(k)-1 downto 0);
component sbox
port(data_in: in std_logic_vector(3 downto 0);
data_out: out std_logic_vector(3 downto 0)
);
end component;
begin
SCHEDULE_80: if k = K_80 generate
shifted <= data_in(18 downto 0) & data_in(79 downto 19);
SB: sbox port map(
data_in => shifted(79 downto 76),
data_out => data_out(79 downto 76)
);
data_out(75 downto 20) <= shifted(75 downto 20);
data_out(19 downto 15) <= shifted(19 downto 15) xor round_counter;
data_out(14 downto 0) <= shifted(14 downto 0);
end generate;
SCHEDULE_128: if k = K_128 generate
shifted <= data_in(66 downto 0) & data_in(127 downto 67);
SB1: sbox port map(
data_in => shifted(127 downto 124),
data_out => data_out(127 downto 124)
);
SB2: sbox port map(
data_in => shifted(123 downto 120),
data_out => data_out(123 downto 120)
);
data_out(119 downto 67) <= shifted(119 downto 67);
data_out(66 downto 62) <= shifted(66 downto 62) xor round_counter;
data_out(61 downto 0) <= shifted(61 downto 0);
end generate;
end structural;
|
library verilog;
use verilog.vl_types.all;
entity mist1032sa_arbiter_matching_queue is
generic(
D : integer := 8;
DN : integer := 3;
FN : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic;
iFLASH : in vl_logic;
iWR_REQ : in vl_logic;
iWR_FLAG : in vl_logic_vector;
oWR_FULL : out vl_logic;
iRD_REQ : in vl_logic;
oRD_VALID : out vl_logic;
oRD_FLAG : out vl_logic_vector;
oRD_EMPTY : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of D : constant is 1;
attribute mti_svvh_generic_type of DN : constant is 1;
attribute mti_svvh_generic_type of FN : constant is 1;
end mist1032sa_arbiter_matching_queue;
|
-- File: inc.vhd
-- Generated by MyHDL 1.0dev
-- Date: Sun May 22 18:46:37 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity inc is
port (
count: inout unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity inc;
-- Incrementer with enable.
--
-- count -- output
-- enable -- control input, increment when 1
-- clock -- clock input
-- reset -- asynchronous reset input
architecture MyHDL of inc is
begin
INC_SEQ: process (clock, reset) is
begin
if (reset = '0') then
count <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
count <= (count + 1);
end if;
end if;
end process INC_SEQ;
end architecture MyHDL;
|
-- File: inc.vhd
-- Generated by MyHDL 1.0dev
-- Date: Sun May 22 18:46:37 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity inc is
port (
count: inout unsigned(7 downto 0);
enable: in std_logic;
clock: in std_logic;
reset: in std_logic
);
end entity inc;
-- Incrementer with enable.
--
-- count -- output
-- enable -- control input, increment when 1
-- clock -- clock input
-- reset -- asynchronous reset input
architecture MyHDL of inc is
begin
INC_SEQ: process (clock, reset) is
begin
if (reset = '0') then
count <= to_unsigned(0, 8);
elsif rising_edge(clock) then
if bool(enable) then
count <= (count + 1);
end if;
end if;
end process INC_SEQ;
end architecture MyHDL;
|
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