content stringlengths 1 1.04M ⌀ |
|---|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is'... |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is'... |
---------------------------------------------------------------------
-- TITLE: Plasma (CPU core with memory)
-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
-- DATE CREATED: 6/4/02
-- FILENAME: plasma.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is'... |
-- NEED RESULT: ARCH00399.P1: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00399.P2: Multi inertial transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00399: One inertial transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH0039... |
architecture RTL of FIFO is
type state_machine is (idle, write, read, done);
-- Violations below
type state_machine is (idle, write, read, done);
begin
end architecture RTL;
|
--MIT License
--
--Copyright (c) 2017 Danny Savory
--
--Permission is hereby granted, free of charge, to any person obtaining a copy
--of this software and associated documentation files (the "Software"), to deal
--in the Software without restriction, including without limitation the rights
--to use, copy, modi... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (c) 2016 Federico Madotto and Coline Doebelin
-- federico.madotto (at) gmail.com
-- coline.doebelin (at) gmail.com
-- https://github.com/fmadotto/DS_bitcoin_miner
-- H_i_calculator.vhd is part of DS_bitcoin_miner.
-- DS_bitcoin_miner is free software: you can redistribute it and/or modify
-- it under the... |
--###############################
--# Project Name :
--# File :
--# Author :
--# Description :
--# Modification History
--#
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity tb_COMPARE is
end tb_COMPARE;
architecture stimulus of tb_COMPAR... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
LIBRARY ieee;
LIBRARY work;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_signed.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOAT CONVERT - CORE LEVEL ***
--*** ... |
entity tb_slice01 is
end tb_slice01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice01 is
signal rst : std_logic;
signal clk : std_logic;
signal di : std_logic;
signal do : std_logic_vector (3 downto 0);
begin
dut: entity work.slice01
generic map (w => 4)
port map (rst, clk... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
... |
----------------------------------------------------------------------------------
-- Engineer: Mike Field <hamster@snap.net.nz>
--
-- Module Name: fifo_32 - Behavioral
--
-- Description: A 32-entry singla-clock FIFO of unknown data width.
--
-------------------------------------------------------------------------... |
package foo is new bar;
|
library std;
use std.textio.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tb_ghdl_test is
end entity tb_ghdl_test;
architecture tb of tb_ghdl_test is
begin
p_test : process is
file f_in : text;
variable v_line : line;
begin
file_open(f_in, "ghdl_test.txt", read_... |
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:22:05 11/15/2013
-- Design Name:
-- Module Name: C:/Users/Silvia/Desktop/RS232 project/RS232/tb_RS232_RX.vhd
-- Project Name: RS232
-- Target Device:
-- Tool versions:
-- Descript... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2013, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-----... |
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7_2 Core - Top File for the Example Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains c... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your o... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
--------------------------------------------------------------------------------
-- File Name: m25p80.vhd
--------------------------------------------------------------------------------
-- Copyright (C) 2005 Free Model Foundry; http://www.FreeModelFoundry.com
--
-- This program is free software; you can redistribut... |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
----------... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
archit... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
archit... |
library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end entity;
archit... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.myTypes.all;
entity execute_block is
generic (
SIZE : integer := 32
);
port (
IMM_i : in std_logic_vector(SIZE - 1 downto 0);
A_i : in std_logic_vector(SIZE - 1 downto 0);
rB_i : in std_logic_vector(4 downto 0);
rC_i : in st... |
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1,... |
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1,... |
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1,... |
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1,... |
entity sub is
port (
x, y : in integer;
z : out integer );
end entity;
architecture test of sub is
begin
z <= x + y;
end architecture;
-------------------------------------------------------------------------------
entity elab4 is
end entity;
architecture test of elab4 is
signal x1,... |
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end ar... |
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end ar... |
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end ar... |
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end ar... |
entity issue169 is
end entity;
architecture a of issue169 is
begin
main : process
procedure proc(x : natural) is
begin
if x > 0 then
wait for 1 ns;
proc(x - 1);
end if;
end procedure;
begin
proc(5);
assert now = 5 ns;
wait;
end process;
end ar... |
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant ... |
-- $Id: nexys2lib.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: nexys2lib
-- Description: Nexys 2 components... |
library ieee;
library std;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity core_c is
port(
clk_i : in std_logic;
rst_i : in std_logic;
en_i : in std_logic;
wr_i : in std_logic;
bidir_io : inout std_logic_vector( 7 downto 0 )
);
end entity;
architecture IMP of... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
... |
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
... |
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
... |
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
... |
entity issue90 is
end entity;
architecture test of issue90 is
procedure proc(x : inout integer) is
procedure nested_p1(x : inout integer) is
begin
x := x + 1;
end;
procedure nested_p2(x : inout integer) is
begin
nested_p1(x);
x := x + 1;
end;
begin
nested_p2(x);
... |
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : ... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.usb1_pkg.all;
entity usb1_ulpi_rx is
generic (
g_allow_token : boolean := true );
port (
clock : in std_logic;
reset : in std_logic;
rx_data : ... |
-- -------------------------------------------------------------
--
-- Entity Declaration for ent_ae
--
-- Generated
-- by: wig
-- on: Fri Jul 15 16:37:11 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../sigport.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id:... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: Serial multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: Serial multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11... |
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: Serial multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 11... |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 04/13/2015
--! Module Name: EPROC_IN2_direct
--! Project Name: FELIX
----------------------------------------------------------------------------------
-... |
-- NEED RESULT: ARCH00151.P1: Multi inertial transactions occurred on signal asg with selected name on LHS passed
-- NEED RESULT: ARCH00151.P2: Multi inertial transactions occurred on signal asg with selected name on LHS failed
-- NEED RESULT: ARCH00151.P3: Multi inertial transactions occurred on signal asg with sele... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-... |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- ____ _ ____ _ _ _ _ ... |
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and ... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
-- Copyright (c) 2015 CERN
-- Maciej Suminski <maciej.suminski@cern.ch>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at y... |
library verilog;
use verilog.vl_types.all;
entity alt_cal_sv is
generic(
number_of_channels: integer := 1;
channel_address_width: integer := 1;
sim_model_mode : string := "TRUE";
lpm_type : string := "alt_cal_sv";
lpm_hint : string := "UNUSED";
sampl... |
-- EMACS settings: -*- tab-width:2 -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-------------------------------------------------------------------------------
-- Description: LCD Test Application designed for the
-- Spartan-3 Evaluation Kit.... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify i... |
---------------------------------------------------------------------------------------------------------
-- MMU in
-- This block handles input values for the DRAM, to perform read/write operation.
-- It is in charge for translating virtual aligned address in physical uniligned addresses and feed
-- the DRAM with t... |
package pack is
function "=" (L: bit; R: bit) return bit;
end package;
use work.pack.all;
entity issue568 is
generic (x : boolean);
end entity;
architecture test of issue568 is
signal y : bit;
begin
p1: assert (y = '1') or (not x);
end architecture;
|
-------------------------------------------------------------------------------
-- Entity : openMAC_DMAmaster
-------------------------------------------------------------------------------
--
-- (c) B&R, 2012
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitt... |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.util.all;
entity key_schedule is
generic(k: key_enum);
port(data_in: in std_logic_vector(key_bits(k)-1 downto 0);
round_counter: in std_logic_vector(4 downto 0);
data_out: out std_logic_vector(key_bits(k)... |
library verilog;
use verilog.vl_types.all;
entity mist1032sa_arbiter_matching_queue is
generic(
D : integer := 8;
DN : integer := 3;
FN : integer := 1
);
port(
iCLOCK : in vl_logic;
inRESET : in vl_logic... |
-- File: inc.vhd
-- Generated by MyHDL 1.0dev
-- Date: Sun May 22 18:46:37 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity inc is
port (
count: inout unsigned(7 downto 0);
enable: in std_logic;
clock: in std_... |
-- File: inc.vhd
-- Generated by MyHDL 1.0dev
-- Date: Sun May 22 18:46:37 2016
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;
use work.pck_myhdl_10.all;
entity inc is
port (
count: inout unsigned(7 downto 0);
enable: in std_logic;
clock: in std_... |
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