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-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity get_gmem_m_axi;
architecture behave of get_gmem_m_axi is
component get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_write;
component get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_read;
component get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component get_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : get_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : get_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity get_gmem_m_axi_fifo;
architecture behave of get_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity get_gmem_m_axi_decoder;
architecture behav of get_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity get_gmem_m_axi_throttl;
architecture behav of get_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_read;
architecture behave of get_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_write;
architecture behave of get_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component get_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : get_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity get_gmem_m_axi;
architecture behave of get_gmem_m_axi is
component get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_write;
component get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_read;
component get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component get_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : get_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : get_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity get_gmem_m_axi_fifo;
architecture behave of get_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity get_gmem_m_axi_decoder;
architecture behav of get_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity get_gmem_m_axi_throttl;
architecture behav of get_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_read;
architecture behave of get_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_write;
architecture behave of get_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component get_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : get_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 2#000#;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
-- system signal
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
-- write address channel
AWID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out STD_LOGIC_VECTOR(7 downto 0);
AWSIZE : out STD_LOGIC_VECTOR(2 downto 0);
AWBURST : out STD_LOGIC_VECTOR(1 downto 0);
AWLOCK : out STD_LOGIC_VECTOR(1 downto 0);
AWCACHE : out STD_LOGIC_VECTOR(3 downto 0);
AWPROT : out STD_LOGIC_VECTOR(2 downto 0);
AWQOS : out STD_LOGIC_VECTOR(3 downto 0);
AWREGION : out STD_LOGIC_VECTOR(3 downto 0);
AWUSER : out STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
-- write data channel
WID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
-- write response channel
BID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in STD_LOGIC_VECTOR(1 downto 0);
BUSER : in STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
-- read address channel
ARID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out STD_LOGIC_VECTOR(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out STD_LOGIC_VECTOR(7 downto 0);
ARSIZE : out STD_LOGIC_VECTOR(2 downto 0);
ARBURST : out STD_LOGIC_VECTOR(1 downto 0);
ARLOCK : out STD_LOGIC_VECTOR(1 downto 0);
ARCACHE : out STD_LOGIC_VECTOR(3 downto 0);
ARPROT : out STD_LOGIC_VECTOR(2 downto 0);
ARQOS : out STD_LOGIC_VECTOR(3 downto 0);
ARREGION : out STD_LOGIC_VECTOR(3 downto 0);
ARUSER : out STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
-- read data channel
RID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in STD_LOGIC_VECTOR(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in STD_LOGIC_VECTOR(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
-- internal bus ports
-- write address channel
I_AWID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_AWADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_AWLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_AWSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_AWBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_AWLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_AWCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_AWPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_AWQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_AWREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_AWUSER : in STD_LOGIC_VECTOR(C_M_AXI_AWUSER_WIDTH-1 downto 0);
I_AWVALID : in STD_LOGIC;
I_AWREADY : out STD_LOGIC;
-- write data channel
I_WID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_WDATA : in STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_WSTRB : in STD_LOGIC_VECTOR(USER_DW/8-1 downto 0);
I_WLAST : in STD_LOGIC;
I_WUSER : in STD_LOGIC_VECTOR(C_M_AXI_WUSER_WIDTH-1 downto 0);
I_WVALID : in STD_LOGIC;
I_WREADY : out STD_LOGIC;
-- write response channel
I_BID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_BRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_BUSER : out STD_LOGIC_VECTOR(C_M_AXI_BUSER_WIDTH-1 downto 0);
I_BVALID : out STD_LOGIC;
I_BREADY : in STD_LOGIC;
-- read address channel
I_ARID : in STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_ARADDR : in STD_LOGIC_VECTOR(USER_AW-1 downto 0);
I_ARLEN : in STD_LOGIC_VECTOR(31 downto 0);
I_ARSIZE : in STD_LOGIC_VECTOR(2 downto 0);
I_ARBURST : in STD_LOGIC_VECTOR(1 downto 0);
I_ARLOCK : in STD_LOGIC_VECTOR(1 downto 0);
I_ARCACHE : in STD_LOGIC_VECTOR(3 downto 0);
I_ARPROT : in STD_LOGIC_VECTOR(2 downto 0);
I_ARQOS : in STD_LOGIC_VECTOR(3 downto 0);
I_ARREGION : in STD_LOGIC_VECTOR(3 downto 0);
I_ARUSER : in STD_LOGIC_VECTOR(C_M_AXI_ARUSER_WIDTH-1 downto 0);
I_ARVALID : in STD_LOGIC;
I_ARREADY : out STD_LOGIC;
-- read data channel
I_RID : out STD_LOGIC_VECTOR(C_M_AXI_ID_WIDTH-1 downto 0);
I_RDATA : out STD_LOGIC_VECTOR(USER_DW-1 downto 0);
I_RRESP : out STD_LOGIC_VECTOR(1 downto 0);
I_RLAST : out STD_LOGIC;
I_RUSER : out STD_LOGIC_VECTOR(C_M_AXI_RUSER_WIDTH-1 downto 0);
I_RVALID : out STD_LOGIC;
I_RREADY : in STD_LOGIC);
end entity get_gmem_m_axi;
architecture behave of get_gmem_m_axi is
component get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_write;
component get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
end component get_gmem_m_axi_read;
component get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := true;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end component get_gmem_m_axi_throttl;
signal AWLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal AWVALID_Dummy : STD_LOGIC;
signal AWREADY_Dummy : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal ARLEN_Dummy : STD_LOGIC_VECTOR(7 downto 0);
signal ARVALID_Dummy : STD_LOGIC;
signal ARREADY_Dummy : STD_LOGIC;
signal RREADY_Dummy : STD_LOGIC;
begin
AWLEN <= AWLEN_Dummy;
WVALID <= WVALID_Dummy;
wreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => false )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => AWLEN_Dummy,
in_req_valid => AWVALID_Dummy,
out_req_valid => AWVALID,
in_req_ready => AWREADY,
out_req_ready => AWREADY_Dummy,
in_data_valid => WVALID_Dummy,
in_data_ready => WREADY);
ARLEN <= ARLEN_Dummy;
RREADY <= RREADY_Dummy;
rreq_throttl : get_gmem_m_axi_throttl
generic map (
USED_FIX => true,
FIX_VALUE => 4 )
port map (
clk => ACLK,
reset => ARESET,
ce => ACLK_EN,
in_len => ARLEN_Dummy,
in_req_valid => ARVALID_Dummy,
out_req_valid => ARVALID,
in_req_ready => ARREADY,
out_req_ready => ARREADY_Dummy,
in_data_valid => RVALID,
in_data_ready => RREADY_Dummy);
I_BID <= (others => '0');
I_BUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_BUSER'length));
I_RID <= (others => '0');
I_RLAST <= '0';
I_RUSER <= STD_LOGIC_VECTOR(TO_UNSIGNED(C_USER_VALUE, I_RUSER'length));
-- Instantiation
bus_write : get_gmem_m_axi_write
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_AWUSER_WIDTH => C_M_AXI_AWUSER_WIDTH,
C_M_AXI_WUSER_WIDTH => C_M_AXI_WUSER_WIDTH,
C_M_AXI_BUSER_WIDTH => C_M_AXI_BUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(AWID) => AWID,
STD_LOGIC_VECTOR(AWADDR) => AWADDR,
STD_LOGIC_VECTOR(AWLEN) => AWLEN_Dummy,
STD_LOGIC_VECTOR(AWSIZE) => AWSIZE,
STD_LOGIC_VECTOR(AWBURST) => AWBURST,
STD_LOGIC_VECTOR(AWLOCK) => AWLOCK,
STD_LOGIC_VECTOR(AWCACHE) => AWCACHE,
STD_LOGIC_VECTOR(AWPROT) => AWPROT,
STD_LOGIC_VECTOR(AWQOS) => AWQOS,
STD_LOGIC_VECTOR(AWREGION) => AWREGION,
STD_LOGIC_VECTOR(AWUSER) => AWUSER,
AWVALID => AWVALID_Dummy,
AWREADY => AWREADY_Dummy,
STD_LOGIC_VECTOR(WID) => WID,
STD_LOGIC_VECTOR(WDATA) => WDATA,
STD_LOGIC_VECTOR(WSTRB) => WSTRB,
WLAST => WLAST,
STD_LOGIC_VECTOR(WUSER) => WUSER,
WVALID => WVALID_Dummy,
WREADY => WREADY,
BID => UNSIGNED(BID),
BRESP => UNSIGNED(BRESP),
BUSER => UNSIGNED(BUSER),
BVALID => BVALID,
BREADY => BREADY,
wreq_valid => I_AWVALID,
wreq_ack => I_AWREADY,
wreq_addr => UNSIGNED(I_AWADDR),
wreq_length => UNSIGNED(I_AWLEN),
wreq_cache => UNSIGNED(I_AWCACHE),
wreq_prot => UNSIGNED(I_AWPROT),
wreq_qos => UNSIGNED(I_AWQOS),
wreq_user => UNSIGNED(I_AWUSER),
wdata_valid => I_WVALID,
wdata_ack => I_WREADY,
wdata_strb => UNSIGNED(I_WSTRB),
wdata_user => UNSIGNED(I_WUSER),
wdata_data => UNSIGNED(I_WDATA),
wrsp_valid => I_BVALID,
wrsp_ack => I_BREADY,
STD_LOGIC_VECTOR(wrsp) => I_BRESP);
bus_read : get_gmem_m_axi_read
generic map (
C_M_AXI_ID_WIDTH => C_M_AXI_ID_WIDTH,
C_M_AXI_ADDR_WIDTH => C_M_AXI_ADDR_WIDTH,
C_TARGET_ADDR => C_TARGET_ADDR,
C_M_AXI_DATA_WIDTH => C_M_AXI_DATA_WIDTH,
C_M_AXI_ARUSER_WIDTH => C_M_AXI_ARUSER_WIDTH,
C_M_AXI_RUSER_WIDTH => C_M_AXI_RUSER_WIDTH,
C_USER_VALUE => C_USER_VALUE,
C_PROT_VALUE => C_PROT_VALUE,
C_CACHE_VALUE => C_CACHE_VALUE,
USER_DW => USER_DW,
USER_AW => USER_AW,
USER_MAXREQS => USER_MAXREQS)
port map (
ACLK => ACLK,
ARESET => ARESET,
ACLK_EN => ACLK_EN,
STD_LOGIC_VECTOR(ARID) => ARID,
STD_LOGIC_VECTOR(ARADDR) => ARADDR,
STD_LOGIC_VECTOR(ARLEN) => ARLEN_Dummy,
STD_LOGIC_VECTOR(ARSIZE) => ARSIZE,
STD_LOGIC_VECTOR(ARBURST) => ARBURST,
STD_LOGIC_VECTOR(ARLOCK) => ARLOCK,
STD_LOGIC_VECTOR(ARCACHE) => ARCACHE,
STD_LOGIC_VECTOR(ARPROT) => ARPROT,
STD_LOGIC_VECTOR(ARQOS) => ARQOS,
STD_LOGIC_VECTOR(ARREGION) => ARREGION,
STD_LOGIC_VECTOR(ARUSER) => ARUSER,
ARVALID => ARVALID_Dummy,
ARREADY => ARREADY_Dummy,
RID => UNSIGNED(RID),
RDATA => UNSIGNED(RDATA),
RRESP => UNSIGNED(RRESP),
RLAST => RLAST,
RUSER => UNSIGNED(RUSER),
RVALID => RVALID,
RREADY => RREADY_Dummy,
rreq_valid => I_ARVALID,
rreq_ack => I_ARREADY,
rreq_addr => UNSIGNED(I_ARADDR),
rreq_length => UNSIGNED(I_ARLEN),
rreq_cache => UNSIGNED(I_ARCACHE),
rreq_prot => UNSIGNED(I_ARPROT),
rreq_qos => UNSIGNED(I_ARQOS),
rreq_user => UNSIGNED(I_ARUSER),
rdata_valid => I_RVALID,
rdata_ack => I_RREADY,
STD_LOGIC_VECTOR(rdata_data)=> I_RDATA,
STD_LOGIC_VECTOR(rrsp) => I_RRESP);
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end entity get_gmem_m_axi_fifo;
architecture behave of get_gmem_m_axi_fifo is
signal push, pop, data_vld : STD_LOGIC;
signal empty_n_tmp, full_n_tmp : STD_LOGIC;
signal pout : INTEGER range 0 to DEPTH -1;
subtype word is UNSIGNED(DATA_BITS-1 downto 0);
type regFileType is array(0 to DEPTH-1) of word;
signal mem : regFileType;
begin
full_n <= full_n_tmp;
empty_n <= empty_n_tmp;
push <= full_n_tmp and wrreq;
pop <= data_vld and (not (empty_n_tmp and (not rdreq)));
q_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
q <= (others => '0');
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
q <= mem(pout);
end if;
end if;
end if;
end process q_proc;
empty_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
empty_n_tmp <= '0';
elsif sclk_en = '1' then
if not (empty_n_tmp = '1' and rdreq = '0') then
empty_n_tmp <= data_vld;
end if;
end if;
end if;
end process empty_n_proc;
data_vld_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
data_vld <= '0';
elsif sclk_en = '1' then
if push = '1' then
data_vld <= '1';
elsif push = '0' and pop = '1' and pout = 0 then
data_vld <= '0';
end if;
end if;
end if;
end process data_vld_proc;
full_n_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
full_n_tmp <= '1';
elsif sclk_en = '1' then
if rdreq = '1' then
full_n_tmp <= '1';
elsif push = '1' and pop = '0' and pout = DEPTH - 2 and data_vld = '1' then
full_n_tmp <= '0';
end if;
end if;
end if;
end process full_n_proc;
pout_proc : process (sclk)
begin
if (sclk'event and sclk = '1') then
if reset = '1' then
pout <= 0;
elsif sclk_en = '1' then
if push = '1' and pop = '0' and data_vld = '1' then
pout <= TO_INTEGER(TO_UNSIGNED(pout + 1, DEPTH_BITS));
elsif push = '0' and pop = '1' and pout /= 0 then
pout <= pout - 1;
end if;
end if;
end if;
end process pout_proc;
process (sclk)
begin
if (sclk'event and sclk = '1') and sclk_en = '1' then
if push = '1' then
for i in 0 to DEPTH - 2 loop
mem(i+1) <= mem(i);
end loop;
mem(0) <= data;
end if;
end if;
end process;
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end entity get_gmem_m_axi_decoder;
architecture behav of get_gmem_m_axi_decoder is
begin
process (din)
begin
dout <= (others => '0');
dout(TO_INTEGER(din) - 1 downto 0) <= (others => '1');
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_throttl is
generic (
USED_FIX : BOOLEAN := false;
FIX_VALUE : INTEGER := 4);
port (
clk : in STD_LOGIC;
reset : in STD_LOGIC;
ce : in STD_LOGIC;
in_len : in STD_LOGIC_VECTOR;
in_req_valid : in STD_LOGIC;
in_req_ready : in STD_LOGIC;
in_data_valid : in STD_LOGIC;
in_data_ready : in STD_LOGIC;
out_req_valid : out STD_LOGIC;
out_req_ready : out STD_LOGIC);
end entity get_gmem_m_axi_throttl;
architecture behav of get_gmem_m_axi_throttl is
type switch_t is array(boolean) of integer;
constant switch : switch_t := (true => FIX_VALUE-1, false => 0);
constant threshold : INTEGER := switch(USED_FIX);
signal req_en : STD_LOGIC;
signal handshake : STD_LOGIC;
signal load_init : UNSIGNED(7 downto 0);
signal throttl_cnt : UNSIGNED(7 downto 0);
begin
fix_gen : if USED_FIX generate
load_init <= TO_UNSIGNED(FIX_VALUE-1, 8);
handshake <= '1';
end generate;
no_fix_gen : if not USED_FIX generate
load_init <= UNSIGNED(in_len);
handshake <= in_data_valid and in_data_ready;
end generate;
out_req_valid <= in_req_valid and req_en;
out_req_ready <= in_req_ready and req_en;
req_en <= '1' when throttl_cnt = 0 else
'0';
process (clk)
begin
if (clk'event and clk = '1') then
if reset = '1' then
throttl_cnt <= (others => '0');
elsif ce = '1' then
if UNSIGNED(in_len) > threshold and throttl_cnt = 0 and in_req_valid = '1' and in_req_ready = '1' then
throttl_cnt <= load_init; --load
elsif throttl_cnt > 0 and handshake = '1' then
throttl_cnt <= throttl_cnt - 1;
end if;
end if;
end if;
end process;
end architecture behav;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_read is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_ARUSER_WIDTH : INTEGER := 1;
C_M_AXI_RUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
ARID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
ARADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
ARLEN : out UNSIGNED(7 downto 0);
ARSIZE : out UNSIGNED(2 downto 0);
ARBURST : out UNSIGNED(1 downto 0);
ARLOCK : out UNSIGNED(1 downto 0);
ARCACHE : out UNSIGNED(3 downto 0);
ARPROT : out UNSIGNED(2 downto 0);
ARQOS : out UNSIGNED(3 downto 0);
ARREGION : out UNSIGNED(3 downto 0);
ARUSER : out UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
ARVALID : out STD_LOGIC;
ARREADY : in STD_LOGIC;
RID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
RDATA : in UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
RRESP : in UNSIGNED(1 downto 0);
RLAST : in STD_LOGIC;
RUSER : in UNSIGNED(C_M_AXI_RUSER_WIDTH-1 downto 0);
RVALID : in STD_LOGIC;
RREADY : out STD_LOGIC;
rreq_valid : in STD_LOGIC;
rreq_ack : out STD_LOGIC;
rreq_addr : in UNSIGNED(USER_AW-1 downto 0);
rreq_length : in UNSIGNED(31 downto 0);
rreq_cache : in UNSIGNED(3 downto 0);
rreq_prot : in UNSIGNED(2 downto 0);
rreq_qos : in UNSIGNED(3 downto 0);
rreq_user : in UNSIGNED(C_M_AXI_ARUSER_WIDTH-1 downto 0);
rdata_valid : out STD_LOGIC;
rdata_ack : in STD_LOGIC;
rdata_data : out UNSIGNED(USER_DW-1 downto 0);
rrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_read;
architecture behave of get_gmem_m_axi_read is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AR channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_rreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal arlen_tmp : UNSIGNED(7 downto 0);
signal araddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal fifo_rreq_valid : STD_LOGIC;
signal fifo_rreq_valid_buf : STD_LOGIC;
signal fifo_rreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal ARVALID_Dummy : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal next_rreq : BOOLEAN;
signal ready_for_rreq : BOOLEAN;
signal rreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--R channel
signal fifo_rresp_rdata : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal data_pack : UNSIGNED(BUS_DATA_WIDTH + 1 downto 0);
signal tmp_data : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal tmp_resp : UNSIGNED(1 downto 0);
signal resp_buf : UNSIGNED(1 downto 0);
signal beat_valid : STD_LOGIC;
signal next_beat : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal rdata_valid_t : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AR channel begin -----------------------------------
-- Instantiation
fifo_rreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_rreq_valid,
full_n => rreq_ack,
rdreq => fifo_rreq_read,
wrreq => rreq_valid,
q => fifo_rreq_data,
data => rreq_data);
rreq_data <= (rreq_length & rreq_addr);
tmp_addr <= fifo_rreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_rreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_rreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_rreq_valid = '1' else '0';
next_rreq <= invalid_len_event = '0' and (fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq;
ready_for_rreq <= not(rreq_handling and not(last_sect and next_sect));
fifo_rreq_read <= '1' when invalid_len_event = '1' or next_rreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_rreq_valid = '1' and ready_for_rreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_rreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_rreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
fifo_rreq_valid_buf <= fifo_rreq_valid;
end if;
end if;
end if;
end process fifo_rreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if ((fifo_rreq_valid = '1' or fifo_rreq_valid_buf = '1') and ready_for_rreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
rreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_rreq_valid_buf = '1' and not rreq_handling and invalid_len_event = '0' then
rreq_handling <= true;
elsif (fifo_rreq_valid_buf = '0' or invalid_len_event = '1') and last_sect and next_sect then
rreq_handling <= false;
end if;
end if;
end if;
end process rreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_rreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= rreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
ARID <= (others => '0');
ARSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, ARSIZE'length);
ARBURST <= "01";
ARLOCK <= "00";
ARCACHE <= TO_UNSIGNED(C_CACHE_VALUE, ARCACHE'length);
ARPROT <= TO_UNSIGNED(C_PROT_VALUE, ARPROT'length);
ARUSER <= TO_UNSIGNED(C_USER_VALUE, ARUSER'length);
ARQOS <= rreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
ARADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
ARLEN <= RESIZE(sect_len_buf, 8);
ARVALID <= ARVALID_Dummy;
ready_for_sect <= '1' when not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1' else '0';
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_sect then
ARVALID_Dummy <= '1';
elsif not next_sect and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_sect else '0';
araddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
arlen_tmp <= RESIZE(sect_len, 8);
burst_end <= sect_end;
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal araddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal arlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
ARADDR <= araddr_buf;
ARLEN <= arlen_buf;
ARVALID <= ARVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_loop <= not (ARVALID_Dummy = '1' and ARREADY = '0') and fifo_burst_ready = '1';
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if rreq_handling and not sect_handling then
sect_handling <= true;
elsif not rreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
araddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
araddr_buf + SHIFT_LEFT(RESIZE(arlen_buf, 32) + 1, BUS_ADDR_ALIGN);
araddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
araddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
araddr_buf <= araddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process araddr_buf_proc;
arlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
arlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
arlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
arlen_buf <= arlen_tmp;
end if;
end if;
end if;
end process arlen_buf_proc;
arvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
ARVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_loop then
ARVALID_Dummy <= '1';
elsif not next_loop and ARREADY = '1' then
ARVALID_Dummy <= '0';
end if;
end if;
end if;
end process arvalid_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AR channel end -------------------------------------
--------------------------- R channel begin ------------------------------------
-- Instantiation
fifo_rdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => BUS_DATA_WIDTH + 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => beat_valid,
full_n => RREADY,
rdreq => next_beat,
wrreq => RVALID,
q => data_pack,
data => fifo_rresp_rdata);
fifo_rresp_rdata <= (RRESP & RDATA);
tmp_data <= data_pack(BUS_DATA_WIDTH - 1 downto 0);
tmp_resp <= data_pack(BUS_DATA_WIDTH + 1 downto BUS_DATA_WIDTH);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal ready_for_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when beat_valid = '1' and ready_for_data else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_beat = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if next_beat = '1' then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_beat = '1' then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_equal_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal tmp_burst_info : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal burst_pack : UNSIGNED(2*SPLIT_ALIGN + 7 downto 0);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal split_cnt_buf : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal head_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tail_split : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2*SPLIT_ALIGN + 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
tmp_burst_info <= araddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(arlen_tmp, 8);
head_split <= burst_pack(2*SPLIT_ALIGN + 7 downto 8 + SPLIT_ALIGN);
tail_split <= burst_pack(SPLIT_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
fifo_burst_ready <= '1';
next_beat <= '1' when last_split else '0';
next_burst <= '1' when last_beat and last_split else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
first_beat <= len_cnt = 0 and burst_valid = '1' and beat_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1' and beat_valid = '1';
first_split <= (split_cnt = 0 and beat_valid = '1' and ready_for_data) when not first_beat else
(split_cnt = head_split and ready_for_data);
last_split <= (split_cnt = (TOTAL_SPLIT - 1) and ready_for_data) when not last_beat else
(split_cnt = tail_split and ready_for_data);
next_split <= (split_cnt /= 0 and ready_for_data) when not first_beat else
(split_cnt /= head_split and ready_for_data);
split_cnt <= head_split when first_beat and (split_cnt_buf = 0) else
split_cnt_buf;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt_buf <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt_buf <= (others => '0');
elsif first_split or next_split then
split_cnt_buf <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_beat and last_split then
len_cnt <= (others => '0');
elsif last_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if first_split and first_beat then
data_buf <= SHIFT_RIGHT(tmp_data, to_integer(head_split)*USER_DATA_WIDTH);
elsif first_split then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, USER_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_buf <= "00";
elsif ACLK_EN = '1' then
if first_split then
resp_buf <= tmp_resp;
end if;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if first_split then
rdata_valid_t <= '1';
elsif not (first_split or next_split) and ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_wide_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal next_data : BOOLEAN;
begin
rrsp <= resp_buf;
rdata_data <= data_buf(USER_DW - 1 downto 0);
rdata_valid <= rdata_valid_t;
fifo_burst_ready <= '1';
next_beat <= '1' when next_pad else '0';
ready_for_data <= not (rdata_valid_t = '1' and rdata_ack = '0');
next_pad <= beat_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - 1) = '1';
next_data <= last_pad and ready_for_data;
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when beat_valid = '0' else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_gen : for i in 1 to TOTAL_PADS generate
begin
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*BUS_DATA_WIDTH - 1 downto (i-1)*BUS_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
end generate data_gen;
resp_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
resp_buf <= "00";
elsif next_beat = '1' and resp_buf(0) = '0' then
resp_buf <= tmp_resp;
end if;
end if;
end process resp_buf_proc;
rdata_valid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rdata_valid_t <= '0';
elsif ACLK_EN = '1' then
if next_data then
rdata_valid_t <= '1';
elsif ready_for_data then
rdata_valid_t <= '0';
end if;
end if;
end if;
end process rdata_valid_proc;
end generate bus_narrow_gen;
--------------------------- R channel end --------------------------------------
end architecture behave;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity get_gmem_m_axi_write is
generic (
C_M_AXI_ID_WIDTH : INTEGER := 1;
C_M_AXI_ADDR_WIDTH : INTEGER := 32;
C_TARGET_ADDR : INTEGER := 16#00000000#;
C_M_AXI_DATA_WIDTH : INTEGER := 32;
C_M_AXI_AWUSER_WIDTH : INTEGER := 1;
C_M_AXI_WUSER_WIDTH : INTEGER := 1;
C_M_AXI_BUSER_WIDTH : INTEGER := 1;
C_USER_VALUE : INTEGER := 0;
C_PROT_VALUE : INTEGER := 0;
C_CACHE_VALUE : INTEGER := 2#0011#;
USER_DW : INTEGER := 16;
USER_AW : INTEGER := 32;
USER_MAXREQS : INTEGER := 16);
port (
ACLK : in STD_LOGIC;
ARESET : in STD_LOGIC;
ACLK_EN : in STD_LOGIC;
AWID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
AWADDR : out UNSIGNED(C_M_AXI_ADDR_WIDTH-1 downto 0);
AWLEN : out UNSIGNED(7 downto 0);
AWSIZE : out UNSIGNED(2 downto 0);
AWBURST : out UNSIGNED(1 downto 0);
AWLOCK : out UNSIGNED(1 downto 0);
AWCACHE : out UNSIGNED(3 downto 0);
AWPROT : out UNSIGNED(2 downto 0);
AWQOS : out UNSIGNED(3 downto 0);
AWREGION : out UNSIGNED(3 downto 0);
AWUSER : out UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
AWVALID : out STD_LOGIC;
AWREADY : in STD_LOGIC;
WID : out UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
WDATA : out UNSIGNED(C_M_AXI_DATA_WIDTH-1 downto 0);
WSTRB : out UNSIGNED(C_M_AXI_DATA_WIDTH/8-1 downto 0);
WLAST : out STD_LOGIC;
WUSER : out UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
WVALID : out STD_LOGIC;
WREADY : in STD_LOGIC;
BID : in UNSIGNED(C_M_AXI_ID_WIDTH-1 downto 0);
BRESP : in UNSIGNED(1 downto 0);
BUSER : in UNSIGNED(C_M_AXI_BUSER_WIDTH-1 downto 0);
BVALID : in STD_LOGIC;
BREADY : out STD_LOGIC;
wreq_valid : in STD_LOGIC;
wreq_ack : out STD_LOGIC;
wreq_addr : in UNSIGNED(USER_AW-1 downto 0);
wreq_length : in UNSIGNED(31 downto 0);
wreq_cache : in UNSIGNED(3 downto 0);
wreq_prot : in UNSIGNED(2 downto 0);
wreq_qos : in UNSIGNED(3 downto 0);
wreq_user : in UNSIGNED(C_M_AXI_AWUSER_WIDTH-1 downto 0);
wdata_valid : in STD_LOGIC;
wdata_ack : out STD_LOGIC;
wdata_strb : in UNSIGNED(USER_DW/8-1 downto 0);
wdata_user : in UNSIGNED(C_M_AXI_WUSER_WIDTH-1 downto 0);
wdata_data : in UNSIGNED(USER_DW-1 downto 0);
wrsp_valid : out STD_LOGIC;
wrsp_ack : in STD_LOGIC;
wrsp : out UNSIGNED(1 downto 0));
function calc_data_width (x : INTEGER) return INTEGER is
variable y : INTEGER;
begin
y := 8;
while y < x loop
y := y * 2;
end loop;
return y;
end function calc_data_width;
function log2 (x : INTEGER) return INTEGER is
variable n, m : INTEGER;
begin
n := 0;
m := 1;
while m < x loop
n := n + 1;
m := m * 2;
end loop;
return n;
end function log2;
end entity get_gmem_m_axi_write;
architecture behave of get_gmem_m_axi_write is
--common
constant USER_DATA_WIDTH : INTEGER := calc_data_width(USER_DW);
constant USER_DATA_BYTES : INTEGER := USER_DATA_WIDTH / 8;
constant USER_ADDR_ALIGN : INTEGER := log2(USER_DATA_BYTES);
constant BUS_DATA_WIDTH : INTEGER := C_M_AXI_DATA_WIDTH;
constant BUS_DATA_BYTES : INTEGER := BUS_DATA_WIDTH / 8;
constant BUS_ADDR_ALIGN : INTEGER := log2(BUS_DATA_BYTES);
--AW channel
constant TARGET_ADDR : INTEGER := (C_TARGET_ADDR/USER_DATA_BYTES)*USER_DATA_BYTES;
constant BOUNDARY_BEATS : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0) := (others => '1');
signal wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal fifo_wreq_data : UNSIGNED(USER_AW + 31 downto 0);
signal tmp_addr : UNSIGNED(USER_AW - 1 downto 0);
signal tmp_len : UNSIGNED(31 downto 0);
signal align_len : UNSIGNED(31 downto 0);
signal sect_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal awlen_tmp : UNSIGNED(7 downto 0);
signal start_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal start_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal end_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awaddr_tmp : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_addr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal sect_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal sect_end_buf : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal burst_end : UNSIGNED(BUS_ADDR_ALIGN - 1 downto 0);
signal start_to_4k : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal sect_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal beat_len_buf : UNSIGNED(11 - BUS_ADDR_ALIGN downto 0);
signal burst_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal zero_len_event : STD_LOGIC;
signal negative_len_event : STD_LOGIC;
signal invalid_len_event : STD_LOGIC;
signal invalid_len_event_1 : STD_LOGIC;
signal invalid_len_event_2 : STD_LOGIC;
signal fifo_wreq_valid : STD_LOGIC;
signal fifo_wreq_valid_buf : STD_LOGIC;
signal fifo_wreq_read : STD_LOGIC;
signal fifo_burst_w : STD_LOGIC;
signal fifo_resp_w : STD_LOGIC;
signal last_sect_buf : STD_LOGIC;
signal ready_for_sect : STD_LOGIC;
signal AWVALID_Dummy : STD_LOGIC;
signal next_wreq : BOOLEAN;
signal ready_for_wreq : BOOLEAN;
signal wreq_handling : BOOLEAN;
signal first_sect : BOOLEAN;
signal last_sect : BOOLEAN;
signal next_sect : BOOLEAN;
--W channel
signal fifo_wdata_wstrb : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal data_pack : UNSIGNED(USER_DW + USER_DW/8 - 1 downto 0);
signal tmp_data : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal tmp_strb : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal len_cnt : UNSIGNED(7 downto 0);
signal burst_len : UNSIGNED(7 downto 0);
signal data_valid : STD_LOGIC;
signal next_data : STD_LOGIC;
signal burst_valid : STD_LOGIC;
signal fifo_burst_ready : STD_LOGIC;
signal next_burst : STD_LOGIC;
signal WVALID_Dummy : STD_LOGIC;
signal WLAST_Dummy : STD_LOGIC;
--B channel
signal resp_total : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal resp_cnt : UNSIGNED(C_M_AXI_ADDR_WIDTH - 13 downto 0);
signal bresp_tmp : UNSIGNED(1 downto 0);
signal next_resp : BOOLEAN;
signal fifo_resp_ready : STD_LOGIC;
signal need_wrsp : STD_LOGIC;
signal resp_match : STD_LOGIC;
signal resp_ready : STD_LOGIC;
component get_gmem_m_axi_fifo is
generic (
DATA_BITS : INTEGER := 8;
DEPTH : INTEGER := 16;
DEPTH_BITS : INTEGER := 4);
port (
sclk : in STD_LOGIC;
reset : in STD_LOGIC;
sclk_en : in STD_LOGIC;
empty_n : out STD_LOGIC;
full_n : out STD_LOGIC;
rdreq : in STD_LOGIC;
wrreq : in STD_LOGIC;
q : out UNSIGNED(DATA_BITS-1 downto 0);
data : in UNSIGNED(DATA_BITS-1 downto 0));
end component get_gmem_m_axi_fifo;
begin
--------------------------- AW channel begin -----------------------------------
-- Instantiation
fifo_wreq : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_AW + 32,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => fifo_wreq_valid,
full_n => wreq_ack,
rdreq => fifo_wreq_read,
wrreq => wreq_valid,
q => fifo_wreq_data,
data => wreq_data);
wreq_data <= (wreq_length & wreq_addr);
tmp_addr <= fifo_wreq_data(USER_AW - 1 downto 0);
tmp_len <= fifo_wreq_data(USER_AW + 31 downto USER_AW);
end_addr <= start_addr + align_len;
zero_len_event <= '1' when fifo_wreq_valid = '1' and tmp_len = 0 else '0';
negative_len_event <= tmp_len(31) when fifo_wreq_valid = '1' else '0';
next_wreq <= (fifo_wreq_valid = '1' or fifo_wreq_valid_buf = '1') and ready_for_wreq;
ready_for_wreq <= not(wreq_handling and not(last_sect and next_sect));
fifo_wreq_read <= '1' when next_wreq else '0';
align_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
align_len <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
if (zero_len_event = '1' or negative_len_event = '1') then
align_len <= (others => '0');
else
align_len <= SHIFT_LEFT(tmp_len, USER_ADDR_ALIGN) - 1;
end if;
end if;
end if;
end if;
end process align_len_proc;
start_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr <= (others => '0');
elsif ACLK_EN = '1' then
if (fifo_wreq_valid = '1' and ready_for_wreq) then
start_addr <= TARGET_ADDR + SHIFT_LEFT(RESIZE(tmp_addr, C_M_AXI_ADDR_WIDTH), USER_ADDR_ALIGN);
end if;
end if;
end if;
end process start_addr_proc;
fifo_wreq_valid_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
fifo_wreq_valid_buf <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
fifo_wreq_valid_buf <= fifo_wreq_valid;
end if;
end if;
end if;
end process fifo_wreq_valid_buf_proc;
invalid_len_event_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event <= '0';
elsif ACLK_EN = '1' then
if (next_wreq) then
invalid_len_event <= zero_len_event or negative_len_event;
end if;
end if;
end if;
end process invalid_len_event_proc;
wreq_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wreq_handling <= false;
elsif ACLK_EN = '1' then
if fifo_wreq_valid_buf = '1' and not wreq_handling then
wreq_handling <= true;
elsif fifo_wreq_valid_buf = '0' and last_sect and next_sect then
wreq_handling <= false;
end if;
end if;
end if;
end process wreq_handling_proc;
start_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
start_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
start_addr_buf <= start_addr;
end if;
end if;
end if;
end process start_addr_buf_proc;
end_addr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
end_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
end_addr_buf <= end_addr;
end if;
end if;
end if;
end process end_addr_buf_proc;
beat_len_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
beat_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
beat_len_buf <= RESIZE(SHIFT_RIGHT(align_len(11 downto 0) + start_addr(BUS_ADDR_ALIGN-1 downto 0), BUS_ADDR_ALIGN), 12-BUS_ADDR_ALIGN);
end if;
end if;
end if;
end process beat_len_buf_proc;
sect_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_wreq then
sect_cnt <= start_addr(C_M_AXI_ADDR_WIDTH - 1 downto 12);
elsif next_sect then
sect_cnt <= sect_cnt + 1;
end if;
end if;
end if;
end process sect_cnt_proc;
-- event registers
invalid_len_event_1_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_1 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_1 <= invalid_len_event;
end if;
end if;
end process invalid_len_event_1_proc;
-- end event registers
first_sect <= (sect_cnt = start_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto 12));
last_sect <= (sect_cnt = end_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 12));
next_sect <= wreq_handling and ready_for_sect = '1';
sect_addr <= start_addr_buf when first_sect else
sect_cnt & (11 downto 0 => '0');
sect_addr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_addr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_addr_buf <= sect_addr;
end if;
end if;
end if;
end process sect_addr_proc;
start_to_4k <= BOUNDARY_BEATS - start_addr_buf(11 downto BUS_ADDR_ALIGN);
sect_len <= beat_len_buf when first_sect and last_sect else
start_to_4k when first_sect and not last_sect else
end_addr_buf(11 downto BUS_ADDR_ALIGN) when not first_sect and last_sect else
BOUNDARY_BEATS when not first_sect and not last_sect;
sect_len_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_len_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_len_buf <= sect_len;
end if;
end if;
end if;
end process sect_len_proc;
sect_end <= end_addr_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_sect else
(others => '1');
sect_end_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_end_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
sect_end_buf <= sect_end;
end if;
end if;
end if;
end process sect_end_proc;
-- event registers
invalid_len_event_2_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
invalid_len_event_2 <= '0';
elsif ACLK_EN = '1' then
invalid_len_event_2 <= invalid_len_event_1;
end if;
end if;
end process invalid_len_event_2_proc;
-- end event registers
AWID <= (others => '0');
AWSIZE <= TO_UNSIGNED(BUS_ADDR_ALIGN, AWSIZE'length);
AWBURST <= "01";
AWLOCK <= "00";
AWCACHE <= TO_UNSIGNED(C_CACHE_VALUE, AWCACHE'length);
AWPROT <= TO_UNSIGNED(C_PROT_VALUE, AWPROT'length);
AWUSER <= TO_UNSIGNED(C_USER_VALUE, AWUSER'length);
AWQOS <= wreq_qos;
-- if BUS_DATA_BYTES >= 16, then a 256 length burst is 4096 bytes(reach boundary).
must_one_burst : if (BUS_DATA_BYTES >= 16) generate
begin
AWADDR <= sect_addr_buf(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
AWLEN <= RESIZE(sect_len_buf, 8);
AWVALID <= AWVALID_Dummy;
ready_for_sect <= '1' when not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1' else '0';
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event = '1' then
AWVALID_Dummy <= '0';
elsif next_sect then
AWVALID_Dummy <= '1';
elsif not next_sect and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when last_sect and next_sect else '0';
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_wreq then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_sect then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_sect else '0';
burst_end <= sect_end;
awaddr_tmp <= sect_addr(C_M_AXI_ADDR_WIDTH - 1 downto 0);
awlen_tmp <= RESIZE(sect_len, 8);
end generate must_one_burst;
could_multi_bursts : if (BUS_DATA_BYTES < 16) generate
signal awaddr_buf : UNSIGNED(C_M_AXI_ADDR_WIDTH - 1 downto 0);
signal awlen_buf : UNSIGNED(7 downto 0);
signal loop_cnt : UNSIGNED(3 - BUS_ADDR_ALIGN downto 0);
signal last_loop : BOOLEAN;
signal next_loop : BOOLEAN;
signal ready_for_loop : BOOLEAN;
signal sect_handling : BOOLEAN;
begin
AWADDR <= awaddr_buf;
AWLEN <= awlen_buf;
AWVALID <= AWVALID_Dummy;
last_loop <= (loop_cnt = sect_len_buf(11 - BUS_ADDR_ALIGN downto 8));
next_loop <= sect_handling and ready_for_loop;
ready_for_sect <= '1' when not (sect_handling and not (last_loop and next_loop)) else '0';
ready_for_loop <= not (AWVALID_Dummy = '1' and AWREADY = '0') and fifo_resp_ready = '1' and fifo_burst_ready = '1';
sect_handling_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
sect_handling <= false;
elsif ACLK_EN = '1' then
if wreq_handling and not sect_handling then
sect_handling <= true;
elsif not wreq_handling and last_loop and next_loop then
sect_handling <= false;
end if;
end if;
end if;
end process sect_handling_proc;
loop_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
loop_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_sect then
loop_cnt <= (others => '0');
elsif next_loop then
loop_cnt <= loop_cnt + 1;
end if;
end if;
end if;
end process loop_cnt_proc;
awaddr_tmp <= sect_addr_buf(C_M_AXI_ADDR_WIDTH -1 downto 0) when loop_cnt = 0 else
awaddr_buf + SHIFT_LEFT(RESIZE(awlen_buf, 32) + 1, BUS_ADDR_ALIGN);
awaddr_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awaddr_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awaddr_buf <= awaddr_tmp(C_M_AXI_ADDR_WIDTH - 1 downto BUS_ADDR_ALIGN) & (BUS_ADDR_ALIGN - 1 downto 0 => '0');
end if;
end if;
end if;
end process awaddr_buf_proc;
awlen_tmp <= sect_len_buf(7 downto 0) when last_loop else
X"FF";
awlen_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
awlen_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_loop then
awlen_buf <= awlen_tmp;
end if;
end if;
end if;
end process awlen_buf_proc;
awvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
AWVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if invalid_len_event_2 = '1' then
AWVALID_Dummy <= '0';
elsif next_loop then
AWVALID_Dummy <= '1';
elsif not next_loop and AWREADY = '1' then
AWVALID_Dummy <= '0';
end if;
end if;
end if;
end process awvalid_proc;
fifo_resp_w <= '1' when next_loop and last_loop and last_sect_buf = '1' else '0';
last_sect_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
last_sect_buf <= '0';
elsif ACLK_EN = '1' then
if next_sect and last_sect then
last_sect_buf <= '1';
elsif next_sect then
last_sect_buf <= '0';
end if;
end if;
end if;
end process last_sect_buf_proc;
burst_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
burst_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if invalid_len_event_1 = '1' then
burst_cnt <= (others => '0');
elsif next_sect and first_sect then
burst_cnt <= (others => '0');
burst_cnt(0) <= '1';
elsif next_loop then
burst_cnt <= burst_cnt + 1;
end if;
end if;
end if;
end process burst_cnt_proc;
fifo_burst_w <= '1' when next_loop else '0';
burst_end <= sect_end_buf(BUS_ADDR_ALIGN - 1 downto 0) when last_loop else (others => '1');
end generate could_multi_bursts;
--------------------------- AW channel end -------------------------------------
--------------------------- W channel begin ------------------------------------
-- Instantiation
fifo_wdata : get_gmem_m_axi_fifo
generic map (
DATA_BITS => USER_DW + USER_DW/8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => data_valid,
full_n => wdata_ack,
rdreq => next_data,
wrreq => wdata_valid,
q => data_pack,
data => fifo_wdata_wstrb);
fifo_wdata_wstrb <= (wdata_strb & wdata_data);
tmp_data <= RESIZE(data_pack(USER_DW - 1 downto 0), USER_DATA_WIDTH);
tmp_strb <= RESIZE(data_pack(USER_DW + USER_DW/8 - 1 downto USER_DW), USER_DATA_BYTES);
bus_equal_gen : if (USER_DATA_WIDTH = BUS_DATA_WIDTH) generate
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal ready_for_data : BOOLEAN;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
next_data <= '1' when burst_valid = '1' and data_valid = '1' and ready_for_data else '0';
next_burst <= '1' when len_cnt = burst_len and next_data = '1' else '0';
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_equal_gen;
bus_narrow_gen : if (USER_DATA_WIDTH > BUS_DATA_WIDTH) generate
constant TOTAL_SPLIT : INTEGER := USER_DATA_WIDTH / BUS_DATA_WIDTH;
constant SPLIT_ALIGN : INTEGER := log2(TOTAL_SPLIT);
signal data_buf : UNSIGNED(USER_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(USER_DATA_BYTES - 1 downto 0);
signal split_cnt : UNSIGNED(SPLIT_ALIGN - 1 downto 0);
signal tmp_burst_info : UNSIGNED(7 downto 0);
signal first_split : BOOLEAN;
signal next_split : BOOLEAN;
signal last_split : BOOLEAN;
signal ready_for_data : BOOLEAN;
begin
-- instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_len,
data => tmp_burst_info);
WDATA <= data_buf(BUS_DATA_WIDTH - 1 downto 0);
WSTRB <= strb_buf(BUS_DATA_BYTES - 1 downto 0);
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= RESIZE(awlen_tmp, 8);
next_data <= '1' when first_split else '0';
next_burst <= '1' when len_cnt = burst_len and burst_valid = '1' and last_split else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_split <= split_cnt = 0 and data_valid = '1' and burst_valid ='1' and ready_for_data;
next_split <= split_cnt /= 0 and ready_for_data;
last_split <= split_cnt = (TOTAL_SPLIT - 1) and ready_for_data;
split_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
split_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if last_split then
split_cnt <= (others => '0');
elsif first_split or next_split then
split_cnt <= split_cnt + 1;
end if;
end if;
end if;
end process split_cnt_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_data = '1' or next_split then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
data_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
data_buf <= tmp_data;
elsif next_split then
data_buf <= SHIFT_RIGHT(data_buf, BUS_DATA_WIDTH);
end if;
end if;
end if;
end process data_buf_proc;
strb_buf_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
strb_buf <= (others => '0');
elsif ACLK_EN = '1' then
if next_data = '1' then
strb_buf <= tmp_strb;
elsif next_split then
strb_buf <= SHIFT_RIGHT(strb_buf, BUS_DATA_BYTES);
end if;
end if;
end if;
end process strb_buf_proc;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_data = '1' then
WVALID_Dummy <= '1';
elsif not (first_split or next_split) and ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' and last_split then
WLAST_Dummy <= '1';
elsif ready_for_data then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
end generate bus_narrow_gen;
bus_wide_gen : if (USER_DATA_WIDTH < BUS_DATA_WIDTH) generate
constant TOTAL_PADS : INTEGER := BUS_DATA_WIDTH / USER_DATA_WIDTH;
constant PAD_ALIGN : INTEGER := log2(TOTAL_PADS);
signal data_buf : UNSIGNED(BUS_DATA_WIDTH - 1 downto 0);
signal strb_buf : UNSIGNED(BUS_DATA_BYTES - 1 downto 0);
signal burst_pack : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal tmp_burst_info : UNSIGNED(2*PAD_ALIGN + 7 downto 0);
signal head_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal tail_pads : UNSIGNED(PAD_ALIGN - 1 downto 0);
signal add_head : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal add_tail : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal pad_oh_reg : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal head_pad_sel : UNSIGNED(TOTAL_PADS - 1 downto 0);
signal tail_pad_sel : UNSIGNED(0 to TOTAL_PADS - 1);
signal ready_for_data : BOOLEAN;
signal next_pad : BOOLEAN;
signal first_pad : BOOLEAN;
signal last_pad : BOOLEAN;
signal first_beat : BOOLEAN;
signal last_beat : BOOLEAN;
signal next_beat : BOOLEAN;
component get_gmem_m_axi_decoder is
generic (
DIN_WIDTH : integer := 3);
port (
din : in UNSIGNED(DIN_WIDTH - 1 downto 0);
dout : out UNSIGNED(2**DIN_WIDTH - 1 downto 0));
end component get_gmem_m_axi_decoder;
begin
-- Instantiation
fifo_burst : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 8 + 2*PAD_ALIGN,
DEPTH => user_maxreqs,
DEPTH_BITS => log2(user_maxreqs))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => burst_valid,
full_n => fifo_burst_ready,
rdreq => next_burst,
wrreq => fifo_burst_w,
q => burst_pack,
data => tmp_burst_info);
WDATA <= data_buf;
WSTRB <= strb_buf;
WLAST <= WLAST_Dummy;
WVALID <= WVALID_Dummy;
tmp_burst_info <= awaddr_tmp(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & burst_end(BUS_ADDR_ALIGN - 1 downto USER_ADDR_ALIGN) & RESIZE(awlen_tmp, 8);
head_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => head_pads,
dout => head_pad_sel);
tail_pad_decoder : get_gmem_m_axi_decoder
generic map (
DIN_WIDTH => PAD_ALIGN)
port map (
din => tail_pads,
dout => tail_pad_sel);
head_pads <= burst_pack(2*PAD_ALIGN + 7 downto 8 + PAD_ALIGN);
tail_pads <= not burst_pack(PAD_ALIGN + 7 downto 8);
burst_len <= burst_pack(7 downto 0);
next_data <= '1' when next_pad else '0';
next_burst <= '1' when last_beat and next_beat else '0';
ready_for_data <= not (WVALID_Dummy = '1' and WREADY = '0');
first_beat <= len_cnt = 0 and burst_valid = '1';
last_beat <= len_cnt = burst_len and burst_valid = '1';
next_beat <= burst_valid = '1' and last_pad and ready_for_data;
next_pad <= burst_valid = '1' and data_valid = '1' and ready_for_data;
last_pad <= pad_oh(TOTAL_PADS - to_integer(tail_pads) - 1) = '1' when last_beat else
pad_oh(TOTAL_PADS - 1) = '1';
first_pad_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
first_pad <= true;
elsif ACLK_EN = '1' then
if next_pad and not last_pad then
first_pad <= false;
elsif next_pad and last_pad then
first_pad <= true;
end if;
end if;
end if;
end process first_pad_proc;
pad_oh <= (others => '0') when data_valid = '0' else
SHIFT_LEFT(TO_UNSIGNED(1, TOTAL_PADS), TO_INTEGER(head_pads)) when first_beat and first_pad else
TO_UNSIGNED(1, TOTAL_PADS) when first_pad else
pad_oh_reg;
pad_oh_reg_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
pad_oh_reg <= (others => '0');
elsif ACLK_EN = '1' then
if next_pad then
pad_oh_reg <= pad_oh(TOTAL_PADS - 2 downto 0) & '0';
end if;
end if;
end if;
end process pad_oh_reg_proc;
data_strb_gen : for i in 1 to TOTAL_PADS generate
begin
add_head(i-1) <= '1' when head_pad_sel(i-1) = '1' and first_beat else
'0';
add_tail(i-1) <= '1' when tail_pad_sel(i-1) = '1' and last_beat else
'0';
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif ACLK_EN = '1' then
if (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
data_buf(i*USER_DATA_WIDTH - 1 downto (i-1)*USER_DATA_WIDTH) <= tmp_data;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') and ACLK_EN = '1' then
if (ARESET = '1') then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif (add_head(i-1) = '1' or add_tail(i-1) = '1') and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= (others => '0');
elsif pad_oh(i-1) = '1' and ready_for_data then
strb_buf(i*USER_DATA_BYTES - 1 downto (i-1)*USER_DATA_BYTES) <= tmp_strb;
end if;
end if;
end process;
end generate data_strb_gen;
wvalid_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WVALID_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_beat then
WVALID_Dummy <= '1';
elsif ready_for_data then
WVALID_Dummy <= '0';
end if;
end if;
end if;
end process wvalid_proc;
wlast_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
WLAST_Dummy <= '0';
elsif ACLK_EN = '1' then
if next_burst = '1' then
WLAST_Dummy <= '1';
elsif next_data = '1' then
WLAST_Dummy <= '0';
end if;
end if;
end if;
end process wlast_proc;
len_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
len_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if next_burst = '1' then
len_cnt <= (others => '0');
elsif next_beat then
len_cnt <= len_cnt + 1;
end if;
end if;
end if;
end process len_cnt_proc;
end generate bus_wide_gen;
--------------------------- W channel end --------------------------------------
--------------------------- B channel begin ------------------------------------
-- Instantiation
fifo_resp : get_gmem_m_axi_fifo
generic map (
DATA_BITS => C_M_AXI_ADDR_WIDTH - 12,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => need_wrsp,
full_n => fifo_resp_ready,
rdreq => resp_match,
wrreq => fifo_resp_w,
q => resp_total,
data => burst_cnt);
fifo_resp_to_user : get_gmem_m_axi_fifo
generic map (
DATA_BITS => 2,
DEPTH => USER_MAXREQS,
DEPTH_BITS => log2(USER_MAXREQS))
port map (
sclk => ACLK,
reset => ARESET,
sclk_en => ACLK_EN,
empty_n => wrsp_valid,
full_n => resp_ready,
rdreq => wrsp_ack,
wrreq => resp_match,
q => wrsp,
data => bresp_tmp);
BREADY <= resp_ready;
resp_match <= '1' when (resp_cnt = resp_total and need_wrsp = '1') else '0';
next_resp <= BVALID = '1' and resp_ready = '1';
resp_cnt_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
resp_cnt <= (others => '0');
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
resp_cnt <= (others => '0');
elsif (resp_match = '1' and next_resp) then
resp_cnt <= (others => '0');
resp_cnt(0) <= '1';
elsif (next_resp) then
resp_cnt <= resp_cnt + 1;
end if;
end if;
end if;
end process resp_cnt_proc;
bresp_tmp_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
bresp_tmp <= "00";
elsif ACLK_EN = '1' then
if (resp_match = '1' and not next_resp) then
bresp_tmp <= "00";
elsif (resp_match = '1' and next_resp) then
bresp_tmp <= BRESP;
elsif (next_resp and bresp_tmp(1) = '0') then
bresp_tmp <= BRESP;
end if;
end if;
end if;
end process bresp_tmp_proc;
--------------------------- B channel end --------------------------------------
end architecture behave;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Sun Sep 22 02:34:31 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub
-- d:/github/Digital-Hardware-Modelling/xilinx-vivado/hls_tutorial_lab1/hls_tutorial_lab1.srcs/sources_1/bd/zybo_zynq_design/ip/zybo_zynq_design_rst_ps7_0_100M_0/zybo_zynq_design_rst_ps7_0_100M_0_stub.vhdl
-- Design : zybo_zynq_design_rst_ps7_0_100M_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zybo_zynq_design_rst_ps7_0_100M_0 is
Port (
slowest_sync_clk : in STD_LOGIC;
ext_reset_in : in STD_LOGIC;
aux_reset_in : in STD_LOGIC;
mb_debug_sys_rst : in STD_LOGIC;
dcm_locked : in STD_LOGIC;
mb_reset : out STD_LOGIC;
bus_struct_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_reset : out STD_LOGIC_VECTOR ( 0 to 0 );
interconnect_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 );
peripheral_aresetn : out STD_LOGIC_VECTOR ( 0 to 0 )
);
end zybo_zynq_design_rst_ps7_0_100M_0;
architecture stub of zybo_zynq_design_rst_ps7_0_100M_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "slowest_sync_clk,ext_reset_in,aux_reset_in,mb_debug_sys_rst,dcm_locked,mb_reset,bus_struct_reset[0:0],peripheral_reset[0:0],interconnect_aresetn[0:0],peripheral_aresetn[0:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "proc_sys_reset,Vivado 2018.2";
begin
end;
|
-------------------------------------------------------------------------------
--
-- The IN port controller.
--
-- $Id: t400_io_in-c.vhd,v 1.1 2006-05-22 00:00:55 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger (arniml@opencores.org)
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t400_io_in_rtl_c0 of t400_io_in is
for rtl
end for;
end t400_io_in_rtl_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- A Mars and Earth timer calibrated for a 50MHz clock.
--
-- entity name: g23_mars_timer
--
-- Copyright (C) 2014 cadesalaberry, grahamludwinski
--
-- Version 1.0
--
-- Author:
-- Charles-Antoine de Salaberry; ca.desalaberry@mail.mcgill.ca,
-- Graham Ludwinski; graham.ludwinski@mail.mcgill.ca
--
-- Date: 13/03/2014
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
ENTITY g23_basic_timer IS
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
EPULSE : out STD_LOGIC;
MPULSE : out STD_LOGIC
);
END g23_basic_timer;
ARCHITECTURE alpha OF g23_basic_timer IS
COMPONENT g23_generic_timer
GENERIC (max : natural := 0);
PORT (
clk : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
pulse : out STD_LOGIC
);
END COMPONENT;
BEGIN
earth : g23_generic_timer
-- GENERIC MAP (max => 49999999)
-- GENERIC MAP (max => 1000)
GENERIC MAP (max => 100)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => EPULSE
);
mars : g23_generic_timer
-- GENERIC MAP (max => 51374562)
-- GENERIC MAP (max => 1027)
GENERIC MAP (max => 102)
PORT MAP (
clk => clk,
enable => enable,
reset => reset,
pulse => MPULSE
);
END alpha;
|
--*****************************************************************************
-- (c) Copyright 2009 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 4.0
-- \ \ Application : MIG
-- / / Filename : example_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 08:35:03 $
-- \ \ / \ Date Created : Wed Feb 01 2012
-- \___\/\___\
--
-- Device : 7 Series
-- Design Name : DDR2 SDRAM
-- Purpose :
-- Top-level module. This module serves as an example,
-- and allows the user to synthesize a self-contained design,
-- which they can be used to test their hardware.
-- In addition to the memory controller, the module instantiates:
-- 1. Synthesizable testbench - used to model user's backend logic
-- and generate different traffic patterns
-- Reference :
-- Revision History :
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity example_top is
-- generic (
--
-- --***************************************************************************
-- -- Traffic Gen related parameters
-- --***************************************************************************
-- BL_WIDTH : integer := 10;
-- PORT_MODE : string := "BI_MODE";
-- DATA_MODE : std_logic_vector(3 downto 0) := "0010";
-- ADDR_MODE : std_logic_vector(3 downto 0) := "0011";
-- TST_MEM_INSTR_MODE : string := "R_W_INSTR_MODE";
-- EYE_TEST : string := "FALSE";
-- -- set EYE_TEST = "TRUE" to probe memory
-- -- signals. Traffic Generator will only
-- -- write to one single location and no
-- -- read transactions will be generated.
-- DATA_PATTERN : string := "DGEN_ALL";
-- -- For small devices, choose one only.
-- -- For large device, choose "DGEN_ALL"
-- -- "DGEN_HAMMER", "DGEN_WALKING1",
-- -- "DGEN_WALKING0","DGEN_ADDR","
-- -- "DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
-- CMD_PATTERN : string := "CGEN_ALL";
-- -- "CGEN_PRBS","CGEN_FIXED","CGEN_BRAM",
-- -- "CGEN_SEQUENTIAL", "CGEN_ALL"
-- BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000000";
-- END_ADDRESS : std_logic_vector(31 downto 0) := X"00ffffff";
-- MEM_ADDR_ORDER : string := "BANK_ROW_COLUMN";
-- --Possible Parameters
-- --1.BANK_ROW_COLUMN : Address mapping is
-- -- in form of Bank Row Column.
-- --2.ROW_BANK_COLUMN : Address mapping is
-- -- in the form of Row Bank Column.
-- --3.TG_TEST : Scrambles Address bits
-- -- for distributed Addressing.
-- PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"ff000000";
-- CMD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
-- WR_WDT : std_logic_vector(31 downto 0) := X"00001fff";
-- RD_WDT : std_logic_vector(31 downto 0) := X"000003ff";
--
-- --***************************************************************************
-- -- The following parameters refer to width of various ports
-- --***************************************************************************
-- BANK_WIDTH : integer := 3;
-- -- # of memory Bank Address bits.
-- COL_WIDTH : integer := 10;
-- -- # of memory Column Address bits.
-- CS_WIDTH : integer := 1;
-- -- # of unique CS outputs to memory.
-- DQ_WIDTH : integer := 16;
-- -- # of DQ (data)
-- DQS_WIDTH : integer := 2;
-- DQS_CNT_WIDTH : integer := 1;
-- -- = ceil(log2(DQS_WIDTH))
-- DRAM_WIDTH : integer := 8;
-- -- # of DQ per DQS
-- ECC_TEST : string := "OFF";
-- RANKS : integer := 1;
-- -- # of Ranks.
-- ROW_WIDTH : integer := 13;
-- -- # of memory Row Address bits.
-- ADDR_WIDTH : integer := 27;
-- -- # = RANK_WIDTH + BANK_WIDTH
-- -- + ROW_WIDTH + COL_WIDTH;
-- -- Chip Select is always tied to low for
-- -- single rank devices
-- --***************************************************************************
-- -- The following parameters are mode register settings
-- --***************************************************************************
-- BURST_MODE : string := "8";
-- -- DDR3 SDRAM:
-- -- Burst Length (Mode Register 0).
-- -- # = "8", "4", "OTF".
-- -- DDR2 SDRAM:
-- -- Burst Length (Mode Register).
-- -- # = "8", "4".
-- --***************************************************************************
-- -- Simulation parameters
-- --***************************************************************************
-- SIMULATION : string := "FALSE";
-- -- Should be TRUE during design simulations and
-- -- FALSE during implementations
--
-- --***************************************************************************
-- -- IODELAY and PHY related parameters
-- --***************************************************************************
-- TCQ : integer := 100;
--
-- DRAM_TYPE : string := "DDR2";
--
--
-- --***************************************************************************
-- -- System clock frequency parameters
-- --***************************************************************************
-- nCK_PER_CLK : integer := 4;
-- -- # of memory CKs per fabric CLK
--
-- --***************************************************************************
-- -- Debug parameters
-- --***************************************************************************
-- DEBUG_PORT : string := "OFF";
-- -- # = "ON" Enable debug signals/controls.
-- -- = "OFF" Disable debug signals/controls.
--
-- --***************************************************************************
-- -- Temparature monitor parameter
-- --***************************************************************************
-- TEMP_MON_CONTROL : string := "INTERNAL"
-- -- # = "INTERNAL", "EXTERNAL"
--
-- -- RST_ACT_LOW : integer := 1
-- -- =1 for active low reset,
-- -- =0 for active high.
-- );
port (
-- Inouts
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0);
-- Outputs
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
-- Inputs
-- Single-ended system clock
sys_clk_i : in std_logic;
tg_compare_error : out std_logic;
init_calib_complete : out std_logic;
-- System reset - Default polarity of sys_rst pin is Active Low.
-- System reset polarity will change based on the option
-- selected in GUI.
sys_rst : in std_logic
);
end entity example_top;
architecture arch_example_top of example_top is
-- -- clogb2 function - ceiling of log base 2
-- function clogb2 (size : integer) return integer is
-- variable base : integer := 1;
-- variable inp : integer := 0;
-- begin
-- inp := size - 1;
-- while (inp > 1) loop
-- inp := inp/2 ;
-- base := base + 1;
-- end loop;
-- return base;
-- end function;function STR_TO_INT(BM : string) return integer is
-- begin
-- if(BM = "8") then
-- return 8;
-- elsif(BM = "4") then
-- return 4;
-- else
-- return 0;
-- end if;
-- end function;
--
-- constant RANK_WIDTH : integer := clogb2(RANKS);
--
-- function XWIDTH return integer is
-- begin
-- if(CS_WIDTH = 1) then
-- return 0;
-- else
-- return RANK_WIDTH;
-- end if;
-- end function;
--
--
--
-- constant CMD_PIPE_PLUS1 : string := "ON";
-- -- add pipeline stage between MC and PHY
-- constant tPRDI : integer := 1000000;
-- -- memory tPRDI paramter in pS.
-- constant DATA_WIDTH : integer := 16;
-- constant PAYLOAD_WIDTH : integer := DATA_WIDTH;
-- constant BURST_LENGTH : integer := STR_TO_INT(BURST_MODE);
-- constant APP_DATA_WIDTH : integer := 2 * nCK_PER_CLK * PAYLOAD_WIDTH;
-- constant APP_MASK_WIDTH : integer := APP_DATA_WIDTH / 8;
--
-- --***************************************************************************
-- -- Traffic Gen related parameters (derived)
-- --***************************************************************************
-- constant TG_ADDR_WIDTH : integer := XWIDTH + BANK_WIDTH + ROW_WIDTH + COL_WIDTH;
-- constant MASK_SIZE : integer := DATA_WIDTH/8;
signal s_init_calibration_complete : std_logic;
-- Start of User Design memory_ctrl component
component memory_ctrl
port
(-- Clock in ports
clk_100MHz_i : in std_logic;
rstn_i : in std_logic;
init_calib_complete_o : out std_logic; -- when calibrated
-- DDR2 interface signals
ddr2_addr : out std_logic_vector(12 downto 0);
ddr2_ba : out std_logic_vector(2 downto 0);
ddr2_ras_n : out std_logic;
ddr2_cas_n : out std_logic;
ddr2_we_n : out std_logic;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out std_logic_vector(1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout std_logic_vector(15 downto 0);
ddr2_dqs_p : inout std_logic_vector(1 downto 0);
ddr2_dqs_n : inout std_logic_vector(1 downto 0)
);
end component;
begin
--***************************************************************************
cmp_memory_ctrl : entity work.memory_ctrl
port map (
clk_100MHz_i => sys_clk_i,
rstn_i => sys_rst,
init_calib_complete_o => s_init_calibration_complete,
-- DDR2 interface signals
ddr2_addr => ddr2_addr,
ddr2_ba => ddr2_ba,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n,
ddr2_ck_p => ddr2_ck_p,
ddr2_ck_n => ddr2_ck_n,
ddr2_cke => ddr2_cke,
ddr2_cs_n => ddr2_cs_n,
ddr2_dm => ddr2_dm,
ddr2_odt => ddr2_odt,
ddr2_dq => ddr2_dq,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n );
init_calib_complete <= s_init_calibration_complete;
tg_compare_error <= '0';
end architecture arch_example_top;
|
/***************************************************************************************************
/
/ Author: Antonio Pastor González
/ ¯¯¯¯¯¯
/
/ Date:
/ ¯¯¯¯
/
/ Version:
/ ¯¯¯¯¯¯¯
/
/ Notes:
/ ¯¯¯¯¯
/ This design makes use of some features from VHDL-2008, all of which have been implemented in
/ Vivado by Xilinx
/ A 3 space tab is used throughout the document
/
/
/ Description:
/ ¯¯¯¯¯¯¯¯¯¯¯
/ This is the interface between the instantiation of an adder an its core. It exists to make it
/ possible to use external std_ulogic_vector which contain the numeric values while having modules
/ which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed).
/ As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer
/ range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed
/ a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is
/ adopted where the integer indexes of the fixed point types are moved to the natural space with a
/ transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and
/ adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example,
/ fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector
/ Additionally, the generics' consistency and correctness are checked in here.
/
**************************************************************************************************/
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.common_data_types_pkg.all;
use work.common_pkg.all;
use work.adder_pkg.all;
use work.fixed_generic_pkg.all;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
entity adder_s is
generic(
DATA_IMM_AFTER_START_opt : boolean := false; --default
SPEED_opt : T_speed := t_min; --exception: value not set
MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set
TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set
S : positive --compulsory
);
port(
input : in u_sfixed_v; --unconstrained array
clk : in std_ulogic;
start : in std_ulogic;
valid_input : in std_ulogic;
output : out u_sfixed; --unconstrained array
valid_output : out std_ulogic
);
end entity;
/*================================================================================================*/
/*================================================================================================*/
/*================================================================================================*/
architecture adder_s1 of adder_s is
constant P : positive := input'length(1);
constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt,
S,
P,
input(1)'high,
input(1)'low);
/*================================================================================================*/
/*================================================================================================*/
begin
adder_core_s_1:
entity work.adder_core_s
generic map(
DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt,
SPEED_opt => SPEED_opt,
MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt,
TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt,
S => S,
P => P,
input_high => input(1)'high,
input_low => input(1)'low
)
port map(
clk => clk,
input => input,
valid_input => valid_input,
start => start,
output => output,
valid_output => valid_output
);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity twos_complement_n is
generic ( N : positive := 8 );
port (
x : in std_logic_vector ( N downto 1 );
y : out std_logic_vector ( N downto 1 )
);
end twos_complement_n;
architecture twos_complement_n_impl of twos_complement_n is
begin
y <= std_logic_vector(unsigned(not(x)) + 1);
end architecture twos_complement_n_impl; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity reg_adder is
port (
A, B: in std_logic_vector (3 downto 0);
clk : in std_logic;
se : in std_logic;
C: out std_logic_vector(3 downto 0);
over : out std_logic
);
end entity;
architecture reg_adder of reg_adder is
signal a1,b1, o: std_logic_vector(3 downto 0) := "0000";
signal c1, ci: std_logic :='0';
begin
process(clk)
begin
if rising_edge(clk) then
if se='1' then
a1<= A;
b1<= B;
else
c1<=a1(0) xor b1(0) xor ci;
ci<=a1(0) and b1(0);
a1<= '0'&a1(3 downto 1);
b1<= '0'&b1(3 downto 1);
o<=c1&o(3 downto 1);
end if;
end if;
end process;
over<=ci;
C<=o;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdmctrl
-- File: sdmctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: SDRAM memory controller to fit with LEON2 memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
entity sdmctrl is
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0;
mobile : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end;
architecture rtl of sdmctrl is
constant WPROTEN : boolean := (wprot /= 0);
constant SDINVCLK : boolean := (invclk /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant PM_PD : std_logic_vector(2 downto 0) := "001";
constant PM_SR : std_logic_vector(2 downto 0) := "010";
constant PM_DPD : std_logic_vector(2 downto 0) := "101";
type mcycletype is (midle, active, leadout);
type sdcycletype is (act1, act2, act3, rd1, rd2, rd3, rd4, rd5, rd6, rd7, rd8,
wr1, wr2, wr3, wr4, wr5, sidle, sref, pd, dpd);
type icycletype is (iidle, pre, ref, lmode, emode, finish);
-- sdram configuration register
type sdram_cfg_type is record
command : std_logic_vector(2 downto 0);
csize : std_logic_vector(1 downto 0);
bsize : std_logic_vector(2 downto 0);
casdel : std_ulogic; -- CAS to data delay: 2/3 clock cycles
trfc : std_logic_vector(2 downto 0);
trp : std_ulogic; -- precharge to activate: 2/3 clock cycles
refresh : std_logic_vector(14 downto 0);
renable : std_ulogic;
pageburst : std_ulogic;
mobileen : std_logic_vector(1 downto 0); -- Mobile SD support, Mobile SD enabled
ds : std_logic_vector(3 downto 0); -- ds(1:0) (ds(3:2) used to detect update)
tcsr : std_logic_vector(3 downto 0); -- tcrs(1:0) (tcrs(3:2) used to detect update)
pasr : std_logic_vector(5 downto 0); -- pasr(2:0) (pasr(5:3) used to detect update)
pmode : std_logic_vector(2 downto 0); -- Power-Saving mode
txsr : std_logic_vector(3 downto 0); -- Exit Self Refresh timing
cke : std_ulogic; -- Clock enable
end record;
-- local registers
type reg_type is record
hready : std_ulogic;
hsel : std_ulogic;
bdrive : std_ulogic;
burst : std_ulogic;
busy : std_ulogic;
bdelay : std_ulogic;
wprothit : std_ulogic;
startsd : std_ulogic;
aload : std_ulogic;
mstate : mcycletype;
sdstate : sdcycletype;
cmstate : mcycletype;
istate : icycletype;
icnt : std_logic_vector(2 downto 0);
cfg : sdram_cfg_type;
trfc : std_logic_vector(3 downto 0);
refresh : std_logic_vector(14 downto 0);
sdcsn : std_logic_vector(1 downto 0);
sdwen : std_ulogic;
rasn : std_ulogic;
casn : std_ulogic;
dqm : std_logic_vector(7 downto 0);
bsel : std_ulogic;
haddr : std_logic_vector(31 downto 10);
-- only needed to keep address lines from switch too much
address : std_logic_vector(16 downto 2); -- memory address
idlecnt : std_logic_vector(3 downto 0); -- Counter, 16 idle clock sycles before entering Power-Saving mode
sref_tmpcom : std_logic_vector(2 downto 0); -- Save SD command when exit sref
end record;
signal r, ri : reg_type;
begin
ctrl : process(rst, apbi, sdi, wpo, r)
variable v : reg_type; -- local variables for registers
variable startsd : std_ulogic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable haddr : std_logic_vector(31 downto 0);
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable dqm : std_logic_vector(7 downto 0);
variable raddr : std_logic_vector(12 downto 0);
variable adec : std_ulogic;
variable busy : std_ulogic;
variable aload : std_ulogic;
variable rams : std_logic_vector(1 downto 0);
variable hresp : std_logic_vector(1 downto 0);
variable ba : std_logic_vector(1 downto 0);
variable lline : std_logic_vector(2 downto 0);
variable rline : std_logic_vector(2 downto 0);
variable lineburst : boolean;
variable arefresh : std_logic;
begin
-- Variable default settings to avoid latches
v := r; startsd := '0'; v.busy := '0'; hresp := HRESP_OKAY;
lline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
rline := not r.cfg.casdel & r.cfg.casdel & r.cfg.casdel;
arefresh := '0';
if sdi.hready = '1' then v.hsel := sdi.hsel; end if;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '1' then v.hready := '0'; end if;
end if;
if fast = 1 then haddr := sdi.rhaddr; else haddr := sdi.haddr; end if;
if (pageburst = 0) or ((pageburst = 2) and r.cfg.pageburst = '0') then
lineburst := true;
else lineburst := false; end if;
-- main state
case sdi.hsize is
when "00" =>
case sdi.rhaddr(1 downto 0) is
when "00" => dqm := "11110111";
when "01" => dqm := "11111011";
when "10" => dqm := "11111101";
when others => dqm := "11111110";
end case;
when "01" =>
if sdi.rhaddr(1) = '0' then dqm := "11110011"; else dqm := "11111100"; end if;
when others => dqm := "11110000";
end case;
if BUS64 and (r.bsel = '1') then
dqm := dqm(3 downto 0) & "1111";
end if;
-- main FSM
case r.mstate is
when midle =>
if (v.hsel and sdi.nhtrans(1)) = '1' then
if (r.sdstate = sidle) and (r.cfg.command = "000") and
(r.cmstate = midle) and (sdi.idle = '1')
then
if fast = 1 then v.startsd := '1'; else startsd := '1'; end if;
v.mstate := active;
elsif ((r.sdstate = sref) or (r.sdstate = pd) or (r.sdstate = dpd))
and (r.cfg.command = "000") and (r.cmstate = midle) --and (v.hio = '0')
then
v.startsd := '1';
if r.sdstate = dpd then -- Error response when on Deep Power-Down mode
hresp := HRESP_ERROR;
else
v.mstate := active;
end if;
end if;
end if;
when others => null;
end case;
startsd := r.startsd or startsd;
-- generate row and column address size
case r.cfg.csize is
when "00" => raddr := haddr(22 downto 10);
when "01" => raddr := haddr(23 downto 11);
when "10" => raddr := haddr(24 downto 12);
when others =>
if r.cfg.bsize = "111" then raddr := haddr(26 downto 14);
else raddr := haddr(25 downto 13); end if;
end case;
-- generate bank address
ba := genmux(r.cfg.bsize, haddr(28 downto 21)) &
genmux(r.cfg.bsize, haddr(27 downto 20));
-- generate chip select
if BUS64 then
adec := genmux(r.cfg.bsize, haddr(30 downto 23));
v.bsel := genmux(r.cfg.bsize, sdi.rhaddr(29 downto 22));
else
adec := genmux(r.cfg.bsize, haddr(29 downto 22)); v.bsel := '0';
end if;
if (sdi.srdis = '0') and (r.cfg.bsize = "111") then adec := not adec; end if;
rams := adec & not adec;
if r.trfc /= "0000" then v.trfc := r.trfc - 1; end if;
if r.idlecnt /= "0000" then v.idlecnt := r.idlecnt - 1; end if;
-- sdram access FSM
case r.sdstate is
when sidle =>
v.bdelay := '0';
if (startsd = '1') and (r.cfg.command = "000") and (r.cmstate = midle) then
v.address(16 downto 2) := ba & raddr;
v.sdcsn := not rams(1 downto 0); v.rasn := '0'; v.sdstate := act1;
v.startsd := '0';
elsif (r.idlecnt = "0000") and (r.cfg.command = "000")
and (r.cmstate = midle) and (r.cfg.mobileen(1) = '1') then
case r.cfg.pmode is
when PM_SR =>
v.cfg.cke := '0'; v.sdstate := sref;
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; -- Control minimum duration of Self Refresh mode (= tRAS)
when PM_PD => v.cfg.cke := '0'; v.sdstate := pd;
when PM_DPD =>
v.cfg.cke := '0'; v.sdstate := dpd;
v.sdcsn := (others => '0'); v.sdwen := '0'; v.rasn := '1'; v.casn := '1';
when others =>
end case;
end if;
when act1 =>
v.rasn := '1'; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc; v.haddr := sdi.rhaddr(31 downto 10);
if r.cfg.casdel = '1' then v.sdstate := act2; else
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
end if;
if WPROTEN then
v.wprothit := wpo.wprothit;
if wpo.wprothit = '1' then hresp := HRESP_ERROR; end if;
end if;
when act2 =>
v.sdstate := act3;
v.hready := sdi.hwrite and sdi.htrans(0) and sdi.htrans(1);
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '0';
end if;
when act3 =>
v.casn := '0';
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
v.dqm := dqm; v.burst := r.hready;
if sdi.hwrite = '1' then
v.sdstate := wr1; v.sdwen := '0'; v.bdrive := '1';
if sdi.htrans = "11" or (r.hready = '0') then v.hready := '1'; end if;
if WPROTEN and (r.wprothit = '1') then
hresp := HRESP_ERROR; v.hready := '1';
v.sdstate := wr1; v.sdwen := '1'; v.bdrive := '0'; v.casn := '1';
end if;
else v.sdstate := rd1; end if;
when wr1 =>
v.address(14 downto 2) := sdi.rhaddr(13 downto 12) & '0' & sdi.rhaddr(11 downto 2);
if (((r.burst and r.hready) = '1') and (sdi.rhtrans = "11"))
and not (WPROTEN and (r.wprothit = '1'))
then
v.hready := sdi.htrans(0) and sdi.htrans(1) and r.hready;
if ((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) then -- exit on refresh
v.hready := '0';
end if;
else
v.sdstate := wr2; v.bdrive := '0'; v.casn := '1'; v.sdwen := '1';
v.dqm := (others => '1');
end if;
when wr2 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.trfc(2 downto 1) = "00") then
if (r.cfg.trp = '0') then v.rasn := '0'; v.sdwen := '0'; end if;
v.sdstate := wr3;
end if;
when wr3 =>
if (sdi.rhtrans = "10") and (sdi.rhaddr(31 downto 10) = r.haddr) and (r.sdwen = '1') and (r.hsel = '1') then
if sdi.hwrite = '1' then v.hready := '1'; end if; v.sdstate := act3;
elsif (r.cfg.trp = '1') then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := wr4;
else
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr4 =>
v.sdcsn := "11"; v.rasn := '1'; v.sdwen := '1';
if (r.cfg.trp = '1') then v.sdstate := wr5;
else
if r.trfc = "0000" then v.sdstate := sidle; end if;
end if;
when wr5 =>
if r.trfc = "0000" then v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
when rd1 =>
v.casn := '1'; v.sdstate := rd7;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "111" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd7 =>
v.casn := '1';
if r.cfg.casdel = '1' then
v.sdstate := rd2;
if lineburst and (sdi.htrans = "11") then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
else
v.sdstate := rd3;
if sdi.htrans /= "11" then
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "110" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
end if;
when rd2 =>
v.casn := '1'; v.sdstate := rd3;
if sdi.htrans /= "11" then -- v.rasn := '0'; v.sdwen := '0';
if (r.trfc(2 downto 1) = "00") then v.rasn := '0'; v.sdwen := '0'; end if;
elsif lineburst then
if sdi.rhaddr(4 downto 2) = "101" then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
if v.sdwen = '0' then v.dqm := (others => '1'); end if;
when rd3 =>
v.sdstate := rd4; v.hready := '1'; v.casn := '1';
if r.sdwen = '0' then
v.rasn := '1'; v.sdwen := '1'; v.sdcsn := "11"; v.dqm := (others => '1');
elsif lineburst and (sdi.htrans = "11") and (r.casn = '1') then
if sdi.rhaddr(4 downto 2) = ("10" & not r.cfg.casdel) then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd4 =>
v.hready := '1'; v.casn := '1';
if (sdi.htrans /= "11") or (r.sdcsn = "11") or
((sdi.rhaddr(5 downto 2) = "1111") and (r.cfg.command = "100")) -- exit on refresh
then
v.hready := '0'; v.dqm := (others => '1');
if (r.sdcsn /= "11") then
v.rasn := '0'; v.sdwen := '0'; v.sdstate := rd5;
else
if r.cfg.trp = '1' then v.sdstate := rd6;
else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
end if;
elsif lineburst then
if (sdi.rhaddr(4 downto 2) = lline) and (r.casn = '1') then
v.address(9 downto 5) := r.address(9 downto 5) + 1;
v.address(4 downto 2) := "000"; v.casn := '0';
end if;
end if;
when rd5 =>
if r.cfg.trp = '1' then v.sdstate := rd6; else v.sdstate := sidle; v.idlecnt := (others => '1'); end if;
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1'; v.dqm := (others => '1');
v.casn := '1';
when rd6 =>
v.sdstate := sidle; v.idlecnt := (others => '1'); v.dqm := (others => '1');
v.sdcsn := (others => '1'); v.rasn := '1'; v.sdwen := '1';
when sref =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_SR then
if r.trfc = "0000" then -- Minimum duration (= tRAS)
v.cfg.cke := '1';
v.sdcsn := (others => '0'); v.rasn := '1'; v.casn := '1';
end if;
if r.cfg.cke = '1' then
if (r.idlecnt = "0000") then -- tXSR ns with NOP
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.sref_tmpcom := r.cfg.command;
v.cfg.command := "100";
end if;
else
v.idlecnt := r.cfg.txsr;
end if;
end if;
when pd =>
if (startsd = '1') -- and (r.hio = '0'))
or (r.cfg.command /= "000") or r.cfg.pmode /= PM_PD then
v.cfg.cke := '1';
v.sdstate := sidle;
v.idlecnt := (others => '1');
end if;
when dpd =>
v.sdcsn := (others => '1'); v.sdwen := '1'; v.rasn := '1'; v.casn := '1';
v.cfg.renable := '0';
if (startsd = '1') then -- and r.hio = '0') then
v.hready := '1'; -- ack all accesses with Error response
v.startsd := '0';
hresp := HRESP_ERROR;
elsif r.cfg.pmode /= PM_DPD then
v.cfg.cke := '1';
if r.cfg.cke = '1' then
v.sdstate := sidle;
v.idlecnt := (others => '1');
v.cfg.renable := '1';
end if;
end if;
when others =>
v.sdstate := sidle; v.idlecnt := (others => '1');
end case;
-- sdram commands
case r.cmstate is
when midle =>
if r.sdstate = sidle then
case r.cfg.command is
when "010" => -- precharge
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.sdwen := '0';
v.address(12) := '1'; v.cmstate := active;
end if;
when "100" => -- auto-refresh
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.cmstate := active;
when "110" =>
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
if lineburst then
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0011";
else
v.address(16 downto 2) := "0000010001" & r.cfg.casdel & "0111";
end if;
end if;
when "111" => -- Load Ext-Mode Reg
if (sdi.idle = '1') then
v.busy := '1';
v.sdcsn := (others => '0'); v.rasn := '0'; v.casn := '0';
v.sdwen := '0'; v.cmstate := active;
v.address(16 downto 2) := "10000000" & r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0)
& r.cfg.pasr(2 downto 0);
end if;
when others => null;
end case;
end if;
when active =>
v.sdcsn := (others => '1'); v.rasn := '1'; v.casn := '1';
v.sdwen := '1'; --v.cfg.command := "000";
v.cfg.command := r.sref_tmpcom; v.sref_tmpcom := "000";
v.cmstate := leadout; v.trfc := (r.cfg.trp and r.cfg.mobileen(1)) & r.cfg.trfc;
when leadout =>
if r.trfc = "0000" then v.cmstate := midle; end if;
end case;
-- sdram init
case r.istate is
when iidle =>
v.cfg.cke := '1';
if (sdi.idle and sdi.enable) = '1' and r.cfg.cke = '1' then
v.cfg.command := "010"; v.istate := pre;
end if;
when pre =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.istate := ref; v.icnt := "111";
end if;
when ref =>
if r.cfg.command = "000" then
v.cfg.command := "100"; v.icnt := r.icnt - 1;
if r.icnt = "000" then v.istate := lmode; v.cfg.command := "110"; end if;
end if;
when lmode =>
if r.cfg.command = "000" then
if r.cfg.mobileen = "11" then
v.cfg.command := "111"; v.istate := emode;
else
v.istate := finish;
end if;
end if;
when emode =>
if r.cfg.command = "000" then
v.istate := finish;
end if;
when others =>
if sdi.enable = '0' and r.sdstate /= dpd then
v.istate := iidle;
end if;
end case;
if (sdi.hready and sdi.hsel ) = '1' then
if sdi.htrans(1) = '0' then v.hready := '1'; end if;
end if;
-- second part of main fsm
case r.mstate is
when active =>
if v.hready = '1' then
v.mstate := midle;
end if;
when others => null;
end case;
-- sdram refresh counter
if (r.cfg.renable = '1') and (r.istate = finish) and r.sdstate /= sref then
v.refresh := r.refresh - 1;
if (v.refresh(14) and not r.refresh(14)) = '1' then
v.refresh := r.cfg.refresh;
v.cfg.command := "100";
arefresh := '1';
end if;
end if;
-- APB register access
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(3 downto 2) is
when "01" =>
if pageburst = 2 then v.cfg.pageburst := apbi.pwdata(17); end if;
if sdi.enable = '1' then
v.cfg.command(2 downto 1) := apbi.pwdata(20 downto 19);
end if;
v.cfg.csize := apbi.pwdata(22 downto 21);
v.cfg.bsize := apbi.pwdata(25 downto 23);
v.cfg.casdel := apbi.pwdata(26);
v.cfg.trfc := apbi.pwdata(29 downto 27);
v.cfg.trp := apbi.pwdata(30);
v.cfg.renable := apbi.pwdata(31);
when "10" =>
v.cfg.refresh := apbi.pwdata(26 downto 12);
v.refresh := (others => '0');
when "11" =>
if r.cfg.mobileen(1) = '1' and mobile /= 3 then v.cfg.mobileen(0) := apbi.pwdata(31); end if;
if r.cfg.pmode = "000" then
v.cfg.cke := apbi.pwdata(30);
end if;
if r.cfg.mobileen(1) = '1' then
if sdi.enable = '1' then
v.cfg.command(0) := apbi.pwdata(29);
end if;
v.cfg.txsr := apbi.pwdata(23 downto 20);
v.cfg.pmode := apbi.pwdata(18 downto 16);
v.cfg.ds(3 downto 2) := apbi.pwdata( 6 downto 5);
v.cfg.tcsr(3 downto 2) := apbi.pwdata( 4 downto 3);
v.cfg.pasr(5 downto 3) := apbi.pwdata( 2 downto 0);
end if;
when others =>
end case;
end if;
-- Disable CS and DPD when Mobile SDR is Disabled
if r.cfg.mobileen(0) = '0' then v.cfg.pmode(2) := '0'; end if;
-- Update EMR when ds, tcsr or pasr change
if r.cfg.command = "000" and arefresh = '0' and r.cfg.mobileen(0) = '1' then
if r.cfg.ds(1 downto 0) /= r.cfg.ds(3 downto 2) then
v.cfg.command := "111"; v.cfg.ds(1 downto 0) := r.cfg.ds(3 downto 2);
end if;
if r.cfg.tcsr(1 downto 0) /= r.cfg.tcsr(3 downto 2) then
v.cfg.command := "111"; v.cfg.tcsr(1 downto 0) := r.cfg.tcsr(3 downto 2);
end if;
if r.cfg.pasr(2 downto 0) /= r.cfg.pasr(5 downto 3) then
v.cfg.command := "111"; v.cfg.pasr(2 downto 0) := r.cfg.pasr(5 downto 3);
end if;
end if;
regsd := (others => '0');
case apbi.paddr(3 downto 2) is
when "01" =>
regsd(31 downto 19) := r.cfg.renable & r.cfg.trp & r.cfg.trfc &
r.cfg.casdel & r.cfg.bsize & r.cfg.csize & r.cfg.command(2 downto 1);
if not lineburst then regsd(17) := '1'; end if;
regsd(16) := r.cfg.mobileen(1);
when "11" =>
regsd(31) := r.cfg.mobileen(0);
regsd(30) := r.cfg.cke;
regsd(30) := r.cfg.command(0);
regsd(23 downto 0) := r.cfg.txsr & '0' & r.cfg.pmode & "000000000" &
r.cfg.ds(1 downto 0) & r.cfg.tcsr(1 downto 0) & r.cfg.pasr(2 downto 0);
when others =>
regsd(26 downto 12) := r.cfg.refresh;
end case;
sdmo.prdata <= regsd;
-- synchronise with sram/prom controller
if fast = 0 then
if (r.sdstate < wr4) or (v.hsel = '1') then v.busy := '1';end if;
else
if (r.sdstate < wr4) or (r.startsd = '1') then v.busy := '1';end if;
end if;
v.busy := v.busy or r.bdelay;
busy := v.busy or r.busy;
v.aload := r.busy and not v.busy;
aload := v.aload;
-- generate memory address
sdmo.address <= v.address;
-- reset
if rst = '0' then
v.sdstate := sidle;
v.mstate := midle;
v.istate := iidle;
v.cmstate := midle;
v.hsel := '0';
v.cfg.command := "000";
v.cfg.csize := "10";
v.cfg.bsize := "000";
v.cfg.casdel := '1';
v.cfg.trfc := "111";
v.cfg.renable := '0';
v.cfg.trp := '1';
v.dqm := (others => '1');
v.sdwen := '1';
v.rasn := '1';
v.casn := '1';
v.hready := '1';
v.startsd := '0';
if (pageburst = 2) then
v.cfg.pageburst := '0';
end if;
if mobile >= 2 then v.cfg.mobileen := "11";
elsif mobile = 1 then v.cfg.mobileen := "10";
else v.cfg.mobileen := "00"; end if;
v.cfg.txsr := (others => '1');
v.cfg.pmode := (others => '0');
v.cfg.ds := (others => '0');
v.cfg.tcsr := (others => '0');
v.cfg.pasr := (others => '0');
if mobile >= 2 then v.cfg.cke := '0';
else v.cfg.cke := '1'; end if;
v.sref_tmpcom := "000";
v.idlecnt := (others => '1');
end if;
ri <= v;
sdmo.bdrive <= v.bdrive;
--sdo.sdcke <= (others => '1');
sdo.sdcke <= (others => r.cfg.cke);
sdo.sdcsn <= r.sdcsn;
sdo.sdwen <= r.sdwen;
sdo.dqm <= r.dqm;
sdo.rasn <= r.rasn;
sdo.casn <= r.casn;
sdmo.busy <= busy;
sdmo.aload <= aload;
sdmo.hready <= r.hready;
sdmo.vhready <= v.hready;
sdmo.hresp <= hresp;
sdmo.hsel <= r.hsel;
sdmo.bsel <= r.bsel;
end process;
regs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri;
if rst = '0' then
r.icnt <= (others => '0');
end if;
end if;
if rst = '0' then
r.bdrive <= '0';
r.sdcsn <= (others => '1');
end if;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_off is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_off;
architecture imp of hwt_led_off is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '0';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
library reconos_v3_01_a;
use reconos_v3_01_a.reconos_pkg.all;
entity hwt_led_off is
port (
-- OSIF FIFO ports
OSIF_FIFO_Sw2Hw_Data : in std_logic_vector(31 downto 0);
OSIF_FIFO_Sw2Hw_Fill : in std_logic_vector(15 downto 0);
OSIF_FIFO_Sw2Hw_Empty : in std_logic;
OSIF_FIFO_Sw2Hw_RE : out std_logic;
OSIF_FIFO_Hw2Sw_Data : out std_logic_vector(31 downto 0);
OSIF_FIFO_Hw2Sw_Rem : in std_logic_vector(15 downto 0);
OSIF_FIFO_Hw2Sw_Full : in std_logic;
OSIF_FIFO_Hw2Sw_WE : out std_logic;
-- MEMIF FIFO ports
MEMIF_FIFO_Hwt2Mem_Data : out std_logic_vector(31 downto 0);
MEMIF_FIFO_Hwt2Mem_Rem : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Hwt2Mem_Full : in std_logic;
MEMIF_FIFO_Hwt2Mem_WE : out std_logic;
MEMIF_FIFO_Mem2Hwt_Data : in std_logic_vector(31 downto 0);
MEMIF_FIFO_Mem2Hwt_Fill : in std_logic_vector(15 downto 0);
MEMIF_FIFO_Mem2Hwt_Empty : in std_logic;
MEMIF_FIFO_Mem2Hwt_RE : out std_logic;
HWT_Clk : in std_logic;
HWT_Rst : in std_logic;
USER_Led : out std_logic
);
attribute SIGIS : string;
attribute SIGIS of HWT_Clk : signal is "Clk";
attribute SIGIS of HWT_Rst : signal is "Rst";
end hwt_led_off;
architecture imp of hwt_led_off is
attribute keep_hierarchy : string;
attribute keep_hierarchy of IMP: architecture is "true";
constant MBOX_RECV : std_logic_vector(31 downto 0) := x"00000000";
constant MBOX_SEND : std_logic_vector(31 downto 0) := x"00000001";
type STATE_TYPE is (STATE_RECV_CMD,STATE_EXEC,STATE_SEND_ACK);
signal state : STATE_TYPE;
signal data : std_logic_vector(31 downto 0);
signal ignore : std_logic_vector(31 downto 0);
signal counter : std_logic_vector(31 downto 0);
signal i_osif : i_osif_t;
signal o_osif : o_osif_t;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= HWT_Clk;
rst <= HWT_Rst;
-- ReconOS initilization
osif_setup (
i_osif,
o_osif,
OSIF_FIFO_Sw2Hw_Data,
OSIF_FIFO_Sw2Hw_Fill,
OSIF_FIFO_Sw2Hw_Empty,
OSIF_FIFO_Hw2Sw_Rem,
OSIF_FIFO_Hw2Sw_Full,
OSIF_FIFO_Sw2Hw_RE,
OSIF_FIFO_Hw2Sw_Data,
OSIF_FIFO_Hw2Sw_WE
);
-- drive memif constant
MEMIF_FIFO_Hwt2Mem_Data <= (others => '0');
MEMIF_FIFO_Hwt2Mem_WE <= '0';
MEMIF_FIFO_Mem2Hwt_RE <= '0';
USER_Led <= '0';
-- os and memory synchronisation state machine
RECONOS_FSM_PROCESS: process (clk,rst) is
variable done : boolean;
begin
if rst = '1' then
osif_reset(o_osif);
done := false;
state <= STATE_RECV_CMD;
elsif rising_edge(clk) then
case state is
when STATE_RECV_CMD =>
osif_mbox_get(i_osif, o_osif, MBOX_RECV, data, done);
if done then
counter <= data(31 downto 0);
state <= STATE_EXEC;
end if;
when STATE_EXEC =>
if or_reduce(counter) = '0' then
state <= STATE_SEND_ACK;
else
counter <= counter - 1;
end if;
when STATE_SEND_ACK =>
osif_set_yield(i_osif, o_osif);
osif_mbox_put(i_osif, o_osif, MBOX_SEND, (others => '0'), ignore, done);
if done then
state <= STATE_RECV_CMD;
end if;
end case;
end if;
end process RECONOS_FSM_PROCESS;
end architecture imp;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10/25/2015 07:19:02 PM
-- Design Name:
-- Module Name: controlUnit - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity controlUnit is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
ENABLE : in STD_LOGIC;
loadSourceSelector : out STD_LOGIC := '0';
addRoundKeySelector1 : out STD_LOGIC_VECTOR(1 downto 0) := (others => '0');
addRoundKeySelector2 : out STD_LOGIC_VECTOR(1 downto 0) := (others => '0')
);
end controlUnit;
architecture Behavioral of controlUnit is
constant INITIAL_STATE : natural := 6;
constant NUM_STATES : natural := 6;
begin
loadSourceSelectorProcess: process(CLK, RESET, ENABLE)
constant ENABLE_STATE : natural := 3;
variable state : natural range 0 to NUM_STATES := INITIAL_STATE;
begin
if RESET = '1' then
state := INITIAL_STATE;
elsif rising_edge(CLK) then
loadSourceSelector <= '0';
if ENABLE = '1' then
if (state = ENABLE_STATE) then
loadSourceSelector <= '1';
else
loadSourceSelector <= '0';
end if;
if (state < NUM_STATES) then
state := state + 1;
else
state := 0;
end if;
end if;
end if;
end process;
addRoundKeySelectorProcess2 : process(CLK, RESET)
variable state : natural range 0 to NUM_STATES := INITIAL_STATE;
begin
if RESET = '1' then
state := INITIAL_STATE;
elsif rising_edge(CLK) then
addRoundKeySelector2 <= "10"; --NOTE: THIS SHOULD ALWAYS BE THE VALUE OUTPUT BY THE PREVIOUS TO INITIAL STATE. IT SHOULD BE MANUALLY UPDATED
if ENABLE = '1' then
case state is
when 3 => addRoundKeySelector2 <= "00";
when 4 => addRoundKeySelector2 <= "11";
when 5 => addRoundKeySelector2 <= "10";
when 6 => addRoundKeySelector2 <= "01";
when others => addRoundKeySelector2 <= (others => '0');
end case;
if (state < NUM_STATES) then
state := state + 1;
else
state := 0;
end if;
end if;
end if;
end process;
--The initial addRoundKeySelector always has four states instead of six, since it occurs before the pipeline delay.
addRoundKeySelectorProcess1 : process(CLK, RESET, ENABLE)
variable state : natural range 0 to 3 := 2;
begin
if RESET = '1' then
state := 3;
elsif rising_edge(CLK) then
addRoundKeySelector1 <= "11"; --NOTE: THIS SHOULD ALWAYS BE THE VALUE OUTPUT BY THE PREVIOUS TO INITIAL STATE. IT SHOULD BE MANUALLY UPDATED
if ENABLE = '1' then
case state is
when 3 => addRoundKeySelector1 <= "11";
when 2 => addRoundKeySelector1 <= "10";
when 1 => addRoundKeySelector1 <= "01";
when 0 => addRoundKeySelector1 <= "00";
when others => addRoundKeySelector1 <= (others => '0');
end case;
if (state > 0) then
state := state - 1;
else
state := 3;
end if;
end if;
end if;
end process;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc\RAM_256x8b_0.vhd
-- Created: 2014-03-05 16:19:14
--
-- Generated by MATLAB 7.12 and Simulink HDL Coder 2.1
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RAM_256x8b_0
-- Source Path: hdlcodercpu_eml/CPU_Subsystem_8_bit/SinglePortRAM_Inst0/RAM_256x8b_0
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RAM_256x8b_0 IS
PORT( clk : IN std_logic;
enb : IN std_logic;
din : IN std_logic_vector(7 DOWNTO 0); -- int8
addr : IN std_logic_vector(7 DOWNTO 0); -- uint8
we : IN std_logic; -- ufix1
dout : OUT std_logic_vector(7 DOWNTO 0) -- int8
);
END RAM_256x8b_0;
ARCHITECTURE rtl OF RAM_256x8b_0 IS
-- Local Type Definitions
CONSTANT AddrWidth : INTEGER := 8;
CONSTANT DataWidth : INTEGER := 8;
TYPE ram_type IS ARRAY (2**AddrWidth - 1 DOWNTO 0) of std_logic_vector(DataWidth - 1 DOWNTO 0);
-- Signals
SIGNAL ram : ram_type := (OTHERS => (OTHERS => '0'));
SIGNAL data_int : std_logic_vector(DataWidth - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL addr_unsigned : unsigned(7 DOWNTO 0); -- uint8
BEGIN
addr_unsigned <= unsigned(addr);
RAM_256x8b_0_process: PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF enb = '1' THEN
IF we = '1' THEN
ram(to_integer(addr_unsigned)) <= din;
data_int <= din;
ELSE
data_int <= ram(to_integer(addr_unsigned));
END IF;
END IF;
END IF;
END PROCESS RAM_256x8b_0_process;
dout <= data_int;
END rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7410_tb is
end ADT7410_tb;
architecture behavior of ADT7410_tb is
component ADT7410
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
I2C_ReceiveSend_n_o : out std_logic;
I2C_ReadCount_o : out std_logic_vector(7 downto 0);
I2C_StartProcess_o : out std_logic;
I2C_Busy_i : in std_logic;
I2C_FIFOReadNext_o : out std_logic;
I2C_FIFOWrite_o : out std_logic;
I2C_Data_o : out std_logic_vector(7 downto 0);
I2C_Data_i : in std_logic_vector(7 downto 0);
I2C_Error_i : in std_logic;
PeriodCounterPreset_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
WaitCounterPreset_i : in std_logic_vector(15 downto 0)
);
end component;
component adt7410_model
port (
scl_i : in std_logic;
sda_io : inout std_logic;
i2c_addr_i : in std_logic_vector(1 downto 0);
int_o : out std_logic;
ct_o : out std_logic;
temp_i : in std_logic_vector(15 downto 0));
end component;
component ExtNames
port (
I2CFSM_Done : out std_logic
);
end component;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal I2C_ReceiveSend_n_o : std_logic;
signal I2C_ReadCount_o : std_logic_vector(7 downto 0);
signal I2C_StartProcess_o : std_logic;
signal I2C_Busy_i : std_logic;
signal I2C_FIFOReadNext_o : std_logic;
signal I2C_FIFOWrite_o : std_logic;
signal I2C_Data_o : std_logic_vector(7 downto 0);
signal I2C_Data_i : std_logic_vector(7 downto 0);
signal I2C_Error_i : std_logic;
signal PeriodCounterPreset_i : std_logic_vector(15 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
signal Threshold_i : std_logic_vector(15 downto 0);
signal WaitCounterPreset_i : std_logic_vector(15 downto 0);
signal I2C_F100_400_n : std_logic;
signal I2C_Divider800 : std_logic_vector(15 downto 0);
signal SensorValue_real : real;
-- look into the ADT7310 app
-- alias I2CFSM_Done_i is << signal .adt7310_tb.DUT.I2CFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the I2CFSM_Done_i signal.
signal I2CFSM_Done_i : std_logic; -- directly from inside I2C_FSM
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- I2CFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal I2CFSM_Done_d : std_logic; -- sightly delayed
signal I2CFSM_Done_a : std_logic; -- I2CFSM_Done_i and I2CFSM_Done_d
-- ADT7410 component ports
signal I2C_SDA_i : std_logic;
signal I2C_SDA_o : std_logic;
signal I2C_SDA_s : std_logic;
signal I2C_SCL_o : std_logic;
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
signal TempBin_s : std_logic_vector(15 downto 0);
-- I2C Master generics
constant I2C_FIFOAddressWidth_g : integer := 4;
constant I2C_ReadCountWidth_g : integer := 4;
constant I2C_DividerWidth_g : integer := 16;
-- I2C Master component ports
signal I2C_FIFOEmpty_s : std_logic := '0';
signal I2C_FIFOFull_s : std_logic := '0';
signal I2C_ErrBusColl_s : std_logic;
signal I2C_ErrCoreBusy_s : std_logic;
signal I2C_ErrCoreStopped_s : std_logic;
signal I2C_ErrDevNotPresent_s : std_logic;
signal I2C_ErrFIFOEmpty_s : std_logic;
signal I2C_ErrFIFOFull_s : std_logic;
signal I2C_ErrGotNAck_s : std_logic;
signal I2C_ErrReadCountZero_s : std_logic;
signal I2C_ScanEnable_s : std_logic := '0';
signal I2C_ScanClk_s : std_logic := '0';
signal I2C_ScanDataIn_s : std_logic := '0';
signal I2C_ScanDataOut_s : std_logic := '0';
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: ADT7410
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
I2C_ReceiveSend_n_o => I2C_ReceiveSend_n_o,
I2C_ReadCount_o => I2C_ReadCount_o,
I2C_StartProcess_o => I2C_StartProcess_o,
I2C_Busy_i => I2C_Busy_i,
I2C_FIFOReadNext_o => I2C_FIFOReadNext_o,
I2C_FIFOWrite_o => I2C_FIFOWrite_o,
I2C_Data_o => I2C_Data_o,
I2C_Data_i => I2C_Data_i,
I2C_Error_i => I2C_Error_i,
PeriodCounterPreset_i => PeriodCounterPreset_i,
SensorValue_o => SensorValue_o,
Threshold_i => Threshold_i,
WaitCounterPreset_i => WaitCounterPreset_i
);
TempBin_s <= std_logic_vector(to_unsigned(integer(Temp_s*128.0),16));
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
ExtNames_1: ExtNames
port map (
I2CFSM_Done => I2CFSM_Done_i
);
I2CFSM_Done_d <= I2CFSM_Done_i after 1.0 ns;
I2CFSM_Done_a <= I2CFSM_Done_i and I2CFSM_Done_d;
i2c_master_1: i2c_master
generic map (
ReadCountWidth_g => I2C_ReadCountWidth_g,
FIFOAddressWidth_g => I2C_FIFOAddressWidth_g,
DividerWidth_g => I2C_DividerWidth_g)
port map (
Reset_i => "not"(Reset_n_i),
Clk_i => Clk_i,
Divider800_i => I2C_Divider800,
F100_400_n_i => I2C_F100_400_n,
StartProcess_i => I2C_StartProcess_o,
ReceiveSend_n_i => I2C_ReceiveSend_n_o,
Busy_o => I2C_Busy_i,
ReadCount_i => I2C_ReadCount_o(I2C_ReadCountWidth_g-1 downto 0),
FIFOReadNext_i => I2C_FIFOReadNext_o,
FIFOWrite_i => I2C_FIFOWrite_o,
FIFOEmpty_o => I2C_FIFOEmpty_s,
FIFOFull_o => I2C_FIFOFull_s,
Data_i => I2C_Data_o,
Data_o => I2C_Data_i,
ErrAck_i => '0',
ErrBusColl_o => I2C_ErrBusColl_s,
ErrFIFOFull_o => I2C_ErrFIFOFull_s,
ErrGotNAck_o => I2C_ErrGotNAck_s,
ErrCoreBusy_o => I2C_ErrCoreBusy_s,
ErrFIFOEmpty_o => I2C_ErrFIFOEmpty_s,
ErrCoreStopped_o => I2C_ErrCoreStopped_s,
ErrDevNotPresent_o => I2C_ErrDevNotPresent_s,
ErrReadCountZero_o => I2C_ErrReadCountZero_s,
SDA_i => I2C_SDA_i,
SDA_o => I2C_SDA_o,
SCL_o => I2C_SCL_o,
ScanEnable_i => I2C_ScanEnable_s,
ScanClk_i => I2C_ScanClk_s,
ScanDataIn_i => I2C_ScanDataIn_s,
ScanDataOut_o => I2C_ScanDataOut_s
);
I2C_Error_i <= I2C_ErrBusColl_s or I2C_ErrCoreBusy_s or I2C_ErrCoreStopped_s or I2C_ErrDevNotPresent_s or I2C_ErrFIFOEmpty_s or I2C_ErrFIFOFull_s or I2C_ErrGotNAck_s or I2C_ErrReadCountZero_s;
I2C_SDA_s <= 'H'; -- weak 1 -> simulate pull-up
I2C_SDA_s <= '0' when I2C_SDA_o = '0' else 'Z';
I2C_SDA_i <= to_X01(I2C_SDA_s) after 0.2 us;
adt7410_1: adt7410_model
port map (
scl_i => I2C_SCL_o,
sda_io => I2C_SDA_s,
i2c_addr_i => "00",
INT_o => INT_n_s,
CT_o => CT_n_s,
temp_i => TempBin_s);
-- constant value for reconfig signal
I2C_F100_400_n <= '1';
-- constant value for reconfig signal
I2C_Divider800 <= "0000000001111100";
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
PeriodCounterPreset_i <= "0000000000001010";
Threshold_i <= "0000000000011110";
WaitCounterPreset_i <= "0101110111000000";
wait for 2.3*ClkPeriode;
-- deassert Reset
Reset_n_i <= '1';
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
Enable_i <= '1';
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after I2CFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until I2CFSM_Done_d = '1';
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after I2CFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after I2CFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
entity tb_slice02 is
end tb_slice02;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_slice02 is
signal di : std_logic_vector (7 downto 0);
signal do : std_logic_vector (3 downto 0);
begin
dut: entity work.slice02
port map (di, do);
process
begin
di <= b"11_10_01_00";
wait for 1 ns;
assert do = b"10_11" severity error;
wait;
end process;
end behav;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.my_lib.all;
entity mux is
generic(
size:integer := 4
);
port (
s : in std_logic_vector(f_log2(size)-1 downto 0);
input : in std_logic_vector(size-1 downto 0);
output : out std_logic
);
end mux;
architecture arch of mux is
signal y : std_logic_vector(size-1 downto 0);
signal z : std_logic_vector( ( size * (s'length+1) ) -1 downto 0);
component or_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
component and_gate is
generic (
width:integer := 2
);
port (
input : in std_logic_vector(width-1 downto 0);
output : out std_logic
);
end component;
begin
ORX: or_gate generic map(width=>size) port map(y,output);
GEN_REG:
for I in 0 to size-1 generate
z(I*(s'length+1)+s'length downto I*(s'length+1)) <= (s xor std_logic_vector(to_unsigned(I,s'length))) & input(size-1-I);
REGX : and_gate generic map(width=> s'length+1 ) port map ( z(I*(s'length+1)+s'length downto I*(s'length+1)) ,y(I) );
end generate ;
end arch;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 16:17:41
-- Design Name:
-- Module Name: output_queue_overflow_check - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: this module checks upon a request if another frame can be accepted from the switching fabric
-- No accept uppon a request will be returned if either the FIFO is full or there is not enough place in the memory
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity output_queue_mem_check is
Generic (
OQ_FIFO_DATA_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_MEM_PTR_START : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
req : in std_logic;
req_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
req_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
accept_frame : out std_logic;
mem_wr_ptr : in std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH-1 downto 0);
fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
fifo_full : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end output_queue_mem_check;
architecture rtl of output_queue_mem_check is
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
signal debug_rd_reg : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_wr_reg : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_mem_space : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_length : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
begin
-- upon a request signal from switch fabric check if the frame can be accepted
-- accept_frame = req AND (fifo_empty OR (NOT fifo_full AND (mem_rd_ptr - mem_wr_ptr >= req_length)))
-- mem_check_p : process (clk)
-- variable mem_rd_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
-- variable temp_mem_full : std_logic;
-- variable temp_accept : std_logic;
-- begin
-- if clk'event and clk = '1' then
-- if reset = '1' then
-- accept_frame <= '0';
-- else
-- temp_accept := req;
-- for i in 0 to NR_OQ_FIFOS-1 loop
-- mem_rd_ptr := fifo_data(i*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto i*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START);
-- if mem_rd_ptr - mem_wr_ptr >= req_length then
-- temp_mem_full := '0';
-- else
-- temp_mem_full := '1';
-- end if;
-- if temp_accept = '1' then
-- temp_accept := fifo_empty(i) or (not fifo_full(i) and not temp_mem_full);
-- else
-- temp_accept := '0';
-- end if;
-- end loop;
-- accept_frame <= temp_accept;
-- end if;
-- end if;
-- end process;
mem_check_p : process (clk)
variable mem_rd_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
variable tmp_mem_wr_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
variable temp_mem_full : std_logic;
variable temp_accept : std_logic;
begin
if clk'event and clk = '1' then
if reset = '1' then
accept_frame <= '0';
else
temp_accept := req;
if NR_OQ_FIFOS = 1 then
mem_rd_ptr := fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
if mem_rd_ptr - mem_wr_ptr >= req_length then
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(0) or (not fifo_full(0) and not temp_mem_full);
else
temp_accept := '0';
end if;
elsif NR_OQ_FIFOS = 2 then
if req_prio >= high_priority_border_value_reg then
mem_rd_ptr := fifo_data(OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START);
tmp_mem_wr_ptr := mem_wr_ptr(2*OQ_MEM_ADDR_WIDTH-1 downto OQ_MEM_ADDR_WIDTH);
if mem_rd_ptr - tmp_mem_wr_ptr >= req_length + 4 then -- + 4: memory is alligned to full 32 bit words when using 32 bit fabric width --> actual memory space is max. length+4
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(1) or (not fifo_full(1) and not temp_mem_full);
else
temp_accept := '0';
end if;
else
mem_rd_ptr := fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
debug_rd_reg <= fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
tmp_mem_wr_ptr := mem_wr_ptr(OQ_MEM_ADDR_WIDTH-1 downto 0);
debug_wr_reg <= mem_wr_ptr(OQ_MEM_ADDR_WIDTH-1 downto 0);
debug_length <= req_length;
debug_mem_space <= mem_rd_ptr - tmp_mem_wr_ptr;
if mem_rd_ptr - tmp_mem_wr_ptr >= req_length + 4 then -- + 4: memory is alligned to full 32 bit words when using 32 bit fabric width --> actual memory space is max. length+4
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(0) or (not fifo_full(0) and not temp_mem_full);
else
temp_accept := '0';
end if;
end if;
end if;
accept_frame <= temp_accept;
end if;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: TUM CREATE
-- Engineer: Andreas Ettner
--
-- Create Date: 10.12.2013 16:17:41
-- Design Name:
-- Module Name: output_queue_overflow_check - rtl
-- Project Name: automotive ethernet gateway
-- Target Devices: zynq 7000
-- Tool Versions: vivado 2013.3
--
-- Description: this module checks upon a request if another frame can be accepted from the switching fabric
-- No accept uppon a request will be returned if either the FIFO is full or there is not enough place in the memory
--
-- further information can be found in switch_port_txpath_output_queue.svg
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.std_logic_unsigned.all;
entity output_queue_mem_check is
Generic (
OQ_FIFO_DATA_WIDTH : integer;
OQ_MEM_ADDR_WIDTH : integer;
OQ_FIFO_MEM_PTR_START : integer;
FRAME_LENGTH_WIDTH : integer;
NR_OQ_FIFOS : integer;
VLAN_PRIO_WIDTH : integer
);
Port (
clk : in std_logic;
reset : in std_logic;
req : in std_logic;
req_length : in std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
req_prio : in std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0);
accept_frame : out std_logic;
mem_wr_ptr : in std_logic_vector(NR_OQ_FIFOS*OQ_MEM_ADDR_WIDTH-1 downto 0);
fifo_data : in std_logic_vector(NR_OQ_FIFOS*OQ_FIFO_DATA_WIDTH-1 downto 0);
fifo_full : in std_logic_vector(NR_OQ_FIFOS-1 downto 0);
fifo_empty : in std_logic_vector(NR_OQ_FIFOS-1 downto 0)
);
end output_queue_mem_check;
architecture rtl of output_queue_mem_check is
signal high_priority_border_value_reg : std_logic_vector(VLAN_PRIO_WIDTH-1 downto 0) := "001";
signal debug_rd_reg : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_wr_reg : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_mem_space : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
signal debug_length : std_logic_vector(FRAME_LENGTH_WIDTH-1 downto 0);
begin
-- upon a request signal from switch fabric check if the frame can be accepted
-- accept_frame = req AND (fifo_empty OR (NOT fifo_full AND (mem_rd_ptr - mem_wr_ptr >= req_length)))
-- mem_check_p : process (clk)
-- variable mem_rd_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
-- variable temp_mem_full : std_logic;
-- variable temp_accept : std_logic;
-- begin
-- if clk'event and clk = '1' then
-- if reset = '1' then
-- accept_frame <= '0';
-- else
-- temp_accept := req;
-- for i in 0 to NR_OQ_FIFOS-1 loop
-- mem_rd_ptr := fifo_data(i*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto i*OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START);
-- if mem_rd_ptr - mem_wr_ptr >= req_length then
-- temp_mem_full := '0';
-- else
-- temp_mem_full := '1';
-- end if;
-- if temp_accept = '1' then
-- temp_accept := fifo_empty(i) or (not fifo_full(i) and not temp_mem_full);
-- else
-- temp_accept := '0';
-- end if;
-- end loop;
-- accept_frame <= temp_accept;
-- end if;
-- end if;
-- end process;
mem_check_p : process (clk)
variable mem_rd_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
variable tmp_mem_wr_ptr : std_logic_vector(OQ_MEM_ADDR_WIDTH-1 downto 0);
variable temp_mem_full : std_logic;
variable temp_accept : std_logic;
begin
if clk'event and clk = '1' then
if reset = '1' then
accept_frame <= '0';
else
temp_accept := req;
if NR_OQ_FIFOS = 1 then
mem_rd_ptr := fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
if mem_rd_ptr - mem_wr_ptr >= req_length then
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(0) or (not fifo_full(0) and not temp_mem_full);
else
temp_accept := '0';
end if;
elsif NR_OQ_FIFOS = 2 then
if req_prio >= high_priority_border_value_reg then
mem_rd_ptr := fifo_data(OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_DATA_WIDTH+OQ_FIFO_MEM_PTR_START);
tmp_mem_wr_ptr := mem_wr_ptr(2*OQ_MEM_ADDR_WIDTH-1 downto OQ_MEM_ADDR_WIDTH);
if mem_rd_ptr - tmp_mem_wr_ptr >= req_length + 4 then -- + 4: memory is alligned to full 32 bit words when using 32 bit fabric width --> actual memory space is max. length+4
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(1) or (not fifo_full(1) and not temp_mem_full);
else
temp_accept := '0';
end if;
else
mem_rd_ptr := fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
debug_rd_reg <= fifo_data(OQ_FIFO_MEM_PTR_START+OQ_MEM_ADDR_WIDTH-1 downto OQ_FIFO_MEM_PTR_START);
tmp_mem_wr_ptr := mem_wr_ptr(OQ_MEM_ADDR_WIDTH-1 downto 0);
debug_wr_reg <= mem_wr_ptr(OQ_MEM_ADDR_WIDTH-1 downto 0);
debug_length <= req_length;
debug_mem_space <= mem_rd_ptr - tmp_mem_wr_ptr;
if mem_rd_ptr - tmp_mem_wr_ptr >= req_length + 4 then -- + 4: memory is alligned to full 32 bit words when using 32 bit fabric width --> actual memory space is max. length+4
temp_mem_full := '0';
else
temp_mem_full := '1';
end if;
if temp_accept = '1' then
temp_accept := fifo_empty(0) or (not fifo_full(0) and not temp_mem_full);
else
temp_accept := '0';
end if;
end if;
end if;
accept_frame <= temp_accept;
end if;
end if;
end process;
end rtl;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library util;
use util.types_pkg.all;
architecture rtl of cpu_l1mem_inst_cache_replace_none is
begin
cpu_l1mem_inst_cache_replace_none_dp_out <= (
rway => (0 => '1'),
rstate => void
);
end;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END HLS_accel_ap_fmul_2_max_dsp_32;
ARCHITECTURE HLS_accel_ap_fmul_2_max_dsp_32_arch OF HLS_accel_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_fmul_2_max_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_fmul_2_max_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_fmul_2_max_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.0
-- IP Revision: 7
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_0;
USE floating_point_v7_0.floating_point_v7_0;
ENTITY HLS_accel_ap_fmul_2_max_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END HLS_accel_ap_fmul_2_max_dsp_32;
ARCHITECTURE HLS_accel_ap_fmul_2_max_dsp_32_arch OF HLS_accel_ap_fmul_2_max_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_0 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_0,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF HLS_accel_ap_fmul_2_max_dsp_32_arch : ARCHITECTURE IS "HLS_accel_ap_fmul_2_max_dsp_32,floating_point_v7_0,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF HLS_accel_ap_fmul_2_max_dsp_32_arch: ARCHITECTURE IS "HLS_accel_ap_fmul_2_max_dsp_32,floating_point_v7_0,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.0,x_ipCoreRevision=7,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=1,C_HAS_DIVIDE=0,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=2,C_OPTIMIZATION=1,C_MULT_USAGE=3,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_0
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 1,
C_HAS_DIVIDE => 0,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 2,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 3,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END HLS_accel_ap_fmul_2_max_dsp_32_arch;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
J7WA7jme3+I19NsPf9M+Hwgwjif117fG+SS/1lPz2YSnAcnIAvNxWqiI726MbtIpQaTNrw1jmOBw
c/UqMzGGXA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WpkCtItYKx/eDqw+UYeRmjrmL2mI5Hoa+YtZRmfPmT5sRLTmRtU7/cUwQiFGy7CTe4aH6MWqC6cl
7yOvMENd/saYaA6CBzjl3bmlQFDQm85ABIvXfAZeXd/bJICw697f+Gp+XDeqGEojeiWpNRwU64lV
wrDc4Q2vkGeh9QI57vE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JMfAjM3enGAj056QPtT14iolBO1T4zxTCtOBki1tkxag0lSir2+mNI/TstrYDMMz+VmoRABO7mG3
E4cyMU4DD1gxa38kFX3Df+y1G6aRoKyhiMH+64JKw9JL46nEHIJOGDEPVrzys4ji/rAcrk+k0ZXU
+BNAptU3RUsEcOB76s54iQVzy3kBSJpMIPgROvcP1r3MO8cIWwwnXwhw1E3NYjdB4x4x28ROQOtM
4aDXOjnVqxltCBSV3c0ejPBRt48MD9nr/NSRVWgjS/hvMP+4BvgWbtA4WpqMqpIi0WkUe+1jnjRK
wOXTKLIQFC/BgXFZ8wCjpmoXB3EaQHWgUTJq6A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xi9FAzd9lUubrlRz4dhDTI4iRyCUPFdcb/aw+H792fSTh+zLCxn5UhtCbP1ODFFxarcJ+MJOP2Zn
+D5JiGjeYLr+BhL4vPssfuWrwy9ZskNkrYlO4+aINK6YeBevOCHzcs3XCoH0oEtDoTX4+iIx3/tD
FUbYXexUE4kxizzBtKY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oq7lhuu2wC7aiGW96HYOfmmfOgDjHG2Qplf9OKcCdkzdYU4+KWhq3a0DuxlG8W7Rd4zGxOBB8KDi
My605jaSXXpuwZd3EOVEbvkbwmD7d5sYpfI/M11YdU8SD1rfe8TRYvis5OZr1zX9o2JsRGTUKl29
l+YsS+J/AZcYBlBelH69sokhM4+JdEbrUAAZj56hLth20QfRMXA1TCZmPp4RdMr8OO8wUEI8/00Y
+dyfXfBQHeZ2hIbRiIgNoAIn5WzlD6oLu2kSV9lZZ8lObO3DVc5rUA5TI92ltjJ2+QHZE15VJsPA
6EH3OhmfTivI/7qVVJaEnf6Fnzk98+CbItIpOw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20336)
`protect data_block
kAa1BqulofOCu73DntWHGpwFbRBeH6gxRXCLgZtk0widaQMD7ZW/DQZMVzdD+x2lT/bTpx8PNo0h
XbV7vZa2J6r+nfcUy9n3pIP3NuWbfn1zHSLzLVwHEP85WIP5IkqVZ/49Q/LljamMmi+mkCCy5W9f
rYtsWjcubTN7O3309+iN1CyFFaxZxvS9jwCdP71eDklGUnW2p5FLgJKxvtgP/8B0FVXQ08a41d1M
14cIt2ePFTZtlk1n0kYmQ3jcXbheCixGrpbpzicAZucwkWbtWN1IoS0zX+ZG/gX6Z75/vFatpGc7
qsm65NlhXqVn54VLs//IWPkEP/IOXUn2kFpxpq03wfRDfJ7GHy8QngQAIfquUAoH0NWn57nMxw20
XF5hMvdBEDjrCyN4WG7FY37txUaJ/WNFpBCAgNU2O1a3AVH7oxoO2N4UJL6N3h0fxtM+/Qr5hahR
h5atCScsrtR/2Ryg7q4ytsmnDirLUbFfjc9jPx/mb4Cc8M45+zuDWIokCSgjLkn5I7XUdx578U2W
cjVsbhS3cn7n4uEgxeSLhmscmDG937eg75PoOu1vsCEnZVW3eOnmWWO7fMdawjlG4JS47xAVuvfs
X95E4nL4/7u72JfLTeaxg374XvHH3o8wx2Te7k7D240zS4MDRgiR3Or7vJTMTQZi71geVg/xRmOk
Gu2Aw/+nvrP1n1WaB3BQa2jbzkcb2U58z3DLncoR6/HTT2CK5tuKPi0vJo9k/bz7wHYp6vVutwgI
yVyim+3yjCQI6e8xOi1+vmx6lTf/qjhe7Kwj4txJOVvgZ3ln0VfVY55PL8sJb0Zm3hcRHOZTp8gv
KGFesxArpGo6ywD2HGMRostUSycrser2wjbuD3V8Q1d7b5b9B/svupByQppSina0RrBEj+Oo+/Hz
FN9kWY4FtnH6FgIj/BJ3qtW6yD6BZWBrUdIjzMJiMeiue6EOO2/ahg41HH4UmYxuxzS+iTjGhyyO
+ZfvCZMsoBg+jbzflFIN9IH/RRVFNHRWPEsupud45SFlXENnzZnrI3OWLwaCvm21MYAlzBRN+Q1A
eQTfxrapwex07PhIEWtupS9S0cEEd9nzP8iLC41my1zIhy1qUF4KVAPDFA+BJfpiCvG8Fe8WIru7
tXVSFERhFzLFVX4zo0jfGQjQnZw1Wqh/4lEz1ps9XtwwQfwnhH31/wojxEWQ5kw9gPItIt0SGlrk
G/fmoyzvuBjIuMKCFZQdb5UL7cJvIznGIfQiSYP6BVpKWUyfZqXtuw+UJ8AhwwxCsXyooQUo0Lpk
7Uu5CxzQAlzUDb8e+VEpWB/lhVM9HaC7ircnHc06CmMUojUYlYbM7IBC/QpeuKxeAPzd+jm8S4fx
Bg2NHSU0wS1iyDAiCvh6KcC0XLGtd1JQpRlWHNVxCMirbAWgCvslJRzHL9FywFe6QFg/yYj7VAGM
j50tVsNDtktAjarMQHVlA9SBfP3tCXj53/3u8OkIwlIGR0d2QLiOPEYWhmtIofYqG/9GcWCKFRvr
YQPvKidrmcpVGIxK9/0F1oK4gk52+KxZuX+OCYUFxF2T0nNvVjKqyjEGA6GrzLBXUQnaadZi6oaA
Cu4ORVti8BkUtEvv4WDx1ne4vKOor0zJ9gi/Ci7vDPoOxL1EvgsZyJqmrhVD7FfMGVI/UixvxZLS
oszbYNeaVWjBsKizhBs+/wVevvPGFaL+rAmPxlPGuunUQ7K/uazyPawAMQTDufxq07lHW2dqr8gZ
qew4zEX1T0FCGZz/+trC66RBAYmUz47RvEnl+6bq7aRsFtpoImEPffqS5vIAO2/vtMweCLptyxkf
drIr4jugThhRZ4JvBWXkxx9a3qDkFMSogvWowYXSdoo5iZuwIv6oCfYmJ8ySatgsHIydszE3/G8W
/3cBLomY9kk4H05+nDhbY1Waq7sr2ajJxKC02BSraC+8VfIJPEtb58ieCfWUmXnzUj5VsqxIpgtj
904qfRIUfuuD96DznDCl4tvsLyo9it+oPSaEYtl/67uCFYUY85/iL6G1uvApxsyWlNS0jVmYQbAZ
aHmQpzeHcSldq0lmuYeXuGxYfnjSj0Du6rq/T2+sO8us8bIvuf3bcDmyJ+ulIQQFmHRbs0kPs4qh
ZdqC9YDBN105NeNA/ibE5W0s/UkC/yxF46tKNlXcSK4w2EzLXPXPaF8s1/tu8yTyhYh12CsyGmfI
Mej2mjZQ981M/r/sl6BZDICWV+H/5OinC0wbwXBOjXhyviIbCeZb4Qb3zlfjZqYzQv0T+MNEfPQi
bBn1QDRW0zw5AobqmbpEY++QCo8IVtuXN/uxYZQv5BpM2cfpMSKGEoAKKQEEpHaVCf2v+D2hRilY
LFM7lt6kWoC2TV9BCiCdJ8KHdOpyvOntrqRmoQhdICk/44cX1IqSJneTL7GMxJBIvEUbRRKFTeG6
z1aMSUQ7V6gm4KNKN7nVN+O+x9BAHQENTwRTwJH3V56FYnkC38qC0pG3C9DzAJulNIVpVPIHZ0Yi
vWIg2cG28rg2z4MNwj/LvlwJETxi/6bd0t34VfsC1wohaa/lu4lLaxr4OTofJFLj60XKbYeU0XRJ
KMbFwPlm6dy2ISra3N04Z+V3JlUYHrX/NdtWyG/He4jQ5R4hkIdDjC+Kpgk4kEbSPKVh5ZzWKRTW
U2fj2B5jAkg7ha5NKvvC+kiJxw4rTwXzlWrmDKqS1I8GHWvTbHiogMqoCprMDDdE4V13a/iMv+Fb
cW+uAvPvVFLhlHkldBfoHIm7Np54u6lq9uNmYLto9VaIpDsN2/vJ0fie0bblpKxHyzZ7koYXpixF
Qpa4rS7ptQFUtNBp5M9EvOjgZRt+IB/LDqXGaB5NJhCzYdPAWaSAo9KfDEEIMxod0+U00Quj2sh2
2mdizs+m5hO/OygsC6rNmkQtHU73Rh8mIvoY9HxHBo/e7KPdF6UKsM04u+GqzER7aXWV3tbwoiEW
PHr1MMPLnlcCSvIrcZ0YeL+1jpBHFnQX13OK/OTgylnlZOB2ezV4oFczrwfrXaPzsR9PaShlfbfb
gYJE1aiB3tbcL5tUPsgLMbHLYnuCV1urlynYYyCNIuXgHx75doFRPHeX1Iv5SpmSQd/F9i/BFFmy
et7u+J5jTsP1CRrHTDf3MhKZxecTW5OOsQbVZYIE0hYqOQYpdg1aSYsZ5KrU8o3cBHOPFULECUOA
dxjQnZjx3q0vWU3vmBzN8FWBg7RPbhtTC6L1Vz3/pWsCCS8gRInVrLucXVg0Psq5meZYEcbYEhxX
Xtsf/i30Kn7/pkXqrAG4gXGDBKYuNDCon6cFXTtGPJ74GxbMn/l0QqRJRyE7yzDytLk3PztBumgc
5D+7ZJA7vffBBYDfh5VcGXS/MObFXOb5l9wjhfoG9d2pd8MjDn/n+IX2TcyrvqHxJOWJctlDLJAt
s+eqbiTGs/cEYHirwYq/R6b5FGKFm62iOPhgqPIq4xsJUmvYlr62WnazggMl8mBMqRiO+eAE7vRB
gU8R5UzbLRUZiqdLevIgYYZwDG/uGeTC7N7ivqfjdSRO+68ZpoLcrWZhK8RXYduBU5WKqkmAoclS
uPTOdMN09yjA2TwaHN0GsrmhoQDocmdqz5gc58uzaa6+IVlFzmLe45PPDuc9+gcWU6ysR/5strUk
Q/i8jbNCWtj2csdJBdWmc+ZKw6fFhKL5IO37XKJYg3TRb+lj2ET7xt06M/dZX+dRvEeidzNPiBhy
mWNIxFoDD6zBv+rZtDxgQnFAYqxhNOY3L7V2pQ3JrOVn0+0wXbv5O4l0ZBNo/OJ8zmMFbpdBZ7zj
QwZde0TU4Ur+O3azpQCRIyPrjI4yKrucQO+ogV2WPW8SVPX/pyEzSNj7usWBfigqp+9P3+MO7b9M
wtD4xq87r3fmw2Vhdyg7q0fiqh33EdOpy4JPFG+sXhyA8El0UjaPif8KaxJG6H/QtXp2+OadEtO/
IrHgxc07oYjQItnTXv6wvzdbQX/aVIGJoSZ2LhTQdUd7dMsqXFlY6Dm2dggZR5m0S+4BNXEz66FL
UjCckoPcPKNqhsHVHRBQbM/DYdKJxefWptyyZk8gwm6QWeFOjTjB0VHvHEUSutP2jAlWU96ir6ZE
P9ARKMMJqZ43B+q4/zaowD0V9JK3kZhSx++w3gxCtfYStWbkn8hxlap977wiiLEN9hR19JJcumFS
Ks00sTY2PPB3FHYDGy3ZTTuGAlNyACVAoqaKRj/8yR2ero/wBdlFygm2dCCUVUf5QSozkgQn6ZFn
uBsqyGSAQAgAN5XZM4tY3aBicMaEOzxBqe9a+xQ8+uE0akER6Ps24JkfpFE+ZRufqtfNhIqt0B0y
F9Hwopqmy24IIqtT0hNel+NbEDujKMr+jDmOJM/xh4CYdUYryXbORc9yztTwx6HzfcfCPKHeiBIG
CBExZiDFXHem3gB65NvqRjYm8Ce1NyH3EpAibUZaVKNgPUD3W5YOlj/NGB+eNzbZsNXQZHKGAObv
Ftnr8vLNmpQPhan3a2QbShyd2Z1HLp8pfyGmxZ34uQY8YGxUrJ6R5Rp/gFt6iZ2Dl5jeq8FN5zJh
8IVktIldd2ZNlgdDJRzylHmV/Mz1NvW1byAanvSKJR7SABdMRHfjdScNiQNUAfhEPAyI9QbA99h8
GTcE5/9Dfk/9yKZ9CNNytY8wsIRWEN91sHQJuc899kc7yezxAfXTRSY6jpRBJPvhSEuWo6G5RUKP
bMaMIVWU1CIAdRppbAa1QI9y9WEs5/X2iCVf7PlGuU6b65ygGRcozw7mGStSsRVK2Bv7onC2FRMm
nDCO7K4zAnJI9Vj7jYkK6Is3DAbWp29tb6wZB4ozfHLXbgJI6Xb9JAV8B3FHV7caRZh5yc+dgCb6
wRQUge+bCx8LJGPFvsc0I60BfsxhdnJ+k7t0i60m6sVh703LgP8OxrJZDPTMYCkd6n9TMRNLZsxM
ECcAdT8ICjurRbkT1UgfMJTboHRer9dfyHdD+a4MRiLYyGWU35hRMMnQJx9MS7w+is6adncxDyn6
IQ07n+8gU6oRpig0mvR6HbitPNHazEMCXOKatU1kqb0XIOMvKSyokxSI9J0WGqi0Nclm+S3OIe9I
fcKxVUtLTrBT5twifP1/mSlGpA/3IQpF5GwY4XVfi25HvtJr0bvAZo6S1z/vfyOwmQdfR6Ti2X+1
uO4iX38qMbuZGr/fZ2FSneHh9f6vSsTvZTST11O+PVmPRaXwE1YBXq5aGFg/GfU0H6OAevr882pX
drg6uO7+EXHMTqyLo2P9TIMyl8T45mr6OxgKUMiEvlD6Tc9Sga7GMe9YnD6INM2+QqvBvu24fH96
r9M1bVUs2yjwGNeIFXEiLwJKE/LcxRsquwOMwKmY2DwD4kzhfkmmdFB3ptxdPEF1AOpTFI+lTCBD
XG1QITeh4dvvjwiNrbNu56BJAKD9McdPaQjbVEZ5TbFMqLKyGzLor/BkZ+V+Y2pXg4CjVByIRRIt
COvXDMu3+j5GLpUcDWNBxvv7TOsUBhUWhfTPWkjOVt0BqIsMp5rwaL9SQv1MYlgfzaixBCLUm++4
aUN/wuQ0jkllyMBTNDDRPf+74xwLo7EhoP/YUa1BSQ3O5eDSy+aQoVQLN+HAvHORJ5Q2NpkzF9g2
p2wfZQb7SwDRuwgNkO5v8Ei4t31D8kSR97xmdcaW1RYVtgIgclWUt5QDHpHaObeFsXnF4mGwEcpJ
h7X2rugx2XrYrC0A/XwVuXB10B0T+3ootAWsL1rifssrrGo+eC3NUYo/tB2aWv5ne/a8RjG8e6wT
VNKnwrihm9/tiTJjYickOxlVj44+52suxa88jPq3tvu0wxLwaf/G4cC0EGgOH4NTagks1bNWwDH9
Dez34ROFZ5ARWFjiXkbwCptpLxDGa3wFGNssSPRJFUBivnce9HuPAV7wvte9C/jp/Jqhx2JLidDZ
RYPwFhHf6KrotcZtMYDtMjAK6Eum0GKFBAkMgOU4BtR/Zm375HVDVvkRGIq3XQ3ECSMI6fedD8GX
m7WTPm49U2cBDka8fZNmBs6sJs7jzyMbn6AGxLP523Rq5hHmnxo9XTWKbFWJ5CLwjoSfslDfs/IG
f04ctO6idUBy7gT0lspIxJ4e5aSxQPWLY4Ex2/j+TqoquM4iFZcIxQql4+fv/tCt9JnoFOHqFUCZ
CmvqYQ0Nix+KP5nizOeHHf7BxLkSLo/Z0fW3wJfiDICP/SpbMlCRSMsYC6bTGt/HB4tIbIY0c4Sg
VZPBdN6OPwPkdzwjrVZXWPFtpJnouVYFsusxAnZKqyFSa5fIPUUjD8zi14Y56GpHbT4O/+75n1IH
G1lwSVjcOVQ/zG7ZsVv5d+9XCTEzZal7wentzZwF4AK04OEw2NnwozR2/iBNxb9z0hcNvbJfOoiF
RRvqMOGRhj0Xq3k/RzfzHCyB764dq9MmokjcD017FI5EG9NIhhiSksTmkUEK66Z2V9uA7HNzE0+D
Z9cWZJqApmlZnVIGfxZ95HT7waiEYjOKDlPsR6gfYX6mdIaPV/XyksqS7WAOaX+Z3aLMdHWF8fk8
t49oxz8dO3WgFOqLrsgMm2920QJriSTNBYzYD4ZR2dyQNE1HLunFTmLgHARoniVJBo2rRE2VPbF9
gH0aCYuh/C+zn1n+YLRMvnKrkPVrTwtN+9vBL/4OPejCVvY47aodRc3GqIImdydk4QUp86co+2Od
RJQuE3nTfAfw4dPA/rvMMjfG5Og3wcGps/6FGJ92hJxLhU2ntcGrBwqy1sm1fhF7WIOK2qgQLXgI
2atng4seuEtwz8TibKSCW3rz91OJ5MowF8B/8jFZdzvjkcOEftRKoIFJQi/ZLXNp2CJ8pBPCFiFG
a8QvSON8WioF1QKWYaPLa5qBaWRwnG0ixBdrg8W2K1oHVYGnR+3W624o1hxKTMF9GfHBDMPk9918
TlsjHJ1fbozrLSFfC9DPnKIVRYBR8Hp4wmRoV1qV368DTxAUXkwrmOcbOoJjGMW7FRdMbW5dzDKp
XEJwIeNbenY5sbTfJeaygfrZqh3n77DFuJV+imQBAWJTcnUYQqSZXh5N5+bzLJQ6tC2b5VlcLtM7
W0bkf7j2X+o0PJPdSJ2ejIEWdvBKtjPmcNJf4qAdxjKWzBT+Kw+uWvhERwW6AYPyFfnX0TC/2YY0
vZPBo5hZrhtNYR64pyUIfBjl+5jYtBOXnqn1zgIfVLq2driekYA1seNNyPgCLMvF6gyvohzPe0kV
mtzHy4bwS0iFPZbWhlethomGNgL5YXgCffbSaPOqQY1OweUy/2kjDbS6wEfoBG+rkAHdHM5M4zSL
Xc1ReF7Jt9S1zentS5a5r74ZvdvhjFTfhXMDizeCpq1lhaka0JEpm6ZDAfLdR7i5Ra6QgjhIco0s
iVQLdTS24DJnGBfBSMWQ/Y49zdAdfL11kCggVWrCtrQGkMYoLhYQsh5/IY0X9gtvxL+e+sbCYQYB
P0jvreRQWMOowFv5Lql8AU/A+kRwnZk/phkZwt3xu1GeWcfUtxmUR3j19xW9NwvYLQJXwFBDxozV
eZHnIWt23781WuYOAXj7zwzErfBCjm3orsJxiUnyXh4flJI0yaEw5WrgK1/Hsv6a033/lOWqck8y
JiYSTz8IbOgT2Rv5COjsZT1KQQMl4H7Cj6MgkI8JvMLGU17LyO/9swRG8jcupxHXumg4pXb5Jm5q
LwRGVU+cdE0ycdfhDspDskGxu+XHi8Ra5S1CiFrewvVwgoXSr+GTUkjOTL1HwyO6E2nTotNpbZFT
LczJ73NNTRTHOM5FGGL9tVUUv9z9PlDu5fWk+lxtEOx9JBKKy8nAq48s/gwNEboX6psFQSUCYDEr
hd+EWR82x7SUjewS57pYIX6AVzsN7gUECvDPewzPnmQ+IB05KRDuAoBeyahh73SHcc5ffkYSuWd4
5ZsbXKOc4OGmFuIVm/x3EGQ3Si3l9STz4rKYHK5+T5frfYxiX4fs5OAWQNiJrXznTmPKDJCO4g9b
5xDCvpiHAi7j410JLQZEW5GTgkGRaIyH6QU/vovyNoti4iASgXDuNQD2h6EFGo059V5cD+eCk0JV
FHVbl1sc/xTvXcfQnGcMfh89IopyHtczZA+tKaICu9EzL5qbUJ8fEHx0+bcFIH3oWlK0vSngWVSG
Gu9gN3+x4F/LD0Qvp0ehymtGKpruwTpHNK+NoaB4jjWJ9GtJ3qS9ltmZzjYhln8wuonPAJdXSjtj
JNW7YPdr24OmNjxYJogRQFq50FS/CcFfThMr9iA9z4+s/MlLYtUT/EoU06CL8fnZf3HJkKHLxIay
xWyhtNsVMCNN8wLmBUQVOtVPJCAesGwChxvgsGcJ8DARuvgCBLm1LRTqA+QXLbqq+Wxrc1TddPWE
CCovZdIq9EXdm6KkkRuIJ6KJaY9f5WklYZP6q4i6ScAzsSksDb7hTwYWoEa/OyT7Kqn1Br6BtNSG
U21Fft9sS83Pads9lZoztUooBPcsRWqXIKcxm2Co9iHnjttdy0MSGD11Ojp0/qZc4V8thOMPNrqu
5YmnUR1x9wYKuLTa804oHMAV4tCHdfOmVLhdNc+jHsS+lM366cZuQkBN3EUfdcGvN3/mC8UkANES
0wiaJTapFL60cMoUiCh6wghBfFk/oqlzX4Q1DwOIZvqahzd6uGDHOhcOJLorHPKoxco9AkAg/qrv
sh7jf51BM1aQJb1A66MY1sObslaE93TsQ/D6UFTbQWzmdaa2cr6nTcmOWCiW/YbVZ0+amQDIv1ze
FIgRHb+tQNbgBPbqRGwXOtwOV13rJ8x8PkgrlXeq6CUfDgg+CLWUku4OzqiLXHH2f3nXzuDj38/W
Y1RUv9fJPXqzcHCSNMCZRhHIuvhia3zuvT7ZoBRIYXBSOIQMDjrXTFS6F9ZLKLcV1mXj/TxDkLf5
agHIKXItFZ3qUTfxVZPdZfkaLowAh2zmRhqg4TV1tCctg3DTXrs3TrXs5X6ErHAY3rRWEV8Nr2p4
6KdCogVlx1eC1gf7/OVAOsBzwt1zg4OsNO04EtrGK9nCZzl0wCEz6q8Yythr0ahgftQjDm41y5By
YyzBgkCriXc9iJHJkGKYB+Lg3jntHLIzkMFbxykZcC05mTUDXu8KmcBUgxTRdb6PlzbhxkkwMaeX
iRZWt2H19TYV1Ms3GMvFwlZAJRTUD4Um+e8oQYgbs2sgMpqvSDM02TImeDvYdDRcyx9D9xTzJf/+
YQA/foROLu4UwpkULNrho0rfmHfarP58Y11QJHED61e8aBnbJ2uL0kPiQUOzEwrD8Qrj2gUvz5Un
s6MRBMQ/rtHyfOXAb3RO5ZpJvMk0Lmp17MtXFyVxXm8LJfg8fVP1qSRmU0mNy+LQiptrBxO8dI4p
0d26uNZj7Ga02w9G8TrBYvrbguXMbtP8ur19G7ec8WuLhPeq6cLQUVCcoz/skq/hIvTFHnVIkCP3
KLhkeLYhixcveeaOH1q8C9xMJQCFa3PNBIK4L/ddkRU28nQhSGsDSJMh0EQkMO4dwpvp2O1z6aYU
2/LuFcdnHTGVNuD0aaZZLA6MMbiL1oC3a7Omy8PRerio11aqp5MPADPwbYUUk5b/uYrZ5dE9R59m
CldGEq6OYeRDgEGkEDn/tAzEEgR1o9cgP2zFEyGsBpa0Ivm7unRydkKxax3VGBEgAdoKZfIeh+Cr
hDlLebblAId1DGNxv9yGi1tQVkqLo6N74oti2xuHxo8+g9p938pO8jCZ2GCvyZ2CdYswO7aM7D86
orlDz83VLnJ4recfmq0ycsFg5kdA3Y5hbU+zAY+IWEZQ7u698B2TbEYjcoB2OO0zTjg9PcXy7f16
tOkRovN0eRDI4a4OgPDRqSJHXwj4JDn8ixfqL2cpp9Cou4ODDQvmATmndct4WxLMypFWDT1QfwjI
qNI8GtFMeIm8vwhlkIsSTechXL4Cm3DOnVrfwoCfKCRMAH5BR1/A9vKieQ4tgHbWS0IytN6o6Ub/
uXVMljEq2VGliJTmGGQq9DBjnjDpW/A0ei/ujPZr7fgYozzSzsWJKIH/Ptjix4hoQGJjH9ku5UUY
np+22q3lwytDOSp45NU7kw6W/lIqJwJ1LEPbOuAPdEhFqaycPHNyboKg3h5Ob1ZxhTbinyeX20N9
ZE6sc21jI/Fb2tuGpl+nj4BxVZc18RG0Jz5MOeFhjmrDkug0+4MRKLCWKMU62NtkJOZ0O9VCYS+i
VzpPVkdXZ0hTErUXMbp8R+xkm4uRYwXjEZTo22sgHwTK/ski8lGBDV5/RyD2RKWOm8Xn31URCeUm
IElRhyQ0aRqb+wlz0bDG01h0SQ5zAqONLXAkn2saY9pVJNP5uOjHvXjtj7HVc9mzyXz1oN1vNcLB
fnC/b2dzZKFlAtVKvOZppxMaud/fcBIZAZYKcmq7kPxybKnoX0TQJvlpig9nJg1gLnKMFgN9+/rP
as9YgvtJZy49sf2TH7A0ac3is/G104ubnO8zHESRScbEcOujKHIo4b0nn23TXBpbhNQMushsAejR
4sYg1snkThDLlBqqhiBjQYlHjrlU3EOB2o0Cr1RtVIZ5OWm6Ndy/6IRQQcxSuiNIDjUW0lbi9SP7
Y8wnu/ZwNMht4v37Efe3PB1F/ThIuHZ6e71j89ShFUwdx9GAVQOwA9AbUSfsKA/YWbgpzp2XkZ3K
eNwEnJ2PxEgVxkxINmDmbHBrba4dGYdQneF7ivd1JrNQHxlwyRYWiDyMBpyi9wZ7W4paipHV9QOt
nL0c3JT1bPymc7sXlhcYQBTaK5+HrYyUll0nKe6CXGFC+tXA5xEG2hFLlKhPGqN8GVo/qjHRG9rp
qwfablhrbtItYxDRtt0gbfE9KYkhREUPvGGIuE1T2IdawVHgFb3LBSeLL9oSd7v3Azfw3olwom4A
oq4i0lSTspTURxNQN1bW2dw8znXQZizqx+9hOtifH34QJlECg/Nj7jbzFuZ0QzU1+4QmRWCl+mU3
mO8xZd0DrSt7RbYaae2Nk5u5ClT+vmLW+hYbORrOgF3WO1R5pOtSFIQugr+JGu3cq0eTDxnPldcY
BxbDSDQKlHz6WgqJi6g94Bi1DrejUeok0nlzRecOx55g6TDA8+7LMvtdXwSz99mYRLeiKE+QQvMC
A/2B1D3Qh3jGiyRBRULeqbequxT2eoufWOQdtHBrIh8KJ0EUtIB40mpYRlCNch82UvLxjGeSP5Jg
yrFDmNL6O0g5/+v2VisUltGd/PgBURkcI9Y7qkK4jroJpPlyua2e09kMeEckM7YaaQjP45wxf7Zt
AZ4FvfGQxu5EKSSFiIR8Uz9XdLTrO4QGddVMsfzB3AL4u66HhzZ49mfA5DCM8cA3N00t0Z/S0tHn
xFqnNgrOfGYF67CCZ8sbI75SiV0Wc1ODsSRrC+4P5kkq/bc0zLe5RDsMdxGharrsZpVhbZtk9DJS
tzwg6Cl6W/krVQWjISqtDDIi2rYihZvTGv9FbNEZF1QYaWsli1RBYbKU2Uavh3iJBxBW5kYNXcwX
yKgG/cXlelv/y0M/7XRZt7sTFZBarnb9MxQQZ4/9BIsUt62xDQSUMQEVkuRN71ngcxhFYeaxujmK
OMJtvzyQFRgsUSes27sLlpvpRZqNGoFfxvLg23aZy4e7bBOtiCVE/6eLgEFs7KZ9i1WVU7R5wdzM
2kFd/HLZJD5yZvgR63QK0aa3q7MUckADPt4tcBAFSLhC6gH5eA8cuCvyE4vCTz24+oWzWQgDjUrD
qbxkYwNEJGwBRE4g6kd6GugLYhITqwSZweZyrY0kQTC0RB474A8vxst7sgkuObrAMAjXzbB3AlSC
MoNQw9guG3htGqbC0RfupQMKUQ5VWNfB7s6V39O1YCBTsEyRGUwundEeY++WtNPr7vOdyhtLEbPg
rD/VyJbOow3Z90f3nqZu7jO68PrFH8bPEnTsRul/5s6RbKeph73bFOeGZ8kYLcsTl5LpMWdVWCgZ
fFNx+/gNR6PNFwAGrcUfjKhXByWAV6wW0912RUZb5l7+sn5hdgDQoewwyUsB4PYshU1QUweuCfAJ
B+nIoVO6Z5t40xyp2eEYYoy3jM4eKZGzcWZJmRXbWy/tFb+eyvqLtciUmDV1PZEt1mVN9vMSWycP
2hyjGh6JBNrA3FmPi2FpRYFAfyClfTrll/cGKLiiJOnTTx3eCzTZIpJ6bltuoWTE5g7H62aRJRWB
3HiAtt9brZh2yUFK0o6jSdBYfDKeXYFB0eOUTMFcwaeq1tJFOZOYM85f0EuKsdyoZ8J5sT806t0q
aVWuJJjn4qUZIJkOMvMpqR7fjtL+fgHBDSKvOGs6xW9KnsNwhf0sXFOEZhx2Jkwnt+kQscn65gxm
EpsZdZqCCEE316MbvLRtXOliKTWMVYVEadfkeiMy+XQ/trgCos5pbqT0JoRXn2SVsPN0Kl19CssI
GQ4IoV7Pwle7LRtOIwQMyjCr/glIPfLBe7DO8jol35OnHlH/1pNz0GysDFbvpPAgm1iiJ56SdpFB
6/4f+RW20stbvbvB0pb744sql+biNqElIlFd35fo9ZVaIsbdJNmFVyKZXc01ch6aELIXhskxCZaW
WCzMnYw1OE2k7DxjkxFyGLgmvykhQGCKKsGKxPC5v+egkt+014V4qTocyuGZ3RV+Qfeq4zJNBVqD
sKhDoC765dvUcVn3kAlN+MFGsugl4qw8gpvp6Pi14ER7cm9Ao4vonzUKhhRnr4qguKNn97eqSBL9
STbIhfb29Ejka0f/KG5b67N7PJnEzcHK5HYBqWeIu4qE6n7lgTdrmhcxoVUY2VLyXlKc/Ni3axgm
9Fp1EGSURYaTa517hZUYkqYq5EG/a9TVOoOy4atrFJ3/btddWW6xvjwR3KevCF7AtqS/PGluVzf5
2ISWMgewxuPen98yvNag26bnsJ13f0rt8jRIT7shQTTFqjiO4eBPny4Gd8VXixVjrp6TREh7Ph61
4BIelRMZbuE61kppF5Zd+ZvemMcYDdJHukWFn8m9CXockbpzNLesinyDU2Y/4rTy9tk7ljom72SH
DqMEDVG8DM1Mbr7D7+ZfvF39KqzxeM+XDURCMozcloK6xnoJLU7rnNW6AGsU1WD2mdzSY7dxTzkN
h8YHjlg2SutlY62hMoLz3dh2w1RGIqY4Fch1ZVAZqfgk4FiLXzF2aTSubumb34pjATv84tWmtwYp
zMQgWEwRcKIKZRUPFzB0Q3BOz/IjLYGLJVf/jNq9eFqfRXlI4A7dHXAaUkCumQJtcatl6tljekKg
Lf6tZ7H3mfK0oKPagxt9yllho8AdvffDdSu7izT+MictcHCGuGoPq5e+gOKFlv0OQvpizEC0Adf7
CfNBOcNGgo7yezsC7GntVcRIiM6+Jve0kFDOCVTiqdS64GF1+5taKpgaQg4/rzqwkj+7HIe9h6z2
XeCVu2kDc+s7929DkXH3j3EYzRavJQ4hRgJWT10yyS4qFKhYK/5ZRGSESBpdThs2bLWCbz64bYXz
h74Z8kvYKGu7ZshuVaFz4NZUuiRVGOIAAgizDrdwRxGlH9/gdZpv58buuxDUoRJXUv2d5E9jqByR
D20FXbreGMsoOSf3bSLDPgIWwgHT9Llux9x26ot82olm2Rc88ZL4z9X6hgm85UfWfNorsgnb/bze
OJUmvLM1hg7Cu534vWTGp93XjskuaGBp+aYTWzcx6s4TSD5AJv8BBgI7bWZx1N0UMbNx2Fa9jcha
2Ok5QTnrVN2bOa57rCA4azQdyAg9I9xUv6g8QATweK++rbHSsDWO+q4YbY4Qme6kvnjk5qdAn1/m
lVcjwNIG51kP1kBWV6tmfVgjt5jjJfONLJofAovVgS5sBxNrlD4PlojiSKqhIjZPOguo8xDsq7zy
h7vzPXRlJXyqDecQlJSB8S5xCfeCYqOzYBl25VdmJGbNCm8n/VxEpVLU1r1RK5o1Kn1rar9zHtS9
K5/Oqms3DEzHCllhjvqccYKJfkgYiMamguEOFnMLPDGrvRaAHOLlJ1lYVq7udzkTSPyTHPNbrpFt
t3Xxjm47ZX2t8X6aW5tdTP2Xl0RR12OxjDAWkp7HwOWn+mnugzPJ7HFoz3Q73VQXHM0r5L10EPBE
c9oFvO/HGcInC6pI88u4XefJLOa5B6fHNolxbfHbhxuBl/XJ9/HiP0yIq8PKIo5tJb2Zzpci1srE
sxwLoU1IgqHNz+9fDI/25ZVw338Bs+C99ZPwsVuQYZTxmxMKP1aEzuSSjo228SZuxsMG7IeEmbvl
iNaFOVJ9ePvwsd8TukLSeq0h+0IQQXv2Gk39Cj5JYV5XZz/CmUOpqxvygSkN/eT7tk6REl94RvUf
NNMPeFFO9Zhjwi9DEule2MZgGUfikwRL7iUqBsDQELPsr2s8NepW07SLEbuO+7HnDNjz8/uukXV4
t9GiyOXN5xl6K0TS7v2rWFw+eQ7emt0TcDqNbveVuI8kVjYCJzoES/63pltTR/BB4JHLbJh57cSv
2NtUGAUSDP84OHW3b7CIm2D9BxB+PmiUY8+zYUUL3+mxF0mIILi1yjO8SliQPr1vG+aZX/u5CRGU
yoCzJTm7+h8bpePTPyOiQv/9mWSi/SPP6sk2q0jSMVmSlQCu0OPJIuInqzKH+o4UR93L8YzLPVUS
IRy7nB2dmW9ZCS3fxVwRIbWOKIAQsprzC2/TcIu2B3EX5baI6UAKptzLgDmII/SoUGg4YKTpgUUE
CnbM1fgwK90O9tLI4aMt+CXGWBXSVnTj9JKR8soDqkQy01gc3/0IGCg64/Yu9/3nZBtf9wsFM7Xw
EAXzANp9SQnrDXAkm1iBToQY6X07lzwAidxgme+2BEL4ov0oNeuc4dirZkywoFX56F5XnXwSS1to
FMKtTVp/w25r75HS+fhfLDR+wahbFwXM4FXwS/2qvjeaeUU/uNuliApdeKdFHwbKZMfDKqHOdisU
Og2Fkc/csQ7c/h/mr0nfANXgYI5TO7eAq2Wz+Ikh0OA4ljqmI5XLWBmsUYaHHXZScBGn4BEWqJ1G
eNS2lPMFxNKKwftQx//vinCNG3OcUgIWdAlQmYW/MUfiraQam2ogb/X7aJqQCn8RCfNYmhspXqg7
VYtRFKVpG9fZ6osv4M8eqVG03UCPlEXCVcq/naH1JJdSxZym4pUoVMtME2cNpNtBw8JBvggMxyn4
zSl/NUfEz9AYrDIboH3J8DDsTVfmQb4Sbr3rNBWNKLpMoyCyQwjcYvBU4yWsnbC5N/ctW/bQRrAR
lzMEjwipBoflEuQ7Yz6aPtlc0FjCpzlsOJLLaoyfVeP7hD+ZAQAuJzgkXXVfyvtdbZ5JpQmwPv5W
+dGFx7dnxKg1ykhq1Jc4KMTWIj9YVM6ZFQLPpR0eSDBzdtVHOWAvEar2XKEyaiAIHIbrTRusI03V
lXTo9eEhMdqcJ6TPh42Te4DoaT9bAivayk4/AJXUH67YU4Yu9t5/OX3FSEDKXW56rKVAEIydp7VU
jftu7csZdASU9/e5Gcj1df/6ZCbYo8cE8ewlt24Dbb82dCBG0pUZwpduE5o+UzZPKWgGnc058LbB
sMvZDqjMkzCUmgRtYibhmlhvexPeWDysZEKK4qvaVjYnpNptLCvfjXz4uIEBLArkYw7BcSxp+6Dm
Keb8S17eomDp4Rffj61OPtz2JEJcKfSYYza7zD0IDfO7P1WBgIT0LJM33N5MZkig65MmU7zpWqa2
qAD6jKOt3Qq/vYerL3yTpE8d2h+mNqCoFesqf8liRfJH/W8dcFnGWBFC8LIS3awlun5C07gNCkeA
WBG/SeOIZyf3pimv4mOG1LOdqCupsUDtrY4PTr8SdG0DP3nvyQkr3HmOqXYuWMjB7xCFz83Xo4Cu
lRf1YruemLoVNGEyA1xxE8ETtP4TH2wxW+EC0xbYHwGH1GzB2iMXz7d/QGb4Lxdg8QqKf3vLP1tX
Vl65871oROwlsdqI+HS5WxDNm7y0xfVEiuKxazr5liF7Q4bfu2Jurv9ugkOWvZH4ENU/sedZbx51
AQnaLVj0FA/BghSxiDZjB3fugKnPMp4sA2/aGZvzHo96dzUnueXkuF9xpXBac72T5WMdwy7MVerv
64IFMNKeVToPT/l+m0IWAdzFV+kl8hmEoOFFstrw6nKl2Xp3dZ8CQ+pE4JAwYD0s0iFKc/hrDPkB
56dmF95Us1Muj9pB85oKKXgSHrrahwXwZhTvGQFi8KnwQEecIKdkvOo/32K8C9MLX2wDILDoJtyh
iFzR3N/W3t1rA2NLbbPP6AaYq5uuxI4J1icTgpCVMuPAZVgzXwdlO5LCHqPrX0cy5qvX5B3bXMKE
8gw7LLzRvJDEMC2FHUdp64ezt/CNN5Wz/T6WTBGKqUZU4e3rRk6smbrtBy3HCFJAEIwP31wAn9iQ
u/+JxSqNgiyIKGW/2C2ow+UDBZl5p3HCmbX5yoult2jSetWVP+qijWpvea0Rt/RItiMMKveMCIK8
18vaVGi7a0PK9ar4WXNjSvSnCHu9Dhirju1ZazOpbu3nd43i7D4COmGMH1b+nmx1tY3zTGd5A1PH
BGt3uKNi+NlS3Rb69sgZtYVmL8ZUSv3hNCxh9jSk9FVMMwk/CwO90Gwq98d/WIAd78fQwPIn3Kal
MgVPjJNlYawVoDiG/QNTpwT8yKGTGfBbnOUVhAQKyU9hVEzTdERe63g/fzkShZPi1vVsaJS40TB7
3SmRKBelXE0lN4TuAH1rNuYtABf4Aub2NUZMRvuvG8nsTijoBgvxrxWoaiqnyAzmco1NAHNoZ1CG
lqCn0NJ1jNFjTJGzcJeFegToiusDe5jYp3VrnYPzEzqZa8A+wfw2BT4mMQdfOr+ROmEiwydDfDOd
Pq1q/ma+vZyVIFobkInHaStoE+UGyOBn0s9h1E88XedpmMWCCdkGSOVrl4VKa9PmONWFAIq+Ru55
oMris0yNafhR6TZXUG0XS6QOGCmIz6HVAit2W1T13f5CySk7jIYtq1jB8QlrwoPsiNTE8msx8cyD
YlCxZiRwPL8nUwPnBT40ZeUmQo9hmgQ0FnNveAN2kOhLxuAY7s24szeWWSe7A9lq3su5idXWktEb
zEWHM4BQZeU6wnB9mbhXjFkLvFjB3G8aNMc1ZHQhnCYDrcazVS+kwTUmUrxcxlAoV2wreUdoWy8M
sDVqgDYVPfKBPL1S5ROzsD0Re85zHvdapGaPJDAFaX1U25mMwHg5aETF1DGGf5Tk0kK1DPToOznn
wz+ZmCK718HtgqslLVQPEU5B0UbSPYxtPLjffqUQGnhvXGTOeV3EiHu83S0l2FXCuml0NoNs80bZ
e+8N59JO0zdPdVk0djs/W/ah+pVY8odjdZpjHqhTcC+rAGybVyUfqbORZHGNDBrrRI56smRMJT5K
u7qBS0TtPMfv5/uV3LxTQ0hwC6ezVhzDAwvnEBP9TFm2BcHJ98nzyTyhM5RmpSUY7VtWiW5TxGH1
8BoylGwECnr6xibI4tvfuddj7tZpLbBp3X5y+4Lwj5aSLopgqupLOB63HCoTTH4Bc6Zas2PA14Mw
Di6Qhx56agj0/VRG3mUNDWkfueVy9QFpOGJqgF/1Cpsx5MQ9VlmHX0elsbCSDxe/SXz2EvkyhoDR
UW5j7PeNoC2irqNCxHsKDI7fZ7aNzLY9jZjFmE0QWARckKtVAL7lxDjDhE75HfMLWmF+hMxjMJSn
Tp/zoeIJYxu5tEEj8nQqoRrnetCjw19MEnMGrtl+zkN4YF0P7qYqCQC3kCLLDQaKmSvVxSo99NUw
ZQm7gMap3r1sqfLMgZNrH98Fl0/1P1uGNJ1dzhJYoK9dhT47p0NjfH0kLCNDbPAI+oTyibh6+7B5
oOU4PsUhYoGoz9YlHdP+1hMzeeXaf+EqfvEHKDLRLlgTPXXKz8LCWRhedpXxAjPq4OlxMR/ksfvW
/FZqos76GWjJG6/jxqnfexSETNB1ovtwSmtQMa5qRNVuXxKZYvXl19RWbz9JMBKf5qvAWtJe8c1M
2gPmVRw05gTf8LAH7zS7W8Hu5I11r+dTBzMSeefusXgTufAm1Kgnoz78ZHhy3+cWS0Knk00DHoZX
rQq763kU9Vkqb7iqahkEDQ7dBbEm9Qb/il5uY+Z4htgTfaWKRBxFgqH/JdWDh6irzIUb+eL4liOV
Pqs6EocTITJJ9dG+VsKm6i0mqmuMDzW+0B0nD+EjCDJqdVz+w6+s1gVlL0xyClZBXlyUfLKZpUDu
ikLTR45hagO6QJTyWL4JnxIgNi560Yo2HCXraD3g1JucP+bgaWhs9KLqT9x+gYReo1YUEiAIvDFV
GeJgxHWRQMv4jbEROiVL0XkoA1MR3RvM1vhd5zXDdkE5XF3AMqp7oij+3b/4jrtz1N3+1K+f9NPN
elAdkkNP0ZdfetaB3PjkoF+NMjEWTDs/qq6Xzjwr3s1GYazCoLUBG3CLYdCcHVWKEu2T5b9ck+Dk
+LdwbX1CBRUVNaWmZbuFEwB6JrL5Q4iyjd6SIApY81cvWfL8evnKZKeAb6TQCU+24gGwsyQgwXMC
0lOGVJ8FbDqAx+E1s7knPPbC4sWCuoFxAQzaGRL2e/J+WYF7ZnHbuuImqxDj7gnbjTw+no1cQvS/
oi3RU/ZTRJ0z8tWNUl7C0VHQXRQQsjgPo9cPqKZ5PVDtYzYISnVXnhfv13pKbnrKLWjWBIVWKczV
fXDGBsf+/hyGvOK7TnMkwTwRVE6joupvKoCvJ9bPT9UJBGBMhP4pHMm5Ybp/hex04GS3df8Y9PY7
Qpo+yHdo3GyIb3lh1lfwuRtUVfIWY2THXCPFG+SuHRjs8JqlO/UPDTlrM8SRlptuhDXqCtLqouGH
3IVAJlJaoh9dDWty09PeLNjNsWwj440FOk46nbYpTIj7NKToSDIglva1ZYgajsC9EsE4tBOyTWM2
OqO7VWK6c7h4O0P9E6/4n2AmmbLq04g1WrzvKOQdzuxVGytfVXvzjxIRchkCu6t2sW19DGKMmYZQ
BprXLAnCIF/xh5B/2fgI4Q0kk+jnFHTaF9h1+OBWKKb27ZW/+qilk31iMTYFwRIfsLUXHceaK7Wb
QlcTLdEaFFUi7kWukUhSoVCWrnrcJVYkpEwF90DPVJTPROwd5cPIscuxPbi7js7mGqjws+Yn/mtQ
+EbbaKea6RT9oet0qSmkE0GCzQaklqbsuKb6xRhyRBoKB07/DYXPzgO55rEQj/CKszUwssUTLWPE
oMFxijbzBXn1eW1XeVLGS0nWLLXjnq7s/1N5YiZ5s+Emtdt8Q9B8Vws2S689ni6D7/TnVkve/soW
7xGX6YMDmLaVFvL2/OwqhbRVT3W5xpLORkrOVlGjcBO9KGGfhl6j2Oz9IxB1ANw0sDiyooeeqBBw
lgNZIGoGuu35hSrm2/2a8QcCuKzckXtUaF5aUz/Z///ZeWR8YCahoNy7WnJ/eIQaX+Xy7zhF8U/d
AVDdJBdGZfLovokwShWhqDHqtFXqJL5r1tKQH8oEFEto76EObLSOi/AzzmsLsBWytj8W9/CqUB3E
pWUO1faS2kvbdbsGesMIKv3jtwT4GJVUVkIaSLnlgeNew5+rb7odvNNcl6dBkvYd3TmUGk+ezdVa
qq3EWKK35Ov+ZQQvIfdmm0OWBVgQcvYrCZOaS6KJRp5pIuTMSCrkb+Cl1o3M4HIrWQybnFwkV9st
aehfYvpE+biffa7JcLLSC2pLXViknYmNPB2mFODPkWVZi3sWkuQ76sS5l+GBElHAZE5IVivqpT2H
annghf19RI7wCgKZo2A23YRNTD3k4IwR2iC5Dhb20HZ1IKsIWjTMd0FMw7zv5hHFSu8EI/hO93/u
z48tTHwm3K35yQwzayWxyZa1saqTd5t8h3Tk5l4UWQZsENz+b7tCXe+1lPr6Z9cutcN7krVZyKU1
Lb3+GT7kR4dmuqz9pWtKigod+RsPt5RAytxAofXFekYXXF4AsyqO7x+gvsmUwPgXZ/O42w39FbeG
1BXwMPmerHfJl6DwZaTb45WgA0t+iVmsp13FHujo4U9hLOMWTN63HWiJzoloP0xDVnoEwzEfhCiU
Nq+bdPlsboRV+Jo81Zq2nAkAw+bCq6KjdSA11CMa/cBkvLqOc1QtXHRUQXa00JMJHum/lCGvo/sC
/MqhC5wTLnw7rMICmaL/d0l44IF0Mzqg+x0yImkdszfzHzeBBzCVqTFFR3ePnQNeLrFWOE5eOlFo
NU1+KUnoArOHkEUxNqt+XngMJ/frRBt1ZH6kxg4J5z9XE1vGd6WHPICAzl6gTfDFI2H7qdFqXO4W
1VKb/uDYzz1WCubD9AUKDJsvsInSHIQBCDIBWNr+0O2h8DRIEhM7jToslqxLaXGMPRpcrLXU4Jm8
C7Pi3DnNx/v4ovsqUJeM72nVqiFDnZUMJd7j8vCyoP8PcDq1VZWu0xEsbvpsSDwionQxhURpmraZ
5hn+IjzlPUCZ6NeiJ45M2R1mY0w92XNh0w9w5mjxUQRRIouehcud7wOQPl3XCHc6TEo05zFDjq1U
Yk6lSk15/+hpjJyMJb4vqhdQvC4+R1NB4mjkRSkTbsz7pFuB/cgwFXg45WMCajp92iWLKCMBkS9a
oDgNaiyrO8gyGnt+ROGuz+W5A1T2JmF/p9YTLqHwnwt7MnmxlbWhi2ih6n8a+RHbyUSUtaSxaAz2
c7hh08C7GbiyGvkYzEN+sL/FDjhdwyoSRVKs9bNVfA9r72ED2CgkL0HVh7jHdyKLCBfAiy131LjX
ZTtps8mcgwdVz4XClQcWdQ0bxe0NPWLVNPpDkQSXqxpuKvluS5aPQ6rwjLMAKC9YcMu7rrVQPcT5
/nzU00dEC2KscXZ6yOSZGRQeCPtOvJtHS6D1zj5Wt+hvTtwej5oHfOH7TqtnW9K9AxuFv5AUzHXd
YklCy6cqhbEd9wj73P966pSFlTMrDHnvMFYLJ8benJVQcdR1XLDyVVcpTYyET/aVyY7McCJBAMb1
ZxgKxFInfJZlk5ZRI1BWI+3jJPbXponA6SQm9DTqxJ27Kcz6yzS1tVK5rsINy+SqfztJWkaWrrHt
XHxLMn10IU7hKZz48+F4oz6MUjOHyDsHrSX6Jrbr4YKzRYLgV44rDETD5H4m+G7KHC4+R8m6XDHG
b6eCAkIXw8fJlSYLRD1qRODt3GGCWbTUvDPULaY1t7wu/7zsQOi+gwFMBwDiRnNs5U4AKLpzysn6
4xc3j1JlBlBN8TVX+8xvkQdJ9mB9Zc9yHIsmwsyUfWisqeax5y5+yh93eKhRG+w6fcOTIW8vEl+d
BgwKBlc5Bk9NnHvZifb6HynJHBw8BDpkzIm//xWpsjT/b/R/z0ddJC8RkRDs9NDYI1ARDW3viyO2
H0bvwnXhu+MhYRhIwpaJkhYN54VsbOtKo0/5+QG912RhlOpKb1eSHqHC9Qf1IGhec9Wl2QzV4Xla
hu0DecRy4//0CJb6qyBSK1Jbj8D8GWA3vAwukHQp/Im3kExWzrdTM0LQ8A/zdUV6fqLVUMI3gRY0
c55dRjrc5EqmSGoXTtmYG3J8qLwSW8YYScU7bY1EePn+L1rXGgaYZS6AsAmS4th7bOFfRwmtfBWl
bH8P20aEW7MEwLJcEyQsIuTS2SUAztq+EFoBFkDdcc4ZtTYgIgmkC1MyWppeaKLiK4sbXVE4ywm5
AP+B+f98Qvn8HzgDJ1AuG/cMZiNJhxgFSFJdQdD4MgdioslU94WVPlEh4QtCKEEit93Ejb9aH+ow
3AszJYIzyjp4bIP2S4yL2OxJ1FtWS0tVSUlRudpUpuBe7HSLE40CxnSfE8PgHrzFnpImxTTddOci
LMopOlp8WVbcNBAYHFVJD/5bEiYsETAFoH+FzxPr8h+iGtxZeZeqhOUcpkrMeoDS+FkymMU6iXcV
epZsYxhTrPIobbitskViCxCtU/u4VagMtXllAygAx833YVhGLcwnulaFDYZZEFj8IK/ona8/KduV
EM+ljxsaXZ64npqvk9Fc7z6izROMUHQu8TKloZf0o6GiGAI6sVScBqx17Uwutm//6inGIhVd0zTF
JDJzdFFZjN+gv4f4ae0t/xs3oXFQpuqXFEv+78Pst8UnZjyvO5/UPvFHK//2V71d2yekxBYZ2+LV
E9aXJlM7Hp8H3ea0edjLnZBkeEmB4/tndMQuPnZUFhM1hyNg0uIuexkS6MLmz7dns85+ojFS/snI
o1s8AitWnHo1BBy9m52KcZ6eg2YpokLGRd/eL4yNvxk9vTkNUXm3OXhnsdpSrbtKzRJfoA4xt1jV
GC7BC3/qoIX/xlwNwylgug7X2iYACj4iDhoSAJ1GiWMelDcAMvNuVW7QNO5y0A0wUHfJ9zdp9J2g
w1DdGAnrHZYZKbAIJjdVGVRFiaQ9cw3Tu8TqnbczisK6P5nvvV6CxYuxL6lE+0f+waP+96QeNq0s
9rK4MzcWCsme4bVFbCZB7a3ssvyBUOlhFIxVBSZCBjVO7Se62Zu/Xm2xYvrF6MlRqU7FSh8o5s8p
HtwcF8cGT//QZrpPb4ywWObDBPaCcKtRS7WKNzYCY61E/f5+MytGY3CU08Fa3gz9iNtBojnzRYNl
QmJDA4gbIQjDXlaFgvTP+pZZWrm4dIggPtoqflG+IMXkJfmuBHpPlUtYjlP4uM75hiZGy0C0/b62
hp5kuHrjEJJr2PavsH/sv34EYtck2wMo/RrwioPuDDmnCJR6p08yphkOOQiUXP0y1MZCtz0rh9kR
72FvcXHY87ovPlO9whNBkaex0LI2btK1MVAjQdS9b6BXiCBZB0gfM15aYUwu5uBSouJOswWtpZJk
Z/bue+47H+IPaq0vWcN28MPC32h84qd960Pb6G1Ei2uyic7r7OcsT4mk6tUxA+yjgDg5WgcerAbj
BIhAYAjcJpp6WtBUsqtOyYpmiyr1WNMJaKb+xk4a5BRSlExnDdQmN2NxDlOImfQ7EzrFLbRdvWSQ
HaKUjY4mVcNCCwmImGUCS/MlURfMn6Zq51hu7lENfUrNchrk0tIeg1tCkH8pjez8bgy+inKB4OTd
jrYDyX5o2NwVIb24LiuX4jkxNlNxmZ2kN44UH7BiTmn/NoPmTTafdpmaMtDRfdTrNjOyk/zWgDOX
ZCZSpjBAfXKXYtPh4Y05j7ivZpbhgYoNIt6G3eUAhv+qu/yuQT5Smwo04wGJZSNN0mLtYkbFknzh
M0DyDyKVLZmbMdkXiID7xV/z7bF60mhQkp3Qh8cLT5vYKOLYx7/hoaOOwl9PgMngfbDMK4sQgPrq
JAvjC8aH/AOQOVHVzbM/BEn07k7+XkkvjbD29rkH5bt/+X5dgaRYEnKh4xxMInMQbeeMuGj6e7l8
Oo1R4AxQA2qnPJ1dfNB0HvoC3v8Yjit+NaTLdXyRUKvFVsVw5pip7zGmBhjH3MtgRAB486FsGtU0
hUZjREvJelLp+IQac0H014wN0hjlOMDT8WYOg7k6pGXcNovnYn2ciszjqCq9d6Brel34Ty6LGa7t
Xlo0KFpgbwzMOCur8oy+1SGdUpeM6Sz/c7PkoKKgzR9Zg1QpJ9JkFkYMNdoQ7zaBLcchax4CmaDn
IVHubptsbvR01zgtH9kE2FbM+NcKUnUJoEnF2UfN985LJ/OL1Hsv7fhA/CfI9E4/7aTSqIEcpVtD
Aua2ahSiVolzoUuhP25Nu4dMJJCRSLXWjNrKO5iLrC4nuDxuqxAfgac3lQEWkCQQDWaGL1YbHNvM
aaZq6Igwj8XXcATMNkZXXzdSpeJ+ePmiPc4vc8bmPLzZ5CxtomP0e8AWMX5iNp2AGYzqy8OmRVpr
OG2s/k0S/WrzXzkNJSjx89hhfFiqq7/qeVwWLd5qta9C40RIj5DmOkVGYwREPVcZytpN+jpWSG2L
z4l0nDaEMRsIrjxg/r8AYoR0hfNwFjVEFDdzMtNDTDnDF0cwcn9agglFeFENp+bEXfkgTdrj4YhB
jNd4v3Tzv4dAXBWn0EFOMdHDtobO4IrZOjgMAx7iM4LPtd6XK4ZQI7YC+dOo+ZQ3NI2qaj4/qZkM
ROWm7ZKNnR8hEGqBruYgwIkrGp7cwySF5m0WYZcQ2IebgDzOODfBBYCrbDb/nKIMCAPOrmpuc2+G
w0qfBAXh474aA1N6NHiYvsxlNyUTPOrbZYIsGB4kx8ikNHq6B7gTeT6YpuiIxO0/Jyy4D+vPbVG5
/lQ/OdOPO5RW5gkHBJ10xuxh93gtnS5a679eDya9zAxraaVcJaOpRwP8d0btpNe3c53iCs+Pg5KL
Z+PGgCVEvNKE958IUbCqV8K0v+n9vMMR5YaNTh0K1gaVpRA3UZKnESZWG1EvfFORFyNhOm9OTgAD
ASl5+8HcLdXF6E6wi0htd4CHj8+zLHnF1Wef/Dz3GndIDfgE5TDw98zIeGlPySGhpcT3jmsx+Fu/
tWPJIPcIyfAFMpwZx81VWf4s0bXrsFLZRlkQ8+Qxa7xgHzkctcX64xBmu5dyaZ4FBGD8ormX3HVy
4sibJHWGQRzqK521inFz+dSznqel2pyoIuA6brt9clzLM8Td2bD4bhpPuVxisIBStxok8FKh3sF0
I4MO8YT7Lc5+H9r+mpH4jrkIbpKrjsX4FyBOvnVAu0OhrqxAiwbaUl7ugJrGxGhk/XJpJYhkdpj5
luIndKU2GdPViX0F38Fy0XUnhZwmOkO/ef40KaqOHHuUQ3n5seA6Ntnmy9kAHrcshFTs301uiLhk
c1ixlyNS/IDeAs0SznmVP71ntJyny8ixTYkAVP5c3dST+gLK08mkxXGcPIoFL1K3DvNa9S6fkB2D
2ekilSOxPbyN/ugcpoBuRml0UVmOTdSMpVMpNUxtpdUKPcdagp7EalQzuj7sS25Vsaa0obqcaymF
6+RsgX26SnEfHnPlMY0YodPXX8f6yhe1wy1lHVX7HVoPdJq9t4JzZQhqMc89129k1JneQtCRPoXt
9vCUNeauvkX5orm2bA2pvoswftpo/HkRrjhIM8C+hr6XjJgEXCWzH7NEQq8jQqByeyrrXfx4S5T+
jPw7EDETavGPziJ8TegYg40pi1NIyEaliqEd8oPR85s3KhMZOkKt8n7WmjARlDRXAeVB4FKjzzzZ
ZlqPS7Fg2Fp29JnZpDjQ/hQXcHNgtrDWKnPg5jPN+zrjZK3DOP0M3HPsn0bwS3A7rCNO3nvbL9Zo
/s8NER5BCsiu0Pkt+KIgkiJQtB8LLhKRw8xZvrtBC7z6sDtYbyghMwcK3tqKo+xfoJl4hXGGFH6E
iiQrOV1gocBrRWk4n/w+WZDv5dG+JYy8zMpJ3zQkFAOiwFvvsUXYH116BMa5+XHyLcOLG+R1nzNo
hzL2YpynUbR2JUCLrlUPjZY5ycoiw8JXxBYzhVjvc5dd25zplqy24pPPcFqGqL9kiJSyRQBL+eDV
sXNOUeK9sCWyDDzw+5fVWqvg+e2BEfsRj//wZFmIhA7X04fRy3gySU4yicaf8fObFPKPIZg7Z2G9
Wg2HdTalosj3XNyNZ7cbma9RZuALgafpupL/fYPkz0vG8IrkkjQ/ymanXbb46VRlXv3rK2Z34zZU
O6l7rSo+aNweK1OLR0fgAKdsBXCaS1zLd0nV9eISQzogL8oDX/A9GzCkAiRvKwzGNmzMvfZSzg5s
uoJYUfpe4DLirhrRlVS00p4oZ5JVhIjHABIPEq5SN586sRahC8I2RoQY8Vp+aL2CXZj0Z1LfsKF1
ODP1p0BIFdUNYnkuQDu1dZP310PglpJk62XP+vzmn48kR5579AmtXhfLCLUJBe5gYppEkWofGgXM
0ilR/fNjCNpjOhk37QPDC4J7zXS1M/EHyQDeJ5Hu07iAiA06Zr8NLdk03BF0mOfJIBeUWzd6MLpu
ZLyxMM4nBErBrl4E7s1rgxu/sfqYoyIwBOVyn6RwQrH/jTvQrYdDdFZ0tKwZUEggXavym6IfiAqu
3Eirp5RE71FxqXPuFXAkKZTx9jxOurV0CXCoI0bK8341zR6WLY6BPWBmdgN+yRd8Cu+3ydOYzd/y
WnJT9ck6a7vceFZaKnNQpgsKK35PFPO9eyaPkLPMkT9tLSLpfppCyRQ8uoWD98JXtjn81BUEtb4P
gkq75uU97wZLrol0TNDkq5BLBFqhocmxwRntolkZtLiCMmJn8/xfKYVXOcEHZV8FI39/4fhSnC1x
o/Rol5TuLYy4l4xrbdRnhyksDqDol2ltykz5kEaD5tuharJ3nw+33BUlqoRyqhMdYYbveCCbwudh
Lo4lqgkKlrupLhmemtHu3JOjfEzEs6CiJziCNYUrsJOycEo3PDVKS0CvdJfD35saqfisvZ8b+Te1
UX4SeBBUsL+ShCDYYyqCXaOnE7Kl25xvNRGEAQPaM26S810Y5deLwrSlW1qEXkrTwtAHJwjB6QXa
5wm+3GRG78DpPH8OwX1zNysej9vDh5i8tQ36uRaK7//mAUfyWeNpzyHn9OhBZ8ClLzfsw1zWW7Oz
UCfHoeMVDMk5JCJb1y9Y3Bqa29/pKMYVITo+KH5iKZTRoyMaWjYF4XwUCLd5O38LSYys1Kco05xv
bbnfnAqdais0LoUxOdg58VWngNQF7FyYlUPmoaHN3AacRWF7jMWSLPlCTLEv7ao5mP+MBHuSUlhi
xgXIShQp3sCMnAreQ0Zm/804vmm2OV56ulzpW7gO2ex4YwlLd2SKj+mcn4CHKCwAIlduu6F9gk9H
36Cfh1bVnMNwpzwUg/ecvh/nRhHmiQjgwh4k4QTMM2nrNCsr2+NHiT7Z1j65COgOz66c3t0vXyhZ
tvacnoi5u9IwhvmNqLhvFXzdtG9BbZ/jVO7HNSpt02dyZDlGJDrXHkIrz7pxhn18qdQlFH3a7ZKh
DT7A3ZZ8hv1cFiUam5aINvqHABzmJRHpj9OnkhDClWrdrEBntUZJvgNzM/LopM17ULB1IQFdr0rv
WKVhl2gLZ8f3HsF4eO5cYjzxLfL9G+y1c00aqQUEEknIcNPeGUKFMLx2Fk4UH0ExUpdw+gXU3IjN
aQVTgB8Fc5cD9bLt5ZlR15qDUEWnKaMbm0ihKbnzwuFM3MHWZ1V+fsZLl9FBmyn0NxR2mKhnkXRr
XOzmeByhz6WsHOmLubjJlhnG72rkjY7SM0cvedxib9TqXJtIkeUuNeLf3Wf1PLcXReuTAqSn8QZi
M5co2lmQNSASgkFRgTwaiva5oGluLZ59OXt3wG8jiB8Jtg/8fJzDGFcWy78=
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
J7WA7jme3+I19NsPf9M+Hwgwjif117fG+SS/1lPz2YSnAcnIAvNxWqiI726MbtIpQaTNrw1jmOBw
c/UqMzGGXA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
WpkCtItYKx/eDqw+UYeRmjrmL2mI5Hoa+YtZRmfPmT5sRLTmRtU7/cUwQiFGy7CTe4aH6MWqC6cl
7yOvMENd/saYaA6CBzjl3bmlQFDQm85ABIvXfAZeXd/bJICw697f+Gp+XDeqGEojeiWpNRwU64lV
wrDc4Q2vkGeh9QI57vE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
JMfAjM3enGAj056QPtT14iolBO1T4zxTCtOBki1tkxag0lSir2+mNI/TstrYDMMz+VmoRABO7mG3
E4cyMU4DD1gxa38kFX3Df+y1G6aRoKyhiMH+64JKw9JL46nEHIJOGDEPVrzys4ji/rAcrk+k0ZXU
+BNAptU3RUsEcOB76s54iQVzy3kBSJpMIPgROvcP1r3MO8cIWwwnXwhw1E3NYjdB4x4x28ROQOtM
4aDXOjnVqxltCBSV3c0ejPBRt48MD9nr/NSRVWgjS/hvMP+4BvgWbtA4WpqMqpIi0WkUe+1jnjRK
wOXTKLIQFC/BgXFZ8wCjpmoXB3EaQHWgUTJq6A==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
xi9FAzd9lUubrlRz4dhDTI4iRyCUPFdcb/aw+H792fSTh+zLCxn5UhtCbP1ODFFxarcJ+MJOP2Zn
+D5JiGjeYLr+BhL4vPssfuWrwy9ZskNkrYlO4+aINK6YeBevOCHzcs3XCoH0oEtDoTX4+iIx3/tD
FUbYXexUE4kxizzBtKY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
oq7lhuu2wC7aiGW96HYOfmmfOgDjHG2Qplf9OKcCdkzdYU4+KWhq3a0DuxlG8W7Rd4zGxOBB8KDi
My605jaSXXpuwZd3EOVEbvkbwmD7d5sYpfI/M11YdU8SD1rfe8TRYvis5OZr1zX9o2JsRGTUKl29
l+YsS+J/AZcYBlBelH69sokhM4+JdEbrUAAZj56hLth20QfRMXA1TCZmPp4RdMr8OO8wUEI8/00Y
+dyfXfBQHeZ2hIbRiIgNoAIn5WzlD6oLu2kSV9lZZ8lObO3DVc5rUA5TI92ltjJ2+QHZE15VJsPA
6EH3OhmfTivI/7qVVJaEnf6Fnzk98+CbItIpOw==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 20336)
`protect data_block
kAa1BqulofOCu73DntWHGpwFbRBeH6gxRXCLgZtk0widaQMD7ZW/DQZMVzdD+x2lT/bTpx8PNo0h
XbV7vZa2J6r+nfcUy9n3pIP3NuWbfn1zHSLzLVwHEP85WIP5IkqVZ/49Q/LljamMmi+mkCCy5W9f
rYtsWjcubTN7O3309+iN1CyFFaxZxvS9jwCdP71eDklGUnW2p5FLgJKxvtgP/8B0FVXQ08a41d1M
14cIt2ePFTZtlk1n0kYmQ3jcXbheCixGrpbpzicAZucwkWbtWN1IoS0zX+ZG/gX6Z75/vFatpGc7
qsm65NlhXqVn54VLs//IWPkEP/IOXUn2kFpxpq03wfRDfJ7GHy8QngQAIfquUAoH0NWn57nMxw20
XF5hMvdBEDjrCyN4WG7FY37txUaJ/WNFpBCAgNU2O1a3AVH7oxoO2N4UJL6N3h0fxtM+/Qr5hahR
h5atCScsrtR/2Ryg7q4ytsmnDirLUbFfjc9jPx/mb4Cc8M45+zuDWIokCSgjLkn5I7XUdx578U2W
cjVsbhS3cn7n4uEgxeSLhmscmDG937eg75PoOu1vsCEnZVW3eOnmWWO7fMdawjlG4JS47xAVuvfs
X95E4nL4/7u72JfLTeaxg374XvHH3o8wx2Te7k7D240zS4MDRgiR3Or7vJTMTQZi71geVg/xRmOk
Gu2Aw/+nvrP1n1WaB3BQa2jbzkcb2U58z3DLncoR6/HTT2CK5tuKPi0vJo9k/bz7wHYp6vVutwgI
yVyim+3yjCQI6e8xOi1+vmx6lTf/qjhe7Kwj4txJOVvgZ3ln0VfVY55PL8sJb0Zm3hcRHOZTp8gv
KGFesxArpGo6ywD2HGMRostUSycrser2wjbuD3V8Q1d7b5b9B/svupByQppSina0RrBEj+Oo+/Hz
FN9kWY4FtnH6FgIj/BJ3qtW6yD6BZWBrUdIjzMJiMeiue6EOO2/ahg41HH4UmYxuxzS+iTjGhyyO
+ZfvCZMsoBg+jbzflFIN9IH/RRVFNHRWPEsupud45SFlXENnzZnrI3OWLwaCvm21MYAlzBRN+Q1A
eQTfxrapwex07PhIEWtupS9S0cEEd9nzP8iLC41my1zIhy1qUF4KVAPDFA+BJfpiCvG8Fe8WIru7
tXVSFERhFzLFVX4zo0jfGQjQnZw1Wqh/4lEz1ps9XtwwQfwnhH31/wojxEWQ5kw9gPItIt0SGlrk
G/fmoyzvuBjIuMKCFZQdb5UL7cJvIznGIfQiSYP6BVpKWUyfZqXtuw+UJ8AhwwxCsXyooQUo0Lpk
7Uu5CxzQAlzUDb8e+VEpWB/lhVM9HaC7ircnHc06CmMUojUYlYbM7IBC/QpeuKxeAPzd+jm8S4fx
Bg2NHSU0wS1iyDAiCvh6KcC0XLGtd1JQpRlWHNVxCMirbAWgCvslJRzHL9FywFe6QFg/yYj7VAGM
j50tVsNDtktAjarMQHVlA9SBfP3tCXj53/3u8OkIwlIGR0d2QLiOPEYWhmtIofYqG/9GcWCKFRvr
YQPvKidrmcpVGIxK9/0F1oK4gk52+KxZuX+OCYUFxF2T0nNvVjKqyjEGA6GrzLBXUQnaadZi6oaA
Cu4ORVti8BkUtEvv4WDx1ne4vKOor0zJ9gi/Ci7vDPoOxL1EvgsZyJqmrhVD7FfMGVI/UixvxZLS
oszbYNeaVWjBsKizhBs+/wVevvPGFaL+rAmPxlPGuunUQ7K/uazyPawAMQTDufxq07lHW2dqr8gZ
qew4zEX1T0FCGZz/+trC66RBAYmUz47RvEnl+6bq7aRsFtpoImEPffqS5vIAO2/vtMweCLptyxkf
drIr4jugThhRZ4JvBWXkxx9a3qDkFMSogvWowYXSdoo5iZuwIv6oCfYmJ8ySatgsHIydszE3/G8W
/3cBLomY9kk4H05+nDhbY1Waq7sr2ajJxKC02BSraC+8VfIJPEtb58ieCfWUmXnzUj5VsqxIpgtj
904qfRIUfuuD96DznDCl4tvsLyo9it+oPSaEYtl/67uCFYUY85/iL6G1uvApxsyWlNS0jVmYQbAZ
aHmQpzeHcSldq0lmuYeXuGxYfnjSj0Du6rq/T2+sO8us8bIvuf3bcDmyJ+ulIQQFmHRbs0kPs4qh
ZdqC9YDBN105NeNA/ibE5W0s/UkC/yxF46tKNlXcSK4w2EzLXPXPaF8s1/tu8yTyhYh12CsyGmfI
Mej2mjZQ981M/r/sl6BZDICWV+H/5OinC0wbwXBOjXhyviIbCeZb4Qb3zlfjZqYzQv0T+MNEfPQi
bBn1QDRW0zw5AobqmbpEY++QCo8IVtuXN/uxYZQv5BpM2cfpMSKGEoAKKQEEpHaVCf2v+D2hRilY
LFM7lt6kWoC2TV9BCiCdJ8KHdOpyvOntrqRmoQhdICk/44cX1IqSJneTL7GMxJBIvEUbRRKFTeG6
z1aMSUQ7V6gm4KNKN7nVN+O+x9BAHQENTwRTwJH3V56FYnkC38qC0pG3C9DzAJulNIVpVPIHZ0Yi
vWIg2cG28rg2z4MNwj/LvlwJETxi/6bd0t34VfsC1wohaa/lu4lLaxr4OTofJFLj60XKbYeU0XRJ
KMbFwPlm6dy2ISra3N04Z+V3JlUYHrX/NdtWyG/He4jQ5R4hkIdDjC+Kpgk4kEbSPKVh5ZzWKRTW
U2fj2B5jAkg7ha5NKvvC+kiJxw4rTwXzlWrmDKqS1I8GHWvTbHiogMqoCprMDDdE4V13a/iMv+Fb
cW+uAvPvVFLhlHkldBfoHIm7Np54u6lq9uNmYLto9VaIpDsN2/vJ0fie0bblpKxHyzZ7koYXpixF
Qpa4rS7ptQFUtNBp5M9EvOjgZRt+IB/LDqXGaB5NJhCzYdPAWaSAo9KfDEEIMxod0+U00Quj2sh2
2mdizs+m5hO/OygsC6rNmkQtHU73Rh8mIvoY9HxHBo/e7KPdF6UKsM04u+GqzER7aXWV3tbwoiEW
PHr1MMPLnlcCSvIrcZ0YeL+1jpBHFnQX13OK/OTgylnlZOB2ezV4oFczrwfrXaPzsR9PaShlfbfb
gYJE1aiB3tbcL5tUPsgLMbHLYnuCV1urlynYYyCNIuXgHx75doFRPHeX1Iv5SpmSQd/F9i/BFFmy
et7u+J5jTsP1CRrHTDf3MhKZxecTW5OOsQbVZYIE0hYqOQYpdg1aSYsZ5KrU8o3cBHOPFULECUOA
dxjQnZjx3q0vWU3vmBzN8FWBg7RPbhtTC6L1Vz3/pWsCCS8gRInVrLucXVg0Psq5meZYEcbYEhxX
Xtsf/i30Kn7/pkXqrAG4gXGDBKYuNDCon6cFXTtGPJ74GxbMn/l0QqRJRyE7yzDytLk3PztBumgc
5D+7ZJA7vffBBYDfh5VcGXS/MObFXOb5l9wjhfoG9d2pd8MjDn/n+IX2TcyrvqHxJOWJctlDLJAt
s+eqbiTGs/cEYHirwYq/R6b5FGKFm62iOPhgqPIq4xsJUmvYlr62WnazggMl8mBMqRiO+eAE7vRB
gU8R5UzbLRUZiqdLevIgYYZwDG/uGeTC7N7ivqfjdSRO+68ZpoLcrWZhK8RXYduBU5WKqkmAoclS
uPTOdMN09yjA2TwaHN0GsrmhoQDocmdqz5gc58uzaa6+IVlFzmLe45PPDuc9+gcWU6ysR/5strUk
Q/i8jbNCWtj2csdJBdWmc+ZKw6fFhKL5IO37XKJYg3TRb+lj2ET7xt06M/dZX+dRvEeidzNPiBhy
mWNIxFoDD6zBv+rZtDxgQnFAYqxhNOY3L7V2pQ3JrOVn0+0wXbv5O4l0ZBNo/OJ8zmMFbpdBZ7zj
QwZde0TU4Ur+O3azpQCRIyPrjI4yKrucQO+ogV2WPW8SVPX/pyEzSNj7usWBfigqp+9P3+MO7b9M
wtD4xq87r3fmw2Vhdyg7q0fiqh33EdOpy4JPFG+sXhyA8El0UjaPif8KaxJG6H/QtXp2+OadEtO/
IrHgxc07oYjQItnTXv6wvzdbQX/aVIGJoSZ2LhTQdUd7dMsqXFlY6Dm2dggZR5m0S+4BNXEz66FL
UjCckoPcPKNqhsHVHRBQbM/DYdKJxefWptyyZk8gwm6QWeFOjTjB0VHvHEUSutP2jAlWU96ir6ZE
P9ARKMMJqZ43B+q4/zaowD0V9JK3kZhSx++w3gxCtfYStWbkn8hxlap977wiiLEN9hR19JJcumFS
Ks00sTY2PPB3FHYDGy3ZTTuGAlNyACVAoqaKRj/8yR2ero/wBdlFygm2dCCUVUf5QSozkgQn6ZFn
uBsqyGSAQAgAN5XZM4tY3aBicMaEOzxBqe9a+xQ8+uE0akER6Ps24JkfpFE+ZRufqtfNhIqt0B0y
F9Hwopqmy24IIqtT0hNel+NbEDujKMr+jDmOJM/xh4CYdUYryXbORc9yztTwx6HzfcfCPKHeiBIG
CBExZiDFXHem3gB65NvqRjYm8Ce1NyH3EpAibUZaVKNgPUD3W5YOlj/NGB+eNzbZsNXQZHKGAObv
Ftnr8vLNmpQPhan3a2QbShyd2Z1HLp8pfyGmxZ34uQY8YGxUrJ6R5Rp/gFt6iZ2Dl5jeq8FN5zJh
8IVktIldd2ZNlgdDJRzylHmV/Mz1NvW1byAanvSKJR7SABdMRHfjdScNiQNUAfhEPAyI9QbA99h8
GTcE5/9Dfk/9yKZ9CNNytY8wsIRWEN91sHQJuc899kc7yezxAfXTRSY6jpRBJPvhSEuWo6G5RUKP
bMaMIVWU1CIAdRppbAa1QI9y9WEs5/X2iCVf7PlGuU6b65ygGRcozw7mGStSsRVK2Bv7onC2FRMm
nDCO7K4zAnJI9Vj7jYkK6Is3DAbWp29tb6wZB4ozfHLXbgJI6Xb9JAV8B3FHV7caRZh5yc+dgCb6
wRQUge+bCx8LJGPFvsc0I60BfsxhdnJ+k7t0i60m6sVh703LgP8OxrJZDPTMYCkd6n9TMRNLZsxM
ECcAdT8ICjurRbkT1UgfMJTboHRer9dfyHdD+a4MRiLYyGWU35hRMMnQJx9MS7w+is6adncxDyn6
IQ07n+8gU6oRpig0mvR6HbitPNHazEMCXOKatU1kqb0XIOMvKSyokxSI9J0WGqi0Nclm+S3OIe9I
fcKxVUtLTrBT5twifP1/mSlGpA/3IQpF5GwY4XVfi25HvtJr0bvAZo6S1z/vfyOwmQdfR6Ti2X+1
uO4iX38qMbuZGr/fZ2FSneHh9f6vSsTvZTST11O+PVmPRaXwE1YBXq5aGFg/GfU0H6OAevr882pX
drg6uO7+EXHMTqyLo2P9TIMyl8T45mr6OxgKUMiEvlD6Tc9Sga7GMe9YnD6INM2+QqvBvu24fH96
r9M1bVUs2yjwGNeIFXEiLwJKE/LcxRsquwOMwKmY2DwD4kzhfkmmdFB3ptxdPEF1AOpTFI+lTCBD
XG1QITeh4dvvjwiNrbNu56BJAKD9McdPaQjbVEZ5TbFMqLKyGzLor/BkZ+V+Y2pXg4CjVByIRRIt
COvXDMu3+j5GLpUcDWNBxvv7TOsUBhUWhfTPWkjOVt0BqIsMp5rwaL9SQv1MYlgfzaixBCLUm++4
aUN/wuQ0jkllyMBTNDDRPf+74xwLo7EhoP/YUa1BSQ3O5eDSy+aQoVQLN+HAvHORJ5Q2NpkzF9g2
p2wfZQb7SwDRuwgNkO5v8Ei4t31D8kSR97xmdcaW1RYVtgIgclWUt5QDHpHaObeFsXnF4mGwEcpJ
h7X2rugx2XrYrC0A/XwVuXB10B0T+3ootAWsL1rifssrrGo+eC3NUYo/tB2aWv5ne/a8RjG8e6wT
VNKnwrihm9/tiTJjYickOxlVj44+52suxa88jPq3tvu0wxLwaf/G4cC0EGgOH4NTagks1bNWwDH9
Dez34ROFZ5ARWFjiXkbwCptpLxDGa3wFGNssSPRJFUBivnce9HuPAV7wvte9C/jp/Jqhx2JLidDZ
RYPwFhHf6KrotcZtMYDtMjAK6Eum0GKFBAkMgOU4BtR/Zm375HVDVvkRGIq3XQ3ECSMI6fedD8GX
m7WTPm49U2cBDka8fZNmBs6sJs7jzyMbn6AGxLP523Rq5hHmnxo9XTWKbFWJ5CLwjoSfslDfs/IG
f04ctO6idUBy7gT0lspIxJ4e5aSxQPWLY4Ex2/j+TqoquM4iFZcIxQql4+fv/tCt9JnoFOHqFUCZ
CmvqYQ0Nix+KP5nizOeHHf7BxLkSLo/Z0fW3wJfiDICP/SpbMlCRSMsYC6bTGt/HB4tIbIY0c4Sg
VZPBdN6OPwPkdzwjrVZXWPFtpJnouVYFsusxAnZKqyFSa5fIPUUjD8zi14Y56GpHbT4O/+75n1IH
G1lwSVjcOVQ/zG7ZsVv5d+9XCTEzZal7wentzZwF4AK04OEw2NnwozR2/iBNxb9z0hcNvbJfOoiF
RRvqMOGRhj0Xq3k/RzfzHCyB764dq9MmokjcD017FI5EG9NIhhiSksTmkUEK66Z2V9uA7HNzE0+D
Z9cWZJqApmlZnVIGfxZ95HT7waiEYjOKDlPsR6gfYX6mdIaPV/XyksqS7WAOaX+Z3aLMdHWF8fk8
t49oxz8dO3WgFOqLrsgMm2920QJriSTNBYzYD4ZR2dyQNE1HLunFTmLgHARoniVJBo2rRE2VPbF9
gH0aCYuh/C+zn1n+YLRMvnKrkPVrTwtN+9vBL/4OPejCVvY47aodRc3GqIImdydk4QUp86co+2Od
RJQuE3nTfAfw4dPA/rvMMjfG5Og3wcGps/6FGJ92hJxLhU2ntcGrBwqy1sm1fhF7WIOK2qgQLXgI
2atng4seuEtwz8TibKSCW3rz91OJ5MowF8B/8jFZdzvjkcOEftRKoIFJQi/ZLXNp2CJ8pBPCFiFG
a8QvSON8WioF1QKWYaPLa5qBaWRwnG0ixBdrg8W2K1oHVYGnR+3W624o1hxKTMF9GfHBDMPk9918
TlsjHJ1fbozrLSFfC9DPnKIVRYBR8Hp4wmRoV1qV368DTxAUXkwrmOcbOoJjGMW7FRdMbW5dzDKp
XEJwIeNbenY5sbTfJeaygfrZqh3n77DFuJV+imQBAWJTcnUYQqSZXh5N5+bzLJQ6tC2b5VlcLtM7
W0bkf7j2X+o0PJPdSJ2ejIEWdvBKtjPmcNJf4qAdxjKWzBT+Kw+uWvhERwW6AYPyFfnX0TC/2YY0
vZPBo5hZrhtNYR64pyUIfBjl+5jYtBOXnqn1zgIfVLq2driekYA1seNNyPgCLMvF6gyvohzPe0kV
mtzHy4bwS0iFPZbWhlethomGNgL5YXgCffbSaPOqQY1OweUy/2kjDbS6wEfoBG+rkAHdHM5M4zSL
Xc1ReF7Jt9S1zentS5a5r74ZvdvhjFTfhXMDizeCpq1lhaka0JEpm6ZDAfLdR7i5Ra6QgjhIco0s
iVQLdTS24DJnGBfBSMWQ/Y49zdAdfL11kCggVWrCtrQGkMYoLhYQsh5/IY0X9gtvxL+e+sbCYQYB
P0jvreRQWMOowFv5Lql8AU/A+kRwnZk/phkZwt3xu1GeWcfUtxmUR3j19xW9NwvYLQJXwFBDxozV
eZHnIWt23781WuYOAXj7zwzErfBCjm3orsJxiUnyXh4flJI0yaEw5WrgK1/Hsv6a033/lOWqck8y
JiYSTz8IbOgT2Rv5COjsZT1KQQMl4H7Cj6MgkI8JvMLGU17LyO/9swRG8jcupxHXumg4pXb5Jm5q
LwRGVU+cdE0ycdfhDspDskGxu+XHi8Ra5S1CiFrewvVwgoXSr+GTUkjOTL1HwyO6E2nTotNpbZFT
LczJ73NNTRTHOM5FGGL9tVUUv9z9PlDu5fWk+lxtEOx9JBKKy8nAq48s/gwNEboX6psFQSUCYDEr
hd+EWR82x7SUjewS57pYIX6AVzsN7gUECvDPewzPnmQ+IB05KRDuAoBeyahh73SHcc5ffkYSuWd4
5ZsbXKOc4OGmFuIVm/x3EGQ3Si3l9STz4rKYHK5+T5frfYxiX4fs5OAWQNiJrXznTmPKDJCO4g9b
5xDCvpiHAi7j410JLQZEW5GTgkGRaIyH6QU/vovyNoti4iASgXDuNQD2h6EFGo059V5cD+eCk0JV
FHVbl1sc/xTvXcfQnGcMfh89IopyHtczZA+tKaICu9EzL5qbUJ8fEHx0+bcFIH3oWlK0vSngWVSG
Gu9gN3+x4F/LD0Qvp0ehymtGKpruwTpHNK+NoaB4jjWJ9GtJ3qS9ltmZzjYhln8wuonPAJdXSjtj
JNW7YPdr24OmNjxYJogRQFq50FS/CcFfThMr9iA9z4+s/MlLYtUT/EoU06CL8fnZf3HJkKHLxIay
xWyhtNsVMCNN8wLmBUQVOtVPJCAesGwChxvgsGcJ8DARuvgCBLm1LRTqA+QXLbqq+Wxrc1TddPWE
CCovZdIq9EXdm6KkkRuIJ6KJaY9f5WklYZP6q4i6ScAzsSksDb7hTwYWoEa/OyT7Kqn1Br6BtNSG
U21Fft9sS83Pads9lZoztUooBPcsRWqXIKcxm2Co9iHnjttdy0MSGD11Ojp0/qZc4V8thOMPNrqu
5YmnUR1x9wYKuLTa804oHMAV4tCHdfOmVLhdNc+jHsS+lM366cZuQkBN3EUfdcGvN3/mC8UkANES
0wiaJTapFL60cMoUiCh6wghBfFk/oqlzX4Q1DwOIZvqahzd6uGDHOhcOJLorHPKoxco9AkAg/qrv
sh7jf51BM1aQJb1A66MY1sObslaE93TsQ/D6UFTbQWzmdaa2cr6nTcmOWCiW/YbVZ0+amQDIv1ze
FIgRHb+tQNbgBPbqRGwXOtwOV13rJ8x8PkgrlXeq6CUfDgg+CLWUku4OzqiLXHH2f3nXzuDj38/W
Y1RUv9fJPXqzcHCSNMCZRhHIuvhia3zuvT7ZoBRIYXBSOIQMDjrXTFS6F9ZLKLcV1mXj/TxDkLf5
agHIKXItFZ3qUTfxVZPdZfkaLowAh2zmRhqg4TV1tCctg3DTXrs3TrXs5X6ErHAY3rRWEV8Nr2p4
6KdCogVlx1eC1gf7/OVAOsBzwt1zg4OsNO04EtrGK9nCZzl0wCEz6q8Yythr0ahgftQjDm41y5By
YyzBgkCriXc9iJHJkGKYB+Lg3jntHLIzkMFbxykZcC05mTUDXu8KmcBUgxTRdb6PlzbhxkkwMaeX
iRZWt2H19TYV1Ms3GMvFwlZAJRTUD4Um+e8oQYgbs2sgMpqvSDM02TImeDvYdDRcyx9D9xTzJf/+
YQA/foROLu4UwpkULNrho0rfmHfarP58Y11QJHED61e8aBnbJ2uL0kPiQUOzEwrD8Qrj2gUvz5Un
s6MRBMQ/rtHyfOXAb3RO5ZpJvMk0Lmp17MtXFyVxXm8LJfg8fVP1qSRmU0mNy+LQiptrBxO8dI4p
0d26uNZj7Ga02w9G8TrBYvrbguXMbtP8ur19G7ec8WuLhPeq6cLQUVCcoz/skq/hIvTFHnVIkCP3
KLhkeLYhixcveeaOH1q8C9xMJQCFa3PNBIK4L/ddkRU28nQhSGsDSJMh0EQkMO4dwpvp2O1z6aYU
2/LuFcdnHTGVNuD0aaZZLA6MMbiL1oC3a7Omy8PRerio11aqp5MPADPwbYUUk5b/uYrZ5dE9R59m
CldGEq6OYeRDgEGkEDn/tAzEEgR1o9cgP2zFEyGsBpa0Ivm7unRydkKxax3VGBEgAdoKZfIeh+Cr
hDlLebblAId1DGNxv9yGi1tQVkqLo6N74oti2xuHxo8+g9p938pO8jCZ2GCvyZ2CdYswO7aM7D86
orlDz83VLnJ4recfmq0ycsFg5kdA3Y5hbU+zAY+IWEZQ7u698B2TbEYjcoB2OO0zTjg9PcXy7f16
tOkRovN0eRDI4a4OgPDRqSJHXwj4JDn8ixfqL2cpp9Cou4ODDQvmATmndct4WxLMypFWDT1QfwjI
qNI8GtFMeIm8vwhlkIsSTechXL4Cm3DOnVrfwoCfKCRMAH5BR1/A9vKieQ4tgHbWS0IytN6o6Ub/
uXVMljEq2VGliJTmGGQq9DBjnjDpW/A0ei/ujPZr7fgYozzSzsWJKIH/Ptjix4hoQGJjH9ku5UUY
np+22q3lwytDOSp45NU7kw6W/lIqJwJ1LEPbOuAPdEhFqaycPHNyboKg3h5Ob1ZxhTbinyeX20N9
ZE6sc21jI/Fb2tuGpl+nj4BxVZc18RG0Jz5MOeFhjmrDkug0+4MRKLCWKMU62NtkJOZ0O9VCYS+i
VzpPVkdXZ0hTErUXMbp8R+xkm4uRYwXjEZTo22sgHwTK/ski8lGBDV5/RyD2RKWOm8Xn31URCeUm
IElRhyQ0aRqb+wlz0bDG01h0SQ5zAqONLXAkn2saY9pVJNP5uOjHvXjtj7HVc9mzyXz1oN1vNcLB
fnC/b2dzZKFlAtVKvOZppxMaud/fcBIZAZYKcmq7kPxybKnoX0TQJvlpig9nJg1gLnKMFgN9+/rP
as9YgvtJZy49sf2TH7A0ac3is/G104ubnO8zHESRScbEcOujKHIo4b0nn23TXBpbhNQMushsAejR
4sYg1snkThDLlBqqhiBjQYlHjrlU3EOB2o0Cr1RtVIZ5OWm6Ndy/6IRQQcxSuiNIDjUW0lbi9SP7
Y8wnu/ZwNMht4v37Efe3PB1F/ThIuHZ6e71j89ShFUwdx9GAVQOwA9AbUSfsKA/YWbgpzp2XkZ3K
eNwEnJ2PxEgVxkxINmDmbHBrba4dGYdQneF7ivd1JrNQHxlwyRYWiDyMBpyi9wZ7W4paipHV9QOt
nL0c3JT1bPymc7sXlhcYQBTaK5+HrYyUll0nKe6CXGFC+tXA5xEG2hFLlKhPGqN8GVo/qjHRG9rp
qwfablhrbtItYxDRtt0gbfE9KYkhREUPvGGIuE1T2IdawVHgFb3LBSeLL9oSd7v3Azfw3olwom4A
oq4i0lSTspTURxNQN1bW2dw8znXQZizqx+9hOtifH34QJlECg/Nj7jbzFuZ0QzU1+4QmRWCl+mU3
mO8xZd0DrSt7RbYaae2Nk5u5ClT+vmLW+hYbORrOgF3WO1R5pOtSFIQugr+JGu3cq0eTDxnPldcY
BxbDSDQKlHz6WgqJi6g94Bi1DrejUeok0nlzRecOx55g6TDA8+7LMvtdXwSz99mYRLeiKE+QQvMC
A/2B1D3Qh3jGiyRBRULeqbequxT2eoufWOQdtHBrIh8KJ0EUtIB40mpYRlCNch82UvLxjGeSP5Jg
yrFDmNL6O0g5/+v2VisUltGd/PgBURkcI9Y7qkK4jroJpPlyua2e09kMeEckM7YaaQjP45wxf7Zt
AZ4FvfGQxu5EKSSFiIR8Uz9XdLTrO4QGddVMsfzB3AL4u66HhzZ49mfA5DCM8cA3N00t0Z/S0tHn
xFqnNgrOfGYF67CCZ8sbI75SiV0Wc1ODsSRrC+4P5kkq/bc0zLe5RDsMdxGharrsZpVhbZtk9DJS
tzwg6Cl6W/krVQWjISqtDDIi2rYihZvTGv9FbNEZF1QYaWsli1RBYbKU2Uavh3iJBxBW5kYNXcwX
yKgG/cXlelv/y0M/7XRZt7sTFZBarnb9MxQQZ4/9BIsUt62xDQSUMQEVkuRN71ngcxhFYeaxujmK
OMJtvzyQFRgsUSes27sLlpvpRZqNGoFfxvLg23aZy4e7bBOtiCVE/6eLgEFs7KZ9i1WVU7R5wdzM
2kFd/HLZJD5yZvgR63QK0aa3q7MUckADPt4tcBAFSLhC6gH5eA8cuCvyE4vCTz24+oWzWQgDjUrD
qbxkYwNEJGwBRE4g6kd6GugLYhITqwSZweZyrY0kQTC0RB474A8vxst7sgkuObrAMAjXzbB3AlSC
MoNQw9guG3htGqbC0RfupQMKUQ5VWNfB7s6V39O1YCBTsEyRGUwundEeY++WtNPr7vOdyhtLEbPg
rD/VyJbOow3Z90f3nqZu7jO68PrFH8bPEnTsRul/5s6RbKeph73bFOeGZ8kYLcsTl5LpMWdVWCgZ
fFNx+/gNR6PNFwAGrcUfjKhXByWAV6wW0912RUZb5l7+sn5hdgDQoewwyUsB4PYshU1QUweuCfAJ
B+nIoVO6Z5t40xyp2eEYYoy3jM4eKZGzcWZJmRXbWy/tFb+eyvqLtciUmDV1PZEt1mVN9vMSWycP
2hyjGh6JBNrA3FmPi2FpRYFAfyClfTrll/cGKLiiJOnTTx3eCzTZIpJ6bltuoWTE5g7H62aRJRWB
3HiAtt9brZh2yUFK0o6jSdBYfDKeXYFB0eOUTMFcwaeq1tJFOZOYM85f0EuKsdyoZ8J5sT806t0q
aVWuJJjn4qUZIJkOMvMpqR7fjtL+fgHBDSKvOGs6xW9KnsNwhf0sXFOEZhx2Jkwnt+kQscn65gxm
EpsZdZqCCEE316MbvLRtXOliKTWMVYVEadfkeiMy+XQ/trgCos5pbqT0JoRXn2SVsPN0Kl19CssI
GQ4IoV7Pwle7LRtOIwQMyjCr/glIPfLBe7DO8jol35OnHlH/1pNz0GysDFbvpPAgm1iiJ56SdpFB
6/4f+RW20stbvbvB0pb744sql+biNqElIlFd35fo9ZVaIsbdJNmFVyKZXc01ch6aELIXhskxCZaW
WCzMnYw1OE2k7DxjkxFyGLgmvykhQGCKKsGKxPC5v+egkt+014V4qTocyuGZ3RV+Qfeq4zJNBVqD
sKhDoC765dvUcVn3kAlN+MFGsugl4qw8gpvp6Pi14ER7cm9Ao4vonzUKhhRnr4qguKNn97eqSBL9
STbIhfb29Ejka0f/KG5b67N7PJnEzcHK5HYBqWeIu4qE6n7lgTdrmhcxoVUY2VLyXlKc/Ni3axgm
9Fp1EGSURYaTa517hZUYkqYq5EG/a9TVOoOy4atrFJ3/btddWW6xvjwR3KevCF7AtqS/PGluVzf5
2ISWMgewxuPen98yvNag26bnsJ13f0rt8jRIT7shQTTFqjiO4eBPny4Gd8VXixVjrp6TREh7Ph61
4BIelRMZbuE61kppF5Zd+ZvemMcYDdJHukWFn8m9CXockbpzNLesinyDU2Y/4rTy9tk7ljom72SH
DqMEDVG8DM1Mbr7D7+ZfvF39KqzxeM+XDURCMozcloK6xnoJLU7rnNW6AGsU1WD2mdzSY7dxTzkN
h8YHjlg2SutlY62hMoLz3dh2w1RGIqY4Fch1ZVAZqfgk4FiLXzF2aTSubumb34pjATv84tWmtwYp
zMQgWEwRcKIKZRUPFzB0Q3BOz/IjLYGLJVf/jNq9eFqfRXlI4A7dHXAaUkCumQJtcatl6tljekKg
Lf6tZ7H3mfK0oKPagxt9yllho8AdvffDdSu7izT+MictcHCGuGoPq5e+gOKFlv0OQvpizEC0Adf7
CfNBOcNGgo7yezsC7GntVcRIiM6+Jve0kFDOCVTiqdS64GF1+5taKpgaQg4/rzqwkj+7HIe9h6z2
XeCVu2kDc+s7929DkXH3j3EYzRavJQ4hRgJWT10yyS4qFKhYK/5ZRGSESBpdThs2bLWCbz64bYXz
h74Z8kvYKGu7ZshuVaFz4NZUuiRVGOIAAgizDrdwRxGlH9/gdZpv58buuxDUoRJXUv2d5E9jqByR
D20FXbreGMsoOSf3bSLDPgIWwgHT9Llux9x26ot82olm2Rc88ZL4z9X6hgm85UfWfNorsgnb/bze
OJUmvLM1hg7Cu534vWTGp93XjskuaGBp+aYTWzcx6s4TSD5AJv8BBgI7bWZx1N0UMbNx2Fa9jcha
2Ok5QTnrVN2bOa57rCA4azQdyAg9I9xUv6g8QATweK++rbHSsDWO+q4YbY4Qme6kvnjk5qdAn1/m
lVcjwNIG51kP1kBWV6tmfVgjt5jjJfONLJofAovVgS5sBxNrlD4PlojiSKqhIjZPOguo8xDsq7zy
h7vzPXRlJXyqDecQlJSB8S5xCfeCYqOzYBl25VdmJGbNCm8n/VxEpVLU1r1RK5o1Kn1rar9zHtS9
K5/Oqms3DEzHCllhjvqccYKJfkgYiMamguEOFnMLPDGrvRaAHOLlJ1lYVq7udzkTSPyTHPNbrpFt
t3Xxjm47ZX2t8X6aW5tdTP2Xl0RR12OxjDAWkp7HwOWn+mnugzPJ7HFoz3Q73VQXHM0r5L10EPBE
c9oFvO/HGcInC6pI88u4XefJLOa5B6fHNolxbfHbhxuBl/XJ9/HiP0yIq8PKIo5tJb2Zzpci1srE
sxwLoU1IgqHNz+9fDI/25ZVw338Bs+C99ZPwsVuQYZTxmxMKP1aEzuSSjo228SZuxsMG7IeEmbvl
iNaFOVJ9ePvwsd8TukLSeq0h+0IQQXv2Gk39Cj5JYV5XZz/CmUOpqxvygSkN/eT7tk6REl94RvUf
NNMPeFFO9Zhjwi9DEule2MZgGUfikwRL7iUqBsDQELPsr2s8NepW07SLEbuO+7HnDNjz8/uukXV4
t9GiyOXN5xl6K0TS7v2rWFw+eQ7emt0TcDqNbveVuI8kVjYCJzoES/63pltTR/BB4JHLbJh57cSv
2NtUGAUSDP84OHW3b7CIm2D9BxB+PmiUY8+zYUUL3+mxF0mIILi1yjO8SliQPr1vG+aZX/u5CRGU
yoCzJTm7+h8bpePTPyOiQv/9mWSi/SPP6sk2q0jSMVmSlQCu0OPJIuInqzKH+o4UR93L8YzLPVUS
IRy7nB2dmW9ZCS3fxVwRIbWOKIAQsprzC2/TcIu2B3EX5baI6UAKptzLgDmII/SoUGg4YKTpgUUE
CnbM1fgwK90O9tLI4aMt+CXGWBXSVnTj9JKR8soDqkQy01gc3/0IGCg64/Yu9/3nZBtf9wsFM7Xw
EAXzANp9SQnrDXAkm1iBToQY6X07lzwAidxgme+2BEL4ov0oNeuc4dirZkywoFX56F5XnXwSS1to
FMKtTVp/w25r75HS+fhfLDR+wahbFwXM4FXwS/2qvjeaeUU/uNuliApdeKdFHwbKZMfDKqHOdisU
Og2Fkc/csQ7c/h/mr0nfANXgYI5TO7eAq2Wz+Ikh0OA4ljqmI5XLWBmsUYaHHXZScBGn4BEWqJ1G
eNS2lPMFxNKKwftQx//vinCNG3OcUgIWdAlQmYW/MUfiraQam2ogb/X7aJqQCn8RCfNYmhspXqg7
VYtRFKVpG9fZ6osv4M8eqVG03UCPlEXCVcq/naH1JJdSxZym4pUoVMtME2cNpNtBw8JBvggMxyn4
zSl/NUfEz9AYrDIboH3J8DDsTVfmQb4Sbr3rNBWNKLpMoyCyQwjcYvBU4yWsnbC5N/ctW/bQRrAR
lzMEjwipBoflEuQ7Yz6aPtlc0FjCpzlsOJLLaoyfVeP7hD+ZAQAuJzgkXXVfyvtdbZ5JpQmwPv5W
+dGFx7dnxKg1ykhq1Jc4KMTWIj9YVM6ZFQLPpR0eSDBzdtVHOWAvEar2XKEyaiAIHIbrTRusI03V
lXTo9eEhMdqcJ6TPh42Te4DoaT9bAivayk4/AJXUH67YU4Yu9t5/OX3FSEDKXW56rKVAEIydp7VU
jftu7csZdASU9/e5Gcj1df/6ZCbYo8cE8ewlt24Dbb82dCBG0pUZwpduE5o+UzZPKWgGnc058LbB
sMvZDqjMkzCUmgRtYibhmlhvexPeWDysZEKK4qvaVjYnpNptLCvfjXz4uIEBLArkYw7BcSxp+6Dm
Keb8S17eomDp4Rffj61OPtz2JEJcKfSYYza7zD0IDfO7P1WBgIT0LJM33N5MZkig65MmU7zpWqa2
qAD6jKOt3Qq/vYerL3yTpE8d2h+mNqCoFesqf8liRfJH/W8dcFnGWBFC8LIS3awlun5C07gNCkeA
WBG/SeOIZyf3pimv4mOG1LOdqCupsUDtrY4PTr8SdG0DP3nvyQkr3HmOqXYuWMjB7xCFz83Xo4Cu
lRf1YruemLoVNGEyA1xxE8ETtP4TH2wxW+EC0xbYHwGH1GzB2iMXz7d/QGb4Lxdg8QqKf3vLP1tX
Vl65871oROwlsdqI+HS5WxDNm7y0xfVEiuKxazr5liF7Q4bfu2Jurv9ugkOWvZH4ENU/sedZbx51
AQnaLVj0FA/BghSxiDZjB3fugKnPMp4sA2/aGZvzHo96dzUnueXkuF9xpXBac72T5WMdwy7MVerv
64IFMNKeVToPT/l+m0IWAdzFV+kl8hmEoOFFstrw6nKl2Xp3dZ8CQ+pE4JAwYD0s0iFKc/hrDPkB
56dmF95Us1Muj9pB85oKKXgSHrrahwXwZhTvGQFi8KnwQEecIKdkvOo/32K8C9MLX2wDILDoJtyh
iFzR3N/W3t1rA2NLbbPP6AaYq5uuxI4J1icTgpCVMuPAZVgzXwdlO5LCHqPrX0cy5qvX5B3bXMKE
8gw7LLzRvJDEMC2FHUdp64ezt/CNN5Wz/T6WTBGKqUZU4e3rRk6smbrtBy3HCFJAEIwP31wAn9iQ
u/+JxSqNgiyIKGW/2C2ow+UDBZl5p3HCmbX5yoult2jSetWVP+qijWpvea0Rt/RItiMMKveMCIK8
18vaVGi7a0PK9ar4WXNjSvSnCHu9Dhirju1ZazOpbu3nd43i7D4COmGMH1b+nmx1tY3zTGd5A1PH
BGt3uKNi+NlS3Rb69sgZtYVmL8ZUSv3hNCxh9jSk9FVMMwk/CwO90Gwq98d/WIAd78fQwPIn3Kal
MgVPjJNlYawVoDiG/QNTpwT8yKGTGfBbnOUVhAQKyU9hVEzTdERe63g/fzkShZPi1vVsaJS40TB7
3SmRKBelXE0lN4TuAH1rNuYtABf4Aub2NUZMRvuvG8nsTijoBgvxrxWoaiqnyAzmco1NAHNoZ1CG
lqCn0NJ1jNFjTJGzcJeFegToiusDe5jYp3VrnYPzEzqZa8A+wfw2BT4mMQdfOr+ROmEiwydDfDOd
Pq1q/ma+vZyVIFobkInHaStoE+UGyOBn0s9h1E88XedpmMWCCdkGSOVrl4VKa9PmONWFAIq+Ru55
oMris0yNafhR6TZXUG0XS6QOGCmIz6HVAit2W1T13f5CySk7jIYtq1jB8QlrwoPsiNTE8msx8cyD
YlCxZiRwPL8nUwPnBT40ZeUmQo9hmgQ0FnNveAN2kOhLxuAY7s24szeWWSe7A9lq3su5idXWktEb
zEWHM4BQZeU6wnB9mbhXjFkLvFjB3G8aNMc1ZHQhnCYDrcazVS+kwTUmUrxcxlAoV2wreUdoWy8M
sDVqgDYVPfKBPL1S5ROzsD0Re85zHvdapGaPJDAFaX1U25mMwHg5aETF1DGGf5Tk0kK1DPToOznn
wz+ZmCK718HtgqslLVQPEU5B0UbSPYxtPLjffqUQGnhvXGTOeV3EiHu83S0l2FXCuml0NoNs80bZ
e+8N59JO0zdPdVk0djs/W/ah+pVY8odjdZpjHqhTcC+rAGybVyUfqbORZHGNDBrrRI56smRMJT5K
u7qBS0TtPMfv5/uV3LxTQ0hwC6ezVhzDAwvnEBP9TFm2BcHJ98nzyTyhM5RmpSUY7VtWiW5TxGH1
8BoylGwECnr6xibI4tvfuddj7tZpLbBp3X5y+4Lwj5aSLopgqupLOB63HCoTTH4Bc6Zas2PA14Mw
Di6Qhx56agj0/VRG3mUNDWkfueVy9QFpOGJqgF/1Cpsx5MQ9VlmHX0elsbCSDxe/SXz2EvkyhoDR
UW5j7PeNoC2irqNCxHsKDI7fZ7aNzLY9jZjFmE0QWARckKtVAL7lxDjDhE75HfMLWmF+hMxjMJSn
Tp/zoeIJYxu5tEEj8nQqoRrnetCjw19MEnMGrtl+zkN4YF0P7qYqCQC3kCLLDQaKmSvVxSo99NUw
ZQm7gMap3r1sqfLMgZNrH98Fl0/1P1uGNJ1dzhJYoK9dhT47p0NjfH0kLCNDbPAI+oTyibh6+7B5
oOU4PsUhYoGoz9YlHdP+1hMzeeXaf+EqfvEHKDLRLlgTPXXKz8LCWRhedpXxAjPq4OlxMR/ksfvW
/FZqos76GWjJG6/jxqnfexSETNB1ovtwSmtQMa5qRNVuXxKZYvXl19RWbz9JMBKf5qvAWtJe8c1M
2gPmVRw05gTf8LAH7zS7W8Hu5I11r+dTBzMSeefusXgTufAm1Kgnoz78ZHhy3+cWS0Knk00DHoZX
rQq763kU9Vkqb7iqahkEDQ7dBbEm9Qb/il5uY+Z4htgTfaWKRBxFgqH/JdWDh6irzIUb+eL4liOV
Pqs6EocTITJJ9dG+VsKm6i0mqmuMDzW+0B0nD+EjCDJqdVz+w6+s1gVlL0xyClZBXlyUfLKZpUDu
ikLTR45hagO6QJTyWL4JnxIgNi560Yo2HCXraD3g1JucP+bgaWhs9KLqT9x+gYReo1YUEiAIvDFV
GeJgxHWRQMv4jbEROiVL0XkoA1MR3RvM1vhd5zXDdkE5XF3AMqp7oij+3b/4jrtz1N3+1K+f9NPN
elAdkkNP0ZdfetaB3PjkoF+NMjEWTDs/qq6Xzjwr3s1GYazCoLUBG3CLYdCcHVWKEu2T5b9ck+Dk
+LdwbX1CBRUVNaWmZbuFEwB6JrL5Q4iyjd6SIApY81cvWfL8evnKZKeAb6TQCU+24gGwsyQgwXMC
0lOGVJ8FbDqAx+E1s7knPPbC4sWCuoFxAQzaGRL2e/J+WYF7ZnHbuuImqxDj7gnbjTw+no1cQvS/
oi3RU/ZTRJ0z8tWNUl7C0VHQXRQQsjgPo9cPqKZ5PVDtYzYISnVXnhfv13pKbnrKLWjWBIVWKczV
fXDGBsf+/hyGvOK7TnMkwTwRVE6joupvKoCvJ9bPT9UJBGBMhP4pHMm5Ybp/hex04GS3df8Y9PY7
Qpo+yHdo3GyIb3lh1lfwuRtUVfIWY2THXCPFG+SuHRjs8JqlO/UPDTlrM8SRlptuhDXqCtLqouGH
3IVAJlJaoh9dDWty09PeLNjNsWwj440FOk46nbYpTIj7NKToSDIglva1ZYgajsC9EsE4tBOyTWM2
OqO7VWK6c7h4O0P9E6/4n2AmmbLq04g1WrzvKOQdzuxVGytfVXvzjxIRchkCu6t2sW19DGKMmYZQ
BprXLAnCIF/xh5B/2fgI4Q0kk+jnFHTaF9h1+OBWKKb27ZW/+qilk31iMTYFwRIfsLUXHceaK7Wb
QlcTLdEaFFUi7kWukUhSoVCWrnrcJVYkpEwF90DPVJTPROwd5cPIscuxPbi7js7mGqjws+Yn/mtQ
+EbbaKea6RT9oet0qSmkE0GCzQaklqbsuKb6xRhyRBoKB07/DYXPzgO55rEQj/CKszUwssUTLWPE
oMFxijbzBXn1eW1XeVLGS0nWLLXjnq7s/1N5YiZ5s+Emtdt8Q9B8Vws2S689ni6D7/TnVkve/soW
7xGX6YMDmLaVFvL2/OwqhbRVT3W5xpLORkrOVlGjcBO9KGGfhl6j2Oz9IxB1ANw0sDiyooeeqBBw
lgNZIGoGuu35hSrm2/2a8QcCuKzckXtUaF5aUz/Z///ZeWR8YCahoNy7WnJ/eIQaX+Xy7zhF8U/d
AVDdJBdGZfLovokwShWhqDHqtFXqJL5r1tKQH8oEFEto76EObLSOi/AzzmsLsBWytj8W9/CqUB3E
pWUO1faS2kvbdbsGesMIKv3jtwT4GJVUVkIaSLnlgeNew5+rb7odvNNcl6dBkvYd3TmUGk+ezdVa
qq3EWKK35Ov+ZQQvIfdmm0OWBVgQcvYrCZOaS6KJRp5pIuTMSCrkb+Cl1o3M4HIrWQybnFwkV9st
aehfYvpE+biffa7JcLLSC2pLXViknYmNPB2mFODPkWVZi3sWkuQ76sS5l+GBElHAZE5IVivqpT2H
annghf19RI7wCgKZo2A23YRNTD3k4IwR2iC5Dhb20HZ1IKsIWjTMd0FMw7zv5hHFSu8EI/hO93/u
z48tTHwm3K35yQwzayWxyZa1saqTd5t8h3Tk5l4UWQZsENz+b7tCXe+1lPr6Z9cutcN7krVZyKU1
Lb3+GT7kR4dmuqz9pWtKigod+RsPt5RAytxAofXFekYXXF4AsyqO7x+gvsmUwPgXZ/O42w39FbeG
1BXwMPmerHfJl6DwZaTb45WgA0t+iVmsp13FHujo4U9hLOMWTN63HWiJzoloP0xDVnoEwzEfhCiU
Nq+bdPlsboRV+Jo81Zq2nAkAw+bCq6KjdSA11CMa/cBkvLqOc1QtXHRUQXa00JMJHum/lCGvo/sC
/MqhC5wTLnw7rMICmaL/d0l44IF0Mzqg+x0yImkdszfzHzeBBzCVqTFFR3ePnQNeLrFWOE5eOlFo
NU1+KUnoArOHkEUxNqt+XngMJ/frRBt1ZH6kxg4J5z9XE1vGd6WHPICAzl6gTfDFI2H7qdFqXO4W
1VKb/uDYzz1WCubD9AUKDJsvsInSHIQBCDIBWNr+0O2h8DRIEhM7jToslqxLaXGMPRpcrLXU4Jm8
C7Pi3DnNx/v4ovsqUJeM72nVqiFDnZUMJd7j8vCyoP8PcDq1VZWu0xEsbvpsSDwionQxhURpmraZ
5hn+IjzlPUCZ6NeiJ45M2R1mY0w92XNh0w9w5mjxUQRRIouehcud7wOQPl3XCHc6TEo05zFDjq1U
Yk6lSk15/+hpjJyMJb4vqhdQvC4+R1NB4mjkRSkTbsz7pFuB/cgwFXg45WMCajp92iWLKCMBkS9a
oDgNaiyrO8gyGnt+ROGuz+W5A1T2JmF/p9YTLqHwnwt7MnmxlbWhi2ih6n8a+RHbyUSUtaSxaAz2
c7hh08C7GbiyGvkYzEN+sL/FDjhdwyoSRVKs9bNVfA9r72ED2CgkL0HVh7jHdyKLCBfAiy131LjX
ZTtps8mcgwdVz4XClQcWdQ0bxe0NPWLVNPpDkQSXqxpuKvluS5aPQ6rwjLMAKC9YcMu7rrVQPcT5
/nzU00dEC2KscXZ6yOSZGRQeCPtOvJtHS6D1zj5Wt+hvTtwej5oHfOH7TqtnW9K9AxuFv5AUzHXd
YklCy6cqhbEd9wj73P966pSFlTMrDHnvMFYLJ8benJVQcdR1XLDyVVcpTYyET/aVyY7McCJBAMb1
ZxgKxFInfJZlk5ZRI1BWI+3jJPbXponA6SQm9DTqxJ27Kcz6yzS1tVK5rsINy+SqfztJWkaWrrHt
XHxLMn10IU7hKZz48+F4oz6MUjOHyDsHrSX6Jrbr4YKzRYLgV44rDETD5H4m+G7KHC4+R8m6XDHG
b6eCAkIXw8fJlSYLRD1qRODt3GGCWbTUvDPULaY1t7wu/7zsQOi+gwFMBwDiRnNs5U4AKLpzysn6
4xc3j1JlBlBN8TVX+8xvkQdJ9mB9Zc9yHIsmwsyUfWisqeax5y5+yh93eKhRG+w6fcOTIW8vEl+d
BgwKBlc5Bk9NnHvZifb6HynJHBw8BDpkzIm//xWpsjT/b/R/z0ddJC8RkRDs9NDYI1ARDW3viyO2
H0bvwnXhu+MhYRhIwpaJkhYN54VsbOtKo0/5+QG912RhlOpKb1eSHqHC9Qf1IGhec9Wl2QzV4Xla
hu0DecRy4//0CJb6qyBSK1Jbj8D8GWA3vAwukHQp/Im3kExWzrdTM0LQ8A/zdUV6fqLVUMI3gRY0
c55dRjrc5EqmSGoXTtmYG3J8qLwSW8YYScU7bY1EePn+L1rXGgaYZS6AsAmS4th7bOFfRwmtfBWl
bH8P20aEW7MEwLJcEyQsIuTS2SUAztq+EFoBFkDdcc4ZtTYgIgmkC1MyWppeaKLiK4sbXVE4ywm5
AP+B+f98Qvn8HzgDJ1AuG/cMZiNJhxgFSFJdQdD4MgdioslU94WVPlEh4QtCKEEit93Ejb9aH+ow
3AszJYIzyjp4bIP2S4yL2OxJ1FtWS0tVSUlRudpUpuBe7HSLE40CxnSfE8PgHrzFnpImxTTddOci
LMopOlp8WVbcNBAYHFVJD/5bEiYsETAFoH+FzxPr8h+iGtxZeZeqhOUcpkrMeoDS+FkymMU6iXcV
epZsYxhTrPIobbitskViCxCtU/u4VagMtXllAygAx833YVhGLcwnulaFDYZZEFj8IK/ona8/KduV
EM+ljxsaXZ64npqvk9Fc7z6izROMUHQu8TKloZf0o6GiGAI6sVScBqx17Uwutm//6inGIhVd0zTF
JDJzdFFZjN+gv4f4ae0t/xs3oXFQpuqXFEv+78Pst8UnZjyvO5/UPvFHK//2V71d2yekxBYZ2+LV
E9aXJlM7Hp8H3ea0edjLnZBkeEmB4/tndMQuPnZUFhM1hyNg0uIuexkS6MLmz7dns85+ojFS/snI
o1s8AitWnHo1BBy9m52KcZ6eg2YpokLGRd/eL4yNvxk9vTkNUXm3OXhnsdpSrbtKzRJfoA4xt1jV
GC7BC3/qoIX/xlwNwylgug7X2iYACj4iDhoSAJ1GiWMelDcAMvNuVW7QNO5y0A0wUHfJ9zdp9J2g
w1DdGAnrHZYZKbAIJjdVGVRFiaQ9cw3Tu8TqnbczisK6P5nvvV6CxYuxL6lE+0f+waP+96QeNq0s
9rK4MzcWCsme4bVFbCZB7a3ssvyBUOlhFIxVBSZCBjVO7Se62Zu/Xm2xYvrF6MlRqU7FSh8o5s8p
HtwcF8cGT//QZrpPb4ywWObDBPaCcKtRS7WKNzYCY61E/f5+MytGY3CU08Fa3gz9iNtBojnzRYNl
QmJDA4gbIQjDXlaFgvTP+pZZWrm4dIggPtoqflG+IMXkJfmuBHpPlUtYjlP4uM75hiZGy0C0/b62
hp5kuHrjEJJr2PavsH/sv34EYtck2wMo/RrwioPuDDmnCJR6p08yphkOOQiUXP0y1MZCtz0rh9kR
72FvcXHY87ovPlO9whNBkaex0LI2btK1MVAjQdS9b6BXiCBZB0gfM15aYUwu5uBSouJOswWtpZJk
Z/bue+47H+IPaq0vWcN28MPC32h84qd960Pb6G1Ei2uyic7r7OcsT4mk6tUxA+yjgDg5WgcerAbj
BIhAYAjcJpp6WtBUsqtOyYpmiyr1WNMJaKb+xk4a5BRSlExnDdQmN2NxDlOImfQ7EzrFLbRdvWSQ
HaKUjY4mVcNCCwmImGUCS/MlURfMn6Zq51hu7lENfUrNchrk0tIeg1tCkH8pjez8bgy+inKB4OTd
jrYDyX5o2NwVIb24LiuX4jkxNlNxmZ2kN44UH7BiTmn/NoPmTTafdpmaMtDRfdTrNjOyk/zWgDOX
ZCZSpjBAfXKXYtPh4Y05j7ivZpbhgYoNIt6G3eUAhv+qu/yuQT5Smwo04wGJZSNN0mLtYkbFknzh
M0DyDyKVLZmbMdkXiID7xV/z7bF60mhQkp3Qh8cLT5vYKOLYx7/hoaOOwl9PgMngfbDMK4sQgPrq
JAvjC8aH/AOQOVHVzbM/BEn07k7+XkkvjbD29rkH5bt/+X5dgaRYEnKh4xxMInMQbeeMuGj6e7l8
Oo1R4AxQA2qnPJ1dfNB0HvoC3v8Yjit+NaTLdXyRUKvFVsVw5pip7zGmBhjH3MtgRAB486FsGtU0
hUZjREvJelLp+IQac0H014wN0hjlOMDT8WYOg7k6pGXcNovnYn2ciszjqCq9d6Brel34Ty6LGa7t
Xlo0KFpgbwzMOCur8oy+1SGdUpeM6Sz/c7PkoKKgzR9Zg1QpJ9JkFkYMNdoQ7zaBLcchax4CmaDn
IVHubptsbvR01zgtH9kE2FbM+NcKUnUJoEnF2UfN985LJ/OL1Hsv7fhA/CfI9E4/7aTSqIEcpVtD
Aua2ahSiVolzoUuhP25Nu4dMJJCRSLXWjNrKO5iLrC4nuDxuqxAfgac3lQEWkCQQDWaGL1YbHNvM
aaZq6Igwj8XXcATMNkZXXzdSpeJ+ePmiPc4vc8bmPLzZ5CxtomP0e8AWMX5iNp2AGYzqy8OmRVpr
OG2s/k0S/WrzXzkNJSjx89hhfFiqq7/qeVwWLd5qta9C40RIj5DmOkVGYwREPVcZytpN+jpWSG2L
z4l0nDaEMRsIrjxg/r8AYoR0hfNwFjVEFDdzMtNDTDnDF0cwcn9agglFeFENp+bEXfkgTdrj4YhB
jNd4v3Tzv4dAXBWn0EFOMdHDtobO4IrZOjgMAx7iM4LPtd6XK4ZQI7YC+dOo+ZQ3NI2qaj4/qZkM
ROWm7ZKNnR8hEGqBruYgwIkrGp7cwySF5m0WYZcQ2IebgDzOODfBBYCrbDb/nKIMCAPOrmpuc2+G
w0qfBAXh474aA1N6NHiYvsxlNyUTPOrbZYIsGB4kx8ikNHq6B7gTeT6YpuiIxO0/Jyy4D+vPbVG5
/lQ/OdOPO5RW5gkHBJ10xuxh93gtnS5a679eDya9zAxraaVcJaOpRwP8d0btpNe3c53iCs+Pg5KL
Z+PGgCVEvNKE958IUbCqV8K0v+n9vMMR5YaNTh0K1gaVpRA3UZKnESZWG1EvfFORFyNhOm9OTgAD
ASl5+8HcLdXF6E6wi0htd4CHj8+zLHnF1Wef/Dz3GndIDfgE5TDw98zIeGlPySGhpcT3jmsx+Fu/
tWPJIPcIyfAFMpwZx81VWf4s0bXrsFLZRlkQ8+Qxa7xgHzkctcX64xBmu5dyaZ4FBGD8ormX3HVy
4sibJHWGQRzqK521inFz+dSznqel2pyoIuA6brt9clzLM8Td2bD4bhpPuVxisIBStxok8FKh3sF0
I4MO8YT7Lc5+H9r+mpH4jrkIbpKrjsX4FyBOvnVAu0OhrqxAiwbaUl7ugJrGxGhk/XJpJYhkdpj5
luIndKU2GdPViX0F38Fy0XUnhZwmOkO/ef40KaqOHHuUQ3n5seA6Ntnmy9kAHrcshFTs301uiLhk
c1ixlyNS/IDeAs0SznmVP71ntJyny8ixTYkAVP5c3dST+gLK08mkxXGcPIoFL1K3DvNa9S6fkB2D
2ekilSOxPbyN/ugcpoBuRml0UVmOTdSMpVMpNUxtpdUKPcdagp7EalQzuj7sS25Vsaa0obqcaymF
6+RsgX26SnEfHnPlMY0YodPXX8f6yhe1wy1lHVX7HVoPdJq9t4JzZQhqMc89129k1JneQtCRPoXt
9vCUNeauvkX5orm2bA2pvoswftpo/HkRrjhIM8C+hr6XjJgEXCWzH7NEQq8jQqByeyrrXfx4S5T+
jPw7EDETavGPziJ8TegYg40pi1NIyEaliqEd8oPR85s3KhMZOkKt8n7WmjARlDRXAeVB4FKjzzzZ
ZlqPS7Fg2Fp29JnZpDjQ/hQXcHNgtrDWKnPg5jPN+zrjZK3DOP0M3HPsn0bwS3A7rCNO3nvbL9Zo
/s8NER5BCsiu0Pkt+KIgkiJQtB8LLhKRw8xZvrtBC7z6sDtYbyghMwcK3tqKo+xfoJl4hXGGFH6E
iiQrOV1gocBrRWk4n/w+WZDv5dG+JYy8zMpJ3zQkFAOiwFvvsUXYH116BMa5+XHyLcOLG+R1nzNo
hzL2YpynUbR2JUCLrlUPjZY5ycoiw8JXxBYzhVjvc5dd25zplqy24pPPcFqGqL9kiJSyRQBL+eDV
sXNOUeK9sCWyDDzw+5fVWqvg+e2BEfsRj//wZFmIhA7X04fRy3gySU4yicaf8fObFPKPIZg7Z2G9
Wg2HdTalosj3XNyNZ7cbma9RZuALgafpupL/fYPkz0vG8IrkkjQ/ymanXbb46VRlXv3rK2Z34zZU
O6l7rSo+aNweK1OLR0fgAKdsBXCaS1zLd0nV9eISQzogL8oDX/A9GzCkAiRvKwzGNmzMvfZSzg5s
uoJYUfpe4DLirhrRlVS00p4oZ5JVhIjHABIPEq5SN586sRahC8I2RoQY8Vp+aL2CXZj0Z1LfsKF1
ODP1p0BIFdUNYnkuQDu1dZP310PglpJk62XP+vzmn48kR5579AmtXhfLCLUJBe5gYppEkWofGgXM
0ilR/fNjCNpjOhk37QPDC4J7zXS1M/EHyQDeJ5Hu07iAiA06Zr8NLdk03BF0mOfJIBeUWzd6MLpu
ZLyxMM4nBErBrl4E7s1rgxu/sfqYoyIwBOVyn6RwQrH/jTvQrYdDdFZ0tKwZUEggXavym6IfiAqu
3Eirp5RE71FxqXPuFXAkKZTx9jxOurV0CXCoI0bK8341zR6WLY6BPWBmdgN+yRd8Cu+3ydOYzd/y
WnJT9ck6a7vceFZaKnNQpgsKK35PFPO9eyaPkLPMkT9tLSLpfppCyRQ8uoWD98JXtjn81BUEtb4P
gkq75uU97wZLrol0TNDkq5BLBFqhocmxwRntolkZtLiCMmJn8/xfKYVXOcEHZV8FI39/4fhSnC1x
o/Rol5TuLYy4l4xrbdRnhyksDqDol2ltykz5kEaD5tuharJ3nw+33BUlqoRyqhMdYYbveCCbwudh
Lo4lqgkKlrupLhmemtHu3JOjfEzEs6CiJziCNYUrsJOycEo3PDVKS0CvdJfD35saqfisvZ8b+Te1
UX4SeBBUsL+ShCDYYyqCXaOnE7Kl25xvNRGEAQPaM26S810Y5deLwrSlW1qEXkrTwtAHJwjB6QXa
5wm+3GRG78DpPH8OwX1zNysej9vDh5i8tQ36uRaK7//mAUfyWeNpzyHn9OhBZ8ClLzfsw1zWW7Oz
UCfHoeMVDMk5JCJb1y9Y3Bqa29/pKMYVITo+KH5iKZTRoyMaWjYF4XwUCLd5O38LSYys1Kco05xv
bbnfnAqdais0LoUxOdg58VWngNQF7FyYlUPmoaHN3AacRWF7jMWSLPlCTLEv7ao5mP+MBHuSUlhi
xgXIShQp3sCMnAreQ0Zm/804vmm2OV56ulzpW7gO2ex4YwlLd2SKj+mcn4CHKCwAIlduu6F9gk9H
36Cfh1bVnMNwpzwUg/ecvh/nRhHmiQjgwh4k4QTMM2nrNCsr2+NHiT7Z1j65COgOz66c3t0vXyhZ
tvacnoi5u9IwhvmNqLhvFXzdtG9BbZ/jVO7HNSpt02dyZDlGJDrXHkIrz7pxhn18qdQlFH3a7ZKh
DT7A3ZZ8hv1cFiUam5aINvqHABzmJRHpj9OnkhDClWrdrEBntUZJvgNzM/LopM17ULB1IQFdr0rv
WKVhl2gLZ8f3HsF4eO5cYjzxLfL9G+y1c00aqQUEEknIcNPeGUKFMLx2Fk4UH0ExUpdw+gXU3IjN
aQVTgB8Fc5cD9bLt5ZlR15qDUEWnKaMbm0ihKbnzwuFM3MHWZ1V+fsZLl9FBmyn0NxR2mKhnkXRr
XOzmeByhz6WsHOmLubjJlhnG72rkjY7SM0cvedxib9TqXJtIkeUuNeLf3Wf1PLcXReuTAqSn8QZi
M5co2lmQNSASgkFRgTwaiva5oGluLZ59OXt3wG8jiB8Jtg/8fJzDGFcWy78=
`protect end_protected
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_e_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_e_e-e.vhd,v 1.1 2004/04/06 10:49:54 wig Exp $
-- $Date: 2004/04/06 10:49:54 $
-- $Log: inst_e_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:49:54 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_e_e
--
entity inst_e_e is
-- Generics:
-- No Generated Generics for Entity inst_e_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_e_e
cgs_ramclk : out std_ulogic;
p_mix_nreset_go : out std_ulogic;
si_vclkx2 : in std_ulogic;
tmu_dac_reset : out std_ulogic;
vclkl27 : out std_ulogic
-- End of Generated Port for Entity inst_e_e
);
end inst_e_e;
--
-- End of Generated Entity inst_e_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x01p01n02i00313ent IS
END c03s01b04x01p01n02i00313ent;
ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
constant C1 : REAL := -1.0E38 ;
constant C2 : REAL := +1.0E38 ;
BEGIN
TESTING: PROCESS
variable k1 : real;
variable k2 : real;
BEGIN
k1 := C1;
k2 := C2;
assert NOT(k1=C1 and k2=C2)
report "***PASSED TEST: c03s01b04x01p01n02i00313"
severity NOTE;
assert (k1=C1 and k2=C2)
report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x01p01n02i00313arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x01p01n02i00313ent IS
END c03s01b04x01p01n02i00313ent;
ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
constant C1 : REAL := -1.0E38 ;
constant C2 : REAL := +1.0E38 ;
BEGIN
TESTING: PROCESS
variable k1 : real;
variable k2 : real;
BEGIN
k1 := C1;
k2 := C2;
assert NOT(k1=C1 and k2=C2)
report "***PASSED TEST: c03s01b04x01p01n02i00313"
severity NOTE;
assert (k1=C1 and k2=C2)
report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x01p01n02i00313arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc313.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x01p01n02i00313ent IS
END c03s01b04x01p01n02i00313ent;
ARCHITECTURE c03s01b04x01p01n02i00313arch OF c03s01b04x01p01n02i00313ent IS
constant C1 : REAL := -1.0E38 ;
constant C2 : REAL := +1.0E38 ;
BEGIN
TESTING: PROCESS
variable k1 : real;
variable k2 : real;
BEGIN
k1 := C1;
k2 := C2;
assert NOT(k1=C1 and k2=C2)
report "***PASSED TEST: c03s01b04x01p01n02i00313"
severity NOTE;
assert (k1=C1 and k2=C2)
report "***FAILED TEST: c03s01b04x01p01n02i00313 - The range of REAL is host-independent, but it is guaranteed to include the range -1E38 to +1E38."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x01p01n02i00313arch;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
CONTROL : out std_logic_vector(7 downto 0);
KEYB_A : in std_logic_vector(7 downto 0);
KEYB_A2 : in std_logic_vector(3 downto 0);
KEYB_D : out std_logic_vector(7 downto 0);
KEYB_D2 : out std_logic_vector(3 downto 0));
end keyboard;
architecture Behavioral of keyboard is
signal CODE : std_logic_vector(7 downto 0);
signal DONE : std_logic;
signal ERROR : std_logic;
signal KEY_REL : std_logic;
signal KEY_EXT : std_logic;
type Matrix_Image is array (natural range <>) of std_logic_vector(7 downto 0);
signal Matrix : Matrix_Image(0 to 7);
type Matrix2_Image is array (natural range <>) of std_logic_vector(3 downto 0);
signal Matrix2 : Matrix2_Image(0 to 3);
begin
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => not RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
DECODER : process(CLK)
variable KEY : std_logic_vector(10 downto 0);
variable KEY2 : std_logic_vector(5 downto 0);
begin
if rising_edge(CLK) then
if RESET = '0' then
Matrix <= (others => (others => '0'));
KEY_REL <= '0';
KEY_EXT <= '0';
CONTROL <= "00000000";
else
CONTROL <= "00000000";
if DONE = '1' then -- ScanCode Readed
if CODE = X"F0" then -- Key Released
KEY_REL <= '1';
elsif CODE = X"E0" then -- Extended Key
KEY_EXT <= '1';
else
KEY := (others => '0');
KEY2 := (others => '0');
case CODE is
when x"1C" => KEY := "11000010000"; -- A
when x"32" => KEY := "01100000010"; -- B
when x"21" => KEY := "10110000000"; -- C
when x"23" => KEY := "01010000000"; -- D
when x"24" => KEY := "10100010000"; -- E
when x"2B" => KEY := "11010000000"; -- F
when x"34" => KEY := "00100000001"; -- G
when x"33" => KEY := "00101000000"; -- H
when x"43" => KEY := "11100100000"; -- I
when x"3B" => KEY := "10100000100"; -- J
when x"42" => KEY := "10100100000"; -- K
when x"4B" => KEY := "01000000100"; -- L
when x"3A" => KEY := "11101000000"; -- M
when x"31" => KEY := "10100001000"; -- N
when x"44" => KEY := "01000000010"; -- O
when x"4D" => KEY := "11000001000"; -- P
when x"15" => KEY := "11100000010"; -- Q
when x"2D" => KEY := "01000000001"; -- R
when x"1B" => KEY := "11110000000"; -- S
when x"2C" => KEY := "11100010000"; -- T
when x"3C" => KEY := "10101000000"; -- U
when x"2A" => KEY := "01001000000"; -- V
when x"1D" => KEY := "11000100000"; -- W
when x"22" => KEY := "11100001000"; -- X
when x"35" => KEY := "11001000000"; -- Y
when x"1A" => KEY := "00110000000"; -- Z
when x"16" => KEY := "10010000000"; -- 1
when x"1E" => KEY := "10001000000"; -- 2
when x"26" => KEY := "10000100000"; -- 3
when x"25" => KEY := "10000010000"; -- 4
when x"2E" => KEY := "10000001000"; -- 5
when x"36" => KEY := "00000000001"; -- 6
when x"3D" => KEY := "00000000010"; -- 7
when x"3E" => KEY := "00000000100"; -- 8
when x"46" => KEY := "00010000000"; -- 9
when x"45" => KEY := "00001000000"; -- 0
when x"29" => KEY := "01100000001"; -- SPACE
when x"66" => KEY := "01000001000"; -- PACKSPACE | ZB
when x"5A" => KEY := "00100001000"; -- ENTER | WK
when x"58" => KEY := "11000000100"; -- CAPS LOCK | SU
when x"12" => KEY := "11100000001"; -- LEFT SHIFT | NR
when x"59" => KEY := "01100001000"; -- RIGHT SHIFT | WR
when x"0D" => KEY := "00000010000"; -- TAB
when x"41" => KEY := "01110000000"; -- ,
when x"49" => KEY := "01000010000"; -- .
when x"4E" => KEY := "00000100000"; -- -
when x"5D" => KEY := "01000100000"; -- \
when x"55" => KEY := "11100000100"; -- = | ^
when x"0E" => KEY := "00100100000"; -- ' | :
when x"54" => KEY := "00100000010"; -- [
-- when x"76" => KEY := "10000000001"; -- | STR
-- when x"76" => KEY := "10000000001"; -- | @
when x"5B" => KEY := "00100000100"; -- ]
when x"4C" => KEY := "11000000001"; -- ;
when x"4A" => KEY := "01101000000"; -- /
when x"0B" => KEY := "10000000010"; -- F6 | [G]
when x"83" => KEY := "10000000100"; -- F7 | [B]
when x"11" =>
if KEY_EXT = '1' then
KEY := "00100010000"; -- RIGHT ALT | PS
else
KEY := "00000001000"; -- LEFT ALT | GT
end if;
when x"14" =>
if KEY_EXT = '1' then
KEY := "01100100000"; -- RIGHT CTRL | LAT
else
KEY := "11000000010"; -- LEFT CTRL | RUS
end if;
when x"76" => KEY2 := "010010"; -- ESC | F0
when x"05" => KEY2 := "010100"; -- F1
when x"06" => KEY2 := "011000"; -- F2
when x"04" => KEY2 := "101000"; -- F3
when x"0C" => KEY2 := "100100"; -- F4
when x"03" => KEY2 := "100010"; -- F5
when x"0A" => KEY2 := "001000"; -- F8 | [R]
when x"01" => KEY2 := "000100"; -- F9 | DIN
when x"09" => KEY2 := "000010"; -- F10 | CD
when x"78" => KEY2 := "000001"; -- F11 | P4
when x"07" => KEY2 := "010001"; -- F12 | P/D
when x"74" =>
if KEY_EXT = '1' then
KEY2 := "110001"; -- RIGHT
end if;
when x"75" =>
if KEY_EXT = '1' then
KEY2 := "110010"; -- UP
end if;
when x"6B" =>
if KEY_EXT = '1' then
KEY2 := "110100"; -- LEFT
end if;
when x"72" =>
if KEY_EXT = '1' then
KEY2 := "111000"; -- DOWN
end if;
when x"71" =>
if KEY_EXT = '1' then
KEY2 := "100001"; -- DEL | DIA
end if;
when x"7e" =>
if KEY_REL = '0' then
CONTROL(0) <= '1';
end if;
when OTHERS => NULL;
end case;
if KEY_REL = '0' then
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) or
std_logic_vector(unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) or
std_logic_vector(unsigned(KEY2(3 downto 0)));
else
Matrix(to_integer(unsigned(KEY(10 downto 8)))) <=
Matrix(to_integer(unsigned(KEY(10 downto 8)))) and
std_logic_vector(not unsigned(KEY(7 downto 0)));
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) <=
Matrix2(to_integer(unsigned(KEY2(5 downto 4)))) and
std_logic_vector(not unsigned(KEY2(3 downto 0)));
end if;
KEY_REL <= '0';
KEY_EXT <= '0';
end if;
end if;
end if;
end if;
end process;
KEYB_D <= not Matrix(0) when KEYB_A(0) = '0' else
not Matrix(1) when KEYB_A(1) = '0' else
not Matrix(2) when KEYB_A(2) = '0' else
not Matrix(3) when KEYB_A(3) = '0' else
not Matrix(4) when KEYB_A(4) = '0' else
not Matrix(5) when KEYB_A(5) = '0' else
not Matrix(6) when KEYB_A(6) = '0' else
not Matrix(7) when KEYB_A(7) = '0' else
"11111111";
KEYB_D2<= not Matrix2(0) when KEYB_A2(0) = '0' else
not Matrix2(1) when KEYB_A2(1) = '0' else
not Matrix2(2) when KEYB_A2(2) = '0' else
not Matrix2(3) when KEYB_A2(3) = '0' else
"1111";
end Behavioral;
|
-- Automatically generated VHDL-93
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.MATH_REAL.ALL;
use std.textio.all;
use work.all;
use work.mac_types.all;
entity mac_mealy is
port(w2 : in mac_types.tup2;
-- clock
system1000 : in std_logic;
-- asynchronous reset: active low
system1000_rstn : in std_logic;
result : out signed(8 downto 0));
end;
architecture structural of mac_mealy is
signal y : signed(8 downto 0);
signal result_0 : mac_types.tup2;
signal tup_case_alt : mac_types.tup2;
signal tup_app_arg : signed(8 downto 0);
signal x : signed(8 downto 0);
signal tup_app_arg_0 : signed(8 downto 0);
signal x_app_arg : signed(8 downto 0);
signal x_0 : signed(8 downto 0);
signal y_0 : signed(8 downto 0);
signal x_1 : signed(8 downto 0);
begin
result <= y;
y <= result_0.tup2_sel1;
result_0 <= tup_case_alt;
tup_case_alt <= (tup2_sel0 => tup_app_arg
,tup2_sel1 => x);
tup_app_arg <= x + tup_app_arg_0;
-- register begin
mac_mealy_register : process(system1000,system1000_rstn)
begin
if system1000_rstn = '0' then
x <= to_signed(0,9);
elsif rising_edge(system1000) then
x <= x_app_arg;
end if;
end process;
-- register end
tup_app_arg_0 <= resize(x_0 * y_0, 9);
x_app_arg <= x_1;
x_0 <= w2.tup2_sel0;
y_0 <= w2.tup2_sel1;
x_1 <= result_0.tup2_sel0;
end;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: data_path - Behavioral
-- Create Date: 13:24:10 10/29/2009
-- Description: the data path of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
use work.common.ALL;
entity data_path is
port( I_CLK : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector( 7 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic);
end data_path;
architecture Behavioral of data_path is
component alu
port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_D : in std_logic_vector(15 downto 0);
I_D0 : in std_logic;
I_DIN : in std_logic_vector( 7 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector( 7 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_R : in std_logic_vector(15 downto 0);
I_R0 : in std_logic;
I_RSEL : in std_logic_vector( 1 downto 0);
Q_FLAGS : out std_logic_vector( 9 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal A_DOUT : std_logic_vector(15 downto 0);
signal A_FLAGS : std_logic_vector( 9 downto 0);
component register_file
port ( I_CLK : in std_logic;
I_AMOD : in std_logic_vector( 5 downto 0);
I_COND : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_RRRR : in std_logic_vector( 4 downto 1);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic;
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_CC : out std_logic;
Q_D : out std_logic_vector(15 downto 0);
Q_FLAGS : out std_logic_vector( 7 downto 0);
Q_R : out std_logic_vector(15 downto 0);
Q_S : out std_logic_vector( 7 downto 0);
Q_Z : out std_logic_vector(15 downto 0));
end component;
signal F_ADR : std_logic_vector(15 downto 0);
signal F_CC : std_logic;
signal F_D : std_logic_vector(15 downto 0);
signal F_FLAGS : std_logic_vector( 7 downto 0);
signal F_R : std_logic_vector(15 downto 0);
signal F_S : std_logic_vector( 7 downto 0);
signal F_Z : std_logic_vector(15 downto 0);
component data_mem
port ( I_CLK : in std_logic;
I_ADR : in std_logic_vector(10 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_WE : in std_logic_vector( 1 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal M_DOUT : std_logic_vector(15 downto 0);
signal L_DIN : std_logic_vector( 7 downto 0);
signal L_WE_SRAM : std_logic_vector( 1 downto 0);
signal L_FLAGS_98 : std_logic_vector( 9 downto 8);
begin
alui : alu
port map( I_ALU_OP => I_ALU_OP,
I_BIT => I_BIT,
I_D => F_D,
I_D0 => I_DDDDD(0),
I_DIN => L_DIN,
I_FLAGS => F_FLAGS,
I_IMM => I_IMM(7 downto 0),
I_PC => I_PC,
I_R => F_R,
I_R0 => I_RRRRR(0),
I_RSEL => I_RSEL,
Q_FLAGS => A_FLAGS,
Q_DOUT => A_DOUT);
regs : register_file
port map( I_CLK => I_CLK,
I_AMOD => I_AMOD,
I_COND(3) => I_OPC(10),
I_COND(2 downto 0)=> I_OPC(2 downto 0),
I_DDDDD => I_DDDDD,
I_DIN => A_DOUT,
I_FLAGS => A_FLAGS(7 downto 0),
I_IMM => I_IMM,
I_RRRR => I_RRRRR(4 downto 1),
I_WE_01 => I_WE_01,
I_WE_D => I_WE_D,
I_WE_F => I_WE_F,
I_WE_M => I_WE_M(0),
I_WE_XYZS => I_WE_XYZS,
Q_ADR => F_ADR,
Q_CC => F_CC,
Q_D => F_D,
Q_FLAGS => F_FLAGS,
Q_R => F_R,
Q_S => F_S, -- Q_Rxx(F_ADR)
Q_Z => F_Z);
sram : data_mem
port map( I_CLK => I_CLK,
I_ADR => F_ADR(10 downto 0),
I_DIN => A_DOUT,
I_WE => L_WE_SRAM,
Q_DOUT => M_DOUT);
-- remember A_FLAGS(9 downto 8) (within the current instruction).
--
flg98: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
L_FLAGS_98 <= A_FLAGS(9 downto 8);
end if;
end process;
-- whether PC shall be loaded with NEW_PC or not.
-- I.e. if a branch shall be taken or not.
--
process(I_PC_OP, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)
when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR
when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z
when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack
when others => Q_LOAD_PC <= '0'; -- no.
end case;
end process;
-- whether the next instruction shall be skipped or not.
--
process(I_PC_OP, L_FLAGS_98, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_SKIP <= F_CC; -- if cond met
when PC_LD_I => Q_SKIP <= '1'; -- yes
when PC_LD_Z => Q_SKIP <= '1'; -- yes
when PC_LD_S => Q_SKIP <= '1'; -- yes
when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set
when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set
when others => Q_SKIP <= '0'; -- no.
end case;
end process;
Q_ADR <= F_ADR;
Q_DOUT <= A_DOUT(7 downto 0);
Q_INT_ENA <= A_FLAGS(7);
Q_OPC <= I_OPC;
Q_PC <= I_PC;
Q_RD_IO <= '0' when (F_ADR < X"20")
else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
else '0';
Q_WE_IO <= '0' when (F_ADR < X"20")
else I_WE_M(0) when (F_ADR < X"5D")
else '0';
L_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;
L_DIN <= I_DIN when (I_PMS = '1')
else F_S when (F_ADR < X"0020")
else I_DIN when (F_ADR < X"005D")
else F_S when (F_ADR < X"0060")
else M_DOUT(7 downto 0);
-- compute potential new PC value from Z, (SP), or IMM.
--
Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL
else M_DOUT when I_PC_OP = PC_LD_S -- RET, RETI
else I_JADR; -- JMP adr
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- Copyright (C) 2009, 2010 Dr. Juergen Sauermann
--
-- This code is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this code (see the file named COPYING).
-- If not, see http://www.gnu.org/licenses/.
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
--
-- Module Name: data_path - Behavioral
-- Create Date: 13:24:10 10/29/2009
-- Description: the data path of a CPU.
--
-------------------------------------------------------------------------------
--
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_ARITH.ALL;
use IEEE.std_logic_UNSIGNED.ALL;
use work.common.ALL;
entity data_path is
port( I_CLK : in std_logic;
I_ALU_OP : in std_logic_vector( 4 downto 0);
I_AMOD : in std_logic_vector( 5 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_JADR : in std_logic_vector(15 downto 0);
I_OPC : in std_logic_vector(15 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_PC_OP : in std_logic_vector( 2 downto 0);
I_PMS : in std_logic; -- program memory select
I_RD_M : in std_logic;
I_RRRRR : in std_logic_vector( 4 downto 0);
I_RSEL : in std_logic_vector( 1 downto 0);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic_vector( 1 downto 0);
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_DOUT : out std_logic_vector( 7 downto 0);
Q_INT_ENA : out std_logic;
Q_LOAD_PC : out std_logic;
Q_NEW_PC : out std_logic_vector(15 downto 0);
Q_OPC : out std_logic_vector(15 downto 0);
Q_PC : out std_logic_vector(15 downto 0);
Q_RD_IO : out std_logic;
Q_SKIP : out std_logic;
Q_WE_IO : out std_logic);
end data_path;
architecture Behavioral of data_path is
component alu
port ( I_ALU_OP : in std_logic_vector( 4 downto 0);
I_BIT : in std_logic_vector( 3 downto 0);
I_D : in std_logic_vector(15 downto 0);
I_D0 : in std_logic;
I_DIN : in std_logic_vector( 7 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector( 7 downto 0);
I_PC : in std_logic_vector(15 downto 0);
I_R : in std_logic_vector(15 downto 0);
I_R0 : in std_logic;
I_RSEL : in std_logic_vector( 1 downto 0);
Q_FLAGS : out std_logic_vector( 9 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal A_DOUT : std_logic_vector(15 downto 0);
signal A_FLAGS : std_logic_vector( 9 downto 0);
component register_file
port ( I_CLK : in std_logic;
I_AMOD : in std_logic_vector( 5 downto 0);
I_COND : in std_logic_vector( 3 downto 0);
I_DDDDD : in std_logic_vector( 4 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_FLAGS : in std_logic_vector( 7 downto 0);
I_IMM : in std_logic_vector(15 downto 0);
I_RRRR : in std_logic_vector( 4 downto 1);
I_WE_01 : in std_logic;
I_WE_D : in std_logic_vector( 1 downto 0);
I_WE_F : in std_logic;
I_WE_M : in std_logic;
I_WE_XYZS : in std_logic;
Q_ADR : out std_logic_vector(15 downto 0);
Q_CC : out std_logic;
Q_D : out std_logic_vector(15 downto 0);
Q_FLAGS : out std_logic_vector( 7 downto 0);
Q_R : out std_logic_vector(15 downto 0);
Q_S : out std_logic_vector( 7 downto 0);
Q_Z : out std_logic_vector(15 downto 0));
end component;
signal F_ADR : std_logic_vector(15 downto 0);
signal F_CC : std_logic;
signal F_D : std_logic_vector(15 downto 0);
signal F_FLAGS : std_logic_vector( 7 downto 0);
signal F_R : std_logic_vector(15 downto 0);
signal F_S : std_logic_vector( 7 downto 0);
signal F_Z : std_logic_vector(15 downto 0);
component data_mem
port ( I_CLK : in std_logic;
I_ADR : in std_logic_vector(10 downto 0);
I_DIN : in std_logic_vector(15 downto 0);
I_WE : in std_logic_vector( 1 downto 0);
Q_DOUT : out std_logic_vector(15 downto 0));
end component;
signal M_DOUT : std_logic_vector(15 downto 0);
signal L_DIN : std_logic_vector( 7 downto 0);
signal L_WE_SRAM : std_logic_vector( 1 downto 0);
signal L_FLAGS_98 : std_logic_vector( 9 downto 8);
begin
alui : alu
port map( I_ALU_OP => I_ALU_OP,
I_BIT => I_BIT,
I_D => F_D,
I_D0 => I_DDDDD(0),
I_DIN => L_DIN,
I_FLAGS => F_FLAGS,
I_IMM => I_IMM(7 downto 0),
I_PC => I_PC,
I_R => F_R,
I_R0 => I_RRRRR(0),
I_RSEL => I_RSEL,
Q_FLAGS => A_FLAGS,
Q_DOUT => A_DOUT);
regs : register_file
port map( I_CLK => I_CLK,
I_AMOD => I_AMOD,
I_COND(3) => I_OPC(10),
I_COND(2 downto 0)=> I_OPC(2 downto 0),
I_DDDDD => I_DDDDD,
I_DIN => A_DOUT,
I_FLAGS => A_FLAGS(7 downto 0),
I_IMM => I_IMM,
I_RRRR => I_RRRRR(4 downto 1),
I_WE_01 => I_WE_01,
I_WE_D => I_WE_D,
I_WE_F => I_WE_F,
I_WE_M => I_WE_M(0),
I_WE_XYZS => I_WE_XYZS,
Q_ADR => F_ADR,
Q_CC => F_CC,
Q_D => F_D,
Q_FLAGS => F_FLAGS,
Q_R => F_R,
Q_S => F_S, -- Q_Rxx(F_ADR)
Q_Z => F_Z);
sram : data_mem
port map( I_CLK => I_CLK,
I_ADR => F_ADR(10 downto 0),
I_DIN => A_DOUT,
I_WE => L_WE_SRAM,
Q_DOUT => M_DOUT);
-- remember A_FLAGS(9 downto 8) (within the current instruction).
--
flg98: process(I_CLK)
begin
if (rising_edge(I_CLK)) then
L_FLAGS_98 <= A_FLAGS(9 downto 8);
end if;
end process;
-- whether PC shall be loaded with NEW_PC or not.
-- I.e. if a branch shall be taken or not.
--
process(I_PC_OP, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_LOAD_PC <= F_CC; -- maybe (PC on I_JADR)
when PC_LD_I => Q_LOAD_PC <= '1'; -- yes: new PC on I_JADR
when PC_LD_Z => Q_LOAD_PC <= '1'; -- yes: new PC in Z
when PC_LD_S => Q_LOAD_PC <= '1'; -- yes: new PC on stack
when others => Q_LOAD_PC <= '0'; -- no.
end case;
end process;
-- whether the next instruction shall be skipped or not.
--
process(I_PC_OP, L_FLAGS_98, F_CC)
begin
case I_PC_OP is
when PC_BCC => Q_SKIP <= F_CC; -- if cond met
when PC_LD_I => Q_SKIP <= '1'; -- yes
when PC_LD_Z => Q_SKIP <= '1'; -- yes
when PC_LD_S => Q_SKIP <= '1'; -- yes
when PC_SKIP_Z => Q_SKIP <= L_FLAGS_98(8); -- if Z set
when PC_SKIP_T => Q_SKIP <= L_FLAGS_98(9); -- if T set
when others => Q_SKIP <= '0'; -- no.
end case;
end process;
Q_ADR <= F_ADR;
Q_DOUT <= A_DOUT(7 downto 0);
Q_INT_ENA <= A_FLAGS(7);
Q_OPC <= I_OPC;
Q_PC <= I_PC;
Q_RD_IO <= '0' when (F_ADR < X"20")
else (I_RD_M and not I_PMS) when (F_ADR < X"5D")
else '0';
Q_WE_IO <= '0' when (F_ADR < X"20")
else I_WE_M(0) when (F_ADR < X"5D")
else '0';
L_WE_SRAM <= "00" when (F_ADR < X"0060") else I_WE_M;
L_DIN <= I_DIN when (I_PMS = '1')
else F_S when (F_ADR < X"0020")
else I_DIN when (F_ADR < X"005D")
else F_S when (F_ADR < X"0060")
else M_DOUT(7 downto 0);
-- compute potential new PC value from Z, (SP), or IMM.
--
Q_NEW_PC <= F_Z when I_PC_OP = PC_LD_Z -- IJMP, ICALL
else M_DOUT when I_PC_OP = PC_LD_S -- RET, RETI
else I_JADR; -- JMP adr
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:30:53 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_axi_bram_ctrl_0_bram_0/zynq_design_1_axi_bram_ctrl_0_bram_0_sim_netlist.vhdl
-- Design : zynq_design_1_axi_bram_ctrl_0_bram_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[1:0][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[3:2][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[5:4][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[23:22][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[25:24][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[27:26][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[29:28][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[31:30][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[7:6][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[9:8][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[11:10][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[13:12][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[15:14][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[17:16][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[19:18][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ : entity is "blk_mem_gen_prim_wrapper";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\ is
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 2 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute bmm_info_memory_device : string;
attribute bmm_info_memory_device of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "[21:20][0:16383]";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 0,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
READ_WIDTH_A => 2,
READ_WIDTH_B => 2,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 2,
WRITE_WIDTH_B => 2
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 1) => addra(13 downto 0),
ADDRARDADDR(0) => '1',
ADDRBWRADDR(15) => '1',
ADDRBWRADDR(14 downto 1) => addrb(13 downto 0),
ADDRBWRADDR(0) => '1',
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clkb,
DBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 2) => B"000000000000000000000000000000",
DIADI(1 downto 0) => dina(1 downto 0),
DIBDI(31 downto 2) => B"000000000000000000000000000000",
DIBDI(1 downto 0) => dinb(1 downto 0),
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOADO_UNCONNECTED\(31 downto 2),
DOADO(1 downto 0) => douta(1 downto 0),
DOBDO(31 downto 2) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOBDO_UNCONNECTED\(31 downto 2),
DOBDO(1 downto 0) => doutb(1 downto 0),
DOPADOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPADOP_UNCONNECTED\(3 downto 0),
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => ena,
ENBWREN => enb,
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '0',
REGCEB => '0',
RSTRAMARSTRAM => rsta,
RSTRAMB => rstb,
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.WITH_BMM_INFO.TRUE_DP.SIMPLE_PRIM36.TDP_SP36_NO_ECC_ATTR.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 4) => B"0000",
WEBWE(3) => web(0),
WEBWE(2) => web(0),
WEBWE(1) => web(0),
WEBWE(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width is
begin
\prim_noinit.ram\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ is
port (
douta : out STD_LOGIC_VECTOR ( 1 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 1 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 1 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 1 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ : entity is "blk_mem_gen_prim_width";
end \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\;
architecture STRUCTURE of \zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\ is
begin
\prim_noinit.ram\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_wrapper__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(1 downto 0),
dinb(1 downto 0) => dinb(1 downto 0),
douta(1 downto 0) => douta(1 downto 0),
doutb(1 downto 0) => doutb(1 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[10].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized9\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(21 downto 20),
dinb(1 downto 0) => dinb(21 downto 20),
douta(1 downto 0) => douta(21 downto 20),
doutb(1 downto 0) => doutb(21 downto 20),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[11].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized10\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(23 downto 22),
dinb(1 downto 0) => dinb(23 downto 22),
douta(1 downto 0) => douta(23 downto 22),
doutb(1 downto 0) => doutb(23 downto 22),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[12].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized11\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(25 downto 24),
dinb(1 downto 0) => dinb(25 downto 24),
douta(1 downto 0) => douta(25 downto 24),
doutb(1 downto 0) => doutb(25 downto 24),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[13].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized12\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(27 downto 26),
dinb(1 downto 0) => dinb(27 downto 26),
douta(1 downto 0) => douta(27 downto 26),
doutb(1 downto 0) => doutb(27 downto 26),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[14].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized13\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(29 downto 28),
dinb(1 downto 0) => dinb(29 downto 28),
douta(1 downto 0) => douta(29 downto 28),
doutb(1 downto 0) => doutb(29 downto 28),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[15].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized14\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(31 downto 30),
dinb(1 downto 0) => dinb(31 downto 30),
douta(1 downto 0) => douta(31 downto 30),
doutb(1 downto 0) => doutb(31 downto 30),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(3),
web(0) => web(3)
);
\ramloop[1].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized0\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(3 downto 2),
dinb(1 downto 0) => dinb(3 downto 2),
douta(1 downto 0) => douta(3 downto 2),
doutb(1 downto 0) => doutb(3 downto 2),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[2].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized1\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(5 downto 4),
dinb(1 downto 0) => dinb(5 downto 4),
douta(1 downto 0) => douta(5 downto 4),
doutb(1 downto 0) => doutb(5 downto 4),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[3].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized2\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(7 downto 6),
dinb(1 downto 0) => dinb(7 downto 6),
douta(1 downto 0) => douta(7 downto 6),
doutb(1 downto 0) => doutb(7 downto 6),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(0),
web(0) => web(0)
);
\ramloop[4].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized3\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(9 downto 8),
dinb(1 downto 0) => dinb(9 downto 8),
douta(1 downto 0) => douta(9 downto 8),
doutb(1 downto 0) => doutb(9 downto 8),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[5].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized4\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(11 downto 10),
dinb(1 downto 0) => dinb(11 downto 10),
douta(1 downto 0) => douta(11 downto 10),
doutb(1 downto 0) => doutb(11 downto 10),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[6].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized5\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(13 downto 12),
dinb(1 downto 0) => dinb(13 downto 12),
douta(1 downto 0) => douta(13 downto 12),
doutb(1 downto 0) => doutb(13 downto 12),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[7].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized6\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(15 downto 14),
dinb(1 downto 0) => dinb(15 downto 14),
douta(1 downto 0) => douta(15 downto 14),
doutb(1 downto 0) => doutb(15 downto 14),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(1),
web(0) => web(1)
);
\ramloop[8].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized7\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(17 downto 16),
dinb(1 downto 0) => dinb(17 downto 16),
douta(1 downto 0) => douta(17 downto 16),
doutb(1 downto 0) => doutb(17 downto 16),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
\ramloop[9].ram.r\: entity work.\zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_prim_width__parameterized8\
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(1 downto 0) => dina(19 downto 18),
dinb(1 downto 0) => dinb(19 downto 18),
douta(1 downto 0) => douta(19 downto 18),
doutb(1 downto 0) => doutb(19 downto 18),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(0) => wea(2),
web(0) => web(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top : entity is "blk_mem_gen_top";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top is
begin
\valid.cstr\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_generic_cstr
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth is
port (
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
clka : in STD_LOGIC;
clkb : in STD_LOGIC;
ena : in STD_LOGIC;
enb : in STD_LOGIC;
rsta : in STD_LOGIC;
rstb : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 13 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 13 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth : entity is "blk_mem_gen_v8_3_6_synth";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth is
begin
\gnbram.gnative_mem_map_bmg.native_mem_map_blk_mem_gen\: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_top
port map (
addra(13 downto 0) => addra(13 downto 0),
addrb(13 downto 0) => addrb(13 downto 0),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "zynq";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "blk_mem_gen_v8_3_6";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 : entity is "yes";
end zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
rdaddrecc(31) <= \<const0>\;
rdaddrecc(30) <= \<const0>\;
rdaddrecc(29) <= \<const0>\;
rdaddrecc(28) <= \<const0>\;
rdaddrecc(27) <= \<const0>\;
rdaddrecc(26) <= \<const0>\;
rdaddrecc(25) <= \<const0>\;
rdaddrecc(24) <= \<const0>\;
rdaddrecc(23) <= \<const0>\;
rdaddrecc(22) <= \<const0>\;
rdaddrecc(21) <= \<const0>\;
rdaddrecc(20) <= \<const0>\;
rdaddrecc(19) <= \<const0>\;
rdaddrecc(18) <= \<const0>\;
rdaddrecc(17) <= \<const0>\;
rdaddrecc(16) <= \<const0>\;
rdaddrecc(15) <= \<const0>\;
rdaddrecc(14) <= \<const0>\;
rdaddrecc(13) <= \<const0>\;
rdaddrecc(12) <= \<const0>\;
rdaddrecc(11) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(31) <= \<const0>\;
s_axi_rdaddrecc(30) <= \<const0>\;
s_axi_rdaddrecc(29) <= \<const0>\;
s_axi_rdaddrecc(28) <= \<const0>\;
s_axi_rdaddrecc(27) <= \<const0>\;
s_axi_rdaddrecc(26) <= \<const0>\;
s_axi_rdaddrecc(25) <= \<const0>\;
s_axi_rdaddrecc(24) <= \<const0>\;
s_axi_rdaddrecc(23) <= \<const0>\;
s_axi_rdaddrecc(22) <= \<const0>\;
s_axi_rdaddrecc(21) <= \<const0>\;
s_axi_rdaddrecc(20) <= \<const0>\;
s_axi_rdaddrecc(19) <= \<const0>\;
s_axi_rdaddrecc(18) <= \<const0>\;
s_axi_rdaddrecc(17) <= \<const0>\;
s_axi_rdaddrecc(16) <= \<const0>\;
s_axi_rdaddrecc(15) <= \<const0>\;
s_axi_rdaddrecc(14) <= \<const0>\;
s_axi_rdaddrecc(13) <= \<const0>\;
s_axi_rdaddrecc(12) <= \<const0>\;
s_axi_rdaddrecc(11) <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6_synth
port map (
addra(13 downto 0) => addra(15 downto 2),
addrb(13 downto 0) => addrb(15 downto 2),
clka => clka,
clkb => clkb,
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
ena => ena,
enb => enb,
rsta => rsta,
rstb => rstb,
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity zynq_design_1_axi_bram_ctrl_0_bram_0 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 31 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 31 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is "zynq_design_1_axi_bram_ctrl_0_bram_0,blk_mem_gen_v8_3_6,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of zynq_design_1_axi_bram_ctrl_0_bram_0 : entity is "blk_mem_gen_v8_3_6,Vivado 2017.2";
end zynq_design_1_axi_bram_ctrl_0_bram_0;
architecture STRUCTURE of zynq_design_1_axi_bram_ctrl_0_bram_0 is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 32;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 32;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "16";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 1;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 20.388 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "zynq";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 1;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 1;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 1;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 1;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "NONE";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 0;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 2;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 16384;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 16384;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 32;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 32;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 1;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 16384;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 16384;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 32;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 32;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "zynq";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.zynq_design_1_axi_bram_ctrl_0_bram_0_blk_mem_gen_v8_3_6
port map (
addra(31 downto 0) => addra(31 downto 0),
addrb(31 downto 0) => addrb(31 downto 0),
clka => clka,
clkb => clkb,
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(31 downto 0) => dina(31 downto 0),
dinb(31 downto 0) => dinb(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
doutb(31 downto 0) => doutb(31 downto 0),
eccpipece => '0',
ena => ena,
enb => enb,
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(31 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(31 downto 0),
regcea => '0',
regceb => '0',
rsta => rsta,
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => rstb,
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(31 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(31 downto 0),
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => web(3 downto 0)
);
end STRUCTURE;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(5 downto 0);
b: in std_logic_vector(5 downto 0);
s: out std_logic_vector(5 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(5 downto 0);
signal b_reg : std_logic_vector(5 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(2 downto 0);
signal b0_cb : std_logic_vector(2 downto 0);
signal a1_cb : std_logic_vector(5 downto 3);
signal b1_cb : std_logic_vector(5 downto 3);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
-- wires for each full adder sum
signal fas : std_logic_vector(5 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal s0_ca_rego0 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(5 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(2 downto 0);
b0_cb <= b_reg(2 downto 0);
a1_cb <= a_reg(5 downto 3);
b1_cb <= b_reg(5 downto 3);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(2 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(5 downto 3),
facout => faccout1_co1);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(2 downto 0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(2 downto 0) <= s0_ca_rego0(0);
s_tmp(5 downto 3) <= fas(5 downto 3);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_U : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(5 downto 0);
b: in std_logic_vector(5 downto 0);
s: out std_logic_vector(5 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(5 downto 0);
signal b_reg : std_logic_vector(5 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(2 downto 0);
signal b0_cb : std_logic_vector(2 downto 0);
signal a1_cb : std_logic_vector(5 downto 3);
signal b1_cb : std_logic_vector(5 downto 3);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
-- wires for each full adder sum
signal fas : std_logic_vector(5 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal s0_ca_rego0 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(5 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(2 downto 0);
b0_cb <= b_reg(2 downto 0);
a1_cb <= a_reg(5 downto 3);
b1_cb <= b_reg(5 downto 3);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(2 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(5 downto 3),
facout => faccout1_co1);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(2 downto 0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(2 downto 0) <= s0_ca_rego0(0);
s_tmp(5 downto 3) <= fas(5 downto 3);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_U : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk: in std_logic;
reset: in std_logic;
ce: in std_logic;
a: in std_logic_vector(5 downto 0);
b: in std_logic_vector(5 downto 0);
s: out std_logic_vector(5 downto 0));
end entity;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
port (
faa : IN STD_LOGIC_VECTOR (3-1 downto 0);
fab : IN STD_LOGIC_VECTOR (3-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (3-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end component;
-- ---- register and wire type variables list here ----
-- wire for the primary inputs
signal a_reg : std_logic_vector(5 downto 0);
signal b_reg : std_logic_vector(5 downto 0);
-- wires for each small adder
signal a0_cb : std_logic_vector(2 downto 0);
signal b0_cb : std_logic_vector(2 downto 0);
signal a1_cb : std_logic_vector(5 downto 3);
signal b1_cb : std_logic_vector(5 downto 3);
-- registers for input register array
type ramtypei0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal a1_cb_regi1 : ramtypei0;
signal b1_cb_regi1 : ramtypei0;
-- wires for each full adder sum
signal fas : std_logic_vector(5 downto 0);
-- wires and register for carry out bit
signal faccout_ini : std_logic_vector (0 downto 0);
signal faccout0_co0 : std_logic_vector (0 downto 0);
signal faccout1_co1 : std_logic_vector (0 downto 0);
signal faccout0_co0_reg : std_logic_vector (0 downto 0);
-- registers for output register array
type ramtypeo0 is array (0 downto 0) of std_logic_vector(2 downto 0);
signal s0_ca_rego0 : ramtypeo0;
-- wire for the temporary output
signal s_tmp : std_logic_vector(5 downto 0);
-- ---- RTL code for assignment statements/always blocks/module instantiations here ----
begin
a_reg <= a;
b_reg <= b;
-- small adder input assigments
a0_cb <= a_reg(2 downto 0);
b0_cb <= b_reg(2 downto 0);
a1_cb <= a_reg(5 downto 3);
b1_cb <= b_reg(5 downto 3);
-- input register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
a1_cb_regi1 (0) <= a1_cb;
b1_cb_regi1 (0) <= b1_cb;
end if;
end if;
end process;
-- carry out bit processing
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
faccout0_co0_reg <= faccout0_co0;
end if;
end if;
end process;
-- small adder generation
u0 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder
port map
(faa => a0_cb,
fab => b0_cb,
facin => faccout_ini,
fas => fas(2 downto 0),
facout => faccout0_co0);
u1 : nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f
port map
(faa => a1_cb_regi1(0),
fab => b1_cb_regi1(0),
facin => faccout0_co0_reg,
fas => fas(5 downto 3),
facout => faccout1_co1);
faccout_ini <= "0";
-- output register array
process (clk)
begin
if (clk'event and clk='1') then
if (ce='1') then
s0_ca_rego0 (0) <= fas(2 downto 0);
end if;
end if;
end process;
-- get the s_tmp, assign it to the primary output
s_tmp(2 downto 0) <= s0_ca_rego0(0);
s_tmp(5 downto 3) <= fas(5 downto 3);
s <= s_tmp;
end architecture;
-- short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
-- the final stage short adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
generic(N : natural :=3);
port (
faa : IN STD_LOGIC_VECTOR (N-1 downto 0);
fab : IN STD_LOGIC_VECTOR (N-1 downto 0);
facin : IN STD_LOGIC_VECTOR (0 downto 0);
fas : OUT STD_LOGIC_VECTOR (N-1 downto 0);
facout : OUT STD_LOGIC_VECTOR (0 downto 0));
end;
architecture behav of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_fadder_f is
signal tmp : STD_LOGIC_VECTOR (N downto 0);
begin
tmp <= std_logic_vector(unsigned(std_logic_vector(unsigned(std_logic_vector(resize(unsigned(faa),N+1))) + unsigned(fab))) + unsigned(facin));
fas <= tmp(N-1 downto 0 );
facout <= tmp(N downto N);
end behav;
Library IEEE;
use IEEE.std_logic_1164.all;
entity nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of nfa_accept_samples_generic_hw_add_6ns_6ns_6_2 is
component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3 is
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
s : OUT STD_LOGIC_VECTOR);
end component;
begin
nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3_U : component nfa_accept_samples_generic_hw_add_6ns_6ns_6_2_AddSubnS_3
port map (
clk => clk,
reset => reset,
ce => ce,
a => din0,
b => din1,
s => dout);
end architecture;
|
-- $Id: ibdr_dl11.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: ibdr_dl11 - syn
-- Description: ibus dev(rem): DL11-A/B
--
-- Dependencies: ib_rlim_slv
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2017.2; ghdl 0.18-0.35
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2010-10-17 333 12.1 M53d xc3s1000-4 39 126 0 72 s 7.6
-- 2009-07-12 233 10.1.03 K39 xc3s1000-4 38 119 0 69 s 6.3
-- 2009-07-11 232 10.1.03 K39 xc3s1000-4 23 61 0 40 s 5.5
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-27 1140 1.3.3 drop rbuf.rrdy, set rbuf.[rx]size0 instead
-- 2019-04-24 1138 1.3.2 add rcsr.ir and xcsr.ir (intreq monitors)
-- 2019-04-14 1131 1.3.1 RLIM_CEV now slv8
-- 2019-04-07 1127 1.3 for dl11_buf compat: xbuf.val in bit 15 and 8;
-- use rbuf instead xbuf for rdry reporting; remove
-- maintenance mode; use ib_rlim_slv; drop CE_USEC
-- 2011-11-18 427 1.2.2 now numeric_std clean
-- 2010-10-23 335 1.2.1 rename RRI_LAM->RB_LAM;
-- 2010-10-17 333 1.2 use ibus V2 interface
-- 2010-06-11 303 1.1 use IB_MREQ.racc instead of RRI_REQ
-- 2009-07-12 233 1.0.5 add RESET, CE_USEC port; implement input rate limit
-- 2008-08-22 161 1.0.6 use iblib; add EI_ACK_* to proc_next sens. list
-- 2008-05-09 144 1.0.5 use intreq flop, use EI_ACK
-- 2008-03-22 128 1.0.4 rename xdone -> xval (no functional change)
-- 2008-01-27 115 1.0.3 BUGFIX: set ilam when rbuf read by cpu;
-- add xdone and rrdy bits to rri xbuf read
-- 2008-01-20 113 1.0.2 fix maint mode logic (proper double buffer now)
-- 2008-01-20 112 1.0.1 use BRESET
-- 2008-01-05 108 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibdr_dl11 is -- ibus dev(rem): DL11-A/B
generic (
IB_ADDR : slv16 := slv(to_unsigned(8#177560#,16)));
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
BRESET : in slbit; -- ibus reset
RLIM_CEV : in slv8; -- clock enable vector
RB_LAM : out slbit; -- remote attention
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type; -- ibus response
EI_REQ_RX : out slbit; -- interrupt request, receiver
EI_REQ_TX : out slbit; -- interrupt request, transmitter
EI_ACK_RX : in slbit; -- interrupt acknowledge, receiver
EI_ACK_TX : in slbit -- interrupt acknowledge, transmitter
);
end ibdr_dl11;
architecture syn of ibdr_dl11 is
constant ibaddr_rcsr : slv2 := "00"; -- rcsr address offset
constant ibaddr_rbuf : slv2 := "01"; -- rbuf address offset
constant ibaddr_xcsr : slv2 := "10"; -- xcsr address offset
constant ibaddr_xbuf : slv2 := "11"; -- xbuf address offset
subtype rcsr_ibf_rrlim is integer range 14 downto 12;
constant rcsr_ibf_rdone : integer := 7;
constant rcsr_ibf_rie : integer := 6;
constant rcsr_ibf_rir : integer := 5;
constant rbuf_ibf_rsize0: integer := 8;
constant rbuf_ibf_xsize0: integer := 0;
subtype rbuf_ibf_data is integer range 7 downto 0;
constant xcsr_ibf_xrdy : integer := 7;
constant xcsr_ibf_xie : integer := 6;
constant xcsr_ibf_xir : integer := 5;
constant xbuf_ibf_xval : integer := 15;
constant xbuf_ibf_xval8 : integer := 8;
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
rrlim : slv3; -- rcsr: receiver rate limit
rdone : slbit; -- rcsr: receiver done
rie : slbit; -- rcsr: receiver interrupt enable
rbuf : slv8; -- rbuf:
rval : slbit; -- rx rbuf valid
rintreq : slbit; -- rx interrupt request
xrdy : slbit; -- xcsr: transmitter ready
xie : slbit; -- xcsr: transmitter interrupt enable
xbuf : slv8; -- xbuf:
xintreq : slbit; -- tx interrupt request
end record regs_type;
constant regs_init : regs_type := (
'0', -- ibsel
(others=>'0'), -- rrlim
'0','0', -- rdone, rie
(others=>'0'), -- rbuf
'0','0', -- rval,rintreq
'1', -- xrdy !! is set !!
'0', -- xie
(others=>'0'), -- xbuf
'0' -- xintreq
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal RRLIM_START : slbit := '0';
signal RRLIM_BUSY : slbit := '0';
begin
RRLIM : ib_rlim_slv
port map (
CLK => CLK,
RESET => RESET,
RLIM_CEV => RLIM_CEV,
SEL => R_REGS.rrlim,
START => RRLIM_START,
STOP => BRESET,
DONE => open,
BUSY => RRLIM_BUSY
);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if BRESET = '1' then
R_REGS <= regs_init;
if RESET = '0' then -- if RESET=0 we do just an ibus reset
R_REGS.rrlim <= N_REGS.rrlim; -- keep RLIM flag
end if;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, EI_ACK_RX, EI_ACK_TX, RRLIM_BUSY)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable ibrd : slbit := '0';
variable ibw0 : slbit := '0';
variable ibw1 : slbit := '0';
variable ilam : slbit := '0';
variable irrlimsta : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
ibrd := IB_MREQ.re;
ibw0 := IB_MREQ.we and IB_MREQ.be0;
ibw1 := IB_MREQ.we and IB_MREQ.be1;
ilam := '0';
irrlimsta := '0';
-- ibus address decoder
n.ibsel := '0';
if IB_MREQ.aval='1' and
IB_MREQ.addr(12 downto 3)=IB_ADDR(12 downto 3) then
n.ibsel := '1';
end if;
-- ibus transactions
if r.ibsel = '1' then
case IB_MREQ.addr(2 downto 1) is
when ibaddr_rcsr => -- RCSR -- receive control status ----
idout(rcsr_ibf_rdone) := r.rdone;
idout(rcsr_ibf_rie) := r.rie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then -- rcsr write
n.rie := IB_MREQ.din(rcsr_ibf_rie);
if IB_MREQ.din(rcsr_ibf_rie) = '1' then
if r.rdone='1' and r.rie='0' then -- ie set while done=1
n.rintreq := '1'; -- request interrupt
end if;
else
n.rintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(rcsr_ibf_rrlim) := r.rrlim;
idout(rcsr_ibf_rir) := r.rintreq;
if ibw1 = '1' then
n.rrlim := IB_MREQ.din(rcsr_ibf_rrlim);
end if;
end if;
when ibaddr_rbuf => -- RBUF -- receive data buffer -------
if IB_MREQ.racc = '0' then -- cpu ---------------------
idout(rbuf_ibf_data) := r.rbuf;
if ibrd = '1' then -- rbuf read
n.rintreq := '0'; -- cancel interrupt
end if;
if ibrd='1' and r.rdone='1' then
n.rval := '0'; -- clear rbuf valid
irrlimsta := '1'; -- start rx timer
ilam := '1'; -- request rb attention
end if;
else -- rri ---------------------
idout(rbuf_ibf_rsize0) := r.rval; -- rbuf occupied when rval=1
idout(rbuf_ibf_xsize0) := not r.xrdy; -- xbuf empty when xrdy=1
if ibw0 = '1' then
n.rbuf := IB_MREQ.din(rbuf_ibf_data);
n.rval := '1'; -- set rbuf valid
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---
idout(xcsr_ibf_xrdy) := r.xrdy;
idout(xcsr_ibf_xie) := r.xie;
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xie := IB_MREQ.din(xcsr_ibf_xie);
if IB_MREQ.din(xcsr_ibf_xie) = '1' then
if r.xrdy='1' and r.xie='0' then -- ie set while ready=1
n.xintreq := '1'; -- request interrupt
end if;
else
n.xintreq := '0';
end if;
end if;
else -- rri ---------------------
idout(xcsr_ibf_xir) := r.xintreq;
end if;
when ibaddr_xbuf => -- XBUF -- transmit data buffer ------
if IB_MREQ.racc = '0' then -- cpu ---------------------
if ibw0 = '1' then
n.xbuf := IB_MREQ.din(n.xbuf'range);
n.xrdy := '0';
n.xintreq := '0';
ilam := '1';
end if;
else -- rri ---------------------
idout(r.xbuf'range) := r.xbuf;
idout(xbuf_ibf_xval) := not r.xrdy;
idout(xbuf_ibf_xval8) := not r.xrdy;
if ibrd = '1' then
n.xrdy := '1';
if r.xie = '1' then
n.xintreq := '1';
end if;
end if;
end if;
when others => null;
end case;
end if;
-- other state changes
if EI_ACK_RX = '1' then
n.rintreq := '0';
end if;
if EI_ACK_TX = '1' then
n.xintreq := '0';
end if;
if (RRLIM_BUSY or (not r.rval)) = '1' then -- busy or no data
n.rdone := '0'; -- clear done
n.rintreq := '0'; -- clear pending interrupts
else -- not busy and data valid
n.rdone := '1'; -- set done
if r.rdone='0' and r.rie='1' then -- done going 0->1 and ie=1
n.rintreq := '1'; -- request rx interrupt
end if;
end if;
N_REGS <= n;
RRLIM_START <= irrlimsta;
IB_SRES.dout <= idout;
IB_SRES.ack <= r.ibsel and ibreq;
IB_SRES.busy <= '0';
RB_LAM <= ilam;
EI_REQ_RX <= r.rintreq;
EI_REQ_TX <= r.xintreq;
end process proc_next;
end syn;
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll8.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll8 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll8;
ARCHITECTURE SYN OF pll8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
locked <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "5000",
clk2_divide_by => 4,
clk2_duty_cycle => 50,
clk2_multiply_by => 75,
clk2_phase_shift => "0",
clk3_divide_by => 4,
clk3_duty_cycle => 50,
clk3_multiply_by => 75,
clk3_phase_shift => "3333",
compensate_clock => "CLK0",
inclk0_input_frequency => 125000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll8",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "304.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll8.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "3333"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- megafunction wizard: %ALTPLL%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altpll
-- ============================================================
-- File Name: pll8.vhd
-- Megafunction Name(s):
-- altpll
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY pll8 IS
PORT
(
inclk0 : IN STD_LOGIC := '0';
c0 : OUT STD_LOGIC ;
c1 : OUT STD_LOGIC ;
c2 : OUT STD_LOGIC ;
c3 : OUT STD_LOGIC ;
locked : OUT STD_LOGIC
);
END pll8;
ARCHITECTURE SYN OF pll8 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
SIGNAL sub_wire1 : STD_LOGIC ;
SIGNAL sub_wire2 : STD_LOGIC ;
SIGNAL sub_wire3 : STD_LOGIC ;
SIGNAL sub_wire4 : STD_LOGIC ;
SIGNAL sub_wire5 : STD_LOGIC ;
SIGNAL sub_wire6 : STD_LOGIC ;
SIGNAL sub_wire7 : STD_LOGIC_VECTOR (1 DOWNTO 0);
SIGNAL sub_wire8_bv : BIT_VECTOR (0 DOWNTO 0);
SIGNAL sub_wire8 : STD_LOGIC_VECTOR (0 DOWNTO 0);
COMPONENT altpll
GENERIC (
bandwidth_type : STRING;
clk0_divide_by : NATURAL;
clk0_duty_cycle : NATURAL;
clk0_multiply_by : NATURAL;
clk0_phase_shift : STRING;
clk1_divide_by : NATURAL;
clk1_duty_cycle : NATURAL;
clk1_multiply_by : NATURAL;
clk1_phase_shift : STRING;
clk2_divide_by : NATURAL;
clk2_duty_cycle : NATURAL;
clk2_multiply_by : NATURAL;
clk2_phase_shift : STRING;
clk3_divide_by : NATURAL;
clk3_duty_cycle : NATURAL;
clk3_multiply_by : NATURAL;
clk3_phase_shift : STRING;
compensate_clock : STRING;
inclk0_input_frequency : NATURAL;
intended_device_family : STRING;
lpm_hint : STRING;
lpm_type : STRING;
operation_mode : STRING;
pll_type : STRING;
port_activeclock : STRING;
port_areset : STRING;
port_clkbad0 : STRING;
port_clkbad1 : STRING;
port_clkloss : STRING;
port_clkswitch : STRING;
port_configupdate : STRING;
port_fbin : STRING;
port_inclk0 : STRING;
port_inclk1 : STRING;
port_locked : STRING;
port_pfdena : STRING;
port_phasecounterselect : STRING;
port_phasedone : STRING;
port_phasestep : STRING;
port_phaseupdown : STRING;
port_pllena : STRING;
port_scanaclr : STRING;
port_scanclk : STRING;
port_scanclkena : STRING;
port_scandata : STRING;
port_scandataout : STRING;
port_scandone : STRING;
port_scanread : STRING;
port_scanwrite : STRING;
port_clk0 : STRING;
port_clk1 : STRING;
port_clk2 : STRING;
port_clk3 : STRING;
port_clk4 : STRING;
port_clk5 : STRING;
port_clkena0 : STRING;
port_clkena1 : STRING;
port_clkena2 : STRING;
port_clkena3 : STRING;
port_clkena4 : STRING;
port_clkena5 : STRING;
port_extclk0 : STRING;
port_extclk1 : STRING;
port_extclk2 : STRING;
port_extclk3 : STRING;
self_reset_on_loss_lock : STRING;
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
locked : OUT STD_LOGIC ;
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire8_bv(0 DOWNTO 0) <= "0";
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
locked <= sub_wire5;
sub_wire6 <= inclk0;
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
altpll_component : altpll
GENERIC MAP (
bandwidth_type => "AUTO",
clk0_divide_by => 2,
clk0_duty_cycle => 50,
clk0_multiply_by => 25,
clk0_phase_shift => "0",
clk1_divide_by => 2,
clk1_duty_cycle => 50,
clk1_multiply_by => 25,
clk1_phase_shift => "5000",
clk2_divide_by => 4,
clk2_duty_cycle => 50,
clk2_multiply_by => 75,
clk2_phase_shift => "0",
clk3_divide_by => 4,
clk3_duty_cycle => 50,
clk3_multiply_by => 75,
clk3_phase_shift => "3333",
compensate_clock => "CLK0",
inclk0_input_frequency => 125000,
intended_device_family => "Cyclone III",
lpm_hint => "CBX_MODULE_PREFIX=pll8",
lpm_type => "altpll",
operation_mode => "NORMAL",
pll_type => "AUTO",
port_activeclock => "PORT_UNUSED",
port_areset => "PORT_UNUSED",
port_clkbad0 => "PORT_UNUSED",
port_clkbad1 => "PORT_UNUSED",
port_clkloss => "PORT_UNUSED",
port_clkswitch => "PORT_UNUSED",
port_configupdate => "PORT_UNUSED",
port_fbin => "PORT_UNUSED",
port_inclk0 => "PORT_USED",
port_inclk1 => "PORT_UNUSED",
port_locked => "PORT_USED",
port_pfdena => "PORT_UNUSED",
port_phasecounterselect => "PORT_UNUSED",
port_phasedone => "PORT_UNUSED",
port_phasestep => "PORT_UNUSED",
port_phaseupdown => "PORT_UNUSED",
port_pllena => "PORT_UNUSED",
port_scanaclr => "PORT_UNUSED",
port_scanclk => "PORT_UNUSED",
port_scanclkena => "PORT_UNUSED",
port_scandata => "PORT_UNUSED",
port_scandataout => "PORT_UNUSED",
port_scandone => "PORT_UNUSED",
port_scanread => "PORT_UNUSED",
port_scanwrite => "PORT_UNUSED",
port_clk0 => "PORT_USED",
port_clk1 => "PORT_USED",
port_clk2 => "PORT_USED",
port_clk3 => "PORT_USED",
port_clk4 => "PORT_UNUSED",
port_clk5 => "PORT_UNUSED",
port_clkena0 => "PORT_UNUSED",
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED",
port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED",
port_clkena5 => "PORT_UNUSED",
port_extclk0 => "PORT_UNUSED",
port_extclk1 => "PORT_UNUSED",
port_extclk2 => "PORT_UNUSED",
port_extclk3 => "PORT_UNUSED",
self_reset_on_loss_lock => "ON",
width_clock => 5
)
PORT MAP (
inclk => sub_wire7,
clk => sub_wire0,
locked => sub_wire5
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "2"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "100.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "150.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "150.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "8.000"
-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "304.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps"
-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "100.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "150.00000000"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "180.00000000"
-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "deg"
-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll8.mif"
-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "1"
-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
-- Retrieval info: PRIVATE: USE_CLK3 STRING "1"
-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
-- Retrieval info: PRIVATE: USE_CLKENA3 STRING "0"
-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "5000"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "4"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "75"
-- Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "3333"
-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "125000"
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED"
-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL pll8_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
-- Retrieval info: CBX_MODULE_PREFIX: ON
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc538.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00538ent IS
END c03s03b00x00p05n02i00538ent;
ARCHITECTURE c03s03b00x00p05n02i00538arch OF c03s03b00x00p05n02i00538ent IS
BEGIN
TESTING: PROCESS
subtype byte is bit_vector (7 downto 0);
type byte_mem is array (0 to 15) of byte;
type ar_bv_ptr is access byte_mem;
variable v_ar_bv_ptr1: ar_bv_ptr := new byte_mem'(0 => "10000000",
1 => "00000001",
others => "00000000");
variable v_ar_bv_ptr2: ar_bv_ptr;
variable v_ar_bv_ptr3: ar_bv_ptr := v_ar_bv_ptr1;
variable OKtest : integer := 0;
BEGIN
assert v_ar_bv_ptr1(1) = "00000001";
if (v_ar_bv_ptr1(1) = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr2 = null;
if (v_ar_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(0) = "10000000";
if (v_ar_bv_ptr3(0) = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(15) = "00000000";
if (v_ar_bv_ptr3(15) = "00000000") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(1)(0) = '1'; -- (7 downto 0)
if (v_ar_bv_ptr3(1)(0) = '1') then
OKtest := Oktest + 1;
end if;
v_ar_bv_ptr2 := new byte_mem'(0 => "10000000",
1 => "00000001",
others => "00000000");
assert v_ar_bv_ptr2(0)(7) = '1'; -- (7 downto 0)
if (v_ar_bv_ptr2(0)(7) = '1') then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000";
if ((v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000") then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000";
if ((v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000") then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true;
if ((v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true) then
OKtest := Oktest + 1;
end if;
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p05n02i00538"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p05n02i00538 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00538arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc538.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00538ent IS
END c03s03b00x00p05n02i00538ent;
ARCHITECTURE c03s03b00x00p05n02i00538arch OF c03s03b00x00p05n02i00538ent IS
BEGIN
TESTING: PROCESS
subtype byte is bit_vector (7 downto 0);
type byte_mem is array (0 to 15) of byte;
type ar_bv_ptr is access byte_mem;
variable v_ar_bv_ptr1: ar_bv_ptr := new byte_mem'(0 => "10000000",
1 => "00000001",
others => "00000000");
variable v_ar_bv_ptr2: ar_bv_ptr;
variable v_ar_bv_ptr3: ar_bv_ptr := v_ar_bv_ptr1;
variable OKtest : integer := 0;
BEGIN
assert v_ar_bv_ptr1(1) = "00000001";
if (v_ar_bv_ptr1(1) = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr2 = null;
if (v_ar_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(0) = "10000000";
if (v_ar_bv_ptr3(0) = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(15) = "00000000";
if (v_ar_bv_ptr3(15) = "00000000") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(1)(0) = '1'; -- (7 downto 0)
if (v_ar_bv_ptr3(1)(0) = '1') then
OKtest := Oktest + 1;
end if;
v_ar_bv_ptr2 := new byte_mem'(0 => "10000000",
1 => "00000001",
others => "00000000");
assert v_ar_bv_ptr2(0)(7) = '1'; -- (7 downto 0)
if (v_ar_bv_ptr2(0)(7) = '1') then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000";
if ((v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000") then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000";
if ((v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000") then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true;
if ((v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true) then
OKtest := Oktest + 1;
end if;
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p05n02i00538"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p05n02i00538 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00538arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc538.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s03b00x00p05n02i00538ent IS
END c03s03b00x00p05n02i00538ent;
ARCHITECTURE c03s03b00x00p05n02i00538arch OF c03s03b00x00p05n02i00538ent IS
BEGIN
TESTING: PROCESS
subtype byte is bit_vector (7 downto 0);
type byte_mem is array (0 to 15) of byte;
type ar_bv_ptr is access byte_mem;
variable v_ar_bv_ptr1: ar_bv_ptr := new byte_mem'(0 => "10000000",
1 => "00000001",
others => "00000000");
variable v_ar_bv_ptr2: ar_bv_ptr;
variable v_ar_bv_ptr3: ar_bv_ptr := v_ar_bv_ptr1;
variable OKtest : integer := 0;
BEGIN
assert v_ar_bv_ptr1(1) = "00000001";
if (v_ar_bv_ptr1(1) = "00000001") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr2 = null;
if (v_ar_bv_ptr2 = null) then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(0) = "10000000";
if (v_ar_bv_ptr3(0) = "10000000") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(15) = "00000000";
if (v_ar_bv_ptr3(15) = "00000000") then
OKtest := Oktest + 1;
end if;
assert v_ar_bv_ptr3(1)(0) = '1'; -- (7 downto 0)
if (v_ar_bv_ptr3(1)(0) = '1') then
OKtest := Oktest + 1;
end if;
v_ar_bv_ptr2 := new byte_mem'(0 => "10000000",
1 => "00000001",
others => "00000000");
assert v_ar_bv_ptr2(0)(7) = '1'; -- (7 downto 0)
if (v_ar_bv_ptr2(0)(7) = '1') then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000";
if ((v_ar_bv_ptr1(1) & v_ar_bv_ptr3(7)) = "0000000100000000") then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000";
if ((v_ar_bv_ptr3(1) & v_ar_bv_ptr2(0)) = "0000000110000000") then
OKtest := Oktest + 1;
end if;
assert (v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true;
if ((v_ar_bv_ptr1(1) /= v_ar_bv_ptr3(0)) = true) then
OKtest := Oktest + 1;
end if;
assert NOT(OKtest = 9)
report "***PASSED TEST: c03s03b00x00p05n02i00538"
severity NOTE;
assert (OKtest = 9)
report "***FAILED TEST: c03s03b00x00p05n02i00538 - An access value belongs to a corresponding subtype of an access type if the value of the designated object satisfies the constraint."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s03b00x00p05n02i00538arch;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- XUPV5
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505";
constant MY_DEVICE : string := "XC5VLX110T";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Package: Project specific configuration.
--
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------
-- This file was created from the template file:
--
-- <PoCRoot>/src/common/my_config.template.vhdl
--
-- and customized for:
--
-- XUPV5
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2014 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "ML505";
constant MY_DEVICE : string := "XC5VLX110T";
constant MY_VERBOSE : boolean := true;
end my_config;
package body my_config is
end my_config;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_nor_gate IS END tb_nor_gate;
ARCHITECTURE test OF tb_nor_gate IS
COMPONENT nor_gate IS
PORT (a:IN STD_LOGIC;
b:IN STD_LOGIC;
q:OUT STD_LOGIC);
END COMPONENT;
SIGNAL test_vector: STD_LOGIC_VECTOR(1 downto 0);
SIGNAL result: STD_LOGIC;
BEGIN
T1: nor_gate PORT MAP(a=>test_vector(1), b=>test_vector(0), q=>result);
test_vector<="00",
"01" AFTER 10 ns,
"10" AFTER 20 ns,
"11" AFTER 30 ns;
END test; |
--------------------------------------------------------------------------------
-- FILE: Extender
-- DESC: Extend a short size number to specific size.
--
-- Author:
-- Create: 2015-05-28
-- Update: 2015-06-10
-- Status: TESTED
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.Consts.all;
--------------------------------------------------------------------------------
-- ENTITY
--------------------------------------------------------------------------------
entity Extender is
generic(
SRC_SIZE : integer := 1;
DEST_SIZE: integer := C_SYS_DATA_SIZE
);
port(
s : in std_logic := '0'; -- signed extend?
i : in std_logic_vector(SRC_SIZE-1 downto 0);
o : out std_logic_vector(DEST_SIZE-1 downto 0)
);
end Extender;
--------------------------------------------------------------------------------
-- ARCHITECTURE
--------------------------------------------------------------------------------
architecture extender_arch of Extender is
signal ext_bit : std_logic := '0';
begin
GE0: if DEST_SIZE <= SRC_SIZE generate
o <= i(DEST_SIZE-1 downto 0);
end generate;
GE1: if DEST_SIZE > SRC_SIZE generate
ext_bit <= s and i(SRC_SIZE-1);
o(SRC_SIZE-1 downto 0) <= i;
o(DEST_SIZE-1 downto SRC_SIZE) <= (others => ext_bit);
end generate;
end extender_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2014.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02014ent IS
END c07s02b02x00p11n02i02014ent;
ARCHITECTURE c07s02b02x00p11n02i02014arch OF c07s02b02x00p11n02i02014ent IS
signal S1 : BIT_VECTOR(0 downto 7);
signal S2 : BIT_VECTOR(0 to 7) := "10101010";
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if (S1 < S2) then
k := 5;
end if;
wait for 1 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02014"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02014 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02014arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2014.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02014ent IS
END c07s02b02x00p11n02i02014ent;
ARCHITECTURE c07s02b02x00p11n02i02014arch OF c07s02b02x00p11n02i02014ent IS
signal S1 : BIT_VECTOR(0 downto 7);
signal S2 : BIT_VECTOR(0 to 7) := "10101010";
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if (S1 < S2) then
k := 5;
end if;
wait for 1 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02014"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02014 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02014arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2014.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p11n02i02014ent IS
END c07s02b02x00p11n02i02014ent;
ARCHITECTURE c07s02b02x00p11n02i02014arch OF c07s02b02x00p11n02i02014ent IS
signal S1 : BIT_VECTOR(0 downto 7);
signal S2 : BIT_VECTOR(0 to 7) := "10101010";
BEGIN
TESTING: PROCESS
variable k : integer := 0;
BEGIN
if (S1 < S2) then
k := 5;
end if;
wait for 1 ns;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p11n02i02014"
severity NOTE;
assert ( k=5 )
report "***FAILED TEST: c07s02b02x00p11n02i02014 - The relation < returns TRUE if the left operand is a null array and the right operand is a non-null array."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p11n02i02014arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rotary_encoder_avalon_tb is
end entity rotary_encoder_avalon_tb;
architecture RTL of rotary_encoder_avalon_tb is
constant datawidth : natural := 32;
constant period : time := 10 ns; -- 100 Mhz
signal clk : std_logic;
signal rst : std_logic;
signal address : std_logic_vector(0 downto 0) := (others => '0');
signal read : std_logic := '0';
signal write : std_logic := '0';
signal chipselect : std_logic := '0';
signal writedata : std_logic_vector(datawidth - 1 downto 0) := (others => '0');
signal readdata : std_logic_vector(datawidth - 1 downto 0);
signal waitrequest : std_logic;
signal rotary_signal : std_logic := '0';
begin
clock_driver : process
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
rotary_signal_proc : process
begin
rotary_signal <= '0';
wait for 1 ms;
rotary_signal <= '1';
wait for 1 ms;
end process rotary_signal_proc;
av_rot_inst : entity work.rotary_encoder_avalon
generic map(
datawidth => datawidth
)
port map(
clk => clk,
rst => rst,
address => address,
read => read,
write => write,
chipselect => chipselect,
writedata => writedata,
readdata => readdata,
waitrequest => waitrequest,
rotary_signal => rotary_signal
);
stim_proc : process is
begin
rst <= '1';
wait until rising_edge(clk);
rst <= '0';
address <= (others => '0');
write <= '1';
chipselect <= '1';
writedata <= x"00000001";
wait until falling_edge(waitrequest);
chipselect <= '0';
write <= '0';
wait for 30 ms;
wait until rising_edge(clk);
chipselect <= '1';
read <= '1';
address <= "1";
wait until rising_edge(clk);
chipselect <= '0';
read <= '0';
wait until rising_edge(clk);
address <= "0";
chipselect <= '1';
write <= '1';
writedata <= x"00000003";
wait until falling_edge(waitrequest);
chipselect <= '0';
wait;
end process stim_proc;
end architecture RTL;
|
-------------------------------------------------------------------------------
--
-- RapidIO IP Library Core
--
-- This file is part of the RapidIO IP library project
-- http://www.opencores.org/cores/rio/
--
-- Description
-- Contains automatic simulation test code to verify a RioSerial implementation.
--
-- To Do:
-- -
--
-- Author(s):
-- - Magnus Rosenius, magro732@opencores.org
--
-------------------------------------------------------------------------------
--
-- Copyright (C) 2013 Authors and OPENCORES.ORG
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- TestRioSerial.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
-- Entity for TestRioSerial.
-------------------------------------------------------------------------------
entity TestRioSerial is
end entity;
-------------------------------------------------------------------------------
-- Architecture for TestUart.
-------------------------------------------------------------------------------
architecture TestRioSerialImpl of TestRioSerial is
component TestSwitchPort is
port(
clk : in std_logic;
areset_n : in std_logic;
frameValid_i : in std_logic_vector(0 to 63);
frameWrite_i : in RioFrameArray(0 to 63);
frameComplete_o : out std_logic;
frameExpected_i : in std_logic;
frameRead_i : in RioFrame;
frameReceived_o : out std_logic;
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(31 downto 0);
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(31 downto 0));
end component;
component RioSerial is
generic(
TIMEOUT_WIDTH : natural);
port(
clk : in std_logic;
areset_n : in std_logic;
portLinkTimeout_i : in std_logic_vector(TIMEOUT_WIDTH-1 downto 0);
linkInitialized_o : out std_logic;
inputPortEnable_i : in std_logic;
outputPortEnable_i : in std_logic;
linkUninitPacketDiscardActive_i : in std_logic;
localAckIdWrite_i : in std_logic;
clrOutstandingAckId_i : in std_logic;
inboundAckId_i : in std_logic_vector(4 downto 0);
outstandingAckId_i : in std_logic_vector(4 downto 0);
outboundAckId_i : in std_logic_vector(4 downto 0);
inboundAckId_o : out std_logic_vector(4 downto 0);
outstandingAckId_o : out std_logic_vector(4 downto 0);
outboundAckId_o : out std_logic_vector(4 downto 0);
readFrameEmpty_i : in std_logic;
readFrame_o : out std_logic;
readFrameRestart_o : out std_logic;
readFrameAborted_i : in std_logic;
readWindowEmpty_i : in std_logic;
readWindowReset_o : out std_logic;
readWindowNext_o : out std_logic;
readContentEmpty_i : in std_logic;
readContent_o : out std_logic;
readContentEnd_i : in std_logic;
readContentData_i : in std_logic_vector(31 downto 0);
writeFrameFull_i : in std_logic;
writeFrame_o : out std_logic;
writeFrameAbort_o : out std_logic;
writeContent_o : out std_logic;
writeContentData_o : out std_logic_vector(31 downto 0);
portInitialized_i : in std_logic;
outboundSymbolEmpty_o : out std_logic;
outboundSymbolRead_i : in std_logic;
outboundSymbol_o : out std_logic_vector(33 downto 0);
inboundSymbolFull_o : out std_logic;
inboundSymbolWrite_i : in std_logic;
inboundSymbol_i : in std_logic_vector(33 downto 0));
end component;
signal clk : std_logic;
signal areset_n : std_logic;
signal uartInbound : std_logic;
signal uartOutbound : std_logic;
signal portLinkTimeout : std_logic_vector(10 downto 0);
signal linkInitialized : std_logic;
signal inputPortEnable : std_logic;
signal outputPortEnable : std_logic;
signal localAckIdWrite : std_logic;
signal clrOutstandingAckId : std_logic;
signal inboundAckIdWrite : std_logic_vector(4 downto 0);
signal outstandingAckIdWrite : std_logic_vector(4 downto 0);
signal outboundAckIdWrite : std_logic_vector(4 downto 0);
signal inboundAckIdRead : std_logic_vector(4 downto 0);
signal outstandingAckIdRead : std_logic_vector(4 downto 0);
signal outboundAckIdRead : std_logic_vector(4 downto 0);
signal portInitialized : std_logic;
signal outboundSymbolEmpty : std_logic;
signal outboundSymbolRead : std_logic;
signal outboundSymbol : std_logic_vector(33 downto 0);
signal inboundSymbolFull : std_logic;
signal inboundSymbolWrite : std_logic;
signal inboundSymbol : std_logic_vector(33 downto 0);
signal readFrameEmpty : std_logic;
signal readFrame : std_logic;
signal readFrameRestart : std_logic;
signal readFrameAborted : std_logic;
signal readWindowEmpty : std_logic;
signal readWindowReset : std_logic;
signal readWindowNext : std_logic;
signal readContentEmpty : std_logic;
signal readContent : std_logic;
signal readContentEnd : std_logic;
signal readContentData : std_logic_vector(31 downto 0);
signal writeFrameFull : std_logic;
signal writeFrame : std_logic;
signal writeFrameAbort : std_logic;
signal writeContent : std_logic;
signal writeContentData : std_logic_vector(31 downto 0);
signal frameValid : std_logic_vector(0 to 63);
signal frameWrite : RioFrameArray(0 to 63);
signal frameComplete : std_logic;
signal frameExpected : std_logic;
signal frameRead : RioFrame;
signal frameReceived : std_logic;
begin
-----------------------------------------------------------------------------
-- Clock generation.
-----------------------------------------------------------------------------
ClockGenerator: process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;
-----------------------------------------------------------------------------
-- Serial protocol test driver.
-----------------------------------------------------------------------------
TestDriver: process
---------------------------------------------------------------------------
-- Procedure to receive a symbol.
---------------------------------------------------------------------------
procedure ReceiveSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
wait until outboundSymbolEmpty = '0' and clk'event and clk = '1';
assert symbolType = outboundSymbol(33 downto 32)
report "Missmatching symbol type:expected=" &
integer'image(to_integer(unsigned(symbolType))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbol(33 downto 32))))
severity error;
if ((outboundSymbol(33 downto 32) = SYMBOL_CONTROL) or
(outboundSymbol(33 downto 32) = SYMBOL_CONTROL)) then
assert symbolContent(31 downto 8) = outboundSymbol(31 downto 8)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 8)))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbol(31 downto 8))))
severity error;
elsif (outboundSymbol(33 downto 32) = SYMBOL_DATA) then
assert symbolContent(31 downto 0) = outboundSymbol(31 downto 0)
report "Missmatching symbol content:expected=" &
integer'image(to_integer(unsigned(symbolContent(31 downto 0)))) &
" got=" &
integer'image(to_integer(unsigned(outboundSymbol(31 downto 0))))
severity error;
end if;
outboundSymbolRead <= '1';
wait until clk'event and clk = '1';
outboundSymbolRead <= '0';
end procedure;
---------------------------------------------------------------------------
-- Procedure to send a symbol.
---------------------------------------------------------------------------
procedure SendSymbol(
constant symbolType : in std_logic_vector(1 downto 0);
constant symbolContent : in std_logic_vector(31 downto 0) := x"00000000") is
begin
wait until inboundSymbolFull = '0' and clk'event and clk = '1';
inboundSymbolWrite <= '1';
inboundSymbol <= symbolType & symbolContent;
wait until clk'event and clk = '1';
inboundSymbolWrite <= '0';
end procedure;
---------------------------------------------------------------------------
-- Process variables.
---------------------------------------------------------------------------
variable seed1 : positive := 1;
variable seed2 : positive := 1;
variable payload : RioPayload;
variable frame : RioFrame;
begin
---------------------------------------------------------------------------
-- Test case initialization.
---------------------------------------------------------------------------
frameValid <= (others=>'0');
frameExpected <= '0';
portLinkTimeout <= (others=>'1');
inputPortEnable <= '1';
outputPortEnable <= '1';
portInitialized <= '0';
outboundSymbolRead <= '0';
inboundSymbolWrite <= '0';
inboundSymbol <= (others => '0');
localAckIdWrite <= '0';
clrOutstandingAckId <= '0';
inboundAckIdWrite <= (others=>'0');
outstandingAckIdWrite <= (others=>'0');
outboundAckIdWrite <= (others=>'0');
-- Generate a startup reset pulse.
areset_n <= '0';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
areset_n <= '1';
wait until clk'event and clk = '1';
wait until clk'event and clk = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial");
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC1");
PrintS("Description: Test idle-sequence transmission at startup.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Read transmission port.");
PrintS("Result: Idle sequence symbols should be read.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC1-Step1");
---------------------------------------------------------------------------
-- Make sure only idle-sequences are transmitted at startup.
for i in 0 to 1024 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC2");
PrintS("Description: Test idle-sequence and status symbol transmission");
PrintS(" when the port has been initialized.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Set port initialized and read transmission port.");
PrintS("Result: Idle sequence and status symbols should be read.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step1");
---------------------------------------------------------------------------
-- Initialize the port to trigger a change of state.
portInitialized <= '1';
-- The transmitter should send idle sequences at startup and a status once
-- in a while.
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Toggle port initialized pin and check that no status ");
PrintS(" symbols are transmitted when uninitialized.");
PrintS("Result: Only idle sequences should be read when uninitialized.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step2");
---------------------------------------------------------------------------
-- Deassert the port initialized flag.
portInitialized <= '0';
-- Make sure only idle-sequences are transmitted at startup.
for i in 0 to 1024 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
-- Initialize the port to trigger a change of state.
portInitialized <= '1';
-- The transmitter should send idle sequences at startup and a status once
-- in a while.
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
for i in 0 to 254 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Send one error free status symbol to trigger the ");
PrintS(" transmission of status symbols with a higher frequency.");
PrintS("Result: Idle sequence and status symbols should be read but ");
PrintS(" status symbols should be recived more often.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step3");
---------------------------------------------------------------------------
-- A received error-free status triggers transmission of status symbols in
-- a more rapid past.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
-- The transmitter should send at least 15 additional statuses after
-- receiving an error free status.
for j in 0 to 15 loop
for i in 0 to 15 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
end loop;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Send one errornous status symbol to restart the status ");
PrintS(" counting.");
PrintS("Result: Idle sequence and status symbols should be read but ");
PrintS(" status symbols should still be received more often.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step4");
---------------------------------------------------------------------------
-- REMARK: Add this...
PrintR("Not implemented.");
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Send one errornous status symbol to restart the status ");
PrintS(" counting.");
PrintS("Result: Idle sequence and status symbols should be read but ");
PrintS(" status symbols should still be received more often.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC2-Step5");
---------------------------------------------------------------------------
-- Make the link fully initialized by sending 7 additional statuses.
for i in 0 to 6 loop
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_NOP, "000"));
end loop;
wait until linkInitialized = '1';
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC3");
PrintS("Description: Test port reception.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Send an inbound frame with pad after the CRC.");
PrintS("Result: The frame should end up in a frame buffer.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step1");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 1;
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Send an inbound frame without a pad after the CRC.");
PrintS("Result: The frame should end up in a frame buffer.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step2");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 2;
frame := RioFrameCreate(ackId=>"00001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmited frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Send an inbound frame with maximum size.");
PrintS("Result: The frame should end up in a frame buffer.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step3");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 133;
frame := RioFrameCreate(ackId=>"00010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00010", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Send two packets without end-of-packet in between.");
PrintS("Result: Both packets should be accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step4");
---------------------------------------------------------------------------
-- Create the first frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 10;
frame := RioFrameCreate(ackId=>"00011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Start the reception of a frame, implicitly ending the previous.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
wait until clk'event and clk = '1';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00011", "11111",
STYPE1_NOP, "000"));
-- Create the second frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 13;
frame := RioFrameCreate(ackId=>"00100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- End the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00100", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Start to send a packet. Abort it with stomp. Then send ");
PrintS(" another packet.");
PrintS("Result: The first packet should be discarded and the second should");
PrintS(" be accepted. The retried packet should be acknowledged.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step5");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 7;
frame := RioFrameCreate(ackId=>"00101", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_STOMP, "000"));
-- Dont expect the aborted frame anymore.
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the retry was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "00101", "11111",
STYPE1_NOP, "000"));
-- Acknowledge the canceled packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 8;
frame := RioFrameCreate(ackId=>"00101", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00101", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 6:");
PrintS("Action: Start to send a packet but dont send any payload. Abort it");
PrintS(" with stomp. Then send another packet.");
PrintS("Result: The first packet should be discarded and the second should");
PrintS(" be accepted. The retried packet should be acknowledged.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step6");
---------------------------------------------------------------------------
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_STOMP, "000"));
-- Receive an idle symbol left in the FIFO before the retry was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "00110", "11111",
STYPE1_NOP, "000"));
-- Acknowledge the canceled packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 8;
frame := RioFrameCreate(ackId=>"00110", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00110", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 7:");
PrintS("Action: Start to send a packet with payload, then send a ");
PrintS(" link-request. Then send another packet.");
PrintS("Result: The first packet should be canceled without any ");
PrintS(" confirmation and a link-response should be returned. The");
PrintS(" second packet should be accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step7");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 9;
frame := RioFrameCreate(ackId=>"00111", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Send a link-request/input-status to abort the current packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- The frame should be canceled by the link-request, dont expect it anymore.
frameExpected <= '0';
-- Receive link-response indicating normal operation and expected ackId.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00111", "10000",
STYPE1_NOP, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 10;
frame := RioFrameCreate(ackId=>"00111", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00111", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 8:");
PrintS("Action: Start to send a packet, no payload, then send a ");
PrintS(" link-request. Then send another packet.");
PrintS("Result: The first packet should be canceled without any ");
PrintS(" confirmation and a link-response should be returned. The");
PrintS(" second packet should be accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step8");
---------------------------------------------------------------------------
-- Expect an empty packet to be aborted.
frameExpected <= '1';
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send a link-request/input-status to abort the current packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Dont expect any frames anymore.
frameExpected <= '0';
-- Receive link-response indicating normal operation and expected ackId.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01000", "10000",
STYPE1_NOP, "000"));
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Send the data symbols of the frame.
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Abort the reception of the frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Check that the frame has been received in the frame buffer.
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive an idle symbol left in the FIFO before the ack was generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 9:");
PrintS("Action: Send a packet when no buffers is available. Reset receiver");
PrintS(" with link-request.");
PrintS("Result: A packet-retry should be transmitted and receiver should");
PrintS(" enter input-retry-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step9");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
SendSymbol(SYMBOL_DATA, frame.payload(0));
-- Receive notification about that the packet needs to be retried.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "01001", "11111",
STYPE1_NOP, "000"));
-- Check the status of the input port and verify the input-retry-stopped state.
-- This should also set the receiver into normal operation.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "00100",
STYPE1_NOP, "000"));
-- Check the status of the input port and verify the input-retry-stopped state.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "10000",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 10:");
PrintS("Action: Send a packet when no buffers is available. Reset receiver");
PrintS(" with restart-from-retry.");
PrintS("Result: A packet-retry should be transmitted and receiver should");
PrintS(" enter input-retry-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step10");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
SendSymbol(SYMBOL_DATA, frame.payload(0));
-- Receive notification about that the packet needs to be retried.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "01001", "11111",
STYPE1_NOP, "000"));
-- Acknowledge the retried packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Check the status of the input port and verify the input-retry-stopped state.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "10000",
STYPE1_NOP, "000"));
-- Always receive a status after a link response when leaving input-error-stopped.
-- ReceiveSymbol(SYMBOL_CONTROL,
-- RioControlSymbolCreate(STYPE0_STATUS, "01001", "11111",
-- STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 11:");
PrintS("Action: Start a new packet when in input-retry-stopped state.");
PrintS("Result: The packet should be discarded.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step11");
---------------------------------------------------------------------------
-- Create a new frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
-- Start the reception of a frame.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
SendSymbol(SYMBOL_DATA, frame.payload(0));
-- Receive notification about that the packet needs to be retried.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "01001", "11111",
STYPE1_NOP, "000"));
-- Create a packet and send it. It should be discarded.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 12;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Acknowledge the retried packet.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Create a packet and send it.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 13;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 12:");
PrintS("Action: Send an erronous control-symbol. Then restore with");
PrintS(" link-request.");
PrintS("Result: Receiver should enter input-error-stopped and return to");
PrintS(" normal operation after the link-request was receiver.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step12");
---------------------------------------------------------------------------
-- Create, corrupt and send a control symbol.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000") xor x"00100000");
-- Receive a packet-not-accepted indicating error in control-symbol crc.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "00010",
STYPE1_NOP, "000"));
-- Create a packet and send it. It should be discarded.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 14;
frame := RioFrameCreate(ackId=>"01010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Make the receiver go back to normal operation by sending a link-request.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01010", "00101",
STYPE1_NOP, "000"));
-- Always receive a status after a link response when leaving input-error-stopped.
-- ReceiveSymbol(SYMBOL_CONTROL,
-- RioControlSymbolCreate(STYPE0_STATUS, "01010", "11111",
-- STYPE1_NOP, "000"));
-- Create a packet and send it.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 15;
frame := RioFrameCreate(ackId=>"01010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01010", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 13:");
PrintS("Action: Send an erronous packet. Then restore with link-request.");
PrintS("Result: Receiver should enter input-error-stopped and return to");
PrintS(" normal operation after the link-request was receiver.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC3-Step13");
---------------------------------------------------------------------------
-- Create a packet and send it with a bit error. It should be discarded.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 15;
frame := RioFrameCreate(ackId=>"01011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frame.payload(0) := frame.payload(0) xor x"00000010";
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Receive a packet-not-accepted indicating error in control-symbol crc.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "00100",
STYPE1_NOP, "000"));
-- Dont expect any frame anymore.
frameExpected <= '0';
-- Make the receiver go back to normal operation by sending a link-request.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_LINK_REQUEST, "100"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01011", "00101",
STYPE1_NOP, "000"));
-- Send a new frame without error.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 16;
frame := RioFrameCreate(ackId=>"01011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameExpected <= '1';
frameRead <= frame;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
SendSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00000", "11111",
STYPE1_END_OF_PACKET, "000"));
wait until frameReceived = '1';
frameExpected <= '0';
-- Receive acknowledge for the transmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01011", "11111",
STYPE1_NOP, "000"));
-- REMARK: Complete with some more error situations: invalid ackId, too
-- short packet, too long packet, etc...
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("TG_RioSerial-TC4");
PrintS("Description: Test port transmission.");
PrintS("Requirement: XXXXX");
PrintS("-----------------------------------------------------------------");
PrintS("Step 1:");
PrintS("Action: Send an outbound frame.");
PrintS("Result: The frame should be read from the frame buffer and ");
PrintS(" received as symbols.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step1");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 3;
frame := RioFrameCreate(ackId=>"00000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(0) <= '1';
frameWrite(0) <= frame;
-- Make sure the transmitter fills in the correct ackId and dont use the
-- one in the input packet.
frameWrite(0).payload(0)(31 downto 27) <= "UUUUU";
-- Receive an idle symbol left in the FIFO before the start of the frame was
-- generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(0) <= '0';
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 2:");
PrintS("Action: Send an outbound packet with maximum length.");
PrintS("Result: The packet should be fragmented and received in symbols.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step2");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 133;
frame := RioFrameCreate(ackId=>"00001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(1) <= '1';
frameWrite(1) <= frame;
-- Receive an idle symbol left in the FIFO before the start of the frame was
-- generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(1) <= '0';
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 3:");
PrintS("Action: Send a packet and confirm it with packet-retry.");
PrintS("Result: A restart-from-retry should be transmitted and the packet");
PrintS(" should be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step3");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 4;
frame := RioFrameCreate(ackId=>"00010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(2) <= '1';
frameWrite(2) <= frame;
-- Receive an idle symbol left in the FIFO before the start of the frame was
-- generated.
ReceiveSymbol(SYMBOL_IDLE);
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send packet-retry that the frame should be retransmitted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "00010", "11111",
STYPE1_NOP, "000"));
-- Receive the acknowledgement for the retransmission.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_RESTART_FROM_RETRY, "000"));
-- Receive the start of the retransmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the retransmitted frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1' and clk'event and clk = '1';
frameValid(2) <= '0';
-- Receive the end of the retransmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00010", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4:");
PrintS("Action: Send a packet and confirm it with packet-not-accepted. ");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step4");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 5;
frame := RioFrameCreate(ackId=>"00011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(3) <= '1';
frameWrite(3) <= frame;
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send packet-retry that the frame should be retransmitted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
-- Receive the acknowledgement for the retransmission.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00011", "11111",
STYPE1_NOP, "000"));
-- Receive the start of the retransmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the retransmitted frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(3) <= '0';
-- Receive the end of the retransmitted frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00011", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 4.1:");
PrintS("Action: Send a packet and reject it with packet-not-accepted many");
PrintS(" times.");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" be retransmitted a few times but discarded when too many ");
PrintS(" packet-not-accepted has been received.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step4.1");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 5;
frame := RioFrameCreate(ackId=>"00100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(4) <= '1';
frameWrite(4) <= frame;
for i in 0 to 3 loop
-- Receive the start of the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
-- Receive the data symbols of the frame.
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Receive the end of the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
----------------------------------------------------------------------------
-- Send packet-not-accepted that the frame should be retransmitted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_NOT_ACCEPTED, "00000", "11111",
STYPE1_NOP, "000"));
-- Receive the acknowledgement for the retransmission.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00100", "11111",
STYPE1_NOP, "000"));
end loop;
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 5:");
PrintS("Action: Let a packet timeout expire. Then answer with link-response.");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step5");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 5;
frame := RioFrameCreate(ackId=>"00100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(5) <= '1';
frameWrite(5) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response to make the transmitter to back to normal mode.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00100", "11111",
STYPE1_NOP, "000"));
-- Receive the retransmitted frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
-- Wait for the frame to complete.
wait until frameComplete = '1';
frameValid(5) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send acknowledge that the frame was received.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00100", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 6:");
PrintS("Action: Let a packet timeout expire. Then answer with link-response");
Prints(" that indicates that the packet was received.");
PrintS("Result: A link-request should be transmitted and the packet should");
PrintS(" not be retransmitted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step6");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 6;
frame := RioFrameCreate(ackId=>"00101", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(6) <= '1';
frameWrite(6) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(6) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response that indicates that the frame was received to make
-- the transmitter to back to normal mode.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "00110", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 7:");
PrintS("Action: Let a packet timeout expire. No more replies.");
PrintS("Result: Three link-requests should be transmitted. When the third");
PrintS(" times out the link will be restarted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step7");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 7;
frame := RioFrameCreate(ackId=>"00110", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(7) <= '1';
frameWrite(7) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
-- Reinitialize the transmitter.
for i in 0 to 255 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00110", "11111",
STYPE1_NOP, "000"));
for j in 0 to 14 loop
for i in 0 to 15 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
end loop;
-- Receive the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(7) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00110", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 8:");
PrintS("Action: Let a packet timeout expire. Then answer with totally ");
PrintS(" unexpected ackId.");
PrintS("Result: A link request should be transmitted and the link should ");
PrintS(" be restarted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step8");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 8;
frame := RioFrameCreate(ackId=>"00111", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(8) <= '1';
frameWrite(8) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Wait a while to let the timer expire and receive the link-request.
for i in 0 to 2048 loop
wait until clk'event and clk = '1';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "10000", "11111",
STYPE1_NOP, "000"));
-- Reinitialize the transmitter.
for i in 0 to 255 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "00111", "11111",
STYPE1_NOP, "000"));
for j in 0 to 14 loop
for i in 0 to 15 loop
ReceiveSymbol(SYMBOL_IDLE);
end loop;
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_NOP, "000"));
end loop;
-- Receive the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(8) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "00111", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 9:");
PrintS("Action: Send status with unexpected ackId in normal operation.");
PrintS("Result: The transmitter should disregard the error.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step9");
---------------------------------------------------------------------------
-- Send a status with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive no change.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 10:");
PrintS("Action: Send packet-retry with unexpected ackId in normal operation.");
PrintS("Result: The transmitter should enter output-error-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step10");
---------------------------------------------------------------------------
-- Send a packet-retry with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_RETRY, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive link-request.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01000", "11111",
STYPE1_NOP, "000"));
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 10;
frame := RioFrameCreate(ackId=>"01000", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(9) <= '1';
frameWrite(9) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(9) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01000", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 11:");
PrintS("Action: Send packet-accepted with unexpected ackId in normal ");
PrintS(" operation.");
PrintS("Result: The transmitter should enter output-error-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step11");
---------------------------------------------------------------------------
-- Send a packet-accepted with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive link-request.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with unexpected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01001", "11111",
STYPE1_NOP, "000"));
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 11;
frame := RioFrameCreate(ackId=>"01001", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(10) <= '1';
frameWrite(10) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(10) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01001", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 12:");
PrintS("Action: Send a packet and then accept it with unexpected ackId.");
PrintS("Result: The transmitter should enter output-error-stopped.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step12");
---------------------------------------------------------------------------
-- Create the frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 12;
frame := RioFrameCreate(ackId=>"01010", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(11) <= '1';
frameWrite(11) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frame.length-1 loop
ReceiveSymbol(SYMBOL_DATA, frame.payload(i));
end loop;
wait until frameComplete = '1';
frameValid(11) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send unexpected ackId in packet-accepted.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "10000", "11111",
STYPE1_NOP, "000"));
-- Receive link-request.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_LINK_REQUEST, "100"));
-- Send a link-response with expected ackId.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_LINK_RESPONSE, "01011", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 13:");
PrintS("Action: Set two valid packets.");
PrintS("Result: The two packet should be sent without waiting for ");
PrintS(" packet-accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step13");
---------------------------------------------------------------------------
-- Create the first frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 13;
frame := RioFrameCreate(ackId=>"01011", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(12) <= '1';
frameWrite(12) <= frame;
-- Create the second frame.
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := 14;
frame := RioFrameCreate(ackId=>"01100", vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(13) <= '1';
frameWrite(13) <= frame;
-- Receive the frame.
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frameWrite(12).length-1 loop
ReceiveSymbol(SYMBOL_DATA, frameWrite(12).payload(i));
end loop;
wait until frameComplete = '1';
frameValid(12) <= '0';
-- Receive the frame.
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frameWrite(13).length-1 loop
ReceiveSymbol(SYMBOL_DATA, frameWrite(13).payload(i));
end loop;
wait until frameComplete = '1';
frameValid(13) <= '0';
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_END_OF_PACKET, "000"));
-- Send packet-accepted for both packets.
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01011", "11111",
STYPE1_NOP, "000"));
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01100", "11111",
STYPE1_NOP, "000"));
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_IDLE);
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step 14:");
PrintS("Action: Set maximum number of valid packets.");
PrintS("Result: Maximum 31 packets should be sent without waiting for ");
PrintS(" packet-accepted.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-Step14");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Create the frames.
---------------------------------------------------------------------------
for j in 0 to 47 loop
CreateRandomPayload(payload.data, seed1, seed2);
payload.length := j+13;
frame := RioFrameCreate(ackId=>std_logic_vector(to_unsigned((j+13) mod 32, 5)), vc=>'0', crf=>'0', prio=>"00",
tt=>"01", ftype=>"0000",
sourceId=>x"0000", destId=>x"0000",
payload=>payload);
frameValid(j+14) <= '1';
frameWrite(j+14) <= frame;
end loop;
---------------------------------------------------------------------------
-- Receive the frames.
---------------------------------------------------------------------------
ReceiveSymbol(SYMBOL_IDLE);
for j in 0 to 30 loop
ReceiveSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_STATUS, "01100", "11111",
STYPE1_START_OF_PACKET, "000"));
for i in 0 to frameWrite(j+14).length-1 loop
ReceiveSymbol(SYMBOL_DATA, frameWrite(j+14).payload(i));
end loop;
wait until frameComplete = '1';
frameValid(j+14) <= '0';
end loop;
ReceiveSymbol(SYMBOL_IDLE);
ReceiveSymbol(SYMBOL_IDLE);
SendSymbol(SYMBOL_CONTROL,
RioControlSymbolCreate(STYPE0_PACKET_ACCEPTED, "01101", "11111",
STYPE1_NOP, "000"));
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step X:");
PrintS("Action: Start sending an outbound packet and while in transmission, ");
PrintS(" start and complete an inbound packet.");
PrintS("Result: The ack for the inbound packet should be inserted into the");
PrintS(" outbound packet.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-StepX");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
PrintS("-----------------------------------------------------------------");
PrintS("Step X:");
PrintS("Action: Send a packet but not all content is available yet.");
PrintS("Result: Idle symbols should be inserted into the packet.");
---------------------------------------------------------------------------
PrintR("TG_RioSerial-TC4-StepX");
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- REMARK: Send long frames with a CRC in the middle...
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Test completed.
---------------------------------------------------------------------------
TestEnd;
end process;
-----------------------------------------------------------------------------
-- Instantiate the uart.
-----------------------------------------------------------------------------
TestPort: TestSwitchPort
port map(
clk=>clk, areset_n=>areset_n,
frameValid_i=>frameValid, frameWrite_i=>frameWrite, frameComplete_o=>frameComplete,
frameExpected_i=>frameExpected, frameRead_i=>frameRead, frameReceived_o=>frameReceived,
readFrameEmpty_o=>readFrameEmpty, readFrame_i=>readFrame,
readFrameRestart_i=>readFrameRestart, readFrameAborted_o=>readFrameAborted,
readWindowEmpty_o=>readWindowEmpty,
readWindowReset_i=>readWindowReset, readWindowNext_i=>readWindowNext,
readContentEmpty_o=>readContentEmpty, readContent_i=>readContent,
readContentEnd_o=>readContentEnd, readContentData_o=>readContentData,
writeFrameFull_o=>writeFrameFull, writeFrame_i=>writeFrame, writeFrameAbort_i=>writeFrameAbort,
writeContent_i=>writeContent, writeContentData_i=>writeContentData);
TestPhy: RioSerial
generic map(
TIMEOUT_WIDTH=>11)
port map(
clk=>clk, areset_n=>areset_n,
portLinkTimeout_i=>portLinkTimeout,
linkInitialized_o=>linkInitialized,
inputPortEnable_i=>inputPortEnable,
outputPortEnable_i=>outputPortEnable,
linkUninitPacketDiscardActive_i=>'0',
localAckIdWrite_i=>localAckIdWrite,
clrOutstandingAckId_i=>clrOutstandingAckId,
inboundAckId_i=>inboundAckIdWrite,
outstandingAckId_i=>outstandingAckIdWrite,
outboundAckId_i=>outboundAckIdWrite,
inboundAckId_o=>inboundAckIdRead,
outstandingAckId_o=>outstandingAckIdRead,
outboundAckId_o=>outboundAckIdRead,
readFrameEmpty_i=>readFrameEmpty, readFrame_o=>readFrame, readFrameRestart_o=>readFrameRestart,
readFrameAborted_i=>readFrameAborted,
readWindowEmpty_i=>readWindowEmpty,
readWindowReset_o=>readWindowReset, readWindowNext_o=>readWindowNext,
readContentEmpty_i=>readContentEmpty,
readContent_o=>readContent, readContentEnd_i=>readContentEnd, readContentData_i=>readContentData,
writeFrameFull_i=>writeFrameFull, writeFrame_o=>writeFrame, writeFrameAbort_o=>writeFrameAbort,
writeContent_o=>writeContent, writeContentData_o=>writeContentData,
portInitialized_i=>portInitialized,
outboundSymbolEmpty_o=>outboundSymbolEmpty, outboundSymbolRead_i=>outboundSymbolRead,
outboundSymbol_o=>outboundSymbol,
inboundSymbolFull_o=>inboundSymbolFull, inboundSymbolWrite_i=>inboundSymbolWrite,
inboundSymbol_i=>inboundSymbol);
end architecture;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
use work.rio_common.all;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
entity TestSwitchPort is
port(
clk : in std_logic;
areset_n : in std_logic;
frameValid_i : in std_logic_vector(0 to 63);
frameWrite_i : in RioFrameArray(0 to 63);
frameComplete_o : out std_logic;
frameExpected_i : in std_logic;
frameRead_i : in RioFrame;
frameReceived_o : out std_logic;
readFrameEmpty_o : out std_logic;
readFrame_i : in std_logic;
readFrameRestart_i : in std_logic;
readFrameAborted_o : out std_logic;
readWindowEmpty_o : out std_logic;
readWindowReset_i : in std_logic;
readWindowNext_i : in std_logic;
readContentEmpty_o : out std_logic;
readContent_i : in std_logic;
readContentEnd_o : out std_logic;
readContentData_o : out std_logic_vector(31 downto 0);
writeFrameFull_o : out std_logic;
writeFrame_i : in std_logic;
writeFrameAbort_i : in std_logic;
writeContent_i : in std_logic;
writeContentData_i : in std_logic_vector(31 downto 0));
end entity;
-------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------
architecture TestSwitchPortImpl of TestSwitchPort is
begin
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
FrameSender: process
variable frameIndex : natural range 0 to 70;
variable backIndex, frontIndex : natural range 0 to 63;
begin
readFrameEmpty_o <= '1';
readFrameAborted_o <= '0';
readWindowEmpty_o <= '1';
readContentEmpty_o <= '1';
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
frameComplete_o <= '0';
backIndex := 0;
frontIndex := 0;
wait until areset_n = '1';
loop
wait until clk'event and clk = '1';
if (readFrame_i = '1') then
assert (frontIndex - backIndex) >= 0 report "Unexpected readFrame." severity error;
if(backIndex < 63) then
backIndex := backIndex + 1;
else
backIndex := 0;
end if;
end if;
if (readWindowReset_i = '1') then
frameIndex := 0;
frontIndex := backIndex;
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
end if;
if (readWindowNext_i = '1') then
assert frameIndex = frameWrite_i(frontIndex).length report "Did not read all frame content." severity error;
frameComplete_o <= '1';
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
frameIndex := 0;
if(frontIndex < 63) then
frontIndex := frontIndex + 1;
else
frontIndex := 0;
end if;
else
frameComplete_o <= '0';
end if;
if (readFrameRestart_i = '1') then
frameIndex := 0;
readContentEnd_o <= '0';
readContentData_o <= (others=>'U');
end if;
if (readContent_i = '1') then
assert frameValid_i(frontIndex) = '1' report "Unexpected content read." severity error;
if (frameIndex /= frameWrite_i(frontIndex).length) then
readContentEnd_o <= '0';
readContentData_o <= frameWrite_i(frontIndex).payload(frameIndex);
frameIndex := frameIndex + 1;
else
readContentEnd_o <= '1';
readContentData_o <= (others=>'U');
end if;
end if;
if(frameValid_i(frontIndex) = '1') then
readFrameEmpty_o <= '0';
readWindowEmpty_o <= '0';
readContentEmpty_o <= '0';
else
readFrameEmpty_o <= '1';
readWindowEmpty_o <= '1';
readContentEmpty_o <= '1';
end if;
end loop;
end process;
-----------------------------------------------------------------------------
--
-----------------------------------------------------------------------------
FrameReader: process
type StateType is (STATE_IDLE, STATE_READ, STATE_UPDATE);
variable state : StateType;
variable frameIndex : natural range 0 to 69;
begin
writeFrameFull_o <= '1';
frameReceived_o <= '0';
wait until areset_n = '1';
state := STATE_IDLE;
loop
wait until clk'event and clk = '1';
case state is
when STATE_IDLE =>
frameReceived_o <= '0';
if (frameExpected_i = '1') then
state := STATE_READ;
frameIndex := 0;
writeFrameFull_o <= '0';
end if;
assert writeFrame_i = '0' report "Unexpected frame received." severity error;
--assert writeFrameAbort_i = '0' report "Unexpected frame aborted received." severity error;
assert writeContent_i = '0' report "Unexpected content received." severity error;
when STATE_READ =>
if (writeFrame_i = '1') then
state := STATE_UPDATE;
frameReceived_o <= '1';
writeFrameFull_o <= '1';
assert frameIndex = frameRead_i.length report "Did not finish the expected frame." severity error;
end if;
if (writeFrameAbort_i = '1') then
frameIndex := 0;
end if;
if (writeContent_i = '1') then
assert writeContentData_i = frameRead_i.payload(frameIndex)
report "Unexpected frame content received." severity error;
frameIndex := frameIndex + 1;
end if;
if (frameExpected_i = '0') then
state := STATE_IDLE;
end if;
when STATE_UPDATE =>
if (frameExpected_i = '0') then
state := STATE_IDLE;
end if;
end case;
end loop;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- File: mux.vhd
------------------------------------------------------------------------------
--Multiplexer design
--The output is chosen based on 2 bit control signal from 4 signals with length 4 bits
--If control signal is '00' then input F1_in is chosen to the output m_o
--If '01' then input F2_in is chosen to the output m_o
--If '10' then input F3_in is chosen to the output m_o
--If '11' then input F4_in is chosen to the output m_o
library IEEE;
use IEEE.std_logic_1164.all;
--Multiplexer entity
entity Mux is
port ( m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0);
F2_in : in STD_LOGIC_VECTOR (3 downto 0);
F3_in : in STD_LOGIC_VECTOR (3 downto 0);
F4_in : in STD_LOGIC_VECTOR (3 downto 0);
m_o : out STD_LOGIC_VECTOR (3 downto 0));
end Mux;
--Architecture of the multiplexer
architecture RTL of Mux is
begin
--Behavioural process DISP_MUX
DISP_MUX: process ( F1_in, F2_in, F3_in, F4_in, m_op ) --sensitivity list
begin
case m_op is
when "00" => m_o <= F1_in;
when "01" => m_o <= F2_in;
when "10" => m_o <= F3_in;
when "11" => m_o <= F4_in;
when others => m_o <= F1_in;
end case;
end process DISP_MUX;
end RTL; |
------------------------------------------------------------------------------
-- File: mux.vhd
------------------------------------------------------------------------------
--Multiplexer design
--The output is chosen based on 2 bit control signal from 4 signals with length 4 bits
--If control signal is '00' then input F1_in is chosen to the output m_o
--If '01' then input F2_in is chosen to the output m_o
--If '10' then input F3_in is chosen to the output m_o
--If '11' then input F4_in is chosen to the output m_o
library IEEE;
use IEEE.std_logic_1164.all;
--Multiplexer entity
entity Mux is
port ( m_op : in STD_LOGIC_VECTOR (1 downto 0);
F1_in : in STD_LOGIC_VECTOR (3 downto 0);
F2_in : in STD_LOGIC_VECTOR (3 downto 0);
F3_in : in STD_LOGIC_VECTOR (3 downto 0);
F4_in : in STD_LOGIC_VECTOR (3 downto 0);
m_o : out STD_LOGIC_VECTOR (3 downto 0));
end Mux;
--Architecture of the multiplexer
architecture RTL of Mux is
begin
--Behavioural process DISP_MUX
DISP_MUX: process ( F1_in, F2_in, F3_in, F4_in, m_op ) --sensitivity list
begin
case m_op is
when "00" => m_o <= F1_in;
when "01" => m_o <= F2_in;
when "10" => m_o <= F3_in;
when "11" => m_o <= F4_in;
when others => m_o <= F1_in;
end case;
end process DISP_MUX;
end RTL; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_xa_e
--
-- Generated
-- by: wig
-- on: Wed Jul 19 05:33:58 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../udc.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_xa_e-rtl-a.vhd,v 1.4 2006/07/19 07:35:16 wig Exp $
-- $Date: 2006/07/19 07:35:16 $
-- $Log: inst_xa_e-rtl-a.vhd,v $
-- Revision 1.4 2006/07/19 07:35:16 wig
-- Updated testcases.
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.92 2006/07/12 15:23:40 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , wilfried.gaensheimer@micronas.com
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
HOOK: global text to add to head of architecture, here is %::inst%
--
--
-- Start of Generated Architecture rtl of inst_xa_e
--
architecture rtl of inst_xa_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-----------------------------------------------------------------------------------
--! @file reducer.vhd
--! @brief REDUCER MODULE :
--! 異なるデータ幅のパスを継ぐためのアダプタ
--! @version 1.0.0
--! @date 2012/8/11
--! @author Ichiro Kawazome <ichiro_k@ca2.so-net.ne.jp>
-----------------------------------------------------------------------------------
--
-- Copyright (C) 2012 Ichiro Kawazome
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-- A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-- OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-- DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-- THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-----------------------------------------------------------------------------------
--! @brief REDUCER :
--! 異なるデータ幅のパスを継ぐためのアダプタ.
--! * REDUCER とは配管用語で径違い継ぎ手、つまり直径違う配管(パイプ)を接続
--! するために用いる管継手のことです.
--! * 論理回路の世界でも、ビット幅の異なるデータパスどうしを継ぐことが多い
--! のでこのような汎用のアダプタを作って REDUCER という名前をつけました.
--! * ちょっと汎用的に作りすぎたせいか、多少回路が冗長です.
--! 特にI_WIDTHが大きいとかなり大きな回路になってしまいます.
--! 例えば32bit入力64bit出力の場合、
--! WORD_BITS=8 、ENBL_BITS=1、I_WIDTH=4、O_WIDTH=8 とするよりも、
--! WORD_BITS=32、ENBL_BITS=4、I_WIDTH=1、O_WIDTH=2 としたほうが
--! 回路はコンパクトになります.
--! * O_WIDTH>I_WIDTHの場合、最初のワードデータを出力する際のオフセットを
--! 設定できます. 詳細はOFFSETの項を参照.
-----------------------------------------------------------------------------------
entity REDUCER is
generic (
WORD_BITS : --! @brief WORD BITS :
--! １ワードのデータのビット数を指定する.
integer := 8;
ENBL_BITS : --! @brief ENABLE BITS :
--! ワードデータのうち有効なデータであることを示す信号の
--! ビット数を指定する.
integer := 1;
I_WIDTH : --! @brief INPUT WORD WIDTH :
--! 入力側のデータのワード数を指定する.
integer := 4;
O_WIDTH : --! @brief OUTPUT WORD WIDTH :
--! 出力側のデータのワード数を指定する.
integer := 4;
QUEUE_SIZE : --! @brief QUEUE SIZE :
--! キューの大きさをワード数で指定する.
--! * 少なくともキューの大きさは、I_WIDTH+O_WIDTH-1以上で
--! なければならない.
--! * ただしQUEUE_SIZE=0を指定した場合は、キューの深さは
--! 自動的にI_WIDTH+O_WIDTH に設定される.
integer := 0;
VALID_MIN : --! @brief BUFFER VALID MINIMUM NUMBER :
--! VALID信号の配列の最小値を指定する.
integer := 0;
VALID_MAX : --! @brief BUFFER VALID MAXIMUM NUMBER :
--! VALID信号の配列の最大値を指定する.
integer := 0;
I_JUSTIFIED : --! @brief INPUT WORD JUSTIFIED :
--! 入力側の有効なデータが常にLOW側に詰められていることを
--! 示すフラグ.
--! * 常にLOW側に詰められている場合は、シフタが必要なくなる
--! ため回路が簡単になる.
integer := 0;
FLUSH_ENABLE: --! @brief FLUSH ENABLE :
--! FLUSH/I_FLUSHによるフラッシュ処理を有効にするかどうかを
--! 指定する.
--! * FLUSHとDONEとの違いは、DONEは最後のデータの出力時に
--! キューの状態をすべてクリアするのに対して、
--! FLUSHは最後のデータの出力時にENBLだけをクリアしてVALは
--! クリアしない.
--! そのため次の入力データは、最後のデータの次のワード位置
--! から格納される.
--! * フラッシュ処理を行わない場合は、0を指定すると回路が若干
--! 簡単になる.
integer := 1
);
port (
-------------------------------------------------------------------------------
-- クロック&リセット信号
-------------------------------------------------------------------------------
CLK : --! @brief CLOCK :
--! クロック信号
in std_logic;
RST : --! @brief ASYNCRONOUSE RESET :
--! 非同期リセット信号.アクティブハイ.
in std_logic;
CLR : --! @brief SYNCRONOUSE RESET :
--! 同期リセット信号.アクティブハイ.
in std_logic;
-------------------------------------------------------------------------------
-- 各種制御信号
-------------------------------------------------------------------------------
START : --! @brief START :
--! 開始信号.
--! * この信号はOFFSETを内部に設定してキューを初期化する.
--! * 最初にデータ入力と同時にアサートしても構わない.
in std_logic;
OFFSET : --! @brief OFFSET :
--! 最初のワードの出力位置を指定する.
--! * START信号がアサートされた時のみ有効.
--! * O_WIDTH>I_WIDTHの場合、最初のワードデータを出力する際の
--! オフセットを設定できる.
--! * 例えばWORD_BITS=8、I_WIDTH=1(1バイト入力)、O_WIDTH=4(4バイト出力)の場合、
--! OFFSET="0000"に設定すると、最初に入力したバイトデータは
--! 1バイト目から出力される.
--! OFFSET="0001"に設定すると、最初に入力したバイトデータは
--! 2バイト目から出力される.
--! OFFSET="0011"に設定すると、最初に入力したバイトデータは
--! 3バイト目から出力される.
--! OFFSET="0111"に設定すると、最初に入力したバイトデータは
--! 4バイト目から出力される.
in std_logic_vector(O_WIDTH-1 downto 0);
DONE : --! @brief DONE :
--! 終了信号.
--! * この信号をアサートすることで、キューに残っているデータ
--! を掃き出す.
--! その際、最後のワードと同時にO_DONE信号がアサートされる.
--! * FLUSH信号との違いは、FLUSH_ENABLEの項を参照.
in std_logic;
FLUSH : --! @brief FLUSH :
--! フラッシュ信号.
--! * この信号をアサートすることで、キューに残っているデータ
--! を掃き出す.
--! その際、最後のワードと同時にO_FLUSH信号がアサートされる.
--! * DONE信号との違いは、FLUSH_ENABLEの項を参照.
in std_logic;
BUSY : --! @brief BUSY :
--! ビジー信号.
--! * 最初にデータが入力されたときにアサートされる.
--! * 最後のデータが出力し終えたらネゲートされる.
out std_logic;
VALID : --! @brief QUEUE VALID FLAG :
--! キュー有効信号.
--! * 対応するインデックスのキューに有効なワードが入って
--! いるかどうかを示すフラグ.
out std_logic_vector(VALID_MAX downto VALID_MIN);
-------------------------------------------------------------------------------
-- 入力側 I/F
-------------------------------------------------------------------------------
I_DATA : --! @brief INPUT WORD DATA :
--! ワードデータ入力.
in std_logic_vector(I_WIDTH*WORD_BITS-1 downto 0);
I_ENBL : --! @brief INPUT WORD ENABLE :
--! ワードイネーブル信号入力.
in std_logic_vector(I_WIDTH*ENBL_BITS-1 downto 0);
I_DONE : --! @brief INPUT WORD DONE :
--! 最終ワード信号入力.
--! * 最後の力ワードデータ入であることを示すフラグ.
--! * 基本的にはDONE信号と同じ働きをするが、I_DONE信号は
--! 最後のワードデータを入力する際に同時にアサートする.
--! * I_FLUSH信号との違いはFLUSH_ENABLEの項を参照.
in std_logic;
I_FLUSH : --! @brief INPUT WORD FLUSH :
--! 最終ワード信号入力.
--! * 最後のワードデータ入力であることを示すフラグ.
--! * 基本的にはFLUSH信号と同じ働きをするが、I_FLUSH信号は
--! 最後のワードデータを入力する際に同時にアサートする.
--! * I_DONE信号との違いはFLUSH_ENABLEの項を参照.
in std_logic;
I_VAL : --! @brief INPUT WORD VALID :
--! 入力ワード有効信号.
--! * I_DATA/I_ENBL/I_DONE/I_FLUSHが有効であることを示す.
--! * I_VAL='1'and I_RDY='1'でワードデータがキューに取り込まれる.
in std_logic;
I_RDY : --! @brief INPUT WORD READY :
--! 入力レディ信号.
--! * キューが次のワードデータを入力出来ることを示す.
--! * I_VAL='1'and I_RDY='1'でワードデータがキューに取り込まれる.
out std_logic;
-------------------------------------------------------------------------------
-- 出力側 I/F
-------------------------------------------------------------------------------
O_DATA : --! @brief OUTPUT WORD DATA :
--! ワードデータ出力.
out std_logic_vector(O_WIDTH*WORD_BITS-1 downto 0);
O_ENBL : --! @brief OUTPUT WORD ENABLE :
--! ワードイネーブル信号出力.
out std_logic_vector(O_WIDTH*ENBL_BITS-1 downto 0);
O_DONE : --! @brief OUTPUT WORD DONE :
--! 最終ワード信号出力.
--! * 最後のワードデータ出力であることを示すフラグ.
--! * O_FLUSH信号との違いはFLUSH_ENABLEの項を参照.
out std_logic;
O_FLUSH : --! @brief OUTPUT WORD FLUSH :
--! 最終ワード信号出力.
--! * 最後のワードデータ出力であることを示すフラグ.
--! * O_DONE信号との違いはFLUSH_ENABLEの項を参照.
out std_logic;
O_VAL : --! @brief OUTPUT WORD VALID :
--! 出力ワード有効信号.
--! * O_DATA/O_ENBL/O_DONE/O_FLUSHが有効であることを示す.
--! * O_VAL='1'and O_RDY='1'でワードデータがキューから取り除かれる.
out std_logic;
O_RDY : --! @brief OUTPUT WORD READY :
--! 出力レディ信号.
--! * キューから次のワードを取り除く準備が出来ていることを示す.
--! * O_VAL='1'and O_RDY='1'でワードデータがキューから取り除かれる.
in std_logic
);
end REDUCER;
-----------------------------------------------------------------------------------
--
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
architecture RTL of REDUCER is
-------------------------------------------------------------------------------
--! @brief ワード単位でデータ/データイネーブル信号/ワード有効フラグをまとめておく
-------------------------------------------------------------------------------
type WORD_TYPE is record
DATA : std_logic_vector(WORD_BITS-1 downto 0);
ENBL : std_logic_vector(ENBL_BITS-1 downto 0);
VAL : boolean;
end record;
-------------------------------------------------------------------------------
--! @brief WORD TYPE の初期化時の値.
-------------------------------------------------------------------------------
constant WORD_NULL : WORD_TYPE := (DATA => (others => '0'),
ENBL => (others => '0'),
VAL => FALSE);
-------------------------------------------------------------------------------
--! @brief WORD TYPE の配列の定義.
-------------------------------------------------------------------------------
type WORD_VECTOR is array (INTEGER range <>) of WORD_TYPE;
-------------------------------------------------------------------------------
--! @brief キューの最後にワードを追加するプロシージャ.
-------------------------------------------------------------------------------
procedure APPEND(
variable QUEUE : inout WORD_VECTOR;
WORDS : in WORD_VECTOR
) is
alias vec : WORD_VECTOR(0 to WORDS'length-1) is WORDS;
type bv is array (INTEGER range <>) of boolean;
variable val : bv(QUEUE'low to QUEUE'high);
variable hit : boolean;
begin
for i in val'range loop -- 先に val を作っておいた方が論理合成の結果
val(i) := QUEUE(i).VAL; -- が良かった
end loop; --
for i in val'range loop
if (val(i) = FALSE) then
QUEUE(i) := WORD_NULL;
for pos in vec'range loop
if (i-pos-1 < val'low) then
hit := TRUE;
else
hit := val(i-pos-1);
end if;
if (hit) then
QUEUE(i) := vec(pos);
exit;
end if;
end loop;
end if;
end loop;
end APPEND;
-------------------------------------------------------------------------------
--! @brief キューのサイズを計算する関数.
-------------------------------------------------------------------------------
function QUEUE_DEPTH return integer is begin
if (QUEUE_SIZE > 0) then
if (QUEUE_SIZE >= O_WIDTH+I_WIDTH-1) then
return QUEUE_SIZE;
else
assert (QUEUE_SIZE >= I_WIDTH+O_WIDTH-1)
report "require QUEUE_SIZE >= I_WIDTH+O_WIDTH-1" severity WARNING;
return I_WIDTH+O_WIDTH;
end if;
else
return I_WIDTH+O_WIDTH;
end if;
end function;
-------------------------------------------------------------------------------
--! @brief 現在のキューの状態.
-------------------------------------------------------------------------------
signal curr_queue : WORD_VECTOR(0 to QUEUE_DEPTH-1);
-------------------------------------------------------------------------------
--! @brief 1ワード分のイネーブル信号がオール0であることを示す定数.
-------------------------------------------------------------------------------
constant ENBL_NULL : std_logic_vector(ENBL_BITS-1 downto 0) := (others => '0');
-------------------------------------------------------------------------------
--! @brief FLUSH 出力フラグ.
-------------------------------------------------------------------------------
signal flush_output : std_logic;
-------------------------------------------------------------------------------
--! @brief FLUSH 保留フラグ.
-------------------------------------------------------------------------------
signal flush_pending : std_logic;
-------------------------------------------------------------------------------
--! @brief DONE 出力フラグ.
-------------------------------------------------------------------------------
signal done_output : std_logic;
-------------------------------------------------------------------------------
--! @brief DONE 保留フラグ.
-------------------------------------------------------------------------------
signal done_pending : std_logic;
-------------------------------------------------------------------------------
--! @brief O_VAL信号を内部で使うための信号.
-------------------------------------------------------------------------------
signal o_valid : std_logic;
-------------------------------------------------------------------------------
--! @brief I_RDY信号を内部で使うための信号.
-------------------------------------------------------------------------------
signal i_ready : std_logic;
-------------------------------------------------------------------------------
--! @brief BUSY信号を内部で使うための信号.
-------------------------------------------------------------------------------
signal curr_busy : std_logic;
begin
-------------------------------------------------------------------------------
-- メインプロセス
-------------------------------------------------------------------------------
process (CLK, RST)
variable in_word : WORD_VECTOR(0 to I_WIDTH-1);
variable next_queue : WORD_VECTOR(curr_queue'range);
variable next_flush_output : std_logic;
variable next_flush_pending: std_logic;
variable next_flush_fall : std_logic;
variable next_done_output : std_logic;
variable next_done_pending : std_logic;
variable next_done_fall : std_logic;
variable pending_flag : boolean;
begin
if (RST = '1') then
curr_queue <= (others => WORD_NULL);
flush_output <= '0';
flush_pending <= '0';
done_output <= '0';
done_pending <= '0';
i_ready <= '0';
o_valid <= '0';
curr_busy <= '0';
elsif (CLK'event and CLK = '1') then
if (CLR = '1') then
curr_queue <= (others => WORD_NULL);
flush_output <= '0';
flush_pending <= '0';
done_output <= '0';
done_pending <= '0';
i_ready <= '0';
o_valid <= '0';
curr_busy <= '0';
else
-------------------------------------------------------------------
-- 次のクロックでのキューの状態を示す変数に現在のキューの状態をセット
-------------------------------------------------------------------
next_queue := curr_queue;
-------------------------------------------------------------------
-- データ出力時の次のクロックでのキューの状態に更新
-------------------------------------------------------------------
if (o_valid = '1' and O_RDY = '1') then
if (FLUSH_ENABLE > 0 ) and
(flush_output = '1') and
(O_WIDTH > 1 ) and
(curr_queue(O_WIDTH-1).VAL = FALSE) then
for i in next_queue'range loop
if (i < O_WIDTH-1) then
next_queue(i).VAL := curr_queue(i).VAL;
else
next_queue(i).VAL := FALSE;
end if;
next_queue(i).DATA := (others => '0');
next_queue(i).ENBL := (others => '0');
end loop;
else
for i in next_queue'range loop
if (i+O_WIDTH > next_queue'high) then
next_queue(i) := WORD_NULL;
else
next_queue(i) := curr_queue(i+O_WIDTH);
end if;
end loop;
end if;
end if;
-------------------------------------------------------------------
-- キュー初期化時の次のクロックでのキューの状態に更新
-------------------------------------------------------------------
if (START = '1') then
for i in next_queue'range loop
if (i < O_WIDTH-1) then
next_queue(i).VAL := (OFFSET(i) = '1');
else
next_queue(i).VAL := FALSE;
end if;
next_queue(i).DATA := (others => '0');
next_queue(i).ENBL := (others => '0');
end loop;
end if;
-------------------------------------------------------------------
-- データ入力時の次のクロックでのキューの状態に更新
-------------------------------------------------------------------
if (I_VAL = '1' and i_ready = '1') then
for i in in_word'range loop
in_word(i).DATA := I_DATA((i+1)*WORD_BITS-1 downto i*WORD_BITS);
in_word(i).ENBL := I_ENBL((i+1)*ENBL_BITS-1 downto i*ENBL_BITS);
in_word(i).VAL := (I_ENBL((i+1)*ENBL_BITS-1 downto i*ENBL_BITS) /= ENBL_NULL);
end loop;
if (I_JUSTIFIED > 0) or
(in_word'length = 1) then
APPEND(next_queue, in_word);
else
for i in in_word'range loop
if (in_word(i).VAL) then
APPEND(next_queue, in_word(i to in_word'high));
exit;
end if;
end loop;
end if;
end if;
-------------------------------------------------------------------
-- 次のクロックでのキューの状態をレジスタに保持
-------------------------------------------------------------------
curr_queue <= next_queue;
-------------------------------------------------------------------
-- 次のクロックでのキューの状態でO_WIDTHの位置にデータが入って
-- いるか否かをチェック.
-------------------------------------------------------------------
if (next_queue'high >= O_WIDTH) then
pending_flag := (next_queue(O_WIDTH).VAL);
else
pending_flag := FALSE;
end if;
-------------------------------------------------------------------
-- FLUSH制御
-------------------------------------------------------------------
if (FLUSH_ENABLE = 0) then
next_flush_output := '0';
next_flush_pending := '0';
next_flush_fall := '0';
elsif (flush_output = '1') then
if (o_valid = '1' and O_RDY = '1') then
next_flush_output := '0';
next_flush_pending := '0';
next_flush_fall := '1';
else
next_flush_output := '1';
next_flush_pending := '0';
next_flush_fall := '0';
end if;
elsif (flush_pending = '1') or
(FLUSH = '1') or
(I_VAL = '1' and i_ready = '1' and I_FLUSH = '1') then
if (pending_flag) then
next_flush_output := '0';
next_flush_pending := '1';
next_flush_fall := '0';
else
next_flush_output := '1';
next_flush_pending := '0';
next_flush_fall := '0';
end if;
else
next_flush_output := '0';
next_flush_pending := '0';
next_flush_fall := '0';
end if;
flush_output <= next_flush_output;
flush_pending <= next_flush_pending;
-------------------------------------------------------------------
-- DONE制御
-------------------------------------------------------------------
if (done_output = '1') then
if (o_valid = '1' and O_RDY = '1') then
next_done_output := '0';
next_done_pending := '0';
next_done_fall := '1';
else
next_done_output := '1';
next_done_pending := '0';
next_done_fall := '0';
end if;
elsif (done_pending = '1') or
(DONE = '1') or
(I_VAL = '1' and i_ready = '1' and I_DONE = '1') then
if (pending_flag) then
next_done_output := '0';
next_done_pending := '1';
next_done_fall := '0';
else
next_done_output := '1';
next_done_pending := '0';
next_done_fall := '0';
end if;
else
next_done_output := '0';
next_done_pending := '0';
next_done_fall := '0';
end if;
done_output <= next_done_output;
done_pending <= next_done_pending;
-------------------------------------------------------------------
-- 出力有効信号の生成
-------------------------------------------------------------------
if (next_done_output = '1') or
(next_flush_output = '1') or
(next_queue(O_WIDTH-1).VAL = TRUE) then
o_valid <= '1';
else
o_valid <= '0';
end if;
-------------------------------------------------------------------
-- 入力可能信号の生成
-------------------------------------------------------------------
if (next_done_output = '0' and next_done_pending = '0') and
(next_flush_output = '0' and next_flush_pending = '0') and
(next_queue(next_queue'length-I_WIDTH).VAL = FALSE) then
i_ready <= '1';
else
i_ready <= '0';
end if;
-------------------------------------------------------------------
-- 現在処理中であることを示すフラグ
-- 最初に入力があった時点で'1'になり、O_DONEまたはO_FLUSHが出力完了
-- した時点で'0'になる。
-------------------------------------------------------------------
if (curr_busy = '1') then
if (next_flush_fall = '1') or
(next_done_fall = '1') then
curr_busy <= '0';
else
curr_busy <= '1';
end if;
else
if (I_VAL = '1' and i_ready = '1') then
curr_busy <= '1';
else
curr_busy <= '0';
end if;
end if;
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- 各種出力信号の生成
-------------------------------------------------------------------------------
O_FLUSH <= flush_output when(FLUSH_ENABLE > 0) else '0';
O_DONE <= done_output;
O_VAL <= o_valid;
I_RDY <= i_ready;
BUSY <= curr_busy;
process (curr_queue) begin
for i in 0 to O_WIDTH-1 loop
O_DATA((i+1)*WORD_BITS-1 downto i*WORD_BITS) <= curr_queue(i).DATA;
O_ENBL((i+1)*ENBL_BITS-1 downto i*ENBL_BITS) <= curr_queue(i).ENBL;
end loop;
for i in VALID'range loop
if (curr_queue'low <= i and i <= curr_queue'high) then
if (curr_queue(i).VAL) then
VALID(i) <= '1';
else
VALID(i) <= '0';
end if;
else
VALID(i) <= '0';
end if;
end loop;
end process;
end RTL;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl_avnet is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
avnetmezz : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl_avnet is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
addressx : std_logic_vector(31 downto 0); -- shifted memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive, lsdo)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if r.address(1) = '0' then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 17) := sdmo.prdata(31 downto 17);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
v.addressx := v.address;
if avnetmezz = 1 then
if v.ramsn(1 downto 0) = "11" then -- SDRAM/SRAM shares strobes
v.mben := lsdo.dqm(3 downto 0);
end if;
if ((v.ramsn(0) and r.ramsn(0)) = '0') then -- mezz address shift
v.addressx := "00" & v.address(31 downto 2);
else
v.addressx := v.address;
end if;
else
v.addressx := "00" & v.address(31 downto 2);
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.addressx;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
if (avnetmezz = 1) then
memo.writen <= r.writen and lsdo.sdwen;
else
memo.writen <= r.writen;
end if;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= dataout;
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl_avnet is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
avnetmezz : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl_avnet is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
addressx : std_logic_vector(31 downto 0); -- shifted memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive, lsdo)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if r.address(1) = '0' then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 17) := sdmo.prdata(31 downto 17);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
v.addressx := v.address;
if avnetmezz = 1 then
if v.ramsn(1 downto 0) = "11" then -- SDRAM/SRAM shares strobes
v.mben := lsdo.dqm(3 downto 0);
end if;
if ((v.ramsn(0) and r.ramsn(0)) = '0') then -- mezz address shift
v.addressx := "00" & v.address(31 downto 2);
else
v.addressx := v.address;
end if;
else
v.addressx := "00" & v.address(31 downto 2);
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.addressx;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
if (avnetmezz = 1) then
memo.writen <= r.writen and lsdo.sdwen;
else
memo.writen <= r.writen;
end if;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= dataout;
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl_avnet is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
avnetmezz : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl_avnet is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
addressx : std_logic_vector(31 downto 0); -- shifted memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive, lsdo)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if r.address(1) = '0' then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 17) := sdmo.prdata(31 downto 17);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
v.addressx := v.address;
if avnetmezz = 1 then
if v.ramsn(1 downto 0) = "11" then -- SDRAM/SRAM shares strobes
v.mben := lsdo.dqm(3 downto 0);
end if;
if ((v.ramsn(0) and r.ramsn(0)) = '0') then -- mezz address shift
v.addressx := "00" & v.address(31 downto 2);
else
v.addressx := v.address;
end if;
else
v.addressx := "00" & v.address(31 downto 2);
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.addressx;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
if (avnetmezz = 1) then
memo.writen <= r.writen and lsdo.sdwen;
else
memo.writen <= r.writen;
end if;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= dataout;
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
|
----------------------------------------------------------------------------
-- This file is a part of the LEON VHDL model
-- Copyright (C) 1999 European Space Agency (ESA)
--
-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2 of the License, or (at your option) any later version.
--
-- See the file COPYING.LGPL for the full details of the license.
-----------------------------------------------------------------------------
-- Entity: mctrl
-- File: mctrl.vhd
-- Author: Jiri Gaisler - ESA/ESTEC
-- Description: External memory controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.memctrl.all;
library esa;
use esa.memoryctrl.all;
entity mctrl_avnet is
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
avnetmezz : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end;
architecture rtl of mctrl_avnet is
constant REVISION : integer := 1;
constant prom : integer := 1;
constant memory : integer := 0;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
4 => ahb_membar(romaddr, '1', '1', rommask),
5 => ahb_membar(ioaddr, '0', '0', iomask),
6 => ahb_membar(ramaddr, '1', '1', rammask),
others => zero32);
constant pconfig : apb_config_type := (
0 => ahb_device_reg ( VENDOR_ESA, ESA_MCTRL, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
constant RAMSEL5 : boolean := srbanks = 5;
constant SDRAMEN : boolean := (sden /= 0);
constant BUS16EN : boolean := (ram16 /= 0);
constant BUS8EN : boolean := (ram8 /= 0);
constant WPROTEN : boolean := (wprot /= 0);
constant WENDFB : boolean := false;
constant SDSEPBUS: boolean := (sepbus /= 0);
constant BUS64 : boolean := (sdbits = 64);
constant rom : integer := 0;
constant io : integer := 1;
constant ram : integer := 2;
type memcycletype is (idle, berr, bread, bwrite, bread8, bwrite8, bread16, bwrite16);
-- memory configuration register 1 type
type mcfg1type is record
romrws : std_logic_vector(3 downto 0);
romwws : std_logic_vector(3 downto 0);
romwidth : std_logic_vector(1 downto 0);
romwrite : std_logic;
ioen : std_logic;
iows : std_logic_vector(3 downto 0);
bexcen : std_logic;
brdyen : std_logic;
iowidth : std_logic_vector(1 downto 0);
end record;
-- memory configuration register 2 type
type mcfg2type is record
ramrws : std_logic_vector(1 downto 0);
ramwws : std_logic_vector(1 downto 0);
ramwidth : std_logic_vector(1 downto 0);
rambanksz : std_logic_vector(3 downto 0);
rmw : std_logic;
brdyen : std_logic;
srdis : std_logic;
sdren : std_logic;
end record;
-- memory status register type
-- local registers
type reg_type is record
address : std_logic_vector(31 downto 0); -- memory address
addressx : std_logic_vector(31 downto 0); -- shifted memory address
data : std_logic_vector(31 downto 0); -- latched memory data
writedata : std_logic_vector(31 downto 0);
writedata8 : std_logic_vector(15 downto 0); -- lsb write data buffer
sdwritedata : std_logic_vector(63 downto 0);
readdata : std_logic_vector(31 downto 0);
brdyn : std_logic;
ready : std_logic;
ready8 : std_logic;
bdrive : std_logic_vector(3 downto 0);
nbdrive : std_logic_vector(3 downto 0);
ws : std_logic_vector(3 downto 0);
romsn : std_logic_vector(1 downto 0);
ramsn : std_logic_vector(4 downto 0);
ramoen : std_logic_vector(4 downto 0);
size : std_logic_vector(1 downto 0);
busw : std_logic_vector(1 downto 0);
oen : std_logic;
iosn : std_logic_vector(1 downto 0);
read : std_logic;
wrn : std_logic_vector(3 downto 0);
writen : std_logic;
bstate : memcycletype;
area : std_logic_vector(0 to 2);
mcfg1 : mcfg1type;
mcfg2 : mcfg2type;
bexcn : std_logic; -- latched external bexcn
echeck : std_logic;
brmw : std_logic;
haddr : std_logic_vector(31 downto 0);
hsel : std_logic;
srhsel : std_logic;
sdhsel : std_logic;
hwrite : std_logic;
hburst : std_logic_vector(2 downto 0);
htrans : std_logic_vector(1 downto 0);
hresp : std_logic_vector(1 downto 0);
sa : std_logic_vector(14 downto 0);
sd : std_logic_vector(63 downto 0);
mben : std_logic_vector(3 downto 0);
end record;
signal r, ri : reg_type;
signal wrnout : std_logic_vector(3 downto 0);
signal sdmo : sdram_mctrl_out_type;
signal sdi : sdram_in_type;
signal lsdo : sdram_out_type;
-- vectored output enable to data pads
signal rbdrive, ribdrive : std_logic_vector(31 downto 0);
signal rsbdrive, risbdrive : std_logic_vector(63 downto 0);
attribute syn_preserve : boolean;
attribute syn_preserve of rbdrive : signal is true;
attribute syn_preserve of rsbdrive : signal is true;
-- **** tame: added signal to invert polarity
-- signal bprom_cs : std_ulogic;
begin
ctrl : process(rst, ahbsi, apbi, memi, r, wpo, sdmo, rbdrive, rsbdrive, lsdo)
variable v : reg_type; -- local variables for registers
variable start : std_logic;
variable dataout : std_logic_vector(31 downto 0); -- data from memory
variable regsd : std_logic_vector(31 downto 0); -- data from registers
variable memdata : std_logic_vector(31 downto 0); -- data to memory
variable rws : std_logic_vector(3 downto 0); -- read waitstates
variable wws : std_logic_vector(3 downto 0); -- write waitstates
variable wsnew : std_logic_vector(3 downto 0); -- write waitstates
variable adec : std_logic_vector(1 downto 0);
variable rams : std_logic_vector(4 downto 0);
variable bready, leadin : std_logic;
variable csen : std_logic; -- Generate chip selects
variable aprot : std_logic_vector(14 downto 0); --
variable wrn : std_logic_vector(3 downto 0); --
variable bexc, addrerr : std_logic;
variable ready : std_logic;
variable writedata : std_logic_vector(31 downto 0);
variable bwdata : std_logic_vector(31 downto 0);
variable merrtype : std_logic_vector(2 downto 0); -- memory error type
variable noerror : std_logic;
variable area : std_logic_vector(0 to 2);
variable bdrive : std_logic_vector(3 downto 0);
variable ramsn : std_logic_vector(4 downto 0);
variable romsn, busw : std_logic_vector(1 downto 0);
variable iosn : std_logic;
variable lock : std_logic;
variable wprothitx : std_logic;
variable brmw : std_logic;
variable bidle: std_logic;
variable haddr : std_logic_vector(31 downto 0);
variable hsize : std_logic_vector(1 downto 0);
variable hwrite : std_logic;
variable hburst : std_logic_vector(2 downto 0);
variable htrans : std_logic_vector(1 downto 0);
variable sdhsel, srhsel, hready : std_logic;
variable vbdrive : std_logic_vector(31 downto 0);
variable vsbdrive : std_logic_vector(63 downto 0);
variable bdrive_sel : std_logic_vector(3 downto 0);
begin
-- Variable default settings to avoid latches
v := r; wprothitx := '0'; v.ready8 := '0'; v.iosn(0) := r.iosn(1);
ready := '0'; addrerr := '0'; regsd := (others => '0'); csen := '0';
v.ready := '0'; v.echeck := '0';
merrtype := "---"; bready := '1';
vbdrive := rbdrive; vsbdrive := rsbdrive;
v.data := memi.data; v.bexcn := memi.bexcn; v.brdyn := memi.brdyn;
if (((r.brdyn and r.mcfg1.brdyen) = '1') and (r.area(io) = '1')) or
(((r.brdyn and r.mcfg2.brdyen) = '1') and (r.area(ram) = '1') and
(r.ramsn(4) = '0') and RAMSEL5)
then
bready := '0';
else bready := '1'; end if;
v.hresp := HRESP_OKAY;
if SDRAMEN and (r.hsel = '1') and (ahbsi.hready = '0') then
haddr := r.haddr; hsize := r.size; hburst := r.hburst;
htrans := r.htrans; hwrite := r.hwrite;
area := r.area;
else
haddr := ahbsi.haddr; hsize := ahbsi.hsize(1 downto 0);
hburst := ahbsi.hburst; htrans := ahbsi.htrans; hwrite := ahbsi.hwrite;
area := ahbsi.hmbsel(0 to 2);
end if;
if SDRAMEN then
if fast = 1 then
sdhsel := ahbsi.hsel(hindex) and ahbsi.haddr(sdrasel) and
ahbsi.htrans(1) and ahbsi.hmbsel(2);
else
sdhsel := ahbsi.hsel(hindex) and ahbsi.htrans(1) and
r.mcfg2.sdren and ahbsi.hmbsel(2) and (ahbsi.haddr(sdrasel) or r.mcfg2.srdis);
end if;
srhsel := ahbsi.hsel(hindex) and not sdhsel;
else sdhsel := '0'; srhsel := ahbsi.hsel(hindex); end if;
-- decode memory area parameters
leadin := '0'; rws := "----"; wws := "----"; adec := "--";
busw := (others => '-'); brmw := '0';
if area(rom) = '1' then
busw := r.mcfg1.romwidth;
end if;
if area(ram) = '1' then
adec := genmux(r.mcfg2.rambanksz, haddr(sdrasel downto 14)) &
genmux(r.mcfg2.rambanksz, haddr(sdrasel-1 downto 13));
if sdhsel = '1' then busw := "10";
else
busw := r.mcfg2.ramwidth;
if ((r.mcfg2.rmw and hwrite) = '1') and
((BUS16EN and (busw = "01") and (hsize = "00")) or
((busw(1) = '1') and (hsize(1) = '0'))
)
then brmw := '1'; end if; -- do a read-modify-write cycle
end if;
end if;
if area(io) = '1' then
leadin := '1';
busw := r.mcfg1.iowidth;
end if;
-- decode waitstates, illegal access and cacheability
if r.area(rom) = '1' then
rws := r.mcfg1.romrws; wws := r.mcfg1.romwws;
if (r.mcfg1.romwrite or r.read) = '0' then addrerr := '1'; end if;
end if;
if r.area(ram) = '1' then
rws := "00" & r.mcfg2.ramrws; wws := "00" & r.mcfg2.ramwws;
end if;
if r.area(io) = '1' then
rws := r.mcfg1.iows; wws := r.mcfg1.iows;
if r.mcfg1.ioen = '0' then addrerr := '1'; end if;
end if;
-- generate data buffer enables
bdrive := (others => '1');
case r.busw is
when "00" => if BUS8EN then bdrive := "0001"; end if;
when "01" => if BUS16EN then bdrive := "0011"; end if;
when others =>
end case;
-- generate chip select and output enable
rams := '0' & decode(adec);
case srbanks is
when 0 => rams := "00000";
when 1 => rams := "00001";
when 2 => rams := "000" & (rams(3 downto 2) or rams(1 downto 0));
when others =>
if RAMSEL5 and (haddr(sdrasel) = '1') then rams := "10000"; end if;
end case;
iosn := '1'; ramsn := (others => '1'); romsn := (others => '1');
if area(rom) = '1' then
romsn := (not haddr(romasel)) & haddr(romasel);
end if;
if area(ram) = '1' then ramsn := not rams; end if;
if area(io) = '1' then iosn := '0'; end if;
-- generate write strobe
wrn := "0000";
case r.busw is
when "00" =>
if BUS8EN then wrn := "1110"; end if;
when "01" =>
if BUS16EN then
if (r.size = "00") and (r.brmw = '0') then
wrn := "11" & (not r.address(0)) & r.address(0);
else wrn := "1100"; end if;
end if;
when "10" | "11" =>
case r.size is
when "00" =>
case r.address(1 downto 0) is
when "00" => wrn := "1110";
when "01" => wrn := "1101";
when "10" => wrn := "1011";
when others => wrn := "0111";
end case;
when "01" =>
wrn := not r.address(1) & not r.address(1) & r.address(1) & r.address(1);
when others => null;
end case;
when others => null;
end case;
if (r.mcfg2.rmw = '1') and (r.area(ram) = '1') then wrn := not bdrive; end if;
if (((ahbsi.hready and ahbsi.hsel(hindex) and ahbsi.htrans(1)) = '1'))
then
v.area := area;
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
if (brmw = '1') then
v.read := '1';
else v.read := not hwrite; end if;
v.busw := busw; v.brmw := brmw;
end if;
if (((sdmo.aload and r.hsel) = '1') and SDRAMEN) then
v.address := haddr;
if (busw = "00") and (hwrite = '0') and (area(io) = '0') and BUS8EN
then v.address(1 downto 0) := "00"; end if;
if (busw = "01") and (hwrite = '0') and (area(io) = '0') and BUS16EN
then v.address(1 downto 0) := "00"; end if;
end if;
-- Select read data depending on bus width
if BUS8EN and (r.busw = "00") then
memdata := r.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
memdata := r.readdata(15 downto 0) & r.data(31 downto 16);
else
memdata := r.data;
end if;
bwdata := memdata;
-- Merge data during byte write
writedata := ahbsi.hwdata;
if ((r.brmw and r.busw(1)) = '1')
then
case r.address(1 downto 0) is
when "00" =>
writedata(15 downto 0) := bwdata(15 downto 0);
if r.size = "00" then
writedata(23 downto 16) := bwdata(23 downto 16);
end if;
when "01" =>
writedata(31 downto 24) := bwdata(31 downto 24);
writedata(15 downto 0) := bwdata(15 downto 0);
when "10" =>
writedata(31 downto 16) := bwdata(31 downto 16);
if r.size = "00" then
writedata(7 downto 0) := bwdata(7 downto 0);
end if;
when others =>
writedata(31 downto 8) := bwdata(31 downto 8);
end case;
end if;
if (r.brmw = '1') and (r.busw = "01") and BUS16EN then
if (r.address(0) = '0') then
writedata(23 downto 16) := r.data(23 downto 16);
else
writedata(31 downto 24) := r.data(31 downto 24);
end if;
end if;
-- save read data during 8/16 bit reads
if BUS8EN and (r.ready8 = '1') and (r.busw = "00") then
v.readdata := v.readdata(23 downto 0) & r.data(31 downto 24);
elsif BUS16EN and (r.ready8 = '1') and (r.busw = "01") then
v.readdata := v.readdata(15 downto 0) & r.data(31 downto 16);
end if;
-- Ram, rom, IO access FSM
if r.read = '1' then wsnew := rws; else wsnew := wws; end if;
case r.bstate is
when idle =>
v.ws := wsnew;
if r.bdrive(0) = '1' then
if r.busw(1) = '1' then
v.writedata(31 downto 16) := writedata(31 downto 16);
elsif r.busw = "01" then
if r.address(1) = '0' then
v.writedata(31 downto 16) := writedata(31 downto 16);
else
v.writedata(31 downto 16) := writedata(15 downto 0);
end if;
else
case r.address(1 downto 0) is
when "00" =>
v.writedata(31 downto 16) := writedata(31 downto 16);
when "01" =>
v.writedata(31 downto 24) := writedata(23 downto 16);
when "10" =>
v.writedata(31 downto 16) := writedata(15 downto 0);
when "11" =>
v.writedata(31 downto 24) := writedata(7 downto 0);
when others =>
null;
end case;
end if;
v.writedata(15 downto 0) := writedata(15 downto 0);
if r.busw(1) = '0' then
v.writedata8 := writedata(15 downto 0);
end if;
end if;
if (r.srhsel = '1') and ((sdmo.busy = '0') or not SDRAMEN)
then
if WPROTEN then wprothitx := wpo.wprothit; end if;
if (wprothitx or addrerr) = '1' then
v.hresp := HRESP_ERROR; v.bstate := berr; v.bdrive := (others => '1');
elsif r.read = '0' then
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then
v.bstate := bwrite8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then
v.bstate := bwrite16;
else v.bstate := bwrite; end if;
v.wrn := wrn; v.writen := '0'; v.bdrive := not bdrive;
else
if r.oen = '1' then v.ramoen := r.ramsn; v.oen := '0';
else
if (r.busw = "00") and (r.area(io) = '0') and BUS8EN then v.bstate := bread8;
elsif (r.busw = "01") and (r.area(io) = '0') and BUS16EN then v.bstate := bread16;
else v.bstate := bread; end if;
end if;
end if;
end if;
when berr =>
v.bstate := idle; ready := '1';
v.hresp := HRESP_ERROR;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11"; v.bdrive := (others => '1');
when bread =>
if ((r.ws = "0000") and (r.ready = '0') and (bready = '1'))
then
if r.brmw = '0' then
ready := '1'; v.echeck := '1';
if r.area(io) = '0' then
v.address := ahbsi.haddr;
end if;
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE) or (r.area(io) = '1'))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
else
v.echeck := '1';
end if;
end if;
end if;
if r.ready = '1' then
v.ws := rws;
else
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
end if;
when bwrite =>
if (r.ws = "0000") and (bready = '1') then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
when bread8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.ws := rws;
v.address(1 downto 0) := r.address(1 downto 0) + 1;
if (r.address(1 downto 0) = "11") then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
end if;
end if;
if (r.ready8 = '1') then v.ws := rws;
elsif r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite8 =>
if BUS8EN then
if (r.ws = "0000") and (r.ready8 = '0') and (bready = '1') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "11") or
((r.address(1 downto 0) = "01") and (r.size = "01")) or
(r.size = "00"))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ready8 = '1') then
v.address(1 downto 0) := r.address(1 downto 0) + 1; v.ws := rws;
v.writedata(31 downto 16) := r.writedata(23 downto 16) & r.writedata8(15 downto 8);
v.writedata8(15 downto 8) := r.writedata8(7 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bread16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and ((r.address(1) or r.brmw) = '1') and
(r.ready8 = '0')
then
if r.brmw = '0' then
ready := '1'; v.address := ahbsi.haddr; v.echeck := '1';
end if;
if (((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans /= HTRANS_SEQ)) or
(r.hburst = HBURST_SINGLE))
then
if r.brmw = '0' then
v.ramsn := (others => '1'); v.romsn := (others => '1');
end if;
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bstate := idle; v.read := not r.hwrite;
end if;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.ws := rws;
if r.brmw = '0' then v.address(1) := not r.address(1); end if;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when bwrite16 =>
if BUS16EN then
if (r.ws = "0000") and (bready = '1') and
((r.address(1 downto 0) = "10") or (r.size(1) = '0'))
then
ready := '1'; v.wrn := (others => '1'); v.writen := '1'; v.echeck := '1';
v.ramsn := (others => '1'); v.romsn := (others => '1'); v.iosn := "11";
v.bdrive := (others => '1'); v.bstate := idle;
end if;
if (r.ws = "0000") and (bready = '1') and (r.ready8 = '0') then
v.ready8 := '1'; v.wrn := (others => '1'); v.writen := '1';
end if;
if (r.ready8 = '1') then
v.address(1) := not r.address(1); v.ws := rws;
v.writedata(31 downto 16) := r.writedata8(15 downto 0);
v.bstate := idle;
end if;
if r.ws /= "0000" then v.ws := r.ws - 1; end if;
else
v.bstate := idle;
end if;
when others =>
end case;
-- if BUSY or IDLE cycle seen, or if de-selected, return to idle state
if (ahbsi.hready = '1') then
if ((ahbsi.hsel(hindex) = '0') or (ahbsi.htrans = HTRANS_BUSY) or
(ahbsi.htrans = HTRANS_IDLE))
then
v.bstate := idle;
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.ramoen := (others => '1'); v.oen := '1'; v.iosn := "11";
v.bdrive := (others => '1'); v.wrn := (others => '1');
v.writen := '1'; v.hsel := '0'; ready := ahbsi.hsel(hindex); v.srhsel := '0';
elsif srhsel = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
end if;
-- error checking and reporting
noerror := '1';
if ((r.echeck and r.mcfg1.bexcen and not r.bexcn) = '1') then
noerror := '0'; v.bstate := berr; v.hresp := HRESP_ERROR; v.bdrive := (others => '1');
v.wrn := (others => '1'); v.writen := '1';
end if;
-- APB register access
case apbi.paddr(3 downto 2) is
when "00" =>
regsd(28 downto 0) := r.mcfg1.iowidth &
r.mcfg1.brdyen & r.mcfg1.bexcen & "0" & r.mcfg1.iows & r.mcfg1.ioen &
'0' &
"000000" & r.mcfg1.romwrite &
'0' & r.mcfg1.romwidth & r.mcfg1.romwws & r.mcfg1.romrws;
when "01" =>
if SDRAMEN then
regsd(31 downto 17) := sdmo.prdata(31 downto 17);
if BUS64 then regsd(18) := '1'; end if;
regsd(14 downto 13) := r.mcfg2.sdren & r.mcfg2.srdis;
end if;
regsd(12 downto 9) := r.mcfg2.rambanksz;
if RAMSEL5 then regsd(7) := r.mcfg2.brdyen; end if;
regsd(6 downto 0) := r.mcfg2.rmw & r.mcfg2.ramwidth &
r.mcfg2.ramwws & r.mcfg2.ramrws;
when "10" =>
if SDRAMEN then
regsd(26 downto 12) := sdmo.prdata(26 downto 12);
end if;
when others => regsd := (others => '0');
end case;
apbo.prdata <= regsd;
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(5 downto 2) is
when "0000" =>
v.mcfg1.romrws := apbi.pwdata(3 downto 0);
v.mcfg1.romwws := apbi.pwdata(7 downto 4);
v.mcfg1.romwidth := apbi.pwdata(9 downto 8);
v.mcfg1.romwrite := apbi.pwdata(11);
v.mcfg1.ioen := apbi.pwdata(19);
v.mcfg1.iows := apbi.pwdata(23 downto 20);
v.mcfg1.bexcen := apbi.pwdata(25);
v.mcfg1.brdyen := apbi.pwdata(26);
v.mcfg1.iowidth := apbi.pwdata(28 downto 27);
when "0001" =>
v.mcfg2.ramrws := apbi.pwdata(1 downto 0);
v.mcfg2.ramwws := apbi.pwdata(3 downto 2);
v.mcfg2.ramwidth := apbi.pwdata(5 downto 4);
v.mcfg2.rmw := apbi.pwdata(6);
v.mcfg2.brdyen := apbi.pwdata(7);
v.mcfg2.rambanksz := apbi.pwdata(12 downto 9);
if SDRAMEN then
v.mcfg2.srdis := apbi.pwdata(13);
v.mcfg2.sdren := apbi.pwdata(14);
end if;
when others => null;
end case;
end if;
-- select appropriate data during reads
if (r.area(rom) or r.area(ram)) = '1' then dataout := memdata;
else
if BUS8EN and (r.busw = "00") then
dataout := r.data(31 downto 24) & r.data(31 downto 24)
& r.data(31 downto 24) & r.data(31 downto 24);
elsif BUS16EN and (r.busw = "01") then
dataout := r.data(31 downto 16) & r.data(31 downto 16);
else dataout := r.data; end if;
end if;
v.ready := ready;
v.srhsel := r.srhsel and not ready;
if ahbsi.hready = '1' then v.hsel := ahbsi.hsel(hindex); end if;
if ((ahbsi.hready and ahbsi.hsel(hindex)) = '1') then
v.size := ahbsi.hsize(1 downto 0); v.hwrite := ahbsi.hwrite;
v.hburst := ahbsi.hburst; v.htrans := ahbsi.htrans;
if ahbsi.htrans(1) = '1' then v.hsel := '1'; v.srhsel := srhsel; end if;
if SDRAMEN then
v.haddr := ahbsi.haddr;
v.sdhsel := sdhsel;
end if;
end if;
-- sdram synchronisation
if SDRAMEN then
v.sa := sdmo.address; v.sd := memi.sd;
if (r.bstate /= idle) or ((r.ramsn & r.romsn & r.iosn) /= "111111111") then bidle := '0';
else
bidle := '1';
if (sdmo.busy and not sdmo.aload) = '1' then
if not SDSEPBUS then
v.address(sdlsb + 14 downto sdlsb) := sdmo.address;
end if;
v.romsn := (others => '1'); v.ramsn(4 downto 0) := (others => '1');
v.iosn := (others =>'1'); v.ramoen(4 downto 0) := (others => '1');
v.oen := '1';
v.bdrive := not (sdmo.bdrive & sdmo.bdrive & sdmo.bdrive & sdmo.bdrive);
if r.sdhsel = '1' then
v.hresp := sdmo.hresp;
end if;
end if;
end if;
if (sdmo.aload and r.srhsel) = '1' then
v.romsn := romsn; v.ramsn(4 downto 0) := ramsn(4 downto 0); v.iosn := iosn & '1';
if v.read = '1' then v.ramoen(4 downto 0) := ramsn(4 downto 0); v.oen := leadin; end if;
end if;
if sdmo.hsel = '1' then
v.writedata := writedata;
v.sdwritedata(31 downto 0) := writedata;
if BUS64 and sdmo.bsel = '1' then
v.sdwritedata(63 downto 32) := writedata;
end if;
hready := sdmo.hready and noerror and not r.brmw;
if SDSEPBUS then
if BUS64 and sdmo.bsel = '1' then dataout := r.sd(63 downto 32);
else dataout := r.sd(31 downto 0); end if;
end if;
else hready := r.ready and noerror; end if;
else
hready := r.ready and noerror;
end if;
if v.read = '1' then v.mben := "0000"; else v.mben := v.wrn; end if;
v.nbdrive := not v.bdrive;
if oepol = 0 then
bdrive_sel := r.bdrive;
vbdrive(31 downto 24) := (others => v.bdrive(0));
vbdrive(23 downto 16) := (others => v.bdrive(1));
vbdrive(15 downto 8) := (others => v.bdrive(2));
vbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(31 downto 24) := (others => v.bdrive(0));
vsbdrive(23 downto 16) := (others => v.bdrive(1));
vsbdrive(15 downto 8) := (others => v.bdrive(2));
vsbdrive(7 downto 0) := (others => v.bdrive(3));
vsbdrive(63 downto 56) := (others => v.bdrive(0));
vsbdrive(55 downto 48) := (others => v.bdrive(1));
vsbdrive(47 downto 40) := (others => v.bdrive(2));
vsbdrive(39 downto 32) := (others => v.bdrive(3));
else
bdrive_sel := r.nbdrive;
vbdrive(31 downto 24) := (others => v.nbdrive(0));
vbdrive(23 downto 16) := (others => v.nbdrive(1));
vbdrive(15 downto 8) := (others => v.nbdrive(2));
vbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(31 downto 24) := (others => v.nbdrive(0));
vsbdrive(23 downto 16) := (others => v.nbdrive(1));
vsbdrive(15 downto 8) := (others => v.nbdrive(2));
vsbdrive(7 downto 0) := (others => v.nbdrive(3));
vsbdrive(63 downto 56) := (others => v.nbdrive(0));
vsbdrive(55 downto 48) := (others => v.nbdrive(1));
vsbdrive(47 downto 40) := (others => v.nbdrive(2));
vsbdrive(39 downto 32) := (others => v.nbdrive(3));
end if;
-- reset
if rst = '0' then
v.bstate := idle;
v.read := '1';
v.wrn := "1111";
v.writen := '1';
v.mcfg1.romwrite := '0';
v.mcfg1.ioen := '0';
v.mcfg1.brdyen := '0';
v.mcfg1.bexcen := '0';
v.hsel := '0';
v.srhsel := '0';
v.ready := '1';
v.mcfg1.iows := "0000";
v.mcfg2.ramrws := "00";
v.mcfg2.ramwws := "00";
v.mcfg1.romrws := "1111";
v.mcfg1.romwws := "1111";
v.mcfg1.romwidth := memi.bwidth;
v.mcfg2.srdis := '0';
v.mcfg2.sdren := '0';
if syncrst = 1 then
v.ramsn := (others => '1'); v.romsn := (others => '1');
v.oen := '1'; v.iosn := "11"; v.ramoen := (others => '1');
v.bdrive := (others => '1'); v.nbdrive := (others => '0');
if oepol = 0 then vbdrive := (others => '1'); vsbdrive := (others => '1');
else vbdrive := (others => '0'); vsbdrive := (others => '0'); end if;
end if;
end if;
-- optional feeb-back from write stobe to data bus drivers
if oepol = 0 then
if WENDFB then bdrive := r.bdrive and memi.wrn;
else bdrive := r.bdrive; end if;
else
if WENDFB then bdrive := r.nbdrive or not memi.wrn;
else bdrive := r.nbdrive; end if;
end if;
-- pragma translate_off
for i in dataout'range loop --'
if is_x(dataout(i)) then dataout(i) := '1'; end if;
end loop;
-- pragma translate_on
v.addressx := v.address;
if avnetmezz = 1 then
if v.ramsn(1 downto 0) = "11" then -- SDRAM/SRAM shares strobes
v.mben := lsdo.dqm(3 downto 0);
end if;
if ((v.ramsn(0) and r.ramsn(0)) = '0') then -- mezz address shift
v.addressx := "00" & v.address(31 downto 2);
else
v.addressx := v.address;
end if;
else
v.addressx := "00" & v.address(31 downto 2);
end if;
-- drive various register inputs and external outputs
ri <= v;
ribdrive <= vbdrive;
risbdrive <= vsbdrive;
memo.address <= r.addressx;
memo.ramsn <= "111" & r.ramsn;
memo.ramoen <= "111" & r.ramoen;
memo.romsn <= "111111" & r.romsn;
memo.oen <= r.oen;
memo.iosn <= r.iosn(0);
memo.read <= r.read;
memo.wrn <= r.wrn;
if (avnetmezz = 1) then
memo.writen <= r.writen and lsdo.sdwen;
else
memo.writen <= r.writen;
end if;
memo.bdrive <= bdrive;
memo.data <= r.writedata;
memo.mben <= r.mben;
memo.vbdrive <= rbdrive;
sdi.idle <= bidle;
sdi.haddr <= haddr;
sdi.rhaddr <= r.haddr;
sdi.nhtrans <= htrans;
sdi.rhtrans <= r.htrans;
sdi.htrans <= ahbsi.htrans;
sdi.hready <= ahbsi.hready;
sdi.hsize <= r.size;
sdi.hwrite <= r.hwrite;
sdi.hsel <= sdhsel;
sdi.enable <= r.mcfg2.sdren;
sdi.srdis <= r.mcfg2.srdis;
ahbso.hrdata <= dataout;
ahbso.hready <= hready;
ahbso.hresp <= r.hresp;
end process;
stdregs : process(clk,rst)
begin
if rising_edge(clk) then
r <= ri; rbdrive <= ribdrive; rsbdrive <= risbdrive;
if rst = '0' then r.ws <= (others => '0'); end if;
end if;
if (syncrst = 0) and (rst = '0') then
r.ramsn <= (others => '1'); r.romsn <= (others => '1');
r.oen <= '1'; r.iosn <= "11"; r.ramoen <= (others => '1');
r.bdrive <= (others => '1'); r.nbdrive <= (others => '0');
if oepol = 0 then rbdrive <= (others => '1'); rsbdrive <= (others => '1');
else rbdrive <= (others => '0'); rsbdrive <= (others => '0'); end if;
end if;
end process;
ahbso.hsplit <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hirq <= (others => '0');
ahbso.hindex <= hindex;
apbo.pconfig <= pconfig;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
-- optional sdram controller
sd0 : if SDRAMEN generate
sdctrl : sdmctrl generic map (pindex, invclk, fast, wprot, sdbits, pageburst)
port map ( rst => rst, clk => clk, sdi => sdi,
sdo => lsdo, apbi => apbi, wpo => wpo, sdmo => sdmo);
rgen : if invclk = 0 generate
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end generate;
ngen : if invclk = 1 generate
nregs : process(clk, rst) begin
if falling_edge(clk) then
memo.sa <= r.sa; sdo <= lsdo; memo.svbdrive <= rsbdrive;
memo.sddata(31 downto 0) <= r.sdwritedata(31 downto 0);
memo.sddata(63 downto 32) <= r.sdwritedata(63 downto 32);
end if;
end process;
end generate;
end generate;
sd1 : if not SDRAMEN generate
sdo <= ("00", "11", '1', '1', '1', "11111111");
sdmo.prdata <= (others => '0');
sdmo.address <= (others => '0'); sdmo.busy <= '0';
sdmo.aload <= '0'; sdmo.bdrive <= '0'; sdmo.hready <= '1';
sdmo.hresp <= "11";
end generate;
end;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.2
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_2;
USE blk_mem_gen_v8_2.blk_mem_gen_v8_2;
ENTITY design_1_blk_mem_gen_0_0 IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END design_1_blk_mem_gen_0_0;
ARCHITECTURE design_1_blk_mem_gen_0_0_arch OF design_1_blk_mem_gen_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_2 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
sleep : IN STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_2;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "blk_mem_gen_v8_2,Vivado 2014.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_blk_mem_gen_0_0_arch : ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_2,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_blk_mem_gen_0_0_arch: ARCHITECTURE IS "design_1_blk_mem_gen_0_0,blk_mem_gen_v8_2,{x_ipProduct=Vivado 2014.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.2,x_ipCoreRevision=3,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_XDEVICEFAMILY=zynq,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=1,C_ENABLE_32BIT_ADDRESS=1,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_coe_file_loaded,C_INIT_FILE=NONE,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=1,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=2048,C_READ_DEPTH_A=2048,C_ADDRA_WIDTH=32,C_HAS_RSTB=1,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=1,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32,C_WRITE_DEPTH_B=2048,C_READ_DEPTH_B=2048,C_ADDRB_WIDTH=32,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=0,C_EST_POWER_SUMMARY=Estimated Power for IP _ 10.7492 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF rsta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA RST";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF rstb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB RST";
ATTRIBUTE X_INTERFACE_INFO OF enb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB EN";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_2
GENERIC MAP (
C_FAMILY => "zynq",
C_XDEVICEFAMILY => "zynq",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 1,
C_ENABLE_32BIT_ADDRESS => 1,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
C_INIT_FILE_NAME => "no_coe_file_loaded",
C_INIT_FILE => "NONE",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 1,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
C_WRITE_DEPTH_A => 2048,
C_READ_DEPTH_A => 2048,
C_ADDRA_WIDTH => 32,
C_HAS_RSTB => 1,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 1,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
C_WRITE_DEPTH_B => 2048,
C_READ_DEPTH_B => 2048,
C_ADDRB_WIDTH => 32,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 0,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "0",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 10.7492 mW"
)
PORT MAP (
clka => clka,
rsta => rsta,
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => rstb,
enb => enb,
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END design_1_blk_mem_gen_0_0_arch;
|
---------------------------------------------------------------------------------
-- Title : 1000 BASE X link autonegotiation
-- Project : General Purpose Core
---------------------------------------------------------------------------------
-- File : Eth1000BaseXAutoNeg.vhd
-- Author : Kurtis Nishimura
---------------------------------------------------------------------------------
-- Description:
-- Autonegotiation for 1000 BASE-X.
---------------------------------------------------------------------------------
LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.UtilityPkg.all;
use work.Eth1000BaseXPkg.all;
entity Eth1000BaseXAutoNeg is
generic (
GATE_DELAY_G : time := 1 ns;
PIPE_STAGES_G : integer range 1 to 8 := 2;
SIM_SPEEDUP_G : boolean := false
);
port (
-- GT user clock and reset (62.5 MHz)
ethRx62Clk : in sl;
ethRx62Rst : in sl;
-- Autonegotiation is done
autonegDone : out sl;
-- Link is synchronized
rxLinkSync : in sl;
-- Physical Interface Signals
phyRxData : in EthRxPhyLaneInType;
phyTxData : out EthTxPhyLaneOutType
);
end Eth1000BaseXAutoNeg;
architecture rtl of Eth1000BaseXAutoNeg is
type AutoNegStateType is (S_IDLE, S_AUTONEG_RESTART, S_ABILITY_DETECT,
S_ACK_DETECT, S_COMPLETE_ACK, S_FIRST_IDLE,
S_IDLE_DETECT, S_LINK_UP);
type PhyRxDataArray is array (PIPE_STAGES_G-1 downto 0) of EthRxPhyLaneInType;
type RegType is record
autoNegState : AutoNegStateType;
rxDataPipe : PhyRxDataArray;
txData : slv(15 downto 0);
toggleC1C2 : sl;
toggleWord : sl;
timerCnt : slv(19 downto 0);
sendIdle : sl;
useI1 : sl;
linkUp : sl;
newState : sl;
end record RegType;
constant REG_INIT_C : RegType := (
autoNegState => S_IDLE,
rxDataPipe => (others => ETH_RX_PHY_LANE_IN_INIT_C),
txData => (others => '0'),
toggleC1C2 => '0',
toggleWord => '0',
timerCnt => (others => '0'),
sendIdle => '0',
useI1 => '0',
linkUp => '0',
newState => '0'
);
signal r : RegType := REG_INIT_C;
signal rin : RegType;
-- Signals for outputs from the match unit
signal abilityMatch : sl;
signal acknowledgeMatch : sl;
signal consistencyMatch : sl;
signal idleMatch : sl;
signal ability : slv(15 downto 0);
constant LINK_TIMER_SIM_C : natural := 625; -- 10 us at 62.5 MHz
constant THIS_LINK_TIMER_C : natural := sel(SIM_SPEEDUP_G,LINK_TIMER_SIM_C,LINK_TIMER_C);
-- ISE attributes to keep signals for debugging
-- attribute keep : string;
-- attribute keep of r : signal is "true";
-- attribute keep of crcOut : signal is "true";
-- Vivado attributes to keep signals for debugging
-- attribute dont_touch : string;
-- attribute dont_touch of r : signal is "true";
-- attribute dont_touch of crcOut : signal is "true";
begin
-- Match unit
U_AbMatch : entity work.Eth1000BaseXAbilityMatch
generic map (
GATE_DELAY_G => GATE_DELAY_G)
port map (
ethRx62Clk => ethRx62Clk,
ethRx62Rst => ethRx62Rst,
rxLinkSync => rxLinkSync,
newState => r.newState,
abilityMatch => abilityMatch,
ability => ability,
acknowledgeMatch => acknowledgeMatch,
consistencyMatch => consistencyMatch,
idleMatch => idleMatch,
phyRxData => r.rxDataPipe(PIPE_STAGES_G-1)
);
comb : process(r,phyRxData,ethRx62Rst,rxLinkSync,abilityMatch,
acknowledgeMatch,consistencyMatch,idleMatch,ability) is
variable v : RegType;
begin
v := r;
-- Pipeline for incoming data
for i in PIPE_STAGES_G-1 downto 0 loop
if (i /= 0) then
v.rxDataPipe(i) := v.rxDataPipe(i-1);
else
v.rxDataPipe(0) := phyRxData;
end if;
end loop;
-- Toggle the configuration bit if toggleWord is 1
if (r.toggleWord = '1') then
v.toggleC1C2 := not(r.toggleC1C2);
end if;
-- Always switch between /C(1,2)/ and ConfigReg
v.toggleWord := not(r.toggleWord);
-- Choose what to send here (idle or configuration)
if (r.sendIdle = '0') then
if (r.toggleWord = '0') then
if (r.toggleC1C2 = '0') then
phyTxData.data <= OS_C1_C;
phyTxData.dataK <= "01";
else
phyTxData.data <= OS_C2_C;
phyTxData.dataK <= "01";
end if;
else
phyTxData.data <= r.txData;
phyTxData.dataK <= "00";
end if;
else
phyTxData.dataK <= "01";
if (r.useI1 = '1') then
phyTxData.data <= OS_I1_C;
else
phyTxData.data <= OS_I2_C;
end if;
end if;
-- Regardless of what you're sending, the data is valid
phyTxData.valid <= '1';
-- Combinatorial state logic
case(r.autoNegState) is
-- Just transmit breaklink until you get a restart
when S_IDLE =>
v.txData := OS_BL_C;
v.sendIdle := '0';
v.timerCnt := (others => '0');
v.linkUp := '0';
if (rxLinkSync = '1') then
v.autoNegState := S_AUTONEG_RESTART;
end if;
-- Transmit breaklink for 10 ms
when S_AUTONEG_RESTART =>
v.sendIdle := '0';
v.txData := OS_BL_C;
v.timerCnt := r.timerCnt + 1;
if (r.timerCnt > THIS_LINK_TIMER_C) then
v.timerCnt := (others => '0');
v.autoNegState := S_ABILITY_DETECT;
end if;
-- Transmit own configuration with no ack
-- Exit when we see 3 consistent non-breaklink configs
when S_ABILITY_DETECT =>
v.sendIdle := '0';
v.txData := OS_CN_C;
if (abilityMatch = '1' and ability /= 0) then
v.autoNegState := S_ACK_DETECT;
end if;
-- Send configuration with ack bit
-- Back to start on ackMatch and not(consistMatch)
-- Success if we get ackMatch and consistencyMatch
when S_ACK_DETECT =>
v.sendIdle := '0';
v.txData := OS_CA_C;
if ( (acknowledgeMatch = '1' and consistencyMatch = '0') or
(abilityMatch = '1' and ability = 0) ) then
v.autoNegState := S_IDLE;
elsif (acknowledgeMatch = '1' and consistencyMatch = '1') then
v.autoNegState := S_COMPLETE_ACK;
end if;
-- Just send configuration with ack bit for timeout period
-- (we're not trying to do next pages [yet])
when S_COMPLETE_ACK =>
v.sendIdle := '0';
v.txData := OS_CA_C;
if (abilityMatch = '1' and ability = 0) then
v.autoNegState := S_IDLE;
end if;
if (r.timerCnt < THIS_LINK_TIMER_C) then
v.timerCnt := r.timerCnt + 1;
elsif (abilityMatch = '0' or ability /= 0) then
v.timerCnt := (others => '0');
--v.autoNegState := S_FIRST_IDLE;
v.autoNegState := S_IDLE_DETECT;
end if;
-- Send one I1 to flip disparity
when S_FIRST_IDLE =>
v.sendIdle := '1';
v.useI1 := '1';
v.autoNegState := S_IDLE_DETECT;
-- Send idles
when S_IDLE_DETECT =>
v.sendIdle := '1';
v.useI1 := '0';
if (abilityMatch = '1' and ability = 0) then
v.autoNegState := S_IDLE;
end if;
if (r.timerCnt < THIS_LINK_TIMER_C) then
v.timerCnt := r.timerCnt + 1;
elsif (idleMatch = '1') then
v.timerCnt := (others => '0');
v.autoNegState := S_LINK_UP;
end if;
when S_LINK_UP =>
v.sendIdle := '1';
v.linkUp := '1';
if (abilityMatch = '1') then
v.autoNegState := S_IDLE;
end if;
when others =>
end case;
-- If we lose sync, always go back to the start
if (rxLinkSync = '0') then
v.autoNegState := S_IDLE;
end if;
-- Check for new state condition
if (v.autoNegState /= r.autoNegState) then
v.newState := '1';
else
v.newState := '0';
end if;
-- Reset logic
if (ethRx62Rst = '1') then
v := REG_INIT_C;
end if;
-- Connections to output ports
autonegDone <= r.linkUp;
rin <= v;
end process;
seq : process (ethRx62Clk) is
begin
if (rising_edge(ethRx62Clk)) then
r <= rin after GATE_DELAY_G;
end if;
end process seq;
end rtl;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := stratix3;
constant CFG_MEMTECH : integer := stratix3;
constant CFG_PADTECH : integer := stratix3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := stratix3;
constant CFG_CLKMUL : integer := (30);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 8;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 0;
constant CFG_ITLBNUM : integer := 2;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0058#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000012#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDR2SP : integer := 1;
constant CFG_DDR2SP_INIT : integer := 1;
constant CFG_DDR2SP_FREQ : integer := (200);
constant CFG_DDR2SP_TRFC : integer := (130);
constant CFG_DDR2SP_DATAWIDTH : integer := (64);
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := (10);
constant CFG_DDR2SP_SIZE : integer := (256);
constant CFG_DDR2SP_DELAY0 : integer := (0);
constant CFG_DDR2SP_DELAY1 : integer := (0);
constant CFG_DDR2SP_DELAY2 : integer := (0);
constant CFG_DDR2SP_DELAY3 : integer := (0);
constant CFG_DDR2SP_DELAY4 : integer := (0);
constant CFG_DDR2SP_DELAY5 : integer := (0);
constant CFG_DDR2SP_DELAY6 : integer := (0);
constant CFG_DDR2SP_DELAY7 : integer := (0);
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 16;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
--! @file file_source_tb.vhd
--! @brief File Source testbench
--! @author Scott Teal (Scott@Teals.org)
--! @date 2013-12-14
--! @copyright
--! Copyright 2013 Richard Scott Teal, Jr.
--!
--! Licensed under the Apache License, Version 2.0 (the "License"); you may not
--! use this file except in compliance with the License. You may obtain a copy
--! of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
--! WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
--! License for the specific language governing permissions and limitations
--! under the License.
--! Standard IEEE Library
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.fixed_float_types.all;
library boostdsp;
use boostdsp.fixed_pkg.all;
use boostdsp.util_pkg.all;
use boostdsp.basic_pkg;
entity file_source_tb is
generic (
FILE_NAME : string := string'("file_source_tb.txt")
);
end entity file_source_tb;
architecture sim of file_source_tb is
constant clk_p : time := 10 ns;
constant clk_hp : time := clk_p / 2;
signal clk : std_logic := '0'; --! Clock line
signal rst : std_logic := '1'; --! Reset line
signal dout : sfixed(4 downto -9); --! Data output (range -16 to 16)
signal data_visualized : signed(13 downto 0);
begin
uut : basic_pkg.file_source
generic map (
FILE_NAME => FILE_NAME
)
port map (
clk => clk,
rst => rst,
dout => dout
);
--! Clock generator
clk_proc : process
begin
wait for clk_hp;
clk <= not clk;
end process;
--! Reset generator
rst_proc : process
begin
wait for clk_p * 4;
rst <= '0';
wait;
end process;
data_visualized <= sfixed_as_signed(dout);
end sim;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity left_shift_n is
generic ( N : positive := 8 );
port (
x : in std_logic_vector ( N downto 1 );
y : out std_logic_vector ( N downto 1 )
);
end entity left_shift_n;
architecture left_shift_n_impl of left_shift_n is
begin
y <= std_logic_vector(unsigned(x) sll 1);
end architecture left_shift_n_impl; |
-- NEED RESULT: ARCH00621: Concurrent proc call 1 passed
-- NEED RESULT: ARCH00621.P1: Multi transport transactions occurred on concurrent signal asg passed
-- NEED RESULT: ARCH00621: Concurrent proc call 2 passed
-- NEED RESULT: ARCH00621: One transport transaction occurred on a concurrent signal asg passed
-- NEED RESULT: ARCH00621: Old transactions were removed on a concurrent signal asg passed
-- NEED RESULT: P1: Transport transactions completed entirely passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00621
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 9.3 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00621(ARCH00621)
-- ENT00621_Test_Bench(ARCH00621_Test_Bench)
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00621 is
end ENT00621 ;
--
--
architecture ARCH00621 of ENT00621 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
--
subtype chk_time_type is Time ;
signal s_st_arr1_vector_savt : chk_time_type := 0 ns ;
--
subtype chk_cnt_type is Integer ;
signal s_st_arr1_vector_cnt : chk_cnt_type := 0 ;
--
type select_type is range 1 to 3 ;
signal st_arr1_vector_select : select_type := 1 ;
--
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
--
procedure P1
(signal s_st_arr1_vector : in st_arr1_vector ;
signal select_sig : out Select_Type ;
signal savtime : out Chk_Time_Type ;
signal chk_sig : out Chk_Sig_Type ;
signal count : out Integer)
is
variable correct : boolean ;
begin
case s_st_arr1_vector_cnt is
when 0
=> null ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00621" ,
"Concurrent proc call 1",
correct ) ;
--
when 2
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00621.P1" ,
"Multi transport transactions occurred on " &
"concurrent signal asg",
correct ) ;
--
select_sig <= transport 2 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
-- c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_2(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00621" ,
"Concurrent proc call 2",
correct ) ;
select_sig <= transport 3 ;
-- s_st_arr1_vector(highb)(lowb to highb-1) <= transport
-- c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns ;
--
when 4
=> correct :=
s_st_arr1_vector(highb)(lowb to highb-1) =
c_st_arr1_vector_1(highb)(lowb to highb-1) and
(s_st_arr1_vector_savt + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00621" ,
"One transport transaction occurred on a " &
"concurrent signal asg",
correct ) ;
test_report ( "ARCH00621" ,
"Old transactions were removed on a " &
"concurrent signal asg",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00621" ,
"Old transactions were removed on a " &
"concurrent signal asg",
false ) ;
--
end case ;
--
savtime <= transport Std.Standard.Now ;
chk_sig <= transport s_st_arr1_vector_cnt
after (1 us - Std.Standard.Now) ;
count <= transport s_st_arr1_vector_cnt + 1 ;
--
end ;
--
begin
CHG1 :
P1(
s_st_arr1_vector ,
st_arr1_vector_select ,
s_st_arr1_vector_savt ,
chk_st_arr1_vector ,
s_st_arr1_vector_cnt ) ;
--
PGEN_CHKP_1 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions completed entirely",
chk_st_arr1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
--
with st_arr1_vector_select select
s_st_arr1_vector(highb)(lowb to highb-1) <= transport
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns
when 1,
--
c_st_arr1_vector_2(highb)(lowb to highb-1) after 10 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 20 ns ,
c_st_arr1_vector_2(highb)(lowb to highb-1) after 30 ns ,
c_st_arr1_vector_1(highb)(lowb to highb-1) after 40 ns
when 2,
--
c_st_arr1_vector_1(highb)(lowb to highb-1) after 5 ns when 3 ;
--
end ARCH00621 ;
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00621_Test_Bench is
end ENT00621_Test_Bench ;
--
--
architecture ARCH00621_Test_Bench of ENT00621_Test_Bench is
begin
L1:
block
component UUT
end component ;
--
for CIS1 : UUT use entity WORK.ENT00621 ( ARCH00621 ) ;
begin
CIS1 : UUT
;
end block L1 ;
end ARCH00621_Test_Bench ;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.debug.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 8; -- rom data width (8/32)
romdepth : integer := 23; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 1 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal clkout, pllref : std_ulogic;
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal ramsn : std_ulogic;
signal ramoen : std_ulogic;
signal rwen : std_ulogic;
signal mben : std_logic_vector(3 downto 0);
--signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_ulogic;
signal iosn : std_ulogic;
signal oen : std_ulogic;
--signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubren, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_ulogic; -- clk en
signal sdcsn : std_ulogic; -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector (3 downto 0); -- data i/o mask
signal sdclk : std_ulogic;
signal sdba : std_logic_vector(1 downto 0);
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
--signal txd2, rxd2 : std_ulogic;
-- for smc lan chip
signal eth_aen : std_ulogic; -- for smsc eth
signal eth_readn : std_ulogic; -- for smsc eth
signal eth_writen : std_ulogic; -- for smsc eth
signal eth_nbe : std_logic_vector(3 downto 0); -- for smsc eth
signal eth_datacsn : std_ulogic;
constant lresp : boolean := false;
signal sa : std_logic_vector(14 downto 0);
signal sd : std_logic_vector(31 downto 0);
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= dsurst;
dsubren <= '1'; rxd1 <= '1';
d3 : entity work.leon3mp generic map (fabtech, memtech, padtech, clktech,
ncpu, disas, dbguart, pclow )
port map (rst, clk, error, address, data, ramsn, ramoen, rwen, mben, iosn,
romsn, oen, writen, open, open, sa(11 downto 0), sd, sdclk, sdcke,
sdcsn, sdwen, sdrasn, sdcasn, sddqm, sdba, dsutx, dsurx, dsubren,
dsuact, rxd1, txd1, eth_aen, eth_readn,
eth_writen, eth_nbe);
sd1 : if (CFG_MCTRL_SDEN = 1) and (CFG_MCTRL_SEPBUS = 1) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sd(31 downto 16), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sd(15 downto 0), Addr => sa(12 downto 0),
Ba => sdba, Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
-- 8 bit prom
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24),
romsn, rwen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn,
rwen, ramoen);
end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2500 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
data <= buskeep(data), (others => 'H') after 250 ns;
sd <= buskeep(sd), (others => 'H') after 250 ns;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
-- Implementation of a 5-stage pipelined MIPS processor's instruction decode stage
-- 2015-08-03 Lukas Jaeger created
-- 2015-08-04 Lukas Jaeger added architecture and started to implement both processes
-- 2015-08-04 Lukas Jaeger added asynchronous reset
-- 2015-08-05 Lukas Jaeger fixed bugs that resulted from me not knowing any VHDL
-- 2015-08-05 Lukas Jaeger added functionality for branch logic
-- 2015-08-06 Lukas, Carlos fixed bug in JAL-instruction-decode
-- 2015-08-06 Lukas added signed/unsigned logic for immediate-output
-- 2015-08-07 Lukas added signed/unsigned exceptions for LW-instructions
-- 2015-08-11 Lukas fixed some bugs in forwarding
-- 2015-08-11 Bahri Enis Demirtel added BLEZ, BLTZ, BLTZAL, BNE
-- 2015-08-12 Lukas fixed bug in immediate expansion and made it falling clock edge sensitive
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity instruction_decode is
port(instr,ip_in, writeback, alu_result, mem_result : in std_logic_vector (31 downto 0);
writeback_reg, regdest_ex, regdest_mem : in std_logic_vector (4 downto 0);
regdest_mux, regshift_mux: in std_logic_vector (1 downto 0);
clk, reset, enable_regs: in std_logic;
reg_a, reg_b, imm, ip_out : out std_logic_vector (31 downto 0);
reg_dest, shift_out : out std_logic_vector (4 downto 0)
);
end entity;
architecture behavioral of instruction_decode is
type regfile is array (31 downto 0) of std_logic_vector (31 downto 0);
signal register_file : regfile;
signal imm_internal : std_logic_vector(31 downto 0) := x"00000000";
signal internal_writeback : std_logic_vector(31 downto 0);
signal pc_imm : std_logic_vector (31 downto 0);
signal imm_16 : std_logic_vector (15 downto 0);
signal internal_wb_flag : std_logic := '0';
begin
imm_16 <= instr (15 downto 0);
-- Splitting registers for R-type-instructions
pc_imm <= imm_internal (31 downto 2) & "00";
-- Defines the instruction decode logic
logic : process (instr, ip_in, writeback, alu_result, mem_result, writeback_reg, regdest_ex, regdest_mem, regdest_mux, regshift_mux) is
begin
-- Forwarding logic for reg_a
-- If the destination register is still used by the writeback-phase, the writeback-output is forwarded
if ((instr (25 downto 21) = regdest_ex) and (instr (25 downto 21) /= "00000")) then
reg_a <= alu_result;
-- If the destination register is still used by the memory-phase, the alu-result is forwarded
elsif ((instr (25 downto 21) = regdest_mem) and (instr (25 downto 21) /= "00000")) then
reg_a <= mem_result;
elsif ((instr (25 downto 21) = writeback_reg)and (instr (25 downto 21) /= "00000")) then
reg_a <= writeback;
-- Otherwise, no forwarding is required and the register specified by rs is read
else
reg_a <= register_file(to_integer(unsigned (instr (25 downto 21))));
end if;
--Forwarding logic for reg_b. Works analogously to the reg_a block above
if ((instr (20 downto 16) = regdest_ex) and (instr (20 downto 16) /= "00000")) then
reg_b <= alu_result;
elsif ((instr (20 downto 16) = regdest_mem) and (instr (20 downto 16) /= "00000")) then
reg_b <= mem_result;
elsif ((instr (20 downto 16) = writeback_reg) and (instr (20 downto 16) /= "00000")) then
reg_b <= writeback;
else
reg_b <= register_file(to_integer(unsigned (instr (20 downto 16))));
end if;
case regshift_mux is -- Determines the output at shift_out
when "00" => shift_out <= instr(10 downto 6);
when "01" => shift_out <= "10000";
when others => shift_out <= "00000";
end case;
case regdest_mux is -- Determines the output at reg_dest
when "00" => reg_dest <= instr (15 downto 11);
when "01" => reg_dest <= "11111";
when "10" => reg_dest <= instr (20 downto 16);
when others => reg_dest <= "00000";
end case;
end process;
-- Process for clocked writebacks to the register file and the asynchronous reset
register_file_write : process (clk,reset,writeback_reg) is
begin
if (reset= '1') then -- asynchronous reset
for i in 0 to 31 loop
register_file(i) <= x"00000000";
end loop;
elsif (clk'event and clk = '0') then
if (enable_regs = '1') then -- If register file is enabled, write back result
if (to_integer(unsigned (writeback_reg)) > 0) then
register_file(to_integer(unsigned (writeback_reg))) <= writeback;
end if;
elsif (internal_wb_flag = '1') then
register_file (31) <= internal_writeback;
end if;
end if;
end process;
-- Process that defines the branch logic
branch_logic : process (instr, ip_in, writeback, alu_result, mem_result, writeback_reg, regdest_ex, regdest_mem, regdest_mux, regshift_mux) is
variable offset : integer;
variable a, b : integer;
begin
-- Prepares values of reg_a and reg_b for comparison
if ((instr (25 downto 21) = regdest_ex) and (instr (25 downto 21) /= "00000")) then
a := to_integer(signed(alu_result));
elsif ((instr (25 downto 21) = regdest_mem) and (instr (25 downto 21) /= "00000")) then
a := to_integer(signed(mem_result));
elsif ((instr (25 downto 21) = writeback_reg) and (instr (25 downto 21) /= "00000")) then
a := to_integer(signed(writeback));
else
a := to_integer(signed(register_file(to_integer(unsigned (instr (25 downto 21))))));
end if;
if ((instr (20 downto 16) = regdest_ex) and (instr (20 downto 16) /= "00000")) then
b:= to_integer(signed(alu_result));
elsif ((instr (20 downto 16) = regdest_mem) and (instr (20 downto 16) /= "00000")) then
b := to_integer(signed(mem_result));
elsif ((instr (20 downto 16) = writeback_reg) and (instr (20 downto 16) /= "00000")) then
b := to_integer(signed(writeback));
else
b := to_integer(signed(register_file(to_integer(unsigned (instr (20 downto 16))))));
end if;
-- Annoyingly lengthy list of if-statements for calculation of branch logic
if (instr (31 downto 26) = "000010") then -- Jump instruction
internal_wb_flag <= '0';
offset := to_integer(signed(instr(25 downto 0)));
offset := (offset * 4);
ip_out <= ip_in (31 downto 28) & std_logic_vector(to_signed(offset,28));
elsif ((instr (31 downto 26) = "000011") or (instr (31 downto 26) = "011101")) then --JAL(X) instruction
internal_writeback <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4,32));
internal_wb_flag <= '1';
offset := to_integer(signed(instr(25 downto 0)));
offset := offset * 4;
ip_out <= ip_in (31 downto 28) & std_logic_vector(to_signed(offset,28));
elsif ((instr(31 downto 26) = "000000") and (instr (20 downto 0) ="000000000000000001000")) then --JR instruction
internal_wb_flag <= '0';
offset := to_integer(signed(instr(25 downto 0)));
offset := offset * 4;
-- VHDL code de ja-vu?
-- This is the same forwarding logic as above for reg_a
if ((instr (25 downto 21) = regdest_ex) and (instr (25 downto 21) /= "00000")) then
ip_out <= alu_result;
elsif ((instr (25 downto 21) = regdest_mem) and (instr (25 downto 21) /= "00000")) then
ip_out <= mem_result;
elsif ((instr (25 downto 21) = writeback_reg) and (instr (25 downto 21) /= "00000")) then
ip_out <= writeback;
else
ip_out <= register_file(to_integer(unsigned (instr (25 downto 21))));
end if;
elsif (instr (31 downto 26) = "000100") then --BEQ
internal_wb_flag <= '0';
if (a = b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif ((instr (31 downto 26) = "000001") and (instr (20 downto 16) = "00001")) then --BGEZ instruction
internal_wb_flag <= '0';
b :=0;
if (a >= b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif ((instr (31 downto 26) = "000001") and (instr (20 downto 16) = "10001")) then --BGEZAL instruction
internal_wb_flag <= '1';
internal_writeback <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4,32));
b :=0;
if (a >= b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif ((instr (31 downto 26) = "000111")and(instr (20 downto 16)="00000")) then -- BGTZ
internal_wb_flag <= '0';
b :=0;
report "The value of 'a' is " & integer'image(a);
if (a > b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif ((instr (31 downto 26) = "000110")and(instr (20 downto 16)="00000")) then -- BLEZ
internal_wb_flag <= '0';
b :=0;
if (a <= b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif ((instr (31 downto 26) = "000001")and(instr (20 downto 16)="00000")) then -- BLTZ
internal_wb_flag <= '0';
b :=0;
if (a < b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif ((instr (31 downto 26) = "000001")and(instr (20 downto 16)="10000")) then -- BLTZAL
internal_wb_flag <= '1';
internal_writeback <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4,32));
b :=0;
if (a < b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
elsif (instr (31 downto 26) = "000101") then -- BNE
internal_wb_flag <= '0';
if (a /= b) then
offset := to_integer(signed(instr(15 downto 0)));
offset := offset * 4;
offset := offset + to_integer (signed(ip_in));
ip_out <= std_logic_vector(to_signed(offset,32));
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
else
ip_out <= std_logic_vector(to_unsigned(to_integer(unsigned(ip_in)) + 4, 32));
end if;
end process;
imm_expand : process (instr) is
begin
imm <= std_logic_vector(to_signed(to_integer(signed (instr (15 downto 0))),32));
end process;
end architecture;
-- FSM-signal-Howto:
--
-- regdest_mux:
-- 00: if instruction is of R-type
-- 01: if regdest must be set to 31 (JAL?)
-- 10: if instruction is of I-type
-- 11: NEVER EVER EVER!!!
--
-- regshift_mux:
-- 00: if instruction is of R-type
-- 01: if shift must be 16 (No idea which instruction uses that...)
-- 10: if you like non-deterministic behaviour
-- 11: if you love non-deterministic behaviour
--
-- enable_regs:
-- 1: if the writeback-stage just finished an R-type- or I-type-instruction (except for JR)
-- 0: if the writeback-stage just finished a J-type-instruction or JR
|
library verilog;
use verilog.vl_types.all;
entity nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1 is
port(
clk : in vl_logic;
ce : in vl_logic;
a : in vl_logic_vector(7 downto 0);
b : in vl_logic_vector(5 downto 0);
p : out vl_logic_vector(13 downto 0)
);
end nfa_accept_samples_generic_hw_mul_8ns_6ns_14_2_MAC2S_1;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: ram_16x8k_dp_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 2
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 16
-- C_READ_WIDTH_A : 16
-- C_WRITE_DEPTH_A : 8192
-- C_READ_DEPTH_A : 8192
-- C_ADDRA_WIDTH : 13
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 2
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 16
-- C_READ_WIDTH_B : 16
-- C_WRITE_DEPTH_B : 8192
-- C_READ_DEPTH_B : 8192
-- C_ADDRB_WIDTH : 13
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY ram_16x8k_dp_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END ram_16x8k_dp_prod;
ARCHITECTURE xilinx OF ram_16x8k_dp_prod IS
COMPONENT ram_16x8k_dp_exdes IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : ram_16x8k_dp_exdes
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert bit'value("'0'") = '0'; -- Works
assert bit'value("'1'") = '1'; -- Works
assert bit'value("0") = '0'; -- Fails
assert bit'value("1") = '1'; -- Fails
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert bit'value("'0'") = '0'; -- Works
assert bit'value("'1'") = '1'; -- Works
assert bit'value("0") = '0'; -- Fails
assert bit'value("1") = '1'; -- Fails
wait;
end process;
end architecture;
|
entity ent is
end entity;
architecture a of ent is
begin
main : process
begin
assert bit'value("'0'") = '0'; -- Works
assert bit'value("'1'") = '1'; -- Works
assert bit'value("0") = '0'; -- Fails
assert bit'value("1") = '1'; -- Fails
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nxor00 is
port(
Anx: in std_logic ;
Bnx: in std_logic ;
Ynx: out std_logic );
end;
architecture nxor0 of nxor00 is
begin
Ynx <= NOT(Anx xor Bnx);
end nxor0;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_dgen.vhd
--
-- Description:
-- Used for write interface stimulus generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_dg_arch OF fg_tb_dgen IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
SIGNAL pr_w_en : STD_LOGIC := '0';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
SIGNAL wr_data_i : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
BEGIN
WR_EN <= PRC_WR_EN ;
WR_DATA <= wr_data_i AFTER 24 ns;
----------------------------------------------
-- Generation of DATA
----------------------------------------------
gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst1:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_w_en
);
END GENERATE;
pr_w_en <= PRC_WR_EN AND NOT FULL;
wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
END ARCHITECTURE;
|
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