content stringlengths 1 1.04M ⌀ |
|---|
library IEEE;
use IEEE.std_logic_1164.all;
--------------------------------------------------------------------------------
package lfsr_tb_components is
component pulse_tester is
generic (
G_lfsr_width : natural := 3;
G_period : natural := 7;
G_expected : time := 70 ns
);
port(
CLK : in std_logic;
RESET : in std_logic;
GO : in std_logic;
DONE : out std_logic;
PASS_nFAIL : out std_logic;
RUNTIME : out time
);
end component;
end lfsr_tb_components; |
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: McEliece_QD-Goppa_Decrypt
-- Module Name: McEliece_QD-Goppa_Decrypt
-- Project Name: McEliece Goppa Decryption
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- This circuit implements McEliece decryption algorithm for binary Goppa codes.
-- The circuit is divided into 3 phases : Syndrome computation, Solving Key Equation and
-- Finding Roots.
-- Each circuits waits for the next one to begin computation. All circuits share some
-- input and output memories, therefore is not possible to make a pipeline of this 3 phases.
-- First circuit, syndrome_calculator_n_pipe_v3, computes the syndrome from the ciphertext
-- and private keys, support L and polynomial g(x) (In this case g(L)^-1).
-- Second circuit, solving_key_equation_4, computes polynomial sigma through
-- the syndrome computed by first circuit.
-- Third circuit, find_and_correct_errors_n and polynomial_evaluator_n_v2, find the roots
-- of polynomial sigma and correct respective errors in the ciphertext and obtains
-- plaintext array.
-- Inversion circuit, inv_gf_2_m_pipeline, is only used during solving_key_equation_4.
-- This circuit was made outside of solving_key_equation_4 so it can be used by other circuits.
--
-- The circuits parameters
--
-- number_of_syndrome_and_find_units :
--
-- The number of pipelines in find_correct_errors_n, polynomial_evaluator_n_v2 and
-- syndrome_calculator_n_pipe_v3 circuits. The number of pipelines is shared between the root
-- finding process and syndrome computation. This happens because of how shared memories.
-- This number can be 1 or greater, however, tests for this unit were only made for 1 and 2.
--
-- syndrome_calculator_units :
--
-- The number of units inside of each syndrome pipeline computational unit.
-- This number can be 1 or greater.
--
-- find_correct_errors_pipeline_size :
--
-- This is the number of stages on the find_correct_errors_n and polynomial_evaluator_n_v2
-- circuits. This number can be 2 or greater.
--
-- find_correct_errors_size_pipeline_size :
--
-- The number of bits necessary to hold the number of stages on the pipeline.
-- This is ceil(log2(find_correct_errors_pipeline_size))
--
-- gf_2_m :
--
-- The size of the finite field extension used in this circuit.
-- This values depends of the Goppa code used.
--
-- length_codeword :
--
-- The length of the codeword in this Goppa code.
-- This values depends of the Goppa code used.
--
-- size_codeword :
--
-- The number of bits necessary to store an array of codeword lengths.
-- This is ceil(log2(length_codeword))
--
-- number_of_errors :
--
-- The number of errors the Goppa code is able to decode.
-- This values depends of the Goppa code used.
--
-- size_number_of_errors :
--
-- The number of bits necessary to store an array of number of errors + 1 length.
-- This is ceil(log2(number_of_errors+1))
--
--
-- Dependencies:
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- syndrome_calculator_n_pipe_v3 Rev 1.0
-- solving_key_equation_4 Rev 1.0
-- find_and_correct_errors_n Rev 1.0
-- polynomial_evaluator_n_v2 Rev 1.0
-- inv_gf_2_m_pipeline Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity mceliece_qd_goppa_decrypt is
Generic(
-- GOPPA [2048, 1751, 27, 11] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 27;
-- size_number_of_errors : integer := 5
-- GOPPA [2048, 1498, 50, 11] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 11;
-- length_codeword : integer := 2048;
-- size_codeword : integer := 11;
-- number_of_errors : integer := 50;
-- size_number_of_errors : integer := 6
-- GOPPA [3307, 2515, 66, 12] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 3307;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 66;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [2528, 2144, 32, 12] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2528;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 32;
-- size_number_of_errors : integer := 6
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_syndrome_and_find_units : integer := 2;
-- syndrome_calculator_units : integer := 1;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- number_of_errors : integer := 64;
-- size_number_of_errors : integer := 7
-- QD-GOPPA [3328, 2560, 64, 12] --
number_of_syndrome_and_find_units : integer := 2;
syndrome_calculator_units : integer := 2;
find_correct_errors_pipeline_size : integer := 17;
find_correct_errors_size_pipeline_size : integer := 5;
gf_2_m : integer range 1 to 20 := 12;
length_codeword : integer := 3328;
size_codeword : integer := 12;
number_of_errors : integer := 64;
size_number_of_errors : integer := 7
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_syndrome_and_find_units : integer := 1;
-- syndrome_calculator_units : integer := 2;
-- find_correct_errors_pipeline_size : integer := 2;
-- find_correct_errors_size_pipeline_size : integer := 2;
-- gf_2_m : integer range 1 to 20 := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- number_of_errors : integer := 128;
-- size_number_of_errors : integer := 8
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_sigma_evaluated : in STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
syndrome_generation_finalized : out STD_LOGIC;
key_equation_finalized : out STD_LOGIC;
decryption_finalized : out STD_LOGIC;
address_value_h : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_value_L : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_codeword : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_sigma : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_message : out STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
new_value_error : out STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
write_enable_new_value_syndrome : out STD_LOGIC;
write_enable_new_value_G : out STD_LOGIC;
write_enable_new_value_B : out STD_LOGIC;
write_enable_new_value_sigma : out STD_LOGIC;
write_enable_new_value_message : out STD_LOGIC;
write_enable_new_value_error : out STD_LOGIC;
write_enable_new_value_sigma_evaluated : out STD_LOGIC;
address_new_value_syndrome : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_sigma : out STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
address_new_value_message : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_new_value_error : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
address_new_value_sigma_evaluated : out STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0)
);
end mceliece_qd_goppa_decrypt;
architecture Behavioral of mceliece_qd_goppa_decrypt is
component syndrome_calculator_n_pipe_v3
Generic(
number_of_syndrome_calculators : integer;
syndrome_calculator_size : integer;
gf_2_m : integer range 1 to 20;
length_codeword : integer;
size_codeword : integer;
length_syndrome : integer;
size_syndrome : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
value_h : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_L : in STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(gf_2_m) - 1) downto 0);
value_syndrome : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_codeword : in STD_LOGIC_VECTOR((number_of_syndrome_calculators - 1) downto 0);
syndrome_finalized : out STD_LOGIC;
write_enable_new_syndrome : out STD_LOGIC;
new_value_syndrome : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_h : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_L : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_codeword : out STD_LOGIC_VECTOR(((number_of_syndrome_calculators)*(size_codeword) - 1) downto 0);
address_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0);
address_new_syndrome : out STD_LOGIC_VECTOR((size_syndrome - 1) downto 0)
);
end component;
component solving_key_equation_4
Generic(
gf_2_m : integer range 1 to 20;
final_degree : integer;
size_final_degree : integer
);
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
ready_inv : in STD_LOGIC;
value_F : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_G : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_B : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_C : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
value_inv : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal_inv : out STD_LOGIC;
key_equation_found : out STD_LOGIC;
write_enable_F : out STD_LOGIC;
write_enable_G : out STD_LOGIC;
write_enable_B : out STD_LOGIC;
write_enable_C : out STD_LOGIC;
new_value_inv : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_F : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_B : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_G : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
new_value_C : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
address_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_F : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_G : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_B : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0);
address_new_value_C : out STD_LOGIC_VECTOR((size_final_degree + 1) downto 0)
);
end component;
component find_correct_errors_n
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
gf_2_m : integer range 1 to 20;
length_support_elements: integer;
size_support_elements : integer
);
Port(
value_message : in STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_evaluated : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
address_value_evaluated : in STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
enable_correction : in STD_LOGIC;
evaluation_finalized : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
correction_finalized : out STD_LOGIC;
address_new_value_message : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
address_value_error : out STD_LOGIC_VECTOR((size_support_elements - 1) downto 0);
write_enable_new_value_message : out STD_LOGIC;
write_enable_value_error : out STD_LOGIC;
new_value_message : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0);
value_error : out STD_LOGIC_VECTOR((number_of_pipelines - 1) downto 0)
);
end component;
component inv_gf_2_m_pipeline
Generic(gf_2_m : integer range 1 to 20 := 13);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
flag : in STD_LOGIC;
clk : in STD_LOGIC;
oflag : out STD_LOGIC;
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
component polynomial_evaluator_n_v2
Generic (
number_of_pipelines : integer;
pipeline_size : integer;
size_pipeline_size : integer;
gf_2_m : integer range 1 to 20;
polynomial_degree : integer;
size_polynomial_degree : integer;
number_of_values_x: integer;
size_number_of_values_x : integer
);
Port(
value_x : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_acc : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0);
value_polynomial : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
last_evaluations : out STD_LOGIC;
evaluation_finalized : out STD_LOGIC;
address_value_polynomial : out STD_LOGIC_VECTOR((size_polynomial_degree - 1) downto 0);
address_value_x : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
address_new_value_acc : out STD_LOGIC_VECTOR((size_number_of_values_x - 1) downto 0);
write_enable_new_value_acc : out STD_LOGIC;
new_value_acc : out STD_LOGIC_VECTOR(((gf_2_m)*(number_of_pipelines) - 1) downto 0)
);
end component;
signal syndrome_calculator_rst : STD_LOGIC;
signal syndrome_calculator_value_h : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal syndrome_calculator_value_L : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal syndrome_calculator_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal syndrome_calculator_value_codeword : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal syndrome_calculator_syndrome_finalized : STD_LOGIC;
signal syndrome_calculator_write_enable_new_syndrome : STD_LOGIC;
signal syndrome_calculator_new_value_syndrome : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal syndrome_calculator_address_h : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal syndrome_calculator_address_L : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal syndrome_calculator_address_codeword : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal syndrome_calculator_address_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal syndrome_calculator_address_new_syndrome : STD_LOGIC_VECTOR((size_number_of_errors) downto 0);
signal solving_key_equation_rst : STD_LOGIC;
signal solving_key_equation_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_key_equation_found : STD_LOGIC;
signal solving_key_equation_write_enable_F : STD_LOGIC;
signal solving_key_equation_write_enable_G : STD_LOGIC;
signal solving_key_equation_write_enable_B : STD_LOGIC;
signal solving_key_equation_write_enable_C : STD_LOGIC;
signal solving_key_equation_new_value_F : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_B : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_G : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_new_value_C : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal solving_key_equation_address_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_F : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_G : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_B : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal solving_key_equation_address_new_value_C : STD_LOGIC_VECTOR((size_number_of_errors + 1) downto 0);
signal find_correct_errors_value_message : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal find_correct_errors_value_evaluated : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal find_correct_errors_address_value_evaluated : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal find_correct_errors_enable_correction : STD_LOGIC;
signal find_correct_errors_evaluation_finalized : STD_LOGIC;
signal find_correct_errors_correction_finalized : STD_LOGIC;
signal find_correct_errors_rst : STD_LOGIC;
signal find_correct_errors_address_new_value_message : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal find_correct_errors_address_new_value_message_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal find_correct_errors_address_value_error : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal find_correct_errors_address_value_error_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal find_correct_errors_write_enable_new_value_message : STD_LOGIC;
signal find_correct_errors_write_enable_value_error : STD_LOGIC;
signal find_correct_errors_new_value_message : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal find_correct_errors_value_error : STD_LOGIC_VECTOR((number_of_syndrome_and_find_units - 1) downto 0);
signal inv_a : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal inv_flag : STD_LOGIC;
signal inv_oflag : STD_LOGIC;
signal inv_o : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_value_x : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal polynomial_evaluator_value_acc : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
signal polynomial_evaluator_value_polynomial : STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
signal polynomial_evaluator_rst : STD_LOGIC;
signal polynomial_evaluator_last_evaluations : STD_LOGIC;
signal polynomial_evaluator_evaluation_finalized : STD_LOGIC;
signal polynomial_evaluator_address_value_polynomial : STD_LOGIC_VECTOR((size_number_of_errors - 1) downto 0);
signal polynomial_evaluator_address_value_x : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal polynomial_evaluator_address_value_x_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal polynomial_evaluator_address_value_acc : STD_LOGIC_VECTOR(((size_codeword) - 1) downto 0);
signal polynomial_evaluator_address_value_acc_complete : STD_LOGIC_VECTOR((((number_of_syndrome_and_find_units)*(size_codeword)) - 1) downto 0);
signal polynomial_evaluator_address_new_value_acc : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal polynomial_evaluator_address_new_value_acc_complete : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(size_codeword) - 1) downto 0);
signal polynomial_evaluator_write_enable_new_value_acc : STD_LOGIC;
signal polynomial_evaluator_new_value_acc : STD_LOGIC_VECTOR(((number_of_syndrome_and_find_units)*(gf_2_m) - 1) downto 0);
begin
syndrome_calculator : syndrome_calculator_n_pipe_v3
Generic Map(
number_of_syndrome_calculators => number_of_syndrome_and_find_units,
syndrome_calculator_size => syndrome_calculator_units,
gf_2_m => gf_2_m,
length_codeword => length_codeword,
size_codeword => size_codeword,
length_syndrome => 2*number_of_errors,
size_syndrome => size_number_of_errors + 1
)
Port Map(
clk => clk,
rst => syndrome_calculator_rst,
value_h => syndrome_calculator_value_h,
value_L => syndrome_calculator_value_L,
value_syndrome => syndrome_calculator_value_syndrome,
value_codeword => syndrome_calculator_value_codeword,
syndrome_finalized => syndrome_calculator_syndrome_finalized,
write_enable_new_syndrome => syndrome_calculator_write_enable_new_syndrome,
new_value_syndrome => syndrome_calculator_new_value_syndrome,
address_h => syndrome_calculator_address_h,
address_L => syndrome_calculator_address_L,
address_codeword => syndrome_calculator_address_codeword,
address_syndrome => syndrome_calculator_address_syndrome,
address_new_syndrome => syndrome_calculator_address_new_syndrome
);
solving_key_equation : solving_key_equation_4
Generic Map(
gf_2_m => gf_2_m,
final_degree => number_of_errors,
size_final_degree => size_number_of_errors
)
Port Map(
clk => clk,
rst => solving_key_equation_rst,
ready_inv => inv_oflag,
value_F => solving_key_equation_value_F,
value_G => solving_key_equation_value_G,
value_B => solving_key_equation_value_B,
value_C => solving_key_equation_value_C,
value_inv => inv_o,
signal_inv => inv_flag,
key_equation_found => solving_key_equation_key_equation_found,
write_enable_F => solving_key_equation_write_enable_F,
write_enable_G => solving_key_equation_write_enable_G,
write_enable_B => solving_key_equation_write_enable_B,
write_enable_C => solving_key_equation_write_enable_C,
new_value_inv => inv_a,
new_value_F => solving_key_equation_new_value_F,
new_value_B => solving_key_equation_new_value_B,
new_value_G => solving_key_equation_new_value_G,
new_value_C => solving_key_equation_new_value_C,
address_value_F => solving_key_equation_address_value_F,
address_value_G => solving_key_equation_address_value_G,
address_value_B => solving_key_equation_address_value_B,
address_value_C => solving_key_equation_address_value_C,
address_new_value_F => solving_key_equation_address_new_value_F,
address_new_value_G => solving_key_equation_address_new_value_G,
address_new_value_B => solving_key_equation_address_new_value_B,
address_new_value_C => solving_key_equation_address_new_value_C
);
find_correct_errors : find_correct_errors_n
Generic Map(
number_of_pipelines => number_of_syndrome_and_find_units,
pipeline_size => find_correct_errors_pipeline_size,
gf_2_m => gf_2_m,
length_support_elements => length_codeword,
size_support_elements => size_codeword
)
Port Map(
value_message => find_correct_errors_value_message,
value_evaluated => find_correct_errors_value_evaluated,
address_value_evaluated => find_correct_errors_address_value_evaluated,
enable_correction => find_correct_errors_enable_correction,
evaluation_finalized => find_correct_errors_evaluation_finalized,
clk => clk,
rst => find_correct_errors_rst,
correction_finalized => find_correct_errors_correction_finalized,
address_new_value_message => find_correct_errors_address_new_value_message,
address_value_error => find_correct_errors_address_value_error,
write_enable_new_value_message => find_correct_errors_write_enable_new_value_message,
write_enable_value_error => find_correct_errors_write_enable_value_error,
new_value_message => find_correct_errors_new_value_message,
value_error => find_correct_errors_value_error
);
inverter : inv_gf_2_m_pipeline
Generic Map(
gf_2_m => gf_2_m
)
Port Map(
a => inv_a,
flag => inv_flag,
clk => clk,
oflag => inv_oflag,
o => inv_o
);
polynomial_evaluator : polynomial_evaluator_n_v2
Generic Map(
number_of_pipelines => number_of_syndrome_and_find_units,
pipeline_size => find_correct_errors_pipeline_size,
size_pipeline_size => find_correct_errors_size_pipeline_size,
gf_2_m => gf_2_m,
polynomial_degree => number_of_errors,
size_polynomial_degree => size_number_of_errors,
number_of_values_x => length_codeword,
size_number_of_values_x => size_codeword
)
Port Map(
value_x => polynomial_evaluator_value_x,
value_acc => polynomial_evaluator_value_acc,
value_polynomial => polynomial_evaluator_value_polynomial,
clk => clk,
rst => polynomial_evaluator_rst,
last_evaluations => polynomial_evaluator_last_evaluations,
evaluation_finalized => polynomial_evaluator_evaluation_finalized,
address_value_polynomial => polynomial_evaluator_address_value_polynomial,
address_value_x => polynomial_evaluator_address_value_x,
address_value_acc => polynomial_evaluator_address_value_acc,
address_new_value_acc => polynomial_evaluator_address_new_value_acc,
write_enable_new_value_acc => polynomial_evaluator_write_enable_new_value_acc,
new_value_acc => polynomial_evaluator_new_value_acc
);
syndrome_calculator_rst <= rst;
syndrome_calculator_value_h <= value_h;
syndrome_calculator_value_L <= value_L;
syndrome_calculator_value_syndrome <= value_syndrome;
syndrome_calculator_value_codeword <= value_codeword;
solving_key_equation_rst <= not syndrome_calculator_syndrome_finalized;
solving_key_equation_value_F <= value_syndrome;
solving_key_equation_value_G <= value_G;
solving_key_equation_value_B <= value_B;
solving_key_equation_value_C <= value_sigma;
find_correct_errors_rst <= not solving_key_equation_key_equation_found;
find_correct_errors_value_message <= value_codeword;
find_correct_errors_value_evaluated <= polynomial_evaluator_new_value_acc;
find_correct_errors_address_value_evaluated <= polynomial_evaluator_address_new_value_acc;
find_correct_errors_enable_correction <= polynomial_evaluator_last_evaluations;
find_correct_errors_evaluation_finalized <= polynomial_evaluator_evaluation_finalized;
polynomial_evaluator_rst <= not solving_key_equation_key_equation_found;
polynomial_evaluator_value_x <= value_L;
polynomial_evaluator_value_acc <= value_sigma_evaluated;
polynomial_evaluator_value_polynomial <= value_sigma;
syndrome_generation_finalized <= syndrome_calculator_syndrome_finalized;
key_equation_finalized <= solving_key_equation_key_equation_found;
decryption_finalized <= syndrome_calculator_syndrome_finalized and solving_key_equation_key_equation_found and find_correct_errors_correction_finalized;
address_value_h <= syndrome_calculator_address_h;
address_value_L <= polynomial_evaluator_address_value_x_complete when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_address_h;
address_value_syndrome <= solving_key_equation_address_value_F when syndrome_calculator_syndrome_finalized = '1' else
"0" & syndrome_calculator_address_syndrome;
address_value_codeword <= polynomial_evaluator_address_value_x_complete when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_address_codeword;
address_value_G <= solving_key_equation_address_value_G;
address_value_B <= solving_key_equation_address_value_B;
address_value_sigma <= "00" & polynomial_evaluator_address_value_polynomial when solving_key_equation_key_equation_found = '1' else
solving_key_equation_address_value_C;
address_value_sigma_evaluated <= polynomial_evaluator_address_value_acc_complete;
new_value_syndrome <= solving_key_equation_new_value_F when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_new_value_syndrome;
new_value_G <= solving_key_equation_new_value_G;
new_value_B <= solving_key_equation_new_value_B;
new_value_sigma <= solving_key_equation_new_value_C;
new_value_message <= find_correct_errors_new_value_message;
new_value_error <= find_correct_errors_value_error;
new_value_sigma_evaluated <= polynomial_evaluator_new_value_acc;
write_enable_new_value_syndrome <= solving_key_equation_write_enable_F when syndrome_calculator_syndrome_finalized = '1' else
syndrome_calculator_write_enable_new_syndrome;
write_enable_new_value_G <= solving_key_equation_write_enable_G;
write_enable_new_value_B <= solving_key_equation_write_enable_B;
write_enable_new_value_sigma <= solving_key_equation_write_enable_C;
write_enable_new_value_message <= find_correct_errors_write_enable_new_value_message;
write_enable_new_value_error <= find_correct_errors_write_enable_value_error;
write_enable_new_value_sigma_evaluated <= polynomial_evaluator_write_enable_new_value_acc;
address_new_value_syndrome <= solving_key_equation_address_new_value_F when syndrome_calculator_syndrome_finalized = '1' else
"0" & syndrome_calculator_address_new_syndrome;
address_new_value_G <= solving_key_equation_address_new_value_G;
address_new_value_B <= solving_key_equation_address_new_value_B;
address_new_value_sigma <= solving_key_equation_address_new_value_C;
address_new_value_message <= find_correct_errors_address_new_value_message_complete;
address_new_value_error <= find_correct_errors_address_value_error_complete;
address_new_value_sigma_evaluated <= polynomial_evaluator_address_new_value_acc_complete;
resolve_address : for I in 0 to (number_of_syndrome_and_find_units - 1) generate
polynomial_evaluator_address_value_x_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(polynomial_evaluator_address_value_x) + to_unsigned(I, size_codeword));
polynomial_evaluator_address_value_acc_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(polynomial_evaluator_address_value_acc) + to_unsigned(I, size_codeword));
find_correct_errors_address_new_value_message_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(find_correct_errors_address_new_value_message) + to_unsigned(I, size_codeword));
find_correct_errors_address_value_error_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(find_correct_errors_address_value_error) + to_unsigned(I, size_codeword));
polynomial_evaluator_address_new_value_acc_complete(((I+1)*size_codeword - 1) downto (I*size_codeword)) <= std_logic_vector(unsigned(polynomial_evaluator_address_new_value_acc) + to_unsigned(I, size_codeword));
end generate;
end Behavioral;
|
--------------------------------------------------------------------------------
-- Author: Parham Alvani (parham.alvani@gmail.com)
--
-- Create Date: 25-04-2016
-- Module Name: p5_t.vhd
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity main_t is
end entity;
architecture behavioral of main_t is
component main
port (clk, load : in std_logic;
b : in std_logic_vector(7 downto 0);
serial : out std_logic);
end component;
for all:main use entity work.main;
signal clk, reset : std_logic := '0';
signal data : std_logic_vector(7 downto 0);
signal serial : std_logic;
begin
reset <= '1', '0' after 100 ns;
clk <= not clk after 50 ns;
data <= "10101010";
m : main port map (clk, reset, data, serial);
end architecture;
|
LIBRARY IEEE; -- These lines informs the compiler that the library IEEE is used
USE IEEE.std_logic_1164.all; -- contains the definition for the std_logic type plus some useful conversion functions
ENTITY tb_manchester_decode IS END tb_manchester_decode;
ARCHITECTURE test OF tb_manchester_decode IS
COMPONENT manchester_decode IS
PORT(input: IN STD_LOGIC;
output: OUT STD_LOGIC:='0');
END COMPONENT;
SIGNAL input: STD_LOGIC:='0';
SIGNAL output: STD_LOGIC;
BEGIN
T1: manchester_decode PORT MAP(input, output);
input<='0',
'1' AFTER 5 ns,
'0' AFTER 10 ns,
'1' AFTER 15 ns,
'1' AFTER 20 ns,
'0' AFTER 25 ns,
'1' AFTER 30 ns,
'0' AFTER 35 ns;
END test; |
package my_time_pkg is
type my_time is range -integer'low to integer'high units
fs;
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms = 1000 us;
sec = 1000 ms;
min = 60 sec;
hr = 60 min;
end units;
end package my_time_pkg;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for ios_e
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: ios_e-e.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: ios_e-e.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , wilfried.gaensheimer@micronas.com
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity ios_e
--
entity ios_e is
-- Generics:
-- No Generated Generics for Entity ios_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end ios_e;
--
-- End of Generated Entity ios_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
`protect begin_protected
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9tdzdCAdSA==
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
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tryOv/dE3EFUwO3dbmutrAmlOHeZ9lNAQOMnA4uZk/+1TOtTXhIPNWcymLs1YIGXaN5wp68xVOmY
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect end_protected
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY preesc_tb IS
END preesc_tb;
ARCHITECTURE behavior OF preesc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(31 downto 0);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0):="0000000000000000";
signal salida_uds : std_logic_vector(1 downto 0):="00";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Stimulus process
stim_proc: process
begin
entrada_frec<="00000000000000000100000100010000";
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY preesc_tb IS
END preesc_tb;
ARCHITECTURE behavior OF preesc_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT EscaladoPrePresentacion
PORT(
entrada_frec : IN std_logic_vector(31 downto 0);
salida_frec : OUT std_logic_vector(15 downto 0);
salida_uds : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal entrada_frec : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal salida_frec : std_logic_vector(15 downto 0):="0000000000000000";
signal salida_uds : std_logic_vector(1 downto 0):="00";
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: EscaladoPrePresentacion PORT MAP (
entrada_frec => entrada_frec,
salida_frec => salida_frec,
salida_uds => salida_uds
);
-- Stimulus process
stim_proc: process
begin
entrada_frec<="00000000000000000100000100010000";
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
------------------------------
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity circuit is
--generic declarations
port (
a: in std_logic;
b: in std_logic;
c: in std_logic;
z: out std_logic);
end entity;
------------------------------
architecture circuit of circuit is
--signal x: std_logic;
--signal y: std_logic;
begin
z <= a xor ((a nand b) or c);
end architecture;
------------------------------
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver modulefor serdes factors
-- from 2 to 8
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line,
-- and perform bitslip if required.
-- Takes in 1 bit of differential data and deserialises this to
-- n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_1_to_n_clk_pll_s2_diff is
generic (
PLLD : integer := 1; -- Parameter to set division for PLL
PLLX : integer := 2; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 5.000; -- clock period (ns) of input clock on clkin_p
S : integer := 2; -- Parameter to set the serdes factor 1..8
BS : boolean := false; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic; -- Input from LVDS receiver pin
clkin_n : in std_logic; -- Input from LVDS receiver pin
reset : in std_logic; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0); -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0); -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic; -- IO Clock network
rx_serdesstrobe : out std_logic; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic; -- Global clock
rx_pll_lckd : out std_logic; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0); -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s2_diff;
architecture arch_serdes_1_to_n_clk_pll_s2_diff of serdes_1_to_n_clk_pll_s2_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0); --
signal cascade : std_logic; --
signal pd_edge : std_logic; --
signal busys : std_logic; --
signal busym : std_logic; --
signal rx_clk_in : std_logic; --
signal feedback : std_logic; --
signal buf_P_clk : std_logic; --
signal iob_data_in : std_logic; --
signal rx_bufg_pll_x1_int : std_logic;
signal rxioclk_int : std_logic;
signal rx_serdesstrobe_int : std_logic;
signal rx_pllout_xs_int : std_logic;
signal rx_pllout_x1 : std_logic;
signal rx_pll_lckd_int : std_logic;
signal state : integer range 0 to 9;
signal bslip : std_logic;
signal count : std_logic_vector(2 downto 0);
signal busyd : std_logic;
signal counter : std_logic_vector(11 downto 0);
signal clk_iserdes_data : std_logic_vector(S-1 downto 0);
signal cal_clk : std_logic;
signal rst_clk : std_logic;
signal rx_bufplllckd : std_logic;
signal not_rx_bufpll_lckd : std_logic;
signal busy_clk : std_logic;
signal enable : std_logic;
constant RX_SWAP_CLK : std_logic := '0'; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int;
rxioclk <= rxioclk_int;
rx_serdesstrobe <= rx_serdesstrobe_int;
rx_pllout_xs <= rx_pllout_xs_int;
rx_pll_lckd <= rx_pll_lckd_int;
bitslip <= bslip;
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK; -- Invert clock as required
busy_clk <= busym;
datain <= clk_iserdes_data;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0;
enable <= '0';
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk;
if counter(5) = '1' then
enable <= '1';
end if;
if counter(11) = '1' then
state <= 0;
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
else
counter <= counter + 1;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1;
elsif state = 1 then -- cal high
cal_clk <= '1'; state <= 2;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0'; state <= 3; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1'; state <= 4; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0'; state <= 5;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6;
count <= "000";
elsif state = 6 then -- hang around
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 7 then
if BS = true and clk_iserdes_data /= pattern1 and clk_iserdes_data /= pattern2 then
bslip <= '1'; -- bitslip needed
state <= 8;
count <= "000";
else
state <= 9;
end if;
elsif state = 8 then
bslip <= '0'; -- bitslip low
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 9 then -- repeat after a delay
state <= 9;
end if;
end if;
end if;
end process;
loop0 : for i in 0 to (S - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data(i) <= mdataout(8+i-S);
end generate;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x1_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 90.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
-- COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs_int, -- x7 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- one of six general clock output signals
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd_int, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_135 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int);
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs_int, -- PLL Clock input
GCLK => rx_bufg_pll_x1_int, -- Global Clock input
LOCKED => rx_pll_lckd_int, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd_int and rx_bufplllckd;
not_rx_bufpll_lckd <= not (rx_pll_lckd_int and rx_bufplllckd);
end arch_serdes_1_to_n_clk_pll_s2_diff;
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_clk_pll_s2_diff.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: 1-bit generic 1:n clock receiver modulefor serdes factors
-- from 2 to 8
-- Instantiates necessary clock buffers and PLL
-- Contains state machine to calibrate clock input delay line,
-- and perform bitslip if required.
-- Takes in 1 bit of differential data and deserialises this to
-- n bits for where this data is required
-- data is received LSB first
-- 0, 1, 2 ......
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
library unisim;
use unisim.vcomponents.all;
entity serdes_1_to_n_clk_pll_s2_diff is
generic (
PLLD : integer := 1; -- Parameter to set division for PLL
PLLX : integer := 2; -- Parameter to set multiplier for PLL (7 for video links, 2 for DDR etc)
CLKIN_PERIOD : real := 5.000; -- clock period (ns) of input clock on clkin_p
S : integer := 2; -- Parameter to set the serdes factor 1..8
BS : boolean := false; -- Parameter to enable bitslip TRUE or FALSE
DIFF_TERM : boolean := false) ; -- Enable or disable internal differential termination
port (
clkin_p : in std_logic; -- Input from LVDS receiver pin
clkin_n : in std_logic; -- Input from LVDS receiver pin
reset : in std_logic; -- Reset line
pattern1 : in std_logic_vector(S-1 downto 0); -- Data to define pattern that bitslip should search for
pattern2 : in std_logic_vector(S-1 downto 0); -- Data to define alternate pattern that bitslip should search for
rxioclk : out std_logic; -- IO Clock network
rx_serdesstrobe : out std_logic; -- Parallel data capture strobe
rx_bufg_pll_x1 : out std_logic; -- Global clock
rx_pll_lckd : out std_logic; -- PLL locked - only used if a 2nd BUFPLL is required
rx_pllout_xs : out std_logic; -- Multiplied PLL clock - only used if a 2nd BUFPLL is required
bitslip : out std_logic; -- Bitslip control line
datain : out std_logic_vector(S-1 downto 0); -- Output data
rx_bufpll_lckd : out std_logic); -- BUFPLL locked
end serdes_1_to_n_clk_pll_s2_diff;
architecture arch_serdes_1_to_n_clk_pll_s2_diff of serdes_1_to_n_clk_pll_s2_diff is
signal P_clk : std_logic; -- P clock out to BUFIO2
signal buf_pll_fb_clk : std_logic; -- PLL feedback clock into BUFIOFB
signal ddly_m : std_logic; -- Master output from IODELAY1
signal ddly_s : std_logic; -- Slave output from IODELAY1
signal mdataout : std_logic_vector(7 downto 0); --
signal cascade : std_logic; --
signal pd_edge : std_logic; --
signal busys : std_logic; --
signal busym : std_logic; --
signal rx_clk_in : std_logic; --
signal feedback : std_logic; --
signal buf_P_clk : std_logic; --
signal iob_data_in : std_logic; --
signal rx_bufg_pll_x1_int : std_logic;
signal rxioclk_int : std_logic;
signal rx_serdesstrobe_int : std_logic;
signal rx_pllout_xs_int : std_logic;
signal rx_pllout_x1 : std_logic;
signal rx_pll_lckd_int : std_logic;
signal state : integer range 0 to 9;
signal bslip : std_logic;
signal count : std_logic_vector(2 downto 0);
signal busyd : std_logic;
signal counter : std_logic_vector(11 downto 0);
signal clk_iserdes_data : std_logic_vector(S-1 downto 0);
signal cal_clk : std_logic;
signal rst_clk : std_logic;
signal rx_bufplllckd : std_logic;
signal not_rx_bufpll_lckd : std_logic;
signal busy_clk : std_logic;
signal enable : std_logic;
constant RX_SWAP_CLK : std_logic := '0'; -- pinswap mask for input clock (0 = no swap (default), 1 = swap). Allows input to be connected the wrong way round to ease PCB routing.
begin
rx_bufg_pll_x1 <= rx_bufg_pll_x1_int;
rxioclk <= rxioclk_int;
rx_serdesstrobe <= rx_serdesstrobe_int;
rx_pllout_xs <= rx_pllout_xs_int;
rx_pll_lckd <= rx_pll_lckd_int;
bitslip <= bslip;
iob_clk_in : IBUFDS generic map(
DIFF_TERM => DIFF_TERM)
port map (
I => clkin_p,
IB => clkin_n,
O => rx_clk_in);
iob_data_in <= rx_clk_in xor RX_SWAP_CLK; -- Invert clock as required
busy_clk <= busym;
datain <= clk_iserdes_data;
-- Bitslip and CAL state machine
process (rx_bufg_pll_x1_int, not_rx_bufpll_lckd)
begin
if not_rx_bufpll_lckd = '1' then
state <= 0;
enable <= '0';
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
elsif rx_bufg_pll_x1_int'event and rx_bufg_pll_x1_int = '1' then
busyd <= busy_clk;
if counter(5) = '1' then
enable <= '1';
end if;
if counter(11) = '1' then
state <= 0;
cal_clk <= '0';
rst_clk <= '0';
bslip <= '0';
busyd <= '1';
counter <= "000000000000";
else
counter <= counter + 1;
if state = 0 and enable = '1' and busyd = '0' then
state <= 1;
elsif state = 1 then -- cal high
cal_clk <= '1'; state <= 2;
elsif state = 2 and busyd = '1' then -- wait for busy high
cal_clk <= '0'; state <= 3; -- cal low
elsif state = 3 and busyd = '0' then -- wait for busy low
rst_clk <= '1'; state <= 4; -- rst high
elsif state = 4 then -- rst low
rst_clk <= '0'; state <= 5;
elsif state = 5 and busyd = '0' then -- wait for busy low
state <= 6;
count <= "000";
elsif state = 6 then -- hang around
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 7 then
if BS = true and clk_iserdes_data /= pattern1 and clk_iserdes_data /= pattern2 then
bslip <= '1'; -- bitslip needed
state <= 8;
count <= "000";
else
state <= 9;
end if;
elsif state = 8 then
bslip <= '0'; -- bitslip low
count <= count + 1;
if count = "111" then
state <= 7;
end if;
elsif state = 9 then -- repeat after a delay
state <= 9;
end if;
end if;
end if;
end process;
loop0 : for i in 0 to (S - 1) generate -- Limit the output data bus to the most significant 'S' number of bits
clk_iserdes_data(i) <= mdataout(8+i-S);
end generate;
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "VARIABLE_FROM_HALF_MAX", -- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from master IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk_int, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => rx_bufg_pll_x1_int, -- Fabric clock (GCLK) for control signals
CAL => cal_clk, -- Calibrate enable signal
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => rst_clk, -- Reset delay line to 1/2 max in this case
BUSY => busym) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
SIM_TAPDELAY_VALUE => 50, -- nominal tap delay (sim parameter only)
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- "NORMAL", "PCI"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
IDELAY_TYPE => "FIXED", -- <DEFAULT>, FIXED, VARIABLE
COUNTER_WRAPAROUND => "STAY_AT_LIMIT", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN") -- "IO", "IDATAIN", "ODATAIN"
port map (
IDATAIN => iob_data_in, -- data from slave IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s, -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => '0', -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => '0', -- Fabric clock (GCLK) for control signals
CAL => '0', -- Calibrate control signal, never needed as the slave supplies the clock input to the PLL
INC => '0', -- Increment counter
CE => '0', -- Clock Enable
RST => '0', -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
P_clk_bufio2_inst : BUFIO2 generic map(
DIVIDE => 1, -- The DIVCLK divider divide-by value; default 1
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => P_clk, -- P_clk input from IDELAY
IOCLK => open, -- Output Clock
DIVCLK => buf_P_clk, -- Output Divided Clock
SERDESSTROBE => open) ; -- Output SERDES strobe (Clock Enable)
P_clk_bufio2fb_inst : BUFIO2FB generic map(
DIVIDE_BYPASS => true) -- DIVCLK output sourced from Divider (FALSE) or from I input, by-passing Divider (TRUE); default TRUE
port map (
I => feedback, -- PLL generated Clock
O => buf_pll_fb_clk) ; -- PLL Output Feedback Clock
iserdes_m : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting in BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => pd_edge,
BITSLIP => bslip,
FABRICOUT => open,
DFB => open,
CFB0 => open,
CFB1 => open,
Q4 => mdataout(7),
Q3 => mdataout(6),
Q2 => mdataout(5),
Q1 => mdataout(4),
VALID => open,
INCDEC => open,
SHIFTOUT => cascade);
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => true, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s,
CE0 => '1',
CLK0 => rxioclk_int,
CLK1 => '0',
IOCE => rx_serdesstrobe_int,
RST => reset,
CLKDIV => rx_bufg_pll_x1_int,
SHIFTIN => cascade,
BITSLIP => bslip,
FABRICOUT => open,
DFB => P_clk,
CFB0 => feedback,
CFB1 => open,
Q4 => mdataout(3),
Q3 => mdataout(2),
Q2 => mdataout(1),
Q1 => mdataout(0),
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge);
rx_pll_adv_inst : PLL_ADV generic map(
BANDWIDTH => "OPTIMIZED", -- "high", "low" or "optimized"
CLKFBOUT_MULT => PLLX, -- multiplication factor for all output clocks
CLKFBOUT_PHASE => 0.0, -- phase shift (degrees) of all output clocks
CLKIN1_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin1
CLKIN2_PERIOD => CLKIN_PERIOD, -- clock period (ns) of input clock on clkin2
CLKOUT0_DIVIDE => 1, -- division factor for clkout0 (1 to 128)
CLKOUT0_DUTY_CYCLE => 0.5, -- duty cycle for clkout0 (0.01 to 0.99)
CLKOUT0_PHASE => 0.0, -- phase shift (degrees) for clkout0 (0.0 to 360.0)
CLKOUT1_DIVIDE => 1, -- division factor for clkout1 (1 to 128)
CLKOUT1_DUTY_CYCLE => 0.5, -- duty cycle for clkout1 (0.01 to 0.99)
CLKOUT1_PHASE => 0.0, -- phase shift (degrees) for clkout1 (0.0 to 360.0)
CLKOUT2_DIVIDE => S, -- division factor for clkout2 (1 to 128)
CLKOUT2_DUTY_CYCLE => 0.5, -- duty cycle for clkout2 (0.01 to 0.99)
CLKOUT2_PHASE => 90.0, -- phase shift (degrees) for clkout2 (0.0 to 360.0)
CLKOUT3_DIVIDE => 7, -- division factor for clkout3 (1 to 128)
CLKOUT3_DUTY_CYCLE => 0.5, -- duty cycle for clkout3 (0.01 to 0.99)
CLKOUT3_PHASE => 0.0, -- phase shift (degrees) for clkout3 (0.0 to 360.0)
CLKOUT4_DIVIDE => 7, -- division factor for clkout4 (1 to 128)
CLKOUT4_DUTY_CYCLE => 0.5, -- duty cycle for clkout4 (0.01 to 0.99)
CLKOUT4_PHASE => 0.0, -- phase shift (degrees) for clkout4 (0.0 to 360.0)
CLKOUT5_DIVIDE => 7, -- division factor for clkout5 (1 to 128)
CLKOUT5_DUTY_CYCLE => 0.5, -- duty cycle for clkout5 (0.01 to 0.99)
CLKOUT5_PHASE => 0.0, -- phase shift (degrees) for clkout5 (0.0 to 360.0)
-- COMPENSATION => "SOURCE_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "INTERNAL", "EXTERNAL", "DCM2PLL", "PLL2DCM"
DIVCLK_DIVIDE => PLLD, -- division factor for all clocks (1 to 52)
CLK_FEEDBACK => "CLKOUT0",
REF_JITTER => 0.100) -- input reference jitter (0.000 to 0.999 ui%)
port map (
CLKFBDCM => open, -- output feedback signal used when pll feeds a dcm
CLKFBOUT => open, -- general output feedback signal
CLKOUT0 => rx_pllout_xs_int, -- x7 clock for transmitter
CLKOUT1 => open,
CLKOUT2 => rx_pllout_x1, -- x1 clock for BUFG
CLKOUT3 => open, -- one of six general clock output signals
CLKOUT4 => open, -- one of six general clock output signals
CLKOUT5 => open, -- one of six general clock output signals
CLKOUTDCM0 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM1 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM2 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM3 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM4 => open, -- one of six clock outputs to connect to the dcm
CLKOUTDCM5 => open, -- one of six clock outputs to connect to the dcm
DO => open, -- dynamic reconfig data output (16-bits)
DRDY => open, -- dynamic reconfig ready output
LOCKED => rx_pll_lckd_int, -- active high pll lock signal
CLKFBIN => buf_pll_fb_clk, -- clock feedback input
CLKIN1 => buf_P_clk, -- primary clock input
CLKIN2 => '0', -- secondary clock input
CLKINSEL => '1', -- selects '1' = clkin1, '0' = clkin2
DADDR => "00000", -- dynamic reconfig address input (5-bits)
DCLK => '0', -- dynamic reconfig clock input
DEN => '0', -- dynamic reconfig enable input
DI => "0000000000000000", -- dynamic reconfig data input (16-bits)
DWE => '0', -- dynamic reconfig write enable input
RST => reset, -- asynchronous pll reset
REL => '0') ; -- used to force the state of the PFD outputs (test only)
bufg_135 : BUFG port map (I => rx_pllout_x1, O => rx_bufg_pll_x1_int);
rx_bufpll_inst : BUFPLL generic map(
DIVIDE => S) -- PLLIN0 divide-by value to produce rx_serdesstrobe (1 to 8); default 1
port map (
PLLIN => rx_pllout_xs_int, -- PLL Clock input
GCLK => rx_bufg_pll_x1_int, -- Global Clock input
LOCKED => rx_pll_lckd_int, -- Clock0 locked input
IOCLK => rxioclk_int, -- Output PLL Clock
LOCK => rx_bufplllckd, -- BUFPLL Clock and strobe locked
serdesstrobe => rx_serdesstrobe_int) ; -- Output SERDES strobe
rx_bufpll_lckd <= rx_pll_lckd_int and rx_bufplllckd;
not_rx_bufpll_lckd <= not (rx_pll_lckd_int and rx_bufplllckd);
end arch_serdes_1_to_n_clk_pll_s2_diff;
|
----------------------------------------------------------------------------------
-- Company: CPE 233
-- Engineer: Jacob Hladky and Curtis Jonaitis
---------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity register_file is
Port( FROM_IN_PORT : in STD_LOGIC_VECTOR(7 downto 0);
FROM_TRI_STATE : in STD_LOGIC_VECTOR(7 downto 0);
FROM_ALU : in STD_LOGIC_VECTOR(7 downto 0);
RF_MUX_SEL : in STD_LOGIC_VECTOR(1 downto 0);
ADRX, ADRY : in STD_LOGIC_VECTOR(4 downto 0);
WE, CLK, DX_OE : in STD_LOGIC;
DX_OUT, DY_OUT : out STD_LOGIC_VECTOR(7 downto 0));
end register_file;
architecture register_file_a of register_file is
TYPE memory is array (0 to 31) of std_logic_vector(7 downto 0);
SIGNAL REG: memory := (others=>(others=>'0'));
SIGNAL D_IN : STD_LOGIC_VECTOR(7 downto 0);
begin
with RF_MUX_SEL select
D_IN <= FROM_IN_PORT when "00",
FROM_TRI_STATE when "01",
FROM_ALU when "10",
(others => 'X') when others;
process(clk, we, d_in) begin
if (rising_edge(clk)) then
if (WE = '1') then
REG(conv_integer(ADRX)) <= D_IN;
end if;
end if;
end process;
DX_OUT <= REG(conv_integer(ADRX)) when DX_OE='1' else (others=>'Z');
DY_OUT <= REG(conv_integer(ADRY));
end register_file_a;
|
-- Testbench generated by script.
-- Date: Seg,18/11/2013-19:27:07
-- Author: rogerio
-- Comments: Test of unidade_a0 entity..
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
-- print messages.
use std.textio.all;
use ieee.std_logic_textio.all;
entity unidade_a0_tb is
end unidade_a0_tb;
architecture estrutural of unidade_a0_tb is
-- Component declaration.
component unidade_a0
port (a, b, c, d: in std_logic; f: out std_logic);
end component;
-- Specifies the entity which is linked with the component. (Especifica qual a entidade está vinculada com o componente).
for unidade_a0_0: unidade_a0 use entity work.unidade_a0;
signal s_t_a, s_t_b, s_t_c, s_t_d, s_t_f: std_logic;
-- procedure print messages definition.
procedure print_message( pi_s_t_a, pi_s_t_b, pi_s_t_c, pi_s_t_d: std_logic; po_s_t_f: std_logic; pe_f: std_logic) is
variable line_out: line;
begin
write(line_out, string'(" At time "));
write(line_out, now);
write(line_out, string'(", inputs ["));
write(line_out, string'(" s_t_a: "));
write(line_out, pi_s_t_a);
write(line_out, string'(" s_t_b: "));
write(line_out, pi_s_t_b);
write(line_out, string'(" s_t_c: "));
write(line_out, pi_s_t_c);
write(line_out, string'(" s_t_d: "));
write(line_out, pi_s_t_d);
write(line_out, string'("]"));
write(line_out, string'(", outputs ["));
write(line_out, string'(" s_t_f: "));
write(line_out, string'("(generated: "));
write(line_out, po_s_t_f);
write(line_out, string'(", expected: "));
write(line_out, pe_f);
write(line_out, string'(")"));
write(line_out, string'("]"));
if (s_t_f = pe_f) then
write(line_out, string'(" [OK]"));
else
write(line_out, string'(" [Error]"));
end if;
writeline(output, line_out);
end procedure print_message;
begin
-- Component instantiation.
-- port map (<<p_in_1>> => <<s_t_in_1>>)
unidade_a0_0: unidade_a0 port map ( a=>s_t_a, b=>s_t_b, c=>s_t_c, d=>s_t_d, f=>s_t_f);
-- Process that works.
process
-- line to print.
variable line_out: line;
-- A record is created with the inputs and outputs of the entity.
-- (<<entrada1>>, <<entradaN>>, <<saida1>>, <<saidaN>>)
type pattern_type is record
-- inputs.
vi_a, vi_b, vi_c, vi_d: std_logic;
-- outputs.
vo_f: std_logic;
end record;
-- The input patterns are applied (injected) to the inputs of the entity under test.
type pattern_array is array (natural range <>) of pattern_type;
-- Test cases.
constant patterns : pattern_array :=
(
('0','0','0','0','0'),
('0','0','0','1','0'),
('0','0','1','0','0'),
('0','0','1','1','1'),
('0','1','0','0','0'),
('0','1','0','1','0'),
('0','1','1','0','0'),
('0','1','1','1','1'),
('1','0','0','0','0'),
('1','0','0','1','0'),
('1','0','1','0','0'),
('1','0','1','1','1'),
('1','1','0','0','1'),
('1','1','0','1','1'),
('1','1','1','0','1'),
('1','1','1','1','1')
);
begin
-- Message starting...
write(line_out, string'("Running testbench: unidade_a0_tb."));
writeline(output, line_out);
write(line_out, string'(" Testing entity: unidade_a0."));
writeline(output, line_out);
-- Injects the inputs and check thte outputs.
for i in patterns'range loop
-- Injects the inputs.
s_t_a <= patterns(i).vi_a;
s_t_b <= patterns(i).vi_b;
s_t_c <= patterns(i).vi_c;
s_t_d <= patterns(i).vi_d;
-- wait for results.
wait for 1 ns;
-- Checks the result with the expected output in the pattern.
print_message( s_t_a, s_t_b, s_t_c, s_t_d, s_t_f, patterns(i).vo_f);
assert (s_t_f = patterns(i).vo_f) report "Valor de s_t_f não confere com o resultado esperado." severity error;
end loop;
write(line_out, string'("Execution of unidade_a0_tb finished."));
writeline(output, line_out);
assert false report "End of test." severity note;
-- Wait forever; Isto finaliza a simulação.
wait;
end process;
end estrutural;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon May 08 23:35:07 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/ZyboIP/examples/zed_vga_test/zed_vga_test.srcs/sources_1/bd/system/ip/system_vga_sync_0_0/system_vga_sync_0_0_stub.vhdl
-- Design : system_vga_sync_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_vga_sync_0_0 is
Port (
clk : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end system_vga_sync_0_0;
architecture stub of system_vga_sync_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,rst,active,hsync,vsync,xaddr[9:0],yaddr[9:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "vga_sync,Vivado 2016.4";
begin
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc708.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00708ent IS
END c03s04b01x00p23n01i00708ent;
ARCHITECTURE c03s04b01x00p23n01i00708arch OF c03s04b01x00p23n01i00708ent IS
-- Some constants...
constant StringLength: INTEGER := 16;
constant NumOfStrings: INTEGER := 5;
-- Types...;
subtype STR16 is STRING (1 to StringLength);
type t1 is record
number: NATURAL;
string: STR16;
end record;
type string_table is array (1 to NumOfStrings) of STR16;
-- Objects...
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft1 is file of t1;
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : ft1 open write_mode is "iofile.59";
-- Declare a variable.
variable VAR : t1;
BEGIN
-- Write out the file.
for I in 1 to NumOfStrings loop
VAR.number := i;
VAR.string := string_array(i);
write(FILEV, VAR);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00708 - The output file will tested by test file s010440.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00708arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc708.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00708ent IS
END c03s04b01x00p23n01i00708ent;
ARCHITECTURE c03s04b01x00p23n01i00708arch OF c03s04b01x00p23n01i00708ent IS
-- Some constants...
constant StringLength: INTEGER := 16;
constant NumOfStrings: INTEGER := 5;
-- Types...;
subtype STR16 is STRING (1 to StringLength);
type t1 is record
number: NATURAL;
string: STR16;
end record;
type string_table is array (1 to NumOfStrings) of STR16;
-- Objects...
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft1 is file of t1;
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : ft1 open write_mode is "iofile.59";
-- Declare a variable.
variable VAR : t1;
BEGIN
-- Write out the file.
for I in 1 to NumOfStrings loop
VAR.number := i;
VAR.string := string_array(i);
write(FILEV, VAR);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00708 - The output file will tested by test file s010440.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00708arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc708.vhd,v 1.3 2001-10-29 02:12:46 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:38:08 1996 --
-- **************************** --
ENTITY c03s04b01x00p23n01i00708ent IS
END c03s04b01x00p23n01i00708ent;
ARCHITECTURE c03s04b01x00p23n01i00708arch OF c03s04b01x00p23n01i00708ent IS
-- Some constants...
constant StringLength: INTEGER := 16;
constant NumOfStrings: INTEGER := 5;
-- Types...;
subtype STR16 is STRING (1 to StringLength);
type t1 is record
number: NATURAL;
string: STR16;
end record;
type string_table is array (1 to NumOfStrings) of STR16;
-- Objects...
constant string_array: string_table :=
( "This is string 1"
,"__Hello World__"
,"This is string " & "3"
,"_Bird is a word_"
,"_Goodbye (ciao)_"
);
type ft1 is file of t1;
BEGIN
TESTING: PROCESS
-- Declare the actual file to write.
file FILEV : ft1 open write_mode is "iofile.59";
-- Declare a variable.
variable VAR : t1;
BEGIN
-- Write out the file.
for I in 1 to NumOfStrings loop
VAR.number := i;
VAR.string := string_array(i);
write(FILEV, VAR);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p23n01i00708 - The output file will tested by test file s010440.vhd"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p23n01i00708arch;
|
-- ####################################
-- # Project: Yarr
-- # Author: Timon Heim
-- # E-Mail: timon.heim at cern.ch
-- # Comments: Bridge between Rx core and Mem
-- ####################################
-- # Address Map:
-- # 0x0000: Start Adr (RO)
-- # 0x0001: Data Cnt (RO)
-- # 0x0002[0]: Loopback (RW)
-- # 0x0003: Data Rate (RO)
-- # 0x0004: Loop Fifo (WO)
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wb_rx_bridge is
port (
-- Sys Connect
sys_clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone slave interface
wb_adr_i : in std_logic_vector(31 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Wishbone DMA Master Interface
dma_clk_i : in std_logic;
dma_adr_o : out std_logic_vector(31 downto 0);
dma_dat_o : out std_logic_vector(63 downto 0);
dma_dat_i : in std_logic_vector(63 downto 0);
dma_cyc_o : out std_logic;
dma_stb_o : out std_logic;
dma_we_o : out std_logic;
dma_ack_i : in std_logic;
dma_stall_i : in std_logic;
-- Rx Interface
rx_data_i : in std_logic_vector(63 downto 0);
rx_valid_i : in std_logic;
-- Status In
trig_pulse_i : in std_logic;
-- Status out
irq_o : out std_logic;
busy_o : out std_logic
);
end wb_rx_bridge;
architecture Behavioral of wb_rx_bridge is
-- Cmoponents
COMPONENT rx_bridge_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
prog_empty_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
prog_full_thresh : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
prog_full : OUT STD_LOGIC;
prog_empty : OUT STD_LOGIC
);
END COMPONENT;
COMPONENT rx_bridge_ctrl_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC
);
END COMPONENT;
-- Constants
constant c_ALMOST_FULL_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(240, 8);
constant c_PACKAGE_SIZE : unsigned(31 downto 0) := TO_UNSIGNED((1680*30), 32); -- ~200kByte, magic number (!!) divisible my any channel number of to 8
constant c_TIMEOUT : unsigned(31 downto 0) := TO_UNSIGNED(2**14, 32); -- Counts in 5ns = 0.1ms
constant c_TIME_FRAME : unsigned(31 downto 0) := TO_UNSIGNED(200000000-1, 32); -- 200MHz clock cycles in 1 sec
constant c_EMPTY_THRESHOLD : unsigned(7 downto 0) := TO_UNSIGNED(16, 8);
constant c_EMPTY_TIMEOUT : unsigned(9 downto 0) := TO_UNSIGNED(2000, 10);
-- Signals
signal data_fifo_din : std_logic_vector(63 downto 0);
signal data_fifo_dout : std_logic_vector(63 downto 0);
signal data_fifo_wren : std_logic;
signal data_fifo_rden : std_logic;
signal data_fifo_full : std_logic;
signal data_fifo_empty : std_logic;
signal data_fifo_almost_full : std_logic;
signal data_fifo_prog_empty : std_logic;
signal data_fifo_empty_cnt : unsigned(10 downto 0);
signal data_fifo_empty_true : std_logic;
signal data_fifo_empty_pressure : std_logic;
signal ctrl_fifo_din : std_logic_vector(63 downto 0);
signal ctrl_fifo_dout : std_logic_vector(63 downto 0);
signal ctrl_fifo_wren : std_logic;
signal ctrl_fifo_rden : std_logic;
signal ctrl_fifo_full : std_logic;
signal ctrl_fifo_empty : std_logic;
signal dma_stb_t : std_logic;
signal dma_stb_valid : std_logic;
signal dma_adr_cnt : unsigned(31 downto 0);
signal dma_start_adr : unsigned(31 downto 0);
signal dma_data_cnt : unsigned(31 downto 0);
signal dma_data_cnt_d : unsigned(31 downto 0);
signal dma_timeout_cnt : unsigned(31 downto 0);
signal dma_ack_cnt : unsigned(7 downto 0);
signal rx_data_local : std_logic_vector(31 downto 0);
signal rx_valid_local : std_logic;
signal rx_data_local_d : std_logic_vector(31 downto 0);
signal rx_valid_local_d : std_logic;
signal ctrl_fifo_dout_tmp : std_logic_vector(31 downto 0);
signal time_cnt : unsigned(31 downto 0);
signal time_pulse : std_logic;
signal data_rate_cnt : unsigned(31 downto 0);
signal trig_cnt : unsigned(31 downto 0);
signal trig_pulse_d0 : std_logic;
signal trig_pulse_d1 : std_logic;
signal trig_pulse_pos : std_logic;
-- Registers
signal loopback : std_logic;
signal data_rate : std_logic_vector(31 downto 0);
begin
--Tie offs
irq_o <= '0';
busy_o <= data_fifo_full;
-- Wishbone Slave
wb_slave_proc: process(sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
wb_dat_o <= (others => '0');
wb_ack_o <= '0';
wb_stall_o <= '0';
ctrl_fifo_rden <= '0';
rx_valid_local <= '0';
ctrl_fifo_dout_tmp <= (others => '0');
-- Regs
loopback <= '0';
elsif rising_edge(sys_clk_i) then
-- Default
wb_ack_o <= '0';
ctrl_fifo_rden <= '0';
wb_stall_o <= '0';
rx_valid_local <= '0';
if (wb_cyc_i = '1' and wb_stb_i = '1') then
if (wb_we_i = '0') then
-- READ
if (wb_adr_i(3 downto 0) = x"0") then -- Start Addr
if (ctrl_fifo_empty = '0') then
wb_dat_o <= ctrl_fifo_dout(31 downto 0);
ctrl_fifo_dout_tmp <= ctrl_fifo_dout(63 downto 32);
wb_ack_o <= '1';
ctrl_fifo_rden <= '1';
else
wb_dat_o <= x"FFFFFFFF";
ctrl_fifo_dout_tmp <= (others => '0');
wb_ack_o <= '1';
ctrl_fifo_rden <= '0';
end if;
elsif (wb_adr_i(3 downto 0) = x"1") then -- Count
wb_dat_o <= ctrl_fifo_dout_tmp;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"2") then -- Loopback
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= loopback;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"3") then -- Data Rate
wb_dat_o <= data_rate;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"5") then -- Bridge Empty
wb_dat_o(31 downto 1) <= (others => '0');
wb_dat_o(0) <= data_fifo_empty_true;
wb_ack_o <= '1';
elsif (wb_adr_i(3 downto 0) = x"6") then -- Cur Count
wb_dat_o <= std_logic_vector(dma_data_cnt_d);
wb_ack_o <= '1';
else
wb_dat_o <= x"DEADBEEF";
wb_ack_o <= '1';
end if;
else
-- WRITE
wb_ack_o <= '1';
if (wb_adr_i(3 downto 0) = x"2") then
loopback <= wb_dat_i(0);
elsif (wb_adr_i(3 downto 0) = x"4") then
rx_valid_local <= '1';
end if;
end if;
end if;
end if;
end process wb_slave_proc;
-- Data from Rx
data_rec : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i <= '0') then
data_fifo_wren <= '0';
data_fifo_din <= (others => '0');
elsif rising_edge(sys_clk_i) then
if (loopback = '1') then
data_fifo_wren <= rx_valid_local_d;
data_fifo_din <= X"03000000" & rx_data_local_d;
else
data_fifo_wren <= rx_valid_i;
data_fifo_din <= rx_data_i;
end if;
end if;
end process data_rec;
-- Empty logic to produce some backpressure
data_fifo_empty <= '1' when (data_fifo_empty_true = '1') else data_fifo_empty_pressure;
empty_proc : process(dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_fifo_empty_pressure <= '0';
data_fifo_empty_cnt <= (others => '0');
elsif rising_edge(dma_clk_i) then
-- Timeout Counter
if (data_fifo_empty_true = '0' and data_fifo_empty_pressure = '1') then
data_fifo_empty_cnt <= data_fifo_empty_cnt + 1;
elsif (data_fifo_empty_true = '1') then
data_fifo_empty_cnt <= (others => '0');
end if;
if (data_fifo_empty_cnt > c_EMPTY_TIMEOUT) then
data_fifo_empty_pressure <= '0';
elsif (data_fifo_prog_empty = '0') then
data_fifo_empty_pressure <= '0';
elsif (data_fifo_empty_true = '1') then
data_fifo_empty_pressure <= '1';
end if;
end if;
end process empty_proc;
-- DMA Master and data control
dma_stb_valid <= dma_stb_t and not data_fifo_empty;
to_ddr_proc: process(dma_clk_i, rst_n_i)
begin
if(rst_n_i = '0') then
dma_stb_t <= '0';
data_fifo_rden <= '0';
dma_adr_o <= (others => '0');
dma_dat_o <= (others => '0');
dma_cyc_o <= '0';
dma_stb_o <= '0';
dma_we_o <= '1'; -- Write only
elsif rising_edge(dma_clk_i) then
if (data_fifo_empty = '0' and dma_stall_i = '0' and ctrl_fifo_full = '0') then
dma_stb_t <= '1';
data_fifo_rden <= '1';
else
dma_stb_t <= '0';
data_fifo_rden <= '0';
end if;
if (data_fifo_empty = '0' or dma_ack_cnt > 0) then
dma_cyc_o <= '1';
else
dma_cyc_o <= '0';
end if;
dma_adr_o <= std_logic_vector(dma_adr_cnt);
dma_dat_o <= data_fifo_dout;
dma_stb_o <= dma_stb_t and not data_fifo_empty;
dma_we_o <= '1'; -- Write only
end if;
end process to_ddr_proc;
adr_proc : process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
ctrl_fifo_wren <= '0';
dma_adr_cnt <= (others => '0');
dma_start_adr <= (others => '0');
dma_data_cnt <= (others => '0');
dma_data_cnt_d <= (others => '0');
dma_timeout_cnt <= (others => '0');
ctrl_fifo_din(63 downto 0) <= (others => '0');
dma_ack_cnt <= (others => '0');
elsif rising_edge(dma_clk_i) then
-- Address Counter
if (dma_stb_valid = '1') then
dma_adr_cnt <= dma_adr_cnt + 1;
end if;
if (dma_stb_valid = '1' and dma_ack_i = '0') then
dma_ack_cnt <= dma_ack_cnt + 1;
elsif (dma_stb_valid = '0' and dma_ack_i = '1' and dma_ack_cnt > 0) then
dma_ack_cnt <= dma_ack_cnt - 1;
end if;
-- Package size counter
-- Check if Fifo is full
if (dma_stb_valid = '1' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE;
dma_data_cnt <= TO_UNSIGNED(2, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '0' and dma_data_cnt >= c_PACKAGE_SIZE and ctrl_fifo_full = '0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + c_PACKAGE_SIZE;
dma_data_cnt <= TO_UNSIGNED(0, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '0' and dma_timeout_cnt >= c_TIMEOUT and dma_data_cnt > 0 and ctrl_fifo_full ='0') then
ctrl_fifo_din(63 downto 32) <= std_logic_vector(dma_data_cnt);
ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_start_adr);
dma_start_adr <= dma_start_adr + dma_data_cnt;
dma_data_cnt <= TO_UNSIGNED(0, 32);
ctrl_fifo_wren <= '1';
elsif (dma_stb_valid = '1') then
dma_data_cnt <= dma_data_cnt + 2;
ctrl_fifo_wren <= '0';
else
ctrl_fifo_wren <= '0';
end if;
dma_data_cnt_d <= dma_data_cnt;
-- if (dma_data_cnt = 0 and ctrl_fifo_wren = '1') then -- New package
-- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt);
-- elsif (dma_data_cnt = 1 and ctrl_fifo_wren = '1') then -- Flying take over
-- ctrl_fifo_din(31 downto 0) <= std_logic_vector(dma_adr_cnt-1);
-- end if;
-- Timeout counter
if (dma_data_cnt > 0 and data_fifo_empty = '1') then
dma_timeout_cnt <= dma_timeout_cnt + 1;
elsif (data_fifo_empty = '0') then
dma_timeout_cnt <= TO_UNSIGNED(0, 32);
end if;
end if;
end process adr_proc;
-- Data Rate maeasurement
data_rate_proc: process(sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
data_rate_cnt <= (others => '0');
data_rate <= (others => '0');
time_cnt <= (others => '0');
time_pulse <= '0';
elsif rising_edge(sys_clk_i) then
-- 1Hz pulser
if (time_cnt = c_TIME_FRAME) then
time_cnt <= (others => '0');
time_pulse <= '1';
else
time_cnt <= time_cnt + 1;
time_pulse <= '0';
end if;
if (time_pulse = '1') then
data_rate <= std_logic_vector(data_rate_cnt);
data_rate_cnt <= (others => '0');
elsif (data_fifo_wren = '1') then
data_rate_cnt <= data_rate_cnt + 1;
end if;
end if;
end process data_rate_proc;
-- Loopback delay
delayproc : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
rx_data_local <= (others => '0');
rx_data_local_d <= (others => '0');
rx_valid_local_d <= '0';
elsif rising_edge(sys_clk_i) then
rx_data_local_d <= wb_dat_i;
rx_valid_local_d <= rx_valid_local;
end if;
end process;
-- Trigger sync and count
trig_sync : process (sys_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
trig_pulse_d0 <= '0';
trig_pulse_d1 <= '0';
trig_pulse_pos <= '0';
trig_cnt <= (others => '0');
elsif rising_edge(sys_clk_i) then
trig_pulse_d0 <= trig_pulse_i;
trig_pulse_d1 <= trig_pulse_d0;
if (trig_pulse_d0 = '1' and trig_pulse_d1 = '0') then
trig_pulse_pos <= '1';
else
trig_pulse_pos <= '0';
end if;
if (trig_pulse_pos = '1') then
trig_cnt <= trig_cnt + 1;
end if;
end if;
end process trig_sync;
cmp_rx_bridge_fifo : rx_bridge_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => sys_clk_i,
rd_clk => dma_clk_i,
din => data_fifo_din,
wr_en => data_fifo_wren,
rd_en => data_fifo_rden,
prog_full_thresh => std_logic_vector(c_ALMOST_FULL_THRESHOLD),
prog_empty_thresh => std_logic_vector(c_EMPTY_THRESHOLD),
dout => data_fifo_dout,
full => data_fifo_full,
empty => data_fifo_empty_true,
prog_full => data_fifo_almost_full,
prog_empty => data_fifo_prog_empty
);
cmp_rx_bridge_ctrl_fifo : rx_bridge_ctrl_fifo PORT MAP (
rst => not rst_n_i,
wr_clk => dma_clk_i,
rd_clk => sys_clk_i,
din => ctrl_fifo_din,
wr_en => ctrl_fifo_wren,
rd_en => ctrl_fifo_rden,
dout => ctrl_fifo_dout,
full => ctrl_fifo_full,
empty => ctrl_fifo_empty
);
end Behavioral;
|
architecture RTL of FIFO is
attribute coordinate of others : component is (0.0, 17.5);
attribute coordinate of OTHERS :component is (0.0, 17.5);
begin
end architecture RTL;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mux2-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of mux2 is
begin
with To_bit(sel) select
y <= i0 after Tpd when '0',
i1 after Tpd when '1';
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mux2-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of mux2 is
begin
with To_bit(sel) select
y <= i0 after Tpd when '0',
i1 after Tpd when '1';
end architecture behavior;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_15_mux2-b.vhd,v 1.2 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
architecture behavior of mux2 is
begin
with To_bit(sel) select
y <= i0 after Tpd when '0',
i1 after Tpd when '1';
end architecture behavior;
|
LIBRARY IEEE;
LIBRARY ALTERA_MF;
LIBRARY LPM;
USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL;
USE LPM.LPM_COMPONENTS.ALL;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DAC_BEEP IS
PORT(
RESETN : IN STD_LOGIC;
FSEL : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DURATION : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CS : IN STD_LOGIC;
CLK_32Hz : IN STD_LOGIC;
DAC_WCLK : IN STD_LOGIC;
DAC_BCLK : IN STD_LOGIC;
DAC_DAT : OUT STD_LOGIC
);
END DAC_BEEP;
ARCHITECTURE a OF DAC_BEEP IS
signal timer : std_logic_vector(15 downto 0);
signal phase : std_logic_vector(15 downto 0);
signal step : std_logic_vector(7 downto 0);
signal sounddata : std_logic_vector(15 downto 0);
BEGIN
-- ROM to hold the waveform
SOUND_LUT : altsyncram
GENERIC MAP (
lpm_type => "altsyncram",
width_a => 16,
numwords_a => 512,
widthad_a => 9,
init_file => "SOUND.mif",
intended_device_family => "Cyclone II",
lpm_hint => "ENABLE_RUNTIME_MOD=NO",
operation_mode => "ROM",
outdata_aclr_a => "NONE",
outdata_reg_a => "UNREGISTERED",
power_up_uninitialized => "FALSE"
)
PORT MAP (
clock0 => NOT(DAC_WCLK),
address_a => phase(10 DOWNTO 2), -- input is angle
q_a => sounddata -- output is amplitude
);
-- shift register to serialize the data to the DAC
DAC_SHIFT : lpm_shiftreg
GENERIC MAP (
lpm_direction => "LEFT",
lpm_type => "LPM_SHIFTREG",
lpm_width => 32
)
PORT MAP (
load => DAC_WCLK,
clock => NOT(DAC_BCLK),
data => sounddata & sounddata,
shiftout => DAC_DAT
);
-- process to perform DDS
PROCESS(RESETN, CS) BEGIN
IF RESETN = '0' THEN
phase <= x"0000";
ELSIF RISING_EDGE(DAC_WCLK) THEN
IF step = x"00" THEN
phase <= x"0000";
ELSE
phase <= phase + step; -- increment the phase
END IF;
END IF;
END PROCESS;
-- process to catch data from SCOMP and run the timer
PROCESS(RESETN, CS, CLK_32Hz) BEGIN
IF RESETN = '0' THEN
timer <= x"0000";
step <= x"00";
ELSIF CS = '1' THEN
timer <= ("000000"&DURATION&"00")-1; -- -1 so that 0 is infinite
step <= FSEL;
ELSIF RISING_EDGE(CLK_32Hz) THEN
IF timer /= x"FFFF" THEN
timer <= timer - 1;
IF timer = x"0000" THEN
step <= x"00";
END IF;
END IF;
END IF;
END PROCESS;
END a;
|
----------------------------------------------------------------------------------
-- 12 bit output to DAC system.
-- Pulls data out from memory and assumes it comes in with the following flow:
-- 1)Waveform duration
-- 2)Starting Voltage
-- 3)Slope
-- If duration comes in as x"FFFF", read_addr is reset to 0 (it is up to the user to design software to insert this)
-- If duration comes in as x"FFFE", the 'running' state is paused to await for a new trigger ( " )
-- If duration comes in as x"FFFD", then 'running' state continues but loops back to the start of memory.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Physical ports
entity output_to_12bitDAC is
port
(
-- clks for incoming data and outputting to DAC
clk_dac : in std_logic;
-- reset trigger for DAC process
iRST : in std_logic;
-- Data buses
data_in : in std_logic_vector(15 downto 0); -- 16 bit data input for waveform data
dac_out : out std_logic_vector(11 downto 0) := (others => '0'); -- 12 bit DAC output
-- Memory address location for DAC data from memory
read_addr_out : out std_logic_vector(13 downto 0);
-- Logic to output new dac value
wr_n : out std_logic; -- Data is transparent to DAC when '0', initialize so dac is suspended
cs_n : out std_logic; -- chip select DAC line, DAC active when '0'
-- Input to begin running waveforms from computer trigger
run_cmd : in std_logic;
-- External logic input to begin running waveforms
run_trigger : in std_logic
);
end entity;
-- Behavioral
architecture rtl of output_to_12bitDAC is
----------------------------------------------------------------------------------
-- SIGNALS
----------------------------------------------------------------------------------
-- Internal write enable and chip select
signal wr_i : std_logic := '0';
signal cs_i : std_logic := '0';
-- Internal copy of the address for reading from memory
signal read_addr : std_logic_vector((read_addr_out'length - 1) downto 0) := (others => '0');
-- Amount of clock cycles to read in new waveform data while running a waveform
constant READ_TIME : std_logic_vector(15 downto 0) := x"0004";
----------------------------------------------------------------------------------
-- BEGIN
----------------------------------------------------------------------------------
begin
-- Latch DAC on/off signals
wr_n <= not(wr_i);
cs_n <= not(cs_i);
-- Latch internal read address to output
read_addr_out <= read_addr;
-- interpret data for DAC
process (clk_dac, run_cmd, run_trigger, iRST)
-- States for the DAC
type DAC_STATES is (RESET, IDLE, RUNNING);
variable dac_state : DAC_STATES := RESET;
-- States when pulling data out of memory
type DAC_READ_MODES is (READ_T, READ_V, READ_dV_float, READ_dV, DONE, NONE);
variable dac_read_mode : DAC_READ_MODES := READ_T;
-- Data communication for the waveform
variable data_comm : std_logic_vector(15 downto 0);
-- The following are internal values for outputting to the DAC waveform
-- Voltage values go 15 downto 4, we have 3 downto 0 to hold decimal points in lower bits
variable dac_out_i : std_logic_vector(31 downto 0);
variable dac_dV_i : std_logic_vector(31 downto 0);
variable time_dac_i : std_logic_vector(15 downto 0);
-- "Reading" versions for reading memory while the DAC still runs the previous waveform cycle
variable dac_out_read : std_logic_vector(31 downto 0);
variable dac_dV_read : std_logic_vector(31 downto 0);
variable time_dac_read : std_logic_vector(15 downto 0);
-- Whether or not we need to be counting
variable timing : std_logic;
begin
-- check reset flag
if iRST = '0' then
dac_state := RESET;
else
-- DAC operations
if rising_edge(clk_dac) then
case dac_state is
when RESET => -- Return to boot conditions
dac_out <= (others => '0');
read_addr <= (others => '0');
wr_i <= '1';
cs_i <= '1';
dac_state := IDLE;
when IDLE => -- Awaiting a run command
-- Prepare to begin reading data at start of 'running'
dac_read_mode := READ_T;
-- empty out linear coefficient while IDLE
dac_dV_i := (others => '0');
-- No counting down when beginning to read a waveform
timing := '0';
-- Deactivate DAC write but activate chip
wr_i <= '0';
cs_i <= '1';
-- Check if the next value on the memory register signifies the end of memory,
-- should be in the position to which READ_T would point in memory
if data_in = x"FFFF" then
read_addr <= (others => '0');
end if;
-- Check conditions to run the waveform
if (run_cmd = '1' OR run_trigger = '1') then
dac_state := RUNNING;
end if;
when RUNNING => -- RUNNING is interpreting data at the current address
-- the M9K RAM updates much faster than this process, so no worries on timing with read_addr
-- Activate DAC output
wr_i <= '1';
-- Latch external waveform data
data_comm := data_in;
case dac_read_mode is
when READ_T =>
-- Read in the time to run the waveform
-- Handling the case that time_dac_read - read_time < 0 to make sure we have time to load the next waveform
if data_comm < READ_TIME then
time_dac_read := READ_TIME;
else
time_dac_read := data_comm;
end if;
read_addr <= read_addr + '1';
-- Read in the starting voltage
dac_read_mode := READ_V;
when READ_V =>
-- Read the voltage
dac_out_read := data_comm & x"0000";
read_addr <= read_addr + '1';
-- Read in the slope
dac_read_mode := READ_dV_float;
when READ_dV_float =>
-- Read fractional linear part
dac_dV_read(15 downto 0) := data_comm;
read_addr <= read_addr + '1';
-- Read the integer part
dac_read_mode := READ_dV;
when READ_dV =>
-- Read linear part
dac_dV_read(31 downto 16) := data_comm;
read_addr <= read_addr + '1';
-- Finished reading in this portion of waveform
dac_read_mode := DONE;
when DONE =>
-- Latch all the read data into values used for writing to DACs, timing including this cycle
dac_out_i := dac_out_read;
dac_dV_i := dac_dV_read;
-- If the next data requires waiting for a new trigger, need to allow the waveform to finish and then break to IDLE
if data_comm >= x"FFFE" then
time_dac_i := time_dac_read - 1 + READ_TIME;
else
time_dac_i := time_dac_read - 1;
end if;
-- If we are in "continous run" mode, loop back to the start of memory but keep running
if data_comm = x"FFFD" then
read_addr <= (others => '0');
end if;
-- We are going to be timing operation time
timing := '1';
-- Prepared to run the waveform
dac_read_mode := NONE;
when NONE =>
-- Not currently reading anything
-- Case statement at NONE should end with the read address for the next waveform's time
dac_read_mode := NONE;
end case;
-- Generating waveform values
-- Alter dac_val_i from coefficients for next output
dac_out_i := dac_out_i + dac_dV_i;
-- Output the voltage
dac_out <= dac_out_i(31 downto (32 - dac_out'length));
if timing = '1' then
if time_dac_i <= READ_TIME then
--Start getting ready for the next round of data
timing := '0';
-- Read in the next waveform
dac_read_mode := READ_T;
-- Check if the time value flags the need to leave RUNNING
if data_comm >= x"FFFE" then
-- Await next run trigger
dac_state := IDLE;
-- Prepare for next waveform
read_addr <= read_addr + '1';
end if;
else -- Still waiting, so loop
time_dac_i := time_dac_i - 1;
dac_read_mode := NONE;
end if;
end if;
end case;
end if;
end if;
end process;
end rtl;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_TRANSCEIVER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KBCLK : INOUT STD_LOGIC;
KBDATA : INOUT STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_TRANSCEIVER;
ARCHITECTURE main OF KB_TRANSCEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
SIGNAL WR_EN : STD_LOGIC;
SIGNAL WR_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0' AND WR_EN = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, HALT_REQ, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT : INTEGER RANGE 0 TO 5000;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
WR_EN <= '0';
ELSIF(CLK'EVENT AND CLK = '1' AND HALT_REQ = '1') THEN
CASE STATE IS
WHEN x"0" =>
IF(COUNT = 5000) THEN
COUNT := 0;
KBCLK <= '1';
STATE := x"1";
END IF;
KBCLK <= '0';
COUNT := COUNT + 1;
WHEN x"1" =>
WR_DATA <= x"EE";
WR_EN <= '1';
STATE := x"1";
WHEN x"2" =>
IF(COUNT = 200) THEN
COUNT := 0;
WR_EN <= '0';
STATE := x"3";
END IF;
COUNT := COUNT + 1;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(KBCLK, WR_EN, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 12;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '1') THEN
CASE STATE IS
WHEN x"0" =>
STATE := x"1";
WHEN x"1" =>
KBDATA <= WR_DATA(ITERATOR);
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
KBDATA <= WR_DATA(0) XOR WR_DATA(1) XOR WR_DATA(2) XOR WR_DATA(3) XOR WR_DATA(4) XOR WR_DATA(5) XOR WR_DATA(6) XOR WR_DATA(7);
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"3";
WHEN OTHERS =>
END CASE;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '0') THEN
STATE := x"0";
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1);
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_TRANSCEIVER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KBCLK : INOUT STD_LOGIC;
KBDATA : INOUT STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_TRANSCEIVER;
ARCHITECTURE main OF KB_TRANSCEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
SIGNAL WR_EN : STD_LOGIC;
SIGNAL WR_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0' AND WR_EN = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, HALT_REQ, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT : INTEGER RANGE 0 TO 5000;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
WR_EN <= '0';
ELSIF(CLK'EVENT AND CLK = '1' AND HALT_REQ = '1') THEN
CASE STATE IS
WHEN x"0" =>
IF(COUNT = 5000) THEN
COUNT := 0;
KBCLK <= '1';
STATE := x"1";
END IF;
KBCLK <= '0';
COUNT := COUNT + 1;
WHEN x"1" =>
WR_DATA <= x"EE";
WR_EN <= '1';
STATE := x"1";
WHEN x"2" =>
IF(COUNT = 200) THEN
COUNT := 0;
WR_EN <= '0';
STATE := x"3";
END IF;
COUNT := COUNT + 1;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(KBCLK, WR_EN, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 12;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '1') THEN
CASE STATE IS
WHEN x"0" =>
STATE := x"1";
WHEN x"1" =>
KBDATA <= WR_DATA(ITERATOR);
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
KBDATA <= WR_DATA(0) XOR WR_DATA(1) XOR WR_DATA(2) XOR WR_DATA(3) XOR WR_DATA(4) XOR WR_DATA(5) XOR WR_DATA(6) XOR WR_DATA(7);
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"3";
WHEN OTHERS =>
END CASE;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '0') THEN
STATE := x"0";
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1);
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_TRANSCEIVER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KBCLK : INOUT STD_LOGIC;
KBDATA : INOUT STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_TRANSCEIVER;
ARCHITECTURE main OF KB_TRANSCEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
SIGNAL WR_EN : STD_LOGIC;
SIGNAL WR_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0' AND WR_EN = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, HALT_REQ, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT : INTEGER RANGE 0 TO 5000;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
WR_EN <= '0';
ELSIF(CLK'EVENT AND CLK = '1' AND HALT_REQ = '1') THEN
CASE STATE IS
WHEN x"0" =>
IF(COUNT = 5000) THEN
COUNT := 0;
KBCLK <= '1';
STATE := x"1";
END IF;
KBCLK <= '0';
COUNT := COUNT + 1;
WHEN x"1" =>
WR_DATA <= x"EE";
WR_EN <= '1';
STATE := x"1";
WHEN x"2" =>
IF(COUNT = 200) THEN
COUNT := 0;
WR_EN <= '0';
STATE := x"3";
END IF;
COUNT := COUNT + 1;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(KBCLK, WR_EN, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 12;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '1') THEN
CASE STATE IS
WHEN x"0" =>
STATE := x"1";
WHEN x"1" =>
KBDATA <= WR_DATA(ITERATOR);
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
KBDATA <= WR_DATA(0) XOR WR_DATA(1) XOR WR_DATA(2) XOR WR_DATA(3) XOR WR_DATA(4) XOR WR_DATA(5) XOR WR_DATA(6) XOR WR_DATA(7);
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"3";
WHEN OTHERS =>
END CASE;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '0') THEN
STATE := x"0";
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1);
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main; |
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY KB_TRANSCEIVER IS
PORT(
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
HALT_REQ : IN STD_LOGIC;
KBCLK : INOUT STD_LOGIC;
KBDATA : INOUT STD_LOGIC;
KEYSTATE : OUT STD_LOGIC;
KEY : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
EXTENDED : OUT STD_LOGIC
);
END KB_TRANSCEIVER;
ARCHITECTURE main OF KB_TRANSCEIVER IS
SIGNAL KBCLKF : STD_LOGIC;
SIGNAL WR_EN : STD_LOGIC;
SIGNAL WR_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
PROCESS(KBCLKF, RST)
VARIABLE REC_DATA : STD_LOGIC_VECTOR(7 DOWNTO 0);
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 10;
VARIABLE UNPRESSING : STD_LOGIC;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
UNPRESSING := '0';
KEY <= x"FF";
KEYSTATE <= '0';
EXTENDED <= '0';
ELSIF(KBCLKF'EVENT AND KBCLKF = '0' AND WR_EN = '0') THEN
CASE STATE IS
WHEN x"0" =>
KEYSTATE <= '1';
STATE := x"1";
WHEN x"1" =>
REC_DATA(ITERATOR) := KBDATA;
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
IF(REC_DATA = x"E0") THEN
EXTENDED <= '1';
ELSIF(REC_DATA = x"F0") THEN
UNPRESSING := '1';
ELSIF(UNPRESSING = '1') THEN
UNPRESSING := '0';
KEYSTATE <= '0';
EXTENDED <= '0';
KEY <= x"FF";
ELSE
KEY <= REC_DATA;
END IF;
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"0";
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(CLK, HALT_REQ, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE COUNT : INTEGER RANGE 0 TO 5000;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
WR_EN <= '0';
ELSIF(CLK'EVENT AND CLK = '1' AND HALT_REQ = '1') THEN
CASE STATE IS
WHEN x"0" =>
IF(COUNT = 5000) THEN
COUNT := 0;
KBCLK <= '1';
STATE := x"1";
END IF;
KBCLK <= '0';
COUNT := COUNT + 1;
WHEN x"1" =>
WR_DATA <= x"EE";
WR_EN <= '1';
STATE := x"1";
WHEN x"2" =>
IF(COUNT = 200) THEN
COUNT := 0;
WR_EN <= '0';
STATE := x"3";
END IF;
COUNT := COUNT + 1;
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS;
PROCESS(KBCLK, WR_EN, RST)
VARIABLE STATE : STD_LOGIC_VECTOR(3 DOWNTO 0);
VARIABLE ITERATOR : INTEGER RANGE 0 TO 12;
BEGIN
IF(RST = '1') THEN
STATE := x"0";
ITERATOR := 0;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '1') THEN
CASE STATE IS
WHEN x"0" =>
STATE := x"1";
WHEN x"1" =>
KBDATA <= WR_DATA(ITERATOR);
ITERATOR := ITERATOR + 1;
IF(ITERATOR = 8) THEN
STATE := x"2";
END IF;
WHEN x"2" =>
KBDATA <= WR_DATA(0) XOR WR_DATA(1) XOR WR_DATA(2) XOR WR_DATA(3) XOR WR_DATA(4) XOR WR_DATA(5) XOR WR_DATA(6) XOR WR_DATA(7);
ITERATOR := 0;
STATE := x"3";
WHEN x"3" =>
STATE := x"3";
WHEN OTHERS =>
END CASE;
ELSIF(KBCLK'EVENT AND KBCLK = '0' AND WR_EN = '0') THEN
STATE := x"0";
END IF;
END PROCESS;
PROCESS(CLK)
VARIABLE CLK_FILTER : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
IF(CLK'EVENT AND CLK = '1') THEN
CLK_FILTER(6 DOWNTO 0) := CLK_FILTER(7 DOWNTO 1);
CLK_FILTER(7) := KBCLK;
IF(CLK_FILTER = "11111111") THEN
KBCLKF <= '1';
ELSIF(CLK_FILTER = "00000000") THEN
KBCLKF <= '0';
END IF;
END IF;
END PROCESS;
END main; |
library ieee;
use ieee.std_logic_1164.all;
entity driver is
port(x: in std_logic;
F: out std_logic);
end Driver;
architecture behaviour of driver is
begin
myproc: process(x)
begin
if (x=4+3*5-7**5/32) then
F <= '1';
else
F <= '0';
end if;
end process myproc;
end behaviour;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Wed Mar 09 00:15:18 2016
-- Host : GilaMonster running 64-bit major release (build 9200)
-- Command : write_vhdl -mode funcsim -nolib -force -file
-- D:/Users/Rob/Documents/Class/ECEC662/video_processing_ip/vga_sync/vga_sync.sim/sim_1/impl/func/vga_sync_func_impl.vhd
-- Design : vga_sync
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vga_sync is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of vga_sync : entity is true;
attribute ECO_CHECKSUM : string;
attribute ECO_CHECKSUM of vga_sync : entity is "1cca350c";
attribute H_BACK_DELAY : integer;
attribute H_BACK_DELAY of vga_sync : entity is 48;
attribute H_FRONT_DELAY : integer;
attribute H_FRONT_DELAY of vga_sync : entity is 16;
attribute H_RETRACE_DELAY : integer;
attribute H_RETRACE_DELAY of vga_sync : entity is 96;
attribute H_SIZE : integer;
attribute H_SIZE of vga_sync : entity is 640;
attribute V_BACK_DELAY : integer;
attribute V_BACK_DELAY of vga_sync : entity is 33;
attribute V_FRONT_DELAY : integer;
attribute V_FRONT_DELAY of vga_sync : entity is 10;
attribute V_RETRACE_DELAY : integer;
attribute V_RETRACE_DELAY of vga_sync : entity is 2;
attribute V_SIZE : integer;
attribute V_SIZE of vga_sync : entity is 480;
end vga_sync;
architecture STRUCTURE of vga_sync is
signal active_OBUF : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal clk_25_IBUF : STD_LOGIC;
signal clk_25_IBUF_BUFG : STD_LOGIC;
signal hcount1 : STD_LOGIC;
signal hcount18_in : STD_LOGIC;
signal \hcount[0]_i_104_n_0\ : STD_LOGIC;
signal \hcount[0]_i_105_n_0\ : STD_LOGIC;
signal \hcount[0]_i_106_n_0\ : STD_LOGIC;
signal \hcount[0]_i_107_n_0\ : STD_LOGIC;
signal \hcount[0]_i_109_n_0\ : STD_LOGIC;
signal \hcount[0]_i_110_n_0\ : STD_LOGIC;
signal \hcount[0]_i_111_n_0\ : STD_LOGIC;
signal \hcount[0]_i_112_n_0\ : STD_LOGIC;
signal \hcount[0]_i_118_n_0\ : STD_LOGIC;
signal \hcount[0]_i_119_n_0\ : STD_LOGIC;
signal \hcount[0]_i_11_n_0\ : STD_LOGIC;
signal \hcount[0]_i_120_n_0\ : STD_LOGIC;
signal \hcount[0]_i_121_n_0\ : STD_LOGIC;
signal \hcount[0]_i_122_n_0\ : STD_LOGIC;
signal \hcount[0]_i_123_n_0\ : STD_LOGIC;
signal \hcount[0]_i_124_n_0\ : STD_LOGIC;
signal \hcount[0]_i_131_n_0\ : STD_LOGIC;
signal \hcount[0]_i_132_n_0\ : STD_LOGIC;
signal \hcount[0]_i_133_n_0\ : STD_LOGIC;
signal \hcount[0]_i_134_n_0\ : STD_LOGIC;
signal \hcount[0]_i_136_n_0\ : STD_LOGIC;
signal \hcount[0]_i_137_n_0\ : STD_LOGIC;
signal \hcount[0]_i_139_n_0\ : STD_LOGIC;
signal \hcount[0]_i_13_n_0\ : STD_LOGIC;
signal \hcount[0]_i_140_n_0\ : STD_LOGIC;
signal \hcount[0]_i_141_n_0\ : STD_LOGIC;
signal \hcount[0]_i_142_n_0\ : STD_LOGIC;
signal \hcount[0]_i_14_n_0\ : STD_LOGIC;
signal \hcount[0]_i_153_n_0\ : STD_LOGIC;
signal \hcount[0]_i_154_n_0\ : STD_LOGIC;
signal \hcount[0]_i_155_n_0\ : STD_LOGIC;
signal \hcount[0]_i_156_n_0\ : STD_LOGIC;
signal \hcount[0]_i_157_n_0\ : STD_LOGIC;
signal \hcount[0]_i_158_n_0\ : STD_LOGIC;
signal \hcount[0]_i_159_n_0\ : STD_LOGIC;
signal \hcount[0]_i_15_n_0\ : STD_LOGIC;
signal \hcount[0]_i_160_n_0\ : STD_LOGIC;
signal \hcount[0]_i_161_n_0\ : STD_LOGIC;
signal \hcount[0]_i_162_n_0\ : STD_LOGIC;
signal \hcount[0]_i_163_n_0\ : STD_LOGIC;
signal \hcount[0]_i_164_n_0\ : STD_LOGIC;
signal \hcount[0]_i_165_n_0\ : STD_LOGIC;
signal \hcount[0]_i_166_n_0\ : STD_LOGIC;
signal \hcount[0]_i_167_n_0\ : STD_LOGIC;
signal \hcount[0]_i_168_n_0\ : STD_LOGIC;
signal \hcount[0]_i_169_n_0\ : STD_LOGIC;
signal \hcount[0]_i_16_n_0\ : STD_LOGIC;
signal \hcount[0]_i_170_n_0\ : STD_LOGIC;
signal \hcount[0]_i_171_n_0\ : STD_LOGIC;
signal \hcount[0]_i_172_n_0\ : STD_LOGIC;
signal \hcount[0]_i_173_n_0\ : STD_LOGIC;
signal \hcount[0]_i_17_n_0\ : STD_LOGIC;
signal \hcount[0]_i_18_n_0\ : STD_LOGIC;
signal \hcount[0]_i_19_n_0\ : STD_LOGIC;
signal \hcount[0]_i_1_n_0\ : STD_LOGIC;
signal \hcount[0]_i_20_n_0\ : STD_LOGIC;
signal \hcount[0]_i_23_n_0\ : STD_LOGIC;
signal \hcount[0]_i_24_n_0\ : STD_LOGIC;
signal \hcount[0]_i_27_n_0\ : STD_LOGIC;
signal \hcount[0]_i_29_n_0\ : STD_LOGIC;
signal \hcount[0]_i_30_n_0\ : STD_LOGIC;
signal \hcount[0]_i_31_n_0\ : STD_LOGIC;
signal \hcount[0]_i_32_n_0\ : STD_LOGIC;
signal \hcount[0]_i_33_n_0\ : STD_LOGIC;
signal \hcount[0]_i_34_n_0\ : STD_LOGIC;
signal \hcount[0]_i_35_n_0\ : STD_LOGIC;
signal \hcount[0]_i_36_n_0\ : STD_LOGIC;
signal \hcount[0]_i_38_n_0\ : STD_LOGIC;
signal \hcount[0]_i_39_n_0\ : STD_LOGIC;
signal \hcount[0]_i_40_n_0\ : STD_LOGIC;
signal \hcount[0]_i_42_n_0\ : STD_LOGIC;
signal \hcount[0]_i_43_n_0\ : STD_LOGIC;
signal \hcount[0]_i_44_n_0\ : STD_LOGIC;
signal \hcount[0]_i_45_n_0\ : STD_LOGIC;
signal \hcount[0]_i_46_n_0\ : STD_LOGIC;
signal \hcount[0]_i_47_n_0\ : STD_LOGIC;
signal \hcount[0]_i_48_n_0\ : STD_LOGIC;
signal \hcount[0]_i_49_n_0\ : STD_LOGIC;
signal \hcount[0]_i_53_n_0\ : STD_LOGIC;
signal \hcount[0]_i_54_n_0\ : STD_LOGIC;
signal \hcount[0]_i_55_n_0\ : STD_LOGIC;
signal \hcount[0]_i_56_n_0\ : STD_LOGIC;
signal \hcount[0]_i_61_n_0\ : STD_LOGIC;
signal \hcount[0]_i_62_n_0\ : STD_LOGIC;
signal \hcount[0]_i_63_n_0\ : STD_LOGIC;
signal \hcount[0]_i_64_n_0\ : STD_LOGIC;
signal \hcount[0]_i_70_n_0\ : STD_LOGIC;
signal \hcount[0]_i_71_n_0\ : STD_LOGIC;
signal \hcount[0]_i_72_n_0\ : STD_LOGIC;
signal \hcount[0]_i_73_n_0\ : STD_LOGIC;
signal \hcount[0]_i_74_n_0\ : STD_LOGIC;
signal \hcount[0]_i_75_n_0\ : STD_LOGIC;
signal \hcount[0]_i_76_n_0\ : STD_LOGIC;
signal \hcount[0]_i_77_n_0\ : STD_LOGIC;
signal \hcount[0]_i_80_n_0\ : STD_LOGIC;
signal \hcount[0]_i_81_n_0\ : STD_LOGIC;
signal \hcount[0]_i_82_n_0\ : STD_LOGIC;
signal \hcount[0]_i_83_n_0\ : STD_LOGIC;
signal \hcount[0]_i_85_n_0\ : STD_LOGIC;
signal \hcount[0]_i_86_n_0\ : STD_LOGIC;
signal \hcount[0]_i_87_n_0\ : STD_LOGIC;
signal \hcount[0]_i_88_n_0\ : STD_LOGIC;
signal \hcount[0]_i_89_n_0\ : STD_LOGIC;
signal \hcount[0]_i_90_n_0\ : STD_LOGIC;
signal \hcount[0]_i_91_n_0\ : STD_LOGIC;
signal \hcount[0]_i_92_n_0\ : STD_LOGIC;
signal hcount_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \hcount_reg[0]_i_103_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_108_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_117_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_12_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_21_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_25_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_28_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_37_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_41_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_4_n_2\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_52_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_60_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_69_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_79_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_7_n_1\ : STD_LOGIC;
signal \hcount_reg[0]_i_84_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_7\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 10 );
signal hsync_OBUF : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal hsync_i_4_n_0 : STD_LOGIC;
signal hsync_i_5_n_0 : STD_LOGIC;
signal hsync_i_6_n_0 : STD_LOGIC;
signal hsync_i_7_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal rst_IBUF : STD_LOGIC;
signal \vcount[0]_i_1_n_0\ : STD_LOGIC;
signal \vcount[0]_i_2_n_0\ : STD_LOGIC;
signal \vcount[0]_i_7_n_0\ : STD_LOGIC;
signal vcount_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \vcount_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 10 );
signal vsync_OBUF : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal vsync_i_3_n_0 : STD_LOGIC;
signal vsync_i_4_n_0 : STD_LOGIC;
signal vsync_i_5_n_0 : STD_LOGIC;
signal vsync_i_6_n_0 : STD_LOGIC;
signal vsync_i_7_n_0 : STD_LOGIC;
signal \xaddr[9]_i_10_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_12_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_13_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_14_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_15_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_16_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_17_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_18_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_19_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_1_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_20_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_21_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_5_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_7_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_8_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_9_n_0\ : STD_LOGIC;
signal xaddr_OBUF : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \xaddr_reg[9]_i_11_n_0\ : STD_LOGIC;
signal \xaddr_reg[9]_i_3_n_3\ : STD_LOGIC;
signal \xaddr_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \xaddr_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_10_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_12_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_13_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_14_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_15_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_16_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_17_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_18_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_19_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_1_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_20_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_21_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_22_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_4_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_5_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_7_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_8_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_9_n_0\ : STD_LOGIC;
signal yaddr_OBUF : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \yaddr_reg[9]_i_11_n_0\ : STD_LOGIC;
signal \yaddr_reg[9]_i_2_n_2\ : STD_LOGIC;
signal \yaddr_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \yaddr_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \NLW_hcount_reg[0]_i_103_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_108_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_117_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_117_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_125_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_126_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_135_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_138_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_143_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_144_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_174_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_183_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_22_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_hcount_reg[0]_i_25_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_hcount_reg[0]_i_28_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_28_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_37_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_37_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_41_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_41_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_hcount_reg[0]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_50_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_51_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_52_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_52_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_60_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_60_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_65_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_78_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_79_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_84_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_84_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_93_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_94_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_vcount_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_xaddr_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
active_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => active_OBUF,
O => active
);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFFAAAA00EA"
)
port map (
I0 => active_OBUF,
I1 => hcount1,
I2 => active_i_2_n_0,
I3 => \hcount_reg[0]_i_7_n_1\,
I4 => rst_IBUF,
I5 => hcount18_in,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_3_n_0\,
I1 => \hcount_reg[0]_i_4_n_2\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => active_i_1_n_0,
Q => active_OBUF,
R => '0'
);
clk_25_IBUF_BUFG_inst: unisim.vcomponents.BUFG
port map (
I => clk_25_IBUF,
O => clk_25_IBUF_BUFG
);
clk_25_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => clk_25,
O => clk_25_IBUF
);
\hcount[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000E00"
)
port map (
I0 => \hcount_reg[0]_i_3_n_0\,
I1 => \hcount_reg[0]_i_4_n_2\,
I2 => hcount18_in,
I3 => hcount1,
I4 => \hcount_reg[0]_i_7_n_1\,
I5 => rst_IBUF,
O => \hcount[0]_i_1_n_0\
);
\hcount[0]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_104_n_0\
);
\hcount[0]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_105_n_0\
);
\hcount[0]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_106_n_0\
);
\hcount[0]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_107_n_0\
);
\hcount[0]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_109_n_0\
);
\hcount[0]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(0),
O => \hcount[0]_i_11_n_0\
);
\hcount[0]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
O => \hcount[0]_i_110_n_0\
);
\hcount[0]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
O => \hcount[0]_i_111_n_0\
);
\hcount[0]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_112_n_0\
);
\hcount[0]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_118_n_0\
);
\hcount[0]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_135_n_4\,
I1 => \hcount_reg[0]_i_126_n_7\,
O => \hcount[0]_i_119_n_0\
);
\hcount[0]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_135_n_6\,
I1 => \hcount_reg[0]_i_135_n_5\,
O => \hcount[0]_i_120_n_0\
);
\hcount[0]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_121_n_0\
);
\hcount[0]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
O => \hcount[0]_i_122_n_0\
);
\hcount[0]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_5\,
I1 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_123_n_0\
);
\hcount[0]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_174_n_4\,
I1 => \hcount_reg[0]_i_135_n_7\,
O => \hcount[0]_i_124_n_0\
);
\hcount[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_13_n_0\
);
\hcount[0]_i_131\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
I1 => \hcount_reg[0]_i_135_n_5\,
I2 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_131_n_0\
);
\hcount[0]_i_132\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \hcount_reg[0]_i_174_n_4\,
I1 => \hcount_reg[0]_i_174_n_5\,
I2 => \hcount_reg[0]_i_174_n_6\,
O => \hcount[0]_i_132_n_0\
);
\hcount[0]_i_133\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_174_n_7\,
I1 => \hcount_reg[0]_i_183_n_4\,
I2 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_133_n_0\
);
\hcount[0]_i_134\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => hcount_reg(0),
I1 => \hcount_reg[0]_i_183_n_7\,
I2 => \hcount_reg[0]_i_183_n_6\,
O => \hcount[0]_i_134_n_0\
);
\hcount[0]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_136_n_0\
);
\hcount[0]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_138_n_4\,
I1 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_137_n_0\
);
\hcount[0]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_139_n_0\
);
\hcount[0]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_14_n_0\
);
\hcount[0]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_138_n_4\,
I1 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_140_n_0\
);
\hcount[0]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_138_n_6\,
I1 => \hcount_reg[0]_i_138_n_5\,
O => \hcount[0]_i_141_n_0\
);
\hcount[0]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(0),
I1 => \hcount_reg[0]_i_138_n_7\,
O => \hcount[0]_i_142_n_0\
);
\hcount[0]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_15_n_0\
);
\hcount[0]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_153_n_0\
);
\hcount[0]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_154_n_0\
);
\hcount[0]_i_155\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_155_n_0\
);
\hcount[0]_i_156\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_156_n_0\
);
\hcount[0]_i_157\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_157_n_0\
);
\hcount[0]_i_158\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_158_n_0\
);
\hcount[0]_i_159\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_144_n_7\,
I1 => \hcount_reg[0]_i_138_n_4\,
O => \hcount[0]_i_159_n_0\
);
\hcount[0]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_16_n_0\
);
\hcount[0]_i_160\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
O => \hcount[0]_i_160_n_0\
);
\hcount[0]_i_161\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_161_n_0\
);
\hcount[0]_i_162\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
O => \hcount[0]_i_162_n_0\
);
\hcount[0]_i_163\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_5\,
I1 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_163_n_0\
);
\hcount[0]_i_164\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
I1 => \hcount_reg[0]_i_174_n_4\,
O => \hcount[0]_i_164_n_0\
);
\hcount[0]_i_165\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_174_n_5\,
I1 => \hcount_reg[0]_i_174_n_6\,
O => \hcount[0]_i_165_n_0\
);
\hcount[0]_i_166\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_174_n_6\,
I1 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_166_n_0\
);
\hcount[0]_i_167\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_183_n_4\,
I1 => \hcount_reg[0]_i_174_n_7\,
O => \hcount[0]_i_167_n_0\
);
\hcount[0]_i_168\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_183_n_6\,
I1 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_168_n_0\
);
\hcount[0]_i_169\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \hcount_reg[0]_i_183_n_7\,
I1 => hcount_reg(0),
O => \hcount[0]_i_169_n_0\
);
\hcount[0]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_17_n_0\
);
\hcount[0]_i_170\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_174_n_6\,
I1 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_170_n_0\
);
\hcount[0]_i_171\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_174_n_7\,
I1 => \hcount_reg[0]_i_183_n_4\,
O => \hcount[0]_i_171_n_0\
);
\hcount[0]_i_172\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_183_n_6\,
I1 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_172_n_0\
);
\hcount[0]_i_173\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(0),
I1 => \hcount_reg[0]_i_183_n_7\,
O => \hcount[0]_i_173_n_0\
);
\hcount[0]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_18_n_0\
);
\hcount[0]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_19_n_0\
);
\hcount[0]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_20_n_0\
);
\hcount[0]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_23_n_0\
);
\hcount[0]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_24_n_0\
);
\hcount[0]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_27_n_0\
);
\hcount[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_29_n_0\
);
\hcount[0]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_65_n_4\,
I1 => \hcount_reg[0]_i_26_n_7\,
O => \hcount[0]_i_30_n_0\
);
\hcount[0]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_31_n_0\
);
\hcount[0]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_78_n_4\,
I1 => \hcount_reg[0]_i_65_n_7\,
O => \hcount[0]_i_32_n_0\
);
\hcount[0]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_33_n_0\
);
\hcount[0]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
O => \hcount[0]_i_34_n_0\
);
\hcount[0]_i_35\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_35_n_0\
);
\hcount[0]_i_36\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
O => \hcount[0]_i_36_n_0\
);
\hcount[0]_i_38\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_38_n_0\
);
\hcount[0]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
I2 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_39_n_0\
);
\hcount[0]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
I2 => \hcount_reg[0]_i_65_n_6\,
O => \hcount[0]_i_40_n_0\
);
\hcount[0]_i_42\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_42_n_0\
);
\hcount[0]_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_43_n_0\
);
\hcount[0]_i_44\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_44_n_0\
);
\hcount[0]_i_45\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_45_n_0\
);
\hcount[0]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_46_n_0\
);
\hcount[0]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_47_n_0\
);
\hcount[0]_i_48\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_48_n_0\
);
\hcount[0]_i_49\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_49_n_0\
);
\hcount[0]_i_53\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_53_n_0\
);
\hcount[0]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_54_n_0\
);
\hcount[0]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_55_n_0\
);
\hcount[0]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_56_n_0\
);
\hcount[0]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
O => \hcount[0]_i_61_n_0\
);
\hcount[0]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_62_n_0\
);
\hcount[0]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
O => \hcount[0]_i_63_n_0\
);
\hcount[0]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
O => \hcount[0]_i_64_n_0\
);
\hcount[0]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_78_n_6\,
I1 => \hcount_reg[0]_i_78_n_5\,
O => \hcount[0]_i_70_n_0\
);
\hcount[0]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_71_n_0\
);
\hcount[0]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_125_n_6\,
I1 => \hcount_reg[0]_i_125_n_5\,
O => \hcount[0]_i_72_n_0\
);
\hcount[0]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_126_n_4\,
I1 => \hcount_reg[0]_i_125_n_7\,
O => \hcount[0]_i_73_n_0\
);
\hcount[0]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
O => \hcount[0]_i_74_n_0\
);
\hcount[0]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_75_n_0\
);
\hcount[0]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
O => \hcount[0]_i_76_n_0\
);
\hcount[0]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
O => \hcount[0]_i_77_n_0\
);
\hcount[0]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
I2 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_80_n_0\
);
\hcount[0]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
I2 => \hcount_reg[0]_i_125_n_4\,
O => \hcount[0]_i_81_n_0\
);
\hcount[0]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
I2 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_82_n_0\
);
\hcount[0]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
I2 => \hcount_reg[0]_i_126_n_6\,
O => \hcount[0]_i_83_n_0\
);
\hcount[0]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_85_n_0\
);
\hcount[0]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_86_n_0\
);
\hcount[0]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_87_n_0\
);
\hcount[0]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_88_n_0\
);
\hcount[0]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_89_n_0\
);
\hcount[0]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_90_n_0\
);
\hcount[0]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_91_n_0\
);
\hcount[0]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_143_n_7\,
I1 => \hcount_reg[0]_i_144_n_4\,
O => \hcount[0]_i_92_n_0\
);
\hcount_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_7\,
Q => hcount_reg(0),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[0]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_103_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_103_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \hcount[0]_i_153_n_0\,
DI(1) => \hcount[0]_i_154_n_0\,
DI(0) => \hcount[0]_i_155_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_156_n_0\,
S(2) => \hcount[0]_i_157_n_0\,
S(1) => \hcount[0]_i_158_n_0\,
S(0) => \hcount[0]_i_159_n_0\
);
\hcount_reg[0]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_108_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_108_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \hcount[0]_i_160_n_0\,
DI(0) => \hcount[0]_i_161_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_162_n_0\,
S(2) => \hcount[0]_i_163_n_0\,
S(1) => \hcount[0]_i_164_n_0\,
S(0) => \hcount[0]_i_165_n_0\
);
\hcount_reg[0]_i_117\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_117_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_117_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => \hcount[0]_i_166_n_0\,
DI(2) => \hcount[0]_i_167_n_0\,
DI(1) => \hcount[0]_i_168_n_0\,
DI(0) => \hcount[0]_i_169_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_117_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_170_n_0\,
S(2) => \hcount[0]_i_171_n_0\,
S(1) => \hcount[0]_i_172_n_0\,
S(0) => \hcount[0]_i_173_n_0\
);
\hcount_reg[0]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_41_n_0\,
CO(3) => \hcount_reg[0]_i_12_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_12_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_42_n_0\,
DI(2) => \hcount[0]_i_43_n_0\,
DI(1) => \hcount[0]_i_44_n_0\,
DI(0) => \hcount[0]_i_45_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_46_n_0\,
S(2) => \hcount[0]_i_47_n_0\,
S(1) => \hcount[0]_i_48_n_0\,
S(0) => \hcount[0]_i_49_n_0\
);
\hcount_reg[0]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_126_n_0\,
CO(3) => \hcount_reg[0]_i_125_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_125_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_125_n_4\,
O(2) => \hcount_reg[0]_i_125_n_5\,
O(1) => \hcount_reg[0]_i_125_n_6\,
O(0) => \hcount_reg[0]_i_125_n_7\,
S(3 downto 0) => \hcount_reg__0\(20 downto 17)
);
\hcount_reg[0]_i_126\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_135_n_0\,
CO(3) => \hcount_reg[0]_i_126_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_126_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_126_n_4\,
O(2) => \hcount_reg[0]_i_126_n_5\,
O(1) => \hcount_reg[0]_i_126_n_6\,
O(0) => \hcount_reg[0]_i_126_n_7\,
S(3 downto 0) => \hcount_reg__0\(16 downto 13)
);
\hcount_reg[0]_i_135\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_174_n_0\,
CO(3) => \hcount_reg[0]_i_135_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_135_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_135_n_4\,
O(2) => \hcount_reg[0]_i_135_n_5\,
O(1) => \hcount_reg[0]_i_135_n_6\,
O(0) => \hcount_reg[0]_i_135_n_7\,
S(3 downto 1) => \hcount_reg__0\(12 downto 10),
S(0) => hcount_reg(9)
);
\hcount_reg[0]_i_138\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_138_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_138_CO_UNCONNECTED\(2 downto 0),
CYINIT => vcount_reg(0),
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_138_n_4\,
O(2) => \hcount_reg[0]_i_138_n_5\,
O(1) => \hcount_reg[0]_i_138_n_6\,
O(0) => \hcount_reg[0]_i_138_n_7\,
S(3 downto 0) => vcount_reg(4 downto 1)
);
\hcount_reg[0]_i_143\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_144_n_0\,
CO(3) => \hcount_reg[0]_i_143_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_143_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_143_n_4\,
O(2) => \hcount_reg[0]_i_143_n_5\,
O(1) => \hcount_reg[0]_i_143_n_6\,
O(0) => \hcount_reg[0]_i_143_n_7\,
S(3 downto 1) => \vcount_reg__0\(12 downto 10),
S(0) => vcount_reg(9)
);
\hcount_reg[0]_i_144\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_138_n_0\,
CO(3) => \hcount_reg[0]_i_144_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_144_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_144_n_4\,
O(2) => \hcount_reg[0]_i_144_n_5\,
O(1) => \hcount_reg[0]_i_144_n_6\,
O(0) => \hcount_reg[0]_i_144_n_7\,
S(3 downto 0) => vcount_reg(8 downto 5)
);
\hcount_reg[0]_i_174\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_183_n_0\,
CO(3) => \hcount_reg[0]_i_174_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_174_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_174_n_4\,
O(2) => \hcount_reg[0]_i_174_n_5\,
O(1) => \hcount_reg[0]_i_174_n_6\,
O(0) => \hcount_reg[0]_i_174_n_7\,
S(3 downto 0) => hcount_reg(8 downto 5)
);
\hcount_reg[0]_i_183\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_183_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_183_CO_UNCONNECTED\(2 downto 0),
CYINIT => hcount_reg(0),
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_183_n_4\,
O(2) => \hcount_reg[0]_i_183_n_5\,
O(1) => \hcount_reg[0]_i_183_n_6\,
O(0) => \hcount_reg[0]_i_183_n_7\,
S(3 downto 0) => hcount_reg(4 downto 1)
);
\hcount_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_2_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \hcount_reg[0]_i_2_n_4\,
O(2) => \hcount_reg[0]_i_2_n_5\,
O(1) => \hcount_reg[0]_i_2_n_6\,
O(0) => \hcount_reg[0]_i_2_n_7\,
S(3 downto 1) => hcount_reg(3 downto 1),
S(0) => \hcount[0]_i_11_n_0\
);
\hcount_reg[0]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_52_n_0\,
CO(3) => \hcount_reg[0]_i_21_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_21_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_53_n_0\,
S(2) => \hcount[0]_i_54_n_0\,
S(1) => \hcount[0]_i_55_n_0\,
S(0) => \hcount[0]_i_56_n_0\
);
\hcount_reg[0]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_50_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[0]_i_22_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_hcount_reg[0]_i_22_O_UNCONNECTED\(3),
O(2) => \hcount_reg[0]_i_22_n_5\,
O(1) => \hcount_reg[0]_i_22_n_6\,
O(0) => \hcount_reg[0]_i_22_n_7\,
S(3) => '0',
S(2 downto 0) => \vcount_reg__0\(31 downto 29)
);
\hcount_reg[0]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_60_n_0\,
CO(3) => \hcount_reg[0]_i_25_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_25_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_61_n_0\,
S(2) => \hcount[0]_i_62_n_0\,
S(1) => \hcount[0]_i_63_n_0\,
S(0) => \hcount[0]_i_64_n_0\
);
\hcount_reg[0]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_65_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[0]_i_26_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_hcount_reg[0]_i_26_O_UNCONNECTED\(3),
O(2) => \hcount_reg[0]_i_26_n_5\,
O(1) => \hcount_reg[0]_i_26_n_6\,
O(0) => \hcount_reg[0]_i_26_n_7\,
S(3) => '0',
S(2 downto 0) => \hcount_reg__0\(31 downto 29)
);
\hcount_reg[0]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_69_n_0\,
CO(3) => \hcount_reg[0]_i_28_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_28_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_70_n_0\,
DI(2) => \hcount[0]_i_71_n_0\,
DI(1) => \hcount[0]_i_72_n_0\,
DI(0) => \hcount[0]_i_73_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_28_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_74_n_0\,
S(2) => \hcount[0]_i_75_n_0\,
S(1) => \hcount[0]_i_76_n_0\,
S(0) => \hcount[0]_i_77_n_0\
);
\hcount_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_12_n_0\,
CO(3) => \hcount_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_13_n_0\,
DI(2) => \hcount[0]_i_14_n_0\,
DI(1) => \hcount[0]_i_15_n_0\,
DI(0) => \hcount[0]_i_16_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_17_n_0\,
S(2) => \hcount[0]_i_18_n_0\,
S(1) => \hcount[0]_i_19_n_0\,
S(0) => \hcount[0]_i_20_n_0\
);
\hcount_reg[0]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_79_n_0\,
CO(3) => \hcount_reg[0]_i_37_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_37_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_37_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_80_n_0\,
S(2) => \hcount[0]_i_81_n_0\,
S(1) => \hcount[0]_i_82_n_0\,
S(0) => \hcount[0]_i_83_n_0\
);
\hcount_reg[0]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_21_n_0\,
CO(3 downto 2) => \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\(3 downto 2),
CO(1) => \hcount_reg[0]_i_4_n_2\,
CO(0) => \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \hcount_reg[0]_i_22_n_5\,
DI(0) => '0',
O(3 downto 0) => \NLW_hcount_reg[0]_i_4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => B"00",
S(1) => \hcount[0]_i_23_n_0\,
S(0) => \hcount[0]_i_24_n_0\
);
\hcount_reg[0]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_84_n_0\,
CO(3) => \hcount_reg[0]_i_41_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_41_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_85_n_0\,
DI(2) => \hcount[0]_i_86_n_0\,
DI(1) => \hcount[0]_i_87_n_0\,
DI(0) => \hcount[0]_i_88_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_41_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_89_n_0\,
S(2) => \hcount[0]_i_90_n_0\,
S(1) => \hcount[0]_i_91_n_0\,
S(0) => \hcount[0]_i_92_n_0\
);
\hcount_reg[0]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_25_n_0\,
CO(3 downto 1) => \NLW_hcount_reg[0]_i_5_CO_UNCONNECTED\(3 downto 1),
CO(0) => hcount18_in,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \hcount_reg[0]_i_26_n_5\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_5_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \hcount[0]_i_27_n_0\
);
\hcount_reg[0]_i_50\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_51_n_0\,
CO(3) => \hcount_reg[0]_i_50_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_50_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_50_n_4\,
O(2) => \hcount_reg[0]_i_50_n_5\,
O(1) => \hcount_reg[0]_i_50_n_6\,
O(0) => \hcount_reg[0]_i_50_n_7\,
S(3 downto 0) => \vcount_reg__0\(28 downto 25)
);
\hcount_reg[0]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_93_n_0\,
CO(3) => \hcount_reg[0]_i_51_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_51_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_51_n_4\,
O(2) => \hcount_reg[0]_i_51_n_5\,
O(1) => \hcount_reg[0]_i_51_n_6\,
O(0) => \hcount_reg[0]_i_51_n_7\,
S(3 downto 0) => \vcount_reg__0\(24 downto 21)
);
\hcount_reg[0]_i_52\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_103_n_0\,
CO(3) => \hcount_reg[0]_i_52_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_52_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_52_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_104_n_0\,
S(2) => \hcount[0]_i_105_n_0\,
S(1) => \hcount[0]_i_106_n_0\,
S(0) => \hcount[0]_i_107_n_0\
);
\hcount_reg[0]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_28_n_0\,
CO(3) => hcount1,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_29_n_0\,
DI(2) => \hcount[0]_i_30_n_0\,
DI(1) => \hcount[0]_i_31_n_0\,
DI(0) => \hcount[0]_i_32_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_33_n_0\,
S(2) => \hcount[0]_i_34_n_0\,
S(1) => \hcount[0]_i_35_n_0\,
S(0) => \hcount[0]_i_36_n_0\
);
\hcount_reg[0]_i_60\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_108_n_0\,
CO(3) => \hcount_reg[0]_i_60_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_60_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_60_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_109_n_0\,
S(2) => \hcount[0]_i_110_n_0\,
S(1) => \hcount[0]_i_111_n_0\,
S(0) => \hcount[0]_i_112_n_0\
);
\hcount_reg[0]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_78_n_0\,
CO(3) => \hcount_reg[0]_i_65_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_65_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_65_n_4\,
O(2) => \hcount_reg[0]_i_65_n_5\,
O(1) => \hcount_reg[0]_i_65_n_6\,
O(0) => \hcount_reg[0]_i_65_n_7\,
S(3 downto 0) => \hcount_reg__0\(28 downto 25)
);
\hcount_reg[0]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_117_n_0\,
CO(3) => \hcount_reg[0]_i_69_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_69_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_118_n_0\,
DI(2) => \hcount[0]_i_119_n_0\,
DI(1) => \hcount[0]_i_120_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_hcount_reg[0]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_121_n_0\,
S(2) => \hcount[0]_i_122_n_0\,
S(1) => \hcount[0]_i_123_n_0\,
S(0) => \hcount[0]_i_124_n_0\
);
\hcount_reg[0]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_37_n_0\,
CO(3) => \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\(3),
CO(2) => \hcount_reg[0]_i_7_n_1\,
CO(1 downto 0) => \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\(1 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_7_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \hcount[0]_i_38_n_0\,
S(1) => \hcount[0]_i_39_n_0\,
S(0) => \hcount[0]_i_40_n_0\
);
\hcount_reg[0]_i_78\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_125_n_0\,
CO(3) => \hcount_reg[0]_i_78_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_78_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_78_n_4\,
O(2) => \hcount_reg[0]_i_78_n_5\,
O(1) => \hcount_reg[0]_i_78_n_6\,
O(0) => \hcount_reg[0]_i_78_n_7\,
S(3 downto 0) => \hcount_reg__0\(24 downto 21)
);
\hcount_reg[0]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_79_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_79_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_131_n_0\,
S(2) => \hcount[0]_i_132_n_0\,
S(1) => \hcount[0]_i_133_n_0\,
S(0) => \hcount[0]_i_134_n_0\
);
\hcount_reg[0]_i_84\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_84_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_84_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => \hcount[0]_i_136_n_0\,
DI(2) => \hcount[0]_i_137_n_0\,
DI(1) => '0',
DI(0) => \hcount_reg[0]_i_138_n_7\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_84_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_139_n_0\,
S(2) => \hcount[0]_i_140_n_0\,
S(1) => \hcount[0]_i_141_n_0\,
S(0) => \hcount[0]_i_142_n_0\
);
\hcount_reg[0]_i_93\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_94_n_0\,
CO(3) => \hcount_reg[0]_i_93_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_93_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_93_n_4\,
O(2) => \hcount_reg[0]_i_93_n_5\,
O(1) => \hcount_reg[0]_i_93_n_6\,
O(0) => \hcount_reg[0]_i_93_n_7\,
S(3 downto 0) => \vcount_reg__0\(20 downto 17)
);
\hcount_reg[0]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_143_n_0\,
CO(3) => \hcount_reg[0]_i_94_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_94_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_94_n_4\,
O(2) => \hcount_reg[0]_i_94_n_5\,
O(1) => \hcount_reg[0]_i_94_n_6\,
O(0) => \hcount_reg[0]_i_94_n_7\,
S(3 downto 0) => \vcount_reg__0\(16 downto 13)
);
\hcount_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_5\,
Q => \hcount_reg__0\(10),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_4\,
Q => \hcount_reg__0\(11),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_7\,
Q => \hcount_reg__0\(12),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[8]_i_1_n_0\,
CO(3) => \hcount_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[12]_i_1_n_4\,
O(2) => \hcount_reg[12]_i_1_n_5\,
O(1) => \hcount_reg[12]_i_1_n_6\,
O(0) => \hcount_reg[12]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(15 downto 12)
);
\hcount_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_6\,
Q => \hcount_reg__0\(13),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_5\,
Q => \hcount_reg__0\(14),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_4\,
Q => \hcount_reg__0\(15),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_7\,
Q => \hcount_reg__0\(16),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[12]_i_1_n_0\,
CO(3) => \hcount_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[16]_i_1_n_4\,
O(2) => \hcount_reg[16]_i_1_n_5\,
O(1) => \hcount_reg[16]_i_1_n_6\,
O(0) => \hcount_reg[16]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(19 downto 16)
);
\hcount_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_6\,
Q => \hcount_reg__0\(17),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_5\,
Q => \hcount_reg__0\(18),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_4\,
Q => \hcount_reg__0\(19),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_6\,
Q => hcount_reg(1),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_7\,
Q => \hcount_reg__0\(20),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[16]_i_1_n_0\,
CO(3) => \hcount_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[20]_i_1_n_4\,
O(2) => \hcount_reg[20]_i_1_n_5\,
O(1) => \hcount_reg[20]_i_1_n_6\,
O(0) => \hcount_reg[20]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(23 downto 20)
);
\hcount_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_6\,
Q => \hcount_reg__0\(21),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_5\,
Q => \hcount_reg__0\(22),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_4\,
Q => \hcount_reg__0\(23),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_7\,
Q => \hcount_reg__0\(24),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[20]_i_1_n_0\,
CO(3) => \hcount_reg[24]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[24]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[24]_i_1_n_4\,
O(2) => \hcount_reg[24]_i_1_n_5\,
O(1) => \hcount_reg[24]_i_1_n_6\,
O(0) => \hcount_reg[24]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(27 downto 24)
);
\hcount_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_6\,
Q => \hcount_reg__0\(25),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_5\,
Q => \hcount_reg__0\(26),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_4\,
Q => \hcount_reg__0\(27),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_7\,
Q => \hcount_reg__0\(28),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[24]_i_1_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[28]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[28]_i_1_n_4\,
O(2) => \hcount_reg[28]_i_1_n_5\,
O(1) => \hcount_reg[28]_i_1_n_6\,
O(0) => \hcount_reg[28]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(31 downto 28)
);
\hcount_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_6\,
Q => \hcount_reg__0\(29),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_5\,
Q => hcount_reg(2),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_5\,
Q => \hcount_reg__0\(30),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_4\,
Q => \hcount_reg__0\(31),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_4\,
Q => hcount_reg(3),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_7\,
Q => hcount_reg(4),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_2_n_0\,
CO(3) => \hcount_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[4]_i_1_n_4\,
O(2) => \hcount_reg[4]_i_1_n_5\,
O(1) => \hcount_reg[4]_i_1_n_6\,
O(0) => \hcount_reg[4]_i_1_n_7\,
S(3 downto 0) => hcount_reg(7 downto 4)
);
\hcount_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_6\,
Q => hcount_reg(5),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_5\,
Q => hcount_reg(6),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_4\,
Q => hcount_reg(7),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_7\,
Q => hcount_reg(8),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[4]_i_1_n_0\,
CO(3) => \hcount_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[8]_i_1_n_4\,
O(2) => \hcount_reg[8]_i_1_n_5\,
O(1) => \hcount_reg[8]_i_1_n_6\,
O(0) => \hcount_reg[8]_i_1_n_7\,
S(3 downto 2) => \hcount_reg__0\(11 downto 10),
S(1 downto 0) => hcount_reg(9 downto 8)
);
\hcount_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_6\,
Q => hcount_reg(9),
R => \hcount[0]_i_1_n_0\
);
hsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => hsync_OBUF,
O => hsync
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8888888"
)
port map (
I0 => hsync_OBUF,
I1 => rst_IBUF,
I2 => hsync_i_2_n_0,
I3 => hsync_i_3_n_0,
I4 => hsync_i_4_n_0,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => hsync_i_5_n_0,
I1 => hsync_i_6_n_0,
I2 => hsync_i_7_n_0,
I3 => hcount_reg(2),
I4 => hcount_reg(1),
I5 => hcount_reg(0),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(29),
I1 => \hcount_reg__0\(30),
I2 => \hcount_reg__0\(27),
I3 => \hcount_reg__0\(28),
I4 => rst_IBUF,
I5 => \hcount_reg__0\(31),
O => hsync_i_3_n_0
);
hsync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(23),
I1 => \hcount_reg__0\(24),
I2 => \hcount_reg__0\(21),
I3 => \hcount_reg__0\(22),
I4 => \hcount_reg__0\(26),
I5 => \hcount_reg__0\(25),
O => hsync_i_4_n_0
);
hsync_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(11),
I1 => \hcount_reg__0\(12),
I2 => hcount_reg(9),
I3 => \hcount_reg__0\(10),
I4 => \hcount_reg__0\(14),
I5 => \hcount_reg__0\(13),
O => hsync_i_5_n_0
);
hsync_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(17),
I1 => \hcount_reg__0\(18),
I2 => \hcount_reg__0\(15),
I3 => \hcount_reg__0\(16),
I4 => \hcount_reg__0\(20),
I5 => \hcount_reg__0\(19),
O => hsync_i_6_n_0
);
hsync_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => hcount_reg(5),
I1 => hcount_reg(6),
I2 => hcount_reg(3),
I3 => hcount_reg(4),
I4 => hcount_reg(8),
I5 => hcount_reg(7),
O => hsync_i_7_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync_OBUF,
R => '0'
);
rst_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => rst,
O => rst_IBUF
);
\vcount[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => \hcount_reg[0]_i_4_n_2\,
I1 => hcount18_in,
I2 => \hcount_reg[0]_i_3_n_0\,
I3 => hcount1,
I4 => \hcount_reg[0]_i_7_n_1\,
I5 => rst_IBUF,
O => \vcount[0]_i_1_n_0\
);
\vcount[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => hcount18_in,
I1 => hcount1,
I2 => \hcount_reg[0]_i_7_n_1\,
O => \vcount[0]_i_2_n_0\
);
\vcount[0]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(0),
O => \vcount[0]_i_7_n_0\
);
\vcount_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_7\,
Q => vcount_reg(0),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \vcount_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \vcount_reg[0]_i_3_n_4\,
O(2) => \vcount_reg[0]_i_3_n_5\,
O(1) => \vcount_reg[0]_i_3_n_6\,
O(0) => \vcount_reg[0]_i_3_n_7\,
S(3 downto 1) => vcount_reg(3 downto 1),
S(0) => \vcount[0]_i_7_n_0\
);
\vcount_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_5\,
Q => \vcount_reg__0\(10),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_4\,
Q => \vcount_reg__0\(11),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_7\,
Q => \vcount_reg__0\(12),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[8]_i_1_n_0\,
CO(3) => \vcount_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[12]_i_1_n_4\,
O(2) => \vcount_reg[12]_i_1_n_5\,
O(1) => \vcount_reg[12]_i_1_n_6\,
O(0) => \vcount_reg[12]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(15 downto 12)
);
\vcount_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_6\,
Q => \vcount_reg__0\(13),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_5\,
Q => \vcount_reg__0\(14),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_4\,
Q => \vcount_reg__0\(15),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_7\,
Q => \vcount_reg__0\(16),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[12]_i_1_n_0\,
CO(3) => \vcount_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[16]_i_1_n_4\,
O(2) => \vcount_reg[16]_i_1_n_5\,
O(1) => \vcount_reg[16]_i_1_n_6\,
O(0) => \vcount_reg[16]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(19 downto 16)
);
\vcount_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_6\,
Q => \vcount_reg__0\(17),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_5\,
Q => \vcount_reg__0\(18),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_4\,
Q => \vcount_reg__0\(19),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_6\,
Q => vcount_reg(1),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_7\,
Q => \vcount_reg__0\(20),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[16]_i_1_n_0\,
CO(3) => \vcount_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[20]_i_1_n_4\,
O(2) => \vcount_reg[20]_i_1_n_5\,
O(1) => \vcount_reg[20]_i_1_n_6\,
O(0) => \vcount_reg[20]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(23 downto 20)
);
\vcount_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_6\,
Q => \vcount_reg__0\(21),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_5\,
Q => \vcount_reg__0\(22),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_4\,
Q => \vcount_reg__0\(23),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_7\,
Q => \vcount_reg__0\(24),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[20]_i_1_n_0\,
CO(3) => \vcount_reg[24]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[24]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[24]_i_1_n_4\,
O(2) => \vcount_reg[24]_i_1_n_5\,
O(1) => \vcount_reg[24]_i_1_n_6\,
O(0) => \vcount_reg[24]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(27 downto 24)
);
\vcount_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_6\,
Q => \vcount_reg__0\(25),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_5\,
Q => \vcount_reg__0\(26),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_4\,
Q => \vcount_reg__0\(27),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_7\,
Q => \vcount_reg__0\(28),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[24]_i_1_n_0\,
CO(3 downto 0) => \NLW_vcount_reg[28]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[28]_i_1_n_4\,
O(2) => \vcount_reg[28]_i_1_n_5\,
O(1) => \vcount_reg[28]_i_1_n_6\,
O(0) => \vcount_reg[28]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(31 downto 28)
);
\vcount_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_6\,
Q => \vcount_reg__0\(29),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_5\,
Q => vcount_reg(2),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_5\,
Q => \vcount_reg__0\(30),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_4\,
Q => \vcount_reg__0\(31),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_4\,
Q => vcount_reg(3),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_7\,
Q => vcount_reg(4),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[0]_i_3_n_0\,
CO(3) => \vcount_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[4]_i_1_n_4\,
O(2) => \vcount_reg[4]_i_1_n_5\,
O(1) => \vcount_reg[4]_i_1_n_6\,
O(0) => \vcount_reg[4]_i_1_n_7\,
S(3 downto 0) => vcount_reg(7 downto 4)
);
\vcount_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_6\,
Q => vcount_reg(5),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_5\,
Q => vcount_reg(6),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_4\,
Q => vcount_reg(7),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_7\,
Q => vcount_reg(8),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[4]_i_1_n_0\,
CO(3) => \vcount_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[8]_i_1_n_4\,
O(2) => \vcount_reg[8]_i_1_n_5\,
O(1) => \vcount_reg[8]_i_1_n_6\,
O(0) => \vcount_reg[8]_i_1_n_7\,
S(3 downto 2) => \vcount_reg__0\(11 downto 10),
S(1 downto 0) => vcount_reg(9 downto 8)
);
\vcount_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_6\,
Q => vcount_reg(9),
R => \vcount[0]_i_1_n_0\
);
vsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => vsync_OBUF,
O => vsync
);
vsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8888888"
)
port map (
I0 => vsync_OBUF,
I1 => rst_IBUF,
I2 => vsync_i_2_n_0,
I3 => vsync_i_3_n_0,
I4 => vsync_i_4_n_0,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => vsync_i_5_n_0,
I1 => vsync_i_6_n_0,
I2 => vsync_i_7_n_0,
I3 => vcount_reg(2),
I4 => vcount_reg(1),
I5 => vcount_reg(0),
O => vsync_i_2_n_0
);
vsync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(29),
I1 => \vcount_reg__0\(30),
I2 => \vcount_reg__0\(27),
I3 => \vcount_reg__0\(28),
I4 => rst_IBUF,
I5 => \vcount_reg__0\(31),
O => vsync_i_3_n_0
);
vsync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(23),
I1 => \vcount_reg__0\(24),
I2 => \vcount_reg__0\(21),
I3 => \vcount_reg__0\(22),
I4 => \vcount_reg__0\(26),
I5 => \vcount_reg__0\(25),
O => vsync_i_4_n_0
);
vsync_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(11),
I1 => \vcount_reg__0\(12),
I2 => vcount_reg(9),
I3 => \vcount_reg__0\(10),
I4 => \vcount_reg__0\(14),
I5 => \vcount_reg__0\(13),
O => vsync_i_5_n_0
);
vsync_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(17),
I1 => \vcount_reg__0\(18),
I2 => \vcount_reg__0\(15),
I3 => \vcount_reg__0\(16),
I4 => \vcount_reg__0\(20),
I5 => \vcount_reg__0\(19),
O => vsync_i_6_n_0
);
vsync_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => vcount_reg(5),
I1 => vcount_reg(6),
I2 => vcount_reg(3),
I3 => vcount_reg(4),
I4 => vcount_reg(8),
I5 => vcount_reg(7),
O => vsync_i_7_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync_OBUF,
R => '0'
);
\xaddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
I1 => \xaddr_reg[9]_i_3_n_3\,
O => \xaddr[9]_i_1_n_0\
);
\xaddr[9]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(22),
I1 => \hcount_reg__0\(23),
O => \xaddr[9]_i_10_n_0\
);
\xaddr[9]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(20),
I1 => \hcount_reg__0\(21),
O => \xaddr[9]_i_12_n_0\
);
\xaddr[9]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(18),
I1 => \hcount_reg__0\(19),
O => \xaddr[9]_i_13_n_0\
);
\xaddr[9]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(16),
I1 => \hcount_reg__0\(17),
O => \xaddr[9]_i_14_n_0\
);
\xaddr[9]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(14),
I1 => \hcount_reg__0\(15),
O => \xaddr[9]_i_15_n_0\
);
\xaddr[9]_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(9),
O => \xaddr[9]_i_16_n_0\
);
\xaddr[9]_i_17\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(7),
O => \xaddr[9]_i_17_n_0\
);
\xaddr[9]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(12),
I1 => \hcount_reg__0\(13),
O => \xaddr[9]_i_18_n_0\
);
\xaddr[9]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(10),
I1 => \hcount_reg__0\(11),
O => \xaddr[9]_i_19_n_0\
);
\xaddr[9]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
O => p_0_in
);
\xaddr[9]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(9),
I1 => hcount_reg(8),
O => \xaddr[9]_i_20_n_0\
);
\xaddr[9]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(7),
I1 => hcount_reg(6),
O => \xaddr[9]_i_21_n_0\
);
\xaddr[9]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(30),
I1 => \hcount_reg__0\(31),
O => \xaddr[9]_i_5_n_0\
);
\xaddr[9]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(28),
I1 => \hcount_reg__0\(29),
O => \xaddr[9]_i_7_n_0\
);
\xaddr[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(26),
I1 => \hcount_reg__0\(27),
O => \xaddr[9]_i_8_n_0\
);
\xaddr[9]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(24),
I1 => \hcount_reg__0\(25),
O => \xaddr[9]_i_9_n_0\
);
\xaddr_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(0),
O => xaddr(0)
);
\xaddr_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(1),
O => xaddr(1)
);
\xaddr_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(2),
O => xaddr(2)
);
\xaddr_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(3),
O => xaddr(3)
);
\xaddr_OBUF[4]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(4),
O => xaddr(4)
);
\xaddr_OBUF[5]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(5),
O => xaddr(5)
);
\xaddr_OBUF[6]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(6),
O => xaddr(6)
);
\xaddr_OBUF[7]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(7),
O => xaddr(7)
);
\xaddr_OBUF[8]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(8),
O => xaddr(8)
);
\xaddr_OBUF[9]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(9),
O => xaddr(9)
);
\xaddr_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(0),
Q => xaddr_OBUF(0),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(1),
Q => xaddr_OBUF(1),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(2),
Q => xaddr_OBUF(2),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(3),
Q => xaddr_OBUF(3),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(4),
Q => xaddr_OBUF(4),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(5),
Q => xaddr_OBUF(5),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(6),
Q => xaddr_OBUF(6),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(7),
Q => xaddr_OBUF(7),
R => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(8),
Q => xaddr_OBUF(8),
R => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(9),
Q => xaddr_OBUF(9),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[9]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \xaddr_reg[9]_i_11_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_11_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \xaddr[9]_i_16_n_0\,
DI(0) => \xaddr[9]_i_17_n_0\,
O(3 downto 0) => \NLW_xaddr_reg[9]_i_11_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_18_n_0\,
S(2) => \xaddr[9]_i_19_n_0\,
S(1) => \xaddr[9]_i_20_n_0\,
S(0) => \xaddr[9]_i_21_n_0\
);
\xaddr_reg[9]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_4_n_0\,
CO(3 downto 1) => \NLW_xaddr_reg[9]_i_3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \xaddr_reg[9]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \hcount_reg__0\(31),
O(3 downto 0) => \NLW_xaddr_reg[9]_i_3_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \xaddr[9]_i_5_n_0\
);
\xaddr_reg[9]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_6_n_0\,
CO(3) => \xaddr_reg[9]_i_4_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_xaddr_reg[9]_i_4_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_7_n_0\,
S(2) => \xaddr[9]_i_8_n_0\,
S(1) => \xaddr[9]_i_9_n_0\,
S(0) => \xaddr[9]_i_10_n_0\
);
\xaddr_reg[9]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_11_n_0\,
CO(3) => \xaddr_reg[9]_i_6_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_xaddr_reg[9]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_12_n_0\,
S(2) => \xaddr[9]_i_13_n_0\,
S(1) => \xaddr[9]_i_14_n_0\,
S(0) => \xaddr[9]_i_15_n_0\
);
\yaddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
I1 => \yaddr_reg[9]_i_2_n_2\,
O => \yaddr[9]_i_1_n_0\
);
\yaddr[9]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(20),
I1 => \vcount_reg__0\(21),
O => \yaddr[9]_i_10_n_0\
);
\yaddr[9]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(18),
I1 => \vcount_reg__0\(19),
O => \yaddr[9]_i_12_n_0\
);
\yaddr[9]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(16),
I1 => \vcount_reg__0\(17),
O => \yaddr[9]_i_13_n_0\
);
\yaddr[9]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(14),
I1 => \vcount_reg__0\(15),
O => \yaddr[9]_i_14_n_0\
);
\yaddr[9]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(12),
I1 => \vcount_reg__0\(13),
O => \yaddr[9]_i_15_n_0\
);
\yaddr[9]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(8),
I1 => vcount_reg(9),
O => \yaddr[9]_i_16_n_0\
);
\yaddr[9]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => vcount_reg(6),
I1 => vcount_reg(7),
O => \yaddr[9]_i_17_n_0\
);
\yaddr[9]_i_18\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(5),
O => \yaddr[9]_i_18_n_0\
);
\yaddr[9]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(10),
I1 => \vcount_reg__0\(11),
O => \yaddr[9]_i_19_n_0\
);
\yaddr[9]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => vcount_reg(8),
I1 => vcount_reg(9),
O => \yaddr[9]_i_20_n_0\
);
\yaddr[9]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => vcount_reg(6),
I1 => vcount_reg(7),
O => \yaddr[9]_i_21_n_0\
);
\yaddr[9]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => vcount_reg(5),
I1 => vcount_reg(4),
O => \yaddr[9]_i_22_n_0\
);
\yaddr[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(30),
I1 => \vcount_reg__0\(31),
O => \yaddr[9]_i_4_n_0\
);
\yaddr[9]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(28),
I1 => \vcount_reg__0\(29),
O => \yaddr[9]_i_5_n_0\
);
\yaddr[9]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(26),
I1 => \vcount_reg__0\(27),
O => \yaddr[9]_i_7_n_0\
);
\yaddr[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(24),
I1 => \vcount_reg__0\(25),
O => \yaddr[9]_i_8_n_0\
);
\yaddr[9]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(22),
I1 => \vcount_reg__0\(23),
O => \yaddr[9]_i_9_n_0\
);
\yaddr_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(0),
O => yaddr(0)
);
\yaddr_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(1),
O => yaddr(1)
);
\yaddr_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(2),
O => yaddr(2)
);
\yaddr_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(3),
O => yaddr(3)
);
\yaddr_OBUF[4]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(4),
O => yaddr(4)
);
\yaddr_OBUF[5]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(5),
O => yaddr(5)
);
\yaddr_OBUF[6]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(6),
O => yaddr(6)
);
\yaddr_OBUF[7]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(7),
O => yaddr(7)
);
\yaddr_OBUF[8]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(8),
O => yaddr(8)
);
\yaddr_OBUF[9]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(9),
O => yaddr(9)
);
\yaddr_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(0),
Q => yaddr_OBUF(0),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(1),
Q => yaddr_OBUF(1),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(2),
Q => yaddr_OBUF(2),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(3),
Q => yaddr_OBUF(3),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(4),
Q => yaddr_OBUF(4),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(5),
Q => yaddr_OBUF(5),
R => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(6),
Q => yaddr_OBUF(6),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(7),
Q => yaddr_OBUF(7),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(8),
Q => yaddr_OBUF(8),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(9),
Q => yaddr_OBUF(9),
R => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[9]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \yaddr_reg[9]_i_11_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_11_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \yaddr[9]_i_16_n_0\,
DI(1) => \yaddr[9]_i_17_n_0\,
DI(0) => \yaddr[9]_i_18_n_0\,
O(3 downto 0) => \NLW_yaddr_reg[9]_i_11_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_19_n_0\,
S(2) => \yaddr[9]_i_20_n_0\,
S(1) => \yaddr[9]_i_21_n_0\,
S(0) => \yaddr[9]_i_22_n_0\
);
\yaddr_reg[9]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_3_n_0\,
CO(3 downto 2) => \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \yaddr_reg[9]_i_2_n_2\,
CO(0) => \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \vcount_reg__0\(31),
DI(0) => '0',
O(3 downto 0) => \NLW_yaddr_reg[9]_i_2_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => B"00",
S(1) => \yaddr[9]_i_4_n_0\,
S(0) => \yaddr[9]_i_5_n_0\
);
\yaddr_reg[9]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_6_n_0\,
CO(3) => \yaddr_reg[9]_i_3_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_yaddr_reg[9]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_7_n_0\,
S(2) => \yaddr[9]_i_8_n_0\,
S(1) => \yaddr[9]_i_9_n_0\,
S(0) => \yaddr[9]_i_10_n_0\
);
\yaddr_reg[9]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_11_n_0\,
CO(3) => \yaddr_reg[9]_i_6_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_yaddr_reg[9]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_12_n_0\,
S(2) => \yaddr[9]_i_13_n_0\,
S(1) => \yaddr[9]_i_14_n_0\,
S(0) => \yaddr[9]_i_15_n_0\
);
end STRUCTURE;
|
-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.4 (win64) Build 1412921 Wed Nov 18 09:43:45 MST 2015
-- Date : Wed Mar 09 00:15:18 2016
-- Host : GilaMonster running 64-bit major release (build 9200)
-- Command : write_vhdl -mode funcsim -nolib -force -file
-- D:/Users/Rob/Documents/Class/ECEC662/video_processing_ip/vga_sync/vga_sync.sim/sim_1/impl/func/vga_sync_func_impl.vhd
-- Design : vga_sync
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity vga_sync is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of vga_sync : entity is true;
attribute ECO_CHECKSUM : string;
attribute ECO_CHECKSUM of vga_sync : entity is "1cca350c";
attribute H_BACK_DELAY : integer;
attribute H_BACK_DELAY of vga_sync : entity is 48;
attribute H_FRONT_DELAY : integer;
attribute H_FRONT_DELAY of vga_sync : entity is 16;
attribute H_RETRACE_DELAY : integer;
attribute H_RETRACE_DELAY of vga_sync : entity is 96;
attribute H_SIZE : integer;
attribute H_SIZE of vga_sync : entity is 640;
attribute V_BACK_DELAY : integer;
attribute V_BACK_DELAY of vga_sync : entity is 33;
attribute V_FRONT_DELAY : integer;
attribute V_FRONT_DELAY of vga_sync : entity is 10;
attribute V_RETRACE_DELAY : integer;
attribute V_RETRACE_DELAY of vga_sync : entity is 2;
attribute V_SIZE : integer;
attribute V_SIZE of vga_sync : entity is 480;
end vga_sync;
architecture STRUCTURE of vga_sync is
signal active_OBUF : STD_LOGIC;
signal active_i_1_n_0 : STD_LOGIC;
signal active_i_2_n_0 : STD_LOGIC;
signal clk_25_IBUF : STD_LOGIC;
signal clk_25_IBUF_BUFG : STD_LOGIC;
signal hcount1 : STD_LOGIC;
signal hcount18_in : STD_LOGIC;
signal \hcount[0]_i_104_n_0\ : STD_LOGIC;
signal \hcount[0]_i_105_n_0\ : STD_LOGIC;
signal \hcount[0]_i_106_n_0\ : STD_LOGIC;
signal \hcount[0]_i_107_n_0\ : STD_LOGIC;
signal \hcount[0]_i_109_n_0\ : STD_LOGIC;
signal \hcount[0]_i_110_n_0\ : STD_LOGIC;
signal \hcount[0]_i_111_n_0\ : STD_LOGIC;
signal \hcount[0]_i_112_n_0\ : STD_LOGIC;
signal \hcount[0]_i_118_n_0\ : STD_LOGIC;
signal \hcount[0]_i_119_n_0\ : STD_LOGIC;
signal \hcount[0]_i_11_n_0\ : STD_LOGIC;
signal \hcount[0]_i_120_n_0\ : STD_LOGIC;
signal \hcount[0]_i_121_n_0\ : STD_LOGIC;
signal \hcount[0]_i_122_n_0\ : STD_LOGIC;
signal \hcount[0]_i_123_n_0\ : STD_LOGIC;
signal \hcount[0]_i_124_n_0\ : STD_LOGIC;
signal \hcount[0]_i_131_n_0\ : STD_LOGIC;
signal \hcount[0]_i_132_n_0\ : STD_LOGIC;
signal \hcount[0]_i_133_n_0\ : STD_LOGIC;
signal \hcount[0]_i_134_n_0\ : STD_LOGIC;
signal \hcount[0]_i_136_n_0\ : STD_LOGIC;
signal \hcount[0]_i_137_n_0\ : STD_LOGIC;
signal \hcount[0]_i_139_n_0\ : STD_LOGIC;
signal \hcount[0]_i_13_n_0\ : STD_LOGIC;
signal \hcount[0]_i_140_n_0\ : STD_LOGIC;
signal \hcount[0]_i_141_n_0\ : STD_LOGIC;
signal \hcount[0]_i_142_n_0\ : STD_LOGIC;
signal \hcount[0]_i_14_n_0\ : STD_LOGIC;
signal \hcount[0]_i_153_n_0\ : STD_LOGIC;
signal \hcount[0]_i_154_n_0\ : STD_LOGIC;
signal \hcount[0]_i_155_n_0\ : STD_LOGIC;
signal \hcount[0]_i_156_n_0\ : STD_LOGIC;
signal \hcount[0]_i_157_n_0\ : STD_LOGIC;
signal \hcount[0]_i_158_n_0\ : STD_LOGIC;
signal \hcount[0]_i_159_n_0\ : STD_LOGIC;
signal \hcount[0]_i_15_n_0\ : STD_LOGIC;
signal \hcount[0]_i_160_n_0\ : STD_LOGIC;
signal \hcount[0]_i_161_n_0\ : STD_LOGIC;
signal \hcount[0]_i_162_n_0\ : STD_LOGIC;
signal \hcount[0]_i_163_n_0\ : STD_LOGIC;
signal \hcount[0]_i_164_n_0\ : STD_LOGIC;
signal \hcount[0]_i_165_n_0\ : STD_LOGIC;
signal \hcount[0]_i_166_n_0\ : STD_LOGIC;
signal \hcount[0]_i_167_n_0\ : STD_LOGIC;
signal \hcount[0]_i_168_n_0\ : STD_LOGIC;
signal \hcount[0]_i_169_n_0\ : STD_LOGIC;
signal \hcount[0]_i_16_n_0\ : STD_LOGIC;
signal \hcount[0]_i_170_n_0\ : STD_LOGIC;
signal \hcount[0]_i_171_n_0\ : STD_LOGIC;
signal \hcount[0]_i_172_n_0\ : STD_LOGIC;
signal \hcount[0]_i_173_n_0\ : STD_LOGIC;
signal \hcount[0]_i_17_n_0\ : STD_LOGIC;
signal \hcount[0]_i_18_n_0\ : STD_LOGIC;
signal \hcount[0]_i_19_n_0\ : STD_LOGIC;
signal \hcount[0]_i_1_n_0\ : STD_LOGIC;
signal \hcount[0]_i_20_n_0\ : STD_LOGIC;
signal \hcount[0]_i_23_n_0\ : STD_LOGIC;
signal \hcount[0]_i_24_n_0\ : STD_LOGIC;
signal \hcount[0]_i_27_n_0\ : STD_LOGIC;
signal \hcount[0]_i_29_n_0\ : STD_LOGIC;
signal \hcount[0]_i_30_n_0\ : STD_LOGIC;
signal \hcount[0]_i_31_n_0\ : STD_LOGIC;
signal \hcount[0]_i_32_n_0\ : STD_LOGIC;
signal \hcount[0]_i_33_n_0\ : STD_LOGIC;
signal \hcount[0]_i_34_n_0\ : STD_LOGIC;
signal \hcount[0]_i_35_n_0\ : STD_LOGIC;
signal \hcount[0]_i_36_n_0\ : STD_LOGIC;
signal \hcount[0]_i_38_n_0\ : STD_LOGIC;
signal \hcount[0]_i_39_n_0\ : STD_LOGIC;
signal \hcount[0]_i_40_n_0\ : STD_LOGIC;
signal \hcount[0]_i_42_n_0\ : STD_LOGIC;
signal \hcount[0]_i_43_n_0\ : STD_LOGIC;
signal \hcount[0]_i_44_n_0\ : STD_LOGIC;
signal \hcount[0]_i_45_n_0\ : STD_LOGIC;
signal \hcount[0]_i_46_n_0\ : STD_LOGIC;
signal \hcount[0]_i_47_n_0\ : STD_LOGIC;
signal \hcount[0]_i_48_n_0\ : STD_LOGIC;
signal \hcount[0]_i_49_n_0\ : STD_LOGIC;
signal \hcount[0]_i_53_n_0\ : STD_LOGIC;
signal \hcount[0]_i_54_n_0\ : STD_LOGIC;
signal \hcount[0]_i_55_n_0\ : STD_LOGIC;
signal \hcount[0]_i_56_n_0\ : STD_LOGIC;
signal \hcount[0]_i_61_n_0\ : STD_LOGIC;
signal \hcount[0]_i_62_n_0\ : STD_LOGIC;
signal \hcount[0]_i_63_n_0\ : STD_LOGIC;
signal \hcount[0]_i_64_n_0\ : STD_LOGIC;
signal \hcount[0]_i_70_n_0\ : STD_LOGIC;
signal \hcount[0]_i_71_n_0\ : STD_LOGIC;
signal \hcount[0]_i_72_n_0\ : STD_LOGIC;
signal \hcount[0]_i_73_n_0\ : STD_LOGIC;
signal \hcount[0]_i_74_n_0\ : STD_LOGIC;
signal \hcount[0]_i_75_n_0\ : STD_LOGIC;
signal \hcount[0]_i_76_n_0\ : STD_LOGIC;
signal \hcount[0]_i_77_n_0\ : STD_LOGIC;
signal \hcount[0]_i_80_n_0\ : STD_LOGIC;
signal \hcount[0]_i_81_n_0\ : STD_LOGIC;
signal \hcount[0]_i_82_n_0\ : STD_LOGIC;
signal \hcount[0]_i_83_n_0\ : STD_LOGIC;
signal \hcount[0]_i_85_n_0\ : STD_LOGIC;
signal \hcount[0]_i_86_n_0\ : STD_LOGIC;
signal \hcount[0]_i_87_n_0\ : STD_LOGIC;
signal \hcount[0]_i_88_n_0\ : STD_LOGIC;
signal \hcount[0]_i_89_n_0\ : STD_LOGIC;
signal \hcount[0]_i_90_n_0\ : STD_LOGIC;
signal \hcount[0]_i_91_n_0\ : STD_LOGIC;
signal \hcount[0]_i_92_n_0\ : STD_LOGIC;
signal hcount_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \hcount_reg[0]_i_103_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_108_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_117_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_125_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_126_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_12_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_135_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_138_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_143_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_144_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_174_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_183_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_21_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_22_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_25_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_26_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_28_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_2_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_37_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_41_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_4_n_2\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_50_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_51_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_52_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_60_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_65_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_69_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_78_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_79_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_7_n_1\ : STD_LOGIC;
signal \hcount_reg[0]_i_84_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_93_n_7\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_0\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_4\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_5\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_6\ : STD_LOGIC;
signal \hcount_reg[0]_i_94_n_7\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \hcount_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \hcount_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 10 );
signal hsync_OBUF : STD_LOGIC;
signal hsync_i_1_n_0 : STD_LOGIC;
signal hsync_i_2_n_0 : STD_LOGIC;
signal hsync_i_3_n_0 : STD_LOGIC;
signal hsync_i_4_n_0 : STD_LOGIC;
signal hsync_i_5_n_0 : STD_LOGIC;
signal hsync_i_6_n_0 : STD_LOGIC;
signal hsync_i_7_n_0 : STD_LOGIC;
signal p_0_in : STD_LOGIC;
signal rst_IBUF : STD_LOGIC;
signal \vcount[0]_i_1_n_0\ : STD_LOGIC;
signal \vcount[0]_i_2_n_0\ : STD_LOGIC;
signal \vcount[0]_i_7_n_0\ : STD_LOGIC;
signal vcount_reg : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \vcount_reg[0]_i_3_n_0\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_4\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_5\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_6\ : STD_LOGIC;
signal \vcount_reg[0]_i_3_n_7\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[12]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[16]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[20]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[24]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[28]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_0\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \vcount_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \vcount_reg__0\ : STD_LOGIC_VECTOR ( 31 downto 10 );
signal vsync_OBUF : STD_LOGIC;
signal vsync_i_1_n_0 : STD_LOGIC;
signal vsync_i_2_n_0 : STD_LOGIC;
signal vsync_i_3_n_0 : STD_LOGIC;
signal vsync_i_4_n_0 : STD_LOGIC;
signal vsync_i_5_n_0 : STD_LOGIC;
signal vsync_i_6_n_0 : STD_LOGIC;
signal vsync_i_7_n_0 : STD_LOGIC;
signal \xaddr[9]_i_10_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_12_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_13_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_14_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_15_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_16_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_17_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_18_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_19_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_1_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_20_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_21_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_5_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_7_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_8_n_0\ : STD_LOGIC;
signal \xaddr[9]_i_9_n_0\ : STD_LOGIC;
signal xaddr_OBUF : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \xaddr_reg[9]_i_11_n_0\ : STD_LOGIC;
signal \xaddr_reg[9]_i_3_n_3\ : STD_LOGIC;
signal \xaddr_reg[9]_i_4_n_0\ : STD_LOGIC;
signal \xaddr_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_10_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_12_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_13_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_14_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_15_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_16_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_17_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_18_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_19_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_1_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_20_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_21_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_22_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_4_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_5_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_7_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_8_n_0\ : STD_LOGIC;
signal \yaddr[9]_i_9_n_0\ : STD_LOGIC;
signal yaddr_OBUF : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \yaddr_reg[9]_i_11_n_0\ : STD_LOGIC;
signal \yaddr_reg[9]_i_2_n_2\ : STD_LOGIC;
signal \yaddr_reg[9]_i_3_n_0\ : STD_LOGIC;
signal \yaddr_reg[9]_i_6_n_0\ : STD_LOGIC;
signal \NLW_hcount_reg[0]_i_103_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_103_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_108_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_108_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_117_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_117_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_12_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_12_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_125_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_126_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_135_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_138_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_143_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_144_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_174_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_183_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_21_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_21_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_22_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_22_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_hcount_reg[0]_i_25_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_25_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_26_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_26_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
signal \NLW_hcount_reg[0]_i_28_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_28_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_37_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_37_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_41_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_41_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_5_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_hcount_reg[0]_i_5_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_50_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_51_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_52_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_52_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_60_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_60_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_65_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_69_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_69_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_7_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_78_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_79_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_79_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_84_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_84_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[0]_i_93_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[0]_i_94_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_hcount_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_hcount_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[0]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[12]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[16]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[24]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[28]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_vcount_reg[4]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_vcount_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
signal \NLW_xaddr_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_4_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_4_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_xaddr_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_xaddr_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_11_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_11_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_3_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_yaddr_reg[9]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_yaddr_reg[9]_i_6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
active_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => active_OBUF,
O => active
);
active_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAFFFFAAAA00EA"
)
port map (
I0 => active_OBUF,
I1 => hcount1,
I2 => active_i_2_n_0,
I3 => \hcount_reg[0]_i_7_n_1\,
I4 => rst_IBUF,
I5 => hcount18_in,
O => active_i_1_n_0
);
active_i_2: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_3_n_0\,
I1 => \hcount_reg[0]_i_4_n_2\,
O => active_i_2_n_0
);
active_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => active_i_1_n_0,
Q => active_OBUF,
R => '0'
);
clk_25_IBUF_BUFG_inst: unisim.vcomponents.BUFG
port map (
I => clk_25_IBUF,
O => clk_25_IBUF_BUFG
);
clk_25_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => clk_25,
O => clk_25_IBUF
);
\hcount[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000E00"
)
port map (
I0 => \hcount_reg[0]_i_3_n_0\,
I1 => \hcount_reg[0]_i_4_n_2\,
I2 => hcount18_in,
I3 => hcount1,
I4 => \hcount_reg[0]_i_7_n_1\,
I5 => rst_IBUF,
O => \hcount[0]_i_1_n_0\
);
\hcount[0]_i_104\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_104_n_0\
);
\hcount[0]_i_105\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_105_n_0\
);
\hcount[0]_i_106\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_106_n_0\
);
\hcount[0]_i_107\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_107_n_0\
);
\hcount[0]_i_109\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_109_n_0\
);
\hcount[0]_i_11\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(0),
O => \hcount[0]_i_11_n_0\
);
\hcount[0]_i_110\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
O => \hcount[0]_i_110_n_0\
);
\hcount[0]_i_111\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
O => \hcount[0]_i_111_n_0\
);
\hcount[0]_i_112\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_112_n_0\
);
\hcount[0]_i_118\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_118_n_0\
);
\hcount[0]_i_119\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_135_n_4\,
I1 => \hcount_reg[0]_i_126_n_7\,
O => \hcount[0]_i_119_n_0\
);
\hcount[0]_i_120\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_135_n_6\,
I1 => \hcount_reg[0]_i_135_n_5\,
O => \hcount[0]_i_120_n_0\
);
\hcount[0]_i_121\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_6\,
I1 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_121_n_0\
);
\hcount[0]_i_122\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
O => \hcount[0]_i_122_n_0\
);
\hcount[0]_i_123\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_5\,
I1 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_123_n_0\
);
\hcount[0]_i_124\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_174_n_4\,
I1 => \hcount_reg[0]_i_135_n_7\,
O => \hcount[0]_i_124_n_0\
);
\hcount[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_13_n_0\
);
\hcount[0]_i_131\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
I1 => \hcount_reg[0]_i_135_n_5\,
I2 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_131_n_0\
);
\hcount[0]_i_132\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \hcount_reg[0]_i_174_n_4\,
I1 => \hcount_reg[0]_i_174_n_5\,
I2 => \hcount_reg[0]_i_174_n_6\,
O => \hcount[0]_i_132_n_0\
);
\hcount[0]_i_133\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_174_n_7\,
I1 => \hcount_reg[0]_i_183_n_4\,
I2 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_133_n_0\
);
\hcount[0]_i_134\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => hcount_reg(0),
I1 => \hcount_reg[0]_i_183_n_7\,
I2 => \hcount_reg[0]_i_183_n_6\,
O => \hcount[0]_i_134_n_0\
);
\hcount[0]_i_136\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_136_n_0\
);
\hcount[0]_i_137\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_138_n_4\,
I1 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_137_n_0\
);
\hcount[0]_i_139\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_139_n_0\
);
\hcount[0]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_14_n_0\
);
\hcount[0]_i_140\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_138_n_4\,
I1 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_140_n_0\
);
\hcount[0]_i_141\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_138_n_6\,
I1 => \hcount_reg[0]_i_138_n_5\,
O => \hcount[0]_i_141_n_0\
);
\hcount[0]_i_142\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(0),
I1 => \hcount_reg[0]_i_138_n_7\,
O => \hcount[0]_i_142_n_0\
);
\hcount[0]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_15_n_0\
);
\hcount[0]_i_153\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_153_n_0\
);
\hcount[0]_i_154\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_154_n_0\
);
\hcount[0]_i_155\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_144_n_7\,
O => \hcount[0]_i_155_n_0\
);
\hcount[0]_i_156\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_156_n_0\
);
\hcount[0]_i_157\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_157_n_0\
);
\hcount[0]_i_158\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_144_n_6\,
I1 => \hcount_reg[0]_i_144_n_5\,
O => \hcount[0]_i_158_n_0\
);
\hcount[0]_i_159\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_144_n_7\,
I1 => \hcount_reg[0]_i_138_n_4\,
O => \hcount[0]_i_159_n_0\
);
\hcount[0]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_16_n_0\
);
\hcount[0]_i_160\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
O => \hcount[0]_i_160_n_0\
);
\hcount[0]_i_161\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_161_n_0\
);
\hcount[0]_i_162\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
O => \hcount[0]_i_162_n_0\
);
\hcount[0]_i_163\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_135_n_5\,
I1 => \hcount_reg[0]_i_135_n_6\,
O => \hcount[0]_i_163_n_0\
);
\hcount[0]_i_164\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_135_n_7\,
I1 => \hcount_reg[0]_i_174_n_4\,
O => \hcount[0]_i_164_n_0\
);
\hcount[0]_i_165\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_174_n_5\,
I1 => \hcount_reg[0]_i_174_n_6\,
O => \hcount[0]_i_165_n_0\
);
\hcount[0]_i_166\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_174_n_6\,
I1 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_166_n_0\
);
\hcount[0]_i_167\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_183_n_4\,
I1 => \hcount_reg[0]_i_174_n_7\,
O => \hcount[0]_i_167_n_0\
);
\hcount[0]_i_168\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_183_n_6\,
I1 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_168_n_0\
);
\hcount[0]_i_169\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \hcount_reg[0]_i_183_n_7\,
I1 => hcount_reg(0),
O => \hcount[0]_i_169_n_0\
);
\hcount[0]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_17_n_0\
);
\hcount[0]_i_170\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_174_n_6\,
I1 => \hcount_reg[0]_i_174_n_5\,
O => \hcount[0]_i_170_n_0\
);
\hcount[0]_i_171\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_174_n_7\,
I1 => \hcount_reg[0]_i_183_n_4\,
O => \hcount[0]_i_171_n_0\
);
\hcount[0]_i_172\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_183_n_6\,
I1 => \hcount_reg[0]_i_183_n_5\,
O => \hcount[0]_i_172_n_0\
);
\hcount[0]_i_173\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(0),
I1 => \hcount_reg[0]_i_183_n_7\,
O => \hcount[0]_i_173_n_0\
);
\hcount[0]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_18_n_0\
);
\hcount[0]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_19_n_0\
);
\hcount[0]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_20_n_0\
);
\hcount[0]_i_23\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_22_n_6\,
I1 => \hcount_reg[0]_i_22_n_5\,
O => \hcount[0]_i_23_n_0\
);
\hcount[0]_i_24\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_4\,
I1 => \hcount_reg[0]_i_22_n_7\,
O => \hcount[0]_i_24_n_0\
);
\hcount[0]_i_27\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_27_n_0\
);
\hcount[0]_i_29\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_29_n_0\
);
\hcount[0]_i_30\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_65_n_4\,
I1 => \hcount_reg[0]_i_26_n_7\,
O => \hcount[0]_i_30_n_0\
);
\hcount[0]_i_31\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_31_n_0\
);
\hcount[0]_i_32\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_78_n_4\,
I1 => \hcount_reg[0]_i_65_n_7\,
O => \hcount[0]_i_32_n_0\
);
\hcount[0]_i_33\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_33_n_0\
);
\hcount[0]_i_34\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
O => \hcount[0]_i_34_n_0\
);
\hcount[0]_i_35\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_35_n_0\
);
\hcount[0]_i_36\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
O => \hcount[0]_i_36_n_0\
);
\hcount[0]_i_38\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_6\,
I1 => \hcount_reg[0]_i_26_n_5\,
O => \hcount[0]_i_38_n_0\
);
\hcount[0]_i_39\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
I2 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_39_n_0\
);
\hcount[0]_i_40\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
I2 => \hcount_reg[0]_i_65_n_6\,
O => \hcount[0]_i_40_n_0\
);
\hcount[0]_i_42\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_42_n_0\
);
\hcount[0]_i_43\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_43_n_0\
);
\hcount[0]_i_44\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_44_n_0\
);
\hcount[0]_i_45\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_45_n_0\
);
\hcount[0]_i_46\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_46_n_0\
);
\hcount[0]_i_47\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_47_n_0\
);
\hcount[0]_i_48\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_6\,
I1 => \hcount_reg[0]_i_93_n_5\,
O => \hcount[0]_i_48_n_0\
);
\hcount[0]_i_49\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_4\,
I1 => \hcount_reg[0]_i_93_n_7\,
O => \hcount[0]_i_49_n_0\
);
\hcount[0]_i_53\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_50_n_6\,
I1 => \hcount_reg[0]_i_50_n_5\,
O => \hcount[0]_i_53_n_0\
);
\hcount[0]_i_54\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_4\,
I1 => \hcount_reg[0]_i_50_n_7\,
O => \hcount[0]_i_54_n_0\
);
\hcount[0]_i_55\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_51_n_6\,
I1 => \hcount_reg[0]_i_51_n_5\,
O => \hcount[0]_i_55_n_0\
);
\hcount[0]_i_56\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_93_n_4\,
I1 => \hcount_reg[0]_i_51_n_7\,
O => \hcount[0]_i_56_n_0\
);
\hcount[0]_i_61\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_26_n_7\,
I1 => \hcount_reg[0]_i_65_n_4\,
O => \hcount[0]_i_61_n_0\
);
\hcount[0]_i_62\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_6\,
I1 => \hcount_reg[0]_i_65_n_5\,
O => \hcount[0]_i_62_n_0\
);
\hcount[0]_i_63\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_65_n_7\,
I1 => \hcount_reg[0]_i_78_n_4\,
O => \hcount[0]_i_63_n_0\
);
\hcount[0]_i_64\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
O => \hcount[0]_i_64_n_0\
);
\hcount[0]_i_70\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_78_n_6\,
I1 => \hcount_reg[0]_i_78_n_5\,
O => \hcount[0]_i_70_n_0\
);
\hcount[0]_i_71\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_71_n_0\
);
\hcount[0]_i_72\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_125_n_6\,
I1 => \hcount_reg[0]_i_125_n_5\,
O => \hcount[0]_i_72_n_0\
);
\hcount[0]_i_73\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_126_n_4\,
I1 => \hcount_reg[0]_i_125_n_7\,
O => \hcount[0]_i_73_n_0\
);
\hcount[0]_i_74\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
O => \hcount[0]_i_74_n_0\
);
\hcount[0]_i_75\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_4\,
I1 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_75_n_0\
);
\hcount[0]_i_76\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
O => \hcount[0]_i_76_n_0\
);
\hcount[0]_i_77\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
O => \hcount[0]_i_77_n_0\
);
\hcount[0]_i_80\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_78_n_5\,
I1 => \hcount_reg[0]_i_78_n_6\,
I2 => \hcount_reg[0]_i_78_n_7\,
O => \hcount[0]_i_80_n_0\
);
\hcount[0]_i_81\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_125_n_5\,
I1 => \hcount_reg[0]_i_125_n_6\,
I2 => \hcount_reg[0]_i_125_n_4\,
O => \hcount[0]_i_81_n_0\
);
\hcount[0]_i_82\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_125_n_7\,
I1 => \hcount_reg[0]_i_126_n_4\,
I2 => \hcount_reg[0]_i_126_n_5\,
O => \hcount[0]_i_82_n_0\
);
\hcount[0]_i_83\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \hcount_reg[0]_i_126_n_7\,
I1 => \hcount_reg[0]_i_135_n_4\,
I2 => \hcount_reg[0]_i_126_n_6\,
O => \hcount[0]_i_83_n_0\
);
\hcount[0]_i_85\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_85_n_0\
);
\hcount[0]_i_86\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_86_n_0\
);
\hcount[0]_i_87\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_87_n_0\
);
\hcount[0]_i_88\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \hcount_reg[0]_i_144_n_4\,
I1 => \hcount_reg[0]_i_143_n_7\,
O => \hcount[0]_i_88_n_0\
);
\hcount[0]_i_89\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_94_n_6\,
I1 => \hcount_reg[0]_i_94_n_5\,
O => \hcount[0]_i_89_n_0\
);
\hcount[0]_i_90\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_4\,
I1 => \hcount_reg[0]_i_94_n_7\,
O => \hcount[0]_i_90_n_0\
);
\hcount[0]_i_91\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg[0]_i_143_n_6\,
I1 => \hcount_reg[0]_i_143_n_5\,
O => \hcount[0]_i_91_n_0\
);
\hcount[0]_i_92\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \hcount_reg[0]_i_143_n_7\,
I1 => \hcount_reg[0]_i_144_n_4\,
O => \hcount[0]_i_92_n_0\
);
\hcount_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_7\,
Q => hcount_reg(0),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[0]_i_103\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_103_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_103_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \hcount[0]_i_153_n_0\,
DI(1) => \hcount[0]_i_154_n_0\,
DI(0) => \hcount[0]_i_155_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_103_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_156_n_0\,
S(2) => \hcount[0]_i_157_n_0\,
S(1) => \hcount[0]_i_158_n_0\,
S(0) => \hcount[0]_i_159_n_0\
);
\hcount_reg[0]_i_108\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_108_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_108_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \hcount[0]_i_160_n_0\,
DI(0) => \hcount[0]_i_161_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_108_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_162_n_0\,
S(2) => \hcount[0]_i_163_n_0\,
S(1) => \hcount[0]_i_164_n_0\,
S(0) => \hcount[0]_i_165_n_0\
);
\hcount_reg[0]_i_117\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_117_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_117_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => \hcount[0]_i_166_n_0\,
DI(2) => \hcount[0]_i_167_n_0\,
DI(1) => \hcount[0]_i_168_n_0\,
DI(0) => \hcount[0]_i_169_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_117_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_170_n_0\,
S(2) => \hcount[0]_i_171_n_0\,
S(1) => \hcount[0]_i_172_n_0\,
S(0) => \hcount[0]_i_173_n_0\
);
\hcount_reg[0]_i_12\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_41_n_0\,
CO(3) => \hcount_reg[0]_i_12_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_12_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_42_n_0\,
DI(2) => \hcount[0]_i_43_n_0\,
DI(1) => \hcount[0]_i_44_n_0\,
DI(0) => \hcount[0]_i_45_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_12_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_46_n_0\,
S(2) => \hcount[0]_i_47_n_0\,
S(1) => \hcount[0]_i_48_n_0\,
S(0) => \hcount[0]_i_49_n_0\
);
\hcount_reg[0]_i_125\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_126_n_0\,
CO(3) => \hcount_reg[0]_i_125_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_125_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_125_n_4\,
O(2) => \hcount_reg[0]_i_125_n_5\,
O(1) => \hcount_reg[0]_i_125_n_6\,
O(0) => \hcount_reg[0]_i_125_n_7\,
S(3 downto 0) => \hcount_reg__0\(20 downto 17)
);
\hcount_reg[0]_i_126\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_135_n_0\,
CO(3) => \hcount_reg[0]_i_126_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_126_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_126_n_4\,
O(2) => \hcount_reg[0]_i_126_n_5\,
O(1) => \hcount_reg[0]_i_126_n_6\,
O(0) => \hcount_reg[0]_i_126_n_7\,
S(3 downto 0) => \hcount_reg__0\(16 downto 13)
);
\hcount_reg[0]_i_135\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_174_n_0\,
CO(3) => \hcount_reg[0]_i_135_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_135_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_135_n_4\,
O(2) => \hcount_reg[0]_i_135_n_5\,
O(1) => \hcount_reg[0]_i_135_n_6\,
O(0) => \hcount_reg[0]_i_135_n_7\,
S(3 downto 1) => \hcount_reg__0\(12 downto 10),
S(0) => hcount_reg(9)
);
\hcount_reg[0]_i_138\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_138_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_138_CO_UNCONNECTED\(2 downto 0),
CYINIT => vcount_reg(0),
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_138_n_4\,
O(2) => \hcount_reg[0]_i_138_n_5\,
O(1) => \hcount_reg[0]_i_138_n_6\,
O(0) => \hcount_reg[0]_i_138_n_7\,
S(3 downto 0) => vcount_reg(4 downto 1)
);
\hcount_reg[0]_i_143\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_144_n_0\,
CO(3) => \hcount_reg[0]_i_143_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_143_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_143_n_4\,
O(2) => \hcount_reg[0]_i_143_n_5\,
O(1) => \hcount_reg[0]_i_143_n_6\,
O(0) => \hcount_reg[0]_i_143_n_7\,
S(3 downto 1) => \vcount_reg__0\(12 downto 10),
S(0) => vcount_reg(9)
);
\hcount_reg[0]_i_144\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_138_n_0\,
CO(3) => \hcount_reg[0]_i_144_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_144_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_144_n_4\,
O(2) => \hcount_reg[0]_i_144_n_5\,
O(1) => \hcount_reg[0]_i_144_n_6\,
O(0) => \hcount_reg[0]_i_144_n_7\,
S(3 downto 0) => vcount_reg(8 downto 5)
);
\hcount_reg[0]_i_174\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_183_n_0\,
CO(3) => \hcount_reg[0]_i_174_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_174_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_174_n_4\,
O(2) => \hcount_reg[0]_i_174_n_5\,
O(1) => \hcount_reg[0]_i_174_n_6\,
O(0) => \hcount_reg[0]_i_174_n_7\,
S(3 downto 0) => hcount_reg(8 downto 5)
);
\hcount_reg[0]_i_183\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_183_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_183_CO_UNCONNECTED\(2 downto 0),
CYINIT => hcount_reg(0),
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_183_n_4\,
O(2) => \hcount_reg[0]_i_183_n_5\,
O(1) => \hcount_reg[0]_i_183_n_6\,
O(0) => \hcount_reg[0]_i_183_n_7\,
S(3 downto 0) => hcount_reg(4 downto 1)
);
\hcount_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_2_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_2_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \hcount_reg[0]_i_2_n_4\,
O(2) => \hcount_reg[0]_i_2_n_5\,
O(1) => \hcount_reg[0]_i_2_n_6\,
O(0) => \hcount_reg[0]_i_2_n_7\,
S(3 downto 1) => hcount_reg(3 downto 1),
S(0) => \hcount[0]_i_11_n_0\
);
\hcount_reg[0]_i_21\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_52_n_0\,
CO(3) => \hcount_reg[0]_i_21_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_21_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_21_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_53_n_0\,
S(2) => \hcount[0]_i_54_n_0\,
S(1) => \hcount[0]_i_55_n_0\,
S(0) => \hcount[0]_i_56_n_0\
);
\hcount_reg[0]_i_22\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_50_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[0]_i_22_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_hcount_reg[0]_i_22_O_UNCONNECTED\(3),
O(2) => \hcount_reg[0]_i_22_n_5\,
O(1) => \hcount_reg[0]_i_22_n_6\,
O(0) => \hcount_reg[0]_i_22_n_7\,
S(3) => '0',
S(2 downto 0) => \vcount_reg__0\(31 downto 29)
);
\hcount_reg[0]_i_25\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_60_n_0\,
CO(3) => \hcount_reg[0]_i_25_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_25_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_25_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_61_n_0\,
S(2) => \hcount[0]_i_62_n_0\,
S(1) => \hcount[0]_i_63_n_0\,
S(0) => \hcount[0]_i_64_n_0\
);
\hcount_reg[0]_i_26\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_65_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[0]_i_26_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \NLW_hcount_reg[0]_i_26_O_UNCONNECTED\(3),
O(2) => \hcount_reg[0]_i_26_n_5\,
O(1) => \hcount_reg[0]_i_26_n_6\,
O(0) => \hcount_reg[0]_i_26_n_7\,
S(3) => '0',
S(2 downto 0) => \hcount_reg__0\(31 downto 29)
);
\hcount_reg[0]_i_28\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_69_n_0\,
CO(3) => \hcount_reg[0]_i_28_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_28_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_70_n_0\,
DI(2) => \hcount[0]_i_71_n_0\,
DI(1) => \hcount[0]_i_72_n_0\,
DI(0) => \hcount[0]_i_73_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_28_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_74_n_0\,
S(2) => \hcount[0]_i_75_n_0\,
S(1) => \hcount[0]_i_76_n_0\,
S(0) => \hcount[0]_i_77_n_0\
);
\hcount_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_12_n_0\,
CO(3) => \hcount_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_13_n_0\,
DI(2) => \hcount[0]_i_14_n_0\,
DI(1) => \hcount[0]_i_15_n_0\,
DI(0) => \hcount[0]_i_16_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_17_n_0\,
S(2) => \hcount[0]_i_18_n_0\,
S(1) => \hcount[0]_i_19_n_0\,
S(0) => \hcount[0]_i_20_n_0\
);
\hcount_reg[0]_i_37\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_79_n_0\,
CO(3) => \hcount_reg[0]_i_37_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_37_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_37_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_80_n_0\,
S(2) => \hcount[0]_i_81_n_0\,
S(1) => \hcount[0]_i_82_n_0\,
S(0) => \hcount[0]_i_83_n_0\
);
\hcount_reg[0]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_21_n_0\,
CO(3 downto 2) => \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\(3 downto 2),
CO(1) => \hcount_reg[0]_i_4_n_2\,
CO(0) => \NLW_hcount_reg[0]_i_4_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \hcount_reg[0]_i_22_n_5\,
DI(0) => '0',
O(3 downto 0) => \NLW_hcount_reg[0]_i_4_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => B"00",
S(1) => \hcount[0]_i_23_n_0\,
S(0) => \hcount[0]_i_24_n_0\
);
\hcount_reg[0]_i_41\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_84_n_0\,
CO(3) => \hcount_reg[0]_i_41_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_41_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_85_n_0\,
DI(2) => \hcount[0]_i_86_n_0\,
DI(1) => \hcount[0]_i_87_n_0\,
DI(0) => \hcount[0]_i_88_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_41_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_89_n_0\,
S(2) => \hcount[0]_i_90_n_0\,
S(1) => \hcount[0]_i_91_n_0\,
S(0) => \hcount[0]_i_92_n_0\
);
\hcount_reg[0]_i_5\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_25_n_0\,
CO(3 downto 1) => \NLW_hcount_reg[0]_i_5_CO_UNCONNECTED\(3 downto 1),
CO(0) => hcount18_in,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \hcount_reg[0]_i_26_n_5\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_5_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \hcount[0]_i_27_n_0\
);
\hcount_reg[0]_i_50\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_51_n_0\,
CO(3) => \hcount_reg[0]_i_50_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_50_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_50_n_4\,
O(2) => \hcount_reg[0]_i_50_n_5\,
O(1) => \hcount_reg[0]_i_50_n_6\,
O(0) => \hcount_reg[0]_i_50_n_7\,
S(3 downto 0) => \vcount_reg__0\(28 downto 25)
);
\hcount_reg[0]_i_51\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_93_n_0\,
CO(3) => \hcount_reg[0]_i_51_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_51_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_51_n_4\,
O(2) => \hcount_reg[0]_i_51_n_5\,
O(1) => \hcount_reg[0]_i_51_n_6\,
O(0) => \hcount_reg[0]_i_51_n_7\,
S(3 downto 0) => \vcount_reg__0\(24 downto 21)
);
\hcount_reg[0]_i_52\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_103_n_0\,
CO(3) => \hcount_reg[0]_i_52_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_52_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_52_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_104_n_0\,
S(2) => \hcount[0]_i_105_n_0\,
S(1) => \hcount[0]_i_106_n_0\,
S(0) => \hcount[0]_i_107_n_0\
);
\hcount_reg[0]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_28_n_0\,
CO(3) => hcount1,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_29_n_0\,
DI(2) => \hcount[0]_i_30_n_0\,
DI(1) => \hcount[0]_i_31_n_0\,
DI(0) => \hcount[0]_i_32_n_0\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_33_n_0\,
S(2) => \hcount[0]_i_34_n_0\,
S(1) => \hcount[0]_i_35_n_0\,
S(0) => \hcount[0]_i_36_n_0\
);
\hcount_reg[0]_i_60\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_108_n_0\,
CO(3) => \hcount_reg[0]_i_60_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_60_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_60_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_109_n_0\,
S(2) => \hcount[0]_i_110_n_0\,
S(1) => \hcount[0]_i_111_n_0\,
S(0) => \hcount[0]_i_112_n_0\
);
\hcount_reg[0]_i_65\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_78_n_0\,
CO(3) => \hcount_reg[0]_i_65_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_65_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_65_n_4\,
O(2) => \hcount_reg[0]_i_65_n_5\,
O(1) => \hcount_reg[0]_i_65_n_6\,
O(0) => \hcount_reg[0]_i_65_n_7\,
S(3 downto 0) => \hcount_reg__0\(28 downto 25)
);
\hcount_reg[0]_i_69\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_117_n_0\,
CO(3) => \hcount_reg[0]_i_69_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_69_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => \hcount[0]_i_118_n_0\,
DI(2) => \hcount[0]_i_119_n_0\,
DI(1) => \hcount[0]_i_120_n_0\,
DI(0) => '0',
O(3 downto 0) => \NLW_hcount_reg[0]_i_69_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_121_n_0\,
S(2) => \hcount[0]_i_122_n_0\,
S(1) => \hcount[0]_i_123_n_0\,
S(0) => \hcount[0]_i_124_n_0\
);
\hcount_reg[0]_i_7\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_37_n_0\,
CO(3) => \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\(3),
CO(2) => \hcount_reg[0]_i_7_n_1\,
CO(1 downto 0) => \NLW_hcount_reg[0]_i_7_CO_UNCONNECTED\(1 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_7_O_UNCONNECTED\(3 downto 0),
S(3) => '0',
S(2) => \hcount[0]_i_38_n_0\,
S(1) => \hcount[0]_i_39_n_0\,
S(0) => \hcount[0]_i_40_n_0\
);
\hcount_reg[0]_i_78\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_125_n_0\,
CO(3) => \hcount_reg[0]_i_78_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_78_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_78_n_4\,
O(2) => \hcount_reg[0]_i_78_n_5\,
O(1) => \hcount_reg[0]_i_78_n_6\,
O(0) => \hcount_reg[0]_i_78_n_7\,
S(3 downto 0) => \hcount_reg__0\(24 downto 21)
);
\hcount_reg[0]_i_79\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_79_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_79_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_hcount_reg[0]_i_79_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_131_n_0\,
S(2) => \hcount[0]_i_132_n_0\,
S(1) => \hcount[0]_i_133_n_0\,
S(0) => \hcount[0]_i_134_n_0\
);
\hcount_reg[0]_i_84\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \hcount_reg[0]_i_84_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_84_CO_UNCONNECTED\(2 downto 0),
CYINIT => '1',
DI(3) => \hcount[0]_i_136_n_0\,
DI(2) => \hcount[0]_i_137_n_0\,
DI(1) => '0',
DI(0) => \hcount_reg[0]_i_138_n_7\,
O(3 downto 0) => \NLW_hcount_reg[0]_i_84_O_UNCONNECTED\(3 downto 0),
S(3) => \hcount[0]_i_139_n_0\,
S(2) => \hcount[0]_i_140_n_0\,
S(1) => \hcount[0]_i_141_n_0\,
S(0) => \hcount[0]_i_142_n_0\
);
\hcount_reg[0]_i_93\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_94_n_0\,
CO(3) => \hcount_reg[0]_i_93_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_93_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_93_n_4\,
O(2) => \hcount_reg[0]_i_93_n_5\,
O(1) => \hcount_reg[0]_i_93_n_6\,
O(0) => \hcount_reg[0]_i_93_n_7\,
S(3 downto 0) => \vcount_reg__0\(20 downto 17)
);
\hcount_reg[0]_i_94\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_143_n_0\,
CO(3) => \hcount_reg[0]_i_94_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[0]_i_94_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[0]_i_94_n_4\,
O(2) => \hcount_reg[0]_i_94_n_5\,
O(1) => \hcount_reg[0]_i_94_n_6\,
O(0) => \hcount_reg[0]_i_94_n_7\,
S(3 downto 0) => \vcount_reg__0\(16 downto 13)
);
\hcount_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_5\,
Q => \hcount_reg__0\(10),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_4\,
Q => \hcount_reg__0\(11),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_7\,
Q => \hcount_reg__0\(12),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[8]_i_1_n_0\,
CO(3) => \hcount_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[12]_i_1_n_4\,
O(2) => \hcount_reg[12]_i_1_n_5\,
O(1) => \hcount_reg[12]_i_1_n_6\,
O(0) => \hcount_reg[12]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(15 downto 12)
);
\hcount_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_6\,
Q => \hcount_reg__0\(13),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_5\,
Q => \hcount_reg__0\(14),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[12]_i_1_n_4\,
Q => \hcount_reg__0\(15),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_7\,
Q => \hcount_reg__0\(16),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[12]_i_1_n_0\,
CO(3) => \hcount_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[16]_i_1_n_4\,
O(2) => \hcount_reg[16]_i_1_n_5\,
O(1) => \hcount_reg[16]_i_1_n_6\,
O(0) => \hcount_reg[16]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(19 downto 16)
);
\hcount_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_6\,
Q => \hcount_reg__0\(17),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_5\,
Q => \hcount_reg__0\(18),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[16]_i_1_n_4\,
Q => \hcount_reg__0\(19),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_6\,
Q => hcount_reg(1),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_7\,
Q => \hcount_reg__0\(20),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[16]_i_1_n_0\,
CO(3) => \hcount_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[20]_i_1_n_4\,
O(2) => \hcount_reg[20]_i_1_n_5\,
O(1) => \hcount_reg[20]_i_1_n_6\,
O(0) => \hcount_reg[20]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(23 downto 20)
);
\hcount_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_6\,
Q => \hcount_reg__0\(21),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_5\,
Q => \hcount_reg__0\(22),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[20]_i_1_n_4\,
Q => \hcount_reg__0\(23),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_7\,
Q => \hcount_reg__0\(24),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[20]_i_1_n_0\,
CO(3) => \hcount_reg[24]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[24]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[24]_i_1_n_4\,
O(2) => \hcount_reg[24]_i_1_n_5\,
O(1) => \hcount_reg[24]_i_1_n_6\,
O(0) => \hcount_reg[24]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(27 downto 24)
);
\hcount_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_6\,
Q => \hcount_reg__0\(25),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_5\,
Q => \hcount_reg__0\(26),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[24]_i_1_n_4\,
Q => \hcount_reg__0\(27),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_7\,
Q => \hcount_reg__0\(28),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[24]_i_1_n_0\,
CO(3 downto 0) => \NLW_hcount_reg[28]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[28]_i_1_n_4\,
O(2) => \hcount_reg[28]_i_1_n_5\,
O(1) => \hcount_reg[28]_i_1_n_6\,
O(0) => \hcount_reg[28]_i_1_n_7\,
S(3 downto 0) => \hcount_reg__0\(31 downto 28)
);
\hcount_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_6\,
Q => \hcount_reg__0\(29),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_5\,
Q => hcount_reg(2),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_5\,
Q => \hcount_reg__0\(30),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[28]_i_1_n_4\,
Q => \hcount_reg__0\(31),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[0]_i_2_n_4\,
Q => hcount_reg(3),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_7\,
Q => hcount_reg(4),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[0]_i_2_n_0\,
CO(3) => \hcount_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[4]_i_1_n_4\,
O(2) => \hcount_reg[4]_i_1_n_5\,
O(1) => \hcount_reg[4]_i_1_n_6\,
O(0) => \hcount_reg[4]_i_1_n_7\,
S(3 downto 0) => hcount_reg(7 downto 4)
);
\hcount_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_6\,
Q => hcount_reg(5),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_5\,
Q => hcount_reg(6),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[4]_i_1_n_4\,
Q => hcount_reg(7),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_7\,
Q => hcount_reg(8),
R => \hcount[0]_i_1_n_0\
);
\hcount_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \hcount_reg[4]_i_1_n_0\,
CO(3) => \hcount_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_hcount_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \hcount_reg[8]_i_1_n_4\,
O(2) => \hcount_reg[8]_i_1_n_5\,
O(1) => \hcount_reg[8]_i_1_n_6\,
O(0) => \hcount_reg[8]_i_1_n_7\,
S(3 downto 2) => \hcount_reg__0\(11 downto 10),
S(1 downto 0) => hcount_reg(9 downto 8)
);
\hcount_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => \hcount_reg[8]_i_1_n_6\,
Q => hcount_reg(9),
R => \hcount[0]_i_1_n_0\
);
hsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => hsync_OBUF,
O => hsync
);
hsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8888888"
)
port map (
I0 => hsync_OBUF,
I1 => rst_IBUF,
I2 => hsync_i_2_n_0,
I3 => hsync_i_3_n_0,
I4 => hsync_i_4_n_0,
O => hsync_i_1_n_0
);
hsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => hsync_i_5_n_0,
I1 => hsync_i_6_n_0,
I2 => hsync_i_7_n_0,
I3 => hcount_reg(2),
I4 => hcount_reg(1),
I5 => hcount_reg(0),
O => hsync_i_2_n_0
);
hsync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(29),
I1 => \hcount_reg__0\(30),
I2 => \hcount_reg__0\(27),
I3 => \hcount_reg__0\(28),
I4 => rst_IBUF,
I5 => \hcount_reg__0\(31),
O => hsync_i_3_n_0
);
hsync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(23),
I1 => \hcount_reg__0\(24),
I2 => \hcount_reg__0\(21),
I3 => \hcount_reg__0\(22),
I4 => \hcount_reg__0\(26),
I5 => \hcount_reg__0\(25),
O => hsync_i_4_n_0
);
hsync_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(11),
I1 => \hcount_reg__0\(12),
I2 => hcount_reg(9),
I3 => \hcount_reg__0\(10),
I4 => \hcount_reg__0\(14),
I5 => \hcount_reg__0\(13),
O => hsync_i_5_n_0
);
hsync_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \hcount_reg__0\(17),
I1 => \hcount_reg__0\(18),
I2 => \hcount_reg__0\(15),
I3 => \hcount_reg__0\(16),
I4 => \hcount_reg__0\(20),
I5 => \hcount_reg__0\(19),
O => hsync_i_6_n_0
);
hsync_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => hcount_reg(5),
I1 => hcount_reg(6),
I2 => hcount_reg(3),
I3 => hcount_reg(4),
I4 => hcount_reg(8),
I5 => hcount_reg(7),
O => hsync_i_7_n_0
);
hsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => hsync_i_1_n_0,
Q => hsync_OBUF,
R => '0'
);
rst_IBUF_inst: unisim.vcomponents.IBUF
port map (
I => rst,
O => rst_IBUF
);
\vcount[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => \hcount_reg[0]_i_4_n_2\,
I1 => hcount18_in,
I2 => \hcount_reg[0]_i_3_n_0\,
I3 => hcount1,
I4 => \hcount_reg[0]_i_7_n_1\,
I5 => rst_IBUF,
O => \vcount[0]_i_1_n_0\
);
\vcount[0]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => hcount18_in,
I1 => hcount1,
I2 => \hcount_reg[0]_i_7_n_1\,
O => \vcount[0]_i_2_n_0\
);
\vcount[0]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(0),
O => \vcount[0]_i_7_n_0\
);
\vcount_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_7\,
Q => vcount_reg(0),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[0]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \vcount_reg[0]_i_3_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[0]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0001",
O(3) => \vcount_reg[0]_i_3_n_4\,
O(2) => \vcount_reg[0]_i_3_n_5\,
O(1) => \vcount_reg[0]_i_3_n_6\,
O(0) => \vcount_reg[0]_i_3_n_7\,
S(3 downto 1) => vcount_reg(3 downto 1),
S(0) => \vcount[0]_i_7_n_0\
);
\vcount_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_5\,
Q => \vcount_reg__0\(10),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_4\,
Q => \vcount_reg__0\(11),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_7\,
Q => \vcount_reg__0\(12),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[12]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[8]_i_1_n_0\,
CO(3) => \vcount_reg[12]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[12]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[12]_i_1_n_4\,
O(2) => \vcount_reg[12]_i_1_n_5\,
O(1) => \vcount_reg[12]_i_1_n_6\,
O(0) => \vcount_reg[12]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(15 downto 12)
);
\vcount_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_6\,
Q => \vcount_reg__0\(13),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_5\,
Q => \vcount_reg__0\(14),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[12]_i_1_n_4\,
Q => \vcount_reg__0\(15),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_7\,
Q => \vcount_reg__0\(16),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[16]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[12]_i_1_n_0\,
CO(3) => \vcount_reg[16]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[16]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[16]_i_1_n_4\,
O(2) => \vcount_reg[16]_i_1_n_5\,
O(1) => \vcount_reg[16]_i_1_n_6\,
O(0) => \vcount_reg[16]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(19 downto 16)
);
\vcount_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_6\,
Q => \vcount_reg__0\(17),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_5\,
Q => \vcount_reg__0\(18),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[16]_i_1_n_4\,
Q => \vcount_reg__0\(19),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_6\,
Q => vcount_reg(1),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_7\,
Q => \vcount_reg__0\(20),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[20]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[16]_i_1_n_0\,
CO(3) => \vcount_reg[20]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[20]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[20]_i_1_n_4\,
O(2) => \vcount_reg[20]_i_1_n_5\,
O(1) => \vcount_reg[20]_i_1_n_6\,
O(0) => \vcount_reg[20]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(23 downto 20)
);
\vcount_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_6\,
Q => \vcount_reg__0\(21),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_5\,
Q => \vcount_reg__0\(22),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[20]_i_1_n_4\,
Q => \vcount_reg__0\(23),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_7\,
Q => \vcount_reg__0\(24),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[24]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[20]_i_1_n_0\,
CO(3) => \vcount_reg[24]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[24]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[24]_i_1_n_4\,
O(2) => \vcount_reg[24]_i_1_n_5\,
O(1) => \vcount_reg[24]_i_1_n_6\,
O(0) => \vcount_reg[24]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(27 downto 24)
);
\vcount_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_6\,
Q => \vcount_reg__0\(25),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_5\,
Q => \vcount_reg__0\(26),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[24]_i_1_n_4\,
Q => \vcount_reg__0\(27),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_7\,
Q => \vcount_reg__0\(28),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[28]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[24]_i_1_n_0\,
CO(3 downto 0) => \NLW_vcount_reg[28]_i_1_CO_UNCONNECTED\(3 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[28]_i_1_n_4\,
O(2) => \vcount_reg[28]_i_1_n_5\,
O(1) => \vcount_reg[28]_i_1_n_6\,
O(0) => \vcount_reg[28]_i_1_n_7\,
S(3 downto 0) => \vcount_reg__0\(31 downto 28)
);
\vcount_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_6\,
Q => \vcount_reg__0\(29),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_5\,
Q => vcount_reg(2),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_5\,
Q => \vcount_reg__0\(30),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[28]_i_1_n_4\,
Q => \vcount_reg__0\(31),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[0]_i_3_n_4\,
Q => vcount_reg(3),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_7\,
Q => vcount_reg(4),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[0]_i_3_n_0\,
CO(3) => \vcount_reg[4]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[4]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[4]_i_1_n_4\,
O(2) => \vcount_reg[4]_i_1_n_5\,
O(1) => \vcount_reg[4]_i_1_n_6\,
O(0) => \vcount_reg[4]_i_1_n_7\,
S(3 downto 0) => vcount_reg(7 downto 4)
);
\vcount_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_6\,
Q => vcount_reg(5),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_5\,
Q => vcount_reg(6),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[4]_i_1_n_4\,
Q => vcount_reg(7),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_7\,
Q => vcount_reg(8),
R => \vcount[0]_i_1_n_0\
);
\vcount_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \vcount_reg[4]_i_1_n_0\,
CO(3) => \vcount_reg[8]_i_1_n_0\,
CO(2 downto 0) => \NLW_vcount_reg[8]_i_1_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \vcount_reg[8]_i_1_n_4\,
O(2) => \vcount_reg[8]_i_1_n_5\,
O(1) => \vcount_reg[8]_i_1_n_6\,
O(0) => \vcount_reg[8]_i_1_n_7\,
S(3 downto 2) => \vcount_reg__0\(11 downto 10),
S(1 downto 0) => vcount_reg(9 downto 8)
);
\vcount_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => \vcount[0]_i_2_n_0\,
D => \vcount_reg[8]_i_1_n_6\,
Q => vcount_reg(9),
R => \vcount[0]_i_1_n_0\
);
vsync_OBUF_inst: unisim.vcomponents.OBUF
port map (
I => vsync_OBUF,
O => vsync
);
vsync_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"F8888888"
)
port map (
I0 => vsync_OBUF,
I1 => rst_IBUF,
I2 => vsync_i_2_n_0,
I3 => vsync_i_3_n_0,
I4 => vsync_i_4_n_0,
O => vsync_i_1_n_0
);
vsync_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000080"
)
port map (
I0 => vsync_i_5_n_0,
I1 => vsync_i_6_n_0,
I2 => vsync_i_7_n_0,
I3 => vcount_reg(2),
I4 => vcount_reg(1),
I5 => vcount_reg(0),
O => vsync_i_2_n_0
);
vsync_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(29),
I1 => \vcount_reg__0\(30),
I2 => \vcount_reg__0\(27),
I3 => \vcount_reg__0\(28),
I4 => rst_IBUF,
I5 => \vcount_reg__0\(31),
O => vsync_i_3_n_0
);
vsync_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(23),
I1 => \vcount_reg__0\(24),
I2 => \vcount_reg__0\(21),
I3 => \vcount_reg__0\(22),
I4 => \vcount_reg__0\(26),
I5 => \vcount_reg__0\(25),
O => vsync_i_4_n_0
);
vsync_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(11),
I1 => \vcount_reg__0\(12),
I2 => vcount_reg(9),
I3 => \vcount_reg__0\(10),
I4 => \vcount_reg__0\(14),
I5 => \vcount_reg__0\(13),
O => vsync_i_5_n_0
);
vsync_i_6: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \vcount_reg__0\(17),
I1 => \vcount_reg__0\(18),
I2 => \vcount_reg__0\(15),
I3 => \vcount_reg__0\(16),
I4 => \vcount_reg__0\(20),
I5 => \vcount_reg__0\(19),
O => vsync_i_6_n_0
);
vsync_i_7: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => vcount_reg(5),
I1 => vcount_reg(6),
I2 => vcount_reg(3),
I3 => vcount_reg(4),
I4 => vcount_reg(8),
I5 => vcount_reg(7),
O => vsync_i_7_n_0
);
vsync_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => '1',
D => vsync_i_1_n_0,
Q => vsync_OBUF,
R => '0'
);
\xaddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
I1 => \xaddr_reg[9]_i_3_n_3\,
O => \xaddr[9]_i_1_n_0\
);
\xaddr[9]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(22),
I1 => \hcount_reg__0\(23),
O => \xaddr[9]_i_10_n_0\
);
\xaddr[9]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(20),
I1 => \hcount_reg__0\(21),
O => \xaddr[9]_i_12_n_0\
);
\xaddr[9]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(18),
I1 => \hcount_reg__0\(19),
O => \xaddr[9]_i_13_n_0\
);
\xaddr[9]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(16),
I1 => \hcount_reg__0\(17),
O => \xaddr[9]_i_14_n_0\
);
\xaddr[9]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(14),
I1 => \hcount_reg__0\(15),
O => \xaddr[9]_i_15_n_0\
);
\xaddr[9]_i_16\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(9),
O => \xaddr[9]_i_16_n_0\
);
\xaddr[9]_i_17\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => hcount_reg(7),
O => \xaddr[9]_i_17_n_0\
);
\xaddr[9]_i_18\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(12),
I1 => \hcount_reg__0\(13),
O => \xaddr[9]_i_18_n_0\
);
\xaddr[9]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(10),
I1 => \hcount_reg__0\(11),
O => \xaddr[9]_i_19_n_0\
);
\xaddr[9]_i_2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
O => p_0_in
);
\xaddr[9]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(9),
I1 => hcount_reg(8),
O => \xaddr[9]_i_20_n_0\
);
\xaddr[9]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => hcount_reg(7),
I1 => hcount_reg(6),
O => \xaddr[9]_i_21_n_0\
);
\xaddr[9]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(30),
I1 => \hcount_reg__0\(31),
O => \xaddr[9]_i_5_n_0\
);
\xaddr[9]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(28),
I1 => \hcount_reg__0\(29),
O => \xaddr[9]_i_7_n_0\
);
\xaddr[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(26),
I1 => \hcount_reg__0\(27),
O => \xaddr[9]_i_8_n_0\
);
\xaddr[9]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \hcount_reg__0\(24),
I1 => \hcount_reg__0\(25),
O => \xaddr[9]_i_9_n_0\
);
\xaddr_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(0),
O => xaddr(0)
);
\xaddr_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(1),
O => xaddr(1)
);
\xaddr_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(2),
O => xaddr(2)
);
\xaddr_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(3),
O => xaddr(3)
);
\xaddr_OBUF[4]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(4),
O => xaddr(4)
);
\xaddr_OBUF[5]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(5),
O => xaddr(5)
);
\xaddr_OBUF[6]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(6),
O => xaddr(6)
);
\xaddr_OBUF[7]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(7),
O => xaddr(7)
);
\xaddr_OBUF[8]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(8),
O => xaddr(8)
);
\xaddr_OBUF[9]_inst\: unisim.vcomponents.OBUF
port map (
I => xaddr_OBUF(9),
O => xaddr(9)
);
\xaddr_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(0),
Q => xaddr_OBUF(0),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(1),
Q => xaddr_OBUF(1),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(2),
Q => xaddr_OBUF(2),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(3),
Q => xaddr_OBUF(3),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(4),
Q => xaddr_OBUF(4),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(5),
Q => xaddr_OBUF(5),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(6),
Q => xaddr_OBUF(6),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(7),
Q => xaddr_OBUF(7),
R => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(8),
Q => xaddr_OBUF(8),
R => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => hcount_reg(9),
Q => xaddr_OBUF(9),
S => \xaddr[9]_i_1_n_0\
);
\xaddr_reg[9]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \xaddr_reg[9]_i_11_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_11_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \xaddr[9]_i_16_n_0\,
DI(0) => \xaddr[9]_i_17_n_0\,
O(3 downto 0) => \NLW_xaddr_reg[9]_i_11_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_18_n_0\,
S(2) => \xaddr[9]_i_19_n_0\,
S(1) => \xaddr[9]_i_20_n_0\,
S(0) => \xaddr[9]_i_21_n_0\
);
\xaddr_reg[9]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_4_n_0\,
CO(3 downto 1) => \NLW_xaddr_reg[9]_i_3_CO_UNCONNECTED\(3 downto 1),
CO(0) => \xaddr_reg[9]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 1) => B"000",
DI(0) => \hcount_reg__0\(31),
O(3 downto 0) => \NLW_xaddr_reg[9]_i_3_O_UNCONNECTED\(3 downto 0),
S(3 downto 1) => B"000",
S(0) => \xaddr[9]_i_5_n_0\
);
\xaddr_reg[9]_i_4\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_6_n_0\,
CO(3) => \xaddr_reg[9]_i_4_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_4_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_xaddr_reg[9]_i_4_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_7_n_0\,
S(2) => \xaddr[9]_i_8_n_0\,
S(1) => \xaddr[9]_i_9_n_0\,
S(0) => \xaddr[9]_i_10_n_0\
);
\xaddr_reg[9]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \xaddr_reg[9]_i_11_n_0\,
CO(3) => \xaddr_reg[9]_i_6_n_0\,
CO(2 downto 0) => \NLW_xaddr_reg[9]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_xaddr_reg[9]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \xaddr[9]_i_12_n_0\,
S(2) => \xaddr[9]_i_13_n_0\,
S(1) => \xaddr[9]_i_14_n_0\,
S(0) => \xaddr[9]_i_15_n_0\
);
\yaddr[9]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => rst_IBUF,
I1 => \yaddr_reg[9]_i_2_n_2\,
O => \yaddr[9]_i_1_n_0\
);
\yaddr[9]_i_10\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(20),
I1 => \vcount_reg__0\(21),
O => \yaddr[9]_i_10_n_0\
);
\yaddr[9]_i_12\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(18),
I1 => \vcount_reg__0\(19),
O => \yaddr[9]_i_12_n_0\
);
\yaddr[9]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(16),
I1 => \vcount_reg__0\(17),
O => \yaddr[9]_i_13_n_0\
);
\yaddr[9]_i_14\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(14),
I1 => \vcount_reg__0\(15),
O => \yaddr[9]_i_14_n_0\
);
\yaddr[9]_i_15\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(12),
I1 => \vcount_reg__0\(13),
O => \yaddr[9]_i_15_n_0\
);
\yaddr[9]_i_16\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(8),
I1 => vcount_reg(9),
O => \yaddr[9]_i_16_n_0\
);
\yaddr[9]_i_17\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => vcount_reg(6),
I1 => vcount_reg(7),
O => \yaddr[9]_i_17_n_0\
);
\yaddr[9]_i_18\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => vcount_reg(5),
O => \yaddr[9]_i_18_n_0\
);
\yaddr[9]_i_19\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(10),
I1 => \vcount_reg__0\(11),
O => \yaddr[9]_i_19_n_0\
);
\yaddr[9]_i_20\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => vcount_reg(8),
I1 => vcount_reg(9),
O => \yaddr[9]_i_20_n_0\
);
\yaddr[9]_i_21\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => vcount_reg(6),
I1 => vcount_reg(7),
O => \yaddr[9]_i_21_n_0\
);
\yaddr[9]_i_22\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => vcount_reg(5),
I1 => vcount_reg(4),
O => \yaddr[9]_i_22_n_0\
);
\yaddr[9]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(30),
I1 => \vcount_reg__0\(31),
O => \yaddr[9]_i_4_n_0\
);
\yaddr[9]_i_5\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(28),
I1 => \vcount_reg__0\(29),
O => \yaddr[9]_i_5_n_0\
);
\yaddr[9]_i_7\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(26),
I1 => \vcount_reg__0\(27),
O => \yaddr[9]_i_7_n_0\
);
\yaddr[9]_i_8\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(24),
I1 => \vcount_reg__0\(25),
O => \yaddr[9]_i_8_n_0\
);
\yaddr[9]_i_9\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \vcount_reg__0\(22),
I1 => \vcount_reg__0\(23),
O => \yaddr[9]_i_9_n_0\
);
\yaddr_OBUF[0]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(0),
O => yaddr(0)
);
\yaddr_OBUF[1]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(1),
O => yaddr(1)
);
\yaddr_OBUF[2]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(2),
O => yaddr(2)
);
\yaddr_OBUF[3]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(3),
O => yaddr(3)
);
\yaddr_OBUF[4]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(4),
O => yaddr(4)
);
\yaddr_OBUF[5]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(5),
O => yaddr(5)
);
\yaddr_OBUF[6]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(6),
O => yaddr(6)
);
\yaddr_OBUF[7]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(7),
O => yaddr(7)
);
\yaddr_OBUF[8]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(8),
O => yaddr(8)
);
\yaddr_OBUF[9]_inst\: unisim.vcomponents.OBUF
port map (
I => yaddr_OBUF(9),
O => yaddr(9)
);
\yaddr_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(0),
Q => yaddr_OBUF(0),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(1),
Q => yaddr_OBUF(1),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(2),
Q => yaddr_OBUF(2),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(3),
Q => yaddr_OBUF(3),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(4),
Q => yaddr_OBUF(4),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(5),
Q => yaddr_OBUF(5),
R => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(6),
Q => yaddr_OBUF(6),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(7),
Q => yaddr_OBUF(7),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(8),
Q => yaddr_OBUF(8),
S => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => clk_25_IBUF_BUFG,
CE => p_0_in,
D => vcount_reg(9),
Q => yaddr_OBUF(9),
R => \yaddr[9]_i_1_n_0\
);
\yaddr_reg[9]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \yaddr_reg[9]_i_11_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_11_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3) => '0',
DI(2) => \yaddr[9]_i_16_n_0\,
DI(1) => \yaddr[9]_i_17_n_0\,
DI(0) => \yaddr[9]_i_18_n_0\,
O(3 downto 0) => \NLW_yaddr_reg[9]_i_11_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_19_n_0\,
S(2) => \yaddr[9]_i_20_n_0\,
S(1) => \yaddr[9]_i_21_n_0\,
S(0) => \yaddr[9]_i_22_n_0\
);
\yaddr_reg[9]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_3_n_0\,
CO(3 downto 2) => \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\(3 downto 2),
CO(1) => \yaddr_reg[9]_i_2_n_2\,
CO(0) => \NLW_yaddr_reg[9]_i_2_CO_UNCONNECTED\(0),
CYINIT => '0',
DI(3 downto 2) => B"00",
DI(1) => \vcount_reg__0\(31),
DI(0) => '0',
O(3 downto 0) => \NLW_yaddr_reg[9]_i_2_O_UNCONNECTED\(3 downto 0),
S(3 downto 2) => B"00",
S(1) => \yaddr[9]_i_4_n_0\,
S(0) => \yaddr[9]_i_5_n_0\
);
\yaddr_reg[9]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_6_n_0\,
CO(3) => \yaddr_reg[9]_i_3_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_3_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_yaddr_reg[9]_i_3_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_7_n_0\,
S(2) => \yaddr[9]_i_8_n_0\,
S(1) => \yaddr[9]_i_9_n_0\,
S(0) => \yaddr[9]_i_10_n_0\
);
\yaddr_reg[9]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \yaddr_reg[9]_i_11_n_0\,
CO(3) => \yaddr_reg[9]_i_6_n_0\,
CO(2 downto 0) => \NLW_yaddr_reg[9]_i_6_CO_UNCONNECTED\(2 downto 0),
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \NLW_yaddr_reg[9]_i_6_O_UNCONNECTED\(3 downto 0),
S(3) => \yaddr[9]_i_12_n_0\,
S(2) => \yaddr[9]_i_13_n_0\,
S(1) => \yaddr[9]_i_14_n_0\,
S(0) => \yaddr[9]_i_15_n_0\
);
end STRUCTURE;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity spi_accel is
Port ( clk100MHz : in STD_LOGIC;
masterReset : in STD_LOGIC;
CS : out STD_LOGIC;
SCLK : out STD_LOGIC;
MOSI : out STD_LOGIC;
MISO : in STD_LOGIC;
READY : inout STD_LOGIC;
X_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Y_VAL : out STD_LOGIC_VECTOR(7 downto 0);
Z_VAL : out STD_LOGIC_VECTOR(7 downto 0));
end spi_accel;
architecture Behavioral of spi_accel is
constant READ_CMD : std_logic_vector (7 downto 0) := x"0B";
constant WRITE_CMD : std_logic_vector (7 downto 0) := x"0A";
constant POWER_CTL_REG : std_logic_vector (7 downto 0) := x"2D";
constant POWER_CTL_VAL : std_logic_vector (7 downto 0) := x"02";
--"01000000";
--"01010000"
--Can use burst read
constant X_REG : std_logic_vector (7 downto 0) := x"08";
signal X_VAL_R: std_logic_vector (7 downto 0) := (others => '0');
constant Y_REG : std_logic_vector (7 downto 0) := x"09";
signal Y_VAL_R: std_logic_vector (7 downto 0) := (others => '0');
constant Z_REG : std_logic_vector (7 downto 0) := x"0A";
signal Z_VAL_R: std_logic_vector (7 downto 0) := (others => '0');
--signal CS : std_logic := '1';
--signal MOSI : std_logic := '0';
--signal MISO : std_logic := '0';
--Initialise Finished -> READY
--signal READY : std_logic := '0';
signal byteCounter : integer range 0 to 7 := 7;
signal byteCounter_delayed : integer range 0 to 7 := 0;
--Intialiser FSM
type SPI_FSM is (CMD, PWR_REG, VAL, DONE, CMD_R, ACC_REG, VAL_ACC, IDLE);
signal SPI_STATE : SPI_FSM := CMD;
signal SPI_STATE_DEBUG : SPI_FSM := CMD;
--Burst Read Accel FSM
type BURST_FSM is (X_VAL_S, Y_VAL_S, Z_VAL_S);
signal BURST_STATE : BURST_FSM := X_VAL_S;
signal BURST_STATE_DEBUG : BURST_FSM := X_VAL_S;
--Clk Scaled Signals
signal clk3Hz : std_logic := '0';
signal clk1MHz : std_logic := '0';
signal clockScalers : std_logic_vector (26 downto 0) := (others => '0');
--Edge Detector
signal clkEdge : std_logic := '0';
type DETECT_FSM is (WAITING, DELAY1, DELAY2);
signal DETECT_STATE : DETECT_FSM := WAITING;
BEGIN
--1MHz Scalar SPI SCLK
--process (masterReset,clk100Mhz)
-- variable wdCounter : std_logic_vector (7 downto 0) := (others => '0');
-- begin
-- if (masterReset = '1') then
-- wdCounter := "00000000";
-- elsif (clk100Mhz'event and clk100Mhz = '1') then
-- wdCounter := wdCounter + '1';
-- if (wdCounter = "00000111") then
-- clk1Mhz <= not(clk1Mhz);
-- wdCounter := "00000000";
-- end if;
-- end if;
--end process;
--300ms watchdog timer
process (masterReset, clk1Mhz)
--Falling edge detector
begin
if (masterReset = '1') then
clk3Hz <= '0';
clkEdge <= '0';
DETECT_STATE <= WAITING;
elsif ( clk1Mhz'event and clk1Mhz = '0') then
if(clkEdge = '1' and clockScalers(24) = '0') then
DETECT_STATE <= DELAY1;
clk3Hz <= '1';
else
case DETECT_STATE is
when DELAY1 => DETECT_STATE <= DELAY2;
when DELAY2 =>
if (READY = '0') then
DETECT_STATE <= WAITING;
end if;
when WAITING =>
clk3Hz <= '0';
end case;
end if;
clkEdge <= clockScalers(24);
end if;
end process;
process (clk100Mhz, masterReset) begin
if (masterReset = '1') then
clockScalers <= "000000000000000000000000000";
elsif (clk100mhz'event and clk100mhz = '1')then
clockScalers <= clockScalers + '1';
end if;
end process;
clk1Mhz <= clockScalers(5);
--SCLK <= not(clk1Mhz);
SCLK <= (clk1Mhz);
READY <= '1' when ( (SPI_STATE_DEBUG = IDLE) or (SPI_STATE_DEBUG = DONE) ) else '0';
X_VAL <= X_VAL_R;
Y_VAL <= Y_VAL_R;
Z_VAL <= Z_VAL_R;
--SPI FSM LOOP
process (masterReset, clk1Mhz) begin
if (masterReset = '1') then
CS <= '1';
SPI_STATE <= CMD;
BURST_STATE <= X_VAL_S;
byteCounter <= 7;
X_VAL_R <= (others => '0');
Y_VAL_R <= (others => '0');
Z_VAL_R <= (others => '0');
elsif (clk1Mhz'event and clk1Mhz = '0') then
--FSM Sent Data loop
case SPI_STATE is
when CMD =>
CS <= '0';
MOSI <= WRITE_CMD(byteCounter);
when PWR_REG =>
CS <= '0';
MOSI <= POWER_CTL_REG(byteCounter);
when VAL =>
CS <= '0';
MOSI <= POWER_CTL_VAL(byteCounter);
when CMD_R =>
CS <= '0';
MOSI <= READ_CMD(byteCounter);
when ACC_REG =>
CS <= '0';
MOSI <= X_REG(byteCounter);
when VAL_ACC =>
CS <= '0';
MOSI <= '1';
--Burst FSM Read/Load
case BURST_STATE_DEBUG is
when X_VAl_S =>
--X_VAL_R(byteCounter) <= MISO;
X_VAL_R(byteCounter_delayed) <= MISO;
when Y_VAl_S =>
--Y_VAL_R(byteCounter) <= MISO;
Y_VAL_R(byteCounter_delayed) <= MISO;
when Z_VAl_S =>
--Z_VAL_R(byteCounter) <= MISO;
Z_VAL_R(byteCounter_delayed) <= MISO;
end case;
when others =>
if (BURST_STATE_DEBUG = Z_VAL_S) then
Z_VAL_R(0) <= MISO;
end if;
CS <= '1';
MOSI <= '0';
end case;
if (byteCounter = 0) then
--Secondary FSM Switch/Transition Loop
case SPI_STATE is
when CMD => SPI_STATE <= PWR_REG;
when PWR_REG => SPI_STATE <= VAL;
when VAL => SPI_STATE <= DONE;
when DONE =>
cs <= '1';
if (clk3Hz = '1') then
SPI_STATE <= CMD_R;
end if;
when CMD_R => SPI_STATE <= ACC_REG;
when ACC_REG => SPI_STATE <= VAL_ACC;
when VAL_ACC =>
--Only Transition on Burst FSM
if (BURST_STATE = Z_VAL_S) then
SPI_STATE <= IDLE;
end if;
case BURST_STATE is
when X_VAl_S => BURST_STATE <= Y_VAL_S;
when Y_VAl_S => BURST_STATE <= Z_VAL_S;
when Z_VAl_S => BURST_STATE <= X_VAL_S;
end case;
when IDLE =>
cs <= '1';
if (clk3Hz = '1') then
SPI_STATE <= CMD_R;
end if;
end case;
byteCounter <= 7;
else
byteCounter <= byteCounter - 1;
end if;
end if;
end process;
--Delayed Clock
process (masterReset, clk1Mhz) begin
if (masterReset = '1') then
byteCounter_delayed <= 0;
SPI_STATE_DEBUG <= CMD;
BURST_STATE_DEBUG <= X_VAL_S;
elsif (clk1Mhz'event and clk1Mhz = '0') then
byteCounter_delayed <= byteCounter;
SPI_STATE_DEBUG <= SPI_STATE;
BURST_STATE_DEBUG <= BURST_STATE;
end if;
end process;
END Behavioral;
|
--
-- \file ppc405_top.vhd
--
-- PowerPC wrapper to connect CPU to OSIF
--
-- \author robert Meiche <rmeiche@gmx.de>
-- \date 22.09.2009
--
-----------------------------------------------------------------------------
-- %%%RECONOS_COPYRIGHT_BEGIN%%%
--
-- This file is part of ReconOS (http://www.reconos.de).
-- Copyright (c) 2006-2010 The ReconOS Project and contributors (see AUTHORS).
-- All rights reserved.
--
-- ReconOS is free software: you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- ReconOS is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-- FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
-- details.
--
-- You should have received a copy of the GNU General Public License along
-- with ReconOS. If not, see <http://www.gnu.org/licenses/>.
--
-- %%%RECONOS_COPYRIGHT_END%%%
-----------------------------------------------------------------------------
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library ppc405_v2_00_c;
use ppc405_v2_00_c.all;
library dcr_v29_v1_00_a;
use dcr_v29_v1_00_a.all;
library cpu_osif_adapter_v1_04_a;
use cpu_osif_adapter_v1_04_a.all;
library reconos_v2_01_a;
use reconos_v2_01_a.reconos_pkg.ALL;
entity ppc405_top is
generic (
C_EXT_RESET_HIGH : integer := 1;
CPU_USE_OTHER_CLK : integer := 0;
CPU_RESET_CYCLES : integer := 8;
CPU_MMU_ENABLE : integer := 1;
CPU_DCR_RESYNC : integer := 0;
C_BOOT_SECT_DATA : std_logic_vector := X"4bffd004"
);
port (
clk : in std_logic; --clock from OSIF
cpu_clk : in std_logic; -- Other clock from extern. Configurable via generic
reset : in std_logic;
--signals to osif
i_osif_flat : in std_logic_vector;
o_osif_flat : out std_logic_vector;
--debug signals
debug_idle_state : out std_logic;
debug_busy_state : out std_logic;
debug_reconos_ready : out std_logic;
--signal to/from bram_logic
boot_sect_ready : in std_logic;
set_boot_sect : out std_logic;
boot_sect_data : out std_logic_vector(31 downto 0);
--CPU PLB ports
PLBCLK : in std_logic;
C405PLBICUABUS : out std_logic_vector(0 to 31);
C405PLBICUBE : out std_logic_vector(0 to 7);
C405PLBICURNW : out std_logic;
C405PLBICUABORT : out std_logic;
C405PLBICUBUSLOCK : out std_logic;
C405PLBICUU0ATTR : out std_logic;
C405PLBICUGUARDED : out std_logic;
C405PLBICULOCKERR : out std_logic;
C405PLBICUMSIZE : out std_logic_vector(0 to 1);
C405PLBICUORDERED : out std_logic;
C405PLBICUPRIORITY : out std_logic_vector(0 to 1);
C405PLBICURDBURST : out std_logic;
C405PLBICUREQUEST : out std_logic;
C405PLBICUSIZE : out std_logic_vector(0 to 3);
C405PLBICUTYPE : out std_logic_vector(0 to 2);
C405PLBICUWRBURST : out std_logic;
C405PLBICUWRDBUS : out std_logic_vector(0 to 63);
C405PLBICUCACHEABLE : out std_logic;
PLBC405ICUADDRACK : in std_logic;
PLBC405ICUBUSY : in std_logic;
PLBC405ICUERR : in std_logic;
PLBC405ICURDBTERM : in std_logic;
PLBC405ICURDDACK : in std_logic;
PLBC405ICURDDBUS : in std_logic_vector(0 to 63);
PLBC405ICURDWDADDR : in std_logic_vector(0 to 3);
PLBC405ICUREARBITRATE : in std_logic;
PLBC405ICUWRBTERM : in std_logic;
PLBC405ICUWRDACK : in std_logic;
PLBC405ICUSSIZE : in std_logic_vector(0 to 1);
PLBC405ICUSERR : in std_logic;
PLBC405ICUSBUSYS : in std_logic;
C405PLBDCUABUS : out std_logic_vector(0 to 31);
C405PLBDCUBE : out std_logic_vector(0 to 7);
C405PLBDCURNW : out std_logic;
C405PLBDCUSIZE2 : out std_logic;
C405PLBDCUABORT : out std_logic;
C405PLBDCUBUSLOCK : out std_logic;
C405PLBDCUU0ATTR : out std_logic;
C405PLBDCUGUARDED : out std_logic;
C405PLBDCULOCKERR : out std_logic;
C405PLBDCUMSIZE : out std_logic_vector(0 to 1);
C405PLBDCUORDERED : out std_logic;
C405PLBDCUPRIORITY : out std_logic_vector(0 to 1);
C405PLBDCURDBURST : out std_logic;
C405PLBDCUREQUEST : out std_logic;
C405PLBDCUSIZE : out std_logic_vector(0 to 3);
C405PLBDCUTYPE : out std_logic_vector(0 to 2);
C405PLBDCUWRBURST : out std_logic;
C405PLBDCUWRDBUS : out std_logic_vector(0 to 63);
C405PLBDCUCACHEABLE : out std_logic;
C405PLBDCUWRITETHRU : out std_logic;
PLBC405DCUADDRACK : in std_logic;
PLBC405DCUBUSY : in std_logic;
PLBC405DCUERR : in std_logic;
PLBC405DCURDBTERM : in std_logic;
PLBC405DCURDDACK : in std_logic;
PLBC405DCURDDBUS : in std_logic_vector(0 to 63);
PLBC405DCURDWDADDR : in std_logic_vector(0 to 3);
PLBC405DCUREARBITRATE : in std_logic;
PLBC405DCUWRBTERM : in std_logic;
PLBC405DCUWRDACK : in std_logic;
PLBC405DCUSSIZE : in std_logic_vector(0 to 1);
PLBC405DCUSERR : in std_logic;
PLBC405DCUSBUSYS : in std_logic;
--OCM
BRAMDSOCMCLK : in std_logic;
BRAMDSOCMRDDBUS : in std_logic_vector(0 to 31);
DSARCVALUE : in std_logic_vector(0 to 7);
DSCNTLVALUE : in std_logic_vector(0 to 7);
DSOCMBRAMABUS : out std_logic_vector(8 to 29);
DSOCMBRAMBYTEWRITE : out std_logic_vector(0 to 3);
DSOCMBRAMEN : out std_logic;
DSOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
DSOCMBUSY : out std_logic;
BRAMISOCMCLK : in std_logic;
BRAMISOCMRDDBUS : in std_logic_vector(0 to 63);
ISARCVALUE : in std_logic_vector(0 to 7);
ISCNTLVALUE : in std_logic_vector(0 to 7);
ISOCMBRAMEN : out std_logic;
ISOCMBRAMEVENWRITEEN : out std_logic;
ISOCMBRAMODDWRITEEN : out std_logic;
ISOCMBRAMRDABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRABUS : out std_logic_vector(8 to 28);
ISOCMBRAMWRDBUS : out std_logic_vector(0 to 31);
--CPU JTAG Interface
C405JTGCAPTUREDR : out std_logic;
C405JTGEXTEST : out std_logic;
C405JTGPGMOUT : out std_logic;
C405JTGSHIFTDR : out std_logic;
C405JTGTDO : out std_logic;
C405JTGTDOEN : out std_logic;
C405JTGUPDATEDR : out std_logic;
MCBJTAGEN : in std_logic;
JTGC405BNDSCANTDO : in std_logic;
JTGC405TCK : in std_logic;
JTGC405TDI : in std_logic;
JTGC405TMS : in std_logic;
JTGC405TRSTNEG : in std_logic
);
end ppc405_top;
architecture structural of ppc405_top is
--constants for DCR
constant C_DCR_AWIDTH : integer := 10;
constant C_DCR_DWIDTH : integer := 32;
--constants for OSIF_ADAPTER
constant COMMANDREG_WIDTH : integer := 5;
constant DATAREG_WIDTH : integer := 32;
constant DONEREG_WIDTH : integer := 1;
constant CPU_DWIDTH : integer := 32;
--BOOTCODE for CPU_Start
--constant C_BOOT_SECT_DATA : std_logic_vector := X"4bffd004";--X"4bffd004";--X"4bfffff0";X"48000000";
--signals --------------------------------------------------------------------
---CPU_DCR -> CPU_HWT_DCR
signal CPU_C405DCRABUS : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal CPU_C405DCRDBUSOUT: std_logic_vector(0 to C_DCR_DWIDTH-1);
signal CPU_DCRC405DBUSIN : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal CPU_C405DCRREAD : std_logic;
signal CPU_C405DCRWRITE : std_logic;
signal CPU_DCRC405ACK : std_logic;
---OSIF_ADPTER -> CPU_HWT_DCR
signal o_dcrDBus : std_logic_vector(0 to C_DCR_DWIDTH-1);
signal i_dcrABus : std_logic_vector(0 to C_DCR_AWIDTH-1);
signal i_dcrDBus : std_logic_vector(0 to C_DCR_DWIDTH-1);
---Connect Ack, Read, Write to DCR
signal o_dcrAck_vec : std_logic_vector(0 to 0);
signal i_dcrRead_vec : std_logic_vector(0 to 0);
signal i_dcrWrite_vec : std_logic_vector(0 to 0);
---OSIF_ADAPTER -> PPC
signal cpu_reset : std_logic;
--OSIF_FLAT / Reset / busylocal
signal o_osif_flat_i : std_logic_vector(0 to C_OSIF_TASK2OS_REC_WIDTH-1);
signal i_osif_flat_i : std_logic_vector(0 to C_OSIF_OS2TASK_REC_WIDTH-1);
signal o_osif : osif_task2os_t;
signal i_osif : osif_os2task_t;
signal busy_local : std_logic;
signal i_reset : std_logic;
--clk signal for PowerPC
signal ppc_clk : std_logic;
--CPU signals which are not used
signal CPMC405CPUCLKEN, CPMC405JTAGCLKEN, CPMC405TIMERCLKEN, CPMC405TIMERTICK, MCBCPUCLKEN, MCBTIMEREN, MCPPCRST : std_logic;
signal CPMC405CORECLKINACTIVE, RSTC405RESETCHIP, RSTC405RESETSYS : std_logic;
signal C405CPMCORESLEEPREQ,C405CPMMSRCE,C405CPMMSREE,C405CPMTIMERIRQ,C405CPMTIMERRESETREQ,C405XXXMACHINECHECK : std_logic;
signal EICC405CRITINPUTIRQ, EICC405EXTINPUTIRQ : std_logic;
signal C405DBGMSRWE, C405DBGSTOPACK, C405DBGWBCOMPLETE, C405DBGWBFULL, DBGC405DEBUGHALT, DBGC405EXTBUSHOLDACK, DBGC405UNCONDDEBUGEVENT : std_logic;
signal C405DBGWBIAR : std_logic_vector(0 to 29);
--other sigs
signal net_vcc0 : std_logic;
begin
--other sigs
net_vcc0 <= '1';
--Processess for the GENERICS ---------------------------------------------------
--C_EXT_RESET_HIGH
RSTPROCESS: process(reset)
begin
if C_EXT_RESET_HIGH = 1 then
i_reset <= reset;
else
i_reset <= not reset;
end if;
end process;
--CPU_USE_OTHER_CLK :
--if 1 then use port cpu_clk otherwise use threadclk_port clk
CPU_CLK_PROCESS: process(clk, cpu_clk)
begin
if CPU_USE_OTHER_CLK = 1 then
ppc_clk <= cpu_clk;
else
ppc_clk <= clk;
end if;
end process;
--Process and assignments for OSIF ----------------------------------------------
-- (un)flatten osif records
o_osif_flat_i <= to_std_logic_vector(o_osif);
-- overlay busy with local busy signal
--i_osif <= to_osif_os2task_t(i_osif_flat_i);
i_osif <= to_osif_os2task_t(i_osif_flat_i or (X"0000000000" & busy_local & "000000"));
register_osif_ports_proc: process(clk)
begin
if rising_edge(clk) then
o_osif_flat <= o_osif_flat_i;
i_osif_flat_i <= i_osif_flat;
end if;
end process;
-- infer latch for local busy signal
-- needed for asynchronous communication between thread and OSIF
busy_local_gen : process(i_reset, o_osif.request, i_osif.ack)
begin
if i_reset = '1' then
busy_local <= '0';
elsif o_osif.request = '1' then
busy_local <= '1';
elsif i_osif.ack = '1' then
busy_local <= '0';
end if;
end process;
--------- COMPONENTS ------------------------------------------------------------
cpu_osif_adapter_i : entity cpu_osif_adapter_v1_04_a.cpu_osif_adapter
generic map (
C_BASEADDR => B"0000011000",
C_HIGHADDR => B"0000011111",
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
COMMANDREG_WIDTH => COMMANDREG_WIDTH,
DATAREG_WIDTH => DATAREG_WIDTH,
DONEREG_WIDTH => DONEREG_WIDTH,
CPU_RESET_CYCLES => CPU_RESET_CYCLES,
CPU_DWIDTH => CPU_DWIDTH,
C_BOOT_SECT_DATA => C_BOOT_SECT_DATA
)
port map (
clk => clk,
reset => i_reset,
--dcr signals for Main CPU
o_dcrAck => o_dcrAck_vec(0),
o_dcrDBus => o_dcrDBus,
i_dcrABus => i_dcrABus,
i_dcrDBus => i_dcrDBus,
i_dcrRead => i_dcrRead_vec(0),
i_dcrWrite => i_dcrWrite_vec(0),
--signals to osif
i_osif => i_osif,
o_osif => o_osif,
cpu_reset => cpu_reset,
--debug signals
debug_idle_state => debug_idle_state,
debug_busy_state => debug_busy_state,
debug_reconos_ready => debug_reconos_ready,
--signal to/from bram_logic
boot_sect_ready => boot_sect_ready,
set_boot_sect => set_boot_sect,
boot_sect_data => boot_sect_data
);
CPU_HWT_DCR_BUS : entity dcr_v29_v1_00_a.dcr_v29
generic map (
C_DCR_NUM_SLAVES => 1,
C_DCR_AWIDTH => C_DCR_AWIDTH,
C_DCR_DWIDTH => C_DCR_DWIDTH,
C_USE_LUT_OR => 1
)
port map (
M_dcrABus => CPU_C405DCRABUS,
M_dcrDBus => CPU_C405DCRDBUSOUT,
M_dcrRead => CPU_C405DCRREAD,
M_dcrWrite => CPU_C405DCRWRITE,
DCR_M_DBus => CPU_DCRC405DBUSIN,
DCR_Ack => CPU_DCRC405ACK,
DCR_ABus => i_dcrABus,
DCR_Sl_DBus => i_dcrDBus,
DCR_Read => i_dcrRead_vec,
DCR_Write => i_dcrWrite_vec,
Sl_dcrDBus => o_dcrDBus,
Sl_dcrAck => o_dcrAck_vec
);
CPU_HWT : entity ppc405_v2_00_c.ppc405_top
generic map (
C_ISOCM_DCR_BASEADDR => B"0000010000",
C_ISOCM_DCR_HIGHADDR => B"0000010011",
C_DSOCM_DCR_BASEADDR => B"0000100000",
C_DSOCM_DCR_HIGHADDR => B"0000100011",
C_DISABLE_OPERAND_FORWARDING => 1,
C_DETERMINISTIC_MULT => 0,
C_MMU_ENABLE => CPU_MMU_ENABLE,
C_DCR_RESYNC => CPU_DCR_RESYNC
)
port map (
CPMC405CLOCK => ppc_clk,
DCRCLK => clk,
C405RSTCHIPRESETREQ => open,
C405RSTCORERESETREQ => open,
C405RSTSYSRESETREQ => open,
RSTC405RESETCHIP => '0',--RSTC405RESETCHIP,
RSTC405RESETCORE => cpu_reset,
RSTC405RESETSYS => '0',--RSTC405RESETSYS,
--PLB signals
PLBCLK => PLBCLK,
C405PLBICUABUS => C405PLBICUABUS,
C405PLBICUBE => C405PLBICUBE,
C405PLBICURNW => C405PLBICURNW,
C405PLBICUABORT => C405PLBICUABORT,
C405PLBICUBUSLOCK => C405PLBICUBUSLOCK,
C405PLBICUU0ATTR => C405PLBICUU0ATTR,
C405PLBICUGUARDED => C405PLBICUGUARDED,
C405PLBICULOCKERR => C405PLBICULOCKERR,
C405PLBICUMSIZE => C405PLBICUMSIZE,
C405PLBICUORDERED => C405PLBICUORDERED,
C405PLBICUPRIORITY => C405PLBICUPRIORITY,
C405PLBICURDBURST => C405PLBICURDBURST,
C405PLBICUREQUEST => C405PLBICUREQUEST,
C405PLBICUSIZE => C405PLBICUSIZE,
C405PLBICUTYPE => C405PLBICUTYPE,
C405PLBICUWRBURST => C405PLBICUWRBURST,
C405PLBICUWRDBUS => C405PLBICUWRDBUS,
C405PLBICUCACHEABLE => C405PLBICUCACHEABLE,
PLBC405ICUADDRACK => PLBC405ICUADDRACK,
PLBC405ICUBUSY => PLBC405ICUBUSY,
PLBC405ICUERR => PLBC405ICUERR,
PLBC405ICURDBTERM => PLBC405ICURDBTERM,
PLBC405ICURDDACK => PLBC405ICURDDACK,
PLBC405ICURDDBUS => PLBC405ICURDDBUS,
PLBC405ICURDWDADDR => PLBC405ICURDWDADDR,
PLBC405ICUREARBITRATE => PLBC405ICUREARBITRATE,
PLBC405ICUWRBTERM => PLBC405ICUWRBTERM,
PLBC405ICUWRDACK => PLBC405ICUWRDACK,
PLBC405ICUSSIZE => PLBC405ICUSSIZE,
PLBC405ICUSERR => PLBC405ICUSERR,
PLBC405ICUSBUSYS => PLBC405ICUSBUSYS,
C405PLBDCUABUS => C405PLBDCUABUS,
C405PLBDCUBE => C405PLBDCUBE,
C405PLBDCURNW => C405PLBDCURNW,
C405PLBDCUABORT => C405PLBDCUABORT,
C405PLBDCUBUSLOCK => C405PLBDCUBUSLOCK,
C405PLBDCUU0ATTR => C405PLBDCUU0ATTR,
C405PLBDCUGUARDED => C405PLBDCUGUARDED,
C405PLBDCULOCKERR => C405PLBDCULOCKERR,
C405PLBDCUMSIZE => C405PLBDCUMSIZE,
C405PLBDCUORDERED => C405PLBDCUORDERED,
C405PLBDCUPRIORITY => C405PLBDCUPRIORITY,
C405PLBDCURDBURST => C405PLBDCURDBURST,
C405PLBDCUREQUEST => C405PLBDCUREQUEST,
C405PLBDCUSIZE => C405PLBDCUSIZE,
C405PLBDCUTYPE => C405PLBDCUTYPE,
C405PLBDCUWRBURST => C405PLBDCUWRBURST,
C405PLBDCUWRDBUS => C405PLBDCUWRDBUS,
C405PLBDCUCACHEABLE => C405PLBDCUCACHEABLE,
C405PLBDCUWRITETHRU => C405PLBDCUWRITETHRU,
PLBC405DCUADDRACK => PLBC405DCUADDRACK,
PLBC405DCUBUSY => PLBC405DCUBUSY,
PLBC405DCUERR => PLBC405DCUERR,
PLBC405DCURDBTERM => PLBC405DCURDBTERM,
PLBC405DCURDDACK => PLBC405DCURDDACK,
PLBC405DCURDDBUS => PLBC405DCURDDBUS,
PLBC405DCURDWDADDR => PLBC405DCURDWDADDR,
PLBC405DCUREARBITRATE => PLBC405DCUREARBITRATE,
PLBC405DCUWRBTERM => PLBC405DCUWRBTERM,
PLBC405DCUWRDACK => PLBC405DCUWRDACK,
PLBC405DCUSSIZE => PLBC405DCUSSIZE,
PLBC405DCUSERR => PLBC405DCUSERR,
PLBC405DCUSBUSYS => PLBC405DCUSBUSYS,
--ocm signals
BRAMDSOCMCLK => BRAMDSOCMCLK,
BRAMDSOCMRDDBUS => BRAMDSOCMRDDBUS,
DSARCVALUE => DSARCVALUE,
DSCNTLVALUE => DSCNTLVALUE,
DSOCMBRAMABUS => DSOCMBRAMABUS,
DSOCMBRAMBYTEWRITE => DSOCMBRAMBYTEWRITE,
DSOCMBRAMEN => DSOCMBRAMEN,
DSOCMBRAMWRDBUS => DSOCMBRAMWRDBUS,
DSOCMBUSY => DSOCMBUSY,
BRAMISOCMCLK => BRAMISOCMCLK,
BRAMISOCMRDDBUS => BRAMISOCMRDDBUS,
ISARCVALUE => ISARCVALUE,
ISCNTLVALUE => ISCNTLVALUE,
ISOCMBRAMEN => ISOCMBRAMEN,
ISOCMBRAMEVENWRITEEN => ISOCMBRAMEVENWRITEEN,
ISOCMBRAMODDWRITEEN => ISOCMBRAMODDWRITEEN,
ISOCMBRAMRDABUS => ISOCMBRAMRDABUS,
ISOCMBRAMWRABUS => ISOCMBRAMWRABUS,
ISOCMBRAMWRDBUS => ISOCMBRAMWRDBUS,
--DCR signals
C405DCRABUS => CPU_C405DCRABUS,
C405DCRDBUSOUT => CPU_C405DCRDBUSOUT,
C405DCRREAD => CPU_C405DCRREAD,
C405DCRWRITE => CPU_C405DCRWRITE,
DCRC405ACK => CPU_DCRC405ACK,
DCRC405DBUSIN => CPU_DCRC405DBUSIN,
-- JTAG Interface
C405JTGCAPTUREDR => C405JTGCAPTUREDR, -- O
C405JTGEXTEST => C405JTGEXTEST, -- O
C405JTGPGMOUT => C405JTGPGMOUT, -- O
C405JTGSHIFTDR => C405JTGSHIFTDR, -- O
C405JTGTDO => C405JTGTDO, -- O
C405JTGTDOEN => C405JTGTDOEN, -- O
C405JTGUPDATEDR => C405JTGUPDATEDR, -- O
MCBJTAGEN => net_vcc0,--MCBJTAGEN, -- I
JTGC405BNDSCANTDO => JTGC405BNDSCANTDO, -- I
JTGC405TCK => JTGC405TCK, -- I
JTGC405TDI => JTGC405TDI, -- I
JTGC405TMS => JTGC405TMS, -- I
JTGC405TRSTNEG => JTGC405TRSTNEG,
--Ports which are not used -----------------------------------------------
CPMC405CORECLKINACTIVE => '0',--CPMC405CORECLKINACTIVE, -- I
CPMC405CPUCLKEN => net_vcc0, --CPMC405CPUCLKEN, -- I
CPMC405JTAGCLKEN => net_vcc0, --CPMC405JTAGCLKEN, -- I
CPMC405TIMERCLKEN => net_vcc0, --CPMC405TIMERCLKEN, -- I
CPMC405TIMERTICK => net_vcc0, --CPMC405TIMERTICK, -- I
MCBCPUCLKEN => net_vcc0, --MCBCPUCLKEN, -- I
MCBTIMEREN => net_vcc0, --MCBTIMEREN, -- I
MCPPCRST => net_vcc0, --MCPPCRST,
C405CPMCORESLEEPREQ => C405CPMCORESLEEPREQ, -- O
C405CPMMSRCE => C405CPMMSRCE, -- O
C405CPMMSREE => C405CPMMSREE, -- O
C405CPMTIMERIRQ => C405CPMTIMERIRQ, -- O
C405CPMTIMERRESETREQ => C405CPMTIMERRESETREQ, -- O
C405XXXMACHINECHECK => C405XXXMACHINECHECK, -- O
-- Interrupt Controller Interface
EICC405CRITINPUTIRQ => '0',--EICC405CRITINPUTIRQ, -- I
EICC405EXTINPUTIRQ => '0',--EICC405EXTINPUTIRQ, -- I
-- Debug Interface
C405DBGMSRWE => C405DBGMSRWE, -- O
C405DBGSTOPACK => C405DBGSTOPACK, -- O
C405DBGWBCOMPLETE => C405DBGWBCOMPLETE, -- O
C405DBGWBFULL => C405DBGWBFULL, -- O
C405DBGWBIAR => C405DBGWBIAR, -- O [0:29]
DBGC405DEBUGHALT => '0',--DBGC405DEBUGHALT, -- I
DBGC405EXTBUSHOLDACK => '0',--DBGC405EXTBUSHOLDACK, -- I
DBGC405UNCONDDEBUGEVENT => '0',--DBGC405UNCONDDEBUGEVENT,
-- Trace Interface
C405TRCCYCLE => open , -- O
C405TRCEVENEXECUTIONSTATUS => open, -- O [0:1]
C405TRCODDEXECUTIONSTATUS => open, -- O [0:1]
C405TRCTRACESTATUS => open, -- O [0:3]
C405TRCTRIGGEREVENTOUT => open, -- O
C405TRCTRIGGEREVENTTYPE => open, -- O [0:10]
TRCC405TRACEDISABLE => '0', -- I
TRCC405TRIGGEREVENTIN => '0' -- I
);
end structural;
|
constant TRFSM1Length : integer := 1778;
constant TRFSM1Cfg : std_logic_vector(TRFSM1Length-1 downto 0) := "00001100000000100000000100000010000101001100000000001000011000110001100000000000000011100010001100000000010000100000010100100000110000000101000001000100000100000000101100001100101000001000000110000000100100000100000011111100000000000000000000011111100000000000000000000000000000000010000100000000100001000000000000000000010001000011101100001000000000000100000000011000000100100000000000100000100000000010100100001100000000000100001000000000101000000000100010000000000010100000000011000010100100000010000000010100000000010100101100101100010000000100100000001001000011001100001000000000100100000001000100100100010001000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000000001000000000110010000010001000000000000000010000000001100010010010001000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000111111000000000000000000000000000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000111111000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000";
|
constant TRFSM1Length : integer := 1778;
constant TRFSM1Cfg : std_logic_vector(TRFSM1Length-1 downto 0) := "00001100000000100000000100000010000101001100000000001000011000110001100000000000000011100010001100000000010000100000010100100000110000000101000001000100000100000000101100001100101000001000000110000000100100000100000011111100000000000000000000011111100000000000000000000000000000000010000100000000100001000000000000000000010001000011101100001000000000000100000000011000000100100000000000100000100000000010100100001100000000000100001000000000101000000000100010000000000010100000000011000010100100000010000000010100000000010100101100101100010000000100100000001001000011001100001000000000100100000001000100100100010001000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000011111100000000000000000000000000000000000001000000000110010000010001000000000000000010000000001100010010010001000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000111111000000000000000000000000000000000001111110000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000111111000000000000000000000000000000000000000000000001111110000000000000000000000000000000000000000000000011111100000000000000000000000000000000000000000000000";
|
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used solely --
-- for design, simulation, implementation and creation of design files --
-- limited to Xilinx devices or technologies. Use with non-Xilinx --
-- devices or technologies is expressly prohibited and immediately --
-- terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
-- PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support appliances, --
-- devices, or systems. Use in such applications are expressly --
-- prohibited. --
-- --
-- (c) Copyright 1995-2014 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- You must compile the wrapper file sb_dc_fifo.vhd when simulating
-- the core, sb_dc_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
LIBRARY XilinxCoreLib;
-- synthesis translate_on
ENTITY sb_dc_fifo IS
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END sb_dc_fifo;
ARCHITECTURE sb_dc_fifo_a OF sb_dc_fifo IS
-- synthesis translate_off
COMPONENT wrapped_sb_dc_fifo
PORT (
rst : IN STD_LOGIC;
wr_clk : IN STD_LOGIC;
rd_clk : IN STD_LOGIC;
din : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
wr_en : IN STD_LOGIC;
rd_en : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
full : OUT STD_LOGIC;
empty : OUT STD_LOGIC;
valid : OUT STD_LOGIC
);
END COMPONENT;
-- Configuration specification
FOR ALL : wrapped_sb_dc_fifo USE ENTITY XilinxCoreLib.fifo_generator_v8_4(behavioral)
GENERIC MAP (
c_add_ngc_constraint => 0,
c_application_type_axis => 0,
c_application_type_rach => 0,
c_application_type_rdch => 0,
c_application_type_wach => 0,
c_application_type_wdch => 0,
c_application_type_wrch => 0,
c_axi_addr_width => 32,
c_axi_aruser_width => 1,
c_axi_awuser_width => 1,
c_axi_buser_width => 1,
c_axi_data_width => 64,
c_axi_id_width => 4,
c_axi_ruser_width => 1,
c_axi_type => 0,
c_axi_wuser_width => 1,
c_axis_tdata_width => 64,
c_axis_tdest_width => 4,
c_axis_tid_width => 8,
c_axis_tkeep_width => 4,
c_axis_tstrb_width => 4,
c_axis_tuser_width => 4,
c_axis_type => 0,
c_common_clock => 0,
c_count_type => 0,
c_data_count_width => 10,
c_default_value => "BlankString",
c_din_width => 16,
c_din_width_axis => 1,
c_din_width_rach => 32,
c_din_width_rdch => 64,
c_din_width_wach => 32,
c_din_width_wdch => 64,
c_din_width_wrch => 2,
c_dout_rst_val => "0",
c_dout_width => 16,
c_enable_rlocs => 0,
c_enable_rst_sync => 1,
c_error_injection_type => 0,
c_error_injection_type_axis => 0,
c_error_injection_type_rach => 0,
c_error_injection_type_rdch => 0,
c_error_injection_type_wach => 0,
c_error_injection_type_wdch => 0,
c_error_injection_type_wrch => 0,
c_family => "virtex6",
c_full_flags_rst_val => 1,
c_has_almost_empty => 0,
c_has_almost_full => 0,
c_has_axi_aruser => 0,
c_has_axi_awuser => 0,
c_has_axi_buser => 0,
c_has_axi_rd_channel => 0,
c_has_axi_ruser => 0,
c_has_axi_wr_channel => 0,
c_has_axi_wuser => 0,
c_has_axis_tdata => 0,
c_has_axis_tdest => 0,
c_has_axis_tid => 0,
c_has_axis_tkeep => 0,
c_has_axis_tlast => 0,
c_has_axis_tready => 1,
c_has_axis_tstrb => 0,
c_has_axis_tuser => 0,
c_has_backup => 0,
c_has_data_count => 0,
c_has_data_counts_axis => 0,
c_has_data_counts_rach => 0,
c_has_data_counts_rdch => 0,
c_has_data_counts_wach => 0,
c_has_data_counts_wdch => 0,
c_has_data_counts_wrch => 0,
c_has_int_clk => 0,
c_has_master_ce => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_has_prog_flags_axis => 0,
c_has_prog_flags_rach => 0,
c_has_prog_flags_rdch => 0,
c_has_prog_flags_wach => 0,
c_has_prog_flags_wdch => 0,
c_has_prog_flags_wrch => 0,
c_has_rd_data_count => 0,
c_has_rd_rst => 0,
c_has_rst => 1,
c_has_slave_ce => 0,
c_has_srst => 0,
c_has_underflow => 0,
c_has_valid => 1,
c_has_wr_ack => 0,
c_has_wr_data_count => 0,
c_has_wr_rst => 0,
c_implementation_type => 2,
c_implementation_type_axis => 1,
c_implementation_type_rach => 1,
c_implementation_type_rdch => 1,
c_implementation_type_wach => 1,
c_implementation_type_wdch => 1,
c_implementation_type_wrch => 1,
c_init_wr_pntr_val => 0,
c_interface_type => 0,
c_memory_type => 1,
c_mif_file_name => "BlankString",
c_msgon_val => 1,
c_optimization_mode => 0,
c_overflow_low => 0,
c_preload_latency => 0,
c_preload_regs => 1,
c_prim_fifo_type => "1kx18",
c_prog_empty_thresh_assert_val => 4,
c_prog_empty_thresh_assert_val_axis => 1022,
c_prog_empty_thresh_assert_val_rach => 1022,
c_prog_empty_thresh_assert_val_rdch => 1022,
c_prog_empty_thresh_assert_val_wach => 1022,
c_prog_empty_thresh_assert_val_wdch => 1022,
c_prog_empty_thresh_assert_val_wrch => 1022,
c_prog_empty_thresh_negate_val => 5,
c_prog_empty_type => 0,
c_prog_empty_type_axis => 5,
c_prog_empty_type_rach => 5,
c_prog_empty_type_rdch => 5,
c_prog_empty_type_wach => 5,
c_prog_empty_type_wdch => 5,
c_prog_empty_type_wrch => 5,
c_prog_full_thresh_assert_val => 1023,
c_prog_full_thresh_assert_val_axis => 1023,
c_prog_full_thresh_assert_val_rach => 1023,
c_prog_full_thresh_assert_val_rdch => 1023,
c_prog_full_thresh_assert_val_wach => 1023,
c_prog_full_thresh_assert_val_wdch => 1023,
c_prog_full_thresh_assert_val_wrch => 1023,
c_prog_full_thresh_negate_val => 1022,
c_prog_full_type => 0,
c_prog_full_type_axis => 5,
c_prog_full_type_rach => 5,
c_prog_full_type_rdch => 5,
c_prog_full_type_wach => 5,
c_prog_full_type_wdch => 5,
c_prog_full_type_wrch => 5,
c_rach_type => 0,
c_rd_data_count_width => 10,
c_rd_depth => 1024,
c_rd_freq => 1,
c_rd_pntr_width => 10,
c_rdch_type => 0,
c_reg_slice_mode_axis => 0,
c_reg_slice_mode_rach => 0,
c_reg_slice_mode_rdch => 0,
c_reg_slice_mode_wach => 0,
c_reg_slice_mode_wdch => 0,
c_reg_slice_mode_wrch => 0,
c_synchronizer_stage => 2,
c_underflow_low => 0,
c_use_common_overflow => 0,
c_use_common_underflow => 0,
c_use_default_settings => 0,
c_use_dout_rst => 1,
c_use_ecc => 0,
c_use_ecc_axis => 0,
c_use_ecc_rach => 0,
c_use_ecc_rdch => 0,
c_use_ecc_wach => 0,
c_use_ecc_wdch => 0,
c_use_ecc_wrch => 0,
c_use_embedded_reg => 0,
c_use_fifo16_flags => 0,
c_use_fwft_data_count => 0,
c_valid_low => 0,
c_wach_type => 0,
c_wdch_type => 0,
c_wr_ack_low => 0,
c_wr_data_count_width => 10,
c_wr_depth => 1024,
c_wr_depth_axis => 1024,
c_wr_depth_rach => 16,
c_wr_depth_rdch => 1024,
c_wr_depth_wach => 16,
c_wr_depth_wdch => 1024,
c_wr_depth_wrch => 16,
c_wr_freq => 1,
c_wr_pntr_width => 10,
c_wr_pntr_width_axis => 10,
c_wr_pntr_width_rach => 4,
c_wr_pntr_width_rdch => 10,
c_wr_pntr_width_wach => 4,
c_wr_pntr_width_wdch => 10,
c_wr_pntr_width_wrch => 4,
c_wr_response_latency => 1,
c_wrch_type => 0
);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_sb_dc_fifo
PORT MAP (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid
);
-- synthesis translate_on
END sb_dc_fifo_a;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
use IEEE.STD_LOGIC_arith.all;
----------------------------------------------------------------------------------------------------
entity celda_A is
generic(
NUM_BITS : positive := 163
);
port(
A : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
B : in STD_LOGIC_VECTOR(NUM_BITS downto 0);
c0 : in STD_LOGIC;
c1 : in STD_LOGIC;
c3 : in STD_LOGIC;
rst : in STD_LOGIC;
clk : in STD_LOGIC;
toA : out STD_LOGIC_VECTOR(NUM_BITS downto 0); -- U = x/y mod Fx,
RegA : out STD_LOGIC_VECTOR(NUM_BITS downto 0) -- U = x/y mod Fx,
);
end;
----------------------------------------------------------------------------------------------------
architecture behave of celda_A is
----------------------------------------------------------------------------------------------------
signal R1,R2 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal A1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
signal B1 : STD_LOGIC_VECTOR(NUM_BITS downto 0);
begin
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
-- Finite state machine
----------------------------------------------------------------------------------------------------
A1 <= A when c0 = '1' else
(others => '0');
B1 <= B when c1 = '1' else
(others => '0');
R1 <= A1 xor B1;
R2 <= '0'&R1(NUM_BITS downto 1);
toA <= R2;
celda_A_process: process (clk)
begin -- syncronous reset
if CLK'event and CLK = '1' then
if (rst = '1')then
RegA <= (others => '0');
else
if c3 = '1' then
RegA <= R2;
end if;
end if;
end if;
end process;
end behave;
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
|
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- upcnt_n - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: upcnt_n.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/07/01 -- First Release
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_SIZE -- Number of bits in counter
--
--
-- Definition of Ports:
-- Data -- parallel data input
-- Cnt_en -- count enable
-- Load -- Load Data
-- Clr -- reset
-- Clk -- Clock
-- Qout -- Count output
--
-------------------------------------------------------------------------------
entity upcnt_n is
generic(
C_SIZE : Integer
);
port(
Data : in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
Cnt_en : in STD_LOGIC;
Load : in STD_LOGIC;
Clr : in STD_LOGIC;
Clk : in STD_LOGIC;
Qout : out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
);
end upcnt_n;
architecture imp of upcnt_n is
constant CLEAR : std_logic := '0';
signal q_int : UNSIGNED (C_SIZE-1 downto 0) := (others => '1');
begin
process(Clk)
begin
if (Clk'event) and Clk = '1' then
-- Clear output register
if (Clr = CLEAR) then
q_int <= (others => '0');
-- Load in start value
elsif (Load = '1') then
q_int <= UNSIGNED(Data);
-- If count enable is high
elsif Cnt_en = '1' then
q_int <= q_int + 1;
end if;
end if;
end process;
Qout <= STD_LOGIC_VECTOR(q_int);
end imp;
-------------------------------------------------------------------------------
-- sequence - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
-- -- proc_sys_reset.vhd
-- -- upcnt_n.vhd
-- -- lpf.vhd
-- -- sequence.vhd
-------------------------------------------------------------------------------
-- Filename: sequence.vhd
--
-- Description:
-- This file control the sequencing coming out of a reset.
-- The sequencing is as follows:
-- Bus_Struct_Reset comes out of reset first. Either when the
-- external or auxiliary reset goes inactive or 16 clocks
-- after a PPC Chip_Reset_Request, or 30 clocks after a PPC
-- System_Reset_Request.
-- Peripheral_Reset comes out of reset 16 clocks after
-- Bus_Struct_Reset.
-- The PPC resetcore, comes out of reset
-- 16 clocks after Peripheral_Reset.
-- The PPC resetchip and resetsystem come out of reset
-- at the same time as Bus_Struct_Reset.
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/12/01 -- First Release
-- LC Whittle 10/11/2004 -- Update for NCSim
-- rolandp 04/16/2007 -- v2.00a
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
--
-- Definition of Ports:
-- Lpf_reset -- Low Pass Filtered in
-- System_Reset_Req -- System Reset Request
-- Chip_Reset_Req -- Chip Reset Request
-- Slowest_Sync_Clk -- Clock
-- Bsr_out -- Bus Structure Reset out
-- Pr_out -- Peripheral Reset out
-- Core_out -- Core reset out
-- Chip_out -- Chip reset out
-- Sys_out -- System reset out
-- MB_out -- MB reset out
--
-------------------------------------------------------------------------------
entity sequence_psr is
port(
Lpf_reset : in std_logic;
-- System_Reset_Req : in std_logic;
-- Chip_Reset_Req : in std_logic;
Slowest_Sync_Clk : in std_logic;
Bsr_out : out std_logic;
Pr_out : out std_logic;
-- Core_out : out std_logic;
-- Chip_out : out std_logic;
-- Sys_out : out std_logic;
MB_out : out std_logic
);
end sequence_psr;
architecture imp of sequence_psr is
constant CLEAR : std_logic := '0';
constant BSR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "001100"; -- 12
constant BSR_END_SYS : std_logic_vector(5 downto 0) := "011001"; -- 25
constant PR_END_LPF_CHIP : std_logic_vector(5 downto 0) := "011100"; -- 28
constant PR_END_SYS : std_logic_vector(5 downto 0) := "101001"; -- 41
constant CORE_END_LPF_CHIP : std_logic_vector(5 downto 0) := "101100"; -- 44
constant CORE_END_SYS : std_logic_vector(5 downto 0) := "111001"; -- 57
constant CHIP_END_LPF_CHIP : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant CHIP_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
constant SYS_END_LPF : std_logic_vector(5 downto 0) := BSR_END_LPF_CHIP;
constant SYS_END_SYS : std_logic_vector(5 downto 0) := BSR_END_SYS;
signal bsr : std_logic := '0';
signal bsr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal pr : std_logic := '0';
signal pr_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Core : std_logic := '0';
signal core_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Chip : std_logic := '0';
signal chip_dec : std_logic_vector(2 downto 0) := (others => '0');
signal Sys : std_logic := '0';
signal sys_dec : std_logic_vector(2 downto 0) := (others => '0');
signal chip_Reset_Req_d1 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d2 : std_logic := '0'; -- delayed Chip_Reset_Req
signal chip_Reset_Req_d3 : std_logic := '0'; -- delayed Chip_Reset_Req
signal system_Reset_Req_d1 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d2 : std_logic := '0'; -- delayed System_Reset_Req
signal system_Reset_Req_d3 : std_logic := '0'; -- delayed System_Reset_Req
signal seq_cnt : std_logic_vector(5 downto 0);
signal seq_cnt_en : std_logic := '0';
signal seq_clr : std_logic := '0';
signal ris_edge : std_logic := '0';
signal sys_edge : std_logic := '0';
signal from_sys : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
begin
Pr_out <= pr;
Bsr_out <= bsr;
MB_out <= core;
-- Core_out <= core;
-- Chip_out <= chip or sys;
-- Sys_out <= sys;
-------------------------------------------------------------------------------
-- This process remembers that the reset was caused be
-- System_Reset_Req
-------------------------------------------------------------------------------
SYS_FROM_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if Lpf_reset='1' or system_reset_req_d3='1' then
if (Lpf_reset = '1') then
from_sys <= '1';
--elsif Chip_Reset_Req_d3='1' then
-- from_sys <= '0';
elsif (Core = '0') then
from_sys <='0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This instantiates a counter to control the sequencing
-------------------------------------------------------------------------------
SEQ_COUNTER : entity proc_sys_reset_v5_0_10.UPCNT_N
generic map (C_SIZE => 6)
port map(
Data => "000000",
Cnt_en => seq_cnt_en,
Load => '0',
Clr => seq_clr,
Clk => Slowest_sync_clk,
Qout => seq_cnt
);
-------------------------------------------------------------------------------
-- SEQ_CNT_EN_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
-- count until all outputs are inactive
-------------------------------------------------------------------------------
SEQ_CNT_EN_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (Lpf_reset='1' --or
--System_Reset_Req_d3='1' or
--Chip_Reset_Req_d3='1' or
--ris_edge = '1'
) then
seq_cnt_en <= '1';
elsif (Core='0') then -- Core always present and always last
seq_cnt_en <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- SEQ_CLR_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset to the sequence counter
-- Clear the counter on a rising edge of chip or system request or low pass
-- filter output
-------------------------------------------------------------------------------
SEQ_CLR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
seq_clr <= '0';
else
seq_clr <= '1';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
PR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
pr <= '1';
elsif (pr_dec(2) = '1') then
pr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
PR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = PR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = PR_END_SYS(5 downto 3) and from_sys = '1')
) then
pr_dec(0) <= '1';
else
pr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = PR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = PR_END_SYS(2 downto 0) and from_sys = '1')
)then
pr_dec(1) <= '1';
else
pr_dec(1) <= '0';
end if;
pr_dec(2) <= pr_dec(1) and pr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Bus_Struct_Reset output signal
-------------------------------------------------------------------------------
BSR_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
--if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
bsr <= '1';
elsif (bsr_dec(2) = '1') then
bsr <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for BSR to use
-------------------------------------------------------------------------------
BSR_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = BSR_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = BSR_END_SYS(5 downto 3) and from_sys = '1')
)then
bsr_dec(0) <= '1';
else
bsr_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = BSR_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = BSR_END_SYS(2 downto 0) and from_sys = '1')
)then
bsr_dec(1) <= '1';
else
bsr_dec(1) <= '0';
end if;
bsr_dec(2) <= bsr_dec(1) and bsr_dec(0);
end if;
end process;
-------------------------------------------------------------------------------
-- This process defines the Peripheral_Reset output signal
-------------------------------------------------------------------------------
CORE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if ris_edge = '1' or Lpf_reset = '1' then
if (Lpf_reset = '1') then
core <= '1';
elsif (core_dec(2) = '1') then
core <= '0';
end if;
end if;
end process;
-------------------------------------------------------------------------------
-- This process decodes the sequence counter for PR to use
-------------------------------------------------------------------------------
CORE_DECODE_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if (
(seq_cnt(5 downto 3) = CORE_END_LPF_CHIP(5 downto 3) and from_sys = '0')
or
(seq_cnt(5 downto 3) = CORE_END_SYS(5 downto 3) and from_sys = '1')
)then
core_dec(0) <= '1';
else
core_dec(0) <= '0';
end if;
if (
(seq_cnt(2 downto 0) = CORE_END_LPF_CHIP(2 downto 0) and from_sys = '0')
or
(seq_cnt(2 downto 0) = CORE_END_SYS(2 downto 0) and from_sys = '1')
)then
core_dec(1) <= '1';
else
core_dec(1) <= '0';
end if;
core_dec(2) <= core_dec(1) and core_dec(0);
end if;
end process;
---------------------------------------------------------------------------------
---- This process defines the Chip output signal
---------------------------------------------------------------------------------
-- CHIP_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- -- if ris_edge = '1' or Lpf_reset = '1' then
-- if Lpf_reset = '1' then
-- chip <= '1';
-- elsif chip_dec(2) = '1' then
-- chip <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Chip to use
---- sys is overlapping the chip reset and thus no need to decode this here
---------------------------------------------------------------------------------
-- CHIP_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 2) = CHIP_END_LPF_CHIP(5 downto 2)) then
-- chip_dec(0) <= '1';
-- else
-- chip_dec(0) <= '0';
-- end if;
-- if (seq_cnt(1 downto 0) = CHIP_END_LPF_CHIP(1 downto 0)) then
-- chip_dec(1) <= '1';
-- else
-- chip_dec(1) <= '0';
-- end if;
-- chip_dec(2) <= chip_dec(1) and chip_dec(0);
-- end if;
-- end process;
---------------------------------------------------------------------------------
---- This process defines the Sys output signal
---------------------------------------------------------------------------------
-- SYS_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if sys_edge = '1' or Lpf_reset = '1' then
-- sys <= '1';
-- elsif sys_dec(2) = '1' then
-- sys <= '0';
-- end if;
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process decodes the sequence counter for Sys to use
---------------------------------------------------------------------------------
-- SYS_DECODE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (seq_cnt(5 downto 3) = SYS_END_LPF(5 downto 3) and from_sys = '0') or
-- (seq_cnt(5 downto 3) = SYS_END_SYS(5 downto 3) and from_sys = '1') then
-- sys_dec(0) <= '1';
-- else
-- sys_dec(0) <= '0';
-- end if;
-- if (seq_cnt(2 downto 0) = SYS_END_LPF(2 downto 0) and from_sys = '0') or
-- (seq_cnt(2 downto 0) = SYS_END_SYS(2 downto 0) and from_sys = '1') then
-- sys_dec(1) <= '1';
-- else
-- sys_dec(1) <= '0';
-- end if;
-- sys_dec(2) <= sys_dec(1) and sys_dec(0);
-- end if;
-- end process;
--
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---------------------------------------------------------------------------------
-- DELAY_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- chip_reset_req_d1 <= Chip_Reset_Req ;
-- chip_reset_req_d2 <= chip_Reset_Req_d1 ;
-- chip_reset_req_d3 <= chip_Reset_Req_d2 ;
-- system_reset_req_d1 <= System_Reset_Req;
-- system_reset_req_d2 <= system_Reset_Req_d1;
-- system_reset_req_d3 <= system_Reset_Req_d2;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of either
-- Chip_Reset_Req or System_Reset_Req
-------------------------------------------------------------------------------
-- RIS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (chip_reset_req_d3='0' and chip_Reset_Req_d2= '1') -- rising edge
-- or (system_reset_req_d3='0' and system_Reset_Req_d2='1') then
-- ris_edge <= '1';
-- else
-- ris_edge <='0';
-- end if;
-- end if;
-- end process;
-------------------------------------------------------------------------------
-- This process creates a signal that goes high on the rising edge of
-- System_Reset_Req
-------------------------------------------------------------------------------
-- SYS_EDGE_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- if (system_reset_req_d3='0' and system_reset_req_d2='1') then
-- sys_edge <= '1';
-- else
-- sys_edge <='0';
-- end if;
-- end if;
-- end process;
end architecture imp;
-------------------------------------------------------------------------------
-- lpf - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: lpf.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: Kurt Conover
-- History:
-- Kurt Conover 11/08/01 -- First Release
--
-- KC 02/25/2002 -- Added Dcm_locked as an input
-- -- Added Power on reset srl_time_out
--
-- KC 08/26/2003 -- Added attribute statements for power on
-- reset SRL
--
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
library lib_cdc_v1_0_2;
--use lib_cdc_v1_0_2.all;
library Unisim;
use Unisim.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
--
-- Definition of Ports:
-- Slowest_sync_clk -- Clock
-- External_System_Reset -- External Reset Input
-- Auxiliary_System_Reset -- Auxiliary Reset Input
-- Dcm_locked -- DCM Locked, hold system in reset until 1
-- Lpf_reset -- Low Pass Filtered Output
--
-------------------------------------------------------------------------------
entity lpf is
generic(
C_EXT_RST_WIDTH : Integer;
C_AUX_RST_WIDTH : Integer;
C_EXT_RESET_HIGH : std_logic;
C_AUX_RESET_HIGH : std_logic
);
port(
MB_Debug_Sys_Rst : in std_logic;
Dcm_locked : in std_logic;
External_System_Reset : in std_logic;
Auxiliary_System_Reset : in std_logic;
Slowest_Sync_Clk : in std_logic;
Lpf_reset : out std_logic
);
end lpf;
architecture imp of lpf is
component SRL16 is
-- synthesis translate_off
generic (
INIT : bit_vector );
-- synthesis translate_on
port (D : in std_logic;
CLK : in std_logic;
A0 : in std_logic;
A1 : in std_logic;
A2 : in std_logic;
A3 : in std_logic;
Q : out std_logic);
end component SRL16;
constant CLEAR : std_logic := '0';
signal exr_d1 : std_logic := '0'; -- delayed External_System_Reset
signal exr_lpf : std_logic_vector(0 to C_EXT_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal asr_d1 : std_logic := '0'; -- delayed Auxiliary_System_Reset
signal asr_lpf : std_logic_vector(0 to C_AUX_RST_WIDTH - 1)
:= (others => '0'); -- LPF DFF
signal exr_and : std_logic := '0'; -- varible input width "and" gate
signal exr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal asr_and : std_logic := '0'; -- varible input width "and" gate
signal asr_nand : std_logic := '0'; -- vaiable input width "and" gate
signal lpf_int : std_logic := '0'; -- internal Lpf_reset
signal lpf_exr : std_logic := '0';
signal lpf_asr : std_logic := '0';
signal srl_time_out : std_logic;
attribute INIT : string;
attribute INIT of POR_SRL_I: label is "FFFF";
begin
Lpf_reset <= lpf_int;
-------------------------------------------------------------------------------
-- Power On Reset Generation
-------------------------------------------------------------------------------
-- This generates a reset for the first 16 clocks after a power up
-------------------------------------------------------------------------------
POR_SRL_I: SRL16
-- synthesis translate_off
generic map (
INIT => X"FFFF")
-- synthesis translate_on
port map (
D => '0',
CLK => Slowest_sync_clk,
A0 => '1',
A1 => '1',
A2 => '1',
A3 => '1',
Q => srl_time_out);
-------------------------------------------------------------------------------
-- LPF_OUTPUT_PROCESS
-------------------------------------------------------------------------------
-- This generates the reset pulse and the count enable to core reset counter
--
--ACTIVE_HIGH_LPF_EXT: if (C_EXT_RESET_HIGH = '1') generate
--begin
LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
lpf_int <= lpf_exr or lpf_asr or srl_time_out or not Dcm_locked;
end if;
end process LPF_OUTPUT_PROCESS;
--end generate ACTIVE_HIGH_LPF_EXT;
--ACTIVE_LOW_LPF_EXT: if (C_EXT_RESET_HIGH = '0') generate
--begin
--LPF_OUTPUT_PROCESS: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- lpf_int <= not (lpf_exr or
-- lpf_asr or
-- srl_time_out)or
-- not Dcm_locked;
-- end if;
-- end process;
--end generate ACTIVE_LOW_LPF_EXT;
EXR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if exr_and = '1' then
lpf_exr <= '1';
elsif (exr_and = '0' and exr_nand = '1') then
lpf_exr <= '0';
end if;
end if;
end process EXR_OUTPUT_PROCESS;
ASR_OUTPUT_PROCESS: process (Slowest_sync_clk)
begin
if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
if asr_and = '1' then
lpf_asr <= '1';
elsif (asr_and = '0' and asr_nand = '1') then
lpf_asr <= '0';
end if;
end if;
end process ASR_OUTPUT_PROCESS;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_EXT: if (C_EXT_RESET_HIGH /= '0') generate
begin
-----------------------------------
exr_d1 <= External_System_Reset or MB_Debug_Sys_Rst;
ACT_HI_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-----------------------------------
end generate ACTIVE_HIGH_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for External System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_EXT: if (C_EXT_RESET_HIGH = '0') generate
begin
exr_d1 <= not External_System_Reset or MB_Debug_Sys_Rst;
-------------------------------------
ACT_LO_EXT: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => exr_d1,
prmry_ack => open,
scndry_out => exr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_EXT;
-------------------------------------------------------------------------------
-- This If-generate selects an active high input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_HIGH_AUX: if (C_AUX_RESET_HIGH /= '0') generate
begin
asr_d1 <= Auxiliary_System_Reset;
-------------------------------------
ACT_HI_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_HIGH_AUX;
-------------------------------------------------------------------------------
-- This If-generate selects an active low input for Auxiliary System Reset
-------------------------------------------------------------------------------
ACTIVE_LOW_AUX: if (C_AUX_RESET_HIGH = '0') generate
begin
-------------------------------------
asr_d1 <= not Auxiliary_System_Reset;
ACT_LO_AUX: entity lib_cdc_v1_0_2.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 2,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',--S_AXI_ARESETN,
prmry_in => asr_d1,
prmry_ack => open,
scndry_out => asr_lpf(0),
scndry_aclk => Slowest_Sync_Clk,
scndry_resetn => '1', --S_AXIS_ARESETN,
prmry_vect_in => "00",
scndry_vect_out => open
);
-------------------------------------
end generate ACTIVE_LOW_AUX;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
EXT_LPF: for i in 1 to C_EXT_RST_WIDTH - 1 generate
begin
----------------------------------------
EXT_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
exr_lpf(i) <= exr_lpf(i-1);
end if;
end process;
----------------------------------------
end generate EXT_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
EXT_LPF_AND : process (exr_lpf)
Variable loop_and : std_logic;
Variable loop_nand : std_logic;
Begin
loop_and := '1';
loop_nand := '1';
for j in 0 to C_EXT_RST_WIDTH - 1 loop
loop_and := loop_and and exr_lpf(j);
loop_nand := loop_nand and not exr_lpf(j);
End loop;
exr_and <= loop_and;
exr_nand <= loop_nand;
end process;
-------------------------------------------------------------------------------
-- This For-generate creates the low pass filter D-Flip Flops
-------------------------------------------------------------------------------
AUX_LPF: for k in 1 to C_AUX_RST_WIDTH - 1 generate
begin
----------------------------------------
AUX_LPF_DFF : process (Slowest_Sync_Clk)
begin
if (Slowest_Sync_Clk'event) and Slowest_Sync_Clk = '1' then
asr_lpf(k) <= asr_lpf(k-1);
end if;
end process;
----------------------------------------
end generate AUX_LPF;
------------------------------------------------------------------------------------------
-- Implement the 'AND' function on the for the LPF
------------------------------------------------------------------------------------------
AUX_LPF_AND : process (asr_lpf)
Variable aux_loop_and : std_logic;
Variable aux_loop_nand : std_logic;
Begin
aux_loop_and := '1';
aux_loop_nand := '1';
for m in 0 to C_AUX_RST_WIDTH - 1 loop
aux_loop_and := aux_loop_and and asr_lpf(m);
aux_loop_nand := aux_loop_nand and not asr_lpf(m);
End loop;
asr_and <= aux_loop_and;
asr_nand <= aux_loop_nand;
end process;
end imp;
-------------------------------------------------------------------------------
-- proc_sys_reset - entity/architecture pair
-------------------------------------------------------------------------------
--
-- ************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2012 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: proc_sys_reset.vhd
-- Version: v4.00a
-- Description: Parameterizeable top level processor reset module.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure: This section should show the hierarchical structure of the
-- designs.Separate lines with blank lines if necessary to improve
-- readability.
--
-- proc_sys_reset.vhd
-- upcnt_n.vhd
-- lpf.vhd
-- sequence.vhd
-------------------------------------------------------------------------------
-- Author: rolandp
-- History:
-- kc 11/07/01 -- First version
--
-- kc 02/25/2002 -- Changed generic names C_EXT_RST_ACTIVE to
-- C_EXT_RESET_HIGH and C_AUX_RST_ACTIVE to
-- C_AUX_RESET_HIGH to match generics used in
-- MicroBlaze. Added the DCM Lock as an input
-- to keep reset active until after the Lock
-- is valid.
-- lcw 10/11/2004 -- Updated for NCSim
-- Ravi 09/14/2006 -- Added Attributes for synthesis
-- rolandp 04/16/2007 -- version 2.00a
-- ~~~~~~~
-- SK 03/11/10
-- ^^^^^^^
-- 1. Updated the core so support the active low "Interconnect_aresetn" and
-- "Peripheral_aresetn" signals.
-- ^^^^^^^
-- ~~~~~~~
-- SK 05/12/11
-- ^^^^^^^
-- 1. Updated the core so remove the support for PPC related functionality.
-- ^^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library proc_sys_reset_v5_0_10;
use proc_sys_reset_v5_0_10.all;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
-- Definition of Generics:
-- C_EXT_RST_WIDTH -- External Reset Low Pass Filter setting
-- C_AUX_RST_WIDTH -- Auxiliary Reset Low Pass Filter setting
-- C_EXT_RESET_HIGH -- External Reset Active High or Active Low
-- C_AUX_RESET_HIGH -= Auxiliary Reset Active High or Active Low
-- C_NUM_BUS_RST -- Number of Bus Structures reset to generate
-- C_NUM_PERP_RST -- Number of Peripheral resets to generate
--
-- C_NUM_INTERCONNECT_ARESETN -- No. of Active low reset to interconnect
-- C_NUM_PERP_ARESETN -- No. of Active low reset to peripheral
-- Definition of Ports:
-- slowest_sync_clk -- Clock
-- ext_reset_in -- External Reset Input
-- aux_reset_in -- Auxiliary Reset Input
-- mb_debug_sys_rst -- MDM Reset Input
-- dcm_locked -- DCM Locked, hold system in reset until 1
-- mb_reset -- MB core reset out
-- bus_struct_reset -- Bus structure reset out
-- peripheral_reset -- Peripheral reset out
-- interconnect_aresetn -- Interconnect Bus structure registered rst out
-- peripheral_aresetn -- Active Low Peripheral registered reset out
-------------------------------------------------------------------------------
entity proc_sys_reset is
generic (
C_FAMILY : string := "virtex7";
C_EXT_RST_WIDTH : integer := 4;
C_AUX_RST_WIDTH : integer := 4;
C_EXT_RESET_HIGH : std_logic := '0'; -- High active input
C_AUX_RESET_HIGH : std_logic := '1'; -- High active input
C_NUM_BUS_RST : integer := 1;
C_NUM_PERP_RST : integer := 1;
C_NUM_INTERCONNECT_ARESETN : integer := 1; -- 3/15/2010
C_NUM_PERP_ARESETN : integer := 1 -- 3/15/2010
);
port (
slowest_sync_clk : in std_logic;
ext_reset_in : in std_logic;
aux_reset_in : in std_logic;
-- from MDM
mb_debug_sys_rst : in std_logic;
-- DCM locked information
dcm_locked : in std_logic := '1';
-- -- from PPC
-- Core_Reset_Req_0 : in std_logic;
-- Chip_Reset_Req_0 : in std_logic;
-- System_Reset_Req_0 : in std_logic;
-- Core_Reset_Req_1 : in std_logic;
-- Chip_Reset_Req_1 : in std_logic;
-- System_Reset_Req_1 : in std_logic;
-- RstcPPCresetcore_0 : out std_logic := '0';
-- RstcPPCresetchip_0 : out std_logic := '0';
-- RstcPPCresetsys_0 : out std_logic := '0';
-- RstcPPCresetcore_1 : out std_logic := '0';
-- RstcPPCresetchip_1 : out std_logic := '0';
-- RstcPPCresetsys_1 : out std_logic := '0';
-- to Microblaze active high reset
mb_reset : out std_logic := '0';
-- active high resets
bus_struct_reset : out std_logic_vector(0 to C_NUM_BUS_RST - 1)
:= (others => '0');
peripheral_reset : out std_logic_vector(0 to C_NUM_PERP_RST - 1)
:= (others => '0');
-- active low resets
interconnect_aresetn : out
std_logic_vector(0 to (C_NUM_INTERCONNECT_ARESETN-1))
:= (others => '1');
peripheral_aresetn : out std_logic_vector(0 to (C_NUM_PERP_ARESETN-1))
:= (others => '1')
);
end entity proc_sys_reset;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture imp of proc_sys_reset is
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-- signal Core_Reset_Req_0_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_0_d3 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d1 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d2 : std_logic := '0'; -- delayed Core_Reset_Req
-- signal Core_Reset_Req_1_d3 : std_logic := '0'; -- delayed Core_Reset_Req
signal core_cnt_en_0 : std_logic := '0'; -- Core_Reset_Req_0 counter enable
signal core_cnt_en_1 : std_logic := '0'; -- Core_Reset_Req_1 counter enable
signal core_req_edge_0 : std_logic := '1'; -- Rising edge of Core_Reset_Req_0
signal core_req_edge_1 : std_logic := '1'; -- Rising edge of Core_Reset_Req_1
signal core_cnt_0 : std_logic_vector(3 downto 0); -- core counter output
signal core_cnt_1 : std_logic_vector(3 downto 0); -- core counter output
signal lpf_reset : std_logic; -- Low pass filtered ext or aux
--signal Chip_Reset_Req : std_logic := '0';
--signal System_Reset_Req : std_logic := '0';
signal Bsr_out : std_logic;
signal Pr_out : std_logic;
-- signal Core_out : std_logic;
-- signal Chip_out : std_logic;
-- signal Sys_out : std_logic;
signal MB_out : std_logic;
-------------------------------------------------------------------------------
-- Attributes to synthesis
-------------------------------------------------------------------------------
attribute equivalent_register_removal: string;
attribute equivalent_register_removal of bus_struct_reset : signal is "no";
attribute equivalent_register_removal of peripheral_reset : signal is "no";
attribute equivalent_register_removal of interconnect_aresetn : signal is "no";
attribute equivalent_register_removal of peripheral_aresetn : signal is "no";
begin
-------------------------------------------------------------------------------
-- ---------------------
-- -- MB_RESET_HIGH_GEN: Generate active high reset for Micro-Blaze
-- ---------------------
-- MB_RESET_HIGH_GEN: if C_INT_RESET_HIGH = 1 generate
-- begin
MB_Reset_PROCESS: process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
mb_reset <= MB_out;
end if;
end process;
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Bus_Struct_Reset output(s)
-- ----------------------------------------------------------------------------
BSR_OUT_DFF: for i in 0 to (C_NUM_BUS_RST-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
bus_struct_reset(i) <= Bsr_out;
end if;
end process;
end generate BSR_OUT_DFF;
-- ---------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Interconnect_aresetn op(s)
-- ---------------------------------------------------------------------------
ACTIVE_LOW_BSR_OUT_DFF: for i in 0 to (C_NUM_INTERCONNECT_ARESETN-1) generate
BSR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
interconnect_aresetn(i) <= not (Bsr_out);
end if;
end process;
end generate ACTIVE_LOW_BSR_OUT_DFF;
-------------------------------------------------------------------------------
-- ----------------------------------------------------------------------------
-- -- This For-generate creates D-Flip Flops for the Peripheral_Reset output(s)
-- ----------------------------------------------------------------------------
PR_OUT_DFF: for i in 0 to (C_NUM_PERP_RST-1) generate
PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_reset(i) <= Pr_out;
end if;
end process;
end generate PR_OUT_DFF;
-- ----------------------------------------------------------------------------
-- This For-generate creates D-Flip Flops for the Peripheral_aresetn op(s)
-- ----------------------------------------------------------------------------
ACTIVE_LOW_PR_OUT_DFF: for i in 0 to (C_NUM_PERP_ARESETN-1) generate
ACTIVE_LOW_PR_DFF : process (slowest_sync_clk)
begin
if (slowest_sync_clk'event and slowest_sync_clk = '1') then
peripheral_aresetn(i) <= not(Pr_out);
end if;
end process;
end generate ACTIVE_LOW_PR_OUT_DFF;
-------------------------------------------------------------------------------
-- This process defines the RstcPPCreset and MB_Reset outputs
-------------------------------------------------------------------------------
-- Rstc_output_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_0 <= not (core_cnt_0(3) and core_cnt_0(2) and
-- core_cnt_0(1) and core_cnt_0(0))
-- or Core_out;
-- RstcPPCresetchip_0 <= Chip_out;
-- RstcPPCresetsys_0 <= Sys_out;
-- end if;
-- end process;
-- Rstc_output_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- RstcPPCresetcore_1 <= not (core_cnt_1(3) and core_cnt_1(2) and
-- core_cnt_1(1) and core_cnt_1(0))
-- or Core_out;
-- RstcPPCresetchip_1 <= Chip_out;
-- RstcPPCresetsys_1 <= Sys_out;
-- end if;
-- end process;
-------------------------------------------------------------------------------
---------------------------------------------------------------------------------
---- This process delays signals so the the edge can be detected and used
---- Double register to sync up with slowest_sync_clk
---------------------------------------------------------------------------------
-- DELAY_PROCESS_0: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_0_d1 <= Core_Reset_Req_0;
-- core_reset_req_0_d2 <= core_reset_req_0_d1;
-- core_reset_req_0_d3 <= core_reset_req_0_d2;
-- end if;
-- end process;
--
-- DELAY_PROCESS_1: process (Slowest_sync_clk)
-- begin
-- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- core_reset_req_1_d1 <= Core_Reset_Req_1;
-- core_reset_req_1_d2 <= core_reset_req_1_d1;
-- core_reset_req_1_d3 <= core_reset_req_1_d2;
-- end if;
-- end process;
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This instantiates a counter to ensure the Core_Reset_Req_* will genereate a
-- ** -- -- RstcPPCresetcore_* that is a mimimum of 15 clocks
-- ** -- -------------------------------------------------------------------------------
-- ** -- CORE_RESET_0 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_0, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_0, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_0 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- CORE_RESET_1 : entity proc_sys_reset_v5_0_10.UPCNT_N
-- ** -- generic map (C_SIZE => 4)
-- ** -- port map(
-- ** -- Data => "0000", -- in STD_LOGIC_VECTOR (C_SIZE-1 downto 0);
-- ** -- Cnt_en => core_cnt_en_1, -- in STD_LOGIC;
-- ** -- Load => '0', -- in STD_LOGIC;
-- ** -- Clr => core_req_edge_1, -- in STD_LOGIC;
-- ** -- Clk => Slowest_sync_clk, -- in STD_LOGIC;
-- ** -- Qout => core_cnt_1 -- out STD_LOGIC_VECTOR (C_SIZE-1 downto 0)
-- ** -- );
-- ** --
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- CORE_RESET_PROCESS
-- ** -- -------------------------------------------------------------------------------
-- ** -- -- This generates the reset pulse and the count enable to core reset counter
-- ** -- --
-- ** -- CORE_RESET_PROCESS_0: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_0 <= not (core_cnt_0(3) and core_cnt_0(2) and core_cnt_0(1));
-- ** -- --or not core_req_edge_0;
-- ** -- --core_req_edge_0 <= not(Core_Reset_Req_0_d2 and not Core_Reset_Req_0_d3);
-- ** -- end if;
-- ** -- end process;
-- ** --
-- ** -- CORE_RESET_PROCESS_1: process (Slowest_sync_clk)
-- ** -- begin
-- ** -- if (Slowest_sync_clk'event and Slowest_sync_clk = '1') then
-- ** -- core_cnt_en_1 <= not (core_cnt_1(3) and core_cnt_1(2) and core_cnt_1(1));
-- ** -- --or not core_req_edge_1;
-- ** -- --core_req_edge_1 <= not(Core_Reset_Req_1_d2 and not Core_Reset_Req_1_d3);
-- ** -- end if;
-- ** -- end process;
-------------------------------------------------------------------------------
-- This instantiates a low pass filter to filter both External and Auxiliary
-- Reset Inputs.
-------------------------------------------------------------------------------
EXT_LPF : entity proc_sys_reset_v5_0_10.LPF
generic map (
C_EXT_RST_WIDTH => C_EXT_RST_WIDTH,
C_AUX_RST_WIDTH => C_AUX_RST_WIDTH,
C_EXT_RESET_HIGH => C_EXT_RESET_HIGH,
C_AUX_RESET_HIGH => C_AUX_RESET_HIGH
)
port map(
MB_Debug_Sys_Rst => mb_debug_sys_rst, -- in std_logic
Dcm_locked => dcm_locked, -- in std_logic
External_System_Reset => ext_reset_in, -- in std_logic
Auxiliary_System_Reset => aux_reset_in, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Lpf_reset => lpf_reset -- out std_logic
);
-------------------------------------------------------------------------------
-- This instantiates the sequencer
-- This controls the time between resets becoming inactive
-------------------------------------------------------------------------------
-- System_Reset_Req <= System_Reset_Req_0 or System_Reset_Req_1;
-- Chip_Reset_Req <= Chip_Reset_Req_0 or Chip_Reset_Req_1;
SEQ : entity proc_sys_reset_v5_0_10.SEQUENCE_PSR
--generic map (
-- C_EXT_RESET_HIGH_1 => C_EXT_RESET_HIGH
--)
port map(
Lpf_reset => lpf_reset, -- in std_logic
--System_Reset_Req => '0', -- System_Reset_Req, -- in std_logic
--Chip_Reset_Req => '0', -- Chip_Reset_Req, -- in std_logic
Slowest_Sync_Clk => slowest_sync_clk, -- in std_logic
Bsr_out => Bsr_out, -- out std_logic
Pr_out => Pr_out, -- out std_logic
--Core_out => open, -- Core_out, -- out std_logic
--Chip_out => open, -- Chip_out, -- out std_logic
--Sys_out => open, -- Sys_out, -- out std_logic
MB_out => MB_out); -- out std_logic
end imp;
--END_SINGLE_FILE_TAG
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9984)
`protect data_block
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`protect begin_protected
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|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
use WORK.alu_types.all;
entity ALU is
generic (
N : integer := NSUMG
);
port (
FUNC: in TYPE_OP;
A, B: in std_logic_vector(N-1 downto 0);
CLK: in std_logic;
RESET: in std_logic;
OUTALU: out std_logic_vector(N-1 downto 0)
);
end ALU;
architecture Behavioral of ALU is
component P4ADDER
generic(N:integer:=NSUMG);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
OVERFLOW: out std_logic;
Cout: out std_logic
);
end component;
component COMPARATOR
generic(N:integer:=NSUMG);
port(
SUM: in std_logic_vector(N-1 downto 0);
Cout: in std_logic;
OVERFLOW: in std_logic;
mod_op: in TYPE_OP;
comp_result : out std_logic_vector(N-1 downto 0)
);
end component;
component T2logic
generic(N:integer:=NSUMG);
port(
R1 : in std_logic_vector(N-1 downto 0);
R2 : in std_logic_vector(N-1 downto 0);
S1 : in std_logic;
S2 : in std_logic;
S3 : in std_logic;
L_OUT : out std_logic_vector(N-1 downto 0)
);
end component;
component bshift -- barrel shifter
generic(N:integer:=NSUMG);
port (
direction : in std_logic; -- '1' for left, '0' for right
logical : in std_logic; -- '1' for logical, '0' for arithmetic
shift : in std_logic_vector(4 downto 0); -- shift count
input : in std_logic_vector (N-1 downto 0);
output : out std_logic_vector (N-1 downto 0)
);
end component;
component REGISTER_FD
generic (
N: integer := 1
);
port (
DIN: in std_logic_vector(N-1 downto 0); -- Data in
CLK: in std_logic; -- Clock
RESET: in std_logic; -- Reset
DOUT: out std_logic_vector(N-1 downto 0) -- Data out
);
end component;
-- component BOOTHMUL
-- generic (
-- N : integer := NSUMG
-- );
-- port (
-- A : in std_logic_vector(N-1 downto 0);
-- B : in std_logic_vector(N-1 downto 0);
-- P : out std_logic_vector(2*N-1 downto 0)
-- );
-- end component;
component MUX4TO1
generic (
N: integer := NSUMG -- Number of bits
);
port (
A: in std_logic_vector(N-1 downto 0);
B: in std_logic_vector(N-1 downto 0);
C: in std_logic_vector(N-1 downto 0);
D: in std_logic_vector(N-1 downto 0);
SEL: in std_logic_vector(1 downto 0);
Y: out std_logic_vector(N-1 downto 0)
);
end component;
signal logical: std_logic;
signal s_depth: std_logic_vector(4 downto 0);
signal dir: std_logic;
-- signal MUL_A: std_logic_vector(N-1 downto 0);
-- signal MUL_B: std_logic_vector(N-1 downto 0);
signal logic_A: std_logic_vector(N-1 downto 0);
signal logic_B: std_logic_vector(N-1 downto 0);
signal int_A: std_logic_vector(N-1 downto 0);
signal shift_A: std_logic_vector(N-1 downto 0);
signal int_B: std_logic_vector(N-1 downto 0);
signal Cin : std_logic:='0';
signal S1,S2,S3: std_logic:='0';
signal cout: std_logic;
signal int_SUM: std_logic_vector(N-1 downto 0);
signal L_OUT: std_logic_vector(N-1 downto 0);
signal shift_out: std_logic_vector(N-1 downto 0);
-- signal MUL_OUT: std_logic_vector(2*N-1 downto 0);
signal MUX_SEL: std_logic_vector(1 downto 0);
signal preout: std_logic_vector(N-1 downto 0);
signal comp_result: std_logic_vector(N-1 downto 0);
signal comp_op: TYPE_OP;
signal overflow: std_logic;
begin
P_ALU : process (FUNC, A, B)
begin
case FUNC is
when ALUADD =>
-- report "Adder w/ A: " & integer'image(to_integer(unsigned(A))) & " - B: " & integer'image(to_integer(unsigned(B)));
int_A <= A;
int_B <= B;
Cin <= '0';
MUX_SEL <= "00";
when ALUSUB =>
-- report "Subtracting " & integer'image(conv_integer(signed(A))) & " and " & integer'image(conv_integer(signed(not B)));
int_A <= A;
int_B <= not B;
Cin <= '1';
MUX_SEL <= "00";
-- when MULT => MUL_A <= A;
-- MUL_B <= B;
-- MUX_SEL <= "100";
-- Bitwise
when ALUAND =>
logic_A <= A;
logic_B <= B;
S1 <= '0';
S2 <= '0';
S3 <= '1';
MUX_SEL <= "01";
when ALUOR => logic_A <= A;
logic_B <= B;
S1 <= '1';
S2 <= '1';
S3 <= '1';
MUX_SEL <= "01";
when ALUXOR => logic_A <= A;
logic_B <= B;
S1 <= '1';
S2 <= '1';
S3 <= '0';
MUX_SEL <= "01";
when ALUSLL =>
shift_A <= A;
s_depth <= B(4 downto 0);
dir <= '1';
logical <= '1';
MUX_SEL <= "11";
when ALUSRL =>
shift_A <= A;
s_depth <= B(4 downto 0);
dir <= '0';
logical <= '1';
MUX_SEL <= "11";
when ALUSRA =>
shift_A <= A;
s_depth <= B(4 downto 0);
dir <= '0';
logical <= '0';
MUX_SEL <= "11";
when ALUSEQ | ALUSLE | ALUSNE | ALUSGE | ALUSGT |
ALUSLT | ALUSLEU | ALUSLTU | ALUSGEU | ALUSGTU =>
int_A <= A;
int_B <= not B;
Cin <= '1';
MUX_SEL <= "10";
comp_op <= FUNC;
when others =>
int_A <= (others => '0');
int_B <= (others => '0');
logic_A <= (others => '0');
logic_B <= (others => '0');
shift_A <= (others => '0');
comp_op <= (others => '0');
s_depth <= (others => '0');
Cin <= '0';
logical <= '0';
dir <= '0';
end case;
end process;
-- report integer'image(A) & string'(" - ") & integer'image(A_IN) & string'(" => ") & integer'image(result);
ADDER: P4ADDER port map (int_A,int_B,cin,int_SUM,overflow,cout);
--report integer'image(A) & string'(" - ") & integer'image(A_IN) & string'(" => ") & integer'image(int_SUM);
LOGIC: t2logic port map (logic_A,logic_B,S1,S2,S3,L_OUT);
COMPARE: comparator port map (int_SUM,cout,overflow,comp_op,comp_result);
--flag_reg(6) <= cout nand cin; --overflow flag
SHIFTER: bshift port map (dir,logical,s_depth,shift_A,shift_out);
-- MULTIPLIER: BOOTHMUL port map (MUL_A,MUL_B,MUL_OUT);
-- MUL_LSB <= MUL_OUT(N-1 downto 0);
MULTIPLEXER: MUX4TO1 port map(int_SUM,L_OUT,comp_result,shift_out,MUX_SEL,preout);
-- OUTPUT: REGISTER_FD generic map( NSUMG ) port map (preout,CLK,RESET,OUTALU);
OUTALU <= preout;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
library altera_mf;
-- pragma translate_off
use altera_mf.altpll;
-- pragma translate_on
entity clkgen_de0 is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of clkgen_de0 is
component altpll
generic (
intended_device_family : string := "Stratix" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "CLK0" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "ZERO_DELAY_BUFFER",
compensate_clock => "CLK2",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10,
clk2_multiply_by => clk_mul, clk2_divide_by => clk_div)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= clkout(2);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone II",
operation_mode => "NORMAL",
inclk0_input_frequency => clk_period,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => 5, clk1_divide_by => 10)
port map (inclk => inclk, clk => clkout, locked => locked);
e0 <= '0';
end generate;
end;
|
----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
use work.debug.all;
library grlib;
use grlib.stdlib.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(24 downto 0);
signal data : std_logic_vector(31 downto 24);
signal pio : std_logic_vector(17 downto 0);
signal genio : std_logic_vector(59 downto 0);
signal romsn : std_logic;
signal oen : std_ulogic;
signal writen : std_ulogic;
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal wdogn,wdogn_local : std_logic;
signal txd1, rxd1 : std_logic;
signal txd2, rxd2 : std_logic;
signal ctsn1, rtsn1 : std_ulogic;
signal ctsn2, rtsn2 : std_ulogic;
signal erx_dv, erx_dv_d, etx_en: std_logic:='0';
signal erxd, erxd_d, etxd: std_logic_vector(7 downto 0):=(others=>'0');
signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
signal emdint : std_ulogic;
signal etx_clk : std_ulogic;
signal erx_clk : std_ulogic := '0';
signal ps2clk : std_logic_vector(1 downto 0);
signal ps2data : std_logic_vector(1 downto 0);
signal clk2 : std_ulogic := '0';
signal clk125 : std_ulogic := '0';
signal iic_scl : std_ulogic;
signal iic_sda : std_ulogic;
signal ddc_scl : std_ulogic;
signal ddc_sda : std_ulogic;
signal dvi_iic_scl : std_logic;
signal dvi_iic_sda : std_logic;
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1) := (others => '0');
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal tft_lcd_data : std_logic_vector(11 downto 0);
signal tft_lcd_clk_p : std_ulogic;
signal tft_lcd_clk_n : std_ulogic;
signal tft_lcd_hsync : std_ulogic;
signal tft_lcd_vsync : std_ulogic;
signal tft_lcd_de : std_ulogic;
signal tft_lcd_reset_b : std_ulogic;
-- DDR2 memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic := '0';
signal ddr_we : std_ulogic; -- write enable
signal ddr_ras : std_ulogic; -- ras
signal ddr_cas : std_ulogic; -- cas
signal ddr_dm : std_logic_vector(1 downto 0); -- dm
signal ddr_dqs : std_logic_vector(1 downto 0); -- dqs
signal ddr_dqsn : std_logic_vector(1 downto 0); -- dqsn
signal ddr_ad : std_logic_vector(12 downto 0); -- address
signal ddr_ba : std_logic_vector(2 downto 0); -- bank address
signal ddr_dq : std_logic_vector(15 downto 0); -- data
signal ddr_dq2 : std_logic_vector(15 downto 0); -- data
signal ddr_odt : std_logic;
signal ddr_rzq : std_logic;
signal ddr_zio : std_logic;
-- SPI flash
signal spi_sel_n : std_ulogic;
signal spi_clk : std_ulogic;
signal spi_mosi : std_ulogic;
signal dsurst : std_ulogic;
signal errorn : std_logic;
signal switch : std_logic_vector(9 downto 0); -- I/O port
signal led : std_logic_vector(3 downto 0); -- I/O port
signal erx_er : std_logic := '0';
signal erx_col : std_logic := '0';
signal erx_crs : std_logic := '1';
signal etx_er : std_logic := '0';
constant lresp : boolean := false;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
clk125 <= not clk125 after 10 ns;
--erx_clk <= not erx_clk after 4 ns;
clk2 <= '0'; --not clk2 after 5 ns;
rst <= dsurst and wdogn_local;
rxd1 <= 'H'; ctsn1 <= '0';
rxd2 <= 'H'; ctsn2 <= '0';
ps2clk <= "HH"; ps2data <= "HH";
pio(4) <= pio(5); pio(1) <= pio(2); pio <= (others => 'H');
wdogn <= 'H';
wdogn_local <= 'H';
switch(7) <= '1';
switch(8) <= '0';
emdio <= 'H';
spw_rxdp <= spw_txdp; spw_rxdn <= spw_txdn;
spw_rxsp <= spw_txsp; spw_rxsn <= spw_txsn;
cpu : entity work.leon3mp
generic map ( fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (rst, clk, clk2, clk125, wdogn, address(24 downto 0), data,
oen, writen, romsn,
ddr_clk, ddr_clkb, ddr_cke, ddr_odt, ddr_we, ddr_ras, ddr_csb ,ddr_cas, ddr_dm,
ddr_dqs, ddr_dqsn, ddr_ad, ddr_ba, ddr_dq, ddr_rzq, ddr_zio,
txd1, rxd1, ctsn1, rtsn1, txd2, rxd2, ctsn2, rtsn2, pio, genio,
switch, led, erx_clk, emdio, erxd(3 downto 0)'delayed(1 ns), erx_dv'delayed(1 ns), emdint,
etx_clk, etxd(3 downto 0), etx_en, emdc,
ps2clk, ps2data, iic_scl, iic_sda, ddc_scl, ddc_sda,
dvi_iic_scl, dvi_iic_sda,
tft_lcd_data, tft_lcd_clk_p, tft_lcd_clk_n, tft_lcd_hsync,
tft_lcd_vsync, tft_lcd_de, tft_lcd_reset_b,
spw_clk, spw_rxdp, spw_rxdn,
spw_rxsp, spw_rxsn, spw_txdp, spw_txdn, spw_txsp, spw_txsn,
spi_sel_n, spi_clk, spi_mosi
);
prom0 : sram generic map (index => 6, abits => romdepth, fname => promfile)
port map (address(romdepth-1 downto 0), data(31 downto 24), romsn,
writen, oen);
ddr2mem : if (CFG_MIG_DDR2 = 1) generate
u1: ddr2ram
generic map (width => 16, abits => 13, babits => 3,
colbits => 10, rowbits => 13, implbanks => 1,
fname => sdramfile, lddelay => (340 us),
speedbin => 1)
port map (ck => ddr_clk, ckn => ddr_clkb, cke => ddr_cke, csn => ddr_csb,
odt => ddr_odt, rasn => ddr_ras, casn => ddr_cas, wen => ddr_we,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad,
dq => ddr_dq, dqs => ddr_dqs, dqsn => ddr_dqsn);
end generate;
ps2devs: for i in 0 to 1 generate
ps2_device(ps2clk(i), ps2data(i));
end generate ps2devs;
errorn <= led(1);
errorn <= 'H'; -- ERROR pull-up
phy0 : if (CFG_GRETH = 1) generate
emdio <= 'H';
p0: phy
generic map(
address => 1,
extended_regs => 1,
aneg => 1,
base100_t4 => 1,
base100_x_fd => 1,
base100_x_hd => 1,
fd_10 => 1,
hd_10 => 1,
base100_t2_fd => 1,
base100_t2_hd => 1,
base1000_x_fd => 1,
base1000_x_hd => 1,
base1000_t_fd => 1,
base1000_t_hd => 1,
rmii => 0,
rgmii => 1
)
port map(rst, emdio, open, erx_clk, erxd_d, erx_dv_d,
erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc, clk125);
end generate;
rcxclkp : process(erx_clk) is
begin
erxd <= erxd_d;
erx_dv <= erx_dv_d;
end process;
wdognp : process
begin
wdogn_local <= 'H';
if wdogn = '0' then
wdogn_local <= '0';
wait for 1 ms;
end if;
wait for 20 ns;
end process;
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 320 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 201 us;
wait for 2500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#2e#, txp);
wait for 25000 ns;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0D#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#70#, 16#11#, 16#78#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#0D#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
txa(dsutx, 16#00#, 16#00#, 16#20#, 16#00#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#44#, txp);
wait;
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#aa#, txp);
txa(dsutx, 16#00#, 16#55#, 16#00#, 16#55#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#00#, 16#00#, 16#0a#, 16#a0#, txp);
txa(dsutx, 16#01#, 16#02#, 16#09#, 16#33#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#80#, 16#00#, 16#02#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(txd2, rxd2);
wait;
end process;
iuerr : process
begin
wait until dsurst = '1';
wait for 5000 ns;
if to_x01(errorn) = '1' then wait on errorn; end if;
assert (to_x01(errorn) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
end ;
|
package STRSYN is
attribute SigDir : string;
attribute SigType : string;
attribute SigBias : string;
end STRSYN;
entity sklp is
port (
terminal in1: electrical;
terminal out1: electrical;
terminal vbias4: electrical;
terminal gnd: electrical;
terminal vdd: electrical;
terminal vbias1: electrical;
terminal vbias2: electrical;
terminal vbias3: electrical;
terminal vref: electrical);
end sklp;
architecture simple of sklp is
-- Attributes for Ports
attribute SigDir of in1:terminal is "input";
attribute SigType of in1:terminal is "voltage";
attribute SigDir of out1:terminal is "output";
attribute SigType of out1:terminal is "voltage";
attribute SigDir of vbias4:terminal is "reference";
attribute SigType of vbias4:terminal is "voltage";
attribute SigDir of gnd:terminal is "reference";
attribute SigType of gnd:terminal is "current";
attribute SigBias of gnd:terminal is "negative";
attribute SigDir of vdd:terminal is "reference";
attribute SigType of vdd:terminal is "current";
attribute SigBias of vdd:terminal is "positive";
attribute SigDir of vbias1:terminal is "reference";
attribute SigType of vbias1:terminal is "voltage";
attribute SigDir of vbias2:terminal is "reference";
attribute SigType of vbias2:terminal is "voltage";
attribute SigDir of vbias3:terminal is "reference";
attribute SigType of vbias3:terminal is "voltage";
attribute SigDir of vref:terminal is "reference";
attribute SigType of vref:terminal is "current";
attribute SigBias of vref:terminal is "negative";
terminal net1: electrical;
terminal net2: electrical;
terminal net3: electrical;
terminal net4: electrical;
terminal net5: electrical;
terminal net6: electrical;
terminal net7: electrical;
begin
subnet0_subnet0_subnet0_m1 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.85e-06,
W => Wdiff_0,
Wdiff_0init => 1.65e-06,
scope => private
)
port map(
D => net3,
G => net1,
S => net5
);
subnet0_subnet0_subnet0_m2 : entity nmos(behave)
generic map(
L => Ldiff_0,
Ldiff_0init => 1.85e-06,
W => Wdiff_0,
Wdiff_0init => 1.65e-06,
scope => private
)
port map(
D => net2,
G => out1,
S => net5
);
subnet0_subnet0_subnet0_m3 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => W_0,
W_0init => 4.5e-06
)
port map(
D => net5,
G => vbias4,
S => gnd
);
subnet0_subnet0_subnet1_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcm_2,
Wcm_2init => 8e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net2,
G => net2,
S => vdd
);
subnet0_subnet0_subnet1_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcmout_2,
Wcmout_2init => 7.49e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net4,
G => net2,
S => vdd
);
subnet0_subnet0_subnet2_m1 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcm_2,
Wcm_2init => 8e-07,
scope => private,
symmetry_scope => sym_5
)
port map(
D => net3,
G => net3,
S => vdd
);
subnet0_subnet0_subnet2_m2 : entity pmos(behave)
generic map(
L => Lcm_2,
Lcm_2init => 7.1e-06,
W => Wcmout_2,
Wcmout_2init => 7.49e-05,
scope => private,
symmetry_scope => sym_5
)
port map(
D => out1,
G => net3,
S => vdd
);
subnet0_subnet0_subnet3_m1 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.25e-06,
W => Wcm_1,
Wcm_1init => 6.45e-06,
scope => private
)
port map(
D => net4,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_m2 : entity nmos(behave)
generic map(
L => Lcm_1,
Lcm_1init => 7.25e-06,
W => Wcmcout_1,
Wcmcout_1init => 6.48e-05,
scope => private
)
port map(
D => out1,
G => net4,
S => gnd
);
subnet0_subnet0_subnet3_c1 : entity cap(behave)
generic map(
C => Ccurmir_1,
scope => private
)
port map(
P => out1,
N => net4
);
subnet0_subnet1_subnet0_m1 : entity pmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => (pfak)*(WBias),
WBiasinit => 2.025e-05
)
port map(
D => vbias1,
G => vbias1,
S => vdd
);
subnet0_subnet1_subnet0_m2 : entity pmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.6e-06,
W => (pfak)*(WBias),
WBiasinit => 2.025e-05
)
port map(
D => vbias2,
G => vbias2,
S => vbias1
);
subnet0_subnet1_subnet0_i1 : entity idc(behave)
generic map(
I => 1.145e-05
)
port map(
P => vdd,
N => vbias3
);
subnet0_subnet1_subnet0_m3 : entity nmos(behave)
generic map(
L => (pfak)*(LBias),
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => vbias3,
G => vbias3,
S => vbias4
);
subnet0_subnet1_subnet0_m4 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => vbias2,
G => vbias3,
S => net6
);
subnet0_subnet1_subnet0_m5 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => vbias4,
G => vbias4,
S => gnd
);
subnet0_subnet1_subnet0_m6 : entity nmos(behave)
generic map(
L => LBias,
LBiasinit => 5.6e-06,
W => WBias,
WBiasinit => 2.025e-05
)
port map(
D => net6,
G => vbias4,
S => gnd
);
subnet1_subnet0_r1 : entity res(behave)
generic map(
R => 200000
)
port map(
P => net7,
N => in1
);
subnet1_subnet0_r2 : entity res(behave)
generic map(
R => 603000
)
port map(
P => net7,
N => net1
);
subnet1_subnet0_c2 : entity cap(behave)
generic map(
C => 1.07e-11
)
port map(
P => net7,
N => out1
);
subnet1_subnet0_c1 : entity cap(behave)
generic map(
C => 4e-12
)
port map(
P => net1,
N => vref
);
end simple;
|
library ieee;
use ieee.std_logic_1164.all;
package mask_pkg is
constant MASK: std_logic_vector(0 downto 0);
end package;
package body mask_pkg is
constant MASK: std_logic_vector(0 downto 0) := "0";
end package body;
library ieee;
use ieee.std_logic_1164.all;
entity my_entity is
port (
data: out std_logic_vector(0 downto 0)
);
end entity;
use work.mask_pkg.all;
architecture arch of my_entity is
begin
data <= MASK;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divider is
port (
clk_in : in STD_LOGIC;
clk_out : out STD_LOGIC;
reset : in STD_LOGIC
);
end clock_divider;
architecture behavioral of clock_divider is
signal t : STD_LOGIC := '0';
signal counter : integer range 0 to 500 := 0;
begin
process(clk_in, t)
begin
if rising_edge(clk_in) then
if (reset = '1') then
counter <= 0;
t <= '0';
else
if (counter = 500) then
counter <= 0;
if (t = '0') then
t <= '1';
else
t <= '0';
end if;
else
counter <= counter + 1;
end if;
end if;
end if;
clk_out <= t;
end process;
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: leon3s
-- File: leon3s.vhd
-- Author: Jan Andersson, Aeroflex Gaisler
-- Description: Top-level LEON3 component
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
library gaisler;
use gaisler.leon3.all;
entity leon3s is
generic (
hindex : integer := 0;
fabtech : integer range 0 to NTECH := DEFFABTECH;
memtech : integer := DEFMEMTECH;
nwindows : integer range 2 to 32 := 8;
dsu : integer range 0 to 1 := 0;
fpu : integer range 0 to 31 := 0;
v8 : integer range 0 to 63 := 0;
cp : integer range 0 to 1 := 0;
mac : integer range 0 to 1 := 0;
pclow : integer range 0 to 2 := 2;
notag : integer range 0 to 1 := 0;
nwp : integer range 0 to 4 := 0;
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 3 := 2;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
dcen : integer range 0 to 1 := 0;
drepl : integer range 0 to 3 := 2;
dsets : integer range 1 to 4 := 1;
dlinesize : integer range 4 to 8 := 4;
dsetsize : integer range 1 to 256 := 1;
dsetlock : integer range 0 to 1 := 0;
dsnoop : integer range 0 to 6 := 0;
ilram : integer range 0 to 1 := 0;
ilramsize : integer range 1 to 512 := 1;
ilramstart : integer range 0 to 255 := 16#8e#;
dlram : integer range 0 to 1 := 0;
dlramsize : integer range 1 to 512 := 1;
dlramstart : integer range 0 to 255 := 16#8f#;
mmuen : integer range 0 to 1 := 0;
itlbnum : integer range 2 to 64 := 8;
dtlbnum : integer range 2 to 64 := 8;
tlb_type : integer range 0 to 3 := 1;
tlb_rep : integer range 0 to 1 := 0;
lddel : integer range 1 to 2 := 2;
disas : integer range 0 to 2 := 0;
tbuf : integer range 0 to 128 := 0;
pwd : integer range 0 to 2 := 2;
svt : integer range 0 to 1 := 1;
rstaddr : integer := 0;
smp : integer range 0 to 15 := 0;
cached : integer := 0;
scantest : integer := 0;
mmupgsz : integer range 0 to 5 := 0;
bp : integer := 1;
npasi : integer range 0 to 1 := 0;
pwrpsr : integer range 0 to 1 := 0;
rex : integer range 0 to 1 := 0;
altwin : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
ahbi : in ahb_mst_in_type;
ahbo : out ahb_mst_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : in ahb_slv_out_vector;
irqi : in l3_irq_in_type;
irqo : out l3_irq_out_type;
dbgi : in l3_debug_in_type;
dbgo : out l3_debug_out_type
);
end;
architecture rtl of leon3s is
signal gnd, vcc : std_logic;
signal fpuo : grfpu_out_type;
begin
gnd <= '0'; vcc <= '1';
fpuo <= grfpu_out_none;
leon3x0 : leon3x
generic map (
hindex => hindex,
fabtech => fabtech,
memtech => memtech,
nwindows => nwindows,
dsu => dsu,
fpu => fpu,
v8 => v8,
cp => cp,
mac => mac,
pclow => pclow,
notag => notag,
nwp => nwp,
icen => icen,
irepl => irepl,
isets => isets,
ilinesize => ilinesize,
isetsize => isetsize,
isetlock => isetlock,
dcen => dcen,
drepl => drepl,
dsets => dsets,
dlinesize => dlinesize,
dsetsize => dsetsize,
dsetlock => dsetlock,
dsnoop => dsnoop,
ilram => ilram,
ilramsize => ilramsize,
ilramstart => ilramstart,
dlram => dlram,
dlramsize => dlramsize,
dlramstart => dlramstart,
mmuen => mmuen,
itlbnum => itlbnum,
dtlbnum => dtlbnum,
tlb_type => tlb_type,
tlb_rep => tlb_rep,
lddel => lddel,
disas => disas,
tbuf => tbuf,
pwd => pwd,
svt => svt,
rstaddr => rstaddr,
smp => smp,
iuft => 0,
fpft => 0,
cmft => 0,
iuinj => 0,
ceinj => 0,
cached => cached,
clk2x => 0,
netlist => 0,
scantest => scantest,
mmupgsz => mmupgsz,
bp => bp,
npasi => npasi,
pwrpsr => pwrpsr,
rex => rex,
altwin => altwin)
port map (
clk => gnd,
gclk2 => clk,
gfclk2 => clk,
clk2 => clk,
rstn => rstn,
ahbi => ahbi,
ahbo => ahbo,
ahbsi => ahbsi,
ahbso => ahbso,
irqi => irqi,
irqo => irqo,
dbgi => dbgi,
dbgo => dbgo,
fpui => open,
fpuo => fpuo,
clken => vcc
);
end;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pkg.vhd
--
-- Description:
-- This is the demo testbench package file for fifo_generator_v8.4 core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
PACKAGE fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC;
------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME;
------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER;
------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector;
------------------------
COMPONENT fg_tb_rng IS
GENERIC (WIDTH : integer := 8;
SEED : integer := 3);
PORT (
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
ENABLE : IN STD_LOGIC;
RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dgen IS
GENERIC (
C_DIN_WIDTH : INTEGER := 32;
C_DOUT_WIDTH : INTEGER := 32;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT (
RESET : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
PRC_WR_EN : IN STD_LOGIC;
FULL : IN STD_LOGIC;
WR_EN : OUT STD_LOGIC;
WR_DATA : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END COMPONENT;
------------------------
COMPONENT fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING := "NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT fg_tb_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END COMPONENT;
------------------------
COMPONENT TX_SEND_FIFO_top IS
PORT (
CLK : IN std_logic;
SRST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(32-1 DOWNTO 0);
DOUT : OUT std_logic_vector(32-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
END COMPONENT;
------------------------
END fg_tb_pkg;
PACKAGE BODY fg_tb_pkg IS
FUNCTION divroundup (
data_value : INTEGER;
divisor : INTEGER)
RETURN INTEGER IS
VARIABLE div : INTEGER;
BEGIN
div := data_value/divisor;
IF ( (data_value MOD divisor) /= 0) THEN
div := div+1;
END IF;
RETURN div;
END divroundup;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : STD_LOGIC;
false_case : STD_LOGIC)
RETURN STD_LOGIC IS
VARIABLE retval : STD_LOGIC := '0';
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : TIME;
false_case : TIME)
RETURN TIME IS
VARIABLE retval : TIME := 0 ps;
BEGIN
IF condition=false THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
-------------------------------
FUNCTION log2roundup (
data_value : INTEGER)
RETURN INTEGER IS
VARIABLE width : INTEGER := 0;
VARIABLE cnt : INTEGER := 1;
BEGIN
IF (data_value <= 1) THEN
width := 1;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
------------------------------------------------------------------------------
-- hexstr_to_std_logic_vec
-- This function converts a hex string to a std_logic_vector
------------------------------------------------------------------------------
FUNCTION hexstr_to_std_logic_vec(
arg1 : string;
size : integer )
RETURN std_logic_vector IS
VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0');
VARIABLE bin : std_logic_vector(3 DOWNTO 0);
VARIABLE index : integer := 0;
BEGIN
FOR i IN arg1'reverse_range LOOP
CASE arg1(i) IS
WHEN '0' => bin := (OTHERS => '0');
WHEN '1' => bin := (0 => '1', OTHERS => '0');
WHEN '2' => bin := (1 => '1', OTHERS => '0');
WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0');
WHEN '4' => bin := (2 => '1', OTHERS => '0');
WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0');
WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0');
WHEN '7' => bin := (3 => '0', OTHERS => '1');
WHEN '8' => bin := (3 => '1', OTHERS => '0');
WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0');
WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1');
WHEN 'B' => bin := (2 => '0', OTHERS => '1');
WHEN 'b' => bin := (2 => '0', OTHERS => '1');
WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1');
WHEN 'D' => bin := (1 => '0', OTHERS => '1');
WHEN 'd' => bin := (1 => '0', OTHERS => '1');
WHEN 'E' => bin := (0 => '0', OTHERS => '1');
WHEN 'e' => bin := (0 => '0', OTHERS => '1');
WHEN 'F' => bin := (OTHERS => '1');
WHEN 'f' => bin := (OTHERS => '1');
WHEN OTHERS =>
FOR j IN 0 TO 3 LOOP
bin(j) := 'X';
END LOOP;
END CASE;
FOR j IN 0 TO 3 LOOP
IF (index*4)+j < size THEN
result((index*4)+j) := bin(j);
END IF;
END LOOP;
index := index + 1;
END LOOP;
RETURN result;
END hexstr_to_std_logic_vec;
END fg_tb_pkg;
|
-------------------------------------------------------------------------------
-- axi_bram_ctrl.vhd
-------------------------------------------------------------------------------
--
--
-- (c) Copyright [2010 - 2011] Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--
-------------------------------------------------------------------------------
-- Filename: axi_bram_ctrl_wrapper.vhd
--
-- Description: This file is the top level module for the AXI BRAM
-- controller IP core.
--
-- VHDL-Standard: VHDL'93
--
-------------------------------------------------------------------------------
-- Structure:
-- axi_bram_ctrl.vhd (v3_0)
-- |
-- |--axi_bram_ctrl_top.vhd
-- |
-- |-- full_axi.vhd
-- | -- sng_port_arb.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- wr_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- | -- rd_chnl.vhd
-- | -- wrap_brst.vhd
-- | -- ua_narrow.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- checkbit_handler_64.vhd
-- | -- (same helper components as checkbit_handler)
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- correct_one_bit_64.vhd
-- | -- ecc_gen.vhd
-- |
-- |-- axi_lite.vhd
-- | -- lite_ecc_reg.vhd
-- | -- axi_lite_if.vhd
-- | -- checkbit_handler.vhd
-- | -- xor18.vhd
-- | -- parity.vhd
-- | -- correct_one_bit.vhd
-- | -- ecc_gen.vhd
--
-------------------------------------------------------------------------------
-- Library declarations
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.numeric_std.all;
library work;
use work.axi_bram_ctrl_top;
use work.axi_bram_ctrl_funcs.all;
use work.coregen_comp_defs.all;
------------------------------------------------------------------------------
entity axi_bram_ctrl is
generic (
C_BRAM_INST_MODE : string := "EXTERNAL"; -- external ; internal
--determines whether the bmg is external or internal to axi bram ctrl wrapper
C_MEMORY_DEPTH : integer := 4096;
--Memory depth specified by the user
C_BRAM_ADDR_WIDTH : integer := 12;
-- Width of AXI address bus (in bits)
C_S_AXI_ADDR_WIDTH : integer := 32;
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH : integer := 32;
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH : INTEGER := 4;
-- AXI ID vector width
C_S_AXI_PROTOCOL : string := "AXI4";
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST : INTEGER := 1;
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM : INTEGER := 0;
-- Enable single port usage of BRAM
-- C_FAMILY : string := "virtex6";
-- Specify the target architecture type
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH : integer := 32;
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH : integer := 32;
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC : integer := 0;
-- Enables or disables ECC functionality
C_FAULT_INJECT : integer := 0;
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE : integer := 1
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
);
port (
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
ecc_interrupt : out std_logic := '0';
ecc_ue : out std_logic := '0';
-- axi write address channel Signals (AW)
s_axi_awid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_awaddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awlock : in std_logic;
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
-- axi write data channel Signals (W)
s_axi_wdata : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_wstrb : in std_logic_vector(C_S_AXI_DATA_WIDTH/8-1 downto 0);
s_axi_wlast : in std_logic;
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
-- axi write data response Channel Signals (B)
s_axi_bid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
-- axi read address channel Signals (AR)
s_axi_arid : in std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_araddr : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arlock : in std_logic;
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
-- axi read data channel Signals (R)
s_axi_rid : out std_logic_vector(C_S_AXI_ID_WIDTH-1 downto 0);
s_axi_rdata : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
-- axi-lite ecc register Interface Signals
-- axi-lite clock and Reset
-- note: axi-lite control IF and AXI IF share the same clock.
-- s_axi_ctrl_aclk : in std_logic;
-- s_axi_ctrl_aresetn : in std_logic;
-- axi-lite write address Channel Signals (AW)
s_axi_ctrl_awvalid : in std_logic;
s_axi_ctrl_awready : out std_logic;
s_axi_ctrl_awaddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
-- axi-lite write data Channel Signals (W)
s_axi_ctrl_wdata : in std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_wvalid : in std_logic;
s_axi_ctrl_wready : out std_logic;
-- axi-lite write data Response Channel Signals (B)
s_axi_ctrl_bresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_bvalid : out std_logic;
s_axi_ctrl_bready : in std_logic;
-- axi-lite read address Channel Signals (AR)
s_axi_ctrl_araddr : in std_logic_vector(C_S_AXI_CTRL_ADDR_WIDTH-1 downto 0);
s_axi_ctrl_arvalid : in std_logic;
s_axi_ctrl_arready : out std_logic;
-- axi-lite read data Channel Signals (R)
s_axi_ctrl_rdata : out std_logic_vector(C_S_AXI_CTRL_DATA_WIDTH-1 downto 0);
s_axi_ctrl_rresp : out std_logic_vector(1 downto 0);
s_axi_ctrl_rvalid : out std_logic;
s_axi_ctrl_rready : in std_logic;
-- bram interface signals (Port A)
bram_rst_a : out std_logic;
bram_clk_a : out std_logic;
bram_en_a : out std_logic;
bram_we_a : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_a : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_a : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_a : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-- bram interface signals (Port B)
bram_rst_b : out std_logic;
bram_clk_b : out std_logic;
bram_en_b : out std_logic;
bram_we_b : out std_logic_vector (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_addr_b : out std_logic_vector (C_S_AXI_ADDR_WIDTH-1 downto 0);
bram_wrdata_b : out std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
bram_rddata_b : in std_logic_vector (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0)
);
end entity axi_bram_ctrl;
-------------------------------------------------------------------------------
architecture implementation of axi_bram_ctrl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
------------------------------------------------------------------------------
-- FUNCTION: if_then_else
-- This function is used to implement an IF..THEN when such a statement is not
-- allowed.
------------------------------------------------------------------------------
FUNCTION if_then_else (
condition : BOOLEAN;
true_case : INTEGER;
false_case : INTEGER)
RETURN INTEGER IS
VARIABLE retval : INTEGER := 0;
BEGIN
IF NOT condition THEN
retval:=false_case;
ELSE
retval:=true_case;
END IF;
RETURN retval;
END if_then_else;
---------------------------------------------------------------------------
-- FUNCTION : log2roundup
---------------------------------------------------------------------------
FUNCTION log2roundup (data_value : integer) RETURN integer IS
VARIABLE width : integer := 0;
VARIABLE cnt : integer := 1;
CONSTANT lower_limit : integer := 1;
CONSTANT upper_limit : integer := 8;
BEGIN
IF (data_value <= 1) THEN
width := 0;
ELSE
WHILE (cnt < data_value) LOOP
width := width + 1;
cnt := cnt *2;
END LOOP;
END IF;
RETURN width;
END log2roundup;
-------------------------------------------------------------------------------
-- Constants
-------------------------------------------------------------------------------
-- Only instantiate logic based on C_S_AXI_PROTOCOL.
-- Determine external ECC width.
-- Use function defined in axi_bram_ctrl_funcs package.
-- Set internal parameters for ECC register enabling when C_ECC = 1
-- Catastrophic error indicated with ECC_UE & Interrupt flags.
-- Counter only sized when C_ECC = 1.
-- Selects CE counter width/threshold to assert ECC_Interrupt
-- Hard coded at 8-bits to capture and count up to 256 correctable errors.
-- ECC algorithm format, 0 = Hamming code, 1 = Hsiao code
constant GND : std_logic := '0';
constant VCC : std_logic := '1';
constant ZERO1 : std_logic_vector(0 downto 0) := (others => '0');
constant ZERO2 : std_logic_vector(1 downto 0) := (others => '0');
constant ZERO3 : std_logic_vector(2 downto 0) := (others => '0');
constant ZERO4 : std_logic_vector(3 downto 0) := (others => '0');
constant ZERO8 : std_logic_vector(7 downto 0) := (others => '0');
constant WSTRB_ZERO : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
constant ZERO16 : std_logic_vector(15 downto 0) := (others => '0');
constant ZERO32 : std_logic_vector(31 downto 0) := (others => '0');
constant ZERO64 : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
CONSTANT MEM_TYPE : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,2);
CONSTANT BWE_B : INTEGER := if_then_else((C_SINGLE_PORT_BRAM=1),0,1);
CONSTANT BMG_ADDR_WIDTH : INTEGER := log2roundup(C_MEMORY_DEPTH) + log2roundup(C_S_AXI_DATA_WIDTH/8) ;
-------------------------------------------------------------------------------
-- Signals
-------------------------------------------------------------------------------
signal clka_bram_clka_i : std_logic := '0';
signal rsta_bram_rsta_i : std_logic := '0';
signal ena_bram_ena_i : std_logic := '0';
signal REGCEA : std_logic := '0';
signal wea_bram_wea_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addra_bram_addra_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dina_bram_dina_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal douta_bram_douta_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
signal clkb_bram_clkb_i : std_logic := '0';
signal rstb_bram_rstb_i : std_logic := '0';
signal enb_bram_enb_i : std_logic := '0';
signal REGCEB : std_logic := '0';
signal web_bram_web_i : std_logic_vector(C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal addrb_bram_addrb_i : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0) := (others => '0');
signal dinb_bram_dinb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0) := (others => '0');
signal doutb_bram_doutb_i : std_logic_vector(C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))-1 downto 0);
-----------------------------------------------------------------------
-- Architecture Body
-----------------------------------------------------------------------
begin
gint_inst: IF (C_BRAM_INST_MODE = "INTERNAL" ) GENERATE
begin
bmgv80_inst : blk_mem_gen_v8_0
GENERIC MAP(
----------------------------------------------------------------------------
-- Generic Declarations
----------------------------------------------------------------------------
--Device Family & Elaboration Directory Parameters:
C_FAMILY => "virtex7" ,
C_XDEVICEFAMILY => "virtex7" ,
---- C_ELABORATION_DIR => "NULL" ,
C_INTERFACE_TYPE => 0 ,
--General Memory Parameters:
----- C_ENABLE_32BIT_ADDRESS => 0 ,
C_MEM_TYPE => MEM_TYPE ,
C_BYTE_SIZE => 8 ,
C_ALGORITHM => 1 ,
C_PRIM_TYPE => 1 ,
--Memory Initialization Parameters:
C_LOAD_INIT_FILE => 0 ,
C_INIT_FILE_NAME => "no_coe_file_loaded" ,
C_USE_DEFAULT_DATA => 0 ,
C_DEFAULT_DATA => "NULL" ,
--Port A Parameters:
--Reset Parameters:
C_HAS_RSTA => 0 ,
--Enable Parameters:
C_HAS_ENA => 1 ,
C_HAS_REGCEA => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEA => 1 ,
C_WEA_WIDTH => (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_A => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_A => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_A => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_A => C_MEMORY_DEPTH ,
C_READ_DEPTH_A => C_MEMORY_DEPTH ,
C_ADDRA_WIDTH => log2roundup(C_MEMORY_DEPTH) ,
--Port B Parameters:
--Reset Parameters:
C_HAS_RSTB => 0 ,
--Enable Parameters:
C_HAS_ENB => 1 ,
C_HAS_REGCEB => 0 ,
--Byte Write Enable Parameters:
C_USE_BYTE_WEB => BWE_B ,
C_WEB_WIDTH => (C_S_AXI_DATA_WIDTH/8 + C_ECC*(1+(C_S_AXI_DATA_WIDTH/128))) ,
--Write Mode:
C_WRITE_MODE_B => "WRITE_FIRST" ,
--Data-Addr Width Parameters:
C_WRITE_WIDTH_B => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_READ_WIDTH_B => (C_S_AXI_DATA_WIDTH+C_ECC*8*(1+(C_S_AXI_DATA_WIDTH/128))) ,
C_WRITE_DEPTH_B => C_MEMORY_DEPTH ,
C_READ_DEPTH_B => C_MEMORY_DEPTH ,
C_ADDRB_WIDTH => log2roundup(C_MEMORY_DEPTH) ,
--Output Registers/ Pipelining Parameters:
C_HAS_MEM_OUTPUT_REGS_A => 0 ,
C_HAS_MEM_OUTPUT_REGS_B => 0 ,
C_HAS_MUX_OUTPUT_REGS_A => 0 ,
C_HAS_MUX_OUTPUT_REGS_B => 0 ,
C_MUX_PIPELINE_STAGES => 0 ,
--Input/Output Registers for SoftECC :
C_HAS_SOFTECC_INPUT_REGS_A => 0 ,
C_HAS_SOFTECC_OUTPUT_REGS_B=> 0 ,
--ECC Parameters
C_USE_ECC => 0 ,
C_USE_SOFTECC => 0 ,
C_HAS_INJECTERR => 0 ,
--Simulation Model Parameters:
C_SIM_COLLISION_CHECK => "NONE" ,
C_COMMON_CLK => 1 ,
C_DISABLE_WARN_BHV_COLL => 1 ,
C_DISABLE_WARN_BHV_RANGE => 1
)
PORT MAP(
----------------------------------------------------------------------------
-- Input and Output Declarations
----------------------------------------------------------------------------
-- Native BMG Input and Output Port Declarations
--Port A:
clka => clka_bram_clka_i ,
rsta => rsta_bram_rsta_i ,
ena => ena_bram_ena_i ,
regcea => GND ,
wea => wea_bram_wea_i ,
addra => addra_bram_addra_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addra => addra_bram_addra_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dina => dina_bram_dina_i ,
douta => douta_bram_douta_i ,
--port b:
clkb => clkb_bram_clkb_i ,
rstb => rstb_bram_rstb_i ,
enb => enb_bram_enb_i ,
regceb => GND ,
web => web_bram_web_i ,
addrb => addrb_bram_addrb_i(BMG_ADDR_WIDTH-1 downto (BMG_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
--addrb => addrb_bram_addrb_i(C_S_AXI_ADDR_WIDTH-1 downto (C_S_AXI_ADDR_WIDTH - C_BRAM_ADDR_WIDTH)) ,
dinb => dinb_bram_dinb_i ,
doutb => doutb_bram_doutb_i ,
--ecc:
injectsbiterr => GND ,
injectdbiterr => GND ,
sbiterr => OPEN ,
dbiterr => OPEN ,
rdaddrecc => OPEN ,
-- axi bmg input and output Port Declarations
-- axi global signals
s_aclk => GND ,
s_aresetn => GND ,
-- axi full/lite slave write (write side)
s_axi_awid => ZERO4 ,
s_axi_awaddr => ZERO32 ,
s_axi_awlen => ZERO8 ,
s_axi_awsize => ZERO3 ,
s_axi_awburst => ZERO2 ,
s_axi_awvalid => GND ,
s_axi_awready => OPEN ,
s_axi_wdata => ZERO64 ,
s_axi_wstrb => WSTRB_ZERO ,
s_axi_wlast => GND ,
s_axi_wvalid => GND ,
s_axi_wready => OPEN ,
s_axi_bid => OPEN ,
s_axi_bresp => OPEN ,
s_axi_bvalid => OPEN ,
s_axi_bready => GND ,
-- axi full/lite slave read (Write side)
s_axi_arid => OPEN ,
s_axi_araddr => OPEN ,
s_axi_arlen => OPEN ,
s_axi_arsize => OPEN ,
s_axi_arburst => OPEN ,
s_axi_arvalid => OPEN ,
s_axi_arready => OPEN ,
s_axi_rid => OPEN ,
s_axi_rdata => OPEN ,
s_axi_rresp => OPEN ,
s_axi_rlast => OPEN ,
s_axi_rvalid => OPEN ,
s_axi_rready => GND ,
-- axi full/lite sideband Signals
s_axi_injectsbiterr => GND ,
s_axi_injectdbiterr => GND ,
s_axi_sbiterr => OPEN ,
s_axi_dbiterr => OPEN ,
s_axi_rdaddrecc => OPEN
);
abcv3_0_int_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
S_AXI_ACLK => S_AXI_ACLK ,
S_AXI_ARESETN => S_AXI_ARESETN ,
ECC_Interrupt => ECC_Interrupt ,
ECC_UE => ECC_UE ,
-- AXI Write Address Channel Signals (AW)
S_AXI_AWID => S_AXI_AWID ,
S_AXI_AWADDR => S_AXI_AWADDR ,
S_AXI_AWLEN => S_AXI_AWLEN ,
S_AXI_AWSIZE => S_AXI_AWSIZE ,
S_AXI_AWBURST => S_AXI_AWBURST ,
S_AXI_AWLOCK => S_AXI_AWLOCK ,
S_AXI_AWCACHE => S_AXI_AWCACHE ,
S_AXI_AWPROT => S_AXI_AWPROT ,
S_AXI_AWVALID => S_AXI_AWVALID ,
S_AXI_AWREADY => S_AXI_AWREADY ,
-- AXI Write Data Channel Signals (W)
S_AXI_WDATA => S_AXI_WDATA ,
S_AXI_WSTRB => S_AXI_WSTRB ,
S_AXI_WLAST => S_AXI_WLAST ,
S_AXI_WVALID => S_AXI_WVALID ,
S_AXI_WREADY => S_AXI_WREADY ,
-- AXI Write Data Response Channel Signals (B)
S_AXI_BID => S_AXI_BID ,
S_AXI_BRESP => S_AXI_BRESP ,
S_AXI_BVALID => S_AXI_BVALID ,
S_AXI_BREADY => S_AXI_BREADY ,
-- AXI Read Address Channel Signals (AR)
S_AXI_ARID => S_AXI_ARID ,
S_AXI_ARADDR => S_AXI_ARADDR ,
S_AXI_ARLEN => S_AXI_ARLEN ,
S_AXI_ARSIZE => S_AXI_ARSIZE ,
S_AXI_ARBURST => S_AXI_ARBURST ,
S_AXI_ARLOCK => S_AXI_ARLOCK ,
S_AXI_ARCACHE => S_AXI_ARCACHE ,
S_AXI_ARPROT => S_AXI_ARPROT ,
S_AXI_ARVALID => S_AXI_ARVALID ,
S_AXI_ARREADY => S_AXI_ARREADY ,
-- AXI Read Data Channel Signals (R)
S_AXI_RID => S_AXI_RID ,
S_AXI_RDATA => S_AXI_RDATA ,
S_AXI_RRESP => S_AXI_RRESP ,
S_AXI_RLAST => S_AXI_RLAST ,
S_AXI_RVALID => S_AXI_RVALID ,
S_AXI_RREADY => S_AXI_RREADY ,
-- AXI-Lite ECC Register Interface Signals
-- AXI-Lite Write Address Channel Signals (AW)
S_AXI_CTRL_AWVALID => S_AXI_CTRL_AWVALID ,
S_AXI_CTRL_AWREADY => S_AXI_CTRL_AWREADY ,
S_AXI_CTRL_AWADDR => S_AXI_CTRL_AWADDR ,
-- AXI-Lite Write Data Channel Signals (W)
S_AXI_CTRL_WDATA => S_AXI_CTRL_WDATA ,
S_AXI_CTRL_WVALID => S_AXI_CTRL_WVALID ,
S_AXI_CTRL_WREADY => S_AXI_CTRL_WREADY ,
-- AXI-Lite Write Data Response Channel Signals (B)
S_AXI_CTRL_BRESP => S_AXI_CTRL_BRESP ,
S_AXI_CTRL_BVALID => S_AXI_CTRL_BVALID ,
S_AXI_CTRL_BREADY => S_AXI_CTRL_BREADY ,
-- AXI-Lite Read Address Channel Signals (AR)
S_AXI_CTRL_ARADDR => S_AXI_CTRL_ARADDR ,
S_AXI_CTRL_ARVALID => S_AXI_CTRL_ARVALID ,
S_AXI_CTRL_ARREADY => S_AXI_CTRL_ARREADY ,
-- AXI-Lite Read Data Channel Signals (R)
S_AXI_CTRL_RDATA => S_AXI_CTRL_RDATA ,
S_AXI_CTRL_RRESP => S_AXI_CTRL_RRESP ,
S_AXI_CTRL_RVALID => S_AXI_CTRL_RVALID ,
S_AXI_CTRL_RREADY => S_AXI_CTRL_RREADY ,
-- BRAM Interface Signals (Port A)
BRAM_Rst_A => rsta_bram_rsta_i ,
BRAM_Clk_A => clka_bram_clka_i ,
BRAM_En_A => ena_bram_ena_i ,
BRAM_WE_A => wea_bram_wea_i ,
BRAM_Addr_A => addra_bram_addra_i,
BRAM_WrData_A => dina_bram_dina_i ,
BRAM_RdData_A => douta_bram_douta_i ,
-- BRAM Interface Signals (Port B)
BRAM_Rst_B => rstb_bram_rstb_i ,
BRAM_Clk_B => clkb_bram_clkb_i ,
BRAM_En_B => enb_bram_enb_i ,
BRAM_WE_B => web_bram_web_i ,
BRAM_Addr_B => addrb_bram_addrb_i ,
BRAM_WrData_B => dinb_bram_dinb_i ,
BRAM_RdData_B => doutb_bram_doutb_i
);
-- The following signals are driven 0's to remove the synthesis warnings
bram_rst_a <= '0';
bram_clk_a <= '0';
bram_en_a <= '0';
bram_we_a <= (others => '0');
bram_addr_a <= (others => '0');
bram_wrdata_a <= (others => '0');
bram_rst_b <= '0';
bram_clk_b <= '0';
bram_en_b <= '0';
bram_we_b <= (others => '0');
bram_addr_b <= (others => '0');
bram_wrdata_b <= (others => '0');
END GENERATE gint_inst; -- End of internal bram instance
gext_inst: IF (C_BRAM_INST_MODE = "EXTERNAL" ) GENERATE
abcv3_0_ext_inst : entity work.axi_bram_ctrl_top
generic map(
-- AXI Parameters
C_BRAM_ADDR_WIDTH => C_BRAM_ADDR_WIDTH ,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH ,
-- Width of AXI address bus (in bits)
C_S_AXI_DATA_WIDTH => C_S_AXI_DATA_WIDTH ,
-- Width of AXI data bus (in bits)
C_S_AXI_ID_WIDTH => C_S_AXI_ID_WIDTH ,
-- AXI ID vector width
C_S_AXI_PROTOCOL => C_S_AXI_PROTOCOL ,
-- Set to AXI4LITE to optimize out burst transaction support
C_S_AXI_SUPPORTS_NARROW_BURST => C_S_AXI_SUPPORTS_NARROW_BURST ,
-- Support for narrow burst operations
C_SINGLE_PORT_BRAM => C_SINGLE_PORT_BRAM ,
-- Enable single port usage of BRAM
-- AXI-Lite Register Parameters
C_S_AXI_CTRL_ADDR_WIDTH => C_S_AXI_CTRL_ADDR_WIDTH ,
-- Width of AXI-Lite address bus (in bits)
C_S_AXI_CTRL_DATA_WIDTH => C_S_AXI_CTRL_DATA_WIDTH ,
-- Width of AXI-Lite data bus (in bits)
-- ECC Parameters
C_ECC => C_ECC ,
-- Enables or disables ECC functionality
C_FAULT_INJECT => C_FAULT_INJECT ,
-- Enable fault injection registers
-- (default = disabled)
C_ECC_ONOFF_RESET_VALUE => C_ECC_ONOFF_RESET_VALUE
-- By default, ECC checking is on
-- (can disable ECC @ reset by setting this to 0)
)
port map(
-- AXI Interface Signals
-- AXI Clock and Reset
s_axi_aclk => s_axi_aclk ,
s_axi_aresetn => s_axi_aresetn ,
ecc_interrupt => ecc_interrupt ,
ecc_ue => ecc_ue ,
-- axi write address channel signals (aw)
s_axi_awid => s_axi_awid ,
s_axi_awaddr => s_axi_awaddr ,
s_axi_awlen => s_axi_awlen ,
s_axi_awsize => s_axi_awsize ,
s_axi_awburst => s_axi_awburst ,
s_axi_awlock => s_axi_awlock ,
s_axi_awcache => s_axi_awcache ,
s_axi_awprot => s_axi_awprot ,
s_axi_awvalid => s_axi_awvalid ,
s_axi_awready => s_axi_awready ,
-- axi write data channel signals (w)
s_axi_wdata => s_axi_wdata ,
s_axi_wstrb => s_axi_wstrb ,
s_axi_wlast => s_axi_wlast ,
s_axi_wvalid => s_axi_wvalid ,
s_axi_wready => s_axi_wready ,
-- axi write data response channel signals (b)
s_axi_bid => s_axi_bid ,
s_axi_bresp => s_axi_bresp ,
s_axi_bvalid => s_axi_bvalid ,
s_axi_bready => s_axi_bready ,
-- axi read address channel signals (ar)
s_axi_arid => s_axi_arid ,
s_axi_araddr => s_axi_araddr ,
s_axi_arlen => s_axi_arlen ,
s_axi_arsize => s_axi_arsize ,
s_axi_arburst => s_axi_arburst ,
s_axi_arlock => s_axi_arlock ,
s_axi_arcache => s_axi_arcache ,
s_axi_arprot => s_axi_arprot ,
s_axi_arvalid => s_axi_arvalid ,
s_axi_arready => s_axi_arready ,
-- axi read data channel signals (r)
s_axi_rid => s_axi_rid ,
s_axi_rdata => s_axi_rdata ,
s_axi_rresp => s_axi_rresp ,
s_axi_rlast => s_axi_rlast ,
s_axi_rvalid => s_axi_rvalid ,
s_axi_rready => s_axi_rready ,
-- axi-lite ecc register interface signals
-- axi-lite write address channel signals (aw)
s_axi_ctrl_awvalid => s_axi_ctrl_awvalid ,
s_axi_ctrl_awready => s_axi_ctrl_awready ,
s_axi_ctrl_awaddr => s_axi_ctrl_awaddr ,
-- axi-lite write data channel signals (w)
s_axi_ctrl_wdata => s_axi_ctrl_wdata ,
s_axi_ctrl_wvalid => s_axi_ctrl_wvalid ,
s_axi_ctrl_wready => s_axi_ctrl_wready ,
-- axi-lite write data response channel signals (b)
s_axi_ctrl_bresp => s_axi_ctrl_bresp ,
s_axi_ctrl_bvalid => s_axi_ctrl_bvalid ,
s_axi_ctrl_bready => s_axi_ctrl_bready ,
-- axi-lite read address channel signals (ar)
s_axi_ctrl_araddr => s_axi_ctrl_araddr ,
s_axi_ctrl_arvalid => s_axi_ctrl_arvalid ,
s_axi_ctrl_arready => s_axi_ctrl_arready ,
-- axi-lite read data channel signals (r)
s_axi_ctrl_rdata => s_axi_ctrl_rdata ,
s_axi_ctrl_rresp => s_axi_ctrl_rresp ,
s_axi_ctrl_rvalid => s_axi_ctrl_rvalid ,
s_axi_ctrl_rready => s_axi_ctrl_rready ,
-- bram interface signals (port a)
bram_rst_a => bram_rst_a ,
bram_clk_a => bram_clk_a ,
bram_en_a => bram_en_a ,
bram_we_a => bram_we_a ,
bram_addr_a => bram_addr_a ,
bram_wrdata_a => bram_wrdata_a ,
bram_rddata_a => bram_rddata_a ,
-- bram interface signals (port b)
bram_rst_b => bram_rst_b ,
bram_clk_b => bram_clk_b ,
bram_en_b => bram_en_b ,
bram_we_b => bram_we_b ,
bram_addr_b => bram_addr_b ,
bram_wrdata_b => bram_wrdata_b ,
bram_rddata_b => bram_rddata_b
);
END GENERATE gext_inst; -- End of internal bram instance
end architecture implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MUX_RF_NRD is
Port (
nrd : in STD_LOGIC_VECTOR (5 downto 0);
r7 : in STD_LOGIC_VECTOR (5 downto 0);
rf_dtn : in STD_LOGIC;
out_nrd : out STD_LOGIC_VECTOR (5 downto 0)
);
end MUX_RF_NRD;
architecture Behavioral of MUX_RF_NRD is
begin
process(nrd,r7,rf_dtn)
begin
if(rf_dtn = '0')then
out_nrd <= nrd;
elsif(rf_dtn = '1')then
out_nrd <= r7;
end if;
end process;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:49:05 07/20/2006
-- Design Name:
-- Module Name: icapCTRL - icapCTRL_rtl
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity icapCTRL is
generic (
C_FAMILY : string := "virtex2P";
C_ICAP_DWIDTH : integer:= 8;
C_BURST_SIZE : natural := 32; -- Number of DWords
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := b"10_0000_0000"; --DCR_BaseAddr
C_DCR_HIGHADDR : std_logic_vector(9 downto 0) := b"00_0000_0011"; --DCR_HighAddr, not used
C_COUNT_ADDR : std_logic_vector(31 downto 0) := X"00000010"
);
port (
clk : in std_logic;
reset : in std_logic;
start : in std_logic_vector(1 downto 0);
M_rdAddr_o : out std_logic_vector(31 downto 0);
M_rdReq_o : out std_logic;
M_rdNum_o : out std_logic_vector(4 downto 0);
M_rdAccept_i : in std_logic;
M_rdData_i : in std_logic_vector(63 downto 0);
M_rdAck_i : in std_logic;
M_rdComp_i : in std_logic;
M_wrAddr_o : out std_logic_vector(31 downto 0);
M_wrReq_o : out std_logic;
M_wrNum_o : out std_logic_vector(4 downto 0);
M_wrAccept_i : in std_logic;
M_wrData_o : out std_logic_vector(63 downto 0);
M_wrRdy_i : in std_logic;
M_wrAck_i : in std_logic;
M_wrComp_i : in std_logic;
--- Interrupt
done_int : out std_logic;
--- DCR signals
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
-- chipscope output
BUSY : out std_ulogic;
O : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
CE : out std_ulogic;
I : out std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
WRITE : out std_ulogic;
DCR_ABus_o : out std_logic_vector(9 downto 0);
DCR_Write_o : out std_logic;
DCR_Din_o : out std_logic_vector(31 downto 0)
);
end icapCTRL;
architecture icapCTRL_rtl of icapCTRL is
function log2(x : natural) return integer is
variable i : integer := 0;
begin
if x = 0 then
return 0;
else
while 2**i < x loop
i := i+1;
end loop;
return i;
end if;
end function log2;
component ICAP_VIRTEX2
port (
BUSY : out std_ulogic;
O : out std_logic_vector(7 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(7 downto 0);
WRITE : in std_ulogic
);
end component;
component ICAP_VIRTEX4
generic (
ICAP_WIDTH : string := "X32" -- "X8" or "X32"
);
port (
BUSY : out std_ulogic;
O : out std_logic_vector(31 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
I : in std_logic_vector(31 downto 0);
WRITE : in std_ulogic
);
end component;
component icapFIFO
generic (
C_FIFO_DEPTH : integer := 64;
C_DIN_WIDTH : integer := 64;
C_DOUT_WIDTH : integer := 8
);
port (
clk : in std_logic;
reset : in std_logic;
wEn_i : in std_logic;
wData_i : in std_logic_vector(C_DIN_WIDTH-1 downto 0);
rEn_i : in std_logic;
rData_o : out std_logic_vector(C_DOUT_WIDTH-1 downto 0);
full_o : out std_logic;
empty_o : out std_logic
);
end component;
component dcr_if is
generic (
C_DCR_BASEADDR : std_logic_vector(9 downto 0) := B"00_0000_0000";
C_ON_INIT : std_logic := '0'
);
port (
clk : in std_logic;
rst : in std_logic;
DCR_ABus : in std_logic_vector(9 downto 0);
DCR_Sl_DBus : in std_logic_vector(31 downto 0);
DCR_Read : in std_logic;
DCR_Write : in std_logic;
Sl_dcrAck : out std_logic;
Sl_dcrDBus : out std_logic_vector(31 downto 0);
ctrl_reg : out std_logic_vector(31 downto 0)
);
end component;
type state_type is (IDLE, INIT, ACTIVE, BURSTING, WRITE_COUNT, DONE);
signal state : state_type;
--signal addr : std_logic_vector(14 downto 0);
--signal addr : std_logic_vector(13 downto 0);
signal addr : std_logic_vector(18-(log2(C_BURST_SIZE)) downto 0);
signal addr_tail : std_logic_vector(2+(log2(C_BURST_SIZE)) downto 0);
signal base_addr : std_logic_vector(31 downto 22);
signal base_lngth : std_logic_vector(15 downto 0);
signal icap_busy : std_logic;
signal icap_dout : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_din_r : std_logic_vector((C_ICAP_DWIDTH-1) downto 0);
signal icap_en_l : std_logic;
signal icap_rnw : std_logic;
signal fifo_rEn : std_logic;
signal fifo_wEn : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal count : std_logic_vector(31 downto 0);
signal debounce : std_logic_vector(1 downto 0);
signal dcr_reg : std_logic_vector(31 downto 0);
signal dcr_start_w : std_logic;
signal dcr_start_w_n : std_logic;
signal dcr_start_r : std_logic;
signal dcr_addr : std_logic_vector(31 downto 0);
signal ctrl_reg : std_logic_vector(31 downto 0);
signal Sl_dcrAck_sig : std_logic;
signal done_int_i : std_logic;
begin
addr_tail <= (others => '0');
-- if virtex2P or Virtex2 use ICAP_Virtex2 and invert input bits
V2_GEN : if (C_FAMILY = "virtex2p" or C_FAMILY = "virtex2") generate
V2_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_0 : ICAP_VIRTEX2
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
-- WARNING!!!
-- The ICAP's data signals are reversed in V2P!
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V2_GEN_8;
end generate V2_GEN;
V4_GEN : if (C_FAMILY = "virtex4") generate
V4_GEN_8 : if (C_ICAP_DWIDTH = 8) generate
ICAP_1 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X8") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
process(icap_din) begin
for i in 0 to 7 loop
icap_din_r(7-i) <= icap_din(i);
end loop;
end process;
end generate V4_GEN_8;
V4_GEN_32 : if (C_ICAP_DWIDTH = 32) generate
ICAP_2 : ICAP_VIRTEX4
generic map (
ICAP_WIDTH => "X32") -- "X8" or "X32"
port map (
BUSY => icap_busy, -- Busy output
O => icap_dout, -- 8-bit data output
CE => icap_en_l, -- Clock enable input
CLK => clk, -- Clock input
I => icap_din_r, -- 8-bit data input
WRITE => icap_rnw -- Write input
);
icap_din_r <= icap_din;
end generate V4_GEN_32;
end generate V4_GEN;
-- dcr interface instantiation
dcr_control: dcr_if
generic map (
C_DCR_BASEADDR => C_DCR_BASEADDR)
port map (
clk => clk,
rst => reset,
DCR_ABus => DCR_ABus,
DCR_Sl_DBus => DCR_Sl_DBus,
DCR_Read => DCR_Read,
DCR_Write => DCR_Write,
Sl_dcrAck => Sl_dcrAck_sig,
Sl_dcrDBus => Sl_dcrDBus,
ctrl_reg => ctrl_reg
);
icapFIFO_0 : icapFIFO
generic map (
C_FIFO_DEPTH => 64,
C_DIN_WIDTH => 64,
C_DOUT_WIDTH => C_ICAP_DWIDTH
)
port map (
clk => clk,
reset => reset,
wEn_i => fifo_wEn,
wData_i => M_rdData_i,
rEn_i => fifo_rEn,
rData_o => icap_din,
full_o => fifo_full,
empty_o => fifo_empty
);
-- fifo_empty is active high. If Fifo is not empty (fifo_empty = '0') rnw and ce gow low!
icap_rnw <= fifo_empty;
icap_en_l <= fifo_empty;
fifo_rEn <= not icap_busy;
dcr_start_w <= Sl_dcrAck_sig and DCR_Write;
Sl_dcrAck <= Sl_dcrAck_sig;
-- Make DCR signals available to chipscope at output
DCR_ABus_o <= DCR_ABus;
DCR_Write_o <= DCR_Write;
DCR_Din_o <= ctrl_reg;
-- Make icap signals available to chipscope at output
BUSY <= icap_busy; -- Busy output
O <= icap_dout; -- 8-bit data output
CE <= icap_en_l; -- Clock enable input
I <= icap_din; -- 8-bit data input
WRITE <= icap_rnw; -- Write input
fifo_wEn <= M_rdAck_i when(state=BURSTING) else '0';
-- Generate the read address
--M_rdAddr_o <= base_addr & addr & b"0000000";
--M_rdAddr_o <= base_addr & addr & b"00000000";
M_rdAddr_o <= base_addr & addr & addr_tail;
done_int <= done_int_i;
-- delay start signal by one cycle
process(clk) begin
if(clk='1' and clk'event) then
dcr_start_w_n <= dcr_start_w;
end if;
end process;
process(state, fifo_full, fifo_empty) begin
-- don't request data
M_rdReq_o <= '0';
M_rdNum_o <= "10000";
M_wrReq_o <= '0';
if(state=ACTIVE) then
M_rdReq_o <= not fifo_full;
elsif(state=WRITE_COUNT) then
M_wrReq_o <= fifo_empty;
end if;
end process;
M_wrAddr_o <= C_COUNT_ADDR;
M_wrNum_o <= "00001";
M_wrData_o(63 downto 32) <= (others=>'0');
M_wrData_o(31 downto 0) <= count;
process(clk) begin
if(clk='1' and clk'event) then
if(state=IDLE) then
count <= (others=>'0');
else
if(fifo_empty='0') then -- if Fifo is not empty increase counter
count <= count+1;
end if;
end if;
end if;
end process;
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
state <= IDLE;
addr <= (others=>'0');
base_addr <= (others=>'0');
base_lngth <= (others=>'0');
dcr_reg <= (others => '0');
done_int_i <= '0';
else
done_int_i <= '0';
case(state) is
when IDLE =>
addr <= (others=>'0');
-- initialize base addr and base_lngth with the data from DCR bus once!
base_addr <= ctrl_reg(31 downto 22);
base_lngth <= ctrl_reg(15 downto 0);
if(dcr_start_w_n='1') then
state <= ACTIVE;
end if;
when ACTIVE =>
if(M_rdAccept_i='1') then
addr <= addr + 1;
--dcr_reg(21 downto 7) <= dcr_reg(21 downto 7) + 1;
state <= BURSTING;
end if;
when BURSTING =>
if(M_rdComp_i='1') then
if(addr=base_lngth) then
state <= WRITE_COUNT;
else
state <= ACTIVE;
end if;
end if;
when WRITE_COUNT =>
if(M_wrAccept_i='1') then
state <= DONE;
end if;
when DONE =>
--if(fifo_empty = '1') then
done_int_i <= '1';
state <= IDLE;
--end if;
when others =>
state <= IDLE;
end case;
end if;
end if;
end process;
end icapCTRL_rtl;
|
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
ENTITY proc IS
end proc;
ARCHITECTURE Behavior OF proc IS
COMPONENT faG IS
GENERIC(N : POSITIVE := 8);
PORT(
A,B : IN std_logic_vector(N-1 DOWNTO 0);
Cin : IN std_logic;
S : OUT std_logic_vector(N-1 DOWNTO 0);
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL A,B, Cin, S, Cout : STD_LOGIC_VECTOR (8 DOWNTO 0);
BEGIN
A <= "0000001" after 10 ns;
B <= "0000010" after 2 ns;
add1 : faG GENERIC MAP(8) PORT MAP(A, B, '0', S, Cout);
ASSERT(S = "00000011") report "ERROR";
END ARCHITECTURE Behavior;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2669.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02669ent IS
END c13s03b01x00p02n01i02669ent;
ARCHITECTURE c13s03b01x00p02n01i02669arch OF c13s03b01x00p02n01i02669ent IS
BEGIN
TESTING: PROCESS
variable ]k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02669 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02669arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2669.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02669ent IS
END c13s03b01x00p02n01i02669ent;
ARCHITECTURE c13s03b01x00p02n01i02669arch OF c13s03b01x00p02n01i02669ent IS
BEGIN
TESTING: PROCESS
variable ]k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02669 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02669arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2669.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02669ent IS
END c13s03b01x00p02n01i02669ent;
ARCHITECTURE c13s03b01x00p02n01i02669arch OF c13s03b01x00p02n01i02669ent IS
BEGIN
TESTING: PROCESS
variable ]k : integer;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02669 - Identifier can only begin with a letter."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02669arch;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved. --
-- --
-- This file contains confidential and proprietary information --
-- of Xilinx, Inc. and is protected under U.S. and --
-- international copyright and other intellectual property --
-- laws. --
-- --
-- DISCLAIMER --
-- This disclaimer is not a license and does not grant any --
-- rights to the materials distributed herewith. Except as --
-- otherwise provided in a valid license issued to you by --
-- Xilinx, and to the maximum extent permitted by applicable --
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND --
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES --
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING --
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- --
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and --
-- (2) Xilinx shall not be liable (whether in contract or tort, --
-- including negligence, or under any other theory of --
-- liability) for any loss or damage of any kind or nature --
-- related to, arising under or in connection with these --
-- materials, including for any direct, or any indirect, --
-- special, incidental, or consequential loss or damage --
-- (including loss of data, profits, goodwill, or any type of --
-- loss or damage suffered as a result of any action brought --
-- by a third party) even if such damage or loss was --
-- reasonably foreseeable or Xilinx had been advised of the --
-- possibility of the same. --
-- --
-- CRITICAL APPLICATIONS --
-- Xilinx products are not designed or intended to be fail- --
-- safe, or for use in any application requiring fail-safe --
-- performance, such as life-support or safety devices or --
-- systems, Class III medical devices, nuclear facilities, --
-- applications related to the deployment of airbags, or any --
-- other applications that could lead to death, personal --
-- injury, or severe property or environmental damage --
-- (individually and collectively, "Critical --
-- Applications"). Customer assumes the sole risk and --
-- liability of any use of Xilinx products in Critical --
-- Applications, subject only to applicable laws and --
-- regulations governing limitations on product liability. --
-- --
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS --
-- PART OF THIS FILE AT ALL TIMES. --
-------------------------------------------------------------------
-- ************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: slave_attachment.vhd
-- Version: v1.01.a
-- Description: AXI slave attachment supporting single transfers
-------------------------------------------------------------------------------
-- Structure: This section shows the hierarchical structure of axi_lite_ipif.
--
-- --axi_lite_ipif.vhd
-- --slave_attachment.vhd
-- --address_decoder.vhd
-------------------------------------------------------------------------------
-- Author: BSB
--
-- History:
--
-- BSB 05/20/10 -- First version
-- ~~~~~~
-- - Created the first version v1.00.a
-- ^^^^^^
-- ~~~~~~
-- SK 06/09/10 -- updated to reduce the utilization
-- 1. State machine is re-designed
-- 2. R and B channels are registered and AW, AR, W channels are non-registered
-- 3. Address decoding is done only for the required address bits and not complete
-- 32 bits
-- 4. combined the response signals like ip2bus_error in optimzed code to remove the mux
-- 5. Added local function "clog2" with "integer" as input in place of proc_common_pkg
-- function.
-- ^^^^^^
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- access_cs machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use work.common_types.all;
-------------------------------------------------------------------------------
-- Definition of Generics
-------------------------------------------------------------------------------
-- C_IPIF_ABUS_WIDTH -- IPIF Address bus width
-- C_IPIF_DBUS_WIDTH -- IPIF Data Bus width
-- C_S_AXI_MIN_SIZE -- Minimum address range of the IP
-- C_USE_WSTRB -- Use write strobs or not
-- C_DPHASE_TIMEOUT -- Data phase time out counter
-- C_ARD_ADDR_RANGE_ARRAY-- Base /High Address Pair for each Address Range
-- C_ARD_NUM_CE_ARRAY -- Desired number of chip enables for an address range
-- C_FAMILY -- Target FPGA family
-------------------------------------------------------------------------------
-- Definition of Ports
-------------------------------------------------------------------------------
-- S_AXI_ACLK -- AXI Clock
-- S_AXI_ARESET -- AXI Reset
-- S_AXI_AWADDR -- AXI Write address
-- S_AXI_AWVALID -- Write address valid
-- S_AXI_AWREADY -- Write address ready
-- S_AXI_WDATA -- Write data
-- S_AXI_WSTRB -- Write strobes
-- S_AXI_WVALID -- Write valid
-- S_AXI_WREADY -- Write ready
-- S_AXI_BRESP -- Write response
-- S_AXI_BVALID -- Write response valid
-- S_AXI_BREADY -- Response ready
-- S_AXI_ARADDR -- Read address
-- S_AXI_ARVALID -- Read address valid
-- S_AXI_ARREADY -- Read address ready
-- S_AXI_RDATA -- Read data
-- S_AXI_RRESP -- Read response
-- S_AXI_RVALID -- Read valid
-- S_AXI_RREADY -- Read ready
-- Bus2IP_Clk -- Synchronization clock provided to User IP
-- Bus2IP_Reset -- Active high reset for use by the User IP
-- Bus2IP_Addr -- Desired address of read or write operation
-- Bus2IP_RNW -- Read or write indicator for the transaction
-- Bus2IP_BE -- Byte enables for the data bus
-- Bus2IP_CS -- Chip select for the transcations
-- Bus2IP_RdCE -- Chip enables for the read
-- Bus2IP_WrCE -- Chip enables for the write
-- Bus2IP_Data -- Write data bus to the User IP
-- IP2Bus_Data -- Input Read Data bus from the User IP
-- IP2Bus_WrAck -- Active high Write Data qualifier from the IP
-- IP2Bus_RdAck -- Active high Read Data qualifier from the IP
-- IP2Bus_Error -- Error signal from the IP
-------------------------------------------------------------------------------
entity slave_attachment is
generic (
C_ARD_ADDR_RANGE_ARRAY: SLV64_ARRAY_TYPE :=
(
X"0000_0000_7000_0000", -- IP user0 base address
X"0000_0000_7000_00FF", -- IP user0 high address
X"0000_0000_7000_0100", -- IP user1 base address
X"0000_0000_7000_01FF" -- IP user1 high address
);
C_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
1, -- User0 CE Number
8 -- User1 CE Number
);
C_IPIF_ABUS_WIDTH : integer := 32;
C_IPIF_DBUS_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector(31 downto 0):= X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer range 0 to 512 := 16;
C_FAMILY : string := "virtex6"
);
port(
-- AXI signals
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector
((C_IPIF_DBUS_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic;
-- Controls to the IP/IPIF modules
Bus2IP_Clk : out std_logic;
Bus2IP_Resetn : out std_logic;
Bus2IP_Addr : out std_logic_vector
(C_IPIF_ABUS_WIDTH-1 downto 0);
Bus2IP_RNW : out std_logic;
Bus2IP_BE : out std_logic_vector
(((C_IPIF_DBUS_WIDTH/8) - 1) downto 0);
Bus2IP_CS : out std_logic_vector
(((C_ARD_ADDR_RANGE_ARRAY'LENGTH)/2 - 1) downto 0);
Bus2IP_RdCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_WrCE : out std_logic_vector
((calc_num_ce(C_ARD_NUM_CE_ARRAY) - 1) downto 0);
Bus2IP_Data : out std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_Data : in std_logic_vector
((C_IPIF_DBUS_WIDTH-1) downto 0);
IP2Bus_WrAck : in std_logic;
IP2Bus_RdAck : in std_logic;
IP2Bus_Error : in std_logic
);
end entity slave_attachment;
-------------------------------------------------------------------------------
architecture imp of slave_attachment is
-------------------------------------------------------------------------------
-- Get_Addr_Bits: Function Declarations
-------------------------------------------------------------------------------
function Get_Addr_Bits (y : std_logic_vector(31 downto 0)) return integer is
variable i : integer := 0;
begin
for i in 31 downto 0 loop
if y(i)='1' then
return (i);
end if;
end loop;
return -1;
end function Get_Addr_Bits;
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
constant CS_BUS_SIZE : integer := C_ARD_ADDR_RANGE_ARRAY'length/2;
constant CE_BUS_SIZE : integer := calc_num_ce(C_ARD_NUM_CE_ARRAY);
constant C_ADDR_DECODE_BITS : integer := Get_Addr_Bits(C_S_AXI_MIN_SIZE);
constant C_NUM_DECODE_BITS : integer := C_ADDR_DECODE_BITS +1;
constant ZEROS : std_logic_vector((C_IPIF_ABUS_WIDTH-1) downto
(C_ADDR_DECODE_BITS+1)) := (others=>'0');
-------------------------------------------------------------------------------
-- Signal and Type Declarations
-------------------------------------------------------------------------------
signal s_axi_bvalid_i : std_logic:= '0';
signal s_axi_arready_i : std_logic;
signal s_axi_rvalid_i : std_logic:= '0';
signal start : std_logic;
-- Intermediate IPIC signals
signal bus2ip_addr_i : std_logic_vector
((C_IPIF_ABUS_WIDTH-1) downto 0);
signal timeout : std_logic;
signal rd_done,wr_done : std_logic;
signal rst : std_logic;
signal temp_i : std_logic;
type BUS_ACCESS_STATES is (
SM_IDLE,
SM_READ,
SM_WRITE,
SM_RESP
);
signal state : BUS_ACCESS_STATES;
signal cs_for_gaps_i : std_logic;
signal bus2ip_rnw_i : std_logic;
signal s_axi_bresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rresp_i : std_logic_vector(1 downto 0):=(others => '0');
signal s_axi_rdata_i : std_logic_vector
(C_IPIF_DBUS_WIDTH-1 downto 0):=(others => '0');
-------------------------------------------------------------------------------
-- begin the architecture logic
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Address registered
-------------------------------------------------------------------------------
Bus2IP_Clk <= S_AXI_ACLK;
Bus2IP_Resetn <= S_AXI_ARESETN;
bus2ip_rnw_i <= '1' when S_AXI_ARVALID='1'
else
'0';
BUS2IP_RNW <= bus2ip_rnw_i;
Bus2IP_BE <= S_AXI_WSTRB when ((C_USE_WSTRB = 1) and (bus2ip_rnw_i = '0'))
else
(others => '1');
Bus2IP_Data <= S_AXI_WDATA;
Bus2IP_Addr <= bus2ip_addr_i;
-- For AXI Lite interface, interconnect will duplicate the addresses on both the
-- read and write channel. so onlyone address is used for decoding as well as
-- passing it to IP.
bus2ip_addr_i <= ZEROS & S_AXI_ARADDR(C_ADDR_DECODE_BITS downto 0)
when (S_AXI_ARVALID='1')
else
ZEROS & S_AXI_AWADDR(C_ADDR_DECODE_BITS downto 0);
--------------------------------------------------------------------------------
-- start signal will be used to latch the incoming address
start<= (S_AXI_ARVALID or (S_AXI_AWVALID and S_AXI_WVALID))
when (state = SM_IDLE)
else
'0';
-- x_done signals are used to release the hold from AXI, it will generate "ready"
-- signal on the read and write address channels.
rd_done <= IP2Bus_RdAck or timeout;
wr_done <= IP2Bus_WrAck or timeout;
temp_i <= rd_done or wr_done;
-------------------------------------------------------------------------------
-- Address Decoder Component Instance
--
-- This component decodes the specified base address pairs and outputs the
-- specified number of chip enables and the target bus size.
-------------------------------------------------------------------------------
I_DECODER : entity work.address_decoder
generic map
(
C_BUS_AWIDTH => C_NUM_DECODE_BITS,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_ARD_ADDR_RANGE_ARRAY=> C_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => C_ARD_NUM_CE_ARRAY,
C_FAMILY => "nofamily"
)
port map
(
Bus_clk => S_AXI_ACLK,
Bus_rst => S_AXI_ARESETN,
Address_In_Erly => bus2ip_addr_i(C_ADDR_DECODE_BITS downto 0),
Address_Valid_Erly => start,
Bus_RNW => S_AXI_ARVALID,
Bus_RNW_Erly => S_AXI_ARVALID,
CS_CE_ld_enable => start,
Clear_CS_CE_Reg => temp_i,
RW_CE_ld_enable => start,
CS_for_gaps => open,
-- Decode output signals
CS_Out => Bus2IP_CS,
RdCE_Out => Bus2IP_RdCE,
WrCE_Out => Bus2IP_WrCE
);
-- REGISTERING_RESET_P: Invert the reset coming from AXI
-----------------------
REGISTERING_RESET_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
rst <= not S_AXI_ARESETN;
end if;
end process REGISTERING_RESET_P;
-------------------------------------------------------------------------------
-- AXI Transaction Controller
-------------------------------------------------------------------------------
-- Access_Control: As per suggestion to optimize the core, the below state machine
-- is re-coded. Latches are removed from original suggestions
Access_Control : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
state <= SM_IDLE;
else
case state is
when SM_IDLE => if (S_AXI_ARVALID = '1') then -- Read precedence over write
state <= SM_READ;
elsif (S_AXI_AWVALID = '1' and S_AXI_WVALID = '1') then
state <= SM_WRITE;
else
state <= SM_IDLE;
end if;
when SM_READ => if rd_done = '1' then
state <= SM_RESP;
else
state <= SM_READ;
end if;
when SM_WRITE=> if (wr_done = '1') then
state <= SM_RESP;
else
state <= SM_WRITE;
end if;
when SM_RESP => if ((s_axi_bvalid_i and S_AXI_BREADY) or
(s_axi_rvalid_i and S_AXI_RREADY)) = '1' then
state <= SM_IDLE;
else
state <= SM_RESP;
end if;
-- coverage off
when others => state <= SM_IDLE;
-- coverage on
end case;
end if;
end if;
end process Access_Control;
-------------------------------------------------------------------------------
-- AXI Transaction Controller signals registered
-------------------------------------------------------------------------------
-- S_AXI_RDATA_RESP_P : BElow process generates the RRESP and RDATA on AXI
-----------------------
S_AXI_RDATA_RESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rresp_i <= (others => '0');
s_axi_rdata_i <= (others => '0');
elsif state = SM_READ then
s_axi_rresp_i <= (IP2Bus_Error) & '0';
s_axi_rdata_i <= IP2Bus_Data;
end if;
end if;
end process S_AXI_RDATA_RESP_P;
S_AXI_RRESP <= s_axi_rresp_i;
S_AXI_RDATA <= s_axi_rdata_i;
-----------------------------
-- S_AXI_RVALID_I_P : below process generates the RVALID response on read channel
----------------------
S_AXI_RVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_rvalid_i <= '0';
elsif ((state = SM_READ) and rd_done = '1') then
s_axi_rvalid_i <= '1';
elsif (S_AXI_RREADY = '1') then
s_axi_rvalid_i <= '0';
end if;
end if;
end process S_AXI_RVALID_I_P;
-- -- S_AXI_BRESP_P: Below process provides logic for write response
-- -----------------
S_AXI_BRESP_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if (rst = '1') then
s_axi_bresp_i <= (others => '0');
elsif (state = SM_WRITE) then
s_axi_bresp_i <= (IP2Bus_Error) & '0';
end if;
end if;
end process S_AXI_BRESP_P;
S_AXI_BRESP <= s_axi_bresp_i;
--S_AXI_BVALID_I_P: below process provides logic for valid write response signal
-------------------
S_AXI_BVALID_I_P : process (S_AXI_ACLK) is
begin
if S_AXI_ACLK'event and S_AXI_ACLK = '1' then
if rst = '1' then
s_axi_bvalid_i <= '0';
elsif ((state = SM_WRITE) and wr_done = '1') then
s_axi_bvalid_i <= '1';
elsif (S_AXI_BREADY = '1') then
s_axi_bvalid_i <= '0';
end if;
end if;
end process S_AXI_BVALID_I_P;
-----------------------------------------------------------------------------
-- INCLUDE_DPHASE_TIMER: Data timeout counter included only when its value is non-zero.
--------------
INCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT /= 0 generate
constant COUNTER_WIDTH : integer := clog2((C_DPHASE_TIMEOUT));
signal dpto_cnt : std_logic_vector (COUNTER_WIDTH downto 0);
-- dpto_cnt is one bit wider then COUNTER_WIDTH, which allows the timeout
-- condition to be captured as a carry into this "extra" bit.
begin
DPTO_CNT_P : process (S_AXI_ACLK) is
begin
if (S_AXI_ACLK'event and S_AXI_ACLK = '1') then
if ((state = SM_IDLE) or (state = SM_RESP)) then
dpto_cnt <= (others=>'0');
else
dpto_cnt <= dpto_cnt + 1;
end if;
end if;
end process DPTO_CNT_P;
timeout <= dpto_cnt(COUNTER_WIDTH);
end generate INCLUDE_DPHASE_TIMER;
EXCLUDE_DPHASE_TIMER: if C_DPHASE_TIMEOUT = 0 generate
timeout <= '0';
end generate EXCLUDE_DPHASE_TIMER;
-----------------------------------------------------------------------------
S_AXI_BVALID <= s_axi_bvalid_i;
S_AXI_RVALID <= s_axi_rvalid_i;
-----------------------------------------------------------------------------
S_AXI_ARREADY <= rd_done;
S_AXI_AWREADY <= wr_done;
S_AXI_WREADY <= wr_done;
-------------------------------------------------------------------------------
end imp;
|
------------------------------------------------------------------------------
-- globalmixer.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: globalmixer.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Fri May 29 17:58:19 2015 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library axi_lite_ipif_v1_01_a;
use axi_lite_ipif_v1_01_a.axi_lite_ipif;
library globalmixer_v1_00_a;
use globalmixer_v1_00_a.user_logic;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_S_AXI_DATA_WIDTH -- AXI4LITE slave: Data width
-- C_S_AXI_ADDR_WIDTH -- AXI4LITE slave: Address Width
-- C_S_AXI_MIN_SIZE -- AXI4LITE slave: Min Size
-- C_USE_WSTRB -- AXI4LITE slave: Write Strobe
-- C_DPHASE_TIMEOUT -- AXI4LITE slave: Data Phase Timeout
-- C_BASEADDR -- AXI4LITE slave: base address
-- C_HIGHADDR -- AXI4LITE slave: high address
-- C_FAMILY -- FPGA Family
-- C_NUM_REG -- Number of software accessible registers
-- C_NUM_MEM -- Number of address-ranges
-- C_SLV_AWIDTH -- Slave interface address bus width
-- C_SLV_DWIDTH -- Slave interface data bus width
--
-- Definition of Ports:
-- S_AXI_ACLK -- AXI4LITE slave: Clock
-- S_AXI_ARESETN -- AXI4LITE slave: Reset
-- S_AXI_AWADDR -- AXI4LITE slave: Write address
-- S_AXI_AWVALID -- AXI4LITE slave: Write address valid
-- S_AXI_WDATA -- AXI4LITE slave: Write data
-- S_AXI_WSTRB -- AXI4LITE slave: Write strobe
-- S_AXI_WVALID -- AXI4LITE slave: Write data valid
-- S_AXI_BREADY -- AXI4LITE slave: Response ready
-- S_AXI_ARADDR -- AXI4LITE slave: Read address
-- S_AXI_ARVALID -- AXI4LITE slave: Read address valid
-- S_AXI_RREADY -- AXI4LITE slave: Read data ready
-- S_AXI_ARREADY -- AXI4LITE slave: read addres ready
-- S_AXI_RDATA -- AXI4LITE slave: Read data
-- S_AXI_RRESP -- AXI4LITE slave: Read data response
-- S_AXI_RVALID -- AXI4LITE slave: Read data valid
-- S_AXI_WREADY -- AXI4LITE slave: Write data ready
-- S_AXI_BRESP -- AXI4LITE slave: Response
-- S_AXI_BVALID -- AXI4LITE slave: Resonse valid
-- S_AXI_AWREADY -- AXI4LITE slave: Wrte address ready
------------------------------------------------------------------------------
entity globalmixer is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
CLK_48_in : in std_logic;
CLK_100M_in : in std_logic; -- get rid of this
GM_Left_in_0 : in std_logic_vector(23 downto 0);
GM_Right_in_0 : in std_logic_vector(23 downto 0);
GM_Left_in_1 : in std_logic_vector(23 downto 0);
GM_Right_in_1 : in std_logic_vector(23 downto 0);
GM_Left_in_2 : in std_logic_vector(23 downto 0);
GM_Right_in_2 : in std_logic_vector(23 downto 0);
GM_Left_in_3 : in std_logic_vector(23 downto 0);
GM_Right_in_3 : in std_logic_vector(23 downto 0);
GM_Left_out : out std_logic_vector(23 downto 0);
GM_Right_out : out std_logic_vector(23 downto 0);
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000";
attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000";
attribute SIGIS of S_AXI_ACLK : signal is "Clk";
attribute SIGIS of S_AXI_ARESETN : signal is "Rst";
end entity globalmixer;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of globalmixer is
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := 32;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
begin
------------------------------------------
-- instantiate axi_lite_ipif
------------------------------------------
AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif
generic map
(
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map
(
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : entity globalmixer_v1_00_a.user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
CLK_48_in => CLK_48_in,
CLK_100M_in => CLK_100M_in,
GM_Left_in_0 => GM_Left_in_0,
GM_Right_in_0 => GM_Right_in_0,
GM_Left_in_1 => GM_Left_in_1,
GM_Right_in_1 => GM_Right_in_1,
GM_Left_in_2 => GM_Left_in_2,
GM_Right_in_2 => GM_Right_in_2,
GM_Left_in_3 => GM_Left_in_3,
GM_Right_in_3 => GM_Right_in_3,
GM_Left_out => GM_Left_out,
GM_Right_out => GM_Right_out,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
------------------------------------------
-- connect internal signals
------------------------------------------
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
end IMP;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/fft_16_bit/RADIX22FFT_SDNF2_4_block5.vhd
-- Created: 2017-03-27 23:13:58
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block5
-- Source Path: fft_16_bit/FFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block5 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_13 : IN std_logic; -- ufix1
dout_13_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_13_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_15_re : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_15_im : IN std_logic_vector(19 DOWNTO 0); -- sfix20
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_13_re_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_13_im_1 : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_14_re : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_14_im : OUT std_logic_vector(20 DOWNTO 0); -- sfix21
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block5;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block5 IS
-- Signals
SIGNAL dout_13_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_13_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din1_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_15_re_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_re : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_15_im_signed : signed(19 DOWNTO 0); -- sfix20
SIGNAL din2_im : signed(20 DOWNTO 0); -- sfix21
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(21 DOWNTO 0); -- sfix22
SIGNAL dout_13_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_13_im_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_14_re_tmp : signed(20 DOWNTO 0); -- sfix21
SIGNAL dout_14_im_tmp : signed(20 DOWNTO 0); -- sfix21
BEGIN
dout_13_re_signed <= signed(dout_13_re);
din1_re <= resize(dout_13_re_signed, 21);
dout_13_im_signed <= signed(dout_13_im);
din1_im <= resize(dout_13_im_signed, 21);
dout_15_re_signed <= signed(dout_15_re);
din2_re <= resize(dout_15_re_signed, 21);
dout_15_im_signed <= signed(dout_15_im);
din2_im <= resize(dout_15_im_signed, 21);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#000000#, 22);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#000000#, 22);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, din1_re, din1_im, din2_re, din2_im,
dout_1_vld, rotate_13)
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_13 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) - resize(din2_re, 22);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(din1_re, 22) + resize(din2_re, 22);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(din1_re, 22) - resize(din2_re, 22);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(din1_im, 22) + resize(din2_im, 22);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(din1_im, 22) - resize(din2_im, 22);
END IF;
dout_13_re_tmp <= Radix22ButterflyG2_NF_btf1_re_reg(20 DOWNTO 0);
dout_13_im_tmp <= Radix22ButterflyG2_NF_btf1_im_reg(20 DOWNTO 0);
dout_14_re_tmp <= Radix22ButterflyG2_NF_btf2_re_reg(20 DOWNTO 0);
dout_14_im_tmp <= Radix22ButterflyG2_NF_btf2_im_reg(20 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_14_re <= std_logic_vector(dout_14_re_tmp);
dout_14_im <= std_logic_vector(dout_14_im_tmp);
dout_13_re_1 <= std_logic_vector(dout_13_re_tmp);
dout_13_im_1 <= std_logic_vector(dout_13_im_tmp);
END rtl;
|
-------------------------------------------------------------------------------
--
-- SNESpad controller core
--
-- Copyright (c) 2004, Arnim Laeuger (arniml@opencores.org)
--
-- $Id: snespad_comp-pack.vhd,v 1.1 2004/10/05 18:20:14 arniml Exp $
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package snespad_comp is
component snespad
generic (
num_pads_g : natural := 1;
reset_level_g : natural := 0;
button_level_g : natural := 0;
clocks_per_6us_g : natural := 6
);
port (
clk_i : in std_logic;
reset_i : in std_logic;
pad_clk_o : out std_logic;
pad_latch_o : out std_logic;
pad_data_i : in std_logic_vector(num_pads_g-1 downto 0);
but_a_o : out std_logic_vector(num_pads_g-1 downto 0);
but_b_o : out std_logic_vector(num_pads_g-1 downto 0);
but_x_o : out std_logic_vector(num_pads_g-1 downto 0);
but_y_o : out std_logic_vector(num_pads_g-1 downto 0);
but_start_o : out std_logic_vector(num_pads_g-1 downto 0);
but_sel_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tl_o : out std_logic_vector(num_pads_g-1 downto 0);
but_tr_o : out std_logic_vector(num_pads_g-1 downto 0);
but_up_o : out std_logic_vector(num_pads_g-1 downto 0);
but_down_o : out std_logic_vector(num_pads_g-1 downto 0);
but_left_o : out std_logic_vector(num_pads_g-1 downto 0);
but_right_o : out std_logic_vector(num_pads_g-1 downto 0)
);
end component snespad;
end snespad_comp;
|
-- The Potato Processor - A simple processor for FPGAs
-- (c) Kristian Klomsten Skordal 2014 - 2015 <kristian.skordal@wafflemail.net>
-- Report bugs and issues on <https://github.com/skordal/potato/issues>
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.pp_types.all;
use work.pp_utilities.all;
--! @brief Simple read-only direct-mapped instruction cache.
entity pp_icache is
generic(
LINE_SIZE : natural := 4; --! Number of words per cache line
NUM_LINES : natural := 128 --! Number of lines in the cache
);
port(
clk : in std_logic;
reset : in std_logic;
-- Memory interface:
mem_address_in : in std_logic_vector(31 downto 0);
mem_data_out : out std_logic_vector(31 downto 0);
mem_read_req : in std_logic;
mem_read_ack : out std_logic;
-- Wishbone interface:
wb_inputs : in wishbone_master_inputs;
wb_outputs : out wishbone_master_outputs
);
end entity pp_icache;
architecture behaviour of pp_icache is
-- Counter types:
subtype line_counter_type is natural range 0 to NUM_LINES;
subtype word_counter_type is natural range 0 to LINE_SIZE;
-- Cache line types:
subtype cache_line_type is std_logic_vector((LINE_SIZE * 32) - 1 downto 0);
type cache_line_word_array is array(0 to LINE_SIZE - 1) of std_logic_vector(31 downto 0);
type cache_line_array is array(0 to NUM_LINES - 1) of cache_line_type;
-- Cache tag type:
subtype cache_tag_type is std_logic_vector(31 - log2(LINE_SIZE * 4) - log2(NUM_LINES) downto 0);
type cache_tag_array is array(0 to NUM_LINES - 1) of cache_tag_type;
-- Cache memories:
signal cache_memory : cache_line_array;
signal tag_memory : cache_tag_array;
signal valid : std_logic_vector(NUM_LINES - 1 downto 0) := (others => '0');
attribute ram_style : string;
attribute ram_style of cache_memory: signal is "block";
-- Cache controller signals:
type state_type is (IDLE, CACHE_READ_STALL,
LOAD_CACHELINE_START, LOAD_CACHELINE_WAIT_ACK, LOAD_CACHELINE_FINISH);
signal state : state_type := IDLE;
-- Input address components:
signal input_address_line : std_logic_vector(log2(NUM_LINES) - 1 downto 0);
signal input_address_word : std_logic_vector(log2(LINE_SIZE) - 1 downto 0);
signal input_address_tag : cache_tag_type;
-- Cacheline matching the current input address:
signal current_cache_line, cache_lookup : cache_line_type;
signal current_cache_line_words : cache_line_word_array;
-- Base address to load a cacheline from:
signal cl_load_address : std_logic_vector(31 downto log2(LINE_SIZE * 4));
-- Cache line to load:
signal cl_current_line : line_counter_type;
-- Current word being loaded:
signal cl_current_word : word_counter_type;
-- Buffer for holding a cache line while loading:
signal load_buffer : cache_line_type;
signal load_buffer_tag : cache_tag_type;
-- Causes a cache line to be stored in the cache memory:
signal store_cache_line : std_logic;
-- Set when the current input address matches a cache line:
signal cache_hit : std_logic;
begin
assert is_pow2(LINE_SIZE) report "Cache line size must be a power of 2!" severity FAILURE;
assert is_pow2(NUM_LINES) report "Number of cache lines must be a power of 2!" severity FAILURE;
mem_data_out <= current_cache_line_words(to_integer(unsigned(input_address_word)));
mem_read_ack <= (cache_hit and mem_read_req) when state = IDLE or state = CACHE_READ_STALL else '0';
input_address_line <= mem_address_in(log2(LINE_SIZE * 4) + log2(NUM_LINES) - 1 downto log2(LINE_SIZE * 4));
input_address_tag <= mem_address_in(31 downto log2(LINE_SIZE * 4) + log2(NUM_LINES));
decompose_cache_line: for i in 0 to LINE_SIZE - 1 generate
current_cache_line_words(i) <= current_cache_line(32 * i + 31 downto 32 * i);
end generate decompose_cache_line;
find_indices: process(clk)
begin
if rising_edge(clk) then
input_address_word <= mem_address_in(log2(LINE_SIZE * 4) - 1 downto 2);
end if;
end process find_indices;
cacheline_lookup: process(clk)
begin
if rising_edge(clk) then
if store_cache_line = '1' then
cache_memory(cl_current_line) <= load_buffer;
end if;
current_cache_line <= cache_memory(to_integer(unsigned(input_address_line)));
end if;
end process cacheline_lookup;
tag_lookup: process(clk)
begin
if rising_edge(clk) then
if store_cache_line = '1' then
tag_memory(cl_current_line) <= load_buffer_tag;
end if;
cache_hit <= valid(to_integer(unsigned(input_address_line)))
and to_std_logic(tag_memory(to_integer(unsigned(input_address_line))) = input_address_tag);
end if;
end process tag_lookup;
controller: process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
state <= IDLE;
wb_outputs.cyc <= '0';
wb_outputs.stb <= '0';
store_cache_line <= '0';
valid <= (others => '0');
else
case state is
when IDLE =>
if mem_read_req = '1' and cache_hit = '0' then
wb_outputs.adr <= mem_address_in(31 downto log2(LINE_SIZE * 4)) & (log2(LINE_SIZE * 4) - 1 downto 0 => '0');
wb_outputs.cyc <= '1';
wb_outputs.we <= '0';
wb_outputs.sel <= (others => '1');
load_buffer_tag <= input_address_tag;
cl_load_address <= mem_address_in(31 downto log2(LINE_SIZE * 4));
cl_current_line <= to_integer(unsigned(input_address_line));
cl_current_word <= 0;
state <= LOAD_CACHELINE_START;
end if;
when CACHE_READ_STALL =>
state <= IDLE;
when LOAD_CACHELINE_START =>
wb_outputs.stb <= '1';
wb_outputs.we <= '0';
wb_outputs.adr <= cl_load_address & std_logic_vector(to_unsigned(cl_current_word, log2(LINE_SIZE))) & b"00";
state <= LOAD_CACHELINE_WAIT_ACK;
when LOAD_CACHELINE_WAIT_ACK =>
if wb_inputs.ack = '1' then
wb_outputs.stb <= '0';
load_buffer(cl_current_word * 32 + 31 downto cl_current_word * 32) <= wb_inputs.dat;
if natural(cl_current_word) = LINE_SIZE - 1 then
wb_outputs.cyc <= '0';
store_cache_line <= '1';
state <= LOAD_CACHELINE_FINISH;
else
cl_current_word <= cl_current_word + 1;
state <= LOAD_CACHELINE_START;
end if;
end if;
when LOAD_CACHELINE_FINISH =>
store_cache_line <= '0';
valid(cl_current_line) <= '1';
state <= CACHE_READ_STALL;
end case;
end if;
end if;
end process controller;
end architecture behaviour;
|
-------------------------------------------------------------------------------
-- $Id: write_buffer.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- write_buffer.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2004,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: write_buffer.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the write buffer design.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- write_buffer.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
--
--
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- Fixed issues with master aborts, delayed IP acknowledges, and single
-- beat reads (i.e. rdce was 2 clocks wide)
-- ~~~~~~~
-- GAB 07/07/04
-- ^^^^^^
-- Fixed issues with xferack due to changes in opb_bam signal timing
-- Fixed wrbuf_burst signal to negate 1 cycle before cs negates
-- Fixed wrbuf_addrvalid signal to only drive during valid addresses
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.srl_fifo3;
use opb_v20_v1_10_d.proc_common_pkg.log2;
use opb_v20_v1_10_d.counter;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity write_buffer is
generic (
C_INCLUDE_OPBIN_PSTAGE : boolean := TRUE;
C_INCLUDE_IPIC_PSTAGE : boolean := TRUE;
C_INCLUDE_OPBOUT_PSTAGE : boolean := TRUE;
C_OPB_DWIDTH : integer := 32;
C_WRBUF_DEPTH : integer := 16; -- max is 16
C_NUM_CES : integer := 4;
C_NUM_ARDS : integer := 4
);
port (
-- Clock and Reset
Bus_reset : in std_logic;
Bus_clk : in std_logic;
-- Inputs
Data_in : in std_logic_vector(0 to C_OPB_DWIDTH-1);
CE : in std_logic_vector(0 to C_NUM_CES-1);
Wr_CE : in std_logic_vector(0 to C_NUM_CES-1);
Rd_CE : in std_logic_vector(0 to C_NUM_CES-1);
RNW : in std_logic;
CS_hit : in std_logic_vector(0 to C_NUM_ARDS-1);
CS : in std_logic_vector(0 to C_NUM_ARDS-1);
CS_enable : in std_logic_vector(0 to C_NUM_ARDS-1);
Burst : in std_logic;
Xfer_start : in std_logic;
Xfer_done : in std_logic;
Addr_ack : in std_logic;
Wrdata_ack : in std_logic;
WrBuf_data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
WrBuf_burst : out std_logic;
WrBuf_xferack : out std_logic;
WrBuf_errack : out std_logic;
WrBuf_retry : out std_logic;
WrBuf_CS : out std_logic_vector(0 to C_NUM_ARDS-1);
WrBuf_RNW : out std_logic;
WrBuf_CE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_WrCE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_RdCE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_Empty : out std_logic;
WrBuf_AddrCnt_en : out std_logic;
WrBuf_AddrCntr_rst : out std_logic;
WrBuf_AddrValid : out std_logic;
IPIC_Pstage_CE : out std_logic
);
end write_buffer;
architecture implementation of write_buffer is
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others=>r);
return( l and rex );
end function "and";
-------------------------------------------------------------------------------
-- Constant Declaration
-------------------------------------------------------------------------------
constant ZERO_LOAD : std_logic_vector(0 to 4) := (others => '0');
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
signal wrbuf_write : std_logic;
signal wrbuf_write_d1 : std_logic;
signal wrbuf_write_re : std_logic;
signal wrbuf_read : std_logic;
signal wrbuf_data_i : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal wrbuf_full : std_logic;
signal wrbuf_empty_i : std_logic;
signal wrbuf_empty_d1 : std_logic;
signal wrbuf_empty_fe : std_logic;
signal wrdata_ack_d1 : std_logic;
signal wrbuf_addr : std_logic_vector(0 to 3);
signal wrbuf_going_full : std_logic;
signal wrbuf_going_empty : std_logic;
signal wrbuf_wrce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_rdce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_ce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_rnw_i : std_logic;
signal wrbuf_burst_i : std_logic;
signal wrbuf_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal wrbuf_addrcnt_en_i : std_logic;
signal wrbuf_addrcntr_rst_i: std_logic;
signal wrbuf_xferack_i : std_logic;
signal wrbuf_retry_i : std_logic;
signal wrbuf_retry_d1 : std_logic;
signal wrbuf_retry_d2 : std_logic;
signal valid_addr_cntr_ce : std_logic;
signal valid_addr_cnt : std_logic_vector(0 to 4);
signal sample_hold_ce : std_logic;
signal xfer_start_reg : std_logic;
signal cs_rnw_rst : std_logic;
signal wrbuf_write_i : std_logic;
signal burst_d1 : std_logic;
signal wrbuf_full_retry : std_logic;
signal wrbuf_xferack_cmb : std_logic;
signal wrbuf_xferack_d1 : std_logic;
signal wr_ce_i : std_logic;
signal wrbuf2ip_burst : std_logic;
signal wrbuf_addrvalid_i : std_logic;
-------------------------------------------------------------------------------
-- Begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Output assignments
-------------------------------------------------------------------------------
WrBuf_data <= wrbuf_data_i;
WrBuf_RNW <= wrbuf_rnw_i;
WrBuf_Burst <= wrbuf2ip_burst;
WrBuf_WrCE <= wrbuf_wrce_i;
WrBuf_RdCE <= wrbuf_rdce_i;
WrBuf_CE <= wrbuf_ce_i;
WrBuf_CS <= wrbuf_cs_i;
WrBuf_AddrCnt_en <= wrbuf_addrcnt_en_i;
WrBuf_AddrCntr_Rst <= wrbuf_addrcntr_rst_i;
WrBuf_Empty <= wrbuf_empty_i;
-------------------------------------------------------------------------------
-- Transaction acknowledges
-------------------------------------------------------------------------------
-- XferAck--
-- Assert XferAck when at the start of a xfer if wrbuffer is empty, keep
-- asserted until wrbuffer is full or cs_hit = 0
-- Don't need to qualify with CS_Hit because the XferAck logic in OPB_BAM
-- takes care of this
--ToDo: see if wrbuf_going_empty can be used
XFERACK_REG: process(Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if or_reduce(CS_hit) ='0'
or (wrbuf_xferack_i = '1' and Burst = '0')
or (wrbuf_rnw_i='0' and wrbuf_going_empty='1' and wrdata_ack='1')then
wrbuf_xferack_i <= '0';
elsif xfer_start = '1' and wrbuf_empty_i = '1' and RNW = '0' then
wrbuf_xferack_i <= '1';
end if;
end if;
end process XFERACK_REG;
wrbuf_xferack_cmb <= (((wrbuf_xferack_i and or_reduce(CS_hit))
or (or_reduce(CS_hit) and wrbuf_empty_i
and not(RNW) and xfer_start and Burst))
and not wrbuf_going_full);
-- Generate for pipeline models 5 and 7
GEN_PIPE_5_7 : if C_INCLUDE_OPBIN_PSTAGE = true
and C_INCLUDE_OPBOUT_PSTAGE = true generate
WrBuf_xferack <= wrbuf_xferack_d1 and not wrbuf_going_full
and not wrbuf_retry_i and or_reduce(CS_hit);
end generate;
-- Generate for pipeline models 1,2,3,4,and 6
GEN_PIPE_THE_REST : if (C_INCLUDE_OPBIN_PSTAGE = false
or C_INCLUDE_OPBOUT_PSTAGE = false)generate
WrBuf_xferack <= wrbuf_xferack_d1 and not wrbuf_retry_i
and or_reduce(CS_hit);
end generate;
-------------------------------------------------------------------------------
-- Transaction Retry
-------------------------------------------------------------------------------
-- If the write buffer is almost full set the full retry flag
-- keep this flag set until the write buffer empties. This
-- will prevent further cycles from occuring once the write
-- buffer becomes full.
RETRY_FULL_PROCESS : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
-- When buffer returns to empty state then reset retry flag
if(Bus_reset = '1' or wrbuf_empty_i = '1')then
wrbuf_full_retry <= '0';
-- When buffer is almost full set retry flag
elsif(wrbuf_going_full = '1')then
wrbuf_full_retry <= '1';
end if;
end if;
end process RETRY_FULL_PROCESS;
wrbuf_retry_i <= (xfer_start and not wrbuf_empty_i)
or (RNW and not wrbuf_empty_i)
or (wrbuf_full_retry);
WrBuf_retry <= wrbuf_retry_i;
-------------------------------------------------------------------------------
-- Transaction Error
-------------------------------------------------------------------------------
-- This signal is never asserted
WrBuf_errack <= '0';
-------------------------------------------------------------------------------
-- Actual write buffer implemented using SRL_FIFO
-------------------------------------------------------------------------------
WRBUF_DATA_FIFO: entity opb_v20_v1_10_d.srl_fifo3
generic map ( C_DWIDTH => C_OPB_DWIDTH,
C_DEPTH => C_WRBUF_DEPTH)
port map (
Clk => Bus_clk,
Reset => Bus_reset,
FIFO_Write => wrbuf_write,
Data_In => Data_in,
FIFO_Read => wrbuf_read,
Data_Out => wrbuf_data_i,
FIFO_Full => wrbuf_full,
FIFO_Empty => wrbuf_empty_i,
FIFO_AlmostEmpty => wrbuf_going_empty,
Data_Exists => open,
Addr => wrbuf_addr
);
-------------------------------------------------------------------------------
-- Generation of write buffer control signals
-------------------------------------------------------------------------------
FIFO_WRITE_2_GEN : if not(C_INCLUDE_OPBIN_PSTAGE)
and (C_INCLUDE_IPIC_PSTAGE)
and not(C_INCLUDE_OPBOUT_PSTAGE) generate
wrbuf_write_i <= (xfer_start and not RNW and not Burst and not(wrbuf_retry_i))
or (wr_ce_i and not(wrbuf_retry_d1) and not(wrbuf_retry_i));
end generate;
FIFO_WRITE_REST_GEN : if C_INCLUDE_OPBIN_PSTAGE
or not(C_INCLUDE_IPIC_PSTAGE)
or C_INCLUDE_OPBOUT_PSTAGE generate
wrbuf_write_i <= (xfer_start and not RNW and not Burst and not(wrbuf_retry_i))
or (wr_ce_i and not(wrbuf_retry_d1));
end generate;
wrbuf_write <= wrbuf_write_i;
wrbuf_read <= Wrdata_ack;
-- Write Buffer is almost full
wrbuf_going_full <= '1' when wrbuf_addr >= C_WRBUF_DEPTH-3
else '0';
REG_FOR_FMAX_PROCESS : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wrbuf_xferack_d1 <= wrbuf_xferack_cmb;
wrbuf_retry_d1 <= wrbuf_retry_i;
end if;
end process REG_FOR_FMAX_PROCESS;
-- Generate register for pipeline models 5 and 7
REGWRCE_GEN_5_7 : if C_INCLUDE_OPBIN_PSTAGE and C_INCLUDE_OPBOUT_PSTAGE generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst
and not(wrbuf_retry_d2);
wrbuf_retry_d2 <= wrbuf_retry_d1;
end if;
end process REG_WRCE;
end generate;
-- Generate register for pipeline models 1,3,4, and 6
REGWRCE_GEN_1_3_4_6 : if (C_INCLUDE_OPBIN_PSTAGE and not(C_INCLUDE_OPBOUT_PSTAGE))
or (not(C_INCLUDE_OPBIN_PSTAGE) and C_INCLUDE_OPBOUT_PSTAGE) generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst
and not(wrbuf_retry_d1);
end if;
end process REG_WRCE;
end generate;
-- Generate register for pipeline models 0 and 2
REGWRCE_GEN_0_2 : if not(C_INCLUDE_OPBIN_PSTAGE) and not(C_INCLUDE_OPBOUT_PSTAGE) generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst;
end if;
end process REG_WRCE;
end generate;
-------------------------------------------------------------------------------
-- Need to count number of valid addresses to be generated (matches the number
-- of data words written into the write buffer) and allow the
-- address counter to only produce that number of addresses
-- counter only needs to count to the max buffer size (16)
-- count up with each wrbuf_write and count down with each Addr_ack - don't
-- count when wrbuf_write and Addr_ack are both asserted
--------------------------------------------------------------------------------
valid_addr_cntr_ce <= wrbuf_write xor Addr_ack;
VALID_ADDR_CNTR: entity opb_v20_v1_10_d.counter
generic map ( C_NUM_BITS => 5)
port map (
Clk => Bus_clk,
Rst => cs_rnw_rst,
Load_In => ZERO_LOAD,
Count_Enable => valid_addr_cntr_ce,
Count_Load => '0',
Count_Down => Addr_ack,
Count_Out => valid_addr_cnt,
Carry_Out => open
);
wrbuf_addrcnt_en_i <= '0' when (valid_addr_cnt = "00000" and wrbuf_rnw_i = '0')
else '1';
wrbuf_addrcntr_rst_i <= '1'
when ( (valid_addr_cnt = "00001" and Addr_Ack = '1'
and valid_addr_cntr_ce ='1')
or Bus_reset = '1' )
else '0';
WRBUF_ADDRVALID_REG: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if (wrbuf_addrcntr_rst_i = '1' and wrbuf_rnw_i = '0')
or (wrbuf_rnw_i = '1' and Addr_ack = '1' and wrbuf_burst_i ='0') then
wrbuf_addrvalid_i <= '0';
elsif xfer_start = '1' then
wrbuf_addrvalid_i <= '1';
end if;
end if;
end process WRBUF_ADDRVALID_REG;
WrBuf_AddrValid <= wrbuf_addrvalid_i when or_reduce(wrbuf_cs_i) = '1'
else '0';
-------------------------------------------------------------------------------
-- Sample and hold Bus2IP_CS, Bus2IP_Burst and Bus2IP_RNW until write buffer is
-- empty and Ack is received from the IP since the OPB Address, SeqAddr, and RNW
-- signals will be modified for the next transaction
--
-- Delay CEs by 1 clock to account for buffer delay
-------------------------------------------------------------------------------
XFER_START_REG_PROCESS: process(Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if or_reduce(CS_enable) = '1' then
xfer_start_reg <= '0';
elsif xfer_start = '1' then
xfer_start_reg <= '1';
end if;
end if;
end process XFER_START_REG_PROCESS;
sample_hold_ce <= ((xfer_start or xfer_start_reg) and wrbuf_empty_i);
DELAY_REG: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
wrbuf_empty_d1 <= wrbuf_empty_i;
wrdata_ack_d1 <= Wrdata_ack;
wrbuf_write_d1 <= wrbuf_write;
burst_d1 <= Burst; --GB
end if;
end process DELAY_REG;
cs_rnw_rst <= Bus_reset or
(not(wrbuf_rnw_i) and wrbuf_going_empty and wrdata_ack ) or
(wrbuf_rnw_i and Xfer_done);
wrbuf_empty_fe <= not(wrbuf_empty_i) and wrbuf_empty_d1;
wrbuf_write_re <= wrbuf_write and not(wrbuf_write_d1);
BURST_RNW_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
wrbuf_rnw_i <= '0';
wrbuf_burst_i <= '0';
elsif sample_hold_ce = '1' then
wrbuf_rnw_i <= RNW;
wrbuf_burst_i <= Burst;
end if;
end if;
end process BURST_RNW_SAMPLE_HOLD;
-- Logic for negating burst signal 1 clock before end of cycle.
wrbuf2ip_burst <= wrbuf_burst_i when cs_rnw_rst='0' and or_reduce(wrbuf_cs_i) = '1'
else '0';
----------------------------------------------------------------------
-- Bus2IP Control Signals
----------------------------------------------------------------------
-- Generate for no output pipeline stage
GEN_WITHOUT_OUTPIPE : if C_INCLUDE_OPBOUT_PSTAGE = false generate
CS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
wrbuf_cs_i <= (others => '0');
wrbuf_wrce_i <= (others => '0');
wrbuf_rdce_i <= (others => '0');
wrbuf_ce_i <= (others => '0');
elsif wrbuf_write_re = '1' or
(sample_hold_ce = '1' and RNW = '1') then
wrbuf_cs_i <= CS;
wrbuf_wrce_i <= Wr_CE;
wrbuf_rdce_i <= Rd_CE;
wrbuf_ce_i <= CE;
end if;
end if;
end process CS_SAMPLE_HOLD;
end generate GEN_WITHOUT_OUTPIPE;
-- Generate for output pipeline stage
GEN_WITH_OUTPIPE : if C_INCLUDE_OPBOUT_PSTAGE = true generate
signal read_rdce_i : std_logic_vector(0 to C_NUM_CES-1);
signal read_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal read_ce_i : std_logic_vector(0 to C_NUM_CES-1);
signal write_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal write_ce_i : std_logic_vector(0 to C_NUM_CES-1);
begin
WRCS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
write_cs_i <= (others => '0');
wrbuf_wrce_i <= (others => '0');
write_ce_i <= (others => '0');
elsif wrbuf_write_re = '1' then
write_cs_i <= CS;
wrbuf_wrce_i <= Wr_CE;
write_ce_i <= CE;
end if;
end if;
end process WRCS_SAMPLE_HOLD;
RDCS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
read_cs_i <= (others => '0');
read_rdce_i <= (others => '0');
read_ce_i <= (others => '0');
elsif sample_hold_ce = '1' and RNW = '1' then
read_cs_i <= CS;
read_rdce_i <= Rd_CE;
read_ce_i <= CE;
end if;
end if;
end process RDCS_SAMPLE_HOLD;
-- Gate off rdce signal to make it a single clock cycle during single beat reads
GEN_RDCE_BUS : process(read_rdce_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_CES-1 loop
wrbuf_rdce_i(i) <= (read_rdce_i(i) and wrbuf_burst_i)
or (read_rdce_i(i) and not(wrbuf_burst_i) and not Xfer_done);
end loop;
end process GEN_RDCE_BUS;
-- Gate off ce signal to make it a single clock cycle during single beat reads
GEN_CE_BUS : process(write_ce_i,read_ce_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_CES-1 loop
wrbuf_ce_i(i) <= (read_ce_i(i) and wrbuf_burst_i)
or (read_ce_i(i) and not(wrbuf_burst_i) and not Xfer_done)
or write_ce_i(i);
end loop;
end process GEN_CE_BUS;
-- Gate off cs signal to make it a single clock cycle during single beat reads
GEN_CS_BUS : process(write_cs_i,read_cs_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_ARDS-1 loop
wrbuf_cs_i(i) <= (read_cs_i(i) and wrbuf_burst_i)
or (read_cs_i(i) and not(wrbuf_burst_i) and not Xfer_done)
or write_cs_i(i);
end loop;
end process GEN_CS_BUS;
end generate GEN_WITH_OUTPIPE;
-------------------------------------------------------------------------------
-- Logic when IPIC_PSTAGE is included
-------------------------------------------------------------------------------
IPIC_PSTAGE_GEN: if C_INCLUDE_IPIC_PSTAGE generate
IPIC_Pstage_CE <= not(wrbuf_empty_i);
end generate IPIC_PSTAGE_GEN;
NO_IPIC_PSTAGE_GEN: if not(C_INCLUDE_IPIC_PSTAGE) generate
IPIC_Pstage_CE <= '1';
end generate NO_IPIC_PSTAGE_GEN;
end implementation;
|
-------------------------------------------------------------------------------
-- $Id: write_buffer.vhd,v 1.1.2.1 2009/10/06 21:15:02 gburch Exp $
-------------------------------------------------------------------------------
-- write_buffer.vhd - vhdl design file for the entity and architecture
-- of the Mauna Loa IPIF Bus to IPIF Bus Address
-- multiplexer.
-------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2004,2009 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: write_buffer.vhd
--
-- Description: This vhdl design file is for the entity and architecture
-- of the write buffer design.
--
-------------------------------------------------------------------------------
-- Structure:
--
--
-- write_buffer.vhd
--
-------------------------------------------------------------------------------
-- Author: ALS
-- History:
--
--
-- GAB 04/14/04
-- ^^^^^^
-- Updated to proc_common_v2_00_a
-- Fixed issues with master aborts, delayed IP acknowledges, and single
-- beat reads (i.e. rdce was 2 clocks wide)
-- ~~~~~~~
-- GAB 07/07/04
-- ^^^^^^
-- Fixed issues with xferack due to changes in opb_bam signal timing
-- Fixed wrbuf_burst signal to negate 1 cycle before cs negates
-- Fixed wrbuf_addrvalid signal to only drive during valid addresses
-- ~~~~~~~
-- GAB 10/05/09
-- ^^^^^^
-- Moved all helper libraries proc_common_v2_00_a, opb_ipif_v3_01_a, and
-- opb_arbiter_v1_02_e locally into opb_v20_v1_10_d
--
-- Updated legal header
-- ~~~~~~
---------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
-- Library definitions
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.or_reduce;
library unisim;
use unisim.vcomponents.all;
library opb_v20_v1_10_d;
use opb_v20_v1_10_d.srl_fifo3;
use opb_v20_v1_10_d.proc_common_pkg.log2;
use opb_v20_v1_10_d.counter;
-------------------------------------------------------------------------------
-- Port Declaration
-------------------------------------------------------------------------------
entity write_buffer is
generic (
C_INCLUDE_OPBIN_PSTAGE : boolean := TRUE;
C_INCLUDE_IPIC_PSTAGE : boolean := TRUE;
C_INCLUDE_OPBOUT_PSTAGE : boolean := TRUE;
C_OPB_DWIDTH : integer := 32;
C_WRBUF_DEPTH : integer := 16; -- max is 16
C_NUM_CES : integer := 4;
C_NUM_ARDS : integer := 4
);
port (
-- Clock and Reset
Bus_reset : in std_logic;
Bus_clk : in std_logic;
-- Inputs
Data_in : in std_logic_vector(0 to C_OPB_DWIDTH-1);
CE : in std_logic_vector(0 to C_NUM_CES-1);
Wr_CE : in std_logic_vector(0 to C_NUM_CES-1);
Rd_CE : in std_logic_vector(0 to C_NUM_CES-1);
RNW : in std_logic;
CS_hit : in std_logic_vector(0 to C_NUM_ARDS-1);
CS : in std_logic_vector(0 to C_NUM_ARDS-1);
CS_enable : in std_logic_vector(0 to C_NUM_ARDS-1);
Burst : in std_logic;
Xfer_start : in std_logic;
Xfer_done : in std_logic;
Addr_ack : in std_logic;
Wrdata_ack : in std_logic;
WrBuf_data : out std_logic_vector(0 to C_OPB_DWIDTH-1);
WrBuf_burst : out std_logic;
WrBuf_xferack : out std_logic;
WrBuf_errack : out std_logic;
WrBuf_retry : out std_logic;
WrBuf_CS : out std_logic_vector(0 to C_NUM_ARDS-1);
WrBuf_RNW : out std_logic;
WrBuf_CE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_WrCE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_RdCE : out std_logic_vector(0 to C_NUM_CES-1);
WrBuf_Empty : out std_logic;
WrBuf_AddrCnt_en : out std_logic;
WrBuf_AddrCntr_rst : out std_logic;
WrBuf_AddrValid : out std_logic;
IPIC_Pstage_CE : out std_logic
);
end write_buffer;
architecture implementation of write_buffer is
-----------------------------------------------------------------------------
-- Functions
-----------------------------------------------------------------------------
function "and" ( l : std_logic_vector; r : std_logic )
return std_logic_vector is
variable rex : std_logic_vector(l'range);
begin
rex := (others=>r);
return( l and rex );
end function "and";
-------------------------------------------------------------------------------
-- Constant Declaration
-------------------------------------------------------------------------------
constant ZERO_LOAD : std_logic_vector(0 to 4) := (others => '0');
-------------------------------------------------------------------------------
-- Signal Declaration
-------------------------------------------------------------------------------
signal wrbuf_write : std_logic;
signal wrbuf_write_d1 : std_logic;
signal wrbuf_write_re : std_logic;
signal wrbuf_read : std_logic;
signal wrbuf_data_i : std_logic_vector(0 to C_OPB_DWIDTH-1);
signal wrbuf_full : std_logic;
signal wrbuf_empty_i : std_logic;
signal wrbuf_empty_d1 : std_logic;
signal wrbuf_empty_fe : std_logic;
signal wrdata_ack_d1 : std_logic;
signal wrbuf_addr : std_logic_vector(0 to 3);
signal wrbuf_going_full : std_logic;
signal wrbuf_going_empty : std_logic;
signal wrbuf_wrce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_rdce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_ce_i : std_logic_vector(0 to C_NUM_CES-1);
signal wrbuf_rnw_i : std_logic;
signal wrbuf_burst_i : std_logic;
signal wrbuf_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal wrbuf_addrcnt_en_i : std_logic;
signal wrbuf_addrcntr_rst_i: std_logic;
signal wrbuf_xferack_i : std_logic;
signal wrbuf_retry_i : std_logic;
signal wrbuf_retry_d1 : std_logic;
signal wrbuf_retry_d2 : std_logic;
signal valid_addr_cntr_ce : std_logic;
signal valid_addr_cnt : std_logic_vector(0 to 4);
signal sample_hold_ce : std_logic;
signal xfer_start_reg : std_logic;
signal cs_rnw_rst : std_logic;
signal wrbuf_write_i : std_logic;
signal burst_d1 : std_logic;
signal wrbuf_full_retry : std_logic;
signal wrbuf_xferack_cmb : std_logic;
signal wrbuf_xferack_d1 : std_logic;
signal wr_ce_i : std_logic;
signal wrbuf2ip_burst : std_logic;
signal wrbuf_addrvalid_i : std_logic;
-------------------------------------------------------------------------------
-- Begin
-------------------------------------------------------------------------------
begin
-------------------------------------------------------------------------------
-- Output assignments
-------------------------------------------------------------------------------
WrBuf_data <= wrbuf_data_i;
WrBuf_RNW <= wrbuf_rnw_i;
WrBuf_Burst <= wrbuf2ip_burst;
WrBuf_WrCE <= wrbuf_wrce_i;
WrBuf_RdCE <= wrbuf_rdce_i;
WrBuf_CE <= wrbuf_ce_i;
WrBuf_CS <= wrbuf_cs_i;
WrBuf_AddrCnt_en <= wrbuf_addrcnt_en_i;
WrBuf_AddrCntr_Rst <= wrbuf_addrcntr_rst_i;
WrBuf_Empty <= wrbuf_empty_i;
-------------------------------------------------------------------------------
-- Transaction acknowledges
-------------------------------------------------------------------------------
-- XferAck--
-- Assert XferAck when at the start of a xfer if wrbuffer is empty, keep
-- asserted until wrbuffer is full or cs_hit = 0
-- Don't need to qualify with CS_Hit because the XferAck logic in OPB_BAM
-- takes care of this
--ToDo: see if wrbuf_going_empty can be used
XFERACK_REG: process(Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if or_reduce(CS_hit) ='0'
or (wrbuf_xferack_i = '1' and Burst = '0')
or (wrbuf_rnw_i='0' and wrbuf_going_empty='1' and wrdata_ack='1')then
wrbuf_xferack_i <= '0';
elsif xfer_start = '1' and wrbuf_empty_i = '1' and RNW = '0' then
wrbuf_xferack_i <= '1';
end if;
end if;
end process XFERACK_REG;
wrbuf_xferack_cmb <= (((wrbuf_xferack_i and or_reduce(CS_hit))
or (or_reduce(CS_hit) and wrbuf_empty_i
and not(RNW) and xfer_start and Burst))
and not wrbuf_going_full);
-- Generate for pipeline models 5 and 7
GEN_PIPE_5_7 : if C_INCLUDE_OPBIN_PSTAGE = true
and C_INCLUDE_OPBOUT_PSTAGE = true generate
WrBuf_xferack <= wrbuf_xferack_d1 and not wrbuf_going_full
and not wrbuf_retry_i and or_reduce(CS_hit);
end generate;
-- Generate for pipeline models 1,2,3,4,and 6
GEN_PIPE_THE_REST : if (C_INCLUDE_OPBIN_PSTAGE = false
or C_INCLUDE_OPBOUT_PSTAGE = false)generate
WrBuf_xferack <= wrbuf_xferack_d1 and not wrbuf_retry_i
and or_reduce(CS_hit);
end generate;
-------------------------------------------------------------------------------
-- Transaction Retry
-------------------------------------------------------------------------------
-- If the write buffer is almost full set the full retry flag
-- keep this flag set until the write buffer empties. This
-- will prevent further cycles from occuring once the write
-- buffer becomes full.
RETRY_FULL_PROCESS : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
-- When buffer returns to empty state then reset retry flag
if(Bus_reset = '1' or wrbuf_empty_i = '1')then
wrbuf_full_retry <= '0';
-- When buffer is almost full set retry flag
elsif(wrbuf_going_full = '1')then
wrbuf_full_retry <= '1';
end if;
end if;
end process RETRY_FULL_PROCESS;
wrbuf_retry_i <= (xfer_start and not wrbuf_empty_i)
or (RNW and not wrbuf_empty_i)
or (wrbuf_full_retry);
WrBuf_retry <= wrbuf_retry_i;
-------------------------------------------------------------------------------
-- Transaction Error
-------------------------------------------------------------------------------
-- This signal is never asserted
WrBuf_errack <= '0';
-------------------------------------------------------------------------------
-- Actual write buffer implemented using SRL_FIFO
-------------------------------------------------------------------------------
WRBUF_DATA_FIFO: entity opb_v20_v1_10_d.srl_fifo3
generic map ( C_DWIDTH => C_OPB_DWIDTH,
C_DEPTH => C_WRBUF_DEPTH)
port map (
Clk => Bus_clk,
Reset => Bus_reset,
FIFO_Write => wrbuf_write,
Data_In => Data_in,
FIFO_Read => wrbuf_read,
Data_Out => wrbuf_data_i,
FIFO_Full => wrbuf_full,
FIFO_Empty => wrbuf_empty_i,
FIFO_AlmostEmpty => wrbuf_going_empty,
Data_Exists => open,
Addr => wrbuf_addr
);
-------------------------------------------------------------------------------
-- Generation of write buffer control signals
-------------------------------------------------------------------------------
FIFO_WRITE_2_GEN : if not(C_INCLUDE_OPBIN_PSTAGE)
and (C_INCLUDE_IPIC_PSTAGE)
and not(C_INCLUDE_OPBOUT_PSTAGE) generate
wrbuf_write_i <= (xfer_start and not RNW and not Burst and not(wrbuf_retry_i))
or (wr_ce_i and not(wrbuf_retry_d1) and not(wrbuf_retry_i));
end generate;
FIFO_WRITE_REST_GEN : if C_INCLUDE_OPBIN_PSTAGE
or not(C_INCLUDE_IPIC_PSTAGE)
or C_INCLUDE_OPBOUT_PSTAGE generate
wrbuf_write_i <= (xfer_start and not RNW and not Burst and not(wrbuf_retry_i))
or (wr_ce_i and not(wrbuf_retry_d1));
end generate;
wrbuf_write <= wrbuf_write_i;
wrbuf_read <= Wrdata_ack;
-- Write Buffer is almost full
wrbuf_going_full <= '1' when wrbuf_addr >= C_WRBUF_DEPTH-3
else '0';
REG_FOR_FMAX_PROCESS : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wrbuf_xferack_d1 <= wrbuf_xferack_cmb;
wrbuf_retry_d1 <= wrbuf_retry_i;
end if;
end process REG_FOR_FMAX_PROCESS;
-- Generate register for pipeline models 5 and 7
REGWRCE_GEN_5_7 : if C_INCLUDE_OPBIN_PSTAGE and C_INCLUDE_OPBOUT_PSTAGE generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst
and not(wrbuf_retry_d2);
wrbuf_retry_d2 <= wrbuf_retry_d1;
end if;
end process REG_WRCE;
end generate;
-- Generate register for pipeline models 1,3,4, and 6
REGWRCE_GEN_1_3_4_6 : if (C_INCLUDE_OPBIN_PSTAGE and not(C_INCLUDE_OPBOUT_PSTAGE))
or (not(C_INCLUDE_OPBIN_PSTAGE) and C_INCLUDE_OPBOUT_PSTAGE) generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst
and not(wrbuf_retry_d1);
end if;
end process REG_WRCE;
end generate;
-- Generate register for pipeline models 0 and 2
REGWRCE_GEN_0_2 : if not(C_INCLUDE_OPBIN_PSTAGE) and not(C_INCLUDE_OPBOUT_PSTAGE) generate
REG_WRCE : process(Bus_clk)
begin
if(Bus_clk'EVENT and Bus_clk = '1')then
wr_ce_i <= or_reduce(Wr_CE)
and Burst;
end if;
end process REG_WRCE;
end generate;
-------------------------------------------------------------------------------
-- Need to count number of valid addresses to be generated (matches the number
-- of data words written into the write buffer) and allow the
-- address counter to only produce that number of addresses
-- counter only needs to count to the max buffer size (16)
-- count up with each wrbuf_write and count down with each Addr_ack - don't
-- count when wrbuf_write and Addr_ack are both asserted
--------------------------------------------------------------------------------
valid_addr_cntr_ce <= wrbuf_write xor Addr_ack;
VALID_ADDR_CNTR: entity opb_v20_v1_10_d.counter
generic map ( C_NUM_BITS => 5)
port map (
Clk => Bus_clk,
Rst => cs_rnw_rst,
Load_In => ZERO_LOAD,
Count_Enable => valid_addr_cntr_ce,
Count_Load => '0',
Count_Down => Addr_ack,
Count_Out => valid_addr_cnt,
Carry_Out => open
);
wrbuf_addrcnt_en_i <= '0' when (valid_addr_cnt = "00000" and wrbuf_rnw_i = '0')
else '1';
wrbuf_addrcntr_rst_i <= '1'
when ( (valid_addr_cnt = "00001" and Addr_Ack = '1'
and valid_addr_cntr_ce ='1')
or Bus_reset = '1' )
else '0';
WRBUF_ADDRVALID_REG: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if (wrbuf_addrcntr_rst_i = '1' and wrbuf_rnw_i = '0')
or (wrbuf_rnw_i = '1' and Addr_ack = '1' and wrbuf_burst_i ='0') then
wrbuf_addrvalid_i <= '0';
elsif xfer_start = '1' then
wrbuf_addrvalid_i <= '1';
end if;
end if;
end process WRBUF_ADDRVALID_REG;
WrBuf_AddrValid <= wrbuf_addrvalid_i when or_reduce(wrbuf_cs_i) = '1'
else '0';
-------------------------------------------------------------------------------
-- Sample and hold Bus2IP_CS, Bus2IP_Burst and Bus2IP_RNW until write buffer is
-- empty and Ack is received from the IP since the OPB Address, SeqAddr, and RNW
-- signals will be modified for the next transaction
--
-- Delay CEs by 1 clock to account for buffer delay
-------------------------------------------------------------------------------
XFER_START_REG_PROCESS: process(Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
if or_reduce(CS_enable) = '1' then
xfer_start_reg <= '0';
elsif xfer_start = '1' then
xfer_start_reg <= '1';
end if;
end if;
end process XFER_START_REG_PROCESS;
sample_hold_ce <= ((xfer_start or xfer_start_reg) and wrbuf_empty_i);
DELAY_REG: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk = '1' then
wrbuf_empty_d1 <= wrbuf_empty_i;
wrdata_ack_d1 <= Wrdata_ack;
wrbuf_write_d1 <= wrbuf_write;
burst_d1 <= Burst; --GB
end if;
end process DELAY_REG;
cs_rnw_rst <= Bus_reset or
(not(wrbuf_rnw_i) and wrbuf_going_empty and wrdata_ack ) or
(wrbuf_rnw_i and Xfer_done);
wrbuf_empty_fe <= not(wrbuf_empty_i) and wrbuf_empty_d1;
wrbuf_write_re <= wrbuf_write and not(wrbuf_write_d1);
BURST_RNW_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
wrbuf_rnw_i <= '0';
wrbuf_burst_i <= '0';
elsif sample_hold_ce = '1' then
wrbuf_rnw_i <= RNW;
wrbuf_burst_i <= Burst;
end if;
end if;
end process BURST_RNW_SAMPLE_HOLD;
-- Logic for negating burst signal 1 clock before end of cycle.
wrbuf2ip_burst <= wrbuf_burst_i when cs_rnw_rst='0' and or_reduce(wrbuf_cs_i) = '1'
else '0';
----------------------------------------------------------------------
-- Bus2IP Control Signals
----------------------------------------------------------------------
-- Generate for no output pipeline stage
GEN_WITHOUT_OUTPIPE : if C_INCLUDE_OPBOUT_PSTAGE = false generate
CS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
wrbuf_cs_i <= (others => '0');
wrbuf_wrce_i <= (others => '0');
wrbuf_rdce_i <= (others => '0');
wrbuf_ce_i <= (others => '0');
elsif wrbuf_write_re = '1' or
(sample_hold_ce = '1' and RNW = '1') then
wrbuf_cs_i <= CS;
wrbuf_wrce_i <= Wr_CE;
wrbuf_rdce_i <= Rd_CE;
wrbuf_ce_i <= CE;
end if;
end if;
end process CS_SAMPLE_HOLD;
end generate GEN_WITHOUT_OUTPIPE;
-- Generate for output pipeline stage
GEN_WITH_OUTPIPE : if C_INCLUDE_OPBOUT_PSTAGE = true generate
signal read_rdce_i : std_logic_vector(0 to C_NUM_CES-1);
signal read_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal read_ce_i : std_logic_vector(0 to C_NUM_CES-1);
signal write_cs_i : std_logic_vector(0 to C_NUM_ARDS-1);
signal write_ce_i : std_logic_vector(0 to C_NUM_CES-1);
begin
WRCS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
write_cs_i <= (others => '0');
wrbuf_wrce_i <= (others => '0');
write_ce_i <= (others => '0');
elsif wrbuf_write_re = '1' then
write_cs_i <= CS;
wrbuf_wrce_i <= Wr_CE;
write_ce_i <= CE;
end if;
end if;
end process WRCS_SAMPLE_HOLD;
RDCS_SAMPLE_HOLD: process (Bus_clk)
begin
if Bus_clk'event and Bus_clk='1' then
if cs_rnw_rst = '1' then
read_cs_i <= (others => '0');
read_rdce_i <= (others => '0');
read_ce_i <= (others => '0');
elsif sample_hold_ce = '1' and RNW = '1' then
read_cs_i <= CS;
read_rdce_i <= Rd_CE;
read_ce_i <= CE;
end if;
end if;
end process RDCS_SAMPLE_HOLD;
-- Gate off rdce signal to make it a single clock cycle during single beat reads
GEN_RDCE_BUS : process(read_rdce_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_CES-1 loop
wrbuf_rdce_i(i) <= (read_rdce_i(i) and wrbuf_burst_i)
or (read_rdce_i(i) and not(wrbuf_burst_i) and not Xfer_done);
end loop;
end process GEN_RDCE_BUS;
-- Gate off ce signal to make it a single clock cycle during single beat reads
GEN_CE_BUS : process(write_ce_i,read_ce_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_CES-1 loop
wrbuf_ce_i(i) <= (read_ce_i(i) and wrbuf_burst_i)
or (read_ce_i(i) and not(wrbuf_burst_i) and not Xfer_done)
or write_ce_i(i);
end loop;
end process GEN_CE_BUS;
-- Gate off cs signal to make it a single clock cycle during single beat reads
GEN_CS_BUS : process(write_cs_i,read_cs_i, Xfer_done, wrbuf_burst_i)
begin
for i in 0 to C_NUM_ARDS-1 loop
wrbuf_cs_i(i) <= (read_cs_i(i) and wrbuf_burst_i)
or (read_cs_i(i) and not(wrbuf_burst_i) and not Xfer_done)
or write_cs_i(i);
end loop;
end process GEN_CS_BUS;
end generate GEN_WITH_OUTPIPE;
-------------------------------------------------------------------------------
-- Logic when IPIC_PSTAGE is included
-------------------------------------------------------------------------------
IPIC_PSTAGE_GEN: if C_INCLUDE_IPIC_PSTAGE generate
IPIC_Pstage_CE <= not(wrbuf_empty_i);
end generate IPIC_PSTAGE_GEN;
NO_IPIC_PSTAGE_GEN: if not(C_INCLUDE_IPIC_PSTAGE) generate
IPIC_Pstage_CE <= '1';
end generate NO_IPIC_PSTAGE_GEN;
end implementation;
|
library ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rca is
generic (M : integer := 64);
Port ( A : in std_logic_vector(M-1 downto 0);
B : in std_logic_vector(M-1 downto 0);
Cin : in std_logic_vector(0 downto 0); -- small trick to have an easy conversion to unsigned
S : out std_logic_vector(M-1 downto 0);
Cout : out std_logic
);
end rca;
architecture behavioral of rca is
signal temp : std_logic_vector(M downto 0);
begin
temp <= std_logic_vector(unsigned('0'&A) + unsigned('0'&B) + unsigned(Cin));
S <= temp(M-1 downto 0);
Cout <= temp(M);
end behavioral;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:proc_sys_reset:5.0
-- IP Revision: 10
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_rst_ps7_0_100M_0 IS
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END design_1_rst_ps7_0_100M_0;
ARCHITECTURE design_1_rst_ps7_0_100M_0_arch OF design_1_rst_ps7_0_100M_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "yes";
COMPONENT proc_sys_reset IS
GENERIC (
C_FAMILY : STRING;
C_EXT_RST_WIDTH : INTEGER;
C_AUX_RST_WIDTH : INTEGER;
C_EXT_RESET_HIGH : STD_LOGIC;
C_AUX_RESET_HIGH : STD_LOGIC;
C_NUM_BUS_RST : INTEGER;
C_NUM_PERP_RST : INTEGER;
C_NUM_INTERCONNECT_ARESETN : INTEGER;
C_NUM_PERP_ARESETN : INTEGER
);
PORT (
slowest_sync_clk : IN STD_LOGIC;
ext_reset_in : IN STD_LOGIC;
aux_reset_in : IN STD_LOGIC;
mb_debug_sys_rst : IN STD_LOGIC;
dcm_locked : IN STD_LOGIC;
mb_reset : OUT STD_LOGIC;
bus_struct_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_reset : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
interconnect_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
peripheral_aresetn : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT proc_sys_reset;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "proc_sys_reset,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_rst_ps7_0_100M_0_arch : ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_rst_ps7_0_100M_0_arch: ARCHITECTURE IS "design_1_rst_ps7_0_100M_0,proc_sys_reset,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=proc_sys_reset,x_ipVersion=5.0,x_ipCoreRevision=10,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=zynq,C_EXT_RST_WIDTH=4,C_AUX_RST_WIDTH=4,C_EXT_RESET_HIGH=0,C_AUX_RESET_HIGH=0,C_NUM_BUS_RST=1,C_NUM_PERP_RST=1,C_NUM_INTERCONNECT_ARESETN=1,C_NUM_PERP_ARESETN=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF slowest_sync_clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clock CLK";
ATTRIBUTE X_INTERFACE_INFO OF ext_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 ext_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF aux_reset_in: SIGNAL IS "xilinx.com:signal:reset:1.0 aux_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_debug_sys_rst: SIGNAL IS "xilinx.com:signal:reset:1.0 dbg_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF mb_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 mb_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF bus_struct_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 bus_struct_reset RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_reset: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_high_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF interconnect_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 interconnect_low_rst RST";
ATTRIBUTE X_INTERFACE_INFO OF peripheral_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 peripheral_low_rst RST";
BEGIN
U0 : proc_sys_reset
GENERIC MAP (
C_FAMILY => "zynq",
C_EXT_RST_WIDTH => 4,
C_AUX_RST_WIDTH => 4,
C_EXT_RESET_HIGH => '0',
C_AUX_RESET_HIGH => '0',
C_NUM_BUS_RST => 1,
C_NUM_PERP_RST => 1,
C_NUM_INTERCONNECT_ARESETN => 1,
C_NUM_PERP_ARESETN => 1
)
PORT MAP (
slowest_sync_clk => slowest_sync_clk,
ext_reset_in => ext_reset_in,
aux_reset_in => aux_reset_in,
mb_debug_sys_rst => mb_debug_sys_rst,
dcm_locked => dcm_locked,
mb_reset => mb_reset,
bus_struct_reset => bus_struct_reset,
peripheral_reset => peripheral_reset,
interconnect_aresetn => interconnect_aresetn,
peripheral_aresetn => peripheral_aresetn
);
END design_1_rst_ps7_0_100M_0_arch;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use work.constants.all;
entity left_XLEN_barrel_shifter is
port( i : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic_vector(4 downto 0);
o : out std_logic_vector(XLEN -1 downto 0)
);
end left_XLEN_barrel_shifter;
architecture structural of left_XLEN_barrel_shifter is
component muxXLEN2a1
port( i0, i1 : in std_logic_vector(XLEN -1 downto 0);
s : in std_logic;
o : out std_logic_vector(XLEN -1 downto 0)
);
end component;
signal s1, s2, s3, s4 : std_logic_vector(XLEN -1 downto 0);
signal aux0, aux1, aux2, aux3, aux4 : std_logic_vector(XLEN -1 downto 0);
begin
aux0 <= i (30 downto 0) & '0';
ins0: muxXLEN2a1 port map(i , aux0, s(0), s1);
aux1 <= s1 (29 downto 0) & "00";
ins1: muxXLEN2a1 port map(s1, aux1, s(1), s2);
aux2 <= s2 (27 downto 0) & "0000";
ins2: muxXLEN2a1 port map(s2, aux2, s(2), s3);
aux3 <= s3 (23 downto 0) & "00000000";
ins3: muxXLEN2a1 port map(s3, aux3, s(3), s4);
aux4 <= s4 (15 downto 0) & "0000000000000000";
ins4: muxXLEN2a1 port map(s4, aux4, s(4), o );
end structural;
|
-- whole_design.vhd
--
-- Created on: 26 Jun 2017
-- Author: Fabian Meyer
library ieee;
use ieee.std_logic_1164.all;
entity whole_design is
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic;
clk: in std_logic;
gpio: in std_logic_vector(5 downto 0);
lcd_en: out std_logic; -- LCD enable
lcd_rw: out std_logic; -- LCD rw
lcd_rs: out std_logic; -- LCD rs
lcd_bl: out std_logic; -- LCD backlight
lcd_data: inout std_logic_vector(3 downto 0)); -- LCD data
end entity;
architecture behavioral of whole_design is
-- import lcd component
component lcd
generic(RSTDEF: std_logic := '0');
port(rst: in std_logic; -- reset, RSTDEF active
clk: in std_logic; -- clock, rising edge
din: in std_logic_vector(7 downto 0); -- data in, 8 bit ASCII char
posx: in std_logic_vector(3 downto 0); -- x position within a line of LCD
posy: in std_logic; -- y position (line number)
flush: in std_logic; -- flush input, high active
rdy: out std_logic; -- ready, high active
en: out std_logic; -- enable, high active
rw: out std_logic;
rs: out std_logic;
bl: out std_logic; -- backlight, high active
data: inout std_logic_vector(3 downto 0)); -- data, dual direction
end component;
-- states for communication over GPIO
type TState is (SIDLE, SCHAR1, SCHAR2, SPOS);
signal state: TState := SIDLE;
-- character that will be written on the LCD
signal char: std_logic_vector(7 downto 0) := (others => '0');
-- position where char will be written
signal pos: std_logic_vector(4 downto 0) := (others => '0');
signal reinit: std_logic := '0';
signal lcd_char: std_logic_vector(7 downto 0) := (others => '0');
signal lcd_pos: std_logic_vector(4 downto 0) := (others => '0');
signal lcd_flush: std_logic := '0';
signal lcd_rdy: std_logic := '0';
signal lcd_rst: std_logic := '1';
-- gpio clock that keeps track of curr and prev signal
-- used to detect rising edges
signal gpio_clk: std_logic_vector(1 downto 0) := (others => '0');
-- payload of gpios whenever we receive rising edge
signal gpio_cmd: std_logic_vector(4 downto 0) := (others => '0');
begin
-- curr gpio clk is msb of gpio
gpio_clk(0) <= gpio(5);
-- remaining bits hold payload
gpio_cmd <= gpio(4 downto 0);
lcd_rst <= RSTDEF when reinit = '1' else rst;
mylcd: lcd
generic map(RSTDEF => RSTDEF)
port map (rst => lcd_rst,
clk => clk,
din => lcd_char,
posx => lcd_pos(3 downto 0),
posy => lcd_pos(4),
flush => lcd_flush,
rdy => lcd_rdy,
en => lcd_en,
rw => lcd_rw,
rs => lcd_rs,
bl => lcd_bl,
data => lcd_data);
process(rst, clk)
begin
if rst = RSTDEF then
state <= SIDLE;
char <= (others => '0');
pos <= (others => '0');
reinit <= '0';
lcd_char <= (others => '0');
lcd_pos <= (others => '0');
lcd_flush <= '0';
gpio_clk(1) <= '0';
elsif rising_edge(clk) then
-- always keep track of prev gpio_clk
-- so we can detect rising and falling edges
gpio_clk(1) <= gpio_clk(0);
-- keep reinit active for only one cycle
reinit <= '0';
-- flush whenever possible
lcd_flush <= '0';
if lcd_rdy = '1' and lcd_flush = '0' and state = SIDLE then
-- data has to be stored temporarily, so it cannot
-- be changed while LCD is writing
lcd_pos <= pos;
lcd_char <= char;
lcd_flush <= '1';
end if;
-- only process communication state machine if
-- gpio_clk shows rising edge
if gpio_clk = "01" then
case state is
when SIDLE =>
-- possible commands:
-- "00001": reset LCD (reinit)
-- "00010": write new char to LCD
-- "00011": change position of character
if gpio_cmd = "00001" then
reinit <= '1';
elsif gpio_cmd = "00010" then
state <= SCHAR1;
elsif gpio_cmd = "00011" then
state <= SPOS;
end if;
when SCHAR1 =>
-- receive first half of character
-- msb of gpio_cmd is unused here
char(7 downto 4) <= gpio_cmd(3 downto 0);
state <= SCHAR2;
when SCHAR2 =>
-- receive second half of character
-- msb of gpio_cmd is unused here
char(3 downto 0) <= gpio_cmd(3 downto 0);
state <= SIDLE;
when SPOS =>
-- gpio_cmd contains position update
-- msb is posy, remaining are posx
pos <= gpio_cmd;
state <= SIDLE;
end case;
end if;
end if;
end process;
end architecture;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity arbiter is
generic(
SIZE : positive
);
port(
requests : in std_logic_vector(SIZE-1 downto 0);
enable : in std_logic;
isOutputSelected : out std_logic;
selectedOutput : out natural range 0 to (SIZE-1)
);
end;
architecture FixedPriorityArbiter of arbiter is
begin
process(requests, enable)
variable auxDone : std_logic;
variable auxSelected : integer range 0 to (SIZE-1);
begin
auxDone := '0';
auxSelected := 0;
if(enable = '1') then
for i in requests'low to requests'high loop
if requests(i) = '1' then
auxSelected := i;
auxDone := '1';
exit;
end if;
end loop;
end if;
isOutputSelected <= auxDone;
selectedOutput <= auxSelected;
end process;
end FixedPriorityArbiter;
architecture RoundRobinArbiter of arbiter is
signal lastPort : integer range 0 to (SIZE-1);
begin
process(enable)
variable SelectedPort : integer range 0 to (SIZE-1) := 0;
variable requestCheck : integer range 0 to (SIZE-1);
begin
if rising_edge(enable) then
requestCheck := lastPort;
SelectedPort := lastPort;
for i in requests'low to requests'high loop
if(requestCheck = SIZE-1) then
requestCheck := 0;
else
requestCheck := requestCheck + 1;
end if;
if(requests(requestCheck) = '1') then
SelectedPort := requestCheck;
exit;
end if;
end loop;
lastPort <= SelectedPort;
selectedOutput <= SelectedPort;
end if;
end process;
isOutputSelected <= enable;
end RoundRobinArbiter;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity arbiter is
generic(
SIZE : positive
);
port(
requests : in std_logic_vector(SIZE-1 downto 0);
enable : in std_logic;
isOutputSelected : out std_logic;
selectedOutput : out natural range 0 to (SIZE-1)
);
end;
architecture FixedPriorityArbiter of arbiter is
begin
process(requests, enable)
variable auxDone : std_logic;
variable auxSelected : integer range 0 to (SIZE-1);
begin
auxDone := '0';
auxSelected := 0;
if(enable = '1') then
for i in requests'low to requests'high loop
if requests(i) = '1' then
auxSelected := i;
auxDone := '1';
exit;
end if;
end loop;
end if;
isOutputSelected <= auxDone;
selectedOutput <= auxSelected;
end process;
end FixedPriorityArbiter;
architecture RoundRobinArbiter of arbiter is
signal lastPort : integer range 0 to (SIZE-1);
begin
process(enable)
variable SelectedPort : integer range 0 to (SIZE-1) := 0;
variable requestCheck : integer range 0 to (SIZE-1);
begin
if rising_edge(enable) then
requestCheck := lastPort;
SelectedPort := lastPort;
for i in requests'low to requests'high loop
if(requestCheck = SIZE-1) then
requestCheck := 0;
else
requestCheck := requestCheck + 1;
end if;
if(requests(requestCheck) = '1') then
SelectedPort := requestCheck;
exit;
end if;
end loop;
lastPort <= SelectedPort;
selectedOutput <= SelectedPort;
end if;
end process;
isOutputSelected <= enable;
end RoundRobinArbiter;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity arbiter is
generic(
SIZE : positive
);
port(
requests : in std_logic_vector(SIZE-1 downto 0);
enable : in std_logic;
isOutputSelected : out std_logic;
selectedOutput : out natural range 0 to (SIZE-1)
);
end;
architecture FixedPriorityArbiter of arbiter is
begin
process(requests, enable)
variable auxDone : std_logic;
variable auxSelected : integer range 0 to (SIZE-1);
begin
auxDone := '0';
auxSelected := 0;
if(enable = '1') then
for i in requests'low to requests'high loop
if requests(i) = '1' then
auxSelected := i;
auxDone := '1';
exit;
end if;
end loop;
end if;
isOutputSelected <= auxDone;
selectedOutput <= auxSelected;
end process;
end FixedPriorityArbiter;
architecture RoundRobinArbiter of arbiter is
signal lastPort : integer range 0 to (SIZE-1);
begin
process(enable)
variable SelectedPort : integer range 0 to (SIZE-1) := 0;
variable requestCheck : integer range 0 to (SIZE-1);
begin
if rising_edge(enable) then
requestCheck := lastPort;
SelectedPort := lastPort;
for i in requests'low to requests'high loop
if(requestCheck = SIZE-1) then
requestCheck := 0;
else
requestCheck := requestCheck + 1;
end if;
if(requests(requestCheck) = '1') then
SelectedPort := requestCheck;
exit;
end if;
end loop;
lastPort <= SelectedPort;
selectedOutput <= SelectedPort;
end if;
end process;
isOutputSelected <= enable;
end RoundRobinArbiter;
|
entity FIFO is
port (
I_WR_EN : IN std_logic;
I_DATA : OUT std_logic_vector(31 downto 0);
I_RD_EN : IN std_logic;
O_DATA : OUT std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
port (
I_WR_EN : IN std_logic;
I_DATA : OUT std_logic_vector(31 downto 0);
I_RD_EN : IN std_logic;
O_DATA : OUT std_logic_vector(31 downto 0)
);
end entity FIFO;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:46:33 07/16/2015
-- Design Name:
-- Module Name: C:/Users/rccoder/ALU/Lab3/serial_tb.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: serial
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY serial_tb IS
END serial_tb;
ARCHITECTURE behavior OF serial_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT serial
PORT(
serialdata : IN std_logic;
clk : IN std_logic;
csn : IN std_logic;
wrn : IN std_logic;
rdn : IN std_logic;
addr : IN std_logic_vector(1 downto 0);
data : INOUT std_logic_vector(7 downto 0);
intn : OUT std_logic
);
END COMPONENT;
--Inputs
signal serialdata : std_logic := '0';
signal clk : std_logic := '0';
signal csn : std_logic := '0';
signal wrn : std_logic := '0';
signal rdn : std_logic := '0';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
--BiDirs
signal data : std_logic_vector(7 downto 0);
--Outputs
signal intn : std_logic;
-- Clock period definitions
constant clk_period : time := 100 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: serial PORT MAP (
serialdata => serialdata,
clk => clk,
csn => csn,
wrn => wrn,
rdn => rdn,
addr => addr,
data => data,
intn => intn
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wrn <= '0';
csn<='0';
rdn<='1';
addr<="01";
wait for 100 ns;
addr<="10";
wait for 100 ns;
addr<="11";
wait for 100 ns;
addr<="00";
wait for 100 ns;
rdn<='0';
csn<='0';
wrn<='1';
--wait for 100 ns;
--serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
addr<="01";
wait for 100 ns;
wrn <= '0';
csn<='0';
rdn<='1';
addr<="01";
wait for 100 ns;
addr<="10";
wait for 100 ns;
addr<="11";
wait for 100 ns;
addr<="00";
wait for 100 ns;
rdn<='0';
csn<='0';
wrn<='1';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '0';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
serialdata <= '1';
wait for 100 ns;
addr<="01";
wait for 100 ns;
addr<="00";
wait for 100 ns;
serialdata <= '0';
wait for 300 ns;
addr<="01";
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2741.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p03n02i02741ent IS
--ERROR: need 2 quotation characters as input for a string literal
constant c: string:="""; -- failure_here
END c13s06b00x00p03n02i02741ent;
ARCHITECTURE c13s06b00x00p03n02i02741arch OF c13s06b00x00p03n02i02741ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s06b00x00p03n02i02741 - Single quotation mark cannot be a string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p03n02i02741arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2741.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p03n02i02741ent IS
--ERROR: need 2 quotation characters as input for a string literal
constant c: string:="""; -- failure_here
END c13s06b00x00p03n02i02741ent;
ARCHITECTURE c13s06b00x00p03n02i02741arch OF c13s06b00x00p03n02i02741ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s06b00x00p03n02i02741 - Single quotation mark cannot be a string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p03n02i02741arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2741.vhd,v 1.2 2001-10-26 16:30:21 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s06b00x00p03n02i02741ent IS
--ERROR: need 2 quotation characters as input for a string literal
constant c: string:="""; -- failure_here
END c13s06b00x00p03n02i02741ent;
ARCHITECTURE c13s06b00x00p03n02i02741arch OF c13s06b00x00p03n02i02741ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s06b00x00p03n02i02741 - Single quotation mark cannot be a string literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s06b00x00p03n02i02741arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc310.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p06n01i00310ent IS
END c03s01b04x00p06n01i00310ent;
ARCHITECTURE c03s01b04x00p06n01i00310arch OF c03s01b04x00p06n01i00310ent IS
type R1 is range -10.0 to 10.0;
constant C1 : R1 := 2.0 ;
signal S1 : R1;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= C1 * 6.0 after 5 ns;
wait for 10 ns;
assert NOT(S1 = 12.0)
report "***PASSED TEST: c03s01b04x00p06n01i00310"
severity NOTE;
assert ( S1=12.0)
report "***FAILED TEST: c03s01b04x00p06n01i00310 - Value not within bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p06n01i00310arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc310.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p06n01i00310ent IS
END c03s01b04x00p06n01i00310ent;
ARCHITECTURE c03s01b04x00p06n01i00310arch OF c03s01b04x00p06n01i00310ent IS
type R1 is range -10.0 to 10.0;
constant C1 : R1 := 2.0 ;
signal S1 : R1;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= C1 * 6.0 after 5 ns;
wait for 10 ns;
assert NOT(S1 = 12.0)
report "***PASSED TEST: c03s01b04x00p06n01i00310"
severity NOTE;
assert ( S1=12.0)
report "***FAILED TEST: c03s01b04x00p06n01i00310 - Value not within bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p06n01i00310arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc310.vhd,v 1.2 2001-10-26 16:30:25 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b04x00p06n01i00310ent IS
END c03s01b04x00p06n01i00310ent;
ARCHITECTURE c03s01b04x00p06n01i00310arch OF c03s01b04x00p06n01i00310ent IS
type R1 is range -10.0 to 10.0;
constant C1 : R1 := 2.0 ;
signal S1 : R1;
BEGIN
TESTING: PROCESS
BEGIN
S1 <= C1 * 6.0 after 5 ns;
wait for 10 ns;
assert NOT(S1 = 12.0)
report "***PASSED TEST: c03s01b04x00p06n01i00310"
severity NOTE;
assert ( S1=12.0)
report "***FAILED TEST: c03s01b04x00p06n01i00310 - Value not within bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b04x00p06n01i00310arch;
|
---------------------------------------------------------------------------
--
-- Title: Hardware Thread User Logic Exit Thread
-- To be used as a place holder, and size estimate for HWTI
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_misc.all;
library Unisim;
use Unisim.all;
---------------------------------------------------------------------------
-- Port declarations
---------------------------------------------------------------------------
-- Definition of Ports:
--
-- Misc. Signals
-- clock
--
-- HWTI to HWTUL interconnect
-- intrfc2thrd_address 32 bits memory
-- intrfc2thrd_value 32 bits memory function
-- intrfc2thrd_function 16 bits control
-- intrfc2thrd_goWait 1 bits control
--
-- HWTUL to HWTI interconnect
-- thrd2intrfc_address 32 bits memory
-- thrd2intrfc_value 32 bits memory function
-- thrd2intrfc_function 16 bits function
-- thrd2intrfc_opcode 6 bits memory function
--
---------------------------------------------------------------------------
-- Thread Manager Entity section
---------------------------------------------------------------------------
entity user_logic_hwtul is
port (
clock : in std_logic;
intrfc2thrd_address : in std_logic_vector(0 to 31);
intrfc2thrd_value : in std_logic_vector(0 to 31);
intrfc2thrd_function : in std_logic_vector(0 to 15);
intrfc2thrd_goWait : in std_logic;
thrd2intrfc_address : out std_logic_vector(0 to 31);
thrd2intrfc_value : out std_logic_vector(0 to 31);
thrd2intrfc_function : out std_logic_vector(0 to 15);
thrd2intrfc_opcode : out std_logic_vector(0 to 5)
);
end entity user_logic_hwtul;
---------------------------------------------------------------------------
-- Architecture section
---------------------------------------------------------------------------
architecture IMP of user_logic_hwtul is
---------------------------------------------------------------------------
-- Signal declarations
---------------------------------------------------------------------------
type state_machine is (
FUNCTION_RESET,
FUNCTION_USER_SELECT,
FUNCTION_START,
FUNCTION_EXIT,
STATE_1,
STATE_2,
STATE_3,
STATE_4,
STATE_5,
STATE_6,
STATE_7,
STATE_8,
STATE_9,
STATE_10,
STATE_11,
STATE_12,
STATE_13,
STATE_14,
STATE_15,
STATE_16,
STATE_17,
STATE_18,
STATE_19,
STATE_20,
WAIT_STATE,
ERROR_STATE);
-- Function definitions
constant U_FUNCTION_RESET : std_logic_vector(0 to 15) := x"0000";
constant U_FUNCTION_WAIT : std_logic_vector(0 to 15) := x"0001";
constant U_FUNCTION_USER_SELECT : std_logic_vector(0 to 15) := x"0002";
constant U_FUNCTION_START : std_logic_vector(0 to 15) := x"0003";
constant U_STATE_1 : std_logic_vector(0 to 15) := x"0101";
constant U_STATE_2 : std_logic_vector(0 to 15) := x"0102";
constant U_STATE_3 : std_logic_vector(0 to 15) := x"0103";
constant U_STATE_4 : std_logic_vector(0 to 15) := x"0104";
constant U_STATE_5 : std_logic_vector(0 to 15) := x"0105";
constant U_STATE_6 : std_logic_vector(0 to 15) := x"0106";
constant U_STATE_7 : std_logic_vector(0 to 15) := x"0107";
constant U_STATE_8 : std_logic_vector(0 to 15) := x"0108";
constant U_STATE_9 : std_logic_vector(0 to 15) := x"0109";
constant U_STATE_10 : std_logic_vector(0 to 15) := x"0110";
constant U_STATE_11 : std_logic_vector(0 to 15) := x"0111";
constant U_STATE_12 : std_logic_vector(0 to 15) := x"0112";
constant U_STATE_13 : std_logic_vector(0 to 15) := x"0113";
constant U_STATE_14 : std_logic_vector(0 to 15) := x"0114";
constant U_STATE_15 : std_logic_vector(0 to 15) := x"0115";
constant U_STATE_16 : std_logic_vector(0 to 15) := x"0116";
constant U_STATE_17 : std_logic_vector(0 to 15) := x"0117";
constant U_STATE_18 : std_logic_vector(0 to 15) := x"0118";
constant U_STATE_19 : std_logic_vector(0 to 15) := x"0119";
constant U_STATE_20 : std_logic_vector(0 to 15) := x"0120";
-- Range 0003 to 7999 reserved for user logic's state machine
-- Range 8000 to 9999 reserved for system calls
constant FUNCTION_HTHREAD_ATTR_INIT : std_logic_vector(0 to 15) := x"8000";
constant FUNCTION_HTHREAD_ATTR_DESTROY : std_logic_vector(0 to 15) := x"8001";
constant FUNCTION_HTHREAD_CREATE : std_logic_vector(0 to 15) := x"8010";
constant FUNCTION_HTHREAD_JOIN : std_logic_vector(0 to 15) := x"8011";
constant FUNCTION_HTHREAD_SELF : std_logic_vector(0 to 15) := x"8012";
constant FUNCTION_HTHREAD_YIELD : std_logic_vector(0 to 15) := x"8013";
constant FUNCTION_HTHREAD_EQUAL : std_logic_vector(0 to 15) := x"8014";
constant FUNCTION_HTHREAD_EXIT : std_logic_vector(0 to 15) := x"8015";
constant FUNCTION_HTHREAD_EXIT_ERROR : std_logic_vector(0 to 15) := x"8016";
constant FUNCTION_HTHREAD_MUTEXATTR_INIT : std_logic_vector(0 to 15) := x"8020";
constant FUNCTION_HTHREAD_MUTEXATTR_DESTROY : std_logic_vector(0 to 15) := x"8021";
constant FUNCTION_HTHREAD_MUTEXATTR_SETNUM : std_logic_vector(0 to 15) := x"8022";
constant FUNCTION_HTHREAD_MUTEXATTR_GETNUM : std_logic_vector(0 to 15) := x"8023";
constant FUNCTION_HTHREAD_MUTEX_INIT : std_logic_vector(0 to 15) := x"8030";
constant FUNCTION_HTHREAD_MUTEX_DESTROY : std_logic_vector(0 to 15) := x"8031";
constant FUNCTION_HTHREAD_MUTEX_LOCK : std_logic_vector(0 to 15) := x"8032";
constant FUNCTION_HTHREAD_MUTEX_UNLOCK : std_logic_vector(0 to 15) := x"8033";
constant FUNCTION_HTHREAD_MUTEX_TRYLOCK : std_logic_vector(0 to 15) := x"8034";
constant FUNCTION_HTHREAD_CONDATTR_INIT : std_logic_vector(0 to 15) := x"8040";
constant FUNCTION_HTHREAD_CONDATTR_DESTROY : std_logic_vector(0 to 15) := x"8041";
constant FUNCTION_HTHREAD_CONDATTR_SETNUM : std_logic_vector(0 to 15) := x"8042";
constant FUNCTION_HTHREAD_CONDATTR_GETNUM : std_logic_vector(0 to 15) := x"8043";
constant FUNCTION_HTHREAD_COND_INIT : std_logic_vector(0 to 15) := x"8050";
constant FUNCTION_HTHREAD_COND_DESTROY : std_logic_vector(0 to 15) := x"8051";
constant FUNCTION_HTHREAD_COND_SIGNAL : std_logic_vector(0 to 15) := x"8052";
constant FUNCTION_HTHREAD_COND_BROADCAST : std_logic_vector(0 to 15) := x"8053";
constant FUNCTION_HTHREAD_COND_WAIT : std_logic_vector(0 to 15) := x"8054";
-- Ranged A000 to FFFF reserved for supported library calls
constant FUNCTION_MALLOC : std_logic_vector(0 to 15) := x"A000";
constant FUNCTION_CALLOC : std_logic_vector(0 to 15) := x"A001";
constant FUNCTION_FREE : std_logic_vector(0 to 15) := x"A002";
-- user_opcode Constants
constant OPCODE_NOOP : std_logic_vector(0 to 5) := "000000";
-- Memory sub-interface specific opcodes
constant OPCODE_LOAD : std_logic_vector(0 to 5) := "000001";
constant OPCODE_STORE : std_logic_vector(0 to 5) := "000010";
constant OPCODE_DECLARE : std_logic_vector(0 to 5) := "000011";
constant OPCODE_READ : std_logic_vector(0 to 5) := "000100";
constant OPCODE_WRITE : std_logic_vector(0 to 5) := "000101";
constant OPCODE_ADDRESS : std_logic_vector(0 to 5) := "000110";
-- Function sub-interface specific opcodes
constant OPCODE_PUSH : std_logic_vector(0 to 5) := "010000";
constant OPCODE_POP : std_logic_vector(0 to 5) := "010001";
constant OPCODE_CALL : std_logic_vector(0 to 5) := "010010";
constant OPCODE_RETURN : std_logic_vector(0 to 5) := "010011";
constant Z32 : std_logic_vector(0 to 31) := (others => '0');
signal current_state, next_state : state_machine := FUNCTION_RESET;
signal return_state, return_state_next: state_machine := FUNCTION_RESET;
signal toUser_address : std_logic_vector(0 to 31);
signal toUser_value : std_logic_vector(0 to 31);
signal toUser_function : std_logic_vector(0 to 15);
signal toUser_goWait : std_logic;
signal retVal, retVal_next : std_logic_vector(0 to 31);
signal arg, arg_next : std_logic_vector(0 to 31);
signal reg1, reg1_next : std_logic_vector(0 to 31);
signal reg2, reg2_next : std_logic_vector(0 to 31);
signal reg3, reg3_next : std_logic_vector(0 to 31);
signal reg4, reg4_next : std_logic_vector(0 to 31);
signal reg5, reg5_next : std_logic_vector(0 to 31);
signal reg6, reg6_next : std_logic_vector(0 to 31);
signal reg7, reg7_next : std_logic_vector(0 to 31);
signal reg8, reg8_next : std_logic_vector(0 to 31);
---------------------------------------------------------------------------
-- Begin architecture
---------------------------------------------------------------------------
begin -- architecture IMP
HWTUL_STATE_PROCESS : process (clock, intrfc2thrd_goWait) is
begin
if (clock'event and (clock = '1')) then
toUser_address <= intrfc2thrd_address;
toUser_value <= intrfc2thrd_value;
toUser_function <= intrfc2thrd_function;
toUser_goWait <= intrfc2thrd_goWait;
return_state <= return_state_next;
retVal <= retVal_next;
arg <= arg_next;
reg1 <= reg1_next;
reg2 <= reg2_next;
reg3 <= reg3_next;
reg4 <= reg4_next;
reg5 <= reg5_next;
reg6 <= reg6_next;
reg7 <= reg7_next;
reg8 <= reg8_next;
-- Find out if the HWTI is tell us what to do
if (intrfc2thrd_goWait = '1') then
case intrfc2thrd_function is
-- Typically the HWTI will tell us to control our own destiny
when U_FUNCTION_USER_SELECT =>
current_state <= next_state;
-- List all the functions the HWTI could tell us to run
when U_FUNCTION_RESET =>
current_state <= FUNCTION_RESET;
when U_FUNCTION_START =>
current_state <= FUNCTION_START;
when U_STATE_1 =>
current_state <= STATE_1;
when U_STATE_2 =>
current_state <= STATE_2;
when U_STATE_3 =>
current_state <= STATE_3;
when U_STATE_4 =>
current_state <= STATE_4;
when U_STATE_5 =>
current_state <= STATE_5;
when U_STATE_6 =>
current_state <= STATE_6;
when U_STATE_7 =>
current_state <= STATE_7;
when U_STATE_8 =>
current_state <= STATE_8;
when U_STATE_9 =>
current_state <= STATE_9;
when U_STATE_10 =>
current_state <= STATE_10;
when U_STATE_11 =>
current_state <= STATE_11;
when U_STATE_12 =>
current_state <= STATE_12;
when U_STATE_13 =>
current_state <= STATE_13;
when U_STATE_14 =>
current_state <= STATE_14;
when U_STATE_15 =>
current_state <= STATE_15;
when U_STATE_16 =>
current_state <= STATE_16;
when U_STATE_17 =>
current_state <= STATE_17;
when U_STATE_18 =>
current_state <= STATE_18;
when U_STATE_19 =>
current_state <= STATE_19;
when U_STATE_20 =>
current_state <= STATE_20;
-- If the HWTI tells us to do something we don't know, error
when OTHERS =>
current_state <= ERROR_STATE;
end case;
else
current_state <= WAIT_STATE;
end if;
end if;
end process HWTUL_STATE_PROCESS;
HWTUL_STATE_MACHINE : process (clock) is
begin
-- Default register assignments
thrd2intrfc_opcode <= OPCODE_NOOP; -- When issuing an OPCODE, must be a pulse
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_USER_SELECT;
return_state_next <= return_state;
next_state <= current_state;
retVal_next <= retVal;
arg_next <= arg;
reg1_next <= reg1;
reg2_next <= reg2;
reg3_next <= reg3;
reg4_next <= reg4;
reg5_next <= reg5;
reg6_next <= reg6;
reg7_next <= reg7;
reg8_next <= reg8;
-----------------------------------------------------------------------
-- Testcase: exit_1.c
-- reg6 = * function
-- reg7 = thread
-----------------------------------------------------------------------
-- The state machine
case current_state is
when FUNCTION_RESET =>
--Set default values
thrd2intrfc_opcode <= OPCODE_NOOP;
thrd2intrfc_address <= Z32;
thrd2intrfc_value <= Z32;
thrd2intrfc_function <= U_FUNCTION_START;
-- struct test_data * data = (struct test_data *) arg;
when FUNCTION_START =>
-- Pop the argument
thrd2intrfc_value <= Z32;
thrd2intrfc_opcode <= OPCODE_POP;
next_state <= WAIT_STATE;
return_state_next <= STATE_1;
when STATE_1 =>
arg_next <= intrfc2thrd_value;
-- Read the address of function
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= intrfc2thrd_value;
next_state <= WAIT_STATE;
return_state_next <= STATE_2;
when STATE_2 =>
reg6_next <= intrfc2thrd_value;
next_state <= STATE_3;
-- hthread_create( &data->thread, NULL, data->function, NULL );
when STATE_3 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_4;
when STATE_4 =>
-- push data->function
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg6;
next_state <= WAIT_STATE;
return_state_next <= STATE_5;
when STATE_5 =>
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_6;
when STATE_6 =>
-- push &data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_7;
when STATE_7 =>
-- call hthread_create
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_CREATE;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_8;
next_state <= WAIT_STATE;
-- hthread_join( data->thread, NULL );
when STATE_8 =>
-- Load the value of data->thread
thrd2intrfc_opcode <= OPCODE_LOAD;
thrd2intrfc_address <= arg + x"00000004";
next_state <= WAIT_STATE;
return_state_next <= STATE_9;
when STATE_9 =>
reg7_next <= intrfc2thrd_value;
-- push NULL
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= Z32;
next_state <= WAIT_STATE;
return_state_next <= STATE_10;
when STATE_10 =>
-- push data->thread
thrd2intrfc_opcode <= OPCODE_PUSH;
thrd2intrfc_value <= reg7;
next_state <= WAIT_STATE;
return_state_next <= STATE_11;
when STATE_11 =>
-- call hthread_join
thrd2intrfc_opcode <= OPCODE_CALL;
thrd2intrfc_function <= FUNCTION_HTHREAD_JOIN;
thrd2intrfc_value <= Z32(0 to 15) & U_STATE_12;
next_state <= WAIT_STATE;
-- retVal = SUCCESS
when STATE_12 =>
retVal_next <= Z32;
next_state <= FUNCTION_EXIT;
when FUNCTION_EXIT =>
--Same as hthread_exit( (void *) retVal );
thrd2intrfc_value <= retVal;
thrd2intrfc_opcode <= OPCODE_RETURN;
next_state <= WAIT_STATE;
when WAIT_STATE =>
next_state <= return_state;
when ERROR_STATE =>
next_state <= ERROR_STATE;
when others =>
next_state <= ERROR_STATE;
end case;
end process HWTUL_STATE_MACHINE;
end architecture IMP;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_mem package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! Provide common generic log() function
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief Declaration of 'virtual' Memory components.
package types_mem is
--! @brief Declaration of the "virtual" BootROM component.
--! @details BootRom start address must implements address matching to the
--! CPU reset vector (0x200) and all processing after power-on is
--! using this memory block. BootRom size depends of the configuration
--! and size of the generated hex file.
--! Component implements one-clock access to the
--! ROM without wait-staits. Datawidth depends of the AXI4 bus
--! configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] hex_filename Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component BootRom_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
--! @brief Declaration of the "virtual" RomImage component.
--! @details This module stores pre-built firmware image that is coping
--! into internal SRAM during Boot stage without any modificaiton.
--! RomImage size is limited by global configuration parameter and
--! it cannot be more than internal SRAM size. Component implements
--! one-clock access to the ROM without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] sim_hexfile Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component RomImage_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
--! @brief Galileo PRN codes ROM storage:
--! @details This ROM is used in FSE Engine to form reference E1 reference
--! signals. HEX-file isn't used for this ROM because 'inferred'
--! module was built using "case when" operators.
component RomPrn_tech is
generic (
generic_tech : integer := 0
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Declaration of the "virtual" SRAM component with unaligned access.
--! @details This module implements internal SRAM and support unaligned access
--! without wait-states. For example it allows to read 4 bytes from
--! address 0x3 for one clock.
--! Component implements one-clock access without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] memtech Generic technology selector.
--! @param[in] abits Generic argument defining SRAM size as 2**abits.
--! @param[in] clk System bus clock.
--! @param[in] raddr Read address.
--! @param[out] rdata Output data value.
--! @param[in] waddr Write address.
--! @param[in] we Write enable.
--! @param[in] wstrb Byte selector to form write only for the specified bytes.
--! @param[in] wdata Write data.
component srambytes_tech is
generic (
memtech : integer := 0;
abits : integer := 16;
init_file : string := ""
);
port (
clk : in std_logic;
raddr : in global_addr_array_type;
rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
waddr : in global_addr_array_type;
we : in std_logic;
wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 32-bits data width.
--! @details This module doesn't support byte access and always implements
--! 4-bytes alignment.
component Ram32_tech
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 64-bits data width.
--! @details This module doesn't support byte access and always implements
--! 8-bytes alignment.
component Ram64_tech
generic (
generic_tech : integer := 0;
generic_abits : integer := 4
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(63 downto 0);
o_data : out std_logic_vector(63 downto 0)
);
end component;
--! @brief dual-port RAM declaration.
component syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end component;
end;
|
----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov
--! @brief Declaration types_mem package components.
------------------------------------------------------------------------------
--! Standard library
library ieee;
use ieee.std_logic_1164.all;
--! Provide common generic log() function
library commonlib;
use commonlib.types_common.all;
--! AMBA system bus specific library.
library ambalib;
--! AXI4 configuration constants.
use ambalib.types_amba4.all;
--! @brief Declaration of 'virtual' Memory components.
package types_mem is
--! @brief Declaration of the "virtual" BootROM component.
--! @details BootRom start address must implements address matching to the
--! CPU reset vector (0x200) and all processing after power-on is
--! using this memory block. BootRom size depends of the configuration
--! and size of the generated hex file.
--! Component implements one-clock access to the
--! ROM without wait-staits. Datawidth depends of the AXI4 bus
--! configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] hex_filename Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component BootRom_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
--! @brief Declaration of the "virtual" RomImage component.
--! @details This module stores pre-built firmware image that is coping
--! into internal SRAM during Boot stage without any modificaiton.
--! RomImage size is limited by global configuration parameter and
--! it cannot be more than internal SRAM size. Component implements
--! one-clock access to the ROM without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] tech Generic technology selector.
--! @param[in] sim_hexfile Generic argument defining hex-file location.
--! @param[in] clk System bus clock.
--! @param[in] address Input address.
--! @param[out] data Output data value.
component RomImage_tech is
generic (
memtech : integer := 0;
sim_hexfile : string
);
port (
clk : in std_logic;
address : in global_addr_array_type;
data : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
------------------------------------------------------------------------------
--! @brief Galileo PRN codes ROM storage:
--! @details This ROM is used in FSE Engine to form reference E1 reference
--! signals. HEX-file isn't used for this ROM because 'inferred'
--! module was built using "case when" operators.
component RomPrn_tech is
generic (
generic_tech : integer := 0
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(12 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Declaration of the "virtual" SRAM component with unaligned access.
--! @details This module implements internal SRAM and support unaligned access
--! without wait-states. For example it allows to read 4 bytes from
--! address 0x3 for one clock.
--! Component implements one-clock access without wait-staits.
--! Datawidth depends of the AXI4 bus configuration.
--! @param[in] memtech Generic technology selector.
--! @param[in] abits Generic argument defining SRAM size as 2**abits.
--! @param[in] clk System bus clock.
--! @param[in] raddr Read address.
--! @param[out] rdata Output data value.
--! @param[in] waddr Write address.
--! @param[in] we Write enable.
--! @param[in] wstrb Byte selector to form write only for the specified bytes.
--! @param[in] wdata Write data.
component srambytes_tech is
generic (
memtech : integer := 0;
abits : integer := 16;
init_file : string := ""
);
port (
clk : in std_logic;
raddr : in global_addr_array_type;
rdata : out std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0);
waddr : in global_addr_array_type;
we : in std_logic;
wstrb : in std_logic_vector(CFG_NASTI_DATA_BYTES-1 downto 0);
wdata : in std_logic_vector(CFG_NASTI_DATA_BITS-1 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 32-bits data width.
--! @details This module doesn't support byte access and always implements
--! 4-bytes alignment.
component Ram32_tech
generic (
generic_tech : integer := 0;
generic_kWords : integer := 1
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(10+log2(generic_kWords)-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(31 downto 0);
o_data : out std_logic_vector(31 downto 0)
);
end component;
--! @brief Virtual SRAM block with fixed 64-bits data width.
--! @details This module doesn't support byte access and always implements
--! 8-bytes alignment.
component Ram64_tech
generic (
generic_tech : integer := 0;
generic_abits : integer := 4
);
port (
i_clk : in std_logic;
i_address : in std_logic_vector(generic_abits-1 downto 0);
i_wr_ena : in std_logic;
i_data : in std_logic_vector(63 downto 0);
o_data : out std_logic_vector(63 downto 0)
);
end component;
--! @brief dual-port RAM declaration.
component syncram_2p_tech is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8;
sepclk : integer := 0;
wrfst : integer := 0;
testen : integer := 0;
words : integer := 0;
custombits : integer := 1
);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0)
);
end component;
end;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 16; -- system clock period
comboard : integer := 1 -- Comms. adapter board attached
);
port (
pci_rst : out std_logic;
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
component leon3mp
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
mezz : integer := CFG_ADS_DAU_MEZZ
);
port (
clk_66mhz : in std_logic;
clk_socket : in std_logic;
leds : out std_logic_vector(7 downto 0);
switches : in std_logic_vector(5 downto 0);
sram_a : out std_logic_vector(24 downto 0);
sram_ben_l : out std_logic_vector(0 to 3);
sram_cs_l : out std_logic_vector(1 downto 0);
sram_oe_l : out std_logic;
sram_we_l : out std_logic;
sram_dq : inout std_logic_vector(31 downto 0);
flash_cs_l : out std_logic;
flash_rst_l : out std_logic;
iosn : out std_logic;
sdclk : out std_logic;
rasn : out std_logic;
casn : out std_logic;
sdcke : out std_logic;
sdcsn : out std_logic;
tx : out std_logic;
rx : in std_logic;
can_txd : out std_logic;
can_rxd : in std_logic;
phy_txck : in std_logic;
phy_rxck : in std_logic;
phy_rxd : in std_logic_vector(3 downto 0);
phy_rxdv : in std_logic;
phy_rxer : in std_logic;
phy_col : in std_logic;
phy_crs : in std_logic;
phy_txd : out std_logic_vector(3 downto 0);
phy_txen : out std_logic;
phy_txer : out std_logic;
phy_mdc : out std_logic;
phy_mdio : inout std_logic; -- ethernet PHY interface
phy_reset_l : inout std_logic;
video_clk : in std_logic;
comp_sync : out std_logic;
blank : out std_logic;
video_out : out std_logic_vector(23 downto 0);
msclk : inout std_logic;
msdata : inout std_logic;
kbclk : inout std_logic;
kbdata : inout std_logic;
disp_seg1 : out std_logic_vector(7 downto 0);
disp_seg2 : out std_logic_vector(7 downto 0);
pci_clk : in std_logic;
pci_gnt : in std_logic;
pci_idsel : in std_logic;
pci_lock : inout std_logic;
pci_ad : inout std_logic_vector(31 downto 0);
pci_cbe : inout std_logic_vector(3 downto 0);
pci_frame : inout std_logic;
pci_irdy : inout std_logic;
pci_trdy : inout std_logic;
pci_devsel : inout std_logic;
pci_stop : inout std_logic;
pci_perr : inout std_logic;
pci_par : inout std_logic;
pci_req : inout std_logic;
pci_serr : inout std_logic;
pci_host : in std_logic;
pci_66 : in std_logic
);
end component;
signal clk : std_logic := '0';
constant ct : integer := clkperiod/2;
signal gnd : std_logic := '0';
signal vcc : std_logic := '1';
signal sdcke : std_logic;
signal sdcsn : std_logic;
signal sdwen : std_logic; -- write en
signal sdrasn : std_logic; -- row addr stb
signal sdcasn : std_logic; -- col addr stb
signal sddqm : std_logic_vector ( 7 downto 0); -- data i/o mask
signal sdclk : std_logic;
signal plllock : std_logic;
signal tx, rx : std_logic;
signal dsutx, dsurx : std_logic;
signal leds : std_logic_vector(7 downto 0);
signal switches : std_logic_vector(5 downto 0);
constant lresp : boolean := false;
signal sram_oe_l, sram_we_l : std_logic;
signal sram_cs_l : std_logic_vector(1 downto 0);
signal sram_ben_l : std_logic_vector(0 to 3);
signal sram_dq : std_logic_vector(31 downto 0);
signal flash_cs_l, flash_rst_l : std_logic;
signal iosn : std_logic;
signal phy_txck : std_logic;
signal phy_rxck : std_logic;
signal phy_rxd : std_logic_vector(3 downto 0);
signal phy_rxdt : std_logic_vector(7 downto 0);
signal phy_rxdv : std_logic;
signal phy_rxer : std_logic;
signal phy_col : std_logic;
signal phy_crs : std_logic;
signal phy_txd : std_logic_vector(3 downto 0);
signal phy_txdt : std_logic_vector(7 downto 0);
signal phy_txen : std_logic;
signal phy_txer : std_logic;
signal phy_mdc : std_logic;
signal phy_mdio : std_logic;
signal phy_reset_l : std_logic;
signal phy_gtx_clk : std_logic := '0';
signal video_clk : std_logic := '0';
signal comp_sync : std_logic;
signal blank : std_logic;
signal video_out : std_logic_vector(23 downto 0);
signal msclk : std_logic;
signal msdata : std_logic;
signal kbclk : std_logic;
signal kbdata : std_logic;
signal dsurst : std_logic;
signal disp_seg1 : std_logic_vector(7 downto 0);
signal disp_seg2 : std_logic_vector(7 downto 0);
signal baddr : std_logic_vector(27 downto 0) := (others => '0');
signal can_txd : std_logic;
signal can_rxd : std_logic;
begin
-- clock and reset
clk <= not clk after ct * 1 ns;
switches(0) <= '1'; -- DSUEN
switches(4) <= not dsurst; -- reset
switches(5) <= '0'; -- DSUBRE
dsutx <= tx; rx <= dsurx;
pci_rst <= phy_reset_l;
phy_reset_l <= 'H';
video_clk <= not video_clk after 20 ns;
can_rxd <= can_txd;
sddqm(3) <= sram_ben_l(0); sddqm(2) <= sram_ben_l(1);
sddqm(1) <= sram_ben_l(2); sddqm(0) <= sram_ben_l(3);
cpu : leon3mp
generic map (fabtech, memtech, padtech, clktech,
disas, dbguart, pclow )
port map (clk, sdclk, leds, switches, baddr(24 downto 0),
sram_ben_l, sram_cs_l, sram_oe_l, sram_we_l, sram_dq,
flash_cs_l, flash_rst_l, iosn, sdclk, sdrasn, sdcasn, sdcke, sdcsn,
tx, rx, can_txd, can_rxd, phy_txck, phy_rxck, phy_rxd, phy_rxdv,
phy_rxer, phy_col, phy_crs, phy_txd, phy_txen, phy_txer, phy_mdc,
phy_mdio, phy_reset_l,
video_clk, comp_sync, blank, video_out,
msclk, msdata, kbclk, kbdata, disp_seg1, disp_seg2,
pci_clk, pci_gnt, pci_idsel, pci_lock, pci_ad, pci_cbe,
pci_frame, pci_irdy, pci_trdy, pci_devsel, pci_stop, pci_perr, pci_par,
pci_req, pci_serr, pci_host, pci_66);
-- One 32-bit SRAM bank on main board
sram0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile)
port map (baddr(17 downto 0), sram_dq(31-i*16 downto 16-i*16),
sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(0), sram_we_l, sram_oe_l);
end generate;
phy_mdio <= 'H';
phy_rxd <= phy_rxdt(3 downto 0);
phy_txdt <= "0000" & phy_txd;
p0: phy
generic map(base1000_t_fd => 0, base1000_t_hd => 0)
port map(dsurst, phy_mdio, phy_txck, phy_rxck, phy_rxdt, phy_rxdv,
phy_rxer, phy_col, phy_crs, phy_txdt, phy_txen, phy_txer, phy_mdc, phy_gtx_clk);
-- optional communications adapter
comms : if (comboard = 1) generate
-- 32-bit flash prom
flash0 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => promfile)
port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16),
flash_cs_l, flash_cs_l, flash_cs_l, sram_we_l, sram_oe_l);
end generate;
-- second SRAM bank
sram1 : for i in 0 to 1 generate
sr0 : sram16 generic map (index => i*2, abits => 18, fname => sramfile)
port map (baddr(19 downto 2), sram_dq(31-i*16 downto 16-i*16),
sram_ben_l(i*2), sram_ben_l(i*2+1), sram_cs_l(1), sram_we_l, sram_oe_l);
end generate;
sdwen <= sram_we_l;
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => sram_dq(31 downto 16), Addr => baddr(14 downto 2),
Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => sram_dq(15 downto 0), Addr => baddr(14 downto 2),
Ba => baddr(16 downto 15), Clk => sdclk, Cke => sdcke,
Cs_n => sdcsn, Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
test0 : grtestmod
port map ( dsurst, clk, leds(0), baddr(21 downto 2), sram_dq,
iosn, sram_oe_l, sram_we_l, open);
leds(0) <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 2000 ns;
if to_x01(leds(0)) = '0' then wait on leds; end if;
assert (to_x01(leds(0)) = '0')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
sram_dq <= buskeep(sram_dq), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_logic; signal dsutx : out std_logic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
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